Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
1 16:52:41.745502 lava-dispatcher, installed at version: 2023.03
2 16:52:41.745776 start: 0 validate
3 16:52:41.745934 Start time: 2023-06-03 16:52:41.745914+00:00 (UTC)
4 16:52:41.746066 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:52:41.746232 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 16:52:42.033099 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:52:42.033288 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:52:42.319470 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:52:42.320151 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:52:42.614710 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:52:42.615488 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:52:42.908909 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:52:42.909660 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:52:43.199590 validate duration: 1.45
16 16:52:43.199855 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:52:43.199956 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:52:43.200057 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:52:43.200187 Not decompressing ramdisk as can be used compressed.
20 16:52:43.200283 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 16:52:43.200350 saving as /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/ramdisk/initrd.cpio.gz
22 16:52:43.200415 total size: 4665601 (4MB)
23 16:52:43.201717 progress 0% (0MB)
24 16:52:43.203155 progress 5% (0MB)
25 16:52:43.204406 progress 10% (0MB)
26 16:52:43.205732 progress 15% (0MB)
27 16:52:43.207009 progress 20% (0MB)
28 16:52:43.208261 progress 25% (1MB)
29 16:52:43.209481 progress 30% (1MB)
30 16:52:43.210728 progress 35% (1MB)
31 16:52:43.211957 progress 40% (1MB)
32 16:52:43.213360 progress 45% (2MB)
33 16:52:43.214657 progress 50% (2MB)
34 16:52:43.215859 progress 55% (2MB)
35 16:52:43.217103 progress 60% (2MB)
36 16:52:43.218354 progress 65% (2MB)
37 16:52:43.219559 progress 70% (3MB)
38 16:52:43.220783 progress 75% (3MB)
39 16:52:43.222033 progress 80% (3MB)
40 16:52:43.223429 progress 85% (3MB)
41 16:52:43.224642 progress 90% (4MB)
42 16:52:43.225898 progress 95% (4MB)
43 16:52:43.227159 progress 100% (4MB)
44 16:52:43.227318 4MB downloaded in 0.03s (165.41MB/s)
45 16:52:43.227471 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:52:43.227732 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:52:43.227823 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:52:43.227910 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:52:43.228040 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:52:43.228114 saving as /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/kernel/Image
52 16:52:43.228176 total size: 45746688 (43MB)
53 16:52:43.228238 No compression specified
54 16:52:43.229347 progress 0% (0MB)
55 16:52:43.241180 progress 5% (2MB)
56 16:52:43.253148 progress 10% (4MB)
57 16:52:43.265113 progress 15% (6MB)
58 16:52:43.277301 progress 20% (8MB)
59 16:52:43.289166 progress 25% (10MB)
60 16:52:43.301113 progress 30% (13MB)
61 16:52:43.313633 progress 35% (15MB)
62 16:52:43.325666 progress 40% (17MB)
63 16:52:43.337528 progress 45% (19MB)
64 16:52:43.349781 progress 50% (21MB)
65 16:52:43.362067 progress 55% (24MB)
66 16:52:43.374751 progress 60% (26MB)
67 16:52:43.387327 progress 65% (28MB)
68 16:52:43.399406 progress 70% (30MB)
69 16:52:43.411641 progress 75% (32MB)
70 16:52:43.423641 progress 80% (34MB)
71 16:52:43.435707 progress 85% (37MB)
72 16:52:43.448010 progress 90% (39MB)
73 16:52:43.460014 progress 95% (41MB)
74 16:52:43.472481 progress 100% (43MB)
75 16:52:43.472675 43MB downloaded in 0.24s (178.44MB/s)
76 16:52:43.472878 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:52:43.473264 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:52:43.473388 start: 1.3 download-retry (timeout 00:10:00) [common]
80 16:52:43.473518 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 16:52:43.473692 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:52:43.473766 saving as /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/dtb/mt8192-asurada-spherion-r0.dtb
83 16:52:43.473830 total size: 46924 (0MB)
84 16:52:43.473892 No compression specified
85 16:52:43.475092 progress 69% (0MB)
86 16:52:43.475378 progress 100% (0MB)
87 16:52:43.475533 0MB downloaded in 0.00s (26.32MB/s)
88 16:52:43.475657 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:52:43.475890 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:52:43.475979 start: 1.4 download-retry (timeout 00:10:00) [common]
92 16:52:43.476065 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 16:52:43.476176 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 16:52:43.476247 saving as /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/nfsrootfs/full.rootfs.tar
95 16:52:43.476310 total size: 200770336 (191MB)
96 16:52:43.476372 Using unxz to decompress xz
97 16:52:43.480449 progress 0% (0MB)
98 16:52:44.020880 progress 5% (9MB)
99 16:52:44.540056 progress 10% (19MB)
100 16:52:45.165716 progress 15% (28MB)
101 16:52:45.559112 progress 20% (38MB)
102 16:52:45.909553 progress 25% (47MB)
103 16:52:46.539434 progress 30% (57MB)
104 16:52:47.099709 progress 35% (67MB)
105 16:52:47.691986 progress 40% (76MB)
106 16:52:48.252379 progress 45% (86MB)
107 16:52:48.842603 progress 50% (95MB)
108 16:52:49.488537 progress 55% (105MB)
109 16:52:50.169644 progress 60% (114MB)
110 16:52:50.291365 progress 65% (124MB)
111 16:52:50.432702 progress 70% (134MB)
112 16:52:50.528500 progress 75% (143MB)
113 16:52:50.601799 progress 80% (153MB)
114 16:52:50.669898 progress 85% (162MB)
115 16:52:50.766830 progress 90% (172MB)
116 16:52:51.037059 progress 95% (181MB)
117 16:52:51.604288 progress 100% (191MB)
118 16:52:51.608907 191MB downloaded in 8.13s (23.54MB/s)
119 16:52:51.609202 end: 1.4.1 http-download (duration 00:00:08) [common]
121 16:52:51.609480 end: 1.4 download-retry (duration 00:00:08) [common]
122 16:52:51.609614 start: 1.5 download-retry (timeout 00:09:52) [common]
123 16:52:51.609705 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 16:52:51.609852 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:52:51.609927 saving as /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/modules/modules.tar
126 16:52:51.609990 total size: 8545664 (8MB)
127 16:52:51.610055 Using unxz to decompress xz
128 16:52:51.613752 progress 0% (0MB)
129 16:52:51.635286 progress 5% (0MB)
130 16:52:51.659830 progress 10% (0MB)
131 16:52:51.685443 progress 15% (1MB)
132 16:52:51.709588 progress 20% (1MB)
133 16:52:51.736749 progress 25% (2MB)
134 16:52:51.762581 progress 30% (2MB)
135 16:52:51.788404 progress 35% (2MB)
136 16:52:51.813929 progress 40% (3MB)
137 16:52:51.839756 progress 45% (3MB)
138 16:52:51.864401 progress 50% (4MB)
139 16:52:51.888078 progress 55% (4MB)
140 16:52:51.913600 progress 60% (4MB)
141 16:52:51.939326 progress 65% (5MB)
142 16:52:51.965338 progress 70% (5MB)
143 16:52:51.992671 progress 75% (6MB)
144 16:52:52.022537 progress 80% (6MB)
145 16:52:52.045863 progress 85% (6MB)
146 16:52:52.071669 progress 90% (7MB)
147 16:52:52.095829 progress 95% (7MB)
148 16:52:52.120099 progress 100% (8MB)
149 16:52:52.126027 8MB downloaded in 0.52s (15.79MB/s)
150 16:52:52.126296 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:52:52.126569 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:52:52.126662 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 16:52:52.126755 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 16:52:55.319597 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10576315/extract-nfsrootfs-ku2096k5
156 16:52:55.319812 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 16:52:55.319916 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 16:52:55.320097 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544
159 16:52:55.320225 makedir: /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin
160 16:52:55.320326 makedir: /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/tests
161 16:52:55.320424 makedir: /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/results
162 16:52:55.320529 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-add-keys
163 16:52:55.320674 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-add-sources
164 16:52:55.320832 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-background-process-start
165 16:52:55.320959 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-background-process-stop
166 16:52:55.321085 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-common-functions
167 16:52:55.321211 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-echo-ipv4
168 16:52:55.321336 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-install-packages
169 16:52:55.321461 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-installed-packages
170 16:52:55.321593 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-os-build
171 16:52:55.321718 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-probe-channel
172 16:52:55.321842 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-probe-ip
173 16:52:55.321964 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-target-ip
174 16:52:55.322087 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-target-mac
175 16:52:55.322209 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-target-storage
176 16:52:55.322335 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-test-case
177 16:52:55.322459 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-test-event
178 16:52:55.322582 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-test-feedback
179 16:52:55.322705 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-test-raise
180 16:52:55.322827 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-test-reference
181 16:52:55.322949 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-test-runner
182 16:52:55.323073 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-test-set
183 16:52:55.323197 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-test-shell
184 16:52:55.323329 Updating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-add-keys (debian)
185 16:52:55.323487 Updating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-add-sources (debian)
186 16:52:55.323632 Updating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-install-packages (debian)
187 16:52:55.323773 Updating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-installed-packages (debian)
188 16:52:55.323913 Updating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/bin/lava-os-build (debian)
189 16:52:55.324037 Creating /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/environment
190 16:52:55.324137 LAVA metadata
191 16:52:55.324210 - LAVA_JOB_ID=10576315
192 16:52:55.324276 - LAVA_DISPATCHER_IP=192.168.201.1
193 16:52:55.324378 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 16:52:55.324447 skipped lava-vland-overlay
195 16:52:55.324526 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 16:52:55.324610 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 16:52:55.324675 skipped lava-multinode-overlay
198 16:52:55.324751 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 16:52:55.324832 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 16:52:55.324908 Loading test definitions
201 16:52:55.325003 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 16:52:55.325076 Using /lava-10576315 at stage 0
203 16:52:55.325367 uuid=10576315_1.6.2.3.1 testdef=None
204 16:52:55.325506 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 16:52:55.326121 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 16:52:55.326573 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 16:52:55.326799 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 16:52:55.327351 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 16:52:55.327654 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 16:52:55.328188 runner path: /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/0/tests/0_timesync-off test_uuid 10576315_1.6.2.3.1
213 16:52:55.328342 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 16:52:55.328574 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 16:52:55.328650 Using /lava-10576315 at stage 0
217 16:52:55.328750 Fetching tests from https://github.com/kernelci/test-definitions.git
218 16:52:55.328829 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/0/tests/1_kselftest-rtc'
219 16:52:59.852606 Running '/usr/bin/git checkout kernelci.org
220 16:52:59.996729 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 16:52:59.997449 uuid=10576315_1.6.2.3.5 testdef=None
222 16:52:59.997666 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 16:52:59.997934 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 16:52:59.998723 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 16:52:59.998964 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 16:52:59.999947 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 16:53:00.000190 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 16:53:00.001133 runner path: /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/0/tests/1_kselftest-rtc test_uuid 10576315_1.6.2.3.5
232 16:53:00.001228 BOARD='mt8192-asurada-spherion-r0'
233 16:53:00.001295 BRANCH='cip-gitlab'
234 16:53:00.001357 SKIPFILE='/dev/null'
235 16:53:00.001418 SKIP_INSTALL='True'
236 16:53:00.001477 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 16:53:00.001565 TST_CASENAME=''
238 16:53:00.001638 TST_CMDFILES='rtc'
239 16:53:00.001783 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 16:53:00.001996 Creating lava-test-runner.conf files
242 16:53:00.002063 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576315/lava-overlay-41nb4544/lava-10576315/0 for stage 0
243 16:53:00.002158 - 0_timesync-off
244 16:53:00.002232 - 1_kselftest-rtc
245 16:53:00.002332 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 16:53:00.002425 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 16:53:07.475477 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 16:53:07.475649 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 16:53:07.475745 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 16:53:07.475849 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 16:53:07.475946 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 16:53:07.592455 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 16:53:07.592821 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 16:53:07.592942 extracting modules file /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576315/extract-nfsrootfs-ku2096k5
255 16:53:07.797155 extracting modules file /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576315/extract-overlay-ramdisk-kkah464j/ramdisk
256 16:53:08.006926 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 16:53:08.007105 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 16:53:08.007205 [common] Applying overlay to NFS
259 16:53:08.007275 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576315/compress-overlay-mxq1k979/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576315/extract-nfsrootfs-ku2096k5
260 16:53:08.906249 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 16:53:08.906428 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 16:53:08.906527 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 16:53:08.906627 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 16:53:08.906712 Building ramdisk /var/lib/lava/dispatcher/tmp/10576315/extract-overlay-ramdisk-kkah464j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576315/extract-overlay-ramdisk-kkah464j/ramdisk
265 16:53:09.178979 >> 117799 blocks
266 16:53:11.111065 rename /var/lib/lava/dispatcher/tmp/10576315/extract-overlay-ramdisk-kkah464j/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/ramdisk/ramdisk.cpio.gz
267 16:53:11.111505 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 16:53:11.111630 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 16:53:11.111731 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 16:53:11.111836 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/kernel/Image'
271 16:53:22.746594 Returned 0 in 11 seconds
272 16:53:22.847163 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/kernel/image.itb
273 16:53:23.167712 output: FIT description: Kernel Image image with one or more FDT blobs
274 16:53:23.168064 output: Created: Sat Jun 3 17:53:23 2023
275 16:53:23.168143 output: Image 0 (kernel-1)
276 16:53:23.168214 output: Description:
277 16:53:23.168281 output: Created: Sat Jun 3 17:53:23 2023
278 16:53:23.168344 output: Type: Kernel Image
279 16:53:23.168410 output: Compression: lzma compressed
280 16:53:23.168474 output: Data Size: 10083474 Bytes = 9847.14 KiB = 9.62 MiB
281 16:53:23.168538 output: Architecture: AArch64
282 16:53:23.168600 output: OS: Linux
283 16:53:23.168662 output: Load Address: 0x00000000
284 16:53:23.168721 output: Entry Point: 0x00000000
285 16:53:23.168778 output: Hash algo: crc32
286 16:53:23.168834 output: Hash value: b48eba69
287 16:53:23.168891 output: Image 1 (fdt-1)
288 16:53:23.168946 output: Description: mt8192-asurada-spherion-r0
289 16:53:23.169002 output: Created: Sat Jun 3 17:53:23 2023
290 16:53:23.169058 output: Type: Flat Device Tree
291 16:53:23.169113 output: Compression: uncompressed
292 16:53:23.169169 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 16:53:23.169225 output: Architecture: AArch64
294 16:53:23.169280 output: Hash algo: crc32
295 16:53:23.169335 output: Hash value: 1df858fa
296 16:53:23.169390 output: Image 2 (ramdisk-1)
297 16:53:23.169445 output: Description: unavailable
298 16:53:23.169500 output: Created: Sat Jun 3 17:53:23 2023
299 16:53:23.169599 output: Type: RAMDisk Image
300 16:53:23.169656 output: Compression: Unknown Compression
301 16:53:23.169711 output: Data Size: 17636840 Bytes = 17223.48 KiB = 16.82 MiB
302 16:53:23.169767 output: Architecture: AArch64
303 16:53:23.169823 output: OS: Linux
304 16:53:23.169878 output: Load Address: unavailable
305 16:53:23.169933 output: Entry Point: unavailable
306 16:53:23.169988 output: Hash algo: crc32
307 16:53:23.170044 output: Hash value: 5e9f2eb0
308 16:53:23.170099 output: Default Configuration: 'conf-1'
309 16:53:23.170155 output: Configuration 0 (conf-1)
310 16:53:23.170210 output: Description: mt8192-asurada-spherion-r0
311 16:53:23.170265 output: Kernel: kernel-1
312 16:53:23.170320 output: Init Ramdisk: ramdisk-1
313 16:53:23.170375 output: FDT: fdt-1
314 16:53:23.170430 output: Loadables: kernel-1
315 16:53:23.170485 output:
316 16:53:23.170728 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 16:53:23.170836 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 16:53:23.170974 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 16:53:23.171076 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 16:53:23.171166 No LXC device requested
321 16:53:23.171252 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 16:53:23.171344 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 16:53:23.171424 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 16:53:23.171492 Checking files for TFTP limit of 4294967296 bytes.
325 16:53:23.171998 end: 1 tftp-deploy (duration 00:00:40) [common]
326 16:53:23.172113 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 16:53:23.172209 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 16:53:23.172338 substitutions:
329 16:53:23.172412 - {DTB}: 10576315/tftp-deploy-hgos60m6/dtb/mt8192-asurada-spherion-r0.dtb
330 16:53:23.172483 - {INITRD}: 10576315/tftp-deploy-hgos60m6/ramdisk/ramdisk.cpio.gz
331 16:53:23.172545 - {KERNEL}: 10576315/tftp-deploy-hgos60m6/kernel/Image
332 16:53:23.172606 - {LAVA_MAC}: None
333 16:53:23.172666 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10576315/extract-nfsrootfs-ku2096k5
334 16:53:23.172726 - {NFS_SERVER_IP}: 192.168.201.1
335 16:53:23.172784 - {PRESEED_CONFIG}: None
336 16:53:23.172843 - {PRESEED_LOCAL}: None
337 16:53:23.172903 - {RAMDISK}: 10576315/tftp-deploy-hgos60m6/ramdisk/ramdisk.cpio.gz
338 16:53:23.172962 - {ROOT_PART}: None
339 16:53:23.173019 - {ROOT}: None
340 16:53:23.173077 - {SERVER_IP}: 192.168.201.1
341 16:53:23.173134 - {TEE}: None
342 16:53:23.173192 Parsed boot commands:
343 16:53:23.173248 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 16:53:23.173424 Parsed boot commands: tftpboot 192.168.201.1 10576315/tftp-deploy-hgos60m6/kernel/image.itb 10576315/tftp-deploy-hgos60m6/kernel/cmdline
345 16:53:23.173547 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 16:53:23.173682 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 16:53:23.173814 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 16:53:23.173907 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 16:53:23.173981 Not connected, no need to disconnect.
350 16:53:23.174094 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 16:53:23.174182 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 16:53:23.174252 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
353 16:53:23.177867 Setting prompt string to ['lava-test: # ']
354 16:53:23.178236 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 16:53:23.178357 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 16:53:23.178462 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 16:53:23.178557 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 16:53:23.178753 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 16:53:28.315995 >> Command sent successfully.
360 16:53:28.318687 Returned 0 in 5 seconds
361 16:53:28.419074 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 16:53:28.419555 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 16:53:28.419694 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 16:53:28.419819 Setting prompt string to 'Starting depthcharge on Spherion...'
366 16:53:28.419889 Changing prompt to 'Starting depthcharge on Spherion...'
367 16:53:28.419991 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 16:53:28.420267 [Enter `^Ec?' for help]
369 16:53:28.592635
370 16:53:28.592842
371 16:53:28.592951 F0: 102B 0000
372 16:53:28.593047
373 16:53:28.593141 F3: 1001 0000 [0200]
374 16:53:28.595754
375 16:53:28.595856 F3: 1001 0000
376 16:53:28.595927
377 16:53:28.595992 F7: 102D 0000
378 16:53:28.596055
379 16:53:28.599258 F1: 0000 0000
380 16:53:28.599368
381 16:53:28.599439 V0: 0000 0000 [0001]
382 16:53:28.599509
383 16:53:28.602703 00: 0007 8000
384 16:53:28.602817
385 16:53:28.602899 01: 0000 0000
386 16:53:28.602989
387 16:53:28.605645 BP: 0C00 0209 [0000]
388 16:53:28.605741
389 16:53:28.605811 G0: 1182 0000
390 16:53:28.605877
391 16:53:28.609061 EC: 0000 0021 [4000]
392 16:53:28.609212
393 16:53:28.609318 S7: 0000 0000 [0000]
394 16:53:28.609423
395 16:53:28.613049 CC: 0000 0000 [0001]
396 16:53:28.613215
397 16:53:28.613322 T0: 0000 0040 [010F]
398 16:53:28.613420
399 16:53:28.613545 Jump to BL
400 16:53:28.613645
401 16:53:28.639945
402 16:53:28.640108
403 16:53:28.640212
404 16:53:28.647213 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 16:53:28.650886 ARM64: Exception handlers installed.
406 16:53:28.654895 ARM64: Testing exception
407 16:53:28.654997 ARM64: Done test exception
408 16:53:28.665105 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 16:53:28.674934 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 16:53:28.681686 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 16:53:28.691409 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 16:53:28.698326 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 16:53:28.705164 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 16:53:28.716417 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 16:53:28.723322 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 16:53:28.742706 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 16:53:28.745898 WDT: Last reset was cold boot
418 16:53:28.748966 SPI1(PAD0) initialized at 2873684 Hz
419 16:53:28.752478 SPI5(PAD0) initialized at 992727 Hz
420 16:53:28.755711 VBOOT: Loading verstage.
421 16:53:28.762360 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 16:53:28.765533 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 16:53:28.768792 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 16:53:28.772516 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 16:53:28.779785 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 16:53:28.786460 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 16:53:28.797753 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 16:53:28.797956
429 16:53:28.798099
430 16:53:28.808884 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 16:53:28.811870 ARM64: Exception handlers installed.
432 16:53:28.812054 ARM64: Testing exception
433 16:53:28.815083 ARM64: Done test exception
434 16:53:28.818645 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 16:53:28.825299 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 16:53:28.838164 Probing TPM: . done!
437 16:53:28.838341 TPM ready after 0 ms
438 16:53:28.846410 Connected to device vid:did:rid of 1ae0:0028:00
439 16:53:28.852799 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 16:53:28.914814 Initialized TPM device CR50 revision 0
441 16:53:28.924058 tlcl_send_startup: Startup return code is 0
442 16:53:28.924178 TPM: setup succeeded
443 16:53:28.935281 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 16:53:28.944112 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 16:53:28.956881 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 16:53:28.965772 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 16:53:28.968939 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 16:53:28.972736 in-header: 03 07 00 00 08 00 00 00
449 16:53:28.975899 in-data: aa e4 47 04 13 02 00 00
450 16:53:28.980308 Chrome EC: UHEPI supported
451 16:53:28.986779 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 16:53:28.990552 in-header: 03 95 00 00 08 00 00 00
453 16:53:28.994279 in-data: 18 20 20 08 00 00 00 00
454 16:53:28.994369 Phase 1
455 16:53:28.997860 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 16:53:29.005264 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 16:53:29.008921 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 16:53:29.012575 Recovery requested (1009000e)
459 16:53:29.023211 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 16:53:29.026955 tlcl_extend: response is 0
461 16:53:29.035263 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 16:53:29.040985 tlcl_extend: response is 0
463 16:53:29.048377 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 16:53:29.067567 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 16:53:29.074468 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 16:53:29.074603
467 16:53:29.074703
468 16:53:29.084693 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 16:53:29.087943 ARM64: Exception handlers installed.
470 16:53:29.091171 ARM64: Testing exception
471 16:53:29.091290 ARM64: Done test exception
472 16:53:29.113400 pmic_efuse_setting: Set efuses in 11 msecs
473 16:53:29.117163 pmwrap_interface_init: Select PMIF_VLD_RDY
474 16:53:29.123793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 16:53:29.126967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 16:53:29.133906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 16:53:29.138219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 16:53:29.141205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 16:53:29.145391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 16:53:29.153717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 16:53:29.157059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 16:53:29.160667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 16:53:29.164196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 16:53:29.172437 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 16:53:29.176285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 16:53:29.180263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 16:53:29.187096 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 16:53:29.191131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 16:53:29.198801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 16:53:29.202993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 16:53:29.210355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 16:53:29.213908 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 16:53:29.221539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 16:53:29.225452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 16:53:29.232677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 16:53:29.236500 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 16:53:29.240297 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 16:53:29.247809 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 16:53:29.254661 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 16:53:29.258271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 16:53:29.262122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 16:53:29.269694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 16:53:29.273237 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 16:53:29.276838 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 16:53:29.284304 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 16:53:29.287894 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 16:53:29.291746 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 16:53:29.299505 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 16:53:29.302687 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 16:53:29.306462 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 16:53:29.313828 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 16:53:29.317373 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 16:53:29.320971 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 16:53:29.324867 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 16:53:29.328130 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 16:53:29.335378 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 16:53:29.339565 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 16:53:29.342665 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 16:53:29.346459 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 16:53:29.349871 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 16:53:29.357287 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 16:53:29.361085 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 16:53:29.365086 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 16:53:29.368580 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 16:53:29.375732 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 16:53:29.383316 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 16:53:29.391058 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 16:53:29.398123 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 16:53:29.405350 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 16:53:29.409117 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 16:53:29.416584 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 16:53:29.419881 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 16:53:29.427546 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 16:53:29.430906 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 16:53:29.438462 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 16:53:29.442381 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 16:53:29.450860 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 16:53:29.460954 [RTC]rtc_get_frequency_meter,154: input=23, output=943
539 16:53:29.469739 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 16:53:29.480000 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 16:53:29.489211 [RTC]rtc_get_frequency_meter,154: input=16, output=781
542 16:53:29.498732 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 16:53:29.508425 [RTC]rtc_get_frequency_meter,154: input=17, output=804
544 16:53:29.511895 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 16:53:29.515636 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 16:53:29.519343 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 16:53:29.526956 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 16:53:29.530468 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 16:53:29.534021 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 16:53:29.537844 ADC[4]: Raw value=906203 ID=7
551 16:53:29.537942 ADC[3]: Raw value=213810 ID=1
552 16:53:29.541689 RAM Code: 0x71
553 16:53:29.545401 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 16:53:29.549037 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 16:53:29.560400 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 16:53:29.564015 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 16:53:29.567235 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 16:53:29.573011 in-header: 03 07 00 00 08 00 00 00
559 16:53:29.576704 in-data: aa e4 47 04 13 02 00 00
560 16:53:29.581399 Chrome EC: UHEPI supported
561 16:53:29.584172 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 16:53:29.588726 in-header: 03 95 00 00 08 00 00 00
563 16:53:29.591732 in-data: 18 20 20 08 00 00 00 00
564 16:53:29.595736 MRC: failed to locate region type 0.
565 16:53:29.602828 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 16:53:29.606972 DRAM-K: Running full calibration
567 16:53:29.610103 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 16:53:29.614010 header.status = 0x0
569 16:53:29.617756 header.version = 0x6 (expected: 0x6)
570 16:53:29.621479 header.size = 0xd00 (expected: 0xd00)
571 16:53:29.621623 header.flags = 0x0
572 16:53:29.628455 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 16:53:29.646983 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
574 16:53:29.654335 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 16:53:29.654475 dram_init: ddr_geometry: 2
576 16:53:29.658091 [EMI] MDL number = 2
577 16:53:29.658205 [EMI] Get MDL freq = 0
578 16:53:29.661788 dram_init: ddr_type: 0
579 16:53:29.665741 is_discrete_lpddr4: 1
580 16:53:29.665870 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 16:53:29.669385
582 16:53:29.669472
583 16:53:29.669582 [Bian_co] ETT version 0.0.0.1
584 16:53:29.672978 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 16:53:29.676881
586 16:53:29.680168 dramc_set_vcore_voltage set vcore to 650000
587 16:53:29.680259 Read voltage for 800, 4
588 16:53:29.680329 Vio18 = 0
589 16:53:29.684031 Vcore = 650000
590 16:53:29.684128 Vdram = 0
591 16:53:29.684198 Vddq = 0
592 16:53:29.686883 Vmddr = 0
593 16:53:29.687005 dram_init: config_dvfs: 1
594 16:53:29.694885 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 16:53:29.698451 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 16:53:29.702004 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 16:53:29.706058 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 16:53:29.709782 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 16:53:29.713134 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 16:53:29.716938 MEM_TYPE=3, freq_sel=18
601 16:53:29.720767 sv_algorithm_assistance_LP4_1600
602 16:53:29.723797 ============ PULL DRAM RESETB DOWN ============
603 16:53:29.727465 ========== PULL DRAM RESETB DOWN end =========
604 16:53:29.730749 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 16:53:29.733918 ===================================
606 16:53:29.737813 LPDDR4 DRAM CONFIGURATION
607 16:53:29.741523 ===================================
608 16:53:29.741623 EX_ROW_EN[0] = 0x0
609 16:53:29.744628 EX_ROW_EN[1] = 0x0
610 16:53:29.744710 LP4Y_EN = 0x0
611 16:53:29.747788 WORK_FSP = 0x0
612 16:53:29.751617 WL = 0x2
613 16:53:29.751707 RL = 0x2
614 16:53:29.755293 BL = 0x2
615 16:53:29.755382 RPST = 0x0
616 16:53:29.755452 RD_PRE = 0x0
617 16:53:29.759166 WR_PRE = 0x1
618 16:53:29.759255 WR_PST = 0x0
619 16:53:29.762338 DBI_WR = 0x0
620 16:53:29.762431 DBI_RD = 0x0
621 16:53:29.765301 OTF = 0x1
622 16:53:29.769174 ===================================
623 16:53:29.772209 ===================================
624 16:53:29.772329 ANA top config
625 16:53:29.775997 ===================================
626 16:53:29.779386 DLL_ASYNC_EN = 0
627 16:53:29.782678 ALL_SLAVE_EN = 1
628 16:53:29.785690 NEW_RANK_MODE = 1
629 16:53:29.785805 DLL_IDLE_MODE = 1
630 16:53:29.788853 LP45_APHY_COMB_EN = 1
631 16:53:29.792282 TX_ODT_DIS = 1
632 16:53:29.796773 NEW_8X_MODE = 1
633 16:53:29.796888 ===================================
634 16:53:29.799681 ===================================
635 16:53:29.803153 data_rate = 1600
636 16:53:29.806906 CKR = 1
637 16:53:29.809783 DQ_P2S_RATIO = 8
638 16:53:29.813299 ===================================
639 16:53:29.816872 CA_P2S_RATIO = 8
640 16:53:29.820268 DQ_CA_OPEN = 0
641 16:53:29.820387 DQ_SEMI_OPEN = 0
642 16:53:29.823684 CA_SEMI_OPEN = 0
643 16:53:29.826743 CA_FULL_RATE = 0
644 16:53:29.830498 DQ_CKDIV4_EN = 1
645 16:53:29.833619 CA_CKDIV4_EN = 1
646 16:53:29.836816 CA_PREDIV_EN = 0
647 16:53:29.836951 PH8_DLY = 0
648 16:53:29.839989 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 16:53:29.843324 DQ_AAMCK_DIV = 4
650 16:53:29.847015 CA_AAMCK_DIV = 4
651 16:53:29.850055 CA_ADMCK_DIV = 4
652 16:53:29.850176 DQ_TRACK_CA_EN = 0
653 16:53:29.853751 CA_PICK = 800
654 16:53:29.856948 CA_MCKIO = 800
655 16:53:29.860599 MCKIO_SEMI = 0
656 16:53:29.864404 PLL_FREQ = 3068
657 16:53:29.868009 DQ_UI_PI_RATIO = 32
658 16:53:29.868139 CA_UI_PI_RATIO = 0
659 16:53:29.871889 ===================================
660 16:53:29.875659 ===================================
661 16:53:29.879441 memory_type:LPDDR4
662 16:53:29.879570 GP_NUM : 10
663 16:53:29.882520 SRAM_EN : 1
664 16:53:29.882647 MD32_EN : 0
665 16:53:29.887112 ===================================
666 16:53:29.890950 [ANA_INIT] >>>>>>>>>>>>>>
667 16:53:29.894149 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 16:53:29.894277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 16:53:29.897632 ===================================
670 16:53:29.901296 data_rate = 1600,PCW = 0X7600
671 16:53:29.904496 ===================================
672 16:53:29.908113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 16:53:29.914860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 16:53:29.921331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 16:53:29.924764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 16:53:29.928013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 16:53:29.931558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 16:53:29.934803 [ANA_INIT] flow start
679 16:53:29.934924 [ANA_INIT] PLL >>>>>>>>
680 16:53:29.938321 [ANA_INIT] PLL <<<<<<<<
681 16:53:29.941441 [ANA_INIT] MIDPI >>>>>>>>
682 16:53:29.941575 [ANA_INIT] MIDPI <<<<<<<<
683 16:53:29.944762 [ANA_INIT] DLL >>>>>>>>
684 16:53:29.947896 [ANA_INIT] flow end
685 16:53:29.951204 ============ LP4 DIFF to SE enter ============
686 16:53:29.955060 ============ LP4 DIFF to SE exit ============
687 16:53:29.958112 [ANA_INIT] <<<<<<<<<<<<<
688 16:53:29.961209 [Flow] Enable top DCM control >>>>>
689 16:53:29.964911 [Flow] Enable top DCM control <<<<<
690 16:53:29.968066 Enable DLL master slave shuffle
691 16:53:29.971828 ==============================================================
692 16:53:29.974963 Gating Mode config
693 16:53:29.978210 ==============================================================
694 16:53:29.981896 Config description:
695 16:53:29.991869 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 16:53:29.998408 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 16:53:30.001674 SELPH_MODE 0: By rank 1: By Phase
698 16:53:30.008531 ==============================================================
699 16:53:30.011570 GAT_TRACK_EN = 1
700 16:53:30.015121 RX_GATING_MODE = 2
701 16:53:30.018733 RX_GATING_TRACK_MODE = 2
702 16:53:30.021592 SELPH_MODE = 1
703 16:53:30.021717 PICG_EARLY_EN = 1
704 16:53:30.025177 VALID_LAT_VALUE = 1
705 16:53:30.031808 ==============================================================
706 16:53:30.034744 Enter into Gating configuration >>>>
707 16:53:30.038303 Exit from Gating configuration <<<<
708 16:53:30.041534 Enter into DVFS_PRE_config >>>>>
709 16:53:30.051687 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 16:53:30.054970 Exit from DVFS_PRE_config <<<<<
711 16:53:30.058193 Enter into PICG configuration >>>>
712 16:53:30.061577 Exit from PICG configuration <<<<
713 16:53:30.065006 [RX_INPUT] configuration >>>>>
714 16:53:30.068667 [RX_INPUT] configuration <<<<<
715 16:53:30.071658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 16:53:30.078471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 16:53:30.084886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 16:53:30.091783 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 16:53:30.094912 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 16:53:30.102155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 16:53:30.105425 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 16:53:30.112163 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 16:53:30.115389 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 16:53:30.118405 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 16:53:30.122063 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 16:53:30.128952 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 16:53:30.132130 ===================================
728 16:53:30.132253 LPDDR4 DRAM CONFIGURATION
729 16:53:30.135182 ===================================
730 16:53:30.138762 EX_ROW_EN[0] = 0x0
731 16:53:30.141895 EX_ROW_EN[1] = 0x0
732 16:53:30.142012 LP4Y_EN = 0x0
733 16:53:30.145577 WORK_FSP = 0x0
734 16:53:30.145694 WL = 0x2
735 16:53:30.148832 RL = 0x2
736 16:53:30.148962 BL = 0x2
737 16:53:30.151821 RPST = 0x0
738 16:53:30.151944 RD_PRE = 0x0
739 16:53:30.155630 WR_PRE = 0x1
740 16:53:30.155748 WR_PST = 0x0
741 16:53:30.158761 DBI_WR = 0x0
742 16:53:30.158886 DBI_RD = 0x0
743 16:53:30.162000 OTF = 0x1
744 16:53:30.165892 ===================================
745 16:53:30.168803 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 16:53:30.172598 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 16:53:30.178751 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 16:53:30.178882 ===================================
749 16:53:30.182548 LPDDR4 DRAM CONFIGURATION
750 16:53:30.185800 ===================================
751 16:53:30.189239 EX_ROW_EN[0] = 0x10
752 16:53:30.189367 EX_ROW_EN[1] = 0x0
753 16:53:30.192248 LP4Y_EN = 0x0
754 16:53:30.192374 WORK_FSP = 0x0
755 16:53:30.195300 WL = 0x2
756 16:53:30.195412 RL = 0x2
757 16:53:30.199092 BL = 0x2
758 16:53:30.202378 RPST = 0x0
759 16:53:30.202491 RD_PRE = 0x0
760 16:53:30.205383 WR_PRE = 0x1
761 16:53:30.205499 WR_PST = 0x0
762 16:53:30.209121 DBI_WR = 0x0
763 16:53:30.209264 DBI_RD = 0x0
764 16:53:30.212373 OTF = 0x1
765 16:53:30.215357 ===================================
766 16:53:30.218627 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 16:53:30.224358 nWR fixed to 40
768 16:53:30.228041 [ModeRegInit_LP4] CH0 RK0
769 16:53:30.228142 [ModeRegInit_LP4] CH0 RK1
770 16:53:30.230814 [ModeRegInit_LP4] CH1 RK0
771 16:53:30.234253 [ModeRegInit_LP4] CH1 RK1
772 16:53:30.234340 match AC timing 13
773 16:53:30.240953 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 16:53:30.244401 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 16:53:30.247957 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 16:53:30.254378 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 16:53:30.258318 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 16:53:30.258405 [EMI DOE] emi_dcm 0
779 16:53:30.264506 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 16:53:30.264659 ==
781 16:53:30.267778 Dram Type= 6, Freq= 0, CH_0, rank 0
782 16:53:30.271511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 16:53:30.271633 ==
784 16:53:30.278305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 16:53:30.281206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 16:53:30.291832 [CA 0] Center 36 (6~67) winsize 62
787 16:53:30.294944 [CA 1] Center 36 (6~67) winsize 62
788 16:53:30.298639 [CA 2] Center 34 (4~65) winsize 62
789 16:53:30.301890 [CA 3] Center 34 (4~64) winsize 61
790 16:53:30.304855 [CA 4] Center 33 (3~64) winsize 62
791 16:53:30.308634 [CA 5] Center 32 (3~62) winsize 60
792 16:53:30.308771
793 16:53:30.311798 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 16:53:30.311931
795 16:53:30.315124 [CATrainingPosCal] consider 1 rank data
796 16:53:30.318750 u2DelayCellTimex100 = 270/100 ps
797 16:53:30.321466 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 16:53:30.325277 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 16:53:30.331538 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 16:53:30.335477 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 16:53:30.338864 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 16:53:30.342158 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 16:53:30.342248
804 16:53:30.345145 CA PerBit enable=1, Macro0, CA PI delay=32
805 16:53:30.345261
806 16:53:30.348825 [CBTSetCACLKResult] CA Dly = 32
807 16:53:30.348914 CS Dly: 5 (0~36)
808 16:53:30.348984 ==
809 16:53:30.352196 Dram Type= 6, Freq= 0, CH_0, rank 1
810 16:53:30.358431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 16:53:30.358522 ==
812 16:53:30.362232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 16:53:30.368549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 16:53:30.378133 [CA 0] Center 36 (6~67) winsize 62
815 16:53:30.381144 [CA 1] Center 36 (6~67) winsize 62
816 16:53:30.384818 [CA 2] Center 34 (4~65) winsize 62
817 16:53:30.388142 [CA 3] Center 33 (3~64) winsize 62
818 16:53:30.391110 [CA 4] Center 32 (2~63) winsize 62
819 16:53:30.394935 [CA 5] Center 32 (2~63) winsize 62
820 16:53:30.395023
821 16:53:30.398081 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 16:53:30.398168
823 16:53:30.401164 [CATrainingPosCal] consider 2 rank data
824 16:53:30.404756 u2DelayCellTimex100 = 270/100 ps
825 16:53:30.407903 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 16:53:30.411115 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 16:53:30.418085 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 16:53:30.421181 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 16:53:30.424858 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 16:53:30.428353 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 16:53:30.428461
832 16:53:30.431128 CA PerBit enable=1, Macro0, CA PI delay=32
833 16:53:30.431216
834 16:53:30.434741 [CBTSetCACLKResult] CA Dly = 32
835 16:53:30.434842 CS Dly: 5 (0~36)
836 16:53:30.434925
837 16:53:30.438620 ----->DramcWriteLeveling(PI) begin...
838 16:53:30.438711 ==
839 16:53:30.442352 Dram Type= 6, Freq= 0, CH_0, rank 0
840 16:53:30.445864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 16:53:30.449308 ==
842 16:53:30.449450 Write leveling (Byte 0): 33 => 33
843 16:53:30.452941 Write leveling (Byte 1): 30 => 30
844 16:53:30.456982 DramcWriteLeveling(PI) end<-----
845 16:53:30.457101
846 16:53:30.457233 ==
847 16:53:30.459707 Dram Type= 6, Freq= 0, CH_0, rank 0
848 16:53:30.463064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 16:53:30.463145 ==
850 16:53:30.466435 [Gating] SW mode calibration
851 16:53:30.473819 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 16:53:30.480701 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 16:53:30.483942 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 16:53:30.487142 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 16:53:30.493770 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 16:53:30.497291 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:53:30.500574 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 16:53:30.507255 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 16:53:30.510393 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:53:30.513924 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:53:30.520405 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:53:30.524241 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:53:30.527456 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:53:30.530684 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 16:53:30.537331 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 16:53:30.540797 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 16:53:30.543949 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 16:53:30.550373 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 16:53:30.554005 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 16:53:30.557120 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 16:53:30.564013 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
872 16:53:30.567440 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 16:53:30.570449 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 16:53:30.577590 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 16:53:30.580875 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 16:53:30.584231 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 16:53:30.590516 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 16:53:30.593751 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 16:53:30.597482 0 9 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
880 16:53:30.603613 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 16:53:30.607118 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 16:53:30.610128 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 16:53:30.617259 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 16:53:30.620811 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 16:53:30.624068 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 16:53:30.627111 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
887 16:53:30.634102 0 10 8 | B1->B0 | 3131 2626 | 1 0 | (1 1) (0 0)
888 16:53:30.637179 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 16:53:30.640880 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 16:53:30.647135 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 16:53:30.650650 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 16:53:30.653761 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 16:53:30.660261 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 16:53:30.663812 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
895 16:53:30.667530 0 11 8 | B1->B0 | 2b2b 4242 | 0 0 | (0 0) (1 1)
896 16:53:30.673868 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
897 16:53:30.677399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 16:53:30.680311 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 16:53:30.687156 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 16:53:30.690431 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 16:53:30.694235 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 16:53:30.700468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 16:53:30.704150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 16:53:30.707311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 16:53:30.710486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 16:53:30.717488 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 16:53:30.721048 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 16:53:30.724400 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 16:53:30.730854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 16:53:30.733910 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 16:53:30.737697 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 16:53:30.744418 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 16:53:30.747517 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 16:53:30.751373 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 16:53:30.758070 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 16:53:30.760916 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 16:53:30.764126 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 16:53:30.770957 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 16:53:30.774665 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 16:53:30.777730 Total UI for P1: 0, mck2ui 16
921 16:53:30.780747 best dqsien dly found for B0: ( 0, 14, 6)
922 16:53:30.784234 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 16:53:30.787788 Total UI for P1: 0, mck2ui 16
924 16:53:30.791183 best dqsien dly found for B1: ( 0, 14, 8)
925 16:53:30.794803 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 16:53:30.798064 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 16:53:30.798178
928 16:53:30.801878 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 16:53:30.805013 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 16:53:30.808117 [Gating] SW calibration Done
931 16:53:30.808200 ==
932 16:53:30.812053 Dram Type= 6, Freq= 0, CH_0, rank 0
933 16:53:30.815148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 16:53:30.815232 ==
935 16:53:30.818306 RX Vref Scan: 0
936 16:53:30.818420
937 16:53:30.821295 RX Vref 0 -> 0, step: 1
938 16:53:30.821386
939 16:53:30.821456 RX Delay -130 -> 252, step: 16
940 16:53:30.828151 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 16:53:30.831656 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 16:53:30.834629 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 16:53:30.837892 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 16:53:30.841003 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 16:53:30.847736 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 16:53:30.851474 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 16:53:30.854709 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 16:53:30.858390 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
949 16:53:30.861230 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
950 16:53:30.867998 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
951 16:53:30.871732 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 16:53:30.874771 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
953 16:53:30.877852 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
954 16:53:30.881334 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 16:53:30.888385 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
956 16:53:30.888479 ==
957 16:53:30.891407 Dram Type= 6, Freq= 0, CH_0, rank 0
958 16:53:30.894905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 16:53:30.894988 ==
960 16:53:30.895056 DQS Delay:
961 16:53:30.898015 DQS0 = 0, DQS1 = 0
962 16:53:30.898092 DQM Delay:
963 16:53:30.901774 DQM0 = 91, DQM1 = 85
964 16:53:30.901883 DQ Delay:
965 16:53:30.904970 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
966 16:53:30.908092 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
967 16:53:30.911747 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
968 16:53:30.914944 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
969 16:53:30.915023
970 16:53:30.915090
971 16:53:30.915157 ==
972 16:53:30.918335 Dram Type= 6, Freq= 0, CH_0, rank 0
973 16:53:30.922020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 16:53:30.922099 ==
975 16:53:30.925093
976 16:53:30.925200
977 16:53:30.925268 TX Vref Scan disable
978 16:53:30.928648 == TX Byte 0 ==
979 16:53:30.931822 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 16:53:30.934927 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 16:53:30.938479 == TX Byte 1 ==
982 16:53:30.941466 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 16:53:30.945082 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 16:53:30.945191 ==
985 16:53:30.948151 Dram Type= 6, Freq= 0, CH_0, rank 0
986 16:53:30.955134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 16:53:30.955257 ==
988 16:53:30.966918 TX Vref=22, minBit 8, minWin=27, winSum=448
989 16:53:30.970269 TX Vref=24, minBit 0, minWin=28, winSum=453
990 16:53:30.973747 TX Vref=26, minBit 0, minWin=28, winSum=455
991 16:53:30.976954 TX Vref=28, minBit 0, minWin=28, winSum=456
992 16:53:30.980872 TX Vref=30, minBit 8, minWin=28, winSum=458
993 16:53:30.983949 TX Vref=32, minBit 5, minWin=28, winSum=455
994 16:53:30.990885 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
995 16:53:30.990981
996 16:53:30.993832 Final TX Range 1 Vref 30
997 16:53:30.993922
998 16:53:30.993990 ==
999 16:53:30.997249 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 16:53:31.000811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 16:53:31.000894 ==
1002 16:53:31.000962
1003 16:53:31.001026
1004 16:53:31.003833 TX Vref Scan disable
1005 16:53:31.007580 == TX Byte 0 ==
1006 16:53:31.010745 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 16:53:31.013862 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 16:53:31.017477 == TX Byte 1 ==
1009 16:53:31.020785 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 16:53:31.023860 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 16:53:31.023949
1012 16:53:31.027422 [DATLAT]
1013 16:53:31.027512 Freq=800, CH0 RK0
1014 16:53:31.027582
1015 16:53:31.030904 DATLAT Default: 0xa
1016 16:53:31.030997 0, 0xFFFF, sum = 0
1017 16:53:31.034227 1, 0xFFFF, sum = 0
1018 16:53:31.034321 2, 0xFFFF, sum = 0
1019 16:53:31.037348 3, 0xFFFF, sum = 0
1020 16:53:31.037465 4, 0xFFFF, sum = 0
1021 16:53:31.040509 5, 0xFFFF, sum = 0
1022 16:53:31.040598 6, 0xFFFF, sum = 0
1023 16:53:31.044167 7, 0xFFFF, sum = 0
1024 16:53:31.044285 8, 0xFFFF, sum = 0
1025 16:53:31.047526 9, 0x0, sum = 1
1026 16:53:31.047614 10, 0x0, sum = 2
1027 16:53:31.050429 11, 0x0, sum = 3
1028 16:53:31.050511 12, 0x0, sum = 4
1029 16:53:31.054096 best_step = 10
1030 16:53:31.054177
1031 16:53:31.054244 ==
1032 16:53:31.057303 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 16:53:31.061084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 16:53:31.061175 ==
1035 16:53:31.064190 RX Vref Scan: 1
1036 16:53:31.064303
1037 16:53:31.064399 Set Vref Range= 32 -> 127
1038 16:53:31.064493
1039 16:53:31.067515 RX Vref 32 -> 127, step: 1
1040 16:53:31.067600
1041 16:53:31.070720 RX Delay -79 -> 252, step: 8
1042 16:53:31.070813
1043 16:53:31.074142 Set Vref, RX VrefLevel [Byte0]: 32
1044 16:53:31.077485 [Byte1]: 32
1045 16:53:31.077584
1046 16:53:31.081057 Set Vref, RX VrefLevel [Byte0]: 33
1047 16:53:31.084490 [Byte1]: 33
1048 16:53:31.087559
1049 16:53:31.087640 Set Vref, RX VrefLevel [Byte0]: 34
1050 16:53:31.090785 [Byte1]: 34
1051 16:53:31.094952
1052 16:53:31.095039 Set Vref, RX VrefLevel [Byte0]: 35
1053 16:53:31.098348 [Byte1]: 35
1054 16:53:31.102618
1055 16:53:31.102709 Set Vref, RX VrefLevel [Byte0]: 36
1056 16:53:31.105702 [Byte1]: 36
1057 16:53:31.110246
1058 16:53:31.110341 Set Vref, RX VrefLevel [Byte0]: 37
1059 16:53:31.113269 [Byte1]: 37
1060 16:53:31.117561
1061 16:53:31.117650 Set Vref, RX VrefLevel [Byte0]: 38
1062 16:53:31.121304 [Byte1]: 38
1063 16:53:31.125180
1064 16:53:31.125265 Set Vref, RX VrefLevel [Byte0]: 39
1065 16:53:31.129103 [Byte1]: 39
1066 16:53:31.133146
1067 16:53:31.133244 Set Vref, RX VrefLevel [Byte0]: 40
1068 16:53:31.136121 [Byte1]: 40
1069 16:53:31.140200
1070 16:53:31.140285 Set Vref, RX VrefLevel [Byte0]: 41
1071 16:53:31.143307 [Byte1]: 41
1072 16:53:31.147726
1073 16:53:31.147806 Set Vref, RX VrefLevel [Byte0]: 42
1074 16:53:31.151183 [Byte1]: 42
1075 16:53:31.155380
1076 16:53:31.155473 Set Vref, RX VrefLevel [Byte0]: 43
1077 16:53:31.158507 [Byte1]: 43
1078 16:53:31.163108
1079 16:53:31.163197 Set Vref, RX VrefLevel [Byte0]: 44
1080 16:53:31.166333 [Byte1]: 44
1081 16:53:31.170754
1082 16:53:31.170835 Set Vref, RX VrefLevel [Byte0]: 45
1083 16:53:31.173948 [Byte1]: 45
1084 16:53:31.177762
1085 16:53:31.177871 Set Vref, RX VrefLevel [Byte0]: 46
1086 16:53:31.181376 [Byte1]: 46
1087 16:53:31.185380
1088 16:53:31.185488 Set Vref, RX VrefLevel [Byte0]: 47
1089 16:53:31.189070 [Byte1]: 47
1090 16:53:31.192830
1091 16:53:31.192910 Set Vref, RX VrefLevel [Byte0]: 48
1092 16:53:31.196113 [Byte1]: 48
1093 16:53:31.200608
1094 16:53:31.200689 Set Vref, RX VrefLevel [Byte0]: 49
1095 16:53:31.204042 [Byte1]: 49
1096 16:53:31.208133
1097 16:53:31.208239 Set Vref, RX VrefLevel [Byte0]: 50
1098 16:53:31.211506 [Byte1]: 50
1099 16:53:31.215695
1100 16:53:31.215783 Set Vref, RX VrefLevel [Byte0]: 51
1101 16:53:31.218771 [Byte1]: 51
1102 16:53:31.223415
1103 16:53:31.223526 Set Vref, RX VrefLevel [Byte0]: 52
1104 16:53:31.226561 [Byte1]: 52
1105 16:53:31.230932
1106 16:53:31.231020 Set Vref, RX VrefLevel [Byte0]: 53
1107 16:53:31.234120 [Byte1]: 53
1108 16:53:31.238262
1109 16:53:31.238350 Set Vref, RX VrefLevel [Byte0]: 54
1110 16:53:31.241377 [Byte1]: 54
1111 16:53:31.245875
1112 16:53:31.245984 Set Vref, RX VrefLevel [Byte0]: 55
1113 16:53:31.249162 [Byte1]: 55
1114 16:53:31.253393
1115 16:53:31.253504 Set Vref, RX VrefLevel [Byte0]: 56
1116 16:53:31.256492 [Byte1]: 56
1117 16:53:31.260859
1118 16:53:31.260983 Set Vref, RX VrefLevel [Byte0]: 57
1119 16:53:31.264429 [Byte1]: 57
1120 16:53:31.268469
1121 16:53:31.268560 Set Vref, RX VrefLevel [Byte0]: 58
1122 16:53:31.271638 [Byte1]: 58
1123 16:53:31.275958
1124 16:53:31.276047 Set Vref, RX VrefLevel [Byte0]: 59
1125 16:53:31.279131 [Byte1]: 59
1126 16:53:31.283483
1127 16:53:31.283573 Set Vref, RX VrefLevel [Byte0]: 60
1128 16:53:31.287066 [Byte1]: 60
1129 16:53:31.290976
1130 16:53:31.291065 Set Vref, RX VrefLevel [Byte0]: 61
1131 16:53:31.294668 [Byte1]: 61
1132 16:53:31.298960
1133 16:53:31.299049 Set Vref, RX VrefLevel [Byte0]: 62
1134 16:53:31.302114 [Byte1]: 62
1135 16:53:31.305989
1136 16:53:31.306076 Set Vref, RX VrefLevel [Byte0]: 63
1137 16:53:31.309538 [Byte1]: 63
1138 16:53:31.314019
1139 16:53:31.314107 Set Vref, RX VrefLevel [Byte0]: 64
1140 16:53:31.316926 [Byte1]: 64
1141 16:53:31.321850
1142 16:53:31.321937 Set Vref, RX VrefLevel [Byte0]: 65
1143 16:53:31.324644 [Byte1]: 65
1144 16:53:31.329294
1145 16:53:31.329385 Set Vref, RX VrefLevel [Byte0]: 66
1146 16:53:31.332215 [Byte1]: 66
1147 16:53:31.336490
1148 16:53:31.336579 Set Vref, RX VrefLevel [Byte0]: 67
1149 16:53:31.339741 [Byte1]: 67
1150 16:53:31.343917
1151 16:53:31.344004 Set Vref, RX VrefLevel [Byte0]: 68
1152 16:53:31.347615 [Byte1]: 68
1153 16:53:31.351439
1154 16:53:31.351526 Set Vref, RX VrefLevel [Byte0]: 69
1155 16:53:31.355048 [Byte1]: 69
1156 16:53:31.358830
1157 16:53:31.362626 Set Vref, RX VrefLevel [Byte0]: 70
1158 16:53:31.365853 [Byte1]: 70
1159 16:53:31.365940
1160 16:53:31.369014 Set Vref, RX VrefLevel [Byte0]: 71
1161 16:53:31.371990 [Byte1]: 71
1162 16:53:31.372077
1163 16:53:31.375532 Set Vref, RX VrefLevel [Byte0]: 72
1164 16:53:31.379101 [Byte1]: 72
1165 16:53:31.379192
1166 16:53:31.382218 Set Vref, RX VrefLevel [Byte0]: 73
1167 16:53:31.385437 [Byte1]: 73
1168 16:53:31.389152
1169 16:53:31.389243 Set Vref, RX VrefLevel [Byte0]: 74
1170 16:53:31.392729 [Byte1]: 74
1171 16:53:31.397185
1172 16:53:31.397308 Set Vref, RX VrefLevel [Byte0]: 75
1173 16:53:31.400326 [Byte1]: 75
1174 16:53:31.404538
1175 16:53:31.404658 Set Vref, RX VrefLevel [Byte0]: 76
1176 16:53:31.407775 [Byte1]: 76
1177 16:53:31.411946
1178 16:53:31.412066 Set Vref, RX VrefLevel [Byte0]: 77
1179 16:53:31.415127 [Byte1]: 77
1180 16:53:31.419458
1181 16:53:31.419579 Final RX Vref Byte 0 = 58 to rank0
1182 16:53:31.422926 Final RX Vref Byte 1 = 57 to rank0
1183 16:53:31.425936 Final RX Vref Byte 0 = 58 to rank1
1184 16:53:31.429604 Final RX Vref Byte 1 = 57 to rank1==
1185 16:53:31.432957 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 16:53:31.439536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 16:53:31.439646 ==
1188 16:53:31.439718 DQS Delay:
1189 16:53:31.439798 DQS0 = 0, DQS1 = 0
1190 16:53:31.443040 DQM Delay:
1191 16:53:31.443124 DQM0 = 92, DQM1 = 85
1192 16:53:31.446124 DQ Delay:
1193 16:53:31.449253 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1194 16:53:31.452919 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1195 16:53:31.456060 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1196 16:53:31.459384 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1197 16:53:31.459474
1198 16:53:31.459557
1199 16:53:31.466184 [DQSOSCAuto] RK0, (LSB)MR18= 0x483e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
1200 16:53:31.469453 CH0 RK0: MR19=606, MR18=483E
1201 16:53:31.476176 CH0_RK0: MR19=0x606, MR18=0x483E, DQSOSC=391, MR23=63, INC=96, DEC=64
1202 16:53:31.476292
1203 16:53:31.479417 ----->DramcWriteLeveling(PI) begin...
1204 16:53:31.479506 ==
1205 16:53:31.482973 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 16:53:31.486093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 16:53:31.486184 ==
1208 16:53:31.489814 Write leveling (Byte 0): 35 => 35
1209 16:53:31.492901 Write leveling (Byte 1): 30 => 30
1210 16:53:31.496527 DramcWriteLeveling(PI) end<-----
1211 16:53:31.496618
1212 16:53:31.496686 ==
1213 16:53:31.499816 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 16:53:31.502923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 16:53:31.503006 ==
1216 16:53:31.506056 [Gating] SW mode calibration
1217 16:53:31.512873 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 16:53:31.556925 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 16:53:31.557098 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 16:53:31.557423 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 16:53:31.557570 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 16:53:31.557730 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 16:53:31.557838 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 16:53:31.557945 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 16:53:31.558062 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 16:53:31.558166 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 16:53:31.558268 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:53:31.600738 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:53:31.601101 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:53:31.601206 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 16:53:31.601302 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 16:53:31.601398 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 16:53:31.601491 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 16:53:31.601581 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 16:53:31.601912 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 16:53:31.602183 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1237 16:53:31.602256 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1238 16:53:31.608364 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 16:53:31.611392 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 16:53:31.615000 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 16:53:31.618072 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 16:53:31.625117 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 16:53:31.628378 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 16:53:31.631284 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 16:53:31.638385 0 9 8 | B1->B0 | 2d2d 2e2e | 1 0 | (1 1) (0 0)
1246 16:53:31.641197 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 16:53:31.644890 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 16:53:31.651479 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 16:53:31.655088 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 16:53:31.658152 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 16:53:31.664777 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 16:53:31.668721 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1253 16:53:31.671576 0 10 8 | B1->B0 | 2828 2b2b | 0 0 | (1 0) (0 1)
1254 16:53:31.678609 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 16:53:31.681690 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 16:53:31.685723 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 16:53:31.689455 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 16:53:31.693303 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 16:53:31.697069 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 16:53:31.704303 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1261 16:53:31.707222 0 11 8 | B1->B0 | 3f3f 3a3a | 0 0 | (0 0) (0 0)
1262 16:53:31.711162 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 16:53:31.714945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 16:53:31.721837 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 16:53:31.724829 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 16:53:31.728472 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 16:53:31.734796 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 16:53:31.738074 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 16:53:31.741625 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1270 16:53:31.748492 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 16:53:31.751483 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 16:53:31.754685 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 16:53:31.761437 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 16:53:31.765081 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 16:53:31.768590 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 16:53:31.774772 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 16:53:31.778488 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 16:53:31.781839 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 16:53:31.784884 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 16:53:31.791553 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 16:53:31.794941 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 16:53:31.798186 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 16:53:31.805038 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 16:53:31.808284 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 16:53:31.811650 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1286 16:53:31.818654 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 16:53:31.822046 Total UI for P1: 0, mck2ui 16
1288 16:53:31.825384 best dqsien dly found for B0: ( 0, 14, 8)
1289 16:53:31.825523 Total UI for P1: 0, mck2ui 16
1290 16:53:31.831498 best dqsien dly found for B1: ( 0, 14, 8)
1291 16:53:31.835395 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1292 16:53:31.838586 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 16:53:31.838717
1294 16:53:31.841864 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1295 16:53:31.844902 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 16:53:31.848571 [Gating] SW calibration Done
1297 16:53:31.848689 ==
1298 16:53:31.851734 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 16:53:31.855142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 16:53:31.855260 ==
1301 16:53:31.858323 RX Vref Scan: 0
1302 16:53:31.858437
1303 16:53:31.858533 RX Vref 0 -> 0, step: 1
1304 16:53:31.858624
1305 16:53:31.862109 RX Delay -130 -> 252, step: 16
1306 16:53:31.865621 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1307 16:53:31.872124 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1308 16:53:31.875362 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1309 16:53:31.878472 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1310 16:53:31.882096 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1311 16:53:31.885378 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1312 16:53:31.888458 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1313 16:53:31.895197 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1314 16:53:31.898503 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1315 16:53:31.902385 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1316 16:53:31.905580 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1317 16:53:31.908844 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1318 16:53:31.915631 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1319 16:53:31.918915 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1320 16:53:31.921753 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1321 16:53:31.925587 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1322 16:53:31.925701 ==
1323 16:53:31.928685 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 16:53:31.935346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 16:53:31.935483 ==
1326 16:53:31.935583 DQS Delay:
1327 16:53:31.939239 DQS0 = 0, DQS1 = 0
1328 16:53:31.939364 DQM Delay:
1329 16:53:31.939470 DQM0 = 94, DQM1 = 81
1330 16:53:31.941770 DQ Delay:
1331 16:53:31.945588 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1332 16:53:31.948805 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1333 16:53:31.951926 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1334 16:53:31.955437 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1335 16:53:31.955525
1336 16:53:31.955615
1337 16:53:31.955695 ==
1338 16:53:31.958551 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 16:53:31.962083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 16:53:31.962180 ==
1341 16:53:31.962270
1342 16:53:31.962353
1343 16:53:31.965350 TX Vref Scan disable
1344 16:53:31.965457 == TX Byte 0 ==
1345 16:53:31.972143 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1346 16:53:31.975233 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1347 16:53:31.975330 == TX Byte 1 ==
1348 16:53:31.981785 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1349 16:53:31.985300 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1350 16:53:31.985414 ==
1351 16:53:31.989011 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 16:53:31.992127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 16:53:31.992216 ==
1354 16:53:32.006497 TX Vref=22, minBit 13, minWin=27, winSum=449
1355 16:53:32.010399 TX Vref=24, minBit 10, minWin=27, winSum=451
1356 16:53:32.013500 TX Vref=26, minBit 11, minWin=27, winSum=453
1357 16:53:32.016697 TX Vref=28, minBit 1, minWin=28, winSum=455
1358 16:53:32.020402 TX Vref=30, minBit 4, minWin=28, winSum=459
1359 16:53:32.026834 TX Vref=32, minBit 1, minWin=28, winSum=456
1360 16:53:32.029910 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 30
1361 16:53:32.030063
1362 16:53:32.033200 Final TX Range 1 Vref 30
1363 16:53:32.033352
1364 16:53:32.033477 ==
1365 16:53:32.036894 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 16:53:32.040414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 16:53:32.040556 ==
1368 16:53:32.043539
1369 16:53:32.043678
1370 16:53:32.043806 TX Vref Scan disable
1371 16:53:32.046813 == TX Byte 0 ==
1372 16:53:32.050486 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1373 16:53:32.053768 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1374 16:53:32.056790 == TX Byte 1 ==
1375 16:53:32.059983 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1376 16:53:32.063497 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1377 16:53:32.066740
1378 16:53:32.066882 [DATLAT]
1379 16:53:32.067011 Freq=800, CH0 RK1
1380 16:53:32.067138
1381 16:53:32.070378 DATLAT Default: 0xa
1382 16:53:32.070520 0, 0xFFFF, sum = 0
1383 16:53:32.073906 1, 0xFFFF, sum = 0
1384 16:53:32.074046 2, 0xFFFF, sum = 0
1385 16:53:32.076837 3, 0xFFFF, sum = 0
1386 16:53:32.076974 4, 0xFFFF, sum = 0
1387 16:53:32.080306 5, 0xFFFF, sum = 0
1388 16:53:32.080439 6, 0xFFFF, sum = 0
1389 16:53:32.083391 7, 0xFFFF, sum = 0
1390 16:53:32.086864 8, 0xFFFF, sum = 0
1391 16:53:32.086998 9, 0x0, sum = 1
1392 16:53:32.087126 10, 0x0, sum = 2
1393 16:53:32.090423 11, 0x0, sum = 3
1394 16:53:32.090554 12, 0x0, sum = 4
1395 16:53:32.093422 best_step = 10
1396 16:53:32.093590
1397 16:53:32.093711 ==
1398 16:53:32.097123 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 16:53:32.100225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 16:53:32.100361 ==
1401 16:53:32.103835 RX Vref Scan: 0
1402 16:53:32.103988
1403 16:53:32.104115 RX Vref 0 -> 0, step: 1
1404 16:53:32.104235
1405 16:53:32.107042 RX Delay -95 -> 252, step: 8
1406 16:53:32.113442 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1407 16:53:32.117211 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1408 16:53:32.120456 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1409 16:53:32.123592 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1410 16:53:32.127363 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1411 16:53:32.133854 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1412 16:53:32.136887 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1413 16:53:32.140582 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1414 16:53:32.143796 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1415 16:53:32.147312 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1416 16:53:32.154097 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1417 16:53:32.157362 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1418 16:53:32.160433 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1419 16:53:32.164164 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1420 16:53:32.167404 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1421 16:53:32.173671 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1422 16:53:32.173810 ==
1423 16:53:32.177285 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 16:53:32.180367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 16:53:32.180507 ==
1426 16:53:32.180630 DQS Delay:
1427 16:53:32.184269 DQS0 = 0, DQS1 = 0
1428 16:53:32.184406 DQM Delay:
1429 16:53:32.187251 DQM0 = 94, DQM1 = 83
1430 16:53:32.187345 DQ Delay:
1431 16:53:32.190860 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1432 16:53:32.194447 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1433 16:53:32.197373 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1434 16:53:32.201001 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1435 16:53:32.201167
1436 16:53:32.201275
1437 16:53:32.207712 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1438 16:53:32.210881 CH0 RK1: MR19=606, MR18=3F10
1439 16:53:32.217846 CH0_RK1: MR19=0x606, MR18=0x3F10, DQSOSC=393, MR23=63, INC=95, DEC=63
1440 16:53:32.221049 [RxdqsGatingPostProcess] freq 800
1441 16:53:32.224265 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 16:53:32.227491 Pre-setting of DQS Precalculation
1443 16:53:32.234275 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 16:53:32.234374 ==
1445 16:53:32.237803 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 16:53:32.240966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 16:53:32.241044 ==
1448 16:53:32.247762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 16:53:32.254270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 16:53:32.262177 [CA 0] Center 36 (6~67) winsize 62
1451 16:53:32.265204 [CA 1] Center 36 (6~67) winsize 62
1452 16:53:32.268810 [CA 2] Center 34 (4~65) winsize 62
1453 16:53:32.271777 [CA 3] Center 34 (4~65) winsize 62
1454 16:53:32.275657 [CA 4] Center 35 (5~65) winsize 61
1455 16:53:32.278789 [CA 5] Center 34 (4~64) winsize 61
1456 16:53:32.278868
1457 16:53:32.282500 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 16:53:32.282577
1459 16:53:32.285341 [CATrainingPosCal] consider 1 rank data
1460 16:53:32.288630 u2DelayCellTimex100 = 270/100 ps
1461 16:53:32.291880 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 16:53:32.295283 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 16:53:32.298829 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 16:53:32.305809 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 16:53:32.308816 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1466 16:53:32.312453 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 16:53:32.312559
1468 16:53:32.315622 CA PerBit enable=1, Macro0, CA PI delay=34
1469 16:53:32.315724
1470 16:53:32.318814 [CBTSetCACLKResult] CA Dly = 34
1471 16:53:32.318889 CS Dly: 5 (0~36)
1472 16:53:32.318955 ==
1473 16:53:32.321951 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 16:53:32.328968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 16:53:32.329070 ==
1476 16:53:32.332132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 16:53:32.339119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 16:53:32.348207 [CA 0] Center 36 (6~67) winsize 62
1479 16:53:32.351962 [CA 1] Center 37 (6~68) winsize 63
1480 16:53:32.355830 [CA 2] Center 35 (4~66) winsize 63
1481 16:53:32.360033 [CA 3] Center 35 (5~66) winsize 62
1482 16:53:32.363660 [CA 4] Center 35 (5~66) winsize 62
1483 16:53:32.363773 [CA 5] Center 34 (4~65) winsize 62
1484 16:53:32.367372
1485 16:53:32.371055 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1486 16:53:32.371148
1487 16:53:32.374762 [CATrainingPosCal] consider 2 rank data
1488 16:53:32.374855 u2DelayCellTimex100 = 270/100 ps
1489 16:53:32.377897 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1490 16:53:32.381853 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 16:53:32.385769 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1492 16:53:32.389460 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1493 16:53:32.392550 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1494 16:53:32.395884 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 16:53:32.399449
1496 16:53:32.402600 CA PerBit enable=1, Macro0, CA PI delay=34
1497 16:53:32.402695
1498 16:53:32.406127 [CBTSetCACLKResult] CA Dly = 34
1499 16:53:32.406220 CS Dly: 6 (0~38)
1500 16:53:32.406289
1501 16:53:32.409200 ----->DramcWriteLeveling(PI) begin...
1502 16:53:32.409291 ==
1503 16:53:32.412660 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 16:53:32.416180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 16:53:32.416276 ==
1506 16:53:32.419171 Write leveling (Byte 0): 27 => 27
1507 16:53:32.422415 Write leveling (Byte 1): 27 => 27
1508 16:53:32.426133 DramcWriteLeveling(PI) end<-----
1509 16:53:32.426223
1510 16:53:32.426291 ==
1511 16:53:32.429352 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 16:53:32.436303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 16:53:32.436406 ==
1514 16:53:32.436477 [Gating] SW mode calibration
1515 16:53:32.446330 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 16:53:32.449523 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 16:53:32.452719 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 16:53:32.459545 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1519 16:53:32.463085 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 16:53:32.466187 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 16:53:32.472730 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 16:53:32.476461 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 16:53:32.479526 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 16:53:32.486579 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 16:53:32.489783 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:53:32.492864 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:53:32.496425 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:53:32.503047 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 16:53:32.506585 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 16:53:32.509739 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 16:53:32.516155 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 16:53:32.519770 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 16:53:32.523255 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1534 16:53:32.529671 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 16:53:32.532881 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 16:53:32.536156 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 16:53:32.543172 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 16:53:32.546194 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 16:53:32.549963 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 16:53:32.556324 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 16:53:32.559998 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 16:53:32.562985 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
1543 16:53:32.566523 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1544 16:53:32.572940 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 16:53:32.576500 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 16:53:32.579763 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 16:53:32.586297 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 16:53:32.590077 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 16:53:32.593285 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1550 16:53:32.599679 0 10 4 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (1 0)
1551 16:53:32.603423 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1552 16:53:32.606353 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 16:53:32.613029 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 16:53:32.616745 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 16:53:32.619629 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 16:53:32.626283 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 16:53:32.629840 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 16:53:32.633257 0 11 4 | B1->B0 | 2525 3939 | 0 1 | (0 0) (0 0)
1559 16:53:32.640195 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1560 16:53:32.643242 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 16:53:32.646542 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 16:53:32.653410 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 16:53:32.656410 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 16:53:32.659707 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 16:53:32.663552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 16:53:32.670066 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1567 16:53:32.673278 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 16:53:32.676679 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 16:53:32.683221 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 16:53:32.686868 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 16:53:32.689917 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 16:53:32.696577 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 16:53:32.699924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 16:53:32.703121 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 16:53:32.710332 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 16:53:32.713232 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 16:53:32.716829 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 16:53:32.723578 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 16:53:32.726587 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 16:53:32.730190 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 16:53:32.736784 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 16:53:32.740386 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1583 16:53:32.743708 Total UI for P1: 0, mck2ui 16
1584 16:53:32.746806 best dqsien dly found for B1: ( 0, 14, 2)
1585 16:53:32.749880 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1586 16:53:32.753751 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 16:53:32.756784 Total UI for P1: 0, mck2ui 16
1588 16:53:32.759905 best dqsien dly found for B0: ( 0, 14, 6)
1589 16:53:32.763194 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1590 16:53:32.766800 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1591 16:53:32.766894
1592 16:53:32.773672 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1593 16:53:32.776698 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1594 16:53:32.776799 [Gating] SW calibration Done
1595 16:53:32.780248 ==
1596 16:53:32.783175 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 16:53:32.787125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 16:53:32.787223 ==
1599 16:53:32.787314 RX Vref Scan: 0
1600 16:53:32.787394
1601 16:53:32.790361 RX Vref 0 -> 0, step: 1
1602 16:53:32.790438
1603 16:53:32.793687 RX Delay -130 -> 252, step: 16
1604 16:53:32.796876 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1605 16:53:32.800279 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1606 16:53:32.803454 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1607 16:53:32.810507 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1608 16:53:32.813699 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1609 16:53:32.816699 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1610 16:53:32.820022 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1611 16:53:32.823572 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1612 16:53:32.830321 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1613 16:53:32.833713 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1614 16:53:32.837131 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1615 16:53:32.839987 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1616 16:53:32.843696 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1617 16:53:32.850013 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1618 16:53:32.853952 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1619 16:53:32.857377 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1620 16:53:32.857488 ==
1621 16:53:32.860494 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 16:53:32.863819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 16:53:32.863924 ==
1624 16:53:32.866944 DQS Delay:
1625 16:53:32.867038 DQS0 = 0, DQS1 = 0
1626 16:53:32.870760 DQM Delay:
1627 16:53:32.870858 DQM0 = 95, DQM1 = 91
1628 16:53:32.870926 DQ Delay:
1629 16:53:32.873865 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1630 16:53:32.877199 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1631 16:53:32.880755 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1632 16:53:32.883669 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1633 16:53:32.887251
1634 16:53:32.887334
1635 16:53:32.887400 ==
1636 16:53:32.890793 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 16:53:32.893889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 16:53:32.893975 ==
1639 16:53:32.894042
1640 16:53:32.894104
1641 16:53:32.897232 TX Vref Scan disable
1642 16:53:32.897316 == TX Byte 0 ==
1643 16:53:32.904162 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1644 16:53:32.907262 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1645 16:53:32.907378 == TX Byte 1 ==
1646 16:53:32.913637 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1647 16:53:32.917550 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1648 16:53:32.917653 ==
1649 16:53:32.920610 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 16:53:32.924132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 16:53:32.924237 ==
1652 16:53:32.934739 TX Vref=22, minBit 1, minWin=26, winSum=438
1653 16:53:32.941147 TX Vref=24, minBit 0, minWin=26, winSum=442
1654 16:53:32.944705 TX Vref=26, minBit 2, minWin=27, winSum=447
1655 16:53:32.947687 TX Vref=28, minBit 2, minWin=27, winSum=448
1656 16:53:32.951122 TX Vref=30, minBit 1, minWin=27, winSum=449
1657 16:53:32.954348 TX Vref=32, minBit 1, minWin=27, winSum=449
1658 16:53:32.960771 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1659 16:53:32.960856
1660 16:53:32.964293 Final TX Range 1 Vref 30
1661 16:53:32.964370
1662 16:53:32.964450 ==
1663 16:53:32.967466 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 16:53:32.971404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 16:53:32.971481 ==
1666 16:53:32.971548
1667 16:53:32.971612
1668 16:53:32.974563 TX Vref Scan disable
1669 16:53:32.977754 == TX Byte 0 ==
1670 16:53:32.981458 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1671 16:53:32.984563 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1672 16:53:32.987790 == TX Byte 1 ==
1673 16:53:32.991562 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1674 16:53:32.994795 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1675 16:53:32.994909
1676 16:53:32.997561 [DATLAT]
1677 16:53:32.997646 Freq=800, CH1 RK0
1678 16:53:32.997713
1679 16:53:33.001296 DATLAT Default: 0xa
1680 16:53:33.001380 0, 0xFFFF, sum = 0
1681 16:53:33.004375 1, 0xFFFF, sum = 0
1682 16:53:33.004476 2, 0xFFFF, sum = 0
1683 16:53:33.007880 3, 0xFFFF, sum = 0
1684 16:53:33.007965 4, 0xFFFF, sum = 0
1685 16:53:33.011508 5, 0xFFFF, sum = 0
1686 16:53:33.011594 6, 0xFFFF, sum = 0
1687 16:53:33.014585 7, 0xFFFF, sum = 0
1688 16:53:33.014670 8, 0xFFFF, sum = 0
1689 16:53:33.017894 9, 0x0, sum = 1
1690 16:53:33.017979 10, 0x0, sum = 2
1691 16:53:33.021042 11, 0x0, sum = 3
1692 16:53:33.021128 12, 0x0, sum = 4
1693 16:53:33.021196 best_step = 10
1694 16:53:33.024805
1695 16:53:33.024889 ==
1696 16:53:33.028057 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 16:53:33.031576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 16:53:33.031661 ==
1699 16:53:33.031727 RX Vref Scan: 1
1700 16:53:33.031791
1701 16:53:33.035154 Set Vref Range= 32 -> 127
1702 16:53:33.035239
1703 16:53:33.038151 RX Vref 32 -> 127, step: 1
1704 16:53:33.038236
1705 16:53:33.041736 RX Delay -79 -> 252, step: 8
1706 16:53:33.041820
1707 16:53:33.044792 Set Vref, RX VrefLevel [Byte0]: 32
1708 16:53:33.048171 [Byte1]: 32
1709 16:53:33.048256
1710 16:53:33.051595 Set Vref, RX VrefLevel [Byte0]: 33
1711 16:53:33.054941 [Byte1]: 33
1712 16:53:33.055063
1713 16:53:33.058375 Set Vref, RX VrefLevel [Byte0]: 34
1714 16:53:33.061275 [Byte1]: 34
1715 16:53:33.065087
1716 16:53:33.065186 Set Vref, RX VrefLevel [Byte0]: 35
1717 16:53:33.068215 [Byte1]: 35
1718 16:53:33.072461
1719 16:53:33.072546 Set Vref, RX VrefLevel [Byte0]: 36
1720 16:53:33.075880 [Byte1]: 36
1721 16:53:33.080114
1722 16:53:33.080236 Set Vref, RX VrefLevel [Byte0]: 37
1723 16:53:33.083201 [Byte1]: 37
1724 16:53:33.087731
1725 16:53:33.087815 Set Vref, RX VrefLevel [Byte0]: 38
1726 16:53:33.090804 [Byte1]: 38
1727 16:53:33.095282
1728 16:53:33.095366 Set Vref, RX VrefLevel [Byte0]: 39
1729 16:53:33.098309 [Byte1]: 39
1730 16:53:33.102500
1731 16:53:33.102584 Set Vref, RX VrefLevel [Byte0]: 40
1732 16:53:33.105841 [Byte1]: 40
1733 16:53:33.110247
1734 16:53:33.110330 Set Vref, RX VrefLevel [Byte0]: 41
1735 16:53:33.113673 [Byte1]: 41
1736 16:53:33.117757
1737 16:53:33.117841 Set Vref, RX VrefLevel [Byte0]: 42
1738 16:53:33.120848 [Byte1]: 42
1739 16:53:33.125264
1740 16:53:33.125348 Set Vref, RX VrefLevel [Byte0]: 43
1741 16:53:33.128435 [Byte1]: 43
1742 16:53:33.132897
1743 16:53:33.132998 Set Vref, RX VrefLevel [Byte0]: 44
1744 16:53:33.136104 [Byte1]: 44
1745 16:53:33.140294
1746 16:53:33.140378 Set Vref, RX VrefLevel [Byte0]: 45
1747 16:53:33.143348 [Byte1]: 45
1748 16:53:33.148173
1749 16:53:33.148257 Set Vref, RX VrefLevel [Byte0]: 46
1750 16:53:33.151219 [Byte1]: 46
1751 16:53:33.155375
1752 16:53:33.155458 Set Vref, RX VrefLevel [Byte0]: 47
1753 16:53:33.158995 [Byte1]: 47
1754 16:53:33.163030
1755 16:53:33.163112 Set Vref, RX VrefLevel [Byte0]: 48
1756 16:53:33.165903 [Byte1]: 48
1757 16:53:33.170727
1758 16:53:33.170809 Set Vref, RX VrefLevel [Byte0]: 49
1759 16:53:33.173808 [Byte1]: 49
1760 16:53:33.177767
1761 16:53:33.177850 Set Vref, RX VrefLevel [Byte0]: 50
1762 16:53:33.181664 [Byte1]: 50
1763 16:53:33.185360
1764 16:53:33.185442 Set Vref, RX VrefLevel [Byte0]: 51
1765 16:53:33.189147 [Byte1]: 51
1766 16:53:33.193440
1767 16:53:33.193531 Set Vref, RX VrefLevel [Byte0]: 52
1768 16:53:33.196634 [Byte1]: 52
1769 16:53:33.200475
1770 16:53:33.200558 Set Vref, RX VrefLevel [Byte0]: 53
1771 16:53:33.204344 [Byte1]: 53
1772 16:53:33.207943
1773 16:53:33.208026 Set Vref, RX VrefLevel [Byte0]: 54
1774 16:53:33.211486 [Byte1]: 54
1775 16:53:33.215592
1776 16:53:33.215676 Set Vref, RX VrefLevel [Byte0]: 55
1777 16:53:33.219126 [Byte1]: 55
1778 16:53:33.223463
1779 16:53:33.223546 Set Vref, RX VrefLevel [Byte0]: 56
1780 16:53:33.226885 [Byte1]: 56
1781 16:53:33.230654
1782 16:53:33.230737 Set Vref, RX VrefLevel [Byte0]: 57
1783 16:53:33.233947 [Byte1]: 57
1784 16:53:33.238467
1785 16:53:33.238551 Set Vref, RX VrefLevel [Byte0]: 58
1786 16:53:33.241914 [Byte1]: 58
1787 16:53:33.245873
1788 16:53:33.245957 Set Vref, RX VrefLevel [Byte0]: 59
1789 16:53:33.249444 [Byte1]: 59
1790 16:53:33.253441
1791 16:53:33.253582 Set Vref, RX VrefLevel [Byte0]: 60
1792 16:53:33.256613 [Byte1]: 60
1793 16:53:33.260737
1794 16:53:33.260860 Set Vref, RX VrefLevel [Byte0]: 61
1795 16:53:33.264423 [Byte1]: 61
1796 16:53:33.268615
1797 16:53:33.268720 Set Vref, RX VrefLevel [Byte0]: 62
1798 16:53:33.271573 [Byte1]: 62
1799 16:53:33.276188
1800 16:53:33.276271 Set Vref, RX VrefLevel [Byte0]: 63
1801 16:53:33.279228 [Byte1]: 63
1802 16:53:33.283748
1803 16:53:33.283831 Set Vref, RX VrefLevel [Byte0]: 64
1804 16:53:33.286900 [Byte1]: 64
1805 16:53:33.291434
1806 16:53:33.291517 Set Vref, RX VrefLevel [Byte0]: 65
1807 16:53:33.294296 [Byte1]: 65
1808 16:53:33.298756
1809 16:53:33.298839 Set Vref, RX VrefLevel [Byte0]: 66
1810 16:53:33.302062 [Byte1]: 66
1811 16:53:33.306490
1812 16:53:33.306588 Set Vref, RX VrefLevel [Byte0]: 67
1813 16:53:33.309596 [Byte1]: 67
1814 16:53:33.313980
1815 16:53:33.314064 Set Vref, RX VrefLevel [Byte0]: 68
1816 16:53:33.317188 [Byte1]: 68
1817 16:53:33.321320
1818 16:53:33.321433 Set Vref, RX VrefLevel [Byte0]: 69
1819 16:53:33.324437 [Byte1]: 69
1820 16:53:33.328783
1821 16:53:33.328867 Set Vref, RX VrefLevel [Byte0]: 70
1822 16:53:33.332371 [Byte1]: 70
1823 16:53:33.336581
1824 16:53:33.336665 Set Vref, RX VrefLevel [Byte0]: 71
1825 16:53:33.339853 [Byte1]: 71
1826 16:53:33.344075
1827 16:53:33.344159 Set Vref, RX VrefLevel [Byte0]: 72
1828 16:53:33.347370 [Byte1]: 72
1829 16:53:33.351839
1830 16:53:33.351923 Set Vref, RX VrefLevel [Byte0]: 73
1831 16:53:33.354834 [Byte1]: 73
1832 16:53:33.359094
1833 16:53:33.359217 Final RX Vref Byte 0 = 57 to rank0
1834 16:53:33.362211 Final RX Vref Byte 1 = 56 to rank0
1835 16:53:33.365927 Final RX Vref Byte 0 = 57 to rank1
1836 16:53:33.369409 Final RX Vref Byte 1 = 56 to rank1==
1837 16:53:33.372447 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 16:53:33.379499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 16:53:33.379585 ==
1840 16:53:33.379652 DQS Delay:
1841 16:53:33.379714 DQS0 = 0, DQS1 = 0
1842 16:53:33.382494 DQM Delay:
1843 16:53:33.382578 DQM0 = 95, DQM1 = 89
1844 16:53:33.385900 DQ Delay:
1845 16:53:33.389045 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1846 16:53:33.392262 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =96
1847 16:53:33.392346 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1848 16:53:33.399229 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1849 16:53:33.399333
1850 16:53:33.399401
1851 16:53:33.405647 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1852 16:53:33.409435 CH1 RK0: MR19=606, MR18=2A47
1853 16:53:33.415863 CH1_RK0: MR19=0x606, MR18=0x2A47, DQSOSC=392, MR23=63, INC=96, DEC=64
1854 16:53:33.415948
1855 16:53:33.419647 ----->DramcWriteLeveling(PI) begin...
1856 16:53:33.419733 ==
1857 16:53:33.422177 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 16:53:33.426062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 16:53:33.426147 ==
1860 16:53:33.428960 Write leveling (Byte 0): 27 => 27
1861 16:53:33.432537 Write leveling (Byte 1): 28 => 28
1862 16:53:33.435571 DramcWriteLeveling(PI) end<-----
1863 16:53:33.435656
1864 16:53:33.435723 ==
1865 16:53:33.439239 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 16:53:33.442312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 16:53:33.442397 ==
1868 16:53:33.446015 [Gating] SW mode calibration
1869 16:53:33.452316 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 16:53:33.458819 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 16:53:33.462445 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 16:53:33.465959 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 16:53:33.472616 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 16:53:33.476182 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 16:53:33.479140 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 16:53:33.485775 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 16:53:33.489269 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 16:53:33.492882 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 16:53:33.499199 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 16:53:33.502347 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 16:53:33.506212 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 16:53:33.512639 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:53:33.515757 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:53:33.519522 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 16:53:33.522610 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 16:53:33.529478 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1887 16:53:33.532590 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1888 16:53:33.535999 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1889 16:53:33.542499 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 16:53:33.546250 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 16:53:33.549370 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 16:53:33.556143 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 16:53:33.559288 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 16:53:33.562443 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 16:53:33.569736 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 16:53:33.572678 0 9 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1897 16:53:33.576383 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1898 16:53:33.582936 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 16:53:33.585808 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 16:53:33.589376 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 16:53:33.595852 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 16:53:33.599351 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 16:53:33.602505 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1904 16:53:33.605774 0 10 4 | B1->B0 | 2a2a 3232 | 0 0 | (1 0) (0 1)
1905 16:53:33.613002 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1906 16:53:33.616071 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 16:53:33.619281 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 16:53:33.626056 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 16:53:33.629120 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 16:53:33.632306 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 16:53:33.639421 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1912 16:53:33.642433 0 11 4 | B1->B0 | 3838 2b2b | 1 1 | (0 0) (0 0)
1913 16:53:33.645905 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1914 16:53:33.652450 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 16:53:33.655970 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 16:53:33.659079 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 16:53:33.666088 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 16:53:33.669305 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 16:53:33.672453 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 16:53:33.679282 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1921 16:53:33.682744 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1922 16:53:33.686364 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 16:53:33.692947 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 16:53:33.695843 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 16:53:33.699462 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 16:53:33.702429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 16:53:33.709030 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 16:53:33.712958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 16:53:33.716006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 16:53:33.722501 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 16:53:33.726436 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 16:53:33.729363 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 16:53:33.735689 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 16:53:33.739082 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 16:53:33.742792 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 16:53:33.749240 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1937 16:53:33.752532 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 16:53:33.756073 Total UI for P1: 0, mck2ui 16
1939 16:53:33.759664 best dqsien dly found for B0: ( 0, 14, 4)
1940 16:53:33.763024 Total UI for P1: 0, mck2ui 16
1941 16:53:33.765980 best dqsien dly found for B1: ( 0, 14, 4)
1942 16:53:33.769268 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1943 16:53:33.772486 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1944 16:53:33.772572
1945 16:53:33.776360 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1946 16:53:33.779236 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1947 16:53:33.782698 [Gating] SW calibration Done
1948 16:53:33.782808 ==
1949 16:53:33.785901 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 16:53:33.789378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 16:53:33.789494 ==
1952 16:53:33.792473 RX Vref Scan: 0
1953 16:53:33.792550
1954 16:53:33.796074 RX Vref 0 -> 0, step: 1
1955 16:53:33.796165
1956 16:53:33.796247 RX Delay -130 -> 252, step: 16
1957 16:53:33.803005 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1958 16:53:33.806031 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1959 16:53:33.809259 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1960 16:53:33.812864 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1961 16:53:33.816005 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1962 16:53:33.822819 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1963 16:53:33.826082 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1964 16:53:33.829206 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1965 16:53:33.832342 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1966 16:53:33.835914 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1967 16:53:33.842350 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1968 16:53:33.846049 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1969 16:53:33.849154 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1970 16:53:33.852363 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1971 16:53:33.856225 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1972 16:53:33.862595 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1973 16:53:33.862680 ==
1974 16:53:33.866222 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 16:53:33.869037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 16:53:33.869146 ==
1977 16:53:33.869247 DQS Delay:
1978 16:53:33.872808 DQS0 = 0, DQS1 = 0
1979 16:53:33.872912 DQM Delay:
1980 16:53:33.876220 DQM0 = 92, DQM1 = 91
1981 16:53:33.876339 DQ Delay:
1982 16:53:33.879613 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1983 16:53:33.882517 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1984 16:53:33.886085 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1985 16:53:33.889737 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1986 16:53:33.889848
1987 16:53:33.889943
1988 16:53:33.890037 ==
1989 16:53:33.892849 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 16:53:33.899003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 16:53:33.899091 ==
1992 16:53:33.899160
1993 16:53:33.899223
1994 16:53:33.899283 TX Vref Scan disable
1995 16:53:33.902495 == TX Byte 0 ==
1996 16:53:33.905769 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 16:53:33.909059 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 16:53:33.912849 == TX Byte 1 ==
1999 16:53:33.916140 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2000 16:53:33.919201 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2001 16:53:33.922807 ==
2002 16:53:33.926128 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 16:53:33.929208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 16:53:33.929294 ==
2005 16:53:33.941923 TX Vref=22, minBit 1, minWin=26, winSum=444
2006 16:53:33.944982 TX Vref=24, minBit 4, minWin=26, winSum=445
2007 16:53:33.948130 TX Vref=26, minBit 1, minWin=27, winSum=448
2008 16:53:33.951428 TX Vref=28, minBit 2, minWin=27, winSum=451
2009 16:53:33.955139 TX Vref=30, minBit 2, minWin=27, winSum=449
2010 16:53:33.958449 TX Vref=32, minBit 1, minWin=27, winSum=449
2011 16:53:33.965298 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
2012 16:53:33.965405
2013 16:53:33.968443 Final TX Range 1 Vref 28
2014 16:53:33.968548
2015 16:53:33.968644 ==
2016 16:53:33.971524 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 16:53:33.975295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 16:53:33.975373 ==
2019 16:53:33.975438
2020 16:53:33.975500
2021 16:53:33.978237 TX Vref Scan disable
2022 16:53:33.981785 == TX Byte 0 ==
2023 16:53:33.985421 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 16:53:33.988631 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 16:53:33.991857 == TX Byte 1 ==
2026 16:53:33.995337 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2027 16:53:33.998687 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2028 16:53:33.998780
2029 16:53:34.001774 [DATLAT]
2030 16:53:34.001858 Freq=800, CH1 RK1
2031 16:53:34.001926
2032 16:53:34.005283 DATLAT Default: 0xa
2033 16:53:34.005382 0, 0xFFFF, sum = 0
2034 16:53:34.008750 1, 0xFFFF, sum = 0
2035 16:53:34.008839 2, 0xFFFF, sum = 0
2036 16:53:34.011762 3, 0xFFFF, sum = 0
2037 16:53:34.011851 4, 0xFFFF, sum = 0
2038 16:53:34.015181 5, 0xFFFF, sum = 0
2039 16:53:34.015295 6, 0xFFFF, sum = 0
2040 16:53:34.018728 7, 0xFFFF, sum = 0
2041 16:53:34.018822 8, 0xFFFF, sum = 0
2042 16:53:34.022213 9, 0x0, sum = 1
2043 16:53:34.022293 10, 0x0, sum = 2
2044 16:53:34.025109 11, 0x0, sum = 3
2045 16:53:34.025217 12, 0x0, sum = 4
2046 16:53:34.028578 best_step = 10
2047 16:53:34.028665
2048 16:53:34.028734 ==
2049 16:53:34.031862 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 16:53:34.035714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 16:53:34.035809 ==
2052 16:53:34.038846 RX Vref Scan: 0
2053 16:53:34.038928
2054 16:53:34.038995 RX Vref 0 -> 0, step: 1
2055 16:53:34.039063
2056 16:53:34.042051 RX Delay -79 -> 252, step: 8
2057 16:53:34.045174 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2058 16:53:34.052250 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2059 16:53:34.055523 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2060 16:53:34.058746 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2061 16:53:34.061746 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2062 16:53:34.065058 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2063 16:53:34.071741 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2064 16:53:34.075327 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2065 16:53:34.078369 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2066 16:53:34.082151 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2067 16:53:34.085171 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2068 16:53:34.088924 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2069 16:53:34.095217 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2070 16:53:34.098895 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2071 16:53:34.101999 iDelay=209, Bit 14, Center 104 (9 ~ 200) 192
2072 16:53:34.105273 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2073 16:53:34.105385 ==
2074 16:53:34.108895 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 16:53:34.115187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 16:53:34.115288 ==
2077 16:53:34.115367 DQS Delay:
2078 16:53:34.115472 DQS0 = 0, DQS1 = 0
2079 16:53:34.119060 DQM Delay:
2080 16:53:34.119188 DQM0 = 97, DQM1 = 92
2081 16:53:34.121950 DQ Delay:
2082 16:53:34.125428 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2083 16:53:34.128985 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2084 16:53:34.131879 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2085 16:53:34.135264 DQ12 =100, DQ13 =96, DQ14 =104, DQ15 =96
2086 16:53:34.135375
2087 16:53:34.135473
2088 16:53:34.142234 [DQSOSCAuto] RK1, (LSB)MR18= 0x430d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
2089 16:53:34.145426 CH1 RK1: MR19=606, MR18=430D
2090 16:53:34.152249 CH1_RK1: MR19=0x606, MR18=0x430D, DQSOSC=393, MR23=63, INC=95, DEC=63
2091 16:53:34.155485 [RxdqsGatingPostProcess] freq 800
2092 16:53:34.158720 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 16:53:34.162640 Pre-setting of DQS Precalculation
2094 16:53:34.168973 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 16:53:34.175250 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 16:53:34.182013 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 16:53:34.182106
2098 16:53:34.182174
2099 16:53:34.185338 [Calibration Summary] 1600 Mbps
2100 16:53:34.185442 CH 0, Rank 0
2101 16:53:34.188569 SW Impedance : PASS
2102 16:53:34.192320 DUTY Scan : NO K
2103 16:53:34.192412 ZQ Calibration : PASS
2104 16:53:34.195790 Jitter Meter : NO K
2105 16:53:34.198852 CBT Training : PASS
2106 16:53:34.198940 Write leveling : PASS
2107 16:53:34.202067 RX DQS gating : PASS
2108 16:53:34.205285 RX DQ/DQS(RDDQC) : PASS
2109 16:53:34.205397 TX DQ/DQS : PASS
2110 16:53:34.208977 RX DATLAT : PASS
2111 16:53:34.211894 RX DQ/DQS(Engine): PASS
2112 16:53:34.211980 TX OE : NO K
2113 16:53:34.212049 All Pass.
2114 16:53:34.212112
2115 16:53:34.215475 CH 0, Rank 1
2116 16:53:34.215561 SW Impedance : PASS
2117 16:53:34.219006 DUTY Scan : NO K
2118 16:53:34.222101 ZQ Calibration : PASS
2119 16:53:34.222191 Jitter Meter : NO K
2120 16:53:34.225346 CBT Training : PASS
2121 16:53:34.228966 Write leveling : PASS
2122 16:53:34.229054 RX DQS gating : PASS
2123 16:53:34.231958 RX DQ/DQS(RDDQC) : PASS
2124 16:53:34.235438 TX DQ/DQS : PASS
2125 16:53:34.235549 RX DATLAT : PASS
2126 16:53:34.238490 RX DQ/DQS(Engine): PASS
2127 16:53:34.242347 TX OE : NO K
2128 16:53:34.242443 All Pass.
2129 16:53:34.242512
2130 16:53:34.242575 CH 1, Rank 0
2131 16:53:34.245417 SW Impedance : PASS
2132 16:53:34.248590 DUTY Scan : NO K
2133 16:53:34.248668 ZQ Calibration : PASS
2134 16:53:34.252327 Jitter Meter : NO K
2135 16:53:34.252414 CBT Training : PASS
2136 16:53:34.255387 Write leveling : PASS
2137 16:53:34.258558 RX DQS gating : PASS
2138 16:53:34.258643 RX DQ/DQS(RDDQC) : PASS
2139 16:53:34.262379 TX DQ/DQS : PASS
2140 16:53:34.265573 RX DATLAT : PASS
2141 16:53:34.265660 RX DQ/DQS(Engine): PASS
2142 16:53:34.268798 TX OE : NO K
2143 16:53:34.268884 All Pass.
2144 16:53:34.268951
2145 16:53:34.272150 CH 1, Rank 1
2146 16:53:34.272236 SW Impedance : PASS
2147 16:53:34.275707 DUTY Scan : NO K
2148 16:53:34.278810 ZQ Calibration : PASS
2149 16:53:34.278903 Jitter Meter : NO K
2150 16:53:34.282600 CBT Training : PASS
2151 16:53:34.282689 Write leveling : PASS
2152 16:53:34.285704 RX DQS gating : PASS
2153 16:53:34.289290 RX DQ/DQS(RDDQC) : PASS
2154 16:53:34.289405 TX DQ/DQS : PASS
2155 16:53:34.292219 RX DATLAT : PASS
2156 16:53:34.295871 RX DQ/DQS(Engine): PASS
2157 16:53:34.295958 TX OE : NO K
2158 16:53:34.299126 All Pass.
2159 16:53:34.299212
2160 16:53:34.299280 DramC Write-DBI off
2161 16:53:34.302719 PER_BANK_REFRESH: Hybrid Mode
2162 16:53:34.305762 TX_TRACKING: ON
2163 16:53:34.309047 [GetDramInforAfterCalByMRR] Vendor 6.
2164 16:53:34.312697 [GetDramInforAfterCalByMRR] Revision 606.
2165 16:53:34.315855 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 16:53:34.315980 MR0 0x3b3b
2167 16:53:34.316058 MR8 0x5151
2168 16:53:34.319453 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 16:53:34.322410
2170 16:53:34.322497 MR0 0x3b3b
2171 16:53:34.322565 MR8 0x5151
2172 16:53:34.326072 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 16:53:34.326163
2174 16:53:34.336162 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 16:53:34.339205 [FAST_K] Save calibration result to emmc
2176 16:53:34.342599 [FAST_K] Save calibration result to emmc
2177 16:53:34.346011 dram_init: config_dvfs: 1
2178 16:53:34.349431 dramc_set_vcore_voltage set vcore to 662500
2179 16:53:34.352633 Read voltage for 1200, 2
2180 16:53:34.352761 Vio18 = 0
2181 16:53:34.352860 Vcore = 662500
2182 16:53:34.355744 Vdram = 0
2183 16:53:34.355830 Vddq = 0
2184 16:53:34.355897 Vmddr = 0
2185 16:53:34.362521 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 16:53:34.365630 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 16:53:34.369388 MEM_TYPE=3, freq_sel=15
2188 16:53:34.372663 sv_algorithm_assistance_LP4_1600
2189 16:53:34.375732 ============ PULL DRAM RESETB DOWN ============
2190 16:53:34.379010 ========== PULL DRAM RESETB DOWN end =========
2191 16:53:34.385828 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 16:53:34.389112 ===================================
2193 16:53:34.389199 LPDDR4 DRAM CONFIGURATION
2194 16:53:34.392297 ===================================
2195 16:53:34.395773 EX_ROW_EN[0] = 0x0
2196 16:53:34.399317 EX_ROW_EN[1] = 0x0
2197 16:53:34.399406 LP4Y_EN = 0x0
2198 16:53:34.402427 WORK_FSP = 0x0
2199 16:53:34.402514 WL = 0x4
2200 16:53:34.406087 RL = 0x4
2201 16:53:34.406173 BL = 0x2
2202 16:53:34.409370 RPST = 0x0
2203 16:53:34.409458 RD_PRE = 0x0
2204 16:53:34.412447 WR_PRE = 0x1
2205 16:53:34.412532 WR_PST = 0x0
2206 16:53:34.416096 DBI_WR = 0x0
2207 16:53:34.416201 DBI_RD = 0x0
2208 16:53:34.419311 OTF = 0x1
2209 16:53:34.422383 ===================================
2210 16:53:34.425868 ===================================
2211 16:53:34.425972 ANA top config
2212 16:53:34.429409 ===================================
2213 16:53:34.432373 DLL_ASYNC_EN = 0
2214 16:53:34.435979 ALL_SLAVE_EN = 0
2215 16:53:34.436098 NEW_RANK_MODE = 1
2216 16:53:34.439511 DLL_IDLE_MODE = 1
2217 16:53:34.442391 LP45_APHY_COMB_EN = 1
2218 16:53:34.445865 TX_ODT_DIS = 1
2219 16:53:34.449427 NEW_8X_MODE = 1
2220 16:53:34.452521 ===================================
2221 16:53:34.455814 ===================================
2222 16:53:34.455934 data_rate = 2400
2223 16:53:34.459166 CKR = 1
2224 16:53:34.462677 DQ_P2S_RATIO = 8
2225 16:53:34.465814 ===================================
2226 16:53:34.469171 CA_P2S_RATIO = 8
2227 16:53:34.472364 DQ_CA_OPEN = 0
2228 16:53:34.476071 DQ_SEMI_OPEN = 0
2229 16:53:34.476188 CA_SEMI_OPEN = 0
2230 16:53:34.479300 CA_FULL_RATE = 0
2231 16:53:34.482548 DQ_CKDIV4_EN = 0
2232 16:53:34.486218 CA_CKDIV4_EN = 0
2233 16:53:34.489407 CA_PREDIV_EN = 0
2234 16:53:34.492820 PH8_DLY = 17
2235 16:53:34.492923 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 16:53:34.495949 DQ_AAMCK_DIV = 4
2237 16:53:34.499515 CA_AAMCK_DIV = 4
2238 16:53:34.502415 CA_ADMCK_DIV = 4
2239 16:53:34.506026 DQ_TRACK_CA_EN = 0
2240 16:53:34.509495 CA_PICK = 1200
2241 16:53:34.509603 CA_MCKIO = 1200
2242 16:53:34.512578 MCKIO_SEMI = 0
2243 16:53:34.515842 PLL_FREQ = 2366
2244 16:53:34.518993 DQ_UI_PI_RATIO = 32
2245 16:53:34.522417 CA_UI_PI_RATIO = 0
2246 16:53:34.525847 ===================================
2247 16:53:34.529541 ===================================
2248 16:53:34.532642 memory_type:LPDDR4
2249 16:53:34.532748 GP_NUM : 10
2250 16:53:34.536063 SRAM_EN : 1
2251 16:53:34.536154 MD32_EN : 0
2252 16:53:34.539127 ===================================
2253 16:53:34.542762 [ANA_INIT] >>>>>>>>>>>>>>
2254 16:53:34.546282 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 16:53:34.549177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 16:53:34.552701 ===================================
2257 16:53:34.556219 data_rate = 2400,PCW = 0X5b00
2258 16:53:34.559655 ===================================
2259 16:53:34.562633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 16:53:34.566014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 16:53:34.573058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 16:53:34.576147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 16:53:34.579349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 16:53:34.586194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 16:53:34.586278 [ANA_INIT] flow start
2266 16:53:34.589191 [ANA_INIT] PLL >>>>>>>>
2267 16:53:34.589271 [ANA_INIT] PLL <<<<<<<<
2268 16:53:34.592975 [ANA_INIT] MIDPI >>>>>>>>
2269 16:53:34.596344 [ANA_INIT] MIDPI <<<<<<<<
2270 16:53:34.599467 [ANA_INIT] DLL >>>>>>>>
2271 16:53:34.599547 [ANA_INIT] DLL <<<<<<<<
2272 16:53:34.602688 [ANA_INIT] flow end
2273 16:53:34.605725 ============ LP4 DIFF to SE enter ============
2274 16:53:34.609529 ============ LP4 DIFF to SE exit ============
2275 16:53:34.612664 [ANA_INIT] <<<<<<<<<<<<<
2276 16:53:34.616095 [Flow] Enable top DCM control >>>>>
2277 16:53:34.619329 [Flow] Enable top DCM control <<<<<
2278 16:53:34.622944 Enable DLL master slave shuffle
2279 16:53:34.629946 ==============================================================
2280 16:53:34.630073 Gating Mode config
2281 16:53:34.636189 ==============================================================
2282 16:53:34.636332 Config description:
2283 16:53:34.646161 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 16:53:34.652497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 16:53:34.659247 SELPH_MODE 0: By rank 1: By Phase
2286 16:53:34.662692 ==============================================================
2287 16:53:34.666142 GAT_TRACK_EN = 1
2288 16:53:34.669421 RX_GATING_MODE = 2
2289 16:53:34.673154 RX_GATING_TRACK_MODE = 2
2290 16:53:34.676103 SELPH_MODE = 1
2291 16:53:34.679799 PICG_EARLY_EN = 1
2292 16:53:34.683095 VALID_LAT_VALUE = 1
2293 16:53:34.686258 ==============================================================
2294 16:53:34.690104 Enter into Gating configuration >>>>
2295 16:53:34.693091 Exit from Gating configuration <<<<
2296 16:53:34.696755 Enter into DVFS_PRE_config >>>>>
2297 16:53:34.709507 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 16:53:34.709660 Exit from DVFS_PRE_config <<<<<
2299 16:53:34.713214 Enter into PICG configuration >>>>
2300 16:53:34.716258 Exit from PICG configuration <<<<
2301 16:53:34.719883 [RX_INPUT] configuration >>>>>
2302 16:53:34.722889 [RX_INPUT] configuration <<<<<
2303 16:53:34.729533 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 16:53:34.733165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 16:53:34.740165 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 16:53:34.746543 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 16:53:34.753406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 16:53:34.759786 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 16:53:34.763235 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 16:53:34.766820 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 16:53:34.769822 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 16:53:34.773258 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 16:53:34.779738 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 16:53:34.783277 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 16:53:34.786970 ===================================
2316 16:53:34.790265 LPDDR4 DRAM CONFIGURATION
2317 16:53:34.793471 ===================================
2318 16:53:34.793596 EX_ROW_EN[0] = 0x0
2319 16:53:34.796549 EX_ROW_EN[1] = 0x0
2320 16:53:34.796661 LP4Y_EN = 0x0
2321 16:53:34.800192 WORK_FSP = 0x0
2322 16:53:34.800280 WL = 0x4
2323 16:53:34.803483 RL = 0x4
2324 16:53:34.803569 BL = 0x2
2325 16:53:34.806580 RPST = 0x0
2326 16:53:34.806667 RD_PRE = 0x0
2327 16:53:34.809710 WR_PRE = 0x1
2328 16:53:34.813413 WR_PST = 0x0
2329 16:53:34.813496 DBI_WR = 0x0
2330 16:53:34.816528 DBI_RD = 0x0
2331 16:53:34.816634 OTF = 0x1
2332 16:53:34.819692 ===================================
2333 16:53:34.823543 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 16:53:34.826727 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 16:53:34.833694 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 16:53:34.836466 ===================================
2337 16:53:34.836586 LPDDR4 DRAM CONFIGURATION
2338 16:53:34.840214 ===================================
2339 16:53:34.843291 EX_ROW_EN[0] = 0x10
2340 16:53:34.847078 EX_ROW_EN[1] = 0x0
2341 16:53:34.847170 LP4Y_EN = 0x0
2342 16:53:34.850155 WORK_FSP = 0x0
2343 16:53:34.850241 WL = 0x4
2344 16:53:34.853177 RL = 0x4
2345 16:53:34.853283 BL = 0x2
2346 16:53:34.857077 RPST = 0x0
2347 16:53:34.857162 RD_PRE = 0x0
2348 16:53:34.860089 WR_PRE = 0x1
2349 16:53:34.860181 WR_PST = 0x0
2350 16:53:34.863459 DBI_WR = 0x0
2351 16:53:34.863542 DBI_RD = 0x0
2352 16:53:34.866865 OTF = 0x1
2353 16:53:34.870458 ===================================
2354 16:53:34.876770 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 16:53:34.876862 ==
2356 16:53:34.880200 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 16:53:34.883562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 16:53:34.883673 ==
2359 16:53:34.887093 [Duty_Offset_Calibration]
2360 16:53:34.887208 B0:2 B1:1 CA:1
2361 16:53:34.887304
2362 16:53:34.890259 [DutyScan_Calibration_Flow] k_type=0
2363 16:53:34.900177
2364 16:53:34.900303 ==CLK 0==
2365 16:53:34.903751 Final CLK duty delay cell = 0
2366 16:53:34.907150 [0] MAX Duty = 5187%(X100), DQS PI = 24
2367 16:53:34.910384 [0] MIN Duty = 4875%(X100), DQS PI = 0
2368 16:53:34.910470 [0] AVG Duty = 5031%(X100)
2369 16:53:34.913481
2370 16:53:34.916648 CH0 CLK Duty spec in!! Max-Min= 312%
2371 16:53:34.920310 [DutyScan_Calibration_Flow] ====Done====
2372 16:53:34.920394
2373 16:53:34.923493 [DutyScan_Calibration_Flow] k_type=1
2374 16:53:34.938406
2375 16:53:34.938515 ==DQS 0 ==
2376 16:53:34.941756 Final DQS duty delay cell = -4
2377 16:53:34.944655 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2378 16:53:34.948028 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2379 16:53:34.951633 [-4] AVG Duty = 4953%(X100)
2380 16:53:34.951760
2381 16:53:34.951858 ==DQS 1 ==
2382 16:53:34.954893 Final DQS duty delay cell = -4
2383 16:53:34.957956 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2384 16:53:34.961659 [-4] MIN Duty = 4844%(X100), DQS PI = 34
2385 16:53:34.964835 [-4] AVG Duty = 4906%(X100)
2386 16:53:34.964929
2387 16:53:34.967878 CH0 DQS 0 Duty spec in!! Max-Min= 405%
2388 16:53:34.967982
2389 16:53:34.971467 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2390 16:53:34.974817 [DutyScan_Calibration_Flow] ====Done====
2391 16:53:34.974949
2392 16:53:34.978416 [DutyScan_Calibration_Flow] k_type=3
2393 16:53:34.994932
2394 16:53:34.995093 ==DQM 0 ==
2395 16:53:34.998482 Final DQM duty delay cell = 0
2396 16:53:35.002176 [0] MAX Duty = 5156%(X100), DQS PI = 30
2397 16:53:35.005157 [0] MIN Duty = 4907%(X100), DQS PI = 58
2398 16:53:35.005244 [0] AVG Duty = 5031%(X100)
2399 16:53:35.009000
2400 16:53:35.009158 ==DQM 1 ==
2401 16:53:35.012339 Final DQM duty delay cell = 0
2402 16:53:35.015277 [0] MAX Duty = 5093%(X100), DQS PI = 0
2403 16:53:35.018605 [0] MIN Duty = 5031%(X100), DQS PI = 34
2404 16:53:35.018712 [0] AVG Duty = 5062%(X100)
2405 16:53:35.021854
2406 16:53:35.025326 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2407 16:53:35.025412
2408 16:53:35.028454 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2409 16:53:35.032489 [DutyScan_Calibration_Flow] ====Done====
2410 16:53:35.032653
2411 16:53:35.035689 [DutyScan_Calibration_Flow] k_type=2
2412 16:53:35.051688
2413 16:53:35.051831 ==DQ 0 ==
2414 16:53:35.055365 Final DQ duty delay cell = 0
2415 16:53:35.058242 [0] MAX Duty = 5062%(X100), DQS PI = 32
2416 16:53:35.061979 [0] MIN Duty = 4875%(X100), DQS PI = 62
2417 16:53:35.062062 [0] AVG Duty = 4968%(X100)
2418 16:53:35.062138
2419 16:53:35.065065 ==DQ 1 ==
2420 16:53:35.068763 Final DQ duty delay cell = 0
2421 16:53:35.072001 [0] MAX Duty = 5093%(X100), DQS PI = 24
2422 16:53:35.075241 [0] MIN Duty = 4938%(X100), DQS PI = 36
2423 16:53:35.075325 [0] AVG Duty = 5015%(X100)
2424 16:53:35.075402
2425 16:53:35.078307 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2426 16:53:35.078397
2427 16:53:35.085392 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2428 16:53:35.088376 [DutyScan_Calibration_Flow] ====Done====
2429 16:53:35.088498 ==
2430 16:53:35.091955 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 16:53:35.094719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 16:53:35.094809 ==
2433 16:53:35.098169 [Duty_Offset_Calibration]
2434 16:53:35.098250 B0:1 B1:0 CA:0
2435 16:53:35.098317
2436 16:53:35.101563 [DutyScan_Calibration_Flow] k_type=0
2437 16:53:35.111082
2438 16:53:35.111228 ==CLK 0==
2439 16:53:35.113989 Final CLK duty delay cell = -4
2440 16:53:35.117800 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2441 16:53:35.121024 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2442 16:53:35.124124 [-4] AVG Duty = 4969%(X100)
2443 16:53:35.124231
2444 16:53:35.127878 CH1 CLK Duty spec in!! Max-Min= 124%
2445 16:53:35.130979 [DutyScan_Calibration_Flow] ====Done====
2446 16:53:35.131092
2447 16:53:35.134104 [DutyScan_Calibration_Flow] k_type=1
2448 16:53:35.150913
2449 16:53:35.151093 ==DQS 0 ==
2450 16:53:35.153958 Final DQS duty delay cell = 0
2451 16:53:35.157319 [0] MAX Duty = 5094%(X100), DQS PI = 28
2452 16:53:35.161307 [0] MIN Duty = 4813%(X100), DQS PI = 0
2453 16:53:35.161419 [0] AVG Duty = 4953%(X100)
2454 16:53:35.163686
2455 16:53:35.163787 ==DQS 1 ==
2456 16:53:35.167370 Final DQS duty delay cell = 0
2457 16:53:35.171175 [0] MAX Duty = 5187%(X100), DQS PI = 18
2458 16:53:35.173840 [0] MIN Duty = 4969%(X100), DQS PI = 10
2459 16:53:35.173958 [0] AVG Duty = 5078%(X100)
2460 16:53:35.177473
2461 16:53:35.180556 CH1 DQS 0 Duty spec in!! Max-Min= 281%
2462 16:53:35.180670
2463 16:53:35.183718 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2464 16:53:35.187245 [DutyScan_Calibration_Flow] ====Done====
2465 16:53:35.187355
2466 16:53:35.190317 [DutyScan_Calibration_Flow] k_type=3
2467 16:53:35.207255
2468 16:53:35.207401 ==DQM 0 ==
2469 16:53:35.210949 Final DQM duty delay cell = 0
2470 16:53:35.213814 [0] MAX Duty = 5156%(X100), DQS PI = 6
2471 16:53:35.217446 [0] MIN Duty = 5031%(X100), DQS PI = 0
2472 16:53:35.217566 [0] AVG Duty = 5093%(X100)
2473 16:53:35.220464
2474 16:53:35.220568 ==DQM 1 ==
2475 16:53:35.223686 Final DQM duty delay cell = 0
2476 16:53:35.227403 [0] MAX Duty = 5031%(X100), DQS PI = 14
2477 16:53:35.230598 [0] MIN Duty = 4907%(X100), DQS PI = 36
2478 16:53:35.230704 [0] AVG Duty = 4969%(X100)
2479 16:53:35.233748
2480 16:53:35.236871 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2481 16:53:35.237008
2482 16:53:35.240736 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2483 16:53:35.243991 [DutyScan_Calibration_Flow] ====Done====
2484 16:53:35.244099
2485 16:53:35.247252 [DutyScan_Calibration_Flow] k_type=2
2486 16:53:35.262969
2487 16:53:35.263140 ==DQ 0 ==
2488 16:53:35.266852 Final DQ duty delay cell = -4
2489 16:53:35.269792 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2490 16:53:35.273175 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2491 16:53:35.276192 [-4] AVG Duty = 4984%(X100)
2492 16:53:35.276304
2493 16:53:35.276400 ==DQ 1 ==
2494 16:53:35.280062 Final DQ duty delay cell = 0
2495 16:53:35.283316 [0] MAX Duty = 5125%(X100), DQS PI = 20
2496 16:53:35.286442 [0] MIN Duty = 4969%(X100), DQS PI = 12
2497 16:53:35.286556 [0] AVG Duty = 5047%(X100)
2498 16:53:35.289519
2499 16:53:35.293224 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2500 16:53:35.293332
2501 16:53:35.296655 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2502 16:53:35.299753 [DutyScan_Calibration_Flow] ====Done====
2503 16:53:35.302891 nWR fixed to 30
2504 16:53:35.303003 [ModeRegInit_LP4] CH0 RK0
2505 16:53:35.306446 [ModeRegInit_LP4] CH0 RK1
2506 16:53:35.309470 [ModeRegInit_LP4] CH1 RK0
2507 16:53:35.312953 [ModeRegInit_LP4] CH1 RK1
2508 16:53:35.313067 match AC timing 7
2509 16:53:35.316444 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 16:53:35.323091 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 16:53:35.327062 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 16:53:35.329946 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 16:53:35.336286 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 16:53:35.336400 ==
2515 16:53:35.340012 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 16:53:35.343229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 16:53:35.343314 ==
2518 16:53:35.349521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 16:53:35.353451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 16:53:35.363569 [CA 0] Center 39 (8~70) winsize 63
2521 16:53:35.366668 [CA 1] Center 39 (9~70) winsize 62
2522 16:53:35.369974 [CA 2] Center 35 (5~66) winsize 62
2523 16:53:35.373412 [CA 3] Center 34 (4~65) winsize 62
2524 16:53:35.376373 [CA 4] Center 33 (3~64) winsize 62
2525 16:53:35.379899 [CA 5] Center 32 (3~62) winsize 60
2526 16:53:35.380033
2527 16:53:35.383128 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2528 16:53:35.383229
2529 16:53:35.386839 [CATrainingPosCal] consider 1 rank data
2530 16:53:35.389919 u2DelayCellTimex100 = 270/100 ps
2531 16:53:35.393687 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2532 16:53:35.396829 CA1 delay=39 (9~70),Diff = 7 PI (33 cell)
2533 16:53:35.403528 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2534 16:53:35.406439 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2535 16:53:35.410029 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2536 16:53:35.413735 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2537 16:53:35.413850
2538 16:53:35.416736 CA PerBit enable=1, Macro0, CA PI delay=32
2539 16:53:35.416829
2540 16:53:35.420148 [CBTSetCACLKResult] CA Dly = 32
2541 16:53:35.420244 CS Dly: 6 (0~37)
2542 16:53:35.420313 ==
2543 16:53:35.423112 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 16:53:35.430251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 16:53:35.430376 ==
2546 16:53:35.433203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 16:53:35.440163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2548 16:53:35.449238 [CA 0] Center 38 (8~69) winsize 62
2549 16:53:35.452331 [CA 1] Center 38 (8~69) winsize 62
2550 16:53:35.455460 [CA 2] Center 35 (5~66) winsize 62
2551 16:53:35.458764 [CA 3] Center 34 (4~65) winsize 62
2552 16:53:35.462115 [CA 4] Center 33 (3~64) winsize 62
2553 16:53:35.465775 [CA 5] Center 32 (3~62) winsize 60
2554 16:53:35.465885
2555 16:53:35.468877 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2556 16:53:35.468972
2557 16:53:35.472542 [CATrainingPosCal] consider 2 rank data
2558 16:53:35.475509 u2DelayCellTimex100 = 270/100 ps
2559 16:53:35.479032 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2560 16:53:35.482457 CA1 delay=39 (9~69),Diff = 7 PI (33 cell)
2561 16:53:35.489077 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2562 16:53:35.492763 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2563 16:53:35.495768 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2564 16:53:35.498948 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2565 16:53:35.499055
2566 16:53:35.502840 CA PerBit enable=1, Macro0, CA PI delay=32
2567 16:53:35.502935
2568 16:53:35.505931 [CBTSetCACLKResult] CA Dly = 32
2569 16:53:35.506019 CS Dly: 6 (0~38)
2570 16:53:35.506088
2571 16:53:35.509657 ----->DramcWriteLeveling(PI) begin...
2572 16:53:35.509746 ==
2573 16:53:35.512454 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 16:53:35.518983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 16:53:35.519112 ==
2576 16:53:35.522483 Write leveling (Byte 0): 32 => 32
2577 16:53:35.525909 Write leveling (Byte 1): 30 => 30
2578 16:53:35.526007 DramcWriteLeveling(PI) end<-----
2579 16:53:35.529399
2580 16:53:35.529494 ==
2581 16:53:35.532849 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 16:53:35.536170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 16:53:35.536278 ==
2584 16:53:35.539200 [Gating] SW mode calibration
2585 16:53:35.546075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 16:53:35.549196 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 16:53:35.555647 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2588 16:53:35.559475 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2589 16:53:35.562592 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 16:53:35.568935 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 16:53:35.572823 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 16:53:35.575856 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 16:53:35.582582 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2594 16:53:35.585659 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2595 16:53:35.589244 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2596 16:53:35.595790 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2597 16:53:35.598902 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 16:53:35.602625 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 16:53:35.609113 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 16:53:35.612390 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 16:53:35.615583 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
2602 16:53:35.619157 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2603 16:53:35.625678 1 1 0 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
2604 16:53:35.629318 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 16:53:35.632858 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 16:53:35.639333 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 16:53:35.642743 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 16:53:35.645759 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 16:53:35.652393 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 16:53:35.656230 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 16:53:35.659291 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2612 16:53:35.665767 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 16:53:35.669523 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 16:53:35.672715 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 16:53:35.679209 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 16:53:35.682837 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 16:53:35.686457 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 16:53:35.692731 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 16:53:35.695770 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 16:53:35.699187 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 16:53:35.705804 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 16:53:35.709676 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 16:53:35.712717 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 16:53:35.716023 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 16:53:35.723043 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 16:53:35.726165 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2627 16:53:35.729120 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2628 16:53:35.732625 Total UI for P1: 0, mck2ui 16
2629 16:53:35.736130 best dqsien dly found for B0: ( 1, 3, 28)
2630 16:53:35.742456 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 16:53:35.742713 Total UI for P1: 0, mck2ui 16
2632 16:53:35.749630 best dqsien dly found for B1: ( 1, 4, 0)
2633 16:53:35.752733 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2634 16:53:35.756055 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2635 16:53:35.756196
2636 16:53:35.759641 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2637 16:53:35.762755 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 16:53:35.766045 [Gating] SW calibration Done
2639 16:53:35.766182 ==
2640 16:53:35.769276 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 16:53:35.773060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 16:53:35.773190 ==
2643 16:53:35.776095 RX Vref Scan: 0
2644 16:53:35.776188
2645 16:53:35.776255 RX Vref 0 -> 0, step: 1
2646 16:53:35.776319
2647 16:53:35.779321 RX Delay -40 -> 252, step: 8
2648 16:53:35.782988 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2649 16:53:35.789712 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2650 16:53:35.792927 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2651 16:53:35.796584 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2652 16:53:35.799454 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2653 16:53:35.803133 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2654 16:53:35.806785 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2655 16:53:35.812924 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2656 16:53:35.816658 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2657 16:53:35.819992 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2658 16:53:35.823165 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2659 16:53:35.826388 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2660 16:53:35.833202 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2661 16:53:35.836945 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2662 16:53:35.839901 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2663 16:53:35.843493 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2664 16:53:35.843579 ==
2665 16:53:35.846375 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 16:53:35.850072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 16:53:35.853489 ==
2668 16:53:35.853604 DQS Delay:
2669 16:53:35.853679 DQS0 = 0, DQS1 = 0
2670 16:53:35.856523 DQM Delay:
2671 16:53:35.856635 DQM0 = 121, DQM1 = 113
2672 16:53:35.859933 DQ Delay:
2673 16:53:35.863012 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2674 16:53:35.866371 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2675 16:53:35.870090 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2676 16:53:35.873366 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2677 16:53:35.873455
2678 16:53:35.873548
2679 16:53:35.873654 ==
2680 16:53:35.876994 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 16:53:35.880215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 16:53:35.880341 ==
2683 16:53:35.880439
2684 16:53:35.883452
2685 16:53:35.883552 TX Vref Scan disable
2686 16:53:35.886501 == TX Byte 0 ==
2687 16:53:35.889635 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2688 16:53:35.893290 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2689 16:53:35.896438 == TX Byte 1 ==
2690 16:53:35.899666 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2691 16:53:35.903422 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2692 16:53:35.903528 ==
2693 16:53:35.906489 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 16:53:35.913096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 16:53:35.913206 ==
2696 16:53:35.923928 TX Vref=22, minBit 0, minWin=25, winSum=413
2697 16:53:35.927047 TX Vref=24, minBit 1, minWin=25, winSum=416
2698 16:53:35.930344 TX Vref=26, minBit 0, minWin=26, winSum=420
2699 16:53:35.934019 TX Vref=28, minBit 12, minWin=25, winSum=423
2700 16:53:35.937295 TX Vref=30, minBit 12, minWin=25, winSum=422
2701 16:53:35.943477 TX Vref=32, minBit 12, minWin=25, winSum=423
2702 16:53:35.947275 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 26
2703 16:53:35.947402
2704 16:53:35.950289 Final TX Range 1 Vref 26
2705 16:53:35.950384
2706 16:53:35.950453 ==
2707 16:53:35.953890 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 16:53:35.956764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 16:53:35.956872 ==
2710 16:53:35.960293
2711 16:53:35.960428
2712 16:53:35.960532 TX Vref Scan disable
2713 16:53:35.963922 == TX Byte 0 ==
2714 16:53:35.966681 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2715 16:53:35.970206 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2716 16:53:35.973896 == TX Byte 1 ==
2717 16:53:35.976842 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2718 16:53:35.980557 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2719 16:53:35.983825
2720 16:53:35.983919 [DATLAT]
2721 16:53:35.983987 Freq=1200, CH0 RK0
2722 16:53:35.984048
2723 16:53:35.986966 DATLAT Default: 0xd
2724 16:53:35.987051 0, 0xFFFF, sum = 0
2725 16:53:35.990112 1, 0xFFFF, sum = 0
2726 16:53:35.990198 2, 0xFFFF, sum = 0
2727 16:53:35.993855 3, 0xFFFF, sum = 0
2728 16:53:35.993951 4, 0xFFFF, sum = 0
2729 16:53:35.996953 5, 0xFFFF, sum = 0
2730 16:53:35.997042 6, 0xFFFF, sum = 0
2731 16:53:36.000158 7, 0xFFFF, sum = 0
2732 16:53:36.004008 8, 0xFFFF, sum = 0
2733 16:53:36.004158 9, 0xFFFF, sum = 0
2734 16:53:36.007097 10, 0xFFFF, sum = 0
2735 16:53:36.007185 11, 0xFFFF, sum = 0
2736 16:53:36.010071 12, 0x0, sum = 1
2737 16:53:36.010162 13, 0x0, sum = 2
2738 16:53:36.013544 14, 0x0, sum = 3
2739 16:53:36.013647 15, 0x0, sum = 4
2740 16:53:36.013718 best_step = 13
2741 16:53:36.013785
2742 16:53:36.016779 ==
2743 16:53:36.020383 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 16:53:36.023369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 16:53:36.023474 ==
2746 16:53:36.023545 RX Vref Scan: 1
2747 16:53:36.023608
2748 16:53:36.026863 Set Vref Range= 32 -> 127
2749 16:53:36.026989
2750 16:53:36.030697 RX Vref 32 -> 127, step: 1
2751 16:53:36.030800
2752 16:53:36.033992 RX Delay -13 -> 252, step: 4
2753 16:53:36.034093
2754 16:53:36.036898 Set Vref, RX VrefLevel [Byte0]: 32
2755 16:53:36.040148 [Byte1]: 32
2756 16:53:36.040252
2757 16:53:36.043976 Set Vref, RX VrefLevel [Byte0]: 33
2758 16:53:36.046973 [Byte1]: 33
2759 16:53:36.047068
2760 16:53:36.050769 Set Vref, RX VrefLevel [Byte0]: 34
2761 16:53:36.053951 [Byte1]: 34
2762 16:53:36.058103
2763 16:53:36.058198 Set Vref, RX VrefLevel [Byte0]: 35
2764 16:53:36.061074 [Byte1]: 35
2765 16:53:36.065752
2766 16:53:36.065836 Set Vref, RX VrefLevel [Byte0]: 36
2767 16:53:36.068782 [Byte1]: 36
2768 16:53:36.073683
2769 16:53:36.073766 Set Vref, RX VrefLevel [Byte0]: 37
2770 16:53:36.077059 [Byte1]: 37
2771 16:53:36.081680
2772 16:53:36.081805 Set Vref, RX VrefLevel [Byte0]: 38
2773 16:53:36.084556 [Byte1]: 38
2774 16:53:36.089487
2775 16:53:36.089628 Set Vref, RX VrefLevel [Byte0]: 39
2776 16:53:36.092762 [Byte1]: 39
2777 16:53:36.097081
2778 16:53:36.097262 Set Vref, RX VrefLevel [Byte0]: 40
2779 16:53:36.100854 [Byte1]: 40
2780 16:53:36.105343
2781 16:53:36.105436 Set Vref, RX VrefLevel [Byte0]: 41
2782 16:53:36.108623 [Byte1]: 41
2783 16:53:36.113198
2784 16:53:36.113313 Set Vref, RX VrefLevel [Byte0]: 42
2785 16:53:36.116411 [Byte1]: 42
2786 16:53:36.121034
2787 16:53:36.121150 Set Vref, RX VrefLevel [Byte0]: 43
2788 16:53:36.124129 [Byte1]: 43
2789 16:53:36.129119
2790 16:53:36.129258 Set Vref, RX VrefLevel [Byte0]: 44
2791 16:53:36.132089 [Byte1]: 44
2792 16:53:36.137197
2793 16:53:36.137316 Set Vref, RX VrefLevel [Byte0]: 45
2794 16:53:36.140137 [Byte1]: 45
2795 16:53:36.144413
2796 16:53:36.144519 Set Vref, RX VrefLevel [Byte0]: 46
2797 16:53:36.147757 [Byte1]: 46
2798 16:53:36.152655
2799 16:53:36.152759 Set Vref, RX VrefLevel [Byte0]: 47
2800 16:53:36.155658 [Byte1]: 47
2801 16:53:36.160193
2802 16:53:36.160337 Set Vref, RX VrefLevel [Byte0]: 48
2803 16:53:36.163790 [Byte1]: 48
2804 16:53:36.167972
2805 16:53:36.168045 Set Vref, RX VrefLevel [Byte0]: 49
2806 16:53:36.171542 [Byte1]: 49
2807 16:53:36.175917
2808 16:53:36.176017 Set Vref, RX VrefLevel [Byte0]: 50
2809 16:53:36.179319 [Byte1]: 50
2810 16:53:36.184173
2811 16:53:36.184273 Set Vref, RX VrefLevel [Byte0]: 51
2812 16:53:36.187530 [Byte1]: 51
2813 16:53:36.192037
2814 16:53:36.192121 Set Vref, RX VrefLevel [Byte0]: 52
2815 16:53:36.195421 [Byte1]: 52
2816 16:53:36.199861
2817 16:53:36.199945 Set Vref, RX VrefLevel [Byte0]: 53
2818 16:53:36.202999 [Byte1]: 53
2819 16:53:36.207394
2820 16:53:36.207478 Set Vref, RX VrefLevel [Byte0]: 54
2821 16:53:36.211205 [Byte1]: 54
2822 16:53:36.215782
2823 16:53:36.218999 Set Vref, RX VrefLevel [Byte0]: 55
2824 16:53:36.219084 [Byte1]: 55
2825 16:53:36.223338
2826 16:53:36.223422 Set Vref, RX VrefLevel [Byte0]: 56
2827 16:53:36.227042 [Byte1]: 56
2828 16:53:36.231340
2829 16:53:36.231424 Set Vref, RX VrefLevel [Byte0]: 57
2830 16:53:36.234466 [Byte1]: 57
2831 16:53:36.239385
2832 16:53:36.239471 Set Vref, RX VrefLevel [Byte0]: 58
2833 16:53:36.242837 [Byte1]: 58
2834 16:53:36.247106
2835 16:53:36.247190 Set Vref, RX VrefLevel [Byte0]: 59
2836 16:53:36.250221 [Byte1]: 59
2837 16:53:36.255133
2838 16:53:36.255217 Set Vref, RX VrefLevel [Byte0]: 60
2839 16:53:36.258333 [Byte1]: 60
2840 16:53:36.262770
2841 16:53:36.262854 Set Vref, RX VrefLevel [Byte0]: 61
2842 16:53:36.265998 [Byte1]: 61
2843 16:53:36.270865
2844 16:53:36.270948 Set Vref, RX VrefLevel [Byte0]: 62
2845 16:53:36.274205 [Byte1]: 62
2846 16:53:36.278482
2847 16:53:36.278566 Set Vref, RX VrefLevel [Byte0]: 63
2848 16:53:36.282203 [Byte1]: 63
2849 16:53:36.286361
2850 16:53:36.286516 Set Vref, RX VrefLevel [Byte0]: 64
2851 16:53:36.290047 [Byte1]: 64
2852 16:53:36.294757
2853 16:53:36.294841 Set Vref, RX VrefLevel [Byte0]: 65
2854 16:53:36.297650 [Byte1]: 65
2855 16:53:36.302594
2856 16:53:36.302679 Set Vref, RX VrefLevel [Byte0]: 66
2857 16:53:36.305889 [Byte1]: 66
2858 16:53:36.310116
2859 16:53:36.310216 Set Vref, RX VrefLevel [Byte0]: 67
2860 16:53:36.313405 [Byte1]: 67
2861 16:53:36.317982
2862 16:53:36.318065 Set Vref, RX VrefLevel [Byte0]: 68
2863 16:53:36.321164 [Byte1]: 68
2864 16:53:36.326164
2865 16:53:36.326269 Set Vref, RX VrefLevel [Byte0]: 69
2866 16:53:36.329378 [Byte1]: 69
2867 16:53:36.334289
2868 16:53:36.334372 Final RX Vref Byte 0 = 57 to rank0
2869 16:53:36.337393 Final RX Vref Byte 1 = 51 to rank0
2870 16:53:36.340529 Final RX Vref Byte 0 = 57 to rank1
2871 16:53:36.343703 Final RX Vref Byte 1 = 51 to rank1==
2872 16:53:36.347292 Dram Type= 6, Freq= 0, CH_0, rank 0
2873 16:53:36.353953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 16:53:36.354097 ==
2875 16:53:36.354168 DQS Delay:
2876 16:53:36.354232 DQS0 = 0, DQS1 = 0
2877 16:53:36.357089 DQM Delay:
2878 16:53:36.357161 DQM0 = 120, DQM1 = 112
2879 16:53:36.360814 DQ Delay:
2880 16:53:36.363920 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2881 16:53:36.367073 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2882 16:53:36.370886 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2883 16:53:36.373950 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2884 16:53:36.374024
2885 16:53:36.374095
2886 16:53:36.380596 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2887 16:53:36.384006 CH0 RK0: MR19=404, MR18=130C
2888 16:53:36.390803 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2889 16:53:36.390887
2890 16:53:36.393927 ----->DramcWriteLeveling(PI) begin...
2891 16:53:36.394002 ==
2892 16:53:36.397370 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 16:53:36.400358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 16:53:36.403823 ==
2895 16:53:36.403901 Write leveling (Byte 0): 34 => 34
2896 16:53:36.407310 Write leveling (Byte 1): 29 => 29
2897 16:53:36.411000 DramcWriteLeveling(PI) end<-----
2898 16:53:36.411078
2899 16:53:36.411144 ==
2900 16:53:36.414040 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 16:53:36.420822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 16:53:36.420928 ==
2903 16:53:36.421022 [Gating] SW mode calibration
2904 16:53:36.430994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2905 16:53:36.434214 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2906 16:53:36.437410 0 15 0 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (0 0)
2907 16:53:36.444106 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 16:53:36.447927 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 16:53:36.450978 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 16:53:36.457782 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 16:53:36.460870 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 16:53:36.464452 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 16:53:36.471245 0 15 28 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 1)
2914 16:53:36.474478 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 16:53:36.477519 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 16:53:36.484487 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 16:53:36.487371 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 16:53:36.490848 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 16:53:36.497321 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 16:53:36.500867 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2921 16:53:36.504050 1 0 28 | B1->B0 | 3636 3939 | 0 0 | (1 1) (0 0)
2922 16:53:36.507547 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2923 16:53:36.514330 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 16:53:36.517768 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 16:53:36.521338 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 16:53:36.527612 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 16:53:36.530706 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 16:53:36.534478 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2929 16:53:36.540954 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2930 16:53:36.544148 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2931 16:53:36.547737 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 16:53:36.554113 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 16:53:36.557796 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 16:53:36.560876 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 16:53:36.567680 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 16:53:36.570816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 16:53:36.574526 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 16:53:36.580849 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 16:53:36.584042 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 16:53:36.587902 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 16:53:36.594075 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 16:53:36.597543 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 16:53:36.601082 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 16:53:36.604077 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 16:53:36.611004 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2946 16:53:36.614632 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 16:53:36.617481 Total UI for P1: 0, mck2ui 16
2948 16:53:36.620964 best dqsien dly found for B0: ( 1, 3, 28)
2949 16:53:36.624353 Total UI for P1: 0, mck2ui 16
2950 16:53:36.627727 best dqsien dly found for B1: ( 1, 3, 28)
2951 16:53:36.630845 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2952 16:53:36.634552 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2953 16:53:36.634638
2954 16:53:36.637756 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2955 16:53:36.641422 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2956 16:53:36.644144 [Gating] SW calibration Done
2957 16:53:36.644266 ==
2958 16:53:36.647745 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 16:53:36.654214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 16:53:36.654315 ==
2961 16:53:36.654386 RX Vref Scan: 0
2962 16:53:36.654452
2963 16:53:36.657963 RX Vref 0 -> 0, step: 1
2964 16:53:36.658037
2965 16:53:36.661044 RX Delay -40 -> 252, step: 8
2966 16:53:36.664164 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2967 16:53:36.667823 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2968 16:53:36.670873 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2969 16:53:36.674431 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2970 16:53:36.680684 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2971 16:53:36.684438 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2972 16:53:36.687583 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2973 16:53:36.690850 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2974 16:53:36.694017 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2975 16:53:36.697760 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2976 16:53:36.704466 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2977 16:53:36.707419 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2978 16:53:36.711097 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2979 16:53:36.714139 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2980 16:53:36.721095 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2981 16:53:36.724623 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2982 16:53:36.724713 ==
2983 16:53:36.727580 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 16:53:36.731296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 16:53:36.731450 ==
2986 16:53:36.734211 DQS Delay:
2987 16:53:36.734296 DQS0 = 0, DQS1 = 0
2988 16:53:36.734363 DQM Delay:
2989 16:53:36.737891 DQM0 = 122, DQM1 = 112
2990 16:53:36.738014 DQ Delay:
2991 16:53:36.741190 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2992 16:53:36.744327 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2993 16:53:36.747484 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2994 16:53:36.750831 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2995 16:53:36.753982
2996 16:53:36.754065
2997 16:53:36.754133 ==
2998 16:53:36.757706 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 16:53:36.761074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 16:53:36.761156 ==
3001 16:53:36.761224
3002 16:53:36.761286
3003 16:53:36.764531 TX Vref Scan disable
3004 16:53:36.764614 == TX Byte 0 ==
3005 16:53:36.770828 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3006 16:53:36.774419 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3007 16:53:36.774503 == TX Byte 1 ==
3008 16:53:36.781017 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3009 16:53:36.784150 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3010 16:53:36.784228 ==
3011 16:53:36.787403 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 16:53:36.791006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 16:53:36.791088 ==
3014 16:53:36.803564 TX Vref=22, minBit 3, minWin=25, winSum=414
3015 16:53:36.807339 TX Vref=24, minBit 1, minWin=25, winSum=416
3016 16:53:36.810264 TX Vref=26, minBit 0, minWin=26, winSum=423
3017 16:53:36.813719 TX Vref=28, minBit 1, minWin=26, winSum=427
3018 16:53:36.817273 TX Vref=30, minBit 12, minWin=25, winSum=427
3019 16:53:36.824015 TX Vref=32, minBit 5, minWin=25, winSum=424
3020 16:53:36.827292 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3021 16:53:36.827367
3022 16:53:36.830258 Final TX Range 1 Vref 28
3023 16:53:36.830334
3024 16:53:36.830397 ==
3025 16:53:36.833656 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 16:53:36.837271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 16:53:36.837389 ==
3028 16:53:36.837487
3029 16:53:36.840755
3030 16:53:36.840844 TX Vref Scan disable
3031 16:53:36.843952 == TX Byte 0 ==
3032 16:53:36.847006 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3033 16:53:36.850189 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3034 16:53:36.854018 == TX Byte 1 ==
3035 16:53:36.857312 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3036 16:53:36.860532 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3037 16:53:36.860613
3038 16:53:36.863771 [DATLAT]
3039 16:53:36.863857 Freq=1200, CH0 RK1
3040 16:53:36.863924
3041 16:53:36.867365 DATLAT Default: 0xd
3042 16:53:36.867459 0, 0xFFFF, sum = 0
3043 16:53:36.870290 1, 0xFFFF, sum = 0
3044 16:53:36.870373 2, 0xFFFF, sum = 0
3045 16:53:36.873834 3, 0xFFFF, sum = 0
3046 16:53:36.873917 4, 0xFFFF, sum = 0
3047 16:53:36.877068 5, 0xFFFF, sum = 0
3048 16:53:36.877147 6, 0xFFFF, sum = 0
3049 16:53:36.880736 7, 0xFFFF, sum = 0
3050 16:53:36.883700 8, 0xFFFF, sum = 0
3051 16:53:36.883793 9, 0xFFFF, sum = 0
3052 16:53:36.887442 10, 0xFFFF, sum = 0
3053 16:53:36.887559 11, 0xFFFF, sum = 0
3054 16:53:36.890793 12, 0x0, sum = 1
3055 16:53:36.890909 13, 0x0, sum = 2
3056 16:53:36.891008 14, 0x0, sum = 3
3057 16:53:36.894151 15, 0x0, sum = 4
3058 16:53:36.894230 best_step = 13
3059 16:53:36.894295
3060 16:53:36.897234 ==
3061 16:53:36.897310 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 16:53:36.903621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 16:53:36.903710 ==
3064 16:53:36.903790 RX Vref Scan: 0
3065 16:53:36.903852
3066 16:53:36.907187 RX Vref 0 -> 0, step: 1
3067 16:53:36.907272
3068 16:53:36.910373 RX Delay -13 -> 252, step: 4
3069 16:53:36.914100 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3070 16:53:36.917173 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3071 16:53:36.924302 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3072 16:53:36.927315 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3073 16:53:36.930645 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3074 16:53:36.934281 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3075 16:53:36.937273 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3076 16:53:36.943903 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3077 16:53:36.947506 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3078 16:53:36.950707 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3079 16:53:36.954387 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3080 16:53:36.957770 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3081 16:53:36.964050 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3082 16:53:36.967320 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3083 16:53:36.970998 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3084 16:53:36.974595 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3085 16:53:36.974682 ==
3086 16:53:36.977526 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 16:53:36.981174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 16:53:36.984405 ==
3089 16:53:36.984526 DQS Delay:
3090 16:53:36.984601 DQS0 = 0, DQS1 = 0
3091 16:53:36.988102 DQM Delay:
3092 16:53:36.988226 DQM0 = 121, DQM1 = 111
3093 16:53:36.991159 DQ Delay:
3094 16:53:36.994879 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3095 16:53:36.997757 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3096 16:53:37.000990 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3097 16:53:37.004685 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =120
3098 16:53:37.004772
3099 16:53:37.004839
3100 16:53:37.010901 [DQSOSCAuto] RK1, (LSB)MR18= 0xfef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3101 16:53:37.014550 CH0 RK1: MR19=403, MR18=FEF
3102 16:53:37.021149 CH0_RK1: MR19=0x403, MR18=0xFEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3103 16:53:37.024678 [RxdqsGatingPostProcess] freq 1200
3104 16:53:37.027773 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3105 16:53:37.031231 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 16:53:37.034813 best DQS1 dly(2T, 0.5T) = (0, 12)
3107 16:53:37.037686 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 16:53:37.041323 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3109 16:53:37.044911 best DQS0 dly(2T, 0.5T) = (0, 11)
3110 16:53:37.048092 best DQS1 dly(2T, 0.5T) = (0, 11)
3111 16:53:37.051198 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3112 16:53:37.054554 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3113 16:53:37.057814 Pre-setting of DQS Precalculation
3114 16:53:37.061022 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3115 16:53:37.061108 ==
3116 16:53:37.064275 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 16:53:37.071212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 16:53:37.071299 ==
3119 16:53:37.075067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 16:53:37.081105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 16:53:37.090013 [CA 0] Center 37 (7~68) winsize 62
3122 16:53:37.093708 [CA 1] Center 37 (7~68) winsize 62
3123 16:53:37.096733 [CA 2] Center 35 (5~65) winsize 61
3124 16:53:37.100402 [CA 3] Center 34 (4~65) winsize 62
3125 16:53:37.103273 [CA 4] Center 34 (5~64) winsize 60
3126 16:53:37.107238 [CA 5] Center 33 (3~63) winsize 61
3127 16:53:37.107337
3128 16:53:37.110257 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3129 16:53:37.110357
3130 16:53:37.113460 [CATrainingPosCal] consider 1 rank data
3131 16:53:37.116935 u2DelayCellTimex100 = 270/100 ps
3132 16:53:37.119971 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 16:53:37.123697 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 16:53:37.129861 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3135 16:53:37.133668 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3136 16:53:37.137210 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3137 16:53:37.140268 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3138 16:53:37.140351
3139 16:53:37.143622 CA PerBit enable=1, Macro0, CA PI delay=33
3140 16:53:37.143737
3141 16:53:37.146715 [CBTSetCACLKResult] CA Dly = 33
3142 16:53:37.146799 CS Dly: 7 (0~38)
3143 16:53:37.146867 ==
3144 16:53:37.150206 Dram Type= 6, Freq= 0, CH_1, rank 1
3145 16:53:37.156740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 16:53:37.156826 ==
3147 16:53:37.160219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3148 16:53:37.166715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3149 16:53:37.175671 [CA 0] Center 37 (7~68) winsize 62
3150 16:53:37.179450 [CA 1] Center 37 (7~68) winsize 62
3151 16:53:37.182494 [CA 2] Center 35 (5~65) winsize 61
3152 16:53:37.185708 [CA 3] Center 34 (4~65) winsize 62
3153 16:53:37.189251 [CA 4] Center 35 (5~65) winsize 61
3154 16:53:37.192315 [CA 5] Center 34 (4~64) winsize 61
3155 16:53:37.192424
3156 16:53:37.195472 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3157 16:53:37.195579
3158 16:53:37.199217 [CATrainingPosCal] consider 2 rank data
3159 16:53:37.202380 u2DelayCellTimex100 = 270/100 ps
3160 16:53:37.206038 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3161 16:53:37.208908 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3162 16:53:37.216042 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3163 16:53:37.218955 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3164 16:53:37.222683 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3165 16:53:37.225642 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3166 16:53:37.225721
3167 16:53:37.228981 CA PerBit enable=1, Macro0, CA PI delay=33
3168 16:53:37.229082
3169 16:53:37.232743 [CBTSetCACLKResult] CA Dly = 33
3170 16:53:37.232822 CS Dly: 8 (0~40)
3171 16:53:37.232888
3172 16:53:37.235983 ----->DramcWriteLeveling(PI) begin...
3173 16:53:37.236084 ==
3174 16:53:37.239140 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 16:53:37.246260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 16:53:37.246382 ==
3177 16:53:37.249576 Write leveling (Byte 0): 27 => 27
3178 16:53:37.252727 Write leveling (Byte 1): 27 => 27
3179 16:53:37.252827 DramcWriteLeveling(PI) end<-----
3180 16:53:37.252928
3181 16:53:37.255956 ==
3182 16:53:37.259354 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 16:53:37.262392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 16:53:37.262498 ==
3185 16:53:37.265868 [Gating] SW mode calibration
3186 16:53:37.272312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3187 16:53:37.276179 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3188 16:53:37.282581 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3189 16:53:37.286225 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 16:53:37.289412 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 16:53:37.296172 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 16:53:37.299148 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 16:53:37.302883 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 16:53:37.309002 0 15 24 | B1->B0 | 3232 2e2e | 0 0 | (0 1) (0 1)
3195 16:53:37.312538 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3196 16:53:37.316128 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 16:53:37.322510 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 16:53:37.326206 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 16:53:37.329294 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 16:53:37.332406 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 16:53:37.339424 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3202 16:53:37.342656 1 0 24 | B1->B0 | 3131 3e3e | 0 1 | (0 0) (0 0)
3203 16:53:37.345859 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 16:53:37.352530 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 16:53:37.355991 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 16:53:37.359515 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 16:53:37.365837 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 16:53:37.368968 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 16:53:37.372544 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 16:53:37.379368 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3211 16:53:37.382710 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3212 16:53:37.385824 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 16:53:37.392835 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 16:53:37.395995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 16:53:37.399098 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 16:53:37.405867 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 16:53:37.409030 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 16:53:37.412669 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 16:53:37.419053 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 16:53:37.422493 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 16:53:37.425682 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 16:53:37.432385 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 16:53:37.435556 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 16:53:37.439449 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 16:53:37.442534 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 16:53:37.448967 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3227 16:53:37.452488 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 16:53:37.455608 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 16:53:37.459056 Total UI for P1: 0, mck2ui 16
3230 16:53:37.462515 best dqsien dly found for B0: ( 1, 3, 26)
3231 16:53:37.465657 Total UI for P1: 0, mck2ui 16
3232 16:53:37.469204 best dqsien dly found for B1: ( 1, 3, 26)
3233 16:53:37.472708 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3234 16:53:37.475684 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3235 16:53:37.475772
3236 16:53:37.482878 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3237 16:53:37.486092 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3238 16:53:37.489276 [Gating] SW calibration Done
3239 16:53:37.489362 ==
3240 16:53:37.492956 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 16:53:37.496179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 16:53:37.496266 ==
3243 16:53:37.496335 RX Vref Scan: 0
3244 16:53:37.496398
3245 16:53:37.499341 RX Vref 0 -> 0, step: 1
3246 16:53:37.499426
3247 16:53:37.502512 RX Delay -40 -> 252, step: 8
3248 16:53:37.506281 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3249 16:53:37.509229 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3250 16:53:37.513008 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3251 16:53:37.519590 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3252 16:53:37.522763 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3253 16:53:37.526187 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3254 16:53:37.529698 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3255 16:53:37.532656 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3256 16:53:37.539519 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3257 16:53:37.542728 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3258 16:53:37.545980 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3259 16:53:37.549221 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3260 16:53:37.552419 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3261 16:53:37.559224 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3262 16:53:37.562946 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3263 16:53:37.565996 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3264 16:53:37.566097 ==
3265 16:53:37.569537 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 16:53:37.572574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 16:53:37.572660 ==
3268 16:53:37.576193 DQS Delay:
3269 16:53:37.576278 DQS0 = 0, DQS1 = 0
3270 16:53:37.579712 DQM Delay:
3271 16:53:37.579798 DQM0 = 120, DQM1 = 116
3272 16:53:37.582743 DQ Delay:
3273 16:53:37.586239 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3274 16:53:37.589521 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3275 16:53:37.592880 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3276 16:53:37.596418 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3277 16:53:37.596504
3278 16:53:37.596572
3279 16:53:37.596636 ==
3280 16:53:37.599698 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 16:53:37.602804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 16:53:37.602928 ==
3283 16:53:37.603039
3284 16:53:37.603141
3285 16:53:37.605993 TX Vref Scan disable
3286 16:53:37.609125 == TX Byte 0 ==
3287 16:53:37.612758 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 16:53:37.615777 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 16:53:37.619516 == TX Byte 1 ==
3290 16:53:37.622775 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3291 16:53:37.626259 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3292 16:53:37.626379 ==
3293 16:53:37.629235 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 16:53:37.635923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 16:53:37.636035 ==
3296 16:53:37.646124 TX Vref=22, minBit 9, minWin=24, winSum=410
3297 16:53:37.649274 TX Vref=24, minBit 0, minWin=25, winSum=417
3298 16:53:37.652503 TX Vref=26, minBit 1, minWin=25, winSum=420
3299 16:53:37.655702 TX Vref=28, minBit 1, minWin=26, winSum=426
3300 16:53:37.658849 TX Vref=30, minBit 1, minWin=26, winSum=427
3301 16:53:37.665805 TX Vref=32, minBit 10, minWin=26, winSum=429
3302 16:53:37.669012 [TxChooseVref] Worse bit 10, Min win 26, Win sum 429, Final Vref 32
3303 16:53:37.669121
3304 16:53:37.672550 Final TX Range 1 Vref 32
3305 16:53:37.672657
3306 16:53:37.672753 ==
3307 16:53:37.675854 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 16:53:37.678872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 16:53:37.682451 ==
3310 16:53:37.682530
3311 16:53:37.682599
3312 16:53:37.682662 TX Vref Scan disable
3313 16:53:37.685386 == TX Byte 0 ==
3314 16:53:37.688802 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 16:53:37.695808 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 16:53:37.695923 == TX Byte 1 ==
3317 16:53:37.698401 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3318 16:53:37.705255 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3319 16:53:37.705341
3320 16:53:37.705430 [DATLAT]
3321 16:53:37.705532 Freq=1200, CH1 RK0
3322 16:53:37.705624
3323 16:53:37.708465 DATLAT Default: 0xd
3324 16:53:37.712344 0, 0xFFFF, sum = 0
3325 16:53:37.712430 1, 0xFFFF, sum = 0
3326 16:53:37.715451 2, 0xFFFF, sum = 0
3327 16:53:37.715535 3, 0xFFFF, sum = 0
3328 16:53:37.718613 4, 0xFFFF, sum = 0
3329 16:53:37.718704 5, 0xFFFF, sum = 0
3330 16:53:37.722115 6, 0xFFFF, sum = 0
3331 16:53:37.722205 7, 0xFFFF, sum = 0
3332 16:53:37.725317 8, 0xFFFF, sum = 0
3333 16:53:37.725404 9, 0xFFFF, sum = 0
3334 16:53:37.729005 10, 0xFFFF, sum = 0
3335 16:53:37.729101 11, 0xFFFF, sum = 0
3336 16:53:37.732102 12, 0x0, sum = 1
3337 16:53:37.732189 13, 0x0, sum = 2
3338 16:53:37.735536 14, 0x0, sum = 3
3339 16:53:37.735623 15, 0x0, sum = 4
3340 16:53:37.735692 best_step = 13
3341 16:53:37.738739
3342 16:53:37.738824 ==
3343 16:53:37.742152 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 16:53:37.745664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 16:53:37.745751 ==
3346 16:53:37.745818 RX Vref Scan: 1
3347 16:53:37.745881
3348 16:53:37.748524 Set Vref Range= 32 -> 127
3349 16:53:37.748634
3350 16:53:37.752399 RX Vref 32 -> 127, step: 1
3351 16:53:37.752510
3352 16:53:37.755520 RX Delay -5 -> 252, step: 4
3353 16:53:37.755605
3354 16:53:37.758710 Set Vref, RX VrefLevel [Byte0]: 32
3355 16:53:37.762031 [Byte1]: 32
3356 16:53:37.762118
3357 16:53:37.765762 Set Vref, RX VrefLevel [Byte0]: 33
3358 16:53:37.768934 [Byte1]: 33
3359 16:53:37.769019
3360 16:53:37.772151 Set Vref, RX VrefLevel [Byte0]: 34
3361 16:53:37.775775 [Byte1]: 34
3362 16:53:37.779934
3363 16:53:37.780054 Set Vref, RX VrefLevel [Byte0]: 35
3364 16:53:37.782881 [Byte1]: 35
3365 16:53:37.787575
3366 16:53:37.787683 Set Vref, RX VrefLevel [Byte0]: 36
3367 16:53:37.790978 [Byte1]: 36
3368 16:53:37.795733
3369 16:53:37.795843 Set Vref, RX VrefLevel [Byte0]: 37
3370 16:53:37.798749 [Byte1]: 37
3371 16:53:37.803250
3372 16:53:37.803332 Set Vref, RX VrefLevel [Byte0]: 38
3373 16:53:37.806870 [Byte1]: 38
3374 16:53:37.811344
3375 16:53:37.811451 Set Vref, RX VrefLevel [Byte0]: 39
3376 16:53:37.814506 [Byte1]: 39
3377 16:53:37.819108
3378 16:53:37.819214 Set Vref, RX VrefLevel [Byte0]: 40
3379 16:53:37.822260 [Byte1]: 40
3380 16:53:37.827124
3381 16:53:37.827228 Set Vref, RX VrefLevel [Byte0]: 41
3382 16:53:37.830229 [Byte1]: 41
3383 16:53:37.834522
3384 16:53:37.834598 Set Vref, RX VrefLevel [Byte0]: 42
3385 16:53:37.838114 [Byte1]: 42
3386 16:53:37.842818
3387 16:53:37.842936 Set Vref, RX VrefLevel [Byte0]: 43
3388 16:53:37.845853 [Byte1]: 43
3389 16:53:37.850388
3390 16:53:37.850499 Set Vref, RX VrefLevel [Byte0]: 44
3391 16:53:37.854058 [Byte1]: 44
3392 16:53:37.858460
3393 16:53:37.858565 Set Vref, RX VrefLevel [Byte0]: 45
3394 16:53:37.861609 [Byte1]: 45
3395 16:53:37.866106
3396 16:53:37.866210 Set Vref, RX VrefLevel [Byte0]: 46
3397 16:53:37.869181 [Byte1]: 46
3398 16:53:37.873741
3399 16:53:37.873844 Set Vref, RX VrefLevel [Byte0]: 47
3400 16:53:37.877363 [Byte1]: 47
3401 16:53:37.881505
3402 16:53:37.881625 Set Vref, RX VrefLevel [Byte0]: 48
3403 16:53:37.885167 [Byte1]: 48
3404 16:53:37.889773
3405 16:53:37.889854 Set Vref, RX VrefLevel [Byte0]: 49
3406 16:53:37.893323 [Byte1]: 49
3407 16:53:37.897505
3408 16:53:37.897622 Set Vref, RX VrefLevel [Byte0]: 50
3409 16:53:37.900926 [Byte1]: 50
3410 16:53:37.905246
3411 16:53:37.905361 Set Vref, RX VrefLevel [Byte0]: 51
3412 16:53:37.908383 [Byte1]: 51
3413 16:53:37.913498
3414 16:53:37.913591 Set Vref, RX VrefLevel [Byte0]: 52
3415 16:53:37.916768 [Byte1]: 52
3416 16:53:37.921187
3417 16:53:37.921272 Set Vref, RX VrefLevel [Byte0]: 53
3418 16:53:37.924443 [Byte1]: 53
3419 16:53:37.928790
3420 16:53:37.928876 Set Vref, RX VrefLevel [Byte0]: 54
3421 16:53:37.932227 [Byte1]: 54
3422 16:53:37.937129
3423 16:53:37.937214 Set Vref, RX VrefLevel [Byte0]: 55
3424 16:53:37.940270 [Byte1]: 55
3425 16:53:37.944522
3426 16:53:37.944635 Set Vref, RX VrefLevel [Byte0]: 56
3427 16:53:37.948065 [Byte1]: 56
3428 16:53:37.952668
3429 16:53:37.952779 Set Vref, RX VrefLevel [Byte0]: 57
3430 16:53:37.955712 [Byte1]: 57
3431 16:53:37.960260
3432 16:53:37.960348 Set Vref, RX VrefLevel [Byte0]: 58
3433 16:53:37.963383 [Byte1]: 58
3434 16:53:37.968509
3435 16:53:37.968596 Set Vref, RX VrefLevel [Byte0]: 59
3436 16:53:37.971581 [Byte1]: 59
3437 16:53:37.976201
3438 16:53:37.976328 Set Vref, RX VrefLevel [Byte0]: 60
3439 16:53:37.979330 [Byte1]: 60
3440 16:53:37.984370
3441 16:53:37.984454 Set Vref, RX VrefLevel [Byte0]: 61
3442 16:53:37.987170 [Byte1]: 61
3443 16:53:37.991959
3444 16:53:37.992040 Set Vref, RX VrefLevel [Byte0]: 62
3445 16:53:37.994794 [Byte1]: 62
3446 16:53:37.999628
3447 16:53:37.999727 Set Vref, RX VrefLevel [Byte0]: 63
3448 16:53:38.002719 [Byte1]: 63
3449 16:53:38.007194
3450 16:53:38.007370 Set Vref, RX VrefLevel [Byte0]: 64
3451 16:53:38.010755 [Byte1]: 64
3452 16:53:38.015618
3453 16:53:38.015700 Set Vref, RX VrefLevel [Byte0]: 65
3454 16:53:38.018797 [Byte1]: 65
3455 16:53:38.023322
3456 16:53:38.023405 Set Vref, RX VrefLevel [Byte0]: 66
3457 16:53:38.026362 [Byte1]: 66
3458 16:53:38.030705
3459 16:53:38.030809 Set Vref, RX VrefLevel [Byte0]: 67
3460 16:53:38.034020 [Byte1]: 67
3461 16:53:38.038953
3462 16:53:38.039075 Set Vref, RX VrefLevel [Byte0]: 68
3463 16:53:38.041843 [Byte1]: 68
3464 16:53:38.046871
3465 16:53:38.046983 Set Vref, RX VrefLevel [Byte0]: 69
3466 16:53:38.049986 [Byte1]: 69
3467 16:53:38.054985
3468 16:53:38.055063 Final RX Vref Byte 0 = 53 to rank0
3469 16:53:38.057941 Final RX Vref Byte 1 = 50 to rank0
3470 16:53:38.060877 Final RX Vref Byte 0 = 53 to rank1
3471 16:53:38.064444 Final RX Vref Byte 1 = 50 to rank1==
3472 16:53:38.068188 Dram Type= 6, Freq= 0, CH_1, rank 0
3473 16:53:38.074410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 16:53:38.074500 ==
3475 16:53:38.074570 DQS Delay:
3476 16:53:38.074635 DQS0 = 0, DQS1 = 0
3477 16:53:38.077541 DQM Delay:
3478 16:53:38.077616 DQM0 = 120, DQM1 = 117
3479 16:53:38.080750 DQ Delay:
3480 16:53:38.084630 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3481 16:53:38.087720 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3482 16:53:38.090829 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110
3483 16:53:38.094512 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3484 16:53:38.094593
3485 16:53:38.094659
3486 16:53:38.104086 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3487 16:53:38.104180 CH1 RK0: MR19=404, MR18=114
3488 16:53:38.111283 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3489 16:53:38.111366
3490 16:53:38.114170 ----->DramcWriteLeveling(PI) begin...
3491 16:53:38.114300 ==
3492 16:53:38.117908 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 16:53:38.120814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 16:53:38.124515 ==
3495 16:53:38.124626 Write leveling (Byte 0): 25 => 25
3496 16:53:38.127736 Write leveling (Byte 1): 29 => 29
3497 16:53:38.130945 DramcWriteLeveling(PI) end<-----
3498 16:53:38.131052
3499 16:53:38.131148 ==
3500 16:53:38.134264 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 16:53:38.140949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 16:53:38.141046 ==
3503 16:53:38.141117 [Gating] SW mode calibration
3504 16:53:38.151097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3505 16:53:38.154365 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3506 16:53:38.157712 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 16:53:38.164501 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 16:53:38.167468 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 16:53:38.171214 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 16:53:38.177665 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 16:53:38.180760 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3512 16:53:38.184765 0 15 24 | B1->B0 | 2d2d 3434 | 0 0 | (1 0) (0 0)
3513 16:53:38.190907 0 15 28 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 0)
3514 16:53:38.194081 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 16:53:38.197544 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 16:53:38.204188 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 16:53:38.208016 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 16:53:38.210863 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 16:53:38.217440 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3520 16:53:38.221542 1 0 24 | B1->B0 | 4040 2929 | 0 0 | (0 0) (0 0)
3521 16:53:38.224707 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 16:53:38.230818 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 16:53:38.234749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 16:53:38.237832 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 16:53:38.240878 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 16:53:38.247719 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 16:53:38.250910 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 16:53:38.254089 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3529 16:53:38.260809 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3530 16:53:38.264043 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 16:53:38.267809 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 16:53:38.274509 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 16:53:38.277306 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 16:53:38.280731 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 16:53:38.287674 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 16:53:38.290854 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 16:53:38.294030 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 16:53:38.300837 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 16:53:38.304460 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 16:53:38.307389 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 16:53:38.313857 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 16:53:38.317412 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 16:53:38.320901 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3544 16:53:38.327387 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3545 16:53:38.331104 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3546 16:53:38.334073 Total UI for P1: 0, mck2ui 16
3547 16:53:38.337125 best dqsien dly found for B1: ( 1, 3, 22)
3548 16:53:38.340400 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 16:53:38.344229 Total UI for P1: 0, mck2ui 16
3550 16:53:38.347537 best dqsien dly found for B0: ( 1, 3, 26)
3551 16:53:38.350669 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3552 16:53:38.353873 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3553 16:53:38.353980
3554 16:53:38.357438 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3555 16:53:38.363684 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3556 16:53:38.363787 [Gating] SW calibration Done
3557 16:53:38.367308 ==
3558 16:53:38.367389 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 16:53:38.373930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 16:53:38.374008 ==
3561 16:53:38.374072 RX Vref Scan: 0
3562 16:53:38.374134
3563 16:53:38.377198 RX Vref 0 -> 0, step: 1
3564 16:53:38.377269
3565 16:53:38.380733 RX Delay -40 -> 252, step: 8
3566 16:53:38.383641 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3567 16:53:38.387183 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3568 16:53:38.390930 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3569 16:53:38.397421 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3570 16:53:38.400492 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3571 16:53:38.403789 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3572 16:53:38.407592 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3573 16:53:38.410427 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3574 16:53:38.416966 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3575 16:53:38.420516 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3576 16:53:38.423439 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3577 16:53:38.427005 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3578 16:53:38.430477 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3579 16:53:38.437290 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3580 16:53:38.440158 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3581 16:53:38.444040 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3582 16:53:38.444130 ==
3583 16:53:38.447241 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 16:53:38.450373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 16:53:38.453355 ==
3586 16:53:38.453470 DQS Delay:
3587 16:53:38.453569 DQS0 = 0, DQS1 = 0
3588 16:53:38.457213 DQM Delay:
3589 16:53:38.457316 DQM0 = 121, DQM1 = 118
3590 16:53:38.460396 DQ Delay:
3591 16:53:38.463558 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3592 16:53:38.466674 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3593 16:53:38.470391 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3594 16:53:38.473458 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3595 16:53:38.473562
3596 16:53:38.473631
3597 16:53:38.473694 ==
3598 16:53:38.476805 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 16:53:38.479872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 16:53:38.479961 ==
3601 16:53:38.480030
3602 16:53:38.483468
3603 16:53:38.483553 TX Vref Scan disable
3604 16:53:38.486463 == TX Byte 0 ==
3605 16:53:38.489899 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3606 16:53:38.493200 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3607 16:53:38.496949 == TX Byte 1 ==
3608 16:53:38.500062 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3609 16:53:38.503315 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3610 16:53:38.503420 ==
3611 16:53:38.506563 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 16:53:38.513501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 16:53:38.513620 ==
3614 16:53:38.523556 TX Vref=22, minBit 1, minWin=25, winSum=417
3615 16:53:38.527235 TX Vref=24, minBit 2, minWin=26, winSum=426
3616 16:53:38.530802 TX Vref=26, minBit 10, minWin=25, winSum=428
3617 16:53:38.533735 TX Vref=28, minBit 1, minWin=26, winSum=431
3618 16:53:38.537092 TX Vref=30, minBit 9, minWin=26, winSum=437
3619 16:53:38.543755 TX Vref=32, minBit 9, minWin=26, winSum=435
3620 16:53:38.547081 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3621 16:53:38.547168
3622 16:53:38.550655 Final TX Range 1 Vref 30
3623 16:53:38.550750
3624 16:53:38.550849 ==
3625 16:53:38.553809 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 16:53:38.556944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 16:53:38.560174 ==
3628 16:53:38.560259
3629 16:53:38.560328
3630 16:53:38.560391 TX Vref Scan disable
3631 16:53:38.563914 == TX Byte 0 ==
3632 16:53:38.566989 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3633 16:53:38.570165 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3634 16:53:38.573893 == TX Byte 1 ==
3635 16:53:38.576954 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3636 16:53:38.583378 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3637 16:53:38.583466
3638 16:53:38.583536 [DATLAT]
3639 16:53:38.583601 Freq=1200, CH1 RK1
3640 16:53:38.583695
3641 16:53:38.586672 DATLAT Default: 0xd
3642 16:53:38.586787 0, 0xFFFF, sum = 0
3643 16:53:38.589992 1, 0xFFFF, sum = 0
3644 16:53:38.590111 2, 0xFFFF, sum = 0
3645 16:53:38.593804 3, 0xFFFF, sum = 0
3646 16:53:38.596823 4, 0xFFFF, sum = 0
3647 16:53:38.596942 5, 0xFFFF, sum = 0
3648 16:53:38.600323 6, 0xFFFF, sum = 0
3649 16:53:38.600439 7, 0xFFFF, sum = 0
3650 16:53:38.603860 8, 0xFFFF, sum = 0
3651 16:53:38.603946 9, 0xFFFF, sum = 0
3652 16:53:38.606813 10, 0xFFFF, sum = 0
3653 16:53:38.606937 11, 0xFFFF, sum = 0
3654 16:53:38.609939 12, 0x0, sum = 1
3655 16:53:38.610053 13, 0x0, sum = 2
3656 16:53:38.613813 14, 0x0, sum = 3
3657 16:53:38.613931 15, 0x0, sum = 4
3658 16:53:38.614041 best_step = 13
3659 16:53:38.616922
3660 16:53:38.617036 ==
3661 16:53:38.620136 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 16:53:38.623762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 16:53:38.623881 ==
3664 16:53:38.623986 RX Vref Scan: 0
3665 16:53:38.624089
3666 16:53:38.626840 RX Vref 0 -> 0, step: 1
3667 16:53:38.626952
3668 16:53:38.630333 RX Delay -5 -> 252, step: 4
3669 16:53:38.633367 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3670 16:53:38.640360 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3671 16:53:38.643399 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3672 16:53:38.646906 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3673 16:53:38.650462 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3674 16:53:38.653357 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3675 16:53:38.659779 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3676 16:53:38.663730 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3677 16:53:38.666856 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3678 16:53:38.670004 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3679 16:53:38.673203 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3680 16:53:38.680087 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3681 16:53:38.683562 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3682 16:53:38.686700 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3683 16:53:38.689911 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3684 16:53:38.693151 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3685 16:53:38.696677 ==
3686 16:53:38.696784 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 16:53:38.702933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 16:53:38.703044 ==
3689 16:53:38.703131 DQS Delay:
3690 16:53:38.706391 DQS0 = 0, DQS1 = 0
3691 16:53:38.706506 DQM Delay:
3692 16:53:38.709830 DQM0 = 120, DQM1 = 117
3693 16:53:38.709911 DQ Delay:
3694 16:53:38.713307 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3695 16:53:38.716396 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3696 16:53:38.719611 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =112
3697 16:53:38.722871 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3698 16:53:38.722953
3699 16:53:38.723038
3700 16:53:38.733163 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3701 16:53:38.736175 CH1 RK1: MR19=403, MR18=11EE
3702 16:53:38.739700 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3703 16:53:38.743269 [RxdqsGatingPostProcess] freq 1200
3704 16:53:38.749958 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3705 16:53:38.752936 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 16:53:38.756403 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 16:53:38.759857 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 16:53:38.762852 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 16:53:38.766699 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 16:53:38.770001 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 16:53:38.773267 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 16:53:38.776528 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 16:53:38.776636 Pre-setting of DQS Precalculation
3714 16:53:38.782717 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3715 16:53:38.789419 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3716 16:53:38.796372 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3717 16:53:38.796484
3718 16:53:38.796574
3719 16:53:38.799641 [Calibration Summary] 2400 Mbps
3720 16:53:38.802722 CH 0, Rank 0
3721 16:53:38.802840 SW Impedance : PASS
3722 16:53:38.806555 DUTY Scan : NO K
3723 16:53:38.809546 ZQ Calibration : PASS
3724 16:53:38.809668 Jitter Meter : NO K
3725 16:53:38.812508 CBT Training : PASS
3726 16:53:38.816175 Write leveling : PASS
3727 16:53:38.816271 RX DQS gating : PASS
3728 16:53:38.819652 RX DQ/DQS(RDDQC) : PASS
3729 16:53:38.819755 TX DQ/DQS : PASS
3730 16:53:38.822700 RX DATLAT : PASS
3731 16:53:38.825972 RX DQ/DQS(Engine): PASS
3732 16:53:38.826071 TX OE : NO K
3733 16:53:38.829857 All Pass.
3734 16:53:38.829942
3735 16:53:38.830009 CH 0, Rank 1
3736 16:53:38.833063 SW Impedance : PASS
3737 16:53:38.833190 DUTY Scan : NO K
3738 16:53:38.836181 ZQ Calibration : PASS
3739 16:53:38.839653 Jitter Meter : NO K
3740 16:53:38.839759 CBT Training : PASS
3741 16:53:38.842951 Write leveling : PASS
3742 16:53:38.846049 RX DQS gating : PASS
3743 16:53:38.846158 RX DQ/DQS(RDDQC) : PASS
3744 16:53:38.849185 TX DQ/DQS : PASS
3745 16:53:38.852837 RX DATLAT : PASS
3746 16:53:38.852923 RX DQ/DQS(Engine): PASS
3747 16:53:38.856223 TX OE : NO K
3748 16:53:38.856335 All Pass.
3749 16:53:38.856437
3750 16:53:38.859433 CH 1, Rank 0
3751 16:53:38.859547 SW Impedance : PASS
3752 16:53:38.863013 DUTY Scan : NO K
3753 16:53:38.865877 ZQ Calibration : PASS
3754 16:53:38.865963 Jitter Meter : NO K
3755 16:53:38.869364 CBT Training : PASS
3756 16:53:38.869477 Write leveling : PASS
3757 16:53:38.872551 RX DQS gating : PASS
3758 16:53:38.876364 RX DQ/DQS(RDDQC) : PASS
3759 16:53:38.876450 TX DQ/DQS : PASS
3760 16:53:38.879557 RX DATLAT : PASS
3761 16:53:38.882789 RX DQ/DQS(Engine): PASS
3762 16:53:38.882875 TX OE : NO K
3763 16:53:38.885781 All Pass.
3764 16:53:38.885867
3765 16:53:38.885934 CH 1, Rank 1
3766 16:53:38.889716 SW Impedance : PASS
3767 16:53:38.889803 DUTY Scan : NO K
3768 16:53:38.892825 ZQ Calibration : PASS
3769 16:53:38.895794 Jitter Meter : NO K
3770 16:53:38.895880 CBT Training : PASS
3771 16:53:38.898964 Write leveling : PASS
3772 16:53:38.902753 RX DQS gating : PASS
3773 16:53:38.902866 RX DQ/DQS(RDDQC) : PASS
3774 16:53:38.905753 TX DQ/DQS : PASS
3775 16:53:38.908893 RX DATLAT : PASS
3776 16:53:38.908979 RX DQ/DQS(Engine): PASS
3777 16:53:38.912762 TX OE : NO K
3778 16:53:38.912874 All Pass.
3779 16:53:38.912971
3780 16:53:38.915845 DramC Write-DBI off
3781 16:53:38.919459 PER_BANK_REFRESH: Hybrid Mode
3782 16:53:38.919545 TX_TRACKING: ON
3783 16:53:38.928936 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3784 16:53:38.932881 [FAST_K] Save calibration result to emmc
3785 16:53:38.936150 dramc_set_vcore_voltage set vcore to 650000
3786 16:53:38.939146 Read voltage for 600, 5
3787 16:53:38.939232 Vio18 = 0
3788 16:53:38.939299 Vcore = 650000
3789 16:53:38.942626 Vdram = 0
3790 16:53:38.942729 Vddq = 0
3791 16:53:38.942798 Vmddr = 0
3792 16:53:38.949138 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3793 16:53:38.952635 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3794 16:53:38.955513 MEM_TYPE=3, freq_sel=19
3795 16:53:38.959099 sv_algorithm_assistance_LP4_1600
3796 16:53:38.962567 ============ PULL DRAM RESETB DOWN ============
3797 16:53:38.965667 ========== PULL DRAM RESETB DOWN end =========
3798 16:53:38.972247 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3799 16:53:38.975745 ===================================
3800 16:53:38.975842 LPDDR4 DRAM CONFIGURATION
3801 16:53:38.978963 ===================================
3802 16:53:38.982739 EX_ROW_EN[0] = 0x0
3803 16:53:38.986034 EX_ROW_EN[1] = 0x0
3804 16:53:38.986138 LP4Y_EN = 0x0
3805 16:53:38.989060 WORK_FSP = 0x0
3806 16:53:38.989161 WL = 0x2
3807 16:53:38.992397 RL = 0x2
3808 16:53:38.992470 BL = 0x2
3809 16:53:38.995608 RPST = 0x0
3810 16:53:38.995711 RD_PRE = 0x0
3811 16:53:38.999166 WR_PRE = 0x1
3812 16:53:38.999272 WR_PST = 0x0
3813 16:53:39.002103 DBI_WR = 0x0
3814 16:53:39.002220 DBI_RD = 0x0
3815 16:53:39.005731 OTF = 0x1
3816 16:53:39.009057 ===================================
3817 16:53:39.012174 ===================================
3818 16:53:39.012251 ANA top config
3819 16:53:39.015427 ===================================
3820 16:53:39.019226 DLL_ASYNC_EN = 0
3821 16:53:39.022261 ALL_SLAVE_EN = 1
3822 16:53:39.022337 NEW_RANK_MODE = 1
3823 16:53:39.025315 DLL_IDLE_MODE = 1
3824 16:53:39.028762 LP45_APHY_COMB_EN = 1
3825 16:53:39.032267 TX_ODT_DIS = 1
3826 16:53:39.035434 NEW_8X_MODE = 1
3827 16:53:39.038811 ===================================
3828 16:53:39.042016 ===================================
3829 16:53:39.042148 data_rate = 1200
3830 16:53:39.045781 CKR = 1
3831 16:53:39.048569 DQ_P2S_RATIO = 8
3832 16:53:39.052118 ===================================
3833 16:53:39.055568 CA_P2S_RATIO = 8
3834 16:53:39.058561 DQ_CA_OPEN = 0
3835 16:53:39.062301 DQ_SEMI_OPEN = 0
3836 16:53:39.062415 CA_SEMI_OPEN = 0
3837 16:53:39.065264 CA_FULL_RATE = 0
3838 16:53:39.068821 DQ_CKDIV4_EN = 1
3839 16:53:39.071775 CA_CKDIV4_EN = 1
3840 16:53:39.075599 CA_PREDIV_EN = 0
3841 16:53:39.078731 PH8_DLY = 0
3842 16:53:39.078815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3843 16:53:39.082217 DQ_AAMCK_DIV = 4
3844 16:53:39.085459 CA_AAMCK_DIV = 4
3845 16:53:39.088706 CA_ADMCK_DIV = 4
3846 16:53:39.091773 DQ_TRACK_CA_EN = 0
3847 16:53:39.095751 CA_PICK = 600
3848 16:53:39.095836 CA_MCKIO = 600
3849 16:53:39.099096 MCKIO_SEMI = 0
3850 16:53:39.102153 PLL_FREQ = 2288
3851 16:53:39.105378 DQ_UI_PI_RATIO = 32
3852 16:53:39.108755 CA_UI_PI_RATIO = 0
3853 16:53:39.111860 ===================================
3854 16:53:39.115010 ===================================
3855 16:53:39.118888 memory_type:LPDDR4
3856 16:53:39.119000 GP_NUM : 10
3857 16:53:39.122209 SRAM_EN : 1
3858 16:53:39.122321 MD32_EN : 0
3859 16:53:39.125346 ===================================
3860 16:53:39.128663 [ANA_INIT] >>>>>>>>>>>>>>
3861 16:53:39.132244 <<<<<< [CONFIGURE PHASE]: ANA_TX
3862 16:53:39.135294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3863 16:53:39.138869 ===================================
3864 16:53:39.142031 data_rate = 1200,PCW = 0X5800
3865 16:53:39.145312 ===================================
3866 16:53:39.148349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3867 16:53:39.155041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 16:53:39.158716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 16:53:39.165055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3870 16:53:39.168688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3871 16:53:39.171533 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3872 16:53:39.171618 [ANA_INIT] flow start
3873 16:53:39.175165 [ANA_INIT] PLL >>>>>>>>
3874 16:53:39.178087 [ANA_INIT] PLL <<<<<<<<
3875 16:53:39.178172 [ANA_INIT] MIDPI >>>>>>>>
3876 16:53:39.181610 [ANA_INIT] MIDPI <<<<<<<<
3877 16:53:39.184794 [ANA_INIT] DLL >>>>>>>>
3878 16:53:39.184879 [ANA_INIT] flow end
3879 16:53:39.191473 ============ LP4 DIFF to SE enter ============
3880 16:53:39.194594 ============ LP4 DIFF to SE exit ============
3881 16:53:39.197766 [ANA_INIT] <<<<<<<<<<<<<
3882 16:53:39.201606 [Flow] Enable top DCM control >>>>>
3883 16:53:39.204756 [Flow] Enable top DCM control <<<<<
3884 16:53:39.204864 Enable DLL master slave shuffle
3885 16:53:39.211086 ==============================================================
3886 16:53:39.214735 Gating Mode config
3887 16:53:39.217632 ==============================================================
3888 16:53:39.221253 Config description:
3889 16:53:39.231007 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3890 16:53:39.237734 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3891 16:53:39.241131 SELPH_MODE 0: By rank 1: By Phase
3892 16:53:39.247894 ==============================================================
3893 16:53:39.251056 GAT_TRACK_EN = 1
3894 16:53:39.254433 RX_GATING_MODE = 2
3895 16:53:39.258008 RX_GATING_TRACK_MODE = 2
3896 16:53:39.260911 SELPH_MODE = 1
3897 16:53:39.261013 PICG_EARLY_EN = 1
3898 16:53:39.263915 VALID_LAT_VALUE = 1
3899 16:53:39.270934 ==============================================================
3900 16:53:39.274500 Enter into Gating configuration >>>>
3901 16:53:39.277571 Exit from Gating configuration <<<<
3902 16:53:39.280462 Enter into DVFS_PRE_config >>>>>
3903 16:53:39.290593 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3904 16:53:39.293662 Exit from DVFS_PRE_config <<<<<
3905 16:53:39.297440 Enter into PICG configuration >>>>
3906 16:53:39.300672 Exit from PICG configuration <<<<
3907 16:53:39.303858 [RX_INPUT] configuration >>>>>
3908 16:53:39.307020 [RX_INPUT] configuration <<<<<
3909 16:53:39.313946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3910 16:53:39.317067 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3911 16:53:39.323784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 16:53:39.330518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 16:53:39.336861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 16:53:39.343797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 16:53:39.347128 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3916 16:53:39.350724 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3917 16:53:39.353613 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3918 16:53:39.357348 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3919 16:53:39.363758 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3920 16:53:39.367243 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 16:53:39.370075 ===================================
3922 16:53:39.373721 LPDDR4 DRAM CONFIGURATION
3923 16:53:39.376654 ===================================
3924 16:53:39.376764 EX_ROW_EN[0] = 0x0
3925 16:53:39.380324 EX_ROW_EN[1] = 0x0
3926 16:53:39.380407 LP4Y_EN = 0x0
3927 16:53:39.383718 WORK_FSP = 0x0
3928 16:53:39.383804 WL = 0x2
3929 16:53:39.386701 RL = 0x2
3930 16:53:39.390286 BL = 0x2
3931 16:53:39.390366 RPST = 0x0
3932 16:53:39.393617 RD_PRE = 0x0
3933 16:53:39.393693 WR_PRE = 0x1
3934 16:53:39.396732 WR_PST = 0x0
3935 16:53:39.396810 DBI_WR = 0x0
3936 16:53:39.400432 DBI_RD = 0x0
3937 16:53:39.400510 OTF = 0x1
3938 16:53:39.403670 ===================================
3939 16:53:39.406840 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3940 16:53:39.413182 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3941 16:53:39.417051 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 16:53:39.420028 ===================================
3943 16:53:39.423345 LPDDR4 DRAM CONFIGURATION
3944 16:53:39.426604 ===================================
3945 16:53:39.426739 EX_ROW_EN[0] = 0x10
3946 16:53:39.430269 EX_ROW_EN[1] = 0x0
3947 16:53:39.430416 LP4Y_EN = 0x0
3948 16:53:39.432962 WORK_FSP = 0x0
3949 16:53:39.433083 WL = 0x2
3950 16:53:39.436775 RL = 0x2
3951 16:53:39.436920 BL = 0x2
3952 16:53:39.439914 RPST = 0x0
3953 16:53:39.440033 RD_PRE = 0x0
3954 16:53:39.443069 WR_PRE = 0x1
3955 16:53:39.446301 WR_PST = 0x0
3956 16:53:39.446433 DBI_WR = 0x0
3957 16:53:39.449950 DBI_RD = 0x0
3958 16:53:39.450071 OTF = 0x1
3959 16:53:39.453624 ===================================
3960 16:53:39.459604 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3961 16:53:39.463734 nWR fixed to 30
3962 16:53:39.466969 [ModeRegInit_LP4] CH0 RK0
3963 16:53:39.467099 [ModeRegInit_LP4] CH0 RK1
3964 16:53:39.470081 [ModeRegInit_LP4] CH1 RK0
3965 16:53:39.473165 [ModeRegInit_LP4] CH1 RK1
3966 16:53:39.473283 match AC timing 17
3967 16:53:39.479996 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3968 16:53:39.483365 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3969 16:53:39.486980 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3970 16:53:39.493255 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3971 16:53:39.497020 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3972 16:53:39.497139 ==
3973 16:53:39.499768 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 16:53:39.503449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 16:53:39.503561 ==
3976 16:53:39.510102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 16:53:39.516309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3978 16:53:39.520153 [CA 0] Center 36 (5~67) winsize 63
3979 16:53:39.523316 [CA 1] Center 36 (5~67) winsize 63
3980 16:53:39.526464 [CA 2] Center 34 (3~65) winsize 63
3981 16:53:39.529706 [CA 3] Center 33 (2~64) winsize 63
3982 16:53:39.532852 [CA 4] Center 33 (2~64) winsize 63
3983 16:53:39.536530 [CA 5] Center 32 (2~63) winsize 62
3984 16:53:39.536646
3985 16:53:39.539518 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3986 16:53:39.539631
3987 16:53:39.543208 [CATrainingPosCal] consider 1 rank data
3988 16:53:39.546537 u2DelayCellTimex100 = 270/100 ps
3989 16:53:39.549826 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3990 16:53:39.552876 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3991 16:53:39.556935 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3992 16:53:39.559759 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3993 16:53:39.566255 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3994 16:53:39.569391 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3995 16:53:39.569495
3996 16:53:39.572651 CA PerBit enable=1, Macro0, CA PI delay=32
3997 16:53:39.572723
3998 16:53:39.576305 [CBTSetCACLKResult] CA Dly = 32
3999 16:53:39.576406 CS Dly: 4 (0~35)
4000 16:53:39.576552 ==
4001 16:53:39.579376 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 16:53:39.582590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 16:53:39.586233 ==
4004 16:53:39.589675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 16:53:39.595826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 16:53:39.599349 [CA 0] Center 35 (5~66) winsize 62
4007 16:53:39.602917 [CA 1] Center 35 (5~66) winsize 62
4008 16:53:39.606221 [CA 2] Center 34 (3~65) winsize 63
4009 16:53:39.609222 [CA 3] Center 33 (3~64) winsize 62
4010 16:53:39.612651 [CA 4] Center 33 (2~64) winsize 63
4011 16:53:39.616045 [CA 5] Center 32 (2~63) winsize 62
4012 16:53:39.616150
4013 16:53:39.619524 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 16:53:39.619631
4015 16:53:39.622811 [CATrainingPosCal] consider 2 rank data
4016 16:53:39.626034 u2DelayCellTimex100 = 270/100 ps
4017 16:53:39.629178 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4018 16:53:39.633038 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4019 16:53:39.636248 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4020 16:53:39.642476 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4021 16:53:39.646129 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4022 16:53:39.649027 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4023 16:53:39.649172
4024 16:53:39.652825 CA PerBit enable=1, Macro0, CA PI delay=32
4025 16:53:39.652925
4026 16:53:39.655927 [CBTSetCACLKResult] CA Dly = 32
4027 16:53:39.656052 CS Dly: 4 (0~36)
4028 16:53:39.656160
4029 16:53:39.659042 ----->DramcWriteLeveling(PI) begin...
4030 16:53:39.659151 ==
4031 16:53:39.662717 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 16:53:39.669348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 16:53:39.669469 ==
4034 16:53:39.672226 Write leveling (Byte 0): 33 => 33
4035 16:53:39.676044 Write leveling (Byte 1): 32 => 32
4036 16:53:39.676162 DramcWriteLeveling(PI) end<-----
4037 16:53:39.676258
4038 16:53:39.679156 ==
4039 16:53:39.682366 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 16:53:39.686004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 16:53:39.686094 ==
4042 16:53:39.689158 [Gating] SW mode calibration
4043 16:53:39.695931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4044 16:53:39.699400 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4045 16:53:39.705702 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 16:53:39.708686 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 16:53:39.712090 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 16:53:39.719057 0 9 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
4049 16:53:39.722523 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (1 1) (0 0)
4050 16:53:39.725383 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 16:53:39.732358 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 16:53:39.735512 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 16:53:39.738749 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 16:53:39.745443 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 16:53:39.748503 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 16:53:39.752337 0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
4057 16:53:39.758764 0 10 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
4058 16:53:39.761854 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 16:53:39.765225 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 16:53:39.771801 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 16:53:39.775023 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 16:53:39.778394 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 16:53:39.785163 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 16:53:39.788240 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4065 16:53:39.791954 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 16:53:39.798354 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 16:53:39.802187 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 16:53:39.805260 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 16:53:39.812269 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 16:53:39.815381 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 16:53:39.818764 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 16:53:39.825201 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 16:53:39.828843 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 16:53:39.831547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 16:53:39.835130 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 16:53:39.841438 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 16:53:39.845289 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 16:53:39.848503 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 16:53:39.854858 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 16:53:39.858468 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4081 16:53:39.861492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 16:53:39.865298 Total UI for P1: 0, mck2ui 16
4083 16:53:39.868513 best dqsien dly found for B0: ( 0, 13, 12)
4084 16:53:39.871768 Total UI for P1: 0, mck2ui 16
4085 16:53:39.875388 best dqsien dly found for B1: ( 0, 13, 14)
4086 16:53:39.878457 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4087 16:53:39.881356 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4088 16:53:39.884850
4089 16:53:39.888076 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4090 16:53:39.891800 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4091 16:53:39.894813 [Gating] SW calibration Done
4092 16:53:39.894922 ==
4093 16:53:39.898215 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 16:53:39.901352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 16:53:39.901459 ==
4096 16:53:39.901564 RX Vref Scan: 0
4097 16:53:39.901667
4098 16:53:39.904527 RX Vref 0 -> 0, step: 1
4099 16:53:39.904616
4100 16:53:39.907794 RX Delay -230 -> 252, step: 16
4101 16:53:39.911380 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4102 16:53:39.915015 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4103 16:53:39.922020 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4104 16:53:39.925066 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4105 16:53:39.928334 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4106 16:53:39.931341 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4107 16:53:39.938536 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4108 16:53:39.941343 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4109 16:53:39.944950 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4110 16:53:39.948301 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4111 16:53:39.951459 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4112 16:53:39.958401 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4113 16:53:39.961648 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4114 16:53:39.965163 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4115 16:53:39.968329 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4116 16:53:39.975000 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4117 16:53:39.975089 ==
4118 16:53:39.978180 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 16:53:39.981263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 16:53:39.981349 ==
4121 16:53:39.981417 DQS Delay:
4122 16:53:39.984627 DQS0 = 0, DQS1 = 0
4123 16:53:39.984713 DQM Delay:
4124 16:53:39.988321 DQM0 = 54, DQM1 = 45
4125 16:53:39.988407 DQ Delay:
4126 16:53:39.991270 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4127 16:53:39.995098 DQ4 =49, DQ5 =49, DQ6 =65, DQ7 =65
4128 16:53:39.998137 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4129 16:53:40.001314 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4130 16:53:40.001399
4131 16:53:40.001467
4132 16:53:40.001540 ==
4133 16:53:40.004350 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 16:53:40.007526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 16:53:40.011456 ==
4136 16:53:40.011542
4137 16:53:40.011609
4138 16:53:40.011672 TX Vref Scan disable
4139 16:53:40.014569 == TX Byte 0 ==
4140 16:53:40.017728 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4141 16:53:40.020885 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4142 16:53:40.024640 == TX Byte 1 ==
4143 16:53:40.027970 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4144 16:53:40.031101 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4145 16:53:40.034455 ==
4146 16:53:40.034559 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 16:53:40.040853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 16:53:40.040940 ==
4149 16:53:40.041008
4150 16:53:40.041070
4151 16:53:40.044523 TX Vref Scan disable
4152 16:53:40.044610 == TX Byte 0 ==
4153 16:53:40.050885 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4154 16:53:40.053999 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4155 16:53:40.054086 == TX Byte 1 ==
4156 16:53:40.060960 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4157 16:53:40.064123 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4158 16:53:40.064228
4159 16:53:40.064323 [DATLAT]
4160 16:53:40.067603 Freq=600, CH0 RK0
4161 16:53:40.067690
4162 16:53:40.067773 DATLAT Default: 0x9
4163 16:53:40.071124 0, 0xFFFF, sum = 0
4164 16:53:40.071211 1, 0xFFFF, sum = 0
4165 16:53:40.074227 2, 0xFFFF, sum = 0
4166 16:53:40.074312 3, 0xFFFF, sum = 0
4167 16:53:40.077358 4, 0xFFFF, sum = 0
4168 16:53:40.077442 5, 0xFFFF, sum = 0
4169 16:53:40.080610 6, 0xFFFF, sum = 0
4170 16:53:40.083851 7, 0xFFFF, sum = 0
4171 16:53:40.083936 8, 0x0, sum = 1
4172 16:53:40.084003 9, 0x0, sum = 2
4173 16:53:40.087623 10, 0x0, sum = 3
4174 16:53:40.087708 11, 0x0, sum = 4
4175 16:53:40.090549 best_step = 9
4176 16:53:40.090646
4177 16:53:40.090711 ==
4178 16:53:40.093896 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 16:53:40.097033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 16:53:40.097131 ==
4181 16:53:40.100462 RX Vref Scan: 1
4182 16:53:40.100555
4183 16:53:40.100622 RX Vref 0 -> 0, step: 1
4184 16:53:40.100684
4185 16:53:40.104085 RX Delay -163 -> 252, step: 8
4186 16:53:40.104195
4187 16:53:40.107398 Set Vref, RX VrefLevel [Byte0]: 57
4188 16:53:40.111197 [Byte1]: 51
4189 16:53:40.114322
4190 16:53:40.114422 Final RX Vref Byte 0 = 57 to rank0
4191 16:53:40.118103 Final RX Vref Byte 1 = 51 to rank0
4192 16:53:40.121263 Final RX Vref Byte 0 = 57 to rank1
4193 16:53:40.124468 Final RX Vref Byte 1 = 51 to rank1==
4194 16:53:40.127605 Dram Type= 6, Freq= 0, CH_0, rank 0
4195 16:53:40.134316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 16:53:40.134393 ==
4197 16:53:40.134457 DQS Delay:
4198 16:53:40.134517 DQS0 = 0, DQS1 = 0
4199 16:53:40.138156 DQM Delay:
4200 16:53:40.138234 DQM0 = 52, DQM1 = 45
4201 16:53:40.141185 DQ Delay:
4202 16:53:40.144811 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4203 16:53:40.144963 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4204 16:53:40.147584 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4205 16:53:40.154601 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4206 16:53:40.154687
4207 16:53:40.154771
4208 16:53:40.160991 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
4209 16:53:40.164780 CH0 RK0: MR19=808, MR18=6B5E
4210 16:53:40.171053 CH0_RK0: MR19=0x808, MR18=0x6B5E, DQSOSC=389, MR23=63, INC=173, DEC=115
4211 16:53:40.171142
4212 16:53:40.174356 ----->DramcWriteLeveling(PI) begin...
4213 16:53:40.174437 ==
4214 16:53:40.178103 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 16:53:40.180981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 16:53:40.181094 ==
4217 16:53:40.184167 Write leveling (Byte 0): 35 => 35
4218 16:53:40.187481 Write leveling (Byte 1): 31 => 31
4219 16:53:40.191161 DramcWriteLeveling(PI) end<-----
4220 16:53:40.191272
4221 16:53:40.191369 ==
4222 16:53:40.194318 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 16:53:40.197970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 16:53:40.198081 ==
4225 16:53:40.200843 [Gating] SW mode calibration
4226 16:53:40.207777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4227 16:53:40.214161 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4228 16:53:40.217351 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 16:53:40.220658 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 16:53:40.227557 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 16:53:40.230764 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4232 16:53:40.234639 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4233 16:53:40.240678 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 16:53:40.244338 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 16:53:40.247280 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 16:53:40.254302 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 16:53:40.257715 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 16:53:40.260736 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 16:53:40.267476 0 10 12 | B1->B0 | 2525 2f2f | 0 0 | (1 1) (1 1)
4240 16:53:40.271013 0 10 16 | B1->B0 | 4141 4141 | 1 0 | (0 0) (0 0)
4241 16:53:40.273985 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 16:53:40.280941 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 16:53:40.283883 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 16:53:40.287102 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 16:53:40.294093 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 16:53:40.297183 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 16:53:40.300400 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 16:53:40.307155 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 16:53:40.310550 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 16:53:40.314156 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 16:53:40.320735 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 16:53:40.324138 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 16:53:40.327247 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 16:53:40.330411 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 16:53:40.337445 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 16:53:40.340529 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 16:53:40.344124 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 16:53:40.350486 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 16:53:40.354181 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 16:53:40.357228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 16:53:40.363509 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 16:53:40.366754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 16:53:40.370500 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 16:53:40.377223 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 16:53:40.380309 Total UI for P1: 0, mck2ui 16
4266 16:53:40.383495 best dqsien dly found for B0: ( 0, 13, 14)
4267 16:53:40.383596 Total UI for P1: 0, mck2ui 16
4268 16:53:40.390399 best dqsien dly found for B1: ( 0, 13, 14)
4269 16:53:40.393543 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4270 16:53:40.397375 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4271 16:53:40.397462
4272 16:53:40.400593 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4273 16:53:40.403770 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4274 16:53:40.406957 [Gating] SW calibration Done
4275 16:53:40.407058 ==
4276 16:53:40.409979 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 16:53:40.413852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 16:53:40.413954 ==
4279 16:53:40.416948 RX Vref Scan: 0
4280 16:53:40.417047
4281 16:53:40.417133 RX Vref 0 -> 0, step: 1
4282 16:53:40.420369
4283 16:53:40.420469 RX Delay -230 -> 252, step: 16
4284 16:53:40.426858 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4285 16:53:40.429797 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4286 16:53:40.433679 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4287 16:53:40.437029 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4288 16:53:40.443307 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4289 16:53:40.447005 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4290 16:53:40.450229 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4291 16:53:40.453246 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4292 16:53:40.456366 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4293 16:53:40.462954 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4294 16:53:40.466322 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4295 16:53:40.469467 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4296 16:53:40.473182 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4297 16:53:40.479760 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4298 16:53:40.483203 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4299 16:53:40.486328 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4300 16:53:40.486418 ==
4301 16:53:40.489794 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 16:53:40.493293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 16:53:40.496188 ==
4304 16:53:40.496287 DQS Delay:
4305 16:53:40.496391 DQS0 = 0, DQS1 = 0
4306 16:53:40.499428 DQM Delay:
4307 16:53:40.499546 DQM0 = 49, DQM1 = 42
4308 16:53:40.502804 DQ Delay:
4309 16:53:40.502910 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4310 16:53:40.506423 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4311 16:53:40.509687 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4312 16:53:40.512741 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4313 16:53:40.516398
4314 16:53:40.516503
4315 16:53:40.516569 ==
4316 16:53:40.519398 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 16:53:40.523263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 16:53:40.523364 ==
4319 16:53:40.523457
4320 16:53:40.523529
4321 16:53:40.526111 TX Vref Scan disable
4322 16:53:40.526183 == TX Byte 0 ==
4323 16:53:40.532535 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4324 16:53:40.535743 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4325 16:53:40.535844 == TX Byte 1 ==
4326 16:53:40.542655 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4327 16:53:40.545961 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4328 16:53:40.546056 ==
4329 16:53:40.548943 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 16:53:40.552729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 16:53:40.552817 ==
4332 16:53:40.552886
4333 16:53:40.552950
4334 16:53:40.555962 TX Vref Scan disable
4335 16:53:40.559155 == TX Byte 0 ==
4336 16:53:40.562841 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4337 16:53:40.568820 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4338 16:53:40.568908 == TX Byte 1 ==
4339 16:53:40.572436 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4340 16:53:40.578729 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4341 16:53:40.578814
4342 16:53:40.578883 [DATLAT]
4343 16:53:40.578946 Freq=600, CH0 RK1
4344 16:53:40.579007
4345 16:53:40.582434 DATLAT Default: 0x9
4346 16:53:40.585473 0, 0xFFFF, sum = 0
4347 16:53:40.585580 1, 0xFFFF, sum = 0
4348 16:53:40.589173 2, 0xFFFF, sum = 0
4349 16:53:40.589287 3, 0xFFFF, sum = 0
4350 16:53:40.592258 4, 0xFFFF, sum = 0
4351 16:53:40.592343 5, 0xFFFF, sum = 0
4352 16:53:40.595479 6, 0xFFFF, sum = 0
4353 16:53:40.595598 7, 0xFFFF, sum = 0
4354 16:53:40.599190 8, 0x0, sum = 1
4355 16:53:40.599307 9, 0x0, sum = 2
4356 16:53:40.599375 10, 0x0, sum = 3
4357 16:53:40.602214 11, 0x0, sum = 4
4358 16:53:40.602299 best_step = 9
4359 16:53:40.602367
4360 16:53:40.605331 ==
4361 16:53:40.605444 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 16:53:40.612360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 16:53:40.612444 ==
4364 16:53:40.612510 RX Vref Scan: 0
4365 16:53:40.612570
4366 16:53:40.615520 RX Vref 0 -> 0, step: 1
4367 16:53:40.615603
4368 16:53:40.619205 RX Delay -163 -> 252, step: 8
4369 16:53:40.622200 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4370 16:53:40.629252 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4371 16:53:40.632088 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4372 16:53:40.635409 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4373 16:53:40.639084 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4374 16:53:40.642070 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4375 16:53:40.648856 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4376 16:53:40.652139 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4377 16:53:40.655266 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4378 16:53:40.658876 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4379 16:53:40.662085 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4380 16:53:40.668941 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4381 16:53:40.671921 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4382 16:53:40.675700 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4383 16:53:40.678651 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4384 16:53:40.682187 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4385 16:53:40.685183 ==
4386 16:53:40.688679 Dram Type= 6, Freq= 0, CH_0, rank 1
4387 16:53:40.691873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 16:53:40.691957 ==
4389 16:53:40.692022 DQS Delay:
4390 16:53:40.695268 DQS0 = 0, DQS1 = 0
4391 16:53:40.695350 DQM Delay:
4392 16:53:40.698445 DQM0 = 54, DQM1 = 46
4393 16:53:40.698528 DQ Delay:
4394 16:53:40.702362 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4395 16:53:40.705366 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4396 16:53:40.708375 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4397 16:53:40.712111 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4398 16:53:40.712193
4399 16:53:40.712258
4400 16:53:40.718540 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
4401 16:53:40.721797 CH0 RK1: MR19=808, MR18=5F1E
4402 16:53:40.728279 CH0_RK1: MR19=0x808, MR18=0x5F1E, DQSOSC=391, MR23=63, INC=171, DEC=114
4403 16:53:40.732183 [RxdqsGatingPostProcess] freq 600
4404 16:53:40.738463 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4405 16:53:40.738585 Pre-setting of DQS Precalculation
4406 16:53:40.745005 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4407 16:53:40.745094 ==
4408 16:53:40.748479 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 16:53:40.751734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 16:53:40.751820 ==
4411 16:53:40.758600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4412 16:53:40.764784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4413 16:53:40.768673 [CA 0] Center 36 (5~67) winsize 63
4414 16:53:40.771809 [CA 1] Center 36 (5~67) winsize 63
4415 16:53:40.774902 [CA 2] Center 34 (4~65) winsize 62
4416 16:53:40.778626 [CA 3] Center 34 (3~65) winsize 63
4417 16:53:40.781461 [CA 4] Center 34 (4~65) winsize 62
4418 16:53:40.784989 [CA 5] Center 34 (3~65) winsize 63
4419 16:53:40.785074
4420 16:53:40.788578 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4421 16:53:40.788663
4422 16:53:40.791678 [CATrainingPosCal] consider 1 rank data
4423 16:53:40.795017 u2DelayCellTimex100 = 270/100 ps
4424 16:53:40.798070 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4425 16:53:40.801968 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4426 16:53:40.805072 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4427 16:53:40.808581 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4428 16:53:40.811814 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4429 16:53:40.814852 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4430 16:53:40.814947
4431 16:53:40.821801 CA PerBit enable=1, Macro0, CA PI delay=34
4432 16:53:40.821897
4433 16:53:40.821963 [CBTSetCACLKResult] CA Dly = 34
4434 16:53:40.825146 CS Dly: 5 (0~36)
4435 16:53:40.825229 ==
4436 16:53:40.828090 Dram Type= 6, Freq= 0, CH_1, rank 1
4437 16:53:40.831785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 16:53:40.831869 ==
4439 16:53:40.838578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4440 16:53:40.844768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4441 16:53:40.848299 [CA 0] Center 36 (5~67) winsize 63
4442 16:53:40.851302 [CA 1] Center 36 (5~67) winsize 63
4443 16:53:40.854778 [CA 2] Center 34 (4~65) winsize 62
4444 16:53:40.858429 [CA 3] Center 34 (4~65) winsize 62
4445 16:53:40.861534 [CA 4] Center 34 (4~65) winsize 62
4446 16:53:40.864679 [CA 5] Center 34 (4~65) winsize 62
4447 16:53:40.864769
4448 16:53:40.868586 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4449 16:53:40.868680
4450 16:53:40.871737 [CATrainingPosCal] consider 2 rank data
4451 16:53:40.874869 u2DelayCellTimex100 = 270/100 ps
4452 16:53:40.878085 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4453 16:53:40.881725 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4454 16:53:40.884812 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4455 16:53:40.888278 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4456 16:53:40.891279 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4457 16:53:40.895239 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4458 16:53:40.895336
4459 16:53:40.902015 CA PerBit enable=1, Macro0, CA PI delay=34
4460 16:53:40.902098
4461 16:53:40.905082 [CBTSetCACLKResult] CA Dly = 34
4462 16:53:40.905159 CS Dly: 6 (0~38)
4463 16:53:40.905224
4464 16:53:40.908466 ----->DramcWriteLeveling(PI) begin...
4465 16:53:40.908549 ==
4466 16:53:40.911684 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 16:53:40.914839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 16:53:40.914915 ==
4469 16:53:40.918732 Write leveling (Byte 0): 30 => 30
4470 16:53:40.921722 Write leveling (Byte 1): 30 => 30
4471 16:53:40.924866 DramcWriteLeveling(PI) end<-----
4472 16:53:40.924954
4473 16:53:40.925023 ==
4474 16:53:40.928473 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 16:53:40.934991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 16:53:40.935112 ==
4477 16:53:40.935180 [Gating] SW mode calibration
4478 16:53:40.945111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4479 16:53:40.948354 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4480 16:53:40.951353 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 16:53:40.957917 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 16:53:40.961581 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4483 16:53:40.964640 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 1)
4484 16:53:40.971418 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 16:53:40.974532 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 16:53:40.977583 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 16:53:40.984658 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 16:53:40.987810 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 16:53:40.991392 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 16:53:40.997941 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4491 16:53:41.000744 0 10 12 | B1->B0 | 3838 3e3e | 0 0 | (0 0) (0 0)
4492 16:53:41.004464 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 16:53:41.011207 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 16:53:41.014747 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 16:53:41.017950 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 16:53:41.024296 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 16:53:41.028016 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 16:53:41.031171 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 16:53:41.037395 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4500 16:53:41.040949 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 16:53:41.044122 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 16:53:41.051089 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 16:53:41.054333 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 16:53:41.057334 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 16:53:41.064188 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 16:53:41.067255 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 16:53:41.070386 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 16:53:41.077564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 16:53:41.080764 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 16:53:41.084126 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 16:53:41.090410 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 16:53:41.094216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 16:53:41.097033 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 16:53:41.104015 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 16:53:41.106992 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4516 16:53:41.110552 Total UI for P1: 0, mck2ui 16
4517 16:53:41.113550 best dqsien dly found for B0: ( 0, 13, 10)
4518 16:53:41.117260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 16:53:41.120258 Total UI for P1: 0, mck2ui 16
4520 16:53:41.123434 best dqsien dly found for B1: ( 0, 13, 12)
4521 16:53:41.127231 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4522 16:53:41.130238 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4523 16:53:41.130323
4524 16:53:41.133929 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4525 16:53:41.140292 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4526 16:53:41.140379 [Gating] SW calibration Done
4527 16:53:41.140446 ==
4528 16:53:41.143882 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 16:53:41.150740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 16:53:41.150831 ==
4531 16:53:41.150900 RX Vref Scan: 0
4532 16:53:41.150964
4533 16:53:41.153912 RX Vref 0 -> 0, step: 1
4534 16:53:41.153997
4535 16:53:41.157187 RX Delay -230 -> 252, step: 16
4536 16:53:41.160485 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4537 16:53:41.163559 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4538 16:53:41.167123 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4539 16:53:41.174033 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4540 16:53:41.176929 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4541 16:53:41.180457 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4542 16:53:41.184159 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4543 16:53:41.190619 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4544 16:53:41.193941 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4545 16:53:41.197156 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4546 16:53:41.200274 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4547 16:53:41.203703 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4548 16:53:41.210260 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4549 16:53:41.213825 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4550 16:53:41.216913 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4551 16:53:41.220360 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4552 16:53:41.223440 ==
4553 16:53:41.223526 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 16:53:41.230102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 16:53:41.230193 ==
4556 16:53:41.230264 DQS Delay:
4557 16:53:41.234000 DQS0 = 0, DQS1 = 0
4558 16:53:41.234117 DQM Delay:
4559 16:53:41.236970 DQM0 = 48, DQM1 = 46
4560 16:53:41.237077 DQ Delay:
4561 16:53:41.240537 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4562 16:53:41.243378 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4563 16:53:41.247197 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4564 16:53:41.250176 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4565 16:53:41.250287
4566 16:53:41.250384
4567 16:53:41.250477 ==
4568 16:53:41.253379 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 16:53:41.257225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 16:53:41.257332 ==
4571 16:53:41.257427
4572 16:53:41.257527
4573 16:53:41.260506 TX Vref Scan disable
4574 16:53:41.263690 == TX Byte 0 ==
4575 16:53:41.266851 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 16:53:41.270692 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 16:53:41.273653 == TX Byte 1 ==
4578 16:53:41.277177 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 16:53:41.280178 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 16:53:41.280285 ==
4581 16:53:41.283676 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 16:53:41.287363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 16:53:41.287468 ==
4584 16:53:41.290297
4585 16:53:41.290405
4586 16:53:41.290501 TX Vref Scan disable
4587 16:53:41.294220 == TX Byte 0 ==
4588 16:53:41.297338 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4589 16:53:41.304281 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4590 16:53:41.304368 == TX Byte 1 ==
4591 16:53:41.307293 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4592 16:53:41.313770 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4593 16:53:41.313881
4594 16:53:41.313959 [DATLAT]
4595 16:53:41.314024 Freq=600, CH1 RK0
4596 16:53:41.314087
4597 16:53:41.317255 DATLAT Default: 0x9
4598 16:53:41.317341 0, 0xFFFF, sum = 0
4599 16:53:41.320197 1, 0xFFFF, sum = 0
4600 16:53:41.323707 2, 0xFFFF, sum = 0
4601 16:53:41.323787 3, 0xFFFF, sum = 0
4602 16:53:41.326804 4, 0xFFFF, sum = 0
4603 16:53:41.326887 5, 0xFFFF, sum = 0
4604 16:53:41.330344 6, 0xFFFF, sum = 0
4605 16:53:41.330424 7, 0xFFFF, sum = 0
4606 16:53:41.333285 8, 0x0, sum = 1
4607 16:53:41.333401 9, 0x0, sum = 2
4608 16:53:41.333498 10, 0x0, sum = 3
4609 16:53:41.336592 11, 0x0, sum = 4
4610 16:53:41.336679 best_step = 9
4611 16:53:41.336747
4612 16:53:41.340351 ==
4613 16:53:41.340455 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 16:53:41.347172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 16:53:41.347279 ==
4616 16:53:41.347349 RX Vref Scan: 1
4617 16:53:41.347412
4618 16:53:41.350174 RX Vref 0 -> 0, step: 1
4619 16:53:41.350267
4620 16:53:41.353479 RX Delay -163 -> 252, step: 8
4621 16:53:41.353574
4622 16:53:41.356579 Set Vref, RX VrefLevel [Byte0]: 53
4623 16:53:41.360494 [Byte1]: 50
4624 16:53:41.360579
4625 16:53:41.363733 Final RX Vref Byte 0 = 53 to rank0
4626 16:53:41.367081 Final RX Vref Byte 1 = 50 to rank0
4627 16:53:41.370156 Final RX Vref Byte 0 = 53 to rank1
4628 16:53:41.373439 Final RX Vref Byte 1 = 50 to rank1==
4629 16:53:41.377055 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 16:53:41.380228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 16:53:41.380314 ==
4632 16:53:41.383181 DQS Delay:
4633 16:53:41.383279 DQS0 = 0, DQS1 = 0
4634 16:53:41.386801 DQM Delay:
4635 16:53:41.386886 DQM0 = 48, DQM1 = 45
4636 16:53:41.386954 DQ Delay:
4637 16:53:41.390464 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4638 16:53:41.393200 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4639 16:53:41.396989 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4640 16:53:41.399714 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4641 16:53:41.399800
4642 16:53:41.399868
4643 16:53:41.409647 [DQSOSCAuto] RK0, (LSB)MR18= 0x4368, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4644 16:53:41.413335 CH1 RK0: MR19=808, MR18=4368
4645 16:53:41.419956 CH1_RK0: MR19=0x808, MR18=0x4368, DQSOSC=390, MR23=63, INC=172, DEC=114
4646 16:53:41.420044
4647 16:53:41.423384 ----->DramcWriteLeveling(PI) begin...
4648 16:53:41.423472 ==
4649 16:53:41.426997 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 16:53:41.430065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 16:53:41.430155 ==
4652 16:53:41.433173 Write leveling (Byte 0): 28 => 28
4653 16:53:41.436667 Write leveling (Byte 1): 31 => 31
4654 16:53:41.439742 DramcWriteLeveling(PI) end<-----
4655 16:53:41.439851
4656 16:53:41.439946 ==
4657 16:53:41.443458 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 16:53:41.446581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 16:53:41.446701 ==
4660 16:53:41.450247 [Gating] SW mode calibration
4661 16:53:41.456458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4662 16:53:41.463075 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4663 16:53:41.466387 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4664 16:53:41.470084 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 16:53:41.476486 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4666 16:53:41.479703 0 9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (0 1) (0 1)
4667 16:53:41.482891 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 16:53:41.486491 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 16:53:41.493229 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 16:53:41.496287 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 16:53:41.499703 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 16:53:41.506132 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 16:53:41.509803 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 16:53:41.513158 0 10 12 | B1->B0 | 3f3f 3030 | 0 0 | (0 0) (1 1)
4675 16:53:41.519997 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 16:53:41.522914 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 16:53:41.526496 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 16:53:41.532902 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 16:53:41.536621 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 16:53:41.539760 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 16:53:41.546144 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 16:53:41.549817 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4683 16:53:41.553053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 16:53:41.559463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 16:53:41.563218 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 16:53:41.566729 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 16:53:41.572921 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 16:53:41.576127 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 16:53:41.579842 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 16:53:41.586378 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 16:53:41.589413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 16:53:41.593236 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 16:53:41.596388 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 16:53:41.602866 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 16:53:41.606292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 16:53:41.609943 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 16:53:41.616318 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 16:53:41.620184 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4699 16:53:41.623415 Total UI for P1: 0, mck2ui 16
4700 16:53:41.626293 best dqsien dly found for B1: ( 0, 13, 10)
4701 16:53:41.629424 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 16:53:41.632866 Total UI for P1: 0, mck2ui 16
4703 16:53:41.636567 best dqsien dly found for B0: ( 0, 13, 12)
4704 16:53:41.640055 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4705 16:53:41.643038 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4706 16:53:41.646190
4707 16:53:41.649790 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4708 16:53:41.653270 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4709 16:53:41.656206 [Gating] SW calibration Done
4710 16:53:41.656289 ==
4711 16:53:41.659910 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 16:53:41.663121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 16:53:41.663206 ==
4714 16:53:41.663272 RX Vref Scan: 0
4715 16:53:41.663334
4716 16:53:41.666277 RX Vref 0 -> 0, step: 1
4717 16:53:41.666360
4718 16:53:41.669395 RX Delay -230 -> 252, step: 16
4719 16:53:41.673075 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4720 16:53:41.679554 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4721 16:53:41.682843 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4722 16:53:41.685945 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4723 16:53:41.689259 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4724 16:53:41.692858 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4725 16:53:41.699872 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4726 16:53:41.702766 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4727 16:53:41.705848 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4728 16:53:41.709429 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4729 16:53:41.712527 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4730 16:53:41.719410 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4731 16:53:41.722741 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4732 16:53:41.725986 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4733 16:53:41.729628 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4734 16:53:41.735768 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4735 16:53:41.735895 ==
4736 16:53:41.739201 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 16:53:41.742640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 16:53:41.742724 ==
4739 16:53:41.742790 DQS Delay:
4740 16:53:41.745654 DQS0 = 0, DQS1 = 0
4741 16:53:41.745737 DQM Delay:
4742 16:53:41.749379 DQM0 = 49, DQM1 = 48
4743 16:53:41.749493 DQ Delay:
4744 16:53:41.752432 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4745 16:53:41.755912 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4746 16:53:41.758792 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4747 16:53:41.762357 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4748 16:53:41.762441
4749 16:53:41.762507
4750 16:53:41.762570 ==
4751 16:53:41.765438 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 16:53:41.771875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 16:53:41.771960 ==
4754 16:53:41.772026
4755 16:53:41.772088
4756 16:53:41.772147 TX Vref Scan disable
4757 16:53:41.775765 == TX Byte 0 ==
4758 16:53:41.778777 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4759 16:53:41.782279 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4760 16:53:41.785872 == TX Byte 1 ==
4761 16:53:41.788978 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4762 16:53:41.792086 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4763 16:53:41.795442 ==
4764 16:53:41.798973 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 16:53:41.802494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 16:53:41.802579 ==
4767 16:53:41.802646
4768 16:53:41.802708
4769 16:53:41.805403 TX Vref Scan disable
4770 16:53:41.808541 == TX Byte 0 ==
4771 16:53:41.812100 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4772 16:53:41.815475 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4773 16:53:41.815559 == TX Byte 1 ==
4774 16:53:41.821983 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4775 16:53:41.825815 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4776 16:53:41.825899
4777 16:53:41.825965 [DATLAT]
4778 16:53:41.829071 Freq=600, CH1 RK1
4779 16:53:41.829155
4780 16:53:41.829222 DATLAT Default: 0x9
4781 16:53:41.832319 0, 0xFFFF, sum = 0
4782 16:53:41.832404 1, 0xFFFF, sum = 0
4783 16:53:41.835355 2, 0xFFFF, sum = 0
4784 16:53:41.835440 3, 0xFFFF, sum = 0
4785 16:53:41.838533 4, 0xFFFF, sum = 0
4786 16:53:41.842110 5, 0xFFFF, sum = 0
4787 16:53:41.842194 6, 0xFFFF, sum = 0
4788 16:53:41.845070 7, 0xFFFF, sum = 0
4789 16:53:41.845155 8, 0x0, sum = 1
4790 16:53:41.845223 9, 0x0, sum = 2
4791 16:53:41.848571 10, 0x0, sum = 3
4792 16:53:41.848660 11, 0x0, sum = 4
4793 16:53:41.852056 best_step = 9
4794 16:53:41.852165
4795 16:53:41.852260 ==
4796 16:53:41.855251 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 16:53:41.858737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 16:53:41.858821 ==
4799 16:53:41.862395 RX Vref Scan: 0
4800 16:53:41.862479
4801 16:53:41.862546 RX Vref 0 -> 0, step: 1
4802 16:53:41.862608
4803 16:53:41.865302 RX Delay -163 -> 252, step: 8
4804 16:53:41.872846 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4805 16:53:41.875907 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4806 16:53:41.879106 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4807 16:53:41.882322 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4808 16:53:41.885957 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4809 16:53:41.892611 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4810 16:53:41.895826 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4811 16:53:41.899066 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4812 16:53:41.902613 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4813 16:53:41.905862 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4814 16:53:41.912760 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4815 16:53:41.915787 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4816 16:53:41.918884 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4817 16:53:41.922391 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4818 16:53:41.929180 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4819 16:53:41.932275 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4820 16:53:41.932403 ==
4821 16:53:41.935585 Dram Type= 6, Freq= 0, CH_1, rank 1
4822 16:53:41.939352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4823 16:53:41.939437 ==
4824 16:53:41.942533 DQS Delay:
4825 16:53:41.942617 DQS0 = 0, DQS1 = 0
4826 16:53:41.942684 DQM Delay:
4827 16:53:41.945424 DQM0 = 48, DQM1 = 46
4828 16:53:41.945515 DQ Delay:
4829 16:53:41.949405 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4830 16:53:41.952265 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4831 16:53:41.955628 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4832 16:53:41.959091 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4833 16:53:41.959176
4834 16:53:41.959260
4835 16:53:41.968874 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4836 16:53:41.968960 CH1 RK1: MR19=808, MR18=6A21
4837 16:53:41.975447 CH1_RK1: MR19=0x808, MR18=0x6A21, DQSOSC=389, MR23=63, INC=173, DEC=115
4838 16:53:41.978530 [RxdqsGatingPostProcess] freq 600
4839 16:53:41.985651 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4840 16:53:41.988538 Pre-setting of DQS Precalculation
4841 16:53:41.992253 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4842 16:53:41.998934 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4843 16:53:42.008432 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4844 16:53:42.008514
4845 16:53:42.008583
4846 16:53:42.011861 [Calibration Summary] 1200 Mbps
4847 16:53:42.011935 CH 0, Rank 0
4848 16:53:42.014924 SW Impedance : PASS
4849 16:53:42.014998 DUTY Scan : NO K
4850 16:53:42.018818 ZQ Calibration : PASS
4851 16:53:42.021923 Jitter Meter : NO K
4852 16:53:42.022016 CBT Training : PASS
4853 16:53:42.025433 Write leveling : PASS
4854 16:53:42.025525 RX DQS gating : PASS
4855 16:53:42.028398 RX DQ/DQS(RDDQC) : PASS
4856 16:53:42.032101 TX DQ/DQS : PASS
4857 16:53:42.032186 RX DATLAT : PASS
4858 16:53:42.035103 RX DQ/DQS(Engine): PASS
4859 16:53:42.038877 TX OE : NO K
4860 16:53:42.038962 All Pass.
4861 16:53:42.039030
4862 16:53:42.039091 CH 0, Rank 1
4863 16:53:42.041992 SW Impedance : PASS
4864 16:53:42.045242 DUTY Scan : NO K
4865 16:53:42.045326 ZQ Calibration : PASS
4866 16:53:42.048299 Jitter Meter : NO K
4867 16:53:42.051707 CBT Training : PASS
4868 16:53:42.051805 Write leveling : PASS
4869 16:53:42.054998 RX DQS gating : PASS
4870 16:53:42.058456 RX DQ/DQS(RDDQC) : PASS
4871 16:53:42.058540 TX DQ/DQS : PASS
4872 16:53:42.061966 RX DATLAT : PASS
4873 16:53:42.065449 RX DQ/DQS(Engine): PASS
4874 16:53:42.065576 TX OE : NO K
4875 16:53:42.065644 All Pass.
4876 16:53:42.068453
4877 16:53:42.068537 CH 1, Rank 0
4878 16:53:42.072049 SW Impedance : PASS
4879 16:53:42.072133 DUTY Scan : NO K
4880 16:53:42.075226 ZQ Calibration : PASS
4881 16:53:42.075336 Jitter Meter : NO K
4882 16:53:42.078758 CBT Training : PASS
4883 16:53:42.081783 Write leveling : PASS
4884 16:53:42.081881 RX DQS gating : PASS
4885 16:53:42.084928 RX DQ/DQS(RDDQC) : PASS
4886 16:53:42.088131 TX DQ/DQS : PASS
4887 16:53:42.088215 RX DATLAT : PASS
4888 16:53:42.091344 RX DQ/DQS(Engine): PASS
4889 16:53:42.094960 TX OE : NO K
4890 16:53:42.095045 All Pass.
4891 16:53:42.095111
4892 16:53:42.095173 CH 1, Rank 1
4893 16:53:42.098175 SW Impedance : PASS
4894 16:53:42.101289 DUTY Scan : NO K
4895 16:53:42.101417 ZQ Calibration : PASS
4896 16:53:42.105018 Jitter Meter : NO K
4897 16:53:42.108219 CBT Training : PASS
4898 16:53:42.108365 Write leveling : PASS
4899 16:53:42.111219 RX DQS gating : PASS
4900 16:53:42.114447 RX DQ/DQS(RDDQC) : PASS
4901 16:53:42.114531 TX DQ/DQS : PASS
4902 16:53:42.118174 RX DATLAT : PASS
4903 16:53:42.121476 RX DQ/DQS(Engine): PASS
4904 16:53:42.121579 TX OE : NO K
4905 16:53:42.124715 All Pass.
4906 16:53:42.124799
4907 16:53:42.124865 DramC Write-DBI off
4908 16:53:42.127726 PER_BANK_REFRESH: Hybrid Mode
4909 16:53:42.127810 TX_TRACKING: ON
4910 16:53:42.137919 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4911 16:53:42.140950 [FAST_K] Save calibration result to emmc
4912 16:53:42.144741 dramc_set_vcore_voltage set vcore to 662500
4913 16:53:42.148032 Read voltage for 933, 3
4914 16:53:42.148116 Vio18 = 0
4915 16:53:42.151120 Vcore = 662500
4916 16:53:42.151204 Vdram = 0
4917 16:53:42.151271 Vddq = 0
4918 16:53:42.151333 Vmddr = 0
4919 16:53:42.158019 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4920 16:53:42.164333 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4921 16:53:42.164440 MEM_TYPE=3, freq_sel=17
4922 16:53:42.167774 sv_algorithm_assistance_LP4_1600
4923 16:53:42.171518 ============ PULL DRAM RESETB DOWN ============
4924 16:53:42.177860 ========== PULL DRAM RESETB DOWN end =========
4925 16:53:42.180806 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4926 16:53:42.184380 ===================================
4927 16:53:42.187902 LPDDR4 DRAM CONFIGURATION
4928 16:53:42.191130 ===================================
4929 16:53:42.191234 EX_ROW_EN[0] = 0x0
4930 16:53:42.194326 EX_ROW_EN[1] = 0x0
4931 16:53:42.194428 LP4Y_EN = 0x0
4932 16:53:42.197949 WORK_FSP = 0x0
4933 16:53:42.198021 WL = 0x3
4934 16:53:42.201026 RL = 0x3
4935 16:53:42.204366 BL = 0x2
4936 16:53:42.204440 RPST = 0x0
4937 16:53:42.207513 RD_PRE = 0x0
4938 16:53:42.207622 WR_PRE = 0x1
4939 16:53:42.211203 WR_PST = 0x0
4940 16:53:42.211308 DBI_WR = 0x0
4941 16:53:42.214364 DBI_RD = 0x0
4942 16:53:42.214461 OTF = 0x1
4943 16:53:42.217447 ===================================
4944 16:53:42.220677 ===================================
4945 16:53:42.224486 ANA top config
4946 16:53:42.227628 ===================================
4947 16:53:42.227729 DLL_ASYNC_EN = 0
4948 16:53:42.230859 ALL_SLAVE_EN = 1
4949 16:53:42.233999 NEW_RANK_MODE = 1
4950 16:53:42.237446 DLL_IDLE_MODE = 1
4951 16:53:42.237591 LP45_APHY_COMB_EN = 1
4952 16:53:42.241054 TX_ODT_DIS = 1
4953 16:53:42.243902 NEW_8X_MODE = 1
4954 16:53:42.247574 ===================================
4955 16:53:42.250864 ===================================
4956 16:53:42.254051 data_rate = 1866
4957 16:53:42.257221 CKR = 1
4958 16:53:42.260529 DQ_P2S_RATIO = 8
4959 16:53:42.264211 ===================================
4960 16:53:42.264315 CA_P2S_RATIO = 8
4961 16:53:42.267264 DQ_CA_OPEN = 0
4962 16:53:42.270800 DQ_SEMI_OPEN = 0
4963 16:53:42.273606 CA_SEMI_OPEN = 0
4964 16:53:42.277066 CA_FULL_RATE = 0
4965 16:53:42.280500 DQ_CKDIV4_EN = 1
4966 16:53:42.280584 CA_CKDIV4_EN = 1
4967 16:53:42.283706 CA_PREDIV_EN = 0
4968 16:53:42.287499 PH8_DLY = 0
4969 16:53:42.290315 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4970 16:53:42.293772 DQ_AAMCK_DIV = 4
4971 16:53:42.297263 CA_AAMCK_DIV = 4
4972 16:53:42.297348 CA_ADMCK_DIV = 4
4973 16:53:42.300534 DQ_TRACK_CA_EN = 0
4974 16:53:42.303595 CA_PICK = 933
4975 16:53:42.306857 CA_MCKIO = 933
4976 16:53:42.310620 MCKIO_SEMI = 0
4977 16:53:42.313801 PLL_FREQ = 3732
4978 16:53:42.317421 DQ_UI_PI_RATIO = 32
4979 16:53:42.317514 CA_UI_PI_RATIO = 0
4980 16:53:42.320459 ===================================
4981 16:53:42.323827 ===================================
4982 16:53:42.327468 memory_type:LPDDR4
4983 16:53:42.330599 GP_NUM : 10
4984 16:53:42.330708 SRAM_EN : 1
4985 16:53:42.333830 MD32_EN : 0
4986 16:53:42.337085 ===================================
4987 16:53:42.340152 [ANA_INIT] >>>>>>>>>>>>>>
4988 16:53:42.343628 <<<<<< [CONFIGURE PHASE]: ANA_TX
4989 16:53:42.347296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4990 16:53:42.350808 ===================================
4991 16:53:42.350895 data_rate = 1866,PCW = 0X8f00
4992 16:53:42.353959 ===================================
4993 16:53:42.357154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4994 16:53:42.363627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4995 16:53:42.370294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 16:53:42.373279 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4997 16:53:42.376713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4998 16:53:42.380323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4999 16:53:42.383680 [ANA_INIT] flow start
5000 16:53:42.383765 [ANA_INIT] PLL >>>>>>>>
5001 16:53:42.386580 [ANA_INIT] PLL <<<<<<<<
5002 16:53:42.389922 [ANA_INIT] MIDPI >>>>>>>>
5003 16:53:42.393649 [ANA_INIT] MIDPI <<<<<<<<
5004 16:53:42.393733 [ANA_INIT] DLL >>>>>>>>
5005 16:53:42.396553 [ANA_INIT] flow end
5006 16:53:42.400142 ============ LP4 DIFF to SE enter ============
5007 16:53:42.403375 ============ LP4 DIFF to SE exit ============
5008 16:53:42.406376 [ANA_INIT] <<<<<<<<<<<<<
5009 16:53:42.410244 [Flow] Enable top DCM control >>>>>
5010 16:53:42.413448 [Flow] Enable top DCM control <<<<<
5011 16:53:42.416545 Enable DLL master slave shuffle
5012 16:53:42.423275 ==============================================================
5013 16:53:42.423375 Gating Mode config
5014 16:53:42.429975 ==============================================================
5015 16:53:42.430058 Config description:
5016 16:53:42.440271 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5017 16:53:42.446401 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5018 16:53:42.453053 SELPH_MODE 0: By rank 1: By Phase
5019 16:53:42.456424 ==============================================================
5020 16:53:42.459673 GAT_TRACK_EN = 1
5021 16:53:42.462779 RX_GATING_MODE = 2
5022 16:53:42.466044 RX_GATING_TRACK_MODE = 2
5023 16:53:42.469853 SELPH_MODE = 1
5024 16:53:42.473007 PICG_EARLY_EN = 1
5025 16:53:42.476068 VALID_LAT_VALUE = 1
5026 16:53:42.479702 ==============================================================
5027 16:53:42.483344 Enter into Gating configuration >>>>
5028 16:53:42.486452 Exit from Gating configuration <<<<
5029 16:53:42.489338 Enter into DVFS_PRE_config >>>>>
5030 16:53:42.502654 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5031 16:53:42.506465 Exit from DVFS_PRE_config <<<<<
5032 16:53:42.509473 Enter into PICG configuration >>>>
5033 16:53:42.512489 Exit from PICG configuration <<<<
5034 16:53:42.512602 [RX_INPUT] configuration >>>>>
5035 16:53:42.516228 [RX_INPUT] configuration <<<<<
5036 16:53:42.522509 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5037 16:53:42.525746 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5038 16:53:42.532856 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5039 16:53:42.539241 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5040 16:53:42.546453 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5041 16:53:42.552647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5042 16:53:42.556166 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5043 16:53:42.559123 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5044 16:53:42.562598 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5045 16:53:42.569189 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5046 16:53:42.572396 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5047 16:53:42.576186 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5048 16:53:42.579465 ===================================
5049 16:53:42.582392 LPDDR4 DRAM CONFIGURATION
5050 16:53:42.585965 ===================================
5051 16:53:42.589502 EX_ROW_EN[0] = 0x0
5052 16:53:42.589620 EX_ROW_EN[1] = 0x0
5053 16:53:42.592483 LP4Y_EN = 0x0
5054 16:53:42.592561 WORK_FSP = 0x0
5055 16:53:42.596066 WL = 0x3
5056 16:53:42.596141 RL = 0x3
5057 16:53:42.599216 BL = 0x2
5058 16:53:42.599287 RPST = 0x0
5059 16:53:42.602668 RD_PRE = 0x0
5060 16:53:42.602736 WR_PRE = 0x1
5061 16:53:42.605642 WR_PST = 0x0
5062 16:53:42.605715 DBI_WR = 0x0
5063 16:53:42.609249 DBI_RD = 0x0
5064 16:53:42.609364 OTF = 0x1
5065 16:53:42.612808 ===================================
5066 16:53:42.619339 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5067 16:53:42.622545 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5068 16:53:42.625769 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5069 16:53:42.629521 ===================================
5070 16:53:42.632684 LPDDR4 DRAM CONFIGURATION
5071 16:53:42.635742 ===================================
5072 16:53:42.639393 EX_ROW_EN[0] = 0x10
5073 16:53:42.639476 EX_ROW_EN[1] = 0x0
5074 16:53:42.642614 LP4Y_EN = 0x0
5075 16:53:42.642697 WORK_FSP = 0x0
5076 16:53:42.645912 WL = 0x3
5077 16:53:42.646043 RL = 0x3
5078 16:53:42.649096 BL = 0x2
5079 16:53:42.649180 RPST = 0x0
5080 16:53:42.652224 RD_PRE = 0x0
5081 16:53:42.652307 WR_PRE = 0x1
5082 16:53:42.656173 WR_PST = 0x0
5083 16:53:42.656255 DBI_WR = 0x0
5084 16:53:42.659185 DBI_RD = 0x0
5085 16:53:42.659268 OTF = 0x1
5086 16:53:42.662193 ===================================
5087 16:53:42.669192 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5088 16:53:42.673834 nWR fixed to 30
5089 16:53:42.676891 [ModeRegInit_LP4] CH0 RK0
5090 16:53:42.676999 [ModeRegInit_LP4] CH0 RK1
5091 16:53:42.680124 [ModeRegInit_LP4] CH1 RK0
5092 16:53:42.683274 [ModeRegInit_LP4] CH1 RK1
5093 16:53:42.683383 match AC timing 9
5094 16:53:42.689914 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5095 16:53:42.693504 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5096 16:53:42.696877 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5097 16:53:42.703303 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5098 16:53:42.706452 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5099 16:53:42.706536 ==
5100 16:53:42.710118 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 16:53:42.713167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 16:53:42.713252 ==
5103 16:53:42.719635 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5104 16:53:42.727029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5105 16:53:42.730150 [CA 0] Center 37 (7~68) winsize 62
5106 16:53:42.733237 [CA 1] Center 37 (7~68) winsize 62
5107 16:53:42.736469 [CA 2] Center 34 (4~65) winsize 62
5108 16:53:42.740090 [CA 3] Center 34 (3~65) winsize 63
5109 16:53:42.743126 [CA 4] Center 33 (3~64) winsize 62
5110 16:53:42.746792 [CA 5] Center 32 (2~62) winsize 61
5111 16:53:42.746876
5112 16:53:42.750085 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5113 16:53:42.750170
5114 16:53:42.753013 [CATrainingPosCal] consider 1 rank data
5115 16:53:42.756309 u2DelayCellTimex100 = 270/100 ps
5116 16:53:42.760093 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5117 16:53:42.763273 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5118 16:53:42.766412 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5119 16:53:42.769810 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5120 16:53:42.772898 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5121 16:53:42.779731 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5122 16:53:42.779814
5123 16:53:42.783158 CA PerBit enable=1, Macro0, CA PI delay=32
5124 16:53:42.783261
5125 16:53:42.786116 [CBTSetCACLKResult] CA Dly = 32
5126 16:53:42.786191 CS Dly: 5 (0~36)
5127 16:53:42.786257 ==
5128 16:53:42.789426 Dram Type= 6, Freq= 0, CH_0, rank 1
5129 16:53:42.793074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 16:53:42.793184 ==
5131 16:53:42.799687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5132 16:53:42.806822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5133 16:53:42.809808 [CA 0] Center 37 (6~68) winsize 63
5134 16:53:42.813433 [CA 1] Center 37 (7~68) winsize 62
5135 16:53:42.816386 [CA 2] Center 34 (4~65) winsize 62
5136 16:53:42.819821 [CA 3] Center 34 (3~65) winsize 63
5137 16:53:42.822857 [CA 4] Center 33 (3~64) winsize 62
5138 16:53:42.826490 [CA 5] Center 32 (2~62) winsize 61
5139 16:53:42.826592
5140 16:53:42.829921 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5141 16:53:42.830000
5142 16:53:42.833117 [CATrainingPosCal] consider 2 rank data
5143 16:53:42.836328 u2DelayCellTimex100 = 270/100 ps
5144 16:53:42.839485 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5145 16:53:42.842706 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5146 16:53:42.846293 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5147 16:53:42.849768 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5148 16:53:42.856234 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5149 16:53:42.859433 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5150 16:53:42.859538
5151 16:53:42.862622 CA PerBit enable=1, Macro0, CA PI delay=32
5152 16:53:42.862727
5153 16:53:42.866453 [CBTSetCACLKResult] CA Dly = 32
5154 16:53:42.866566 CS Dly: 5 (0~37)
5155 16:53:42.866659
5156 16:53:42.869793 ----->DramcWriteLeveling(PI) begin...
5157 16:53:42.869870 ==
5158 16:53:42.872613 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 16:53:42.879733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 16:53:42.879816 ==
5161 16:53:42.882783 Write leveling (Byte 0): 31 => 31
5162 16:53:42.882889 Write leveling (Byte 1): 29 => 29
5163 16:53:42.886522 DramcWriteLeveling(PI) end<-----
5164 16:53:42.886598
5165 16:53:42.886663 ==
5166 16:53:42.889790 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 16:53:42.896148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 16:53:42.896254 ==
5169 16:53:42.899201 [Gating] SW mode calibration
5170 16:53:42.905874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5171 16:53:42.909443 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5172 16:53:42.915955 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5173 16:53:42.919480 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 16:53:42.922450 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 16:53:42.929009 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 16:53:42.932814 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 16:53:42.935624 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 16:53:42.942437 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5179 16:53:42.945714 0 14 28 | B1->B0 | 3434 2828 | 0 0 | (0 0) (1 1)
5180 16:53:42.948890 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5181 16:53:42.956030 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 16:53:42.959205 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 16:53:42.962347 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 16:53:42.966260 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 16:53:42.972480 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 16:53:42.975848 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5187 16:53:42.979248 0 15 28 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (0 0)
5188 16:53:42.985719 1 0 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5189 16:53:42.989270 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 16:53:42.992535 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 16:53:42.998977 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 16:53:43.002211 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 16:53:43.005895 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 16:53:43.012307 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 16:53:43.015813 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5196 16:53:43.018826 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5197 16:53:43.025530 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 16:53:43.029101 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 16:53:43.032276 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 16:53:43.038876 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 16:53:43.042412 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 16:53:43.045468 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 16:53:43.051892 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 16:53:43.055058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 16:53:43.059151 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 16:53:43.065395 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 16:53:43.068500 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 16:53:43.071703 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 16:53:43.078559 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 16:53:43.081697 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5211 16:53:43.085735 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5212 16:53:43.091761 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 16:53:43.091851 Total UI for P1: 0, mck2ui 16
5214 16:53:43.098691 best dqsien dly found for B0: ( 1, 2, 26)
5215 16:53:43.098777 Total UI for P1: 0, mck2ui 16
5216 16:53:43.101943 best dqsien dly found for B1: ( 1, 2, 28)
5217 16:53:43.108423 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5218 16:53:43.112093 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5219 16:53:43.112177
5220 16:53:43.114835 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5221 16:53:43.118298 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5222 16:53:43.121806 [Gating] SW calibration Done
5223 16:53:43.121891 ==
5224 16:53:43.125248 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 16:53:43.128078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 16:53:43.128163 ==
5227 16:53:43.131756 RX Vref Scan: 0
5228 16:53:43.131841
5229 16:53:43.131908 RX Vref 0 -> 0, step: 1
5230 16:53:43.131970
5231 16:53:43.135330 RX Delay -80 -> 252, step: 8
5232 16:53:43.138336 iDelay=200, Bit 0, Center 103 (8 ~ 199) 192
5233 16:53:43.144792 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5234 16:53:43.148327 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5235 16:53:43.152058 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5236 16:53:43.155135 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5237 16:53:43.158241 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5238 16:53:43.161500 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5239 16:53:43.168559 iDelay=200, Bit 7, Center 111 (24 ~ 199) 176
5240 16:53:43.171323 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5241 16:53:43.174772 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5242 16:53:43.178028 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5243 16:53:43.181801 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5244 16:53:43.184935 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5245 16:53:43.188130 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5246 16:53:43.194823 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5247 16:53:43.198271 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5248 16:53:43.198355 ==
5249 16:53:43.201841 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 16:53:43.205018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 16:53:43.205103 ==
5252 16:53:43.205170 DQS Delay:
5253 16:53:43.208193 DQS0 = 0, DQS1 = 0
5254 16:53:43.208292 DQM Delay:
5255 16:53:43.211459 DQM0 = 103, DQM1 = 94
5256 16:53:43.211542 DQ Delay:
5257 16:53:43.215268 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5258 16:53:43.218285 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5259 16:53:43.221943 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5260 16:53:43.224900 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5261 16:53:43.224985
5262 16:53:43.225052
5263 16:53:43.225114 ==
5264 16:53:43.228566 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 16:53:43.234820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 16:53:43.234920 ==
5267 16:53:43.235002
5268 16:53:43.235064
5269 16:53:43.235123 TX Vref Scan disable
5270 16:53:43.238615 == TX Byte 0 ==
5271 16:53:43.242137 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5272 16:53:43.245123 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5273 16:53:43.248721 == TX Byte 1 ==
5274 16:53:43.252185 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5275 16:53:43.258842 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5276 16:53:43.258927 ==
5277 16:53:43.262156 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 16:53:43.265266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 16:53:43.265350 ==
5280 16:53:43.265417
5281 16:53:43.265479
5282 16:53:43.268492 TX Vref Scan disable
5283 16:53:43.268616 == TX Byte 0 ==
5284 16:53:43.275341 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5285 16:53:43.278495 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5286 16:53:43.278580 == TX Byte 1 ==
5287 16:53:43.285449 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5288 16:53:43.288891 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5289 16:53:43.288975
5290 16:53:43.289041 [DATLAT]
5291 16:53:43.292038 Freq=933, CH0 RK0
5292 16:53:43.292123
5293 16:53:43.292203 DATLAT Default: 0xd
5294 16:53:43.295057 0, 0xFFFF, sum = 0
5295 16:53:43.295143 1, 0xFFFF, sum = 0
5296 16:53:43.298773 2, 0xFFFF, sum = 0
5297 16:53:43.298858 3, 0xFFFF, sum = 0
5298 16:53:43.301733 4, 0xFFFF, sum = 0
5299 16:53:43.301822 5, 0xFFFF, sum = 0
5300 16:53:43.305275 6, 0xFFFF, sum = 0
5301 16:53:43.308460 7, 0xFFFF, sum = 0
5302 16:53:43.308546 8, 0xFFFF, sum = 0
5303 16:53:43.311768 9, 0xFFFF, sum = 0
5304 16:53:43.311853 10, 0x0, sum = 1
5305 16:53:43.314944 11, 0x0, sum = 2
5306 16:53:43.315029 12, 0x0, sum = 3
5307 16:53:43.315096 13, 0x0, sum = 4
5308 16:53:43.318740 best_step = 11
5309 16:53:43.318824
5310 16:53:43.318891 ==
5311 16:53:43.322060 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 16:53:43.325009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 16:53:43.325093 ==
5314 16:53:43.328748 RX Vref Scan: 1
5315 16:53:43.328831
5316 16:53:43.328897 RX Vref 0 -> 0, step: 1
5317 16:53:43.331718
5318 16:53:43.331830 RX Delay -45 -> 252, step: 4
5319 16:53:43.331927
5320 16:53:43.335323 Set Vref, RX VrefLevel [Byte0]: 57
5321 16:53:43.338054 [Byte1]: 51
5322 16:53:43.343095
5323 16:53:43.343177 Final RX Vref Byte 0 = 57 to rank0
5324 16:53:43.346193 Final RX Vref Byte 1 = 51 to rank0
5325 16:53:43.348915 Final RX Vref Byte 0 = 57 to rank1
5326 16:53:43.352392 Final RX Vref Byte 1 = 51 to rank1==
5327 16:53:43.356094 Dram Type= 6, Freq= 0, CH_0, rank 0
5328 16:53:43.362597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 16:53:43.362683 ==
5330 16:53:43.362750 DQS Delay:
5331 16:53:43.362831 DQS0 = 0, DQS1 = 0
5332 16:53:43.365729 DQM Delay:
5333 16:53:43.365832 DQM0 = 105, DQM1 = 96
5334 16:53:43.369041 DQ Delay:
5335 16:53:43.372174 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5336 16:53:43.376026 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =110
5337 16:53:43.379045 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =90
5338 16:53:43.382279 DQ12 =100, DQ13 =100, DQ14 =108, DQ15 =104
5339 16:53:43.382391
5340 16:53:43.382490
5341 16:53:43.389094 [DQSOSCAuto] RK0, (LSB)MR18= 0x322b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5342 16:53:43.392366 CH0 RK0: MR19=505, MR18=322B
5343 16:53:43.398697 CH0_RK0: MR19=0x505, MR18=0x322B, DQSOSC=406, MR23=63, INC=65, DEC=43
5344 16:53:43.398807
5345 16:53:43.402526 ----->DramcWriteLeveling(PI) begin...
5346 16:53:43.402626 ==
5347 16:53:43.405486 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 16:53:43.409109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 16:53:43.412010 ==
5350 16:53:43.412095 Write leveling (Byte 0): 33 => 33
5351 16:53:43.415318 Write leveling (Byte 1): 32 => 32
5352 16:53:43.418970 DramcWriteLeveling(PI) end<-----
5353 16:53:43.419054
5354 16:53:43.419120 ==
5355 16:53:43.422134 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 16:53:43.428563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 16:53:43.428648 ==
5358 16:53:43.428715 [Gating] SW mode calibration
5359 16:53:43.438838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5360 16:53:43.442230 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5361 16:53:43.445569 0 14 0 | B1->B0 | 3333 3232 | 1 1 | (0 0) (0 0)
5362 16:53:43.452245 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 16:53:43.455311 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 16:53:43.458877 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 16:53:43.465314 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 16:53:43.468790 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 16:53:43.471999 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 16:53:43.478944 0 14 28 | B1->B0 | 2929 2c2c | 0 1 | (0 0) (1 0)
5369 16:53:43.482031 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5370 16:53:43.485096 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 16:53:43.492015 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 16:53:43.495837 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 16:53:43.498344 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 16:53:43.505683 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 16:53:43.508515 0 15 24 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
5376 16:53:43.511750 0 15 28 | B1->B0 | 3a3a 3e3e | 1 1 | (0 0) (0 0)
5377 16:53:43.518659 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 16:53:43.521864 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 16:53:43.525132 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 16:53:43.532084 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 16:53:43.535303 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 16:53:43.538448 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 16:53:43.545156 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5384 16:53:43.548733 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5385 16:53:43.551635 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5386 16:53:43.558230 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 16:53:43.561765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 16:53:43.565461 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 16:53:43.568433 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 16:53:43.574854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 16:53:43.578676 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 16:53:43.581979 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 16:53:43.588749 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 16:53:43.591893 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 16:53:43.594910 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 16:53:43.601804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 16:53:43.605003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 16:53:43.608137 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 16:53:43.614988 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5400 16:53:43.618544 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5401 16:53:43.621446 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 16:53:43.625053 Total UI for P1: 0, mck2ui 16
5403 16:53:43.628062 best dqsien dly found for B0: ( 1, 2, 26)
5404 16:53:43.631390 Total UI for P1: 0, mck2ui 16
5405 16:53:43.635214 best dqsien dly found for B1: ( 1, 2, 28)
5406 16:53:43.637926 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5407 16:53:43.641656 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5408 16:53:43.641771
5409 16:53:43.648239 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5410 16:53:43.651268 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5411 16:53:43.651353 [Gating] SW calibration Done
5412 16:53:43.654913 ==
5413 16:53:43.657981 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 16:53:43.661498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 16:53:43.661619 ==
5416 16:53:43.661685 RX Vref Scan: 0
5417 16:53:43.661747
5418 16:53:43.664688 RX Vref 0 -> 0, step: 1
5419 16:53:43.664770
5420 16:53:43.668302 RX Delay -80 -> 252, step: 8
5421 16:53:43.671334 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5422 16:53:43.674968 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5423 16:53:43.678421 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5424 16:53:43.684751 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5425 16:53:43.688415 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5426 16:53:43.691402 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5427 16:53:43.694690 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5428 16:53:43.698443 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5429 16:53:43.701502 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5430 16:53:43.708312 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5431 16:53:43.711562 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5432 16:53:43.714697 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5433 16:53:43.718561 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5434 16:53:43.721851 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5435 16:53:43.725300 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5436 16:53:43.728210 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5437 16:53:43.731785 ==
5438 16:53:43.734759 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 16:53:43.738537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 16:53:43.738622 ==
5441 16:53:43.738689 DQS Delay:
5442 16:53:43.741803 DQS0 = 0, DQS1 = 0
5443 16:53:43.741887 DQM Delay:
5444 16:53:43.744961 DQM0 = 105, DQM1 = 94
5445 16:53:43.745043 DQ Delay:
5446 16:53:43.748191 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5447 16:53:43.751708 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5448 16:53:43.755322 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5449 16:53:43.758226 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5450 16:53:43.758310
5451 16:53:43.758376
5452 16:53:43.758438 ==
5453 16:53:43.761730 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 16:53:43.764598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 16:53:43.764683 ==
5456 16:53:43.768102
5457 16:53:43.768203
5458 16:53:43.768283 TX Vref Scan disable
5459 16:53:43.771248 == TX Byte 0 ==
5460 16:53:43.775020 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5461 16:53:43.778425 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5462 16:53:43.781384 == TX Byte 1 ==
5463 16:53:43.784960 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5464 16:53:43.787957 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5465 16:53:43.788041 ==
5466 16:53:43.791791 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 16:53:43.797927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 16:53:43.798017 ==
5469 16:53:43.798120
5470 16:53:43.798182
5471 16:53:43.798241 TX Vref Scan disable
5472 16:53:43.802552 == TX Byte 0 ==
5473 16:53:43.805653 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5474 16:53:43.812463 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5475 16:53:43.812552 == TX Byte 1 ==
5476 16:53:43.815795 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5477 16:53:43.822156 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5478 16:53:43.822243
5479 16:53:43.822310 [DATLAT]
5480 16:53:43.822372 Freq=933, CH0 RK1
5481 16:53:43.822433
5482 16:53:43.825375 DATLAT Default: 0xb
5483 16:53:43.825459 0, 0xFFFF, sum = 0
5484 16:53:43.829206 1, 0xFFFF, sum = 0
5485 16:53:43.829292 2, 0xFFFF, sum = 0
5486 16:53:43.832206 3, 0xFFFF, sum = 0
5487 16:53:43.835821 4, 0xFFFF, sum = 0
5488 16:53:43.835907 5, 0xFFFF, sum = 0
5489 16:53:43.839362 6, 0xFFFF, sum = 0
5490 16:53:43.839448 7, 0xFFFF, sum = 0
5491 16:53:43.842141 8, 0xFFFF, sum = 0
5492 16:53:43.842227 9, 0xFFFF, sum = 0
5493 16:53:43.845231 10, 0x0, sum = 1
5494 16:53:43.845317 11, 0x0, sum = 2
5495 16:53:43.849074 12, 0x0, sum = 3
5496 16:53:43.849160 13, 0x0, sum = 4
5497 16:53:43.849227 best_step = 11
5498 16:53:43.849290
5499 16:53:43.852352 ==
5500 16:53:43.855335 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 16:53:43.858855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 16:53:43.858942 ==
5503 16:53:43.859009 RX Vref Scan: 0
5504 16:53:43.859071
5505 16:53:43.862399 RX Vref 0 -> 0, step: 1
5506 16:53:43.862526
5507 16:53:43.865291 RX Delay -45 -> 252, step: 4
5508 16:53:43.868804 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5509 16:53:43.875427 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5510 16:53:43.878546 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5511 16:53:43.881817 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5512 16:53:43.885383 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5513 16:53:43.888392 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5514 16:53:43.895005 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5515 16:53:43.898818 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5516 16:53:43.901850 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5517 16:53:43.905174 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5518 16:53:43.908217 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5519 16:53:43.911976 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5520 16:53:43.918267 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5521 16:53:43.921487 iDelay=199, Bit 13, Center 102 (19 ~ 186) 168
5522 16:53:43.925240 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5523 16:53:43.928402 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5524 16:53:43.928481 ==
5525 16:53:43.931709 Dram Type= 6, Freq= 0, CH_0, rank 1
5526 16:53:43.938521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 16:53:43.938599 ==
5528 16:53:43.938664 DQS Delay:
5529 16:53:43.941785 DQS0 = 0, DQS1 = 0
5530 16:53:43.941859 DQM Delay:
5531 16:53:43.944704 DQM0 = 105, DQM1 = 95
5532 16:53:43.944778 DQ Delay:
5533 16:53:43.948498 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5534 16:53:43.951868 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5535 16:53:43.955107 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5536 16:53:43.958165 DQ12 =100, DQ13 =102, DQ14 =106, DQ15 =102
5537 16:53:43.958263
5538 16:53:43.958331
5539 16:53:43.968097 [DQSOSCAuto] RK1, (LSB)MR18= 0x26ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5540 16:53:43.968178 CH0 RK1: MR19=504, MR18=26FF
5541 16:53:43.974846 CH0_RK1: MR19=0x504, MR18=0x26FF, DQSOSC=409, MR23=63, INC=64, DEC=43
5542 16:53:43.977937 [RxdqsGatingPostProcess] freq 933
5543 16:53:43.984552 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5544 16:53:43.988091 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 16:53:43.991168 best DQS1 dly(2T, 0.5T) = (0, 10)
5546 16:53:43.994628 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 16:53:43.997704 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5548 16:53:43.997816 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 16:53:44.001166 best DQS1 dly(2T, 0.5T) = (0, 10)
5550 16:53:44.004635 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 16:53:44.007851 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5552 16:53:44.010945 Pre-setting of DQS Precalculation
5553 16:53:44.018007 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5554 16:53:44.018128 ==
5555 16:53:44.021196 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 16:53:44.024805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 16:53:44.024880 ==
5558 16:53:44.031182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 16:53:44.038036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5560 16:53:44.040935 [CA 0] Center 36 (6~67) winsize 62
5561 16:53:44.044184 [CA 1] Center 37 (6~68) winsize 63
5562 16:53:44.047983 [CA 2] Center 34 (4~65) winsize 62
5563 16:53:44.051004 [CA 3] Center 34 (4~65) winsize 62
5564 16:53:44.054694 [CA 4] Center 34 (4~65) winsize 62
5565 16:53:44.054809 [CA 5] Center 33 (3~64) winsize 62
5566 16:53:44.057449
5567 16:53:44.061290 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5568 16:53:44.061374
5569 16:53:44.064132 [CATrainingPosCal] consider 1 rank data
5570 16:53:44.067412 u2DelayCellTimex100 = 270/100 ps
5571 16:53:44.070663 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5572 16:53:44.074411 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5573 16:53:44.077255 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5574 16:53:44.080806 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5575 16:53:44.084398 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5576 16:53:44.087904 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5577 16:53:44.087987
5578 16:53:44.090968 CA PerBit enable=1, Macro0, CA PI delay=33
5579 16:53:44.093867
5580 16:53:44.093950 [CBTSetCACLKResult] CA Dly = 33
5581 16:53:44.097321 CS Dly: 6 (0~37)
5582 16:53:44.097405 ==
5583 16:53:44.100505 Dram Type= 6, Freq= 0, CH_1, rank 1
5584 16:53:44.103866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 16:53:44.103951 ==
5586 16:53:44.110654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5587 16:53:44.117488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5588 16:53:44.120547 [CA 0] Center 36 (6~67) winsize 62
5589 16:53:44.123717 [CA 1] Center 37 (7~68) winsize 62
5590 16:53:44.126952 [CA 2] Center 35 (5~65) winsize 61
5591 16:53:44.130382 [CA 3] Center 34 (4~65) winsize 62
5592 16:53:44.133713 [CA 4] Center 34 (4~65) winsize 62
5593 16:53:44.137501 [CA 5] Center 33 (3~64) winsize 62
5594 16:53:44.137621
5595 16:53:44.140648 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5596 16:53:44.140750
5597 16:53:44.143624 [CATrainingPosCal] consider 2 rank data
5598 16:53:44.147314 u2DelayCellTimex100 = 270/100 ps
5599 16:53:44.150440 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5600 16:53:44.153655 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5601 16:53:44.157469 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5602 16:53:44.160533 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5603 16:53:44.163681 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5604 16:53:44.166926 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5605 16:53:44.167073
5606 16:53:44.173400 CA PerBit enable=1, Macro0, CA PI delay=33
5607 16:53:44.173483
5608 16:53:44.176697 [CBTSetCACLKResult] CA Dly = 33
5609 16:53:44.176780 CS Dly: 7 (0~40)
5610 16:53:44.176846
5611 16:53:44.180369 ----->DramcWriteLeveling(PI) begin...
5612 16:53:44.180455 ==
5613 16:53:44.183345 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 16:53:44.187022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 16:53:44.187106 ==
5616 16:53:44.190370 Write leveling (Byte 0): 25 => 25
5617 16:53:44.193304 Write leveling (Byte 1): 26 => 26
5618 16:53:44.196630 DramcWriteLeveling(PI) end<-----
5619 16:53:44.196713
5620 16:53:44.196809 ==
5621 16:53:44.200227 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 16:53:44.206716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 16:53:44.206808 ==
5624 16:53:44.206875 [Gating] SW mode calibration
5625 16:53:44.216705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5626 16:53:44.220124 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5627 16:53:44.223210 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 16:53:44.230232 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 16:53:44.233385 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 16:53:44.236956 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 16:53:44.243330 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 16:53:44.247092 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5633 16:53:44.250025 0 14 24 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
5634 16:53:44.256353 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
5635 16:53:44.259763 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 16:53:44.263155 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 16:53:44.269932 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 16:53:44.272978 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 16:53:44.276697 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 16:53:44.283032 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 16:53:44.286186 0 15 24 | B1->B0 | 2727 3636 | 0 1 | (0 0) (0 0)
5642 16:53:44.289875 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5643 16:53:44.296147 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 16:53:44.299729 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 16:53:44.303149 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 16:53:44.309774 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 16:53:44.313187 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 16:53:44.316147 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5649 16:53:44.323128 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5650 16:53:44.326071 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 16:53:44.329656 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 16:53:44.336711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 16:53:44.339710 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 16:53:44.342766 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 16:53:44.349329 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 16:53:44.352958 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 16:53:44.356077 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 16:53:44.359191 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 16:53:44.366026 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 16:53:44.369261 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 16:53:44.372999 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 16:53:44.379517 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 16:53:44.382736 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 16:53:44.385804 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5665 16:53:44.392871 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5666 16:53:44.395861 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5667 16:53:44.399058 Total UI for P1: 0, mck2ui 16
5668 16:53:44.402645 best dqsien dly found for B0: ( 1, 2, 24)
5669 16:53:44.406049 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 16:53:44.409172 Total UI for P1: 0, mck2ui 16
5671 16:53:44.412504 best dqsien dly found for B1: ( 1, 2, 24)
5672 16:53:44.416178 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5673 16:53:44.419299 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5674 16:53:44.419425
5675 16:53:44.425721 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5676 16:53:44.429365 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5677 16:53:44.432289 [Gating] SW calibration Done
5678 16:53:44.432441 ==
5679 16:53:44.435699 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 16:53:44.438909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 16:53:44.439017 ==
5682 16:53:44.439112 RX Vref Scan: 0
5683 16:53:44.439213
5684 16:53:44.442760 RX Vref 0 -> 0, step: 1
5685 16:53:44.442864
5686 16:53:44.445899 RX Delay -80 -> 252, step: 8
5687 16:53:44.449221 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5688 16:53:44.452455 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5689 16:53:44.456041 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5690 16:53:44.462413 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5691 16:53:44.465699 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5692 16:53:44.469432 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5693 16:53:44.472315 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5694 16:53:44.476187 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5695 16:53:44.479304 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5696 16:53:44.485970 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5697 16:53:44.489057 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5698 16:53:44.492262 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5699 16:53:44.496103 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5700 16:53:44.499143 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5701 16:53:44.505920 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5702 16:53:44.508911 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5703 16:53:44.509015 ==
5704 16:53:44.512452 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 16:53:44.515460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 16:53:44.515538 ==
5707 16:53:44.515605 DQS Delay:
5708 16:53:44.518894 DQS0 = 0, DQS1 = 0
5709 16:53:44.518971 DQM Delay:
5710 16:53:44.522573 DQM0 = 103, DQM1 = 98
5711 16:53:44.522659 DQ Delay:
5712 16:53:44.525387 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5713 16:53:44.529119 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5714 16:53:44.532589 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5715 16:53:44.535419 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5716 16:53:44.535529
5717 16:53:44.535629
5718 16:53:44.535722 ==
5719 16:53:44.539089 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 16:53:44.545720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 16:53:44.545833 ==
5722 16:53:44.545931
5723 16:53:44.546024
5724 16:53:44.548873 TX Vref Scan disable
5725 16:53:44.548975 == TX Byte 0 ==
5726 16:53:44.552036 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5727 16:53:44.558730 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5728 16:53:44.558846 == TX Byte 1 ==
5729 16:53:44.562305 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5730 16:53:44.568679 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5731 16:53:44.568761 ==
5732 16:53:44.572011 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 16:53:44.575582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 16:53:44.575686 ==
5735 16:53:44.575779
5736 16:53:44.575871
5737 16:53:44.578670 TX Vref Scan disable
5738 16:53:44.582112 == TX Byte 0 ==
5739 16:53:44.585820 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5740 16:53:44.588927 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5741 16:53:44.591954 == TX Byte 1 ==
5742 16:53:44.595127 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5743 16:53:44.598968 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5744 16:53:44.599077
5745 16:53:44.599171 [DATLAT]
5746 16:53:44.602097 Freq=933, CH1 RK0
5747 16:53:44.602198
5748 16:53:44.602291 DATLAT Default: 0xd
5749 16:53:44.605186 0, 0xFFFF, sum = 0
5750 16:53:44.608966 1, 0xFFFF, sum = 0
5751 16:53:44.609039 2, 0xFFFF, sum = 0
5752 16:53:44.611955 3, 0xFFFF, sum = 0
5753 16:53:44.612029 4, 0xFFFF, sum = 0
5754 16:53:44.615602 5, 0xFFFF, sum = 0
5755 16:53:44.615687 6, 0xFFFF, sum = 0
5756 16:53:44.618462 7, 0xFFFF, sum = 0
5757 16:53:44.618552 8, 0xFFFF, sum = 0
5758 16:53:44.622008 9, 0xFFFF, sum = 0
5759 16:53:44.622086 10, 0x0, sum = 1
5760 16:53:44.625549 11, 0x0, sum = 2
5761 16:53:44.625644 12, 0x0, sum = 3
5762 16:53:44.628617 13, 0x0, sum = 4
5763 16:53:44.628692 best_step = 11
5764 16:53:44.628755
5765 16:53:44.628819 ==
5766 16:53:44.632106 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 16:53:44.635177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 16:53:44.635281 ==
5769 16:53:44.638746 RX Vref Scan: 1
5770 16:53:44.638849
5771 16:53:44.641694 RX Vref 0 -> 0, step: 1
5772 16:53:44.641799
5773 16:53:44.641892 RX Delay -45 -> 252, step: 4
5774 16:53:44.641980
5775 16:53:44.645197 Set Vref, RX VrefLevel [Byte0]: 53
5776 16:53:44.648216 [Byte1]: 50
5777 16:53:44.653244
5778 16:53:44.653377 Final RX Vref Byte 0 = 53 to rank0
5779 16:53:44.656390 Final RX Vref Byte 1 = 50 to rank0
5780 16:53:44.659665 Final RX Vref Byte 0 = 53 to rank1
5781 16:53:44.663303 Final RX Vref Byte 1 = 50 to rank1==
5782 16:53:44.666394 Dram Type= 6, Freq= 0, CH_1, rank 0
5783 16:53:44.673136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 16:53:44.673250 ==
5785 16:53:44.673351 DQS Delay:
5786 16:53:44.673443 DQS0 = 0, DQS1 = 0
5787 16:53:44.676359 DQM Delay:
5788 16:53:44.676459 DQM0 = 103, DQM1 = 100
5789 16:53:44.680020 DQ Delay:
5790 16:53:44.683220 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =102
5791 16:53:44.686358 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5792 16:53:44.689687 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =94
5793 16:53:44.692831 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5794 16:53:44.692937
5795 16:53:44.693038
5796 16:53:44.700063 [DQSOSCAuto] RK0, (LSB)MR18= 0x152d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
5797 16:53:44.703307 CH1 RK0: MR19=505, MR18=152D
5798 16:53:44.709487 CH1_RK0: MR19=0x505, MR18=0x152D, DQSOSC=407, MR23=63, INC=65, DEC=43
5799 16:53:44.709649
5800 16:53:44.712663 ----->DramcWriteLeveling(PI) begin...
5801 16:53:44.712771 ==
5802 16:53:44.716484 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 16:53:44.719498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 16:53:44.723021 ==
5805 16:53:44.723105 Write leveling (Byte 0): 27 => 27
5806 16:53:44.726083 Write leveling (Byte 1): 30 => 30
5807 16:53:44.729687 DramcWriteLeveling(PI) end<-----
5808 16:53:44.729788
5809 16:53:44.729869 ==
5810 16:53:44.732704 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 16:53:44.739264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 16:53:44.739377 ==
5813 16:53:44.739479 [Gating] SW mode calibration
5814 16:53:44.749176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5815 16:53:44.752638 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5816 16:53:44.758918 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 16:53:44.762717 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 16:53:44.765958 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 16:53:44.772271 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 16:53:44.776131 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 16:53:44.779185 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 16:53:44.785890 0 14 24 | B1->B0 | 2a2a 2f2f | 0 1 | (0 0) (1 1)
5823 16:53:44.789077 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
5824 16:53:44.792221 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 16:53:44.796078 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 16:53:44.802515 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 16:53:44.805919 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 16:53:44.809157 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 16:53:44.815470 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 16:53:44.818551 0 15 24 | B1->B0 | 3636 2828 | 0 0 | (0 0) (0 0)
5831 16:53:44.822424 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5832 16:53:44.829135 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 16:53:44.832192 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 16:53:44.835669 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 16:53:44.842171 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 16:53:44.845751 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 16:53:44.848889 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 16:53:44.855296 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5839 16:53:44.858965 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5840 16:53:44.861957 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 16:53:44.868807 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 16:53:44.872102 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 16:53:44.875187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 16:53:44.882152 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 16:53:44.885190 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 16:53:44.888852 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 16:53:44.895212 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 16:53:44.898987 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 16:53:44.902189 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 16:53:44.908332 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 16:53:44.912248 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 16:53:44.915321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 16:53:44.918373 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 16:53:44.925408 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5855 16:53:44.928658 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 16:53:44.931704 Total UI for P1: 0, mck2ui 16
5857 16:53:44.935265 best dqsien dly found for B0: ( 1, 2, 26)
5858 16:53:44.938864 Total UI for P1: 0, mck2ui 16
5859 16:53:44.941846 best dqsien dly found for B1: ( 1, 2, 24)
5860 16:53:44.945358 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5861 16:53:44.948422 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5862 16:53:44.948507
5863 16:53:44.952069 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5864 16:53:44.955614 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5865 16:53:44.958707 [Gating] SW calibration Done
5866 16:53:44.958825 ==
5867 16:53:44.961800 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 16:53:44.968311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 16:53:44.968396 ==
5870 16:53:44.968464 RX Vref Scan: 0
5871 16:53:44.968527
5872 16:53:44.972045 RX Vref 0 -> 0, step: 1
5873 16:53:44.972129
5874 16:53:44.975241 RX Delay -80 -> 252, step: 8
5875 16:53:44.978389 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5876 16:53:44.981447 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5877 16:53:44.985163 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5878 16:53:44.988178 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5879 16:53:44.995416 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5880 16:53:44.998615 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5881 16:53:45.001729 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5882 16:53:45.004916 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5883 16:53:45.008057 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5884 16:53:45.011253 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5885 16:53:45.017948 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5886 16:53:45.021737 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5887 16:53:45.024765 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5888 16:53:45.028011 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5889 16:53:45.031343 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5890 16:53:45.038111 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5891 16:53:45.038200 ==
5892 16:53:45.041269 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 16:53:45.044875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 16:53:45.044959 ==
5895 16:53:45.045025 DQS Delay:
5896 16:53:45.047848 DQS0 = 0, DQS1 = 0
5897 16:53:45.047931 DQM Delay:
5898 16:53:45.050912 DQM0 = 103, DQM1 = 98
5899 16:53:45.050996 DQ Delay:
5900 16:53:45.054463 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =95
5901 16:53:45.058094 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5902 16:53:45.061215 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5903 16:53:45.064166 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5904 16:53:45.064253
5905 16:53:45.064329
5906 16:53:45.064424 ==
5907 16:53:45.067794 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 16:53:45.074409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 16:53:45.074564 ==
5910 16:53:45.074672
5911 16:53:45.074764
5912 16:53:45.074883 TX Vref Scan disable
5913 16:53:45.077493 == TX Byte 0 ==
5914 16:53:45.080740 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5915 16:53:45.087399 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5916 16:53:45.087487 == TX Byte 1 ==
5917 16:53:45.090680 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5918 16:53:45.097878 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5919 16:53:45.097967 ==
5920 16:53:45.100796 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 16:53:45.104010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 16:53:45.104092 ==
5923 16:53:45.104178
5924 16:53:45.104256
5925 16:53:45.107797 TX Vref Scan disable
5926 16:53:45.107891 == TX Byte 0 ==
5927 16:53:45.114316 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5928 16:53:45.117436 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5929 16:53:45.117519 == TX Byte 1 ==
5930 16:53:45.124162 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5931 16:53:45.127178 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5932 16:53:45.127276
5933 16:53:45.127343 [DATLAT]
5934 16:53:45.130924 Freq=933, CH1 RK1
5935 16:53:45.131038
5936 16:53:45.131139 DATLAT Default: 0xb
5937 16:53:45.134236 0, 0xFFFF, sum = 0
5938 16:53:45.134347 1, 0xFFFF, sum = 0
5939 16:53:45.137312 2, 0xFFFF, sum = 0
5940 16:53:45.137430 3, 0xFFFF, sum = 0
5941 16:53:45.140621 4, 0xFFFF, sum = 0
5942 16:53:45.143754 5, 0xFFFF, sum = 0
5943 16:53:45.143866 6, 0xFFFF, sum = 0
5944 16:53:45.147246 7, 0xFFFF, sum = 0
5945 16:53:45.147354 8, 0xFFFF, sum = 0
5946 16:53:45.150631 9, 0xFFFF, sum = 0
5947 16:53:45.150717 10, 0x0, sum = 1
5948 16:53:45.153770 11, 0x0, sum = 2
5949 16:53:45.153898 12, 0x0, sum = 3
5950 16:53:45.154004 13, 0x0, sum = 4
5951 16:53:45.157305 best_step = 11
5952 16:53:45.157405
5953 16:53:45.157505 ==
5954 16:53:45.160312 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 16:53:45.164085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 16:53:45.164170 ==
5957 16:53:45.167038 RX Vref Scan: 0
5958 16:53:45.167122
5959 16:53:45.170540 RX Vref 0 -> 0, step: 1
5960 16:53:45.170624
5961 16:53:45.170691 RX Delay -45 -> 252, step: 4
5962 16:53:45.178430 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5963 16:53:45.181391 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5964 16:53:45.184596 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5965 16:53:45.187832 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5966 16:53:45.191323 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5967 16:53:45.197704 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5968 16:53:45.201354 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5969 16:53:45.204873 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5970 16:53:45.207973 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5971 16:53:45.211202 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5972 16:53:45.214975 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5973 16:53:45.221360 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5974 16:53:45.224496 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5975 16:53:45.228198 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5976 16:53:45.231075 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5977 16:53:45.238106 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5978 16:53:45.238191 ==
5979 16:53:45.241212 Dram Type= 6, Freq= 0, CH_1, rank 1
5980 16:53:45.244411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5981 16:53:45.244568 ==
5982 16:53:45.244660 DQS Delay:
5983 16:53:45.248310 DQS0 = 0, DQS1 = 0
5984 16:53:45.248433 DQM Delay:
5985 16:53:45.251432 DQM0 = 104, DQM1 = 99
5986 16:53:45.251516 DQ Delay:
5987 16:53:45.254271 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5988 16:53:45.257756 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5989 16:53:45.261169 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =94
5990 16:53:45.264872 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5991 16:53:45.264951
5992 16:53:45.265017
5993 16:53:45.274428 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5994 16:53:45.274523 CH1 RK1: MR19=505, MR18=2C00
5995 16:53:45.281452 CH1_RK1: MR19=0x505, MR18=0x2C00, DQSOSC=408, MR23=63, INC=65, DEC=43
5996 16:53:45.284313 [RxdqsGatingPostProcess] freq 933
5997 16:53:45.290837 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5998 16:53:45.294657 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 16:53:45.297838 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 16:53:45.300918 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 16:53:45.304227 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 16:53:45.307753 best DQS0 dly(2T, 0.5T) = (0, 10)
6003 16:53:45.311438 best DQS1 dly(2T, 0.5T) = (0, 10)
6004 16:53:45.314322 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6005 16:53:45.314400 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6006 16:53:45.317554 Pre-setting of DQS Precalculation
6007 16:53:45.324466 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6008 16:53:45.330841 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6009 16:53:45.337664 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6010 16:53:45.337748
6011 16:53:45.337815
6012 16:53:45.340951 [Calibration Summary] 1866 Mbps
6013 16:53:45.344140 CH 0, Rank 0
6014 16:53:45.344224 SW Impedance : PASS
6015 16:53:45.347973 DUTY Scan : NO K
6016 16:53:45.348057 ZQ Calibration : PASS
6017 16:53:45.351182 Jitter Meter : NO K
6018 16:53:45.354421 CBT Training : PASS
6019 16:53:45.354509 Write leveling : PASS
6020 16:53:45.357750 RX DQS gating : PASS
6021 16:53:45.361248 RX DQ/DQS(RDDQC) : PASS
6022 16:53:45.361331 TX DQ/DQS : PASS
6023 16:53:45.364272 RX DATLAT : PASS
6024 16:53:45.367851 RX DQ/DQS(Engine): PASS
6025 16:53:45.367934 TX OE : NO K
6026 16:53:45.370795 All Pass.
6027 16:53:45.370982
6028 16:53:45.371051 CH 0, Rank 1
6029 16:53:45.374392 SW Impedance : PASS
6030 16:53:45.374476 DUTY Scan : NO K
6031 16:53:45.377320 ZQ Calibration : PASS
6032 16:53:45.380955 Jitter Meter : NO K
6033 16:53:45.381038 CBT Training : PASS
6034 16:53:45.384613 Write leveling : PASS
6035 16:53:45.387591 RX DQS gating : PASS
6036 16:53:45.387675 RX DQ/DQS(RDDQC) : PASS
6037 16:53:45.391015 TX DQ/DQS : PASS
6038 16:53:45.394030 RX DATLAT : PASS
6039 16:53:45.394115 RX DQ/DQS(Engine): PASS
6040 16:53:45.397248 TX OE : NO K
6041 16:53:45.397333 All Pass.
6042 16:53:45.397400
6043 16:53:45.400962 CH 1, Rank 0
6044 16:53:45.401046 SW Impedance : PASS
6045 16:53:45.404001 DUTY Scan : NO K
6046 16:53:45.404085 ZQ Calibration : PASS
6047 16:53:45.407234 Jitter Meter : NO K
6048 16:53:45.410605 CBT Training : PASS
6049 16:53:45.410770 Write leveling : PASS
6050 16:53:45.414217 RX DQS gating : PASS
6051 16:53:45.417289 RX DQ/DQS(RDDQC) : PASS
6052 16:53:45.417378 TX DQ/DQS : PASS
6053 16:53:45.420491 RX DATLAT : PASS
6054 16:53:45.424222 RX DQ/DQS(Engine): PASS
6055 16:53:45.424306 TX OE : NO K
6056 16:53:45.427397 All Pass.
6057 16:53:45.427480
6058 16:53:45.427547 CH 1, Rank 1
6059 16:53:45.430538 SW Impedance : PASS
6060 16:53:45.430664 DUTY Scan : NO K
6061 16:53:45.433756 ZQ Calibration : PASS
6062 16:53:45.437136 Jitter Meter : NO K
6063 16:53:45.437219 CBT Training : PASS
6064 16:53:45.440355 Write leveling : PASS
6065 16:53:45.443937 RX DQS gating : PASS
6066 16:53:45.444021 RX DQ/DQS(RDDQC) : PASS
6067 16:53:45.447426 TX DQ/DQS : PASS
6068 16:53:45.450583 RX DATLAT : PASS
6069 16:53:45.450683 RX DQ/DQS(Engine): PASS
6070 16:53:45.453768 TX OE : NO K
6071 16:53:45.453854 All Pass.
6072 16:53:45.453921
6073 16:53:45.456888 DramC Write-DBI off
6074 16:53:45.460158 PER_BANK_REFRESH: Hybrid Mode
6075 16:53:45.460248 TX_TRACKING: ON
6076 16:53:45.470549 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6077 16:53:45.474007 [FAST_K] Save calibration result to emmc
6078 16:53:45.476969 dramc_set_vcore_voltage set vcore to 650000
6079 16:53:45.480027 Read voltage for 400, 6
6080 16:53:45.480111 Vio18 = 0
6081 16:53:45.480177 Vcore = 650000
6082 16:53:45.483555 Vdram = 0
6083 16:53:45.483638 Vddq = 0
6084 16:53:45.483704 Vmddr = 0
6085 16:53:45.490009 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6086 16:53:45.493531 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6087 16:53:45.496608 MEM_TYPE=3, freq_sel=20
6088 16:53:45.500120 sv_algorithm_assistance_LP4_800
6089 16:53:45.503026 ============ PULL DRAM RESETB DOWN ============
6090 16:53:45.506585 ========== PULL DRAM RESETB DOWN end =========
6091 16:53:45.512838 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6092 16:53:45.516802 ===================================
6093 16:53:45.519748 LPDDR4 DRAM CONFIGURATION
6094 16:53:45.519832 ===================================
6095 16:53:45.522767 EX_ROW_EN[0] = 0x0
6096 16:53:45.526442 EX_ROW_EN[1] = 0x0
6097 16:53:45.526526 LP4Y_EN = 0x0
6098 16:53:45.529324 WORK_FSP = 0x0
6099 16:53:45.529408 WL = 0x2
6100 16:53:45.533051 RL = 0x2
6101 16:53:45.533135 BL = 0x2
6102 16:53:45.536267 RPST = 0x0
6103 16:53:45.536350 RD_PRE = 0x0
6104 16:53:45.539499 WR_PRE = 0x1
6105 16:53:45.539625 WR_PST = 0x0
6106 16:53:45.542717 DBI_WR = 0x0
6107 16:53:45.542801 DBI_RD = 0x0
6108 16:53:45.546409 OTF = 0x1
6109 16:53:45.549443 ===================================
6110 16:53:45.552540 ===================================
6111 16:53:45.552635 ANA top config
6112 16:53:45.556376 ===================================
6113 16:53:45.559388 DLL_ASYNC_EN = 0
6114 16:53:45.562747 ALL_SLAVE_EN = 1
6115 16:53:45.565888 NEW_RANK_MODE = 1
6116 16:53:45.565981 DLL_IDLE_MODE = 1
6117 16:53:45.569722 LP45_APHY_COMB_EN = 1
6118 16:53:45.572699 TX_ODT_DIS = 1
6119 16:53:45.575759 NEW_8X_MODE = 1
6120 16:53:45.579535 ===================================
6121 16:53:45.582525 ===================================
6122 16:53:45.586286 data_rate = 800
6123 16:53:45.586465 CKR = 1
6124 16:53:45.589411 DQ_P2S_RATIO = 4
6125 16:53:45.592366 ===================================
6126 16:53:45.596118 CA_P2S_RATIO = 4
6127 16:53:45.599147 DQ_CA_OPEN = 0
6128 16:53:45.602796 DQ_SEMI_OPEN = 1
6129 16:53:45.605903 CA_SEMI_OPEN = 1
6130 16:53:45.606005 CA_FULL_RATE = 0
6131 16:53:45.609492 DQ_CKDIV4_EN = 0
6132 16:53:45.612429 CA_CKDIV4_EN = 1
6133 16:53:45.616161 CA_PREDIV_EN = 0
6134 16:53:45.619308 PH8_DLY = 0
6135 16:53:45.622604 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6136 16:53:45.622689 DQ_AAMCK_DIV = 0
6137 16:53:45.625962 CA_AAMCK_DIV = 0
6138 16:53:45.629020 CA_ADMCK_DIV = 4
6139 16:53:45.632248 DQ_TRACK_CA_EN = 0
6140 16:53:45.635843 CA_PICK = 800
6141 16:53:45.639218 CA_MCKIO = 400
6142 16:53:45.642374 MCKIO_SEMI = 400
6143 16:53:45.642451 PLL_FREQ = 3016
6144 16:53:45.645490 DQ_UI_PI_RATIO = 32
6145 16:53:45.648834 CA_UI_PI_RATIO = 32
6146 16:53:45.652485 ===================================
6147 16:53:45.655736 ===================================
6148 16:53:45.659116 memory_type:LPDDR4
6149 16:53:45.662430 GP_NUM : 10
6150 16:53:45.662509 SRAM_EN : 1
6151 16:53:45.665543 MD32_EN : 0
6152 16:53:45.668793 ===================================
6153 16:53:45.668884 [ANA_INIT] >>>>>>>>>>>>>>
6154 16:53:45.672275 <<<<<< [CONFIGURE PHASE]: ANA_TX
6155 16:53:45.675374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6156 16:53:45.679112 ===================================
6157 16:53:45.682235 data_rate = 800,PCW = 0X7400
6158 16:53:45.685763 ===================================
6159 16:53:45.688837 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6160 16:53:45.695614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 16:53:45.705539 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6162 16:53:45.712237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6163 16:53:45.715268 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6164 16:53:45.718742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6165 16:53:45.718826 [ANA_INIT] flow start
6166 16:53:45.721877 [ANA_INIT] PLL >>>>>>>>
6167 16:53:45.725766 [ANA_INIT] PLL <<<<<<<<
6168 16:53:45.725875 [ANA_INIT] MIDPI >>>>>>>>
6169 16:53:45.729061 [ANA_INIT] MIDPI <<<<<<<<
6170 16:53:45.732029 [ANA_INIT] DLL >>>>>>>>
6171 16:53:45.732125 [ANA_INIT] flow end
6172 16:53:45.738735 ============ LP4 DIFF to SE enter ============
6173 16:53:45.741865 ============ LP4 DIFF to SE exit ============
6174 16:53:45.745419 [ANA_INIT] <<<<<<<<<<<<<
6175 16:53:45.748633 [Flow] Enable top DCM control >>>>>
6176 16:53:45.751874 [Flow] Enable top DCM control <<<<<
6177 16:53:45.751957 Enable DLL master slave shuffle
6178 16:53:45.758950 ==============================================================
6179 16:53:45.762222 Gating Mode config
6180 16:53:45.765361 ==============================================================
6181 16:53:45.769128 Config description:
6182 16:53:45.778431 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6183 16:53:45.785494 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6184 16:53:45.788549 SELPH_MODE 0: By rank 1: By Phase
6185 16:53:45.795477 ==============================================================
6186 16:53:45.798556 GAT_TRACK_EN = 0
6187 16:53:45.802416 RX_GATING_MODE = 2
6188 16:53:45.805249 RX_GATING_TRACK_MODE = 2
6189 16:53:45.805334 SELPH_MODE = 1
6190 16:53:45.808506 PICG_EARLY_EN = 1
6191 16:53:45.812091 VALID_LAT_VALUE = 1
6192 16:53:45.818767 ==============================================================
6193 16:53:45.821652 Enter into Gating configuration >>>>
6194 16:53:45.825206 Exit from Gating configuration <<<<
6195 16:53:45.828481 Enter into DVFS_PRE_config >>>>>
6196 16:53:45.838515 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6197 16:53:45.841816 Exit from DVFS_PRE_config <<<<<
6198 16:53:45.845060 Enter into PICG configuration >>>>
6199 16:53:45.848265 Exit from PICG configuration <<<<
6200 16:53:45.851958 [RX_INPUT] configuration >>>>>
6201 16:53:45.855291 [RX_INPUT] configuration <<<<<
6202 16:53:45.858488 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6203 16:53:45.865413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6204 16:53:45.872048 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 16:53:45.878742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 16:53:45.882080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 16:53:45.888577 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 16:53:45.891857 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6209 16:53:45.898526 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6210 16:53:45.901939 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6211 16:53:45.905099 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6212 16:53:45.908217 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6213 16:53:45.914903 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6214 16:53:45.918614 ===================================
6215 16:53:45.921495 LPDDR4 DRAM CONFIGURATION
6216 16:53:45.921624 ===================================
6217 16:53:45.925220 EX_ROW_EN[0] = 0x0
6218 16:53:45.928256 EX_ROW_EN[1] = 0x0
6219 16:53:45.928368 LP4Y_EN = 0x0
6220 16:53:45.931830 WORK_FSP = 0x0
6221 16:53:45.931913 WL = 0x2
6222 16:53:45.935271 RL = 0x2
6223 16:53:45.935368 BL = 0x2
6224 16:53:45.938287 RPST = 0x0
6225 16:53:45.938384 RD_PRE = 0x0
6226 16:53:45.941437 WR_PRE = 0x1
6227 16:53:45.941574 WR_PST = 0x0
6228 16:53:45.945245 DBI_WR = 0x0
6229 16:53:45.945319 DBI_RD = 0x0
6230 16:53:45.948589 OTF = 0x1
6231 16:53:45.951676 ===================================
6232 16:53:45.955472 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6233 16:53:45.958598 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6234 16:53:45.964909 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6235 16:53:45.968198 ===================================
6236 16:53:45.968277 LPDDR4 DRAM CONFIGURATION
6237 16:53:45.972075 ===================================
6238 16:53:45.975361 EX_ROW_EN[0] = 0x10
6239 16:53:45.978889 EX_ROW_EN[1] = 0x0
6240 16:53:45.978963 LP4Y_EN = 0x0
6241 16:53:45.981801 WORK_FSP = 0x0
6242 16:53:45.981885 WL = 0x2
6243 16:53:45.985045 RL = 0x2
6244 16:53:45.985128 BL = 0x2
6245 16:53:45.988485 RPST = 0x0
6246 16:53:45.988569 RD_PRE = 0x0
6247 16:53:45.991764 WR_PRE = 0x1
6248 16:53:45.991846 WR_PST = 0x0
6249 16:53:45.995071 DBI_WR = 0x0
6250 16:53:45.995180 DBI_RD = 0x0
6251 16:53:45.998203 OTF = 0x1
6252 16:53:46.001964 ===================================
6253 16:53:46.008878 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6254 16:53:46.011413 nWR fixed to 30
6255 16:53:46.011498 [ModeRegInit_LP4] CH0 RK0
6256 16:53:46.015132 [ModeRegInit_LP4] CH0 RK1
6257 16:53:46.018258 [ModeRegInit_LP4] CH1 RK0
6258 16:53:46.018341 [ModeRegInit_LP4] CH1 RK1
6259 16:53:46.021891 match AC timing 19
6260 16:53:46.024872 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6261 16:53:46.028662 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6262 16:53:46.035254 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6263 16:53:46.038347 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6264 16:53:46.045039 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6265 16:53:46.045124 ==
6266 16:53:46.048447 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 16:53:46.051523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 16:53:46.051602 ==
6269 16:53:46.058147 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6270 16:53:46.061949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6271 16:53:46.065156 [CA 0] Center 36 (8~64) winsize 57
6272 16:53:46.068317 [CA 1] Center 36 (8~64) winsize 57
6273 16:53:46.071428 [CA 2] Center 36 (8~64) winsize 57
6274 16:53:46.074894 [CA 3] Center 36 (8~64) winsize 57
6275 16:53:46.078204 [CA 4] Center 36 (8~64) winsize 57
6276 16:53:46.081333 [CA 5] Center 36 (8~64) winsize 57
6277 16:53:46.081436
6278 16:53:46.085337 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6279 16:53:46.085447
6280 16:53:46.088485 [CATrainingPosCal] consider 1 rank data
6281 16:53:46.091723 u2DelayCellTimex100 = 270/100 ps
6282 16:53:46.094820 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 16:53:46.098214 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 16:53:46.101426 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 16:53:46.108226 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 16:53:46.111843 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 16:53:46.114831 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 16:53:46.114914
6289 16:53:46.117856 CA PerBit enable=1, Macro0, CA PI delay=36
6290 16:53:46.117940
6291 16:53:46.121943 [CBTSetCACLKResult] CA Dly = 36
6292 16:53:46.122027 CS Dly: 1 (0~32)
6293 16:53:46.122093 ==
6294 16:53:46.124847 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 16:53:46.131540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 16:53:46.131631 ==
6297 16:53:46.134695 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6298 16:53:46.141737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6299 16:53:46.144833 [CA 0] Center 36 (8~64) winsize 57
6300 16:53:46.148326 [CA 1] Center 36 (8~64) winsize 57
6301 16:53:46.151285 [CA 2] Center 36 (8~64) winsize 57
6302 16:53:46.155155 [CA 3] Center 36 (8~64) winsize 57
6303 16:53:46.157818 [CA 4] Center 36 (8~64) winsize 57
6304 16:53:46.161698 [CA 5] Center 36 (8~64) winsize 57
6305 16:53:46.161781
6306 16:53:46.164953 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6307 16:53:46.165037
6308 16:53:46.167934 [CATrainingPosCal] consider 2 rank data
6309 16:53:46.171122 u2DelayCellTimex100 = 270/100 ps
6310 16:53:46.174846 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 16:53:46.178286 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 16:53:46.180973 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 16:53:46.184268 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 16:53:46.188153 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 16:53:46.191141 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 16:53:46.194362
6317 16:53:46.197686 CA PerBit enable=1, Macro0, CA PI delay=36
6318 16:53:46.197794
6319 16:53:46.200954 [CBTSetCACLKResult] CA Dly = 36
6320 16:53:46.201032 CS Dly: 1 (0~32)
6321 16:53:46.201106
6322 16:53:46.204187 ----->DramcWriteLeveling(PI) begin...
6323 16:53:46.204273 ==
6324 16:53:46.207989 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 16:53:46.211176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 16:53:46.211261 ==
6327 16:53:46.214431 Write leveling (Byte 0): 40 => 8
6328 16:53:46.217682 Write leveling (Byte 1): 40 => 8
6329 16:53:46.221392 DramcWriteLeveling(PI) end<-----
6330 16:53:46.221476
6331 16:53:46.221571 ==
6332 16:53:46.224321 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 16:53:46.227930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 16:53:46.230982 ==
6335 16:53:46.231092 [Gating] SW mode calibration
6336 16:53:46.241239 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6337 16:53:46.244275 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6338 16:53:46.247878 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 16:53:46.254473 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6340 16:53:46.257865 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 16:53:46.260736 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 16:53:46.267804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 16:53:46.271004 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 16:53:46.274000 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 16:53:46.280733 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 16:53:46.284004 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 16:53:46.287345 Total UI for P1: 0, mck2ui 16
6348 16:53:46.290548 best dqsien dly found for B0: ( 0, 14, 24)
6349 16:53:46.293818 Total UI for P1: 0, mck2ui 16
6350 16:53:46.297924 best dqsien dly found for B1: ( 0, 14, 24)
6351 16:53:46.300886 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6352 16:53:46.304117 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6353 16:53:46.304234
6354 16:53:46.307389 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 16:53:46.310727 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6356 16:53:46.313854 [Gating] SW calibration Done
6357 16:53:46.313966 ==
6358 16:53:46.317699 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 16:53:46.320750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 16:53:46.324121 ==
6361 16:53:46.324228 RX Vref Scan: 0
6362 16:53:46.324320
6363 16:53:46.327230 RX Vref 0 -> 0, step: 1
6364 16:53:46.327336
6365 16:53:46.331103 RX Delay -410 -> 252, step: 16
6366 16:53:46.334218 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6367 16:53:46.337100 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6368 16:53:46.340701 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6369 16:53:46.347339 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6370 16:53:46.350386 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6371 16:53:46.353968 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6372 16:53:46.357433 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6373 16:53:46.363992 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6374 16:53:46.367592 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6375 16:53:46.371095 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6376 16:53:46.374266 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6377 16:53:46.380679 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6378 16:53:46.384085 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6379 16:53:46.387182 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6380 16:53:46.390426 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6381 16:53:46.397545 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6382 16:53:46.397642 ==
6383 16:53:46.400760 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 16:53:46.403864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 16:53:46.403947 ==
6386 16:53:46.404013 DQS Delay:
6387 16:53:46.407006 DQS0 = 27, DQS1 = 35
6388 16:53:46.407088 DQM Delay:
6389 16:53:46.410389 DQM0 = 11, DQM1 = 11
6390 16:53:46.410471 DQ Delay:
6391 16:53:46.413699 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6392 16:53:46.417327 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6393 16:53:46.420888 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6394 16:53:46.424026 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6395 16:53:46.424108
6396 16:53:46.424173
6397 16:53:46.424232 ==
6398 16:53:46.427207 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 16:53:46.430432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 16:53:46.430517 ==
6401 16:53:46.430583
6402 16:53:46.430643
6403 16:53:46.433547 TX Vref Scan disable
6404 16:53:46.436786 == TX Byte 0 ==
6405 16:53:46.440426 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 16:53:46.443616 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 16:53:46.446713 == TX Byte 1 ==
6408 16:53:46.450572 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 16:53:46.453415 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 16:53:46.453497 ==
6411 16:53:46.457161 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 16:53:46.460050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 16:53:46.460133 ==
6414 16:53:46.460199
6415 16:53:46.463612
6416 16:53:46.463725 TX Vref Scan disable
6417 16:53:46.467394 == TX Byte 0 ==
6418 16:53:46.470463 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 16:53:46.473939 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 16:53:46.477007 == TX Byte 1 ==
6421 16:53:46.480198 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 16:53:46.483456 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 16:53:46.483558
6424 16:53:46.483650 [DATLAT]
6425 16:53:46.487319 Freq=400, CH0 RK0
6426 16:53:46.487419
6427 16:53:46.487511 DATLAT Default: 0xf
6428 16:53:46.490565 0, 0xFFFF, sum = 0
6429 16:53:46.490640 1, 0xFFFF, sum = 0
6430 16:53:46.493436 2, 0xFFFF, sum = 0
6431 16:53:46.493567 3, 0xFFFF, sum = 0
6432 16:53:46.497411 4, 0xFFFF, sum = 0
6433 16:53:46.497493 5, 0xFFFF, sum = 0
6434 16:53:46.500622 6, 0xFFFF, sum = 0
6435 16:53:46.504051 7, 0xFFFF, sum = 0
6436 16:53:46.504134 8, 0xFFFF, sum = 0
6437 16:53:46.507224 9, 0xFFFF, sum = 0
6438 16:53:46.507307 10, 0xFFFF, sum = 0
6439 16:53:46.510321 11, 0xFFFF, sum = 0
6440 16:53:46.510418 12, 0xFFFF, sum = 0
6441 16:53:46.513504 13, 0x0, sum = 1
6442 16:53:46.513610 14, 0x0, sum = 2
6443 16:53:46.516782 15, 0x0, sum = 3
6444 16:53:46.516866 16, 0x0, sum = 4
6445 16:53:46.520760 best_step = 14
6446 16:53:46.520843
6447 16:53:46.520907 ==
6448 16:53:46.523673 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 16:53:46.526761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 16:53:46.526842 ==
6451 16:53:46.526907 RX Vref Scan: 1
6452 16:53:46.526967
6453 16:53:46.530053 RX Vref 0 -> 0, step: 1
6454 16:53:46.530134
6455 16:53:46.533977 RX Delay -311 -> 252, step: 8
6456 16:53:46.534058
6457 16:53:46.537175 Set Vref, RX VrefLevel [Byte0]: 57
6458 16:53:46.540351 [Byte1]: 51
6459 16:53:46.544239
6460 16:53:46.544321 Final RX Vref Byte 0 = 57 to rank0
6461 16:53:46.547175 Final RX Vref Byte 1 = 51 to rank0
6462 16:53:46.550716 Final RX Vref Byte 0 = 57 to rank1
6463 16:53:46.553946 Final RX Vref Byte 1 = 51 to rank1==
6464 16:53:46.557023 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 16:53:46.563833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 16:53:46.563915 ==
6467 16:53:46.563980 DQS Delay:
6468 16:53:46.564040 DQS0 = 28, DQS1 = 36
6469 16:53:46.567388 DQM Delay:
6470 16:53:46.567469 DQM0 = 10, DQM1 = 13
6471 16:53:46.570458 DQ Delay:
6472 16:53:46.570539 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6473 16:53:46.573980 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6474 16:53:46.577583 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6475 16:53:46.580767 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6476 16:53:46.580848
6477 16:53:46.580911
6478 16:53:46.590431 [DQSOSCAuto] RK0, (LSB)MR18= 0xc5b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6479 16:53:46.594355 CH0 RK0: MR19=C0C, MR18=C5B1
6480 16:53:46.600875 CH0_RK0: MR19=0xC0C, MR18=0xC5B1, DQSOSC=385, MR23=63, INC=398, DEC=265
6481 16:53:46.600964 ==
6482 16:53:46.604166 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 16:53:46.607424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 16:53:46.607508 ==
6485 16:53:46.610800 [Gating] SW mode calibration
6486 16:53:46.617688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6487 16:53:46.620859 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6488 16:53:46.627312 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 16:53:46.630567 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 16:53:46.633866 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 16:53:46.640806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 16:53:46.644030 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 16:53:46.647323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 16:53:46.654188 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 16:53:46.657161 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 16:53:46.661006 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 16:53:46.664078 Total UI for P1: 0, mck2ui 16
6498 16:53:46.667069 best dqsien dly found for B0: ( 0, 14, 24)
6499 16:53:46.670546 Total UI for P1: 0, mck2ui 16
6500 16:53:46.674225 best dqsien dly found for B1: ( 0, 14, 24)
6501 16:53:46.677194 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6502 16:53:46.680754 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6503 16:53:46.680838
6504 16:53:46.687420 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 16:53:46.690498 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6506 16:53:46.693858 [Gating] SW calibration Done
6507 16:53:46.693943 ==
6508 16:53:46.697112 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 16:53:46.700181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 16:53:46.700258 ==
6511 16:53:46.700323 RX Vref Scan: 0
6512 16:53:46.700388
6513 16:53:46.703892 RX Vref 0 -> 0, step: 1
6514 16:53:46.703968
6515 16:53:46.707004 RX Delay -410 -> 252, step: 16
6516 16:53:46.710149 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6517 16:53:46.716705 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6518 16:53:46.720490 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6519 16:53:46.723515 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6520 16:53:46.726967 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6521 16:53:46.730571 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6522 16:53:46.737208 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6523 16:53:46.740521 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6524 16:53:46.743508 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6525 16:53:46.746685 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6526 16:53:46.753824 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6527 16:53:46.757105 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6528 16:53:46.760100 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6529 16:53:46.763580 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6530 16:53:46.770466 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6531 16:53:46.773422 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6532 16:53:46.773497 ==
6533 16:53:46.777226 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 16:53:46.780328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 16:53:46.780410 ==
6536 16:53:46.783207 DQS Delay:
6537 16:53:46.783277 DQS0 = 27, DQS1 = 35
6538 16:53:46.786848 DQM Delay:
6539 16:53:46.786921 DQM0 = 12, DQM1 = 11
6540 16:53:46.786986 DQ Delay:
6541 16:53:46.789941 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6542 16:53:46.793547 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6543 16:53:46.796709 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6544 16:53:46.800007 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6545 16:53:46.800082
6546 16:53:46.800145
6547 16:53:46.800204 ==
6548 16:53:46.803289 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 16:53:46.810224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 16:53:46.810305 ==
6551 16:53:46.810370
6552 16:53:46.810431
6553 16:53:46.810493 TX Vref Scan disable
6554 16:53:46.813406 == TX Byte 0 ==
6555 16:53:46.816528 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6556 16:53:46.819879 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6557 16:53:46.823096 == TX Byte 1 ==
6558 16:53:46.827024 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6559 16:53:46.830271 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6560 16:53:46.830344 ==
6561 16:53:46.833308 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 16:53:46.839838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 16:53:46.839916 ==
6564 16:53:46.839983
6565 16:53:46.840045
6566 16:53:46.840105 TX Vref Scan disable
6567 16:53:46.843209 == TX Byte 0 ==
6568 16:53:46.846374 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6569 16:53:46.850082 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6570 16:53:46.853201 == TX Byte 1 ==
6571 16:53:46.856532 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6572 16:53:46.859801 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6573 16:53:46.859875
6574 16:53:46.863201 [DATLAT]
6575 16:53:46.863275 Freq=400, CH0 RK1
6576 16:53:46.863339
6577 16:53:46.866295 DATLAT Default: 0xe
6578 16:53:46.866368 0, 0xFFFF, sum = 0
6579 16:53:46.869950 1, 0xFFFF, sum = 0
6580 16:53:46.870026 2, 0xFFFF, sum = 0
6581 16:53:46.872894 3, 0xFFFF, sum = 0
6582 16:53:46.872975 4, 0xFFFF, sum = 0
6583 16:53:46.876527 5, 0xFFFF, sum = 0
6584 16:53:46.876604 6, 0xFFFF, sum = 0
6585 16:53:46.879666 7, 0xFFFF, sum = 0
6586 16:53:46.879747 8, 0xFFFF, sum = 0
6587 16:53:46.883281 9, 0xFFFF, sum = 0
6588 16:53:46.883362 10, 0xFFFF, sum = 0
6589 16:53:46.886209 11, 0xFFFF, sum = 0
6590 16:53:46.889796 12, 0xFFFF, sum = 0
6591 16:53:46.889874 13, 0x0, sum = 1
6592 16:53:46.893254 14, 0x0, sum = 2
6593 16:53:46.893326 15, 0x0, sum = 3
6594 16:53:46.893388 16, 0x0, sum = 4
6595 16:53:46.896324 best_step = 14
6596 16:53:46.896395
6597 16:53:46.896463 ==
6598 16:53:46.899769 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 16:53:46.902868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 16:53:46.902968 ==
6601 16:53:46.906161 RX Vref Scan: 0
6602 16:53:46.906237
6603 16:53:46.906301 RX Vref 0 -> 0, step: 1
6604 16:53:46.909305
6605 16:53:46.909414 RX Delay -311 -> 252, step: 8
6606 16:53:46.917844 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6607 16:53:46.921243 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6608 16:53:46.924544 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6609 16:53:46.927887 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6610 16:53:46.934554 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6611 16:53:46.937731 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6612 16:53:46.941455 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6613 16:53:46.944716 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6614 16:53:46.951209 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6615 16:53:46.954282 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6616 16:53:46.957756 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6617 16:53:46.960967 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6618 16:53:46.967390 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6619 16:53:46.971081 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6620 16:53:46.974247 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6621 16:53:46.980848 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6622 16:53:46.980932 ==
6623 16:53:46.983926 Dram Type= 6, Freq= 0, CH_0, rank 1
6624 16:53:46.987498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 16:53:46.987576 ==
6626 16:53:46.987676 DQS Delay:
6627 16:53:46.991272 DQS0 = 24, DQS1 = 32
6628 16:53:46.991348 DQM Delay:
6629 16:53:46.994328 DQM0 = 9, DQM1 = 9
6630 16:53:46.994400 DQ Delay:
6631 16:53:46.997838 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6632 16:53:47.000786 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6633 16:53:47.004338 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6634 16:53:47.007806 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6635 16:53:47.007905
6636 16:53:47.008009
6637 16:53:47.014432 [DQSOSCAuto] RK1, (LSB)MR18= 0xb454, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6638 16:53:47.017597 CH0 RK1: MR19=C0C, MR18=B454
6639 16:53:47.024133 CH0_RK1: MR19=0xC0C, MR18=0xB454, DQSOSC=387, MR23=63, INC=394, DEC=262
6640 16:53:47.027846 [RxdqsGatingPostProcess] freq 400
6641 16:53:47.031080 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6642 16:53:47.034400 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 16:53:47.037446 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 16:53:47.040708 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 16:53:47.044218 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 16:53:47.047357 best DQS0 dly(2T, 0.5T) = (0, 10)
6647 16:53:47.050550 best DQS1 dly(2T, 0.5T) = (0, 10)
6648 16:53:47.053789 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6649 16:53:47.057454 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6650 16:53:47.060648 Pre-setting of DQS Precalculation
6651 16:53:47.063990 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6652 16:53:47.067081 ==
6653 16:53:47.070975 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 16:53:47.074268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 16:53:47.074352 ==
6656 16:53:47.076967 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6657 16:53:47.083714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6658 16:53:47.086888 [CA 0] Center 36 (8~64) winsize 57
6659 16:53:47.090447 [CA 1] Center 36 (8~64) winsize 57
6660 16:53:47.094046 [CA 2] Center 36 (8~64) winsize 57
6661 16:53:47.097261 [CA 3] Center 36 (8~64) winsize 57
6662 16:53:47.100421 [CA 4] Center 36 (8~64) winsize 57
6663 16:53:47.103975 [CA 5] Center 36 (8~64) winsize 57
6664 16:53:47.104058
6665 16:53:47.107025 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6666 16:53:47.107108
6667 16:53:47.110519 [CATrainingPosCal] consider 1 rank data
6668 16:53:47.113514 u2DelayCellTimex100 = 270/100 ps
6669 16:53:47.117018 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 16:53:47.119998 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 16:53:47.123732 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 16:53:47.127104 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 16:53:47.133317 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 16:53:47.136641 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 16:53:47.136726
6676 16:53:47.140508 CA PerBit enable=1, Macro0, CA PI delay=36
6677 16:53:47.140591
6678 16:53:47.143733 [CBTSetCACLKResult] CA Dly = 36
6679 16:53:47.143816 CS Dly: 1 (0~32)
6680 16:53:47.143882 ==
6681 16:53:47.146968 Dram Type= 6, Freq= 0, CH_1, rank 1
6682 16:53:47.150417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 16:53:47.153459 ==
6684 16:53:47.156663 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6685 16:53:47.163612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6686 16:53:47.166771 [CA 0] Center 36 (8~64) winsize 57
6687 16:53:47.170028 [CA 1] Center 36 (8~64) winsize 57
6688 16:53:47.173356 [CA 2] Center 36 (8~64) winsize 57
6689 16:53:47.177217 [CA 3] Center 36 (8~64) winsize 57
6690 16:53:47.180355 [CA 4] Center 36 (8~64) winsize 57
6691 16:53:47.183525 [CA 5] Center 36 (8~64) winsize 57
6692 16:53:47.183625
6693 16:53:47.187051 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6694 16:53:47.187128
6695 16:53:47.190260 [CATrainingPosCal] consider 2 rank data
6696 16:53:47.193781 u2DelayCellTimex100 = 270/100 ps
6697 16:53:47.196847 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 16:53:47.200022 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 16:53:47.203696 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 16:53:47.206682 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 16:53:47.210415 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 16:53:47.213617 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 16:53:47.213701
6704 16:53:47.217218 CA PerBit enable=1, Macro0, CA PI delay=36
6705 16:53:47.220298
6706 16:53:47.220382 [CBTSetCACLKResult] CA Dly = 36
6707 16:53:47.223921 CS Dly: 1 (0~32)
6708 16:53:47.224005
6709 16:53:47.226799 ----->DramcWriteLeveling(PI) begin...
6710 16:53:47.226885 ==
6711 16:53:47.230234 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 16:53:47.233423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 16:53:47.233515 ==
6714 16:53:47.237176 Write leveling (Byte 0): 40 => 8
6715 16:53:47.240253 Write leveling (Byte 1): 40 => 8
6716 16:53:47.243449 DramcWriteLeveling(PI) end<-----
6717 16:53:47.243534
6718 16:53:47.243620 ==
6719 16:53:47.246876 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 16:53:47.250139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 16:53:47.250226 ==
6722 16:53:47.253684 [Gating] SW mode calibration
6723 16:53:47.260357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6724 16:53:47.267026 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6725 16:53:47.270186 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 16:53:47.276709 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6727 16:53:47.280108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 16:53:47.283256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 16:53:47.287074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 16:53:47.293440 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 16:53:47.296687 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 16:53:47.299795 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 16:53:47.306730 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 16:53:47.310357 Total UI for P1: 0, mck2ui 16
6735 16:53:47.313326 best dqsien dly found for B0: ( 0, 14, 24)
6736 16:53:47.316363 Total UI for P1: 0, mck2ui 16
6737 16:53:47.319589 best dqsien dly found for B1: ( 0, 14, 24)
6738 16:53:47.323273 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6739 16:53:47.326894 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6740 16:53:47.327008
6741 16:53:47.329948 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 16:53:47.332995 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6743 16:53:47.336244 [Gating] SW calibration Done
6744 16:53:47.336328 ==
6745 16:53:47.339528 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 16:53:47.343218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 16:53:47.343303 ==
6748 16:53:47.346229 RX Vref Scan: 0
6749 16:53:47.346313
6750 16:53:47.349648 RX Vref 0 -> 0, step: 1
6751 16:53:47.349737
6752 16:53:47.349804 RX Delay -410 -> 252, step: 16
6753 16:53:47.356157 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6754 16:53:47.360059 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6755 16:53:47.363169 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6756 16:53:47.366295 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6757 16:53:47.372990 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6758 16:53:47.376362 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6759 16:53:47.379466 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6760 16:53:47.382895 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6761 16:53:47.389293 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6762 16:53:47.393066 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6763 16:53:47.396195 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6764 16:53:47.399504 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6765 16:53:47.405937 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6766 16:53:47.409464 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6767 16:53:47.412508 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6768 16:53:47.416065 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6769 16:53:47.419742 ==
6770 16:53:47.422695 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 16:53:47.425795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 16:53:47.425880 ==
6773 16:53:47.425947 DQS Delay:
6774 16:53:47.429413 DQS0 = 35, DQS1 = 35
6775 16:53:47.429496 DQM Delay:
6776 16:53:47.432413 DQM0 = 20, DQM1 = 17
6777 16:53:47.432496 DQ Delay:
6778 16:53:47.436205 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6779 16:53:47.439188 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6780 16:53:47.442294 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6781 16:53:47.446095 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6782 16:53:47.446179
6783 16:53:47.446245
6784 16:53:47.446306 ==
6785 16:53:47.449246 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 16:53:47.452377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 16:53:47.452495 ==
6788 16:53:47.452561
6789 16:53:47.452623
6790 16:53:47.455726 TX Vref Scan disable
6791 16:53:47.455811 == TX Byte 0 ==
6792 16:53:47.462691 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 16:53:47.465741 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 16:53:47.465822 == TX Byte 1 ==
6795 16:53:47.472662 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 16:53:47.475679 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 16:53:47.475774 ==
6798 16:53:47.479343 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 16:53:47.482491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 16:53:47.482566 ==
6801 16:53:47.482635
6802 16:53:47.482696
6803 16:53:47.485844 TX Vref Scan disable
6804 16:53:47.485915 == TX Byte 0 ==
6805 16:53:47.492179 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 16:53:47.495493 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 16:53:47.495569 == TX Byte 1 ==
6808 16:53:47.502483 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 16:53:47.505807 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 16:53:47.505893
6811 16:53:47.505981 [DATLAT]
6812 16:53:47.509002 Freq=400, CH1 RK0
6813 16:53:47.509088
6814 16:53:47.509174 DATLAT Default: 0xf
6815 16:53:47.512099 0, 0xFFFF, sum = 0
6816 16:53:47.512187 1, 0xFFFF, sum = 0
6817 16:53:47.515810 2, 0xFFFF, sum = 0
6818 16:53:47.515897 3, 0xFFFF, sum = 0
6819 16:53:47.518942 4, 0xFFFF, sum = 0
6820 16:53:47.519030 5, 0xFFFF, sum = 0
6821 16:53:47.522401 6, 0xFFFF, sum = 0
6822 16:53:47.522489 7, 0xFFFF, sum = 0
6823 16:53:47.525441 8, 0xFFFF, sum = 0
6824 16:53:47.528769 9, 0xFFFF, sum = 0
6825 16:53:47.528856 10, 0xFFFF, sum = 0
6826 16:53:47.532389 11, 0xFFFF, sum = 0
6827 16:53:47.532477 12, 0xFFFF, sum = 0
6828 16:53:47.535344 13, 0x0, sum = 1
6829 16:53:47.535432 14, 0x0, sum = 2
6830 16:53:47.538921 15, 0x0, sum = 3
6831 16:53:47.539009 16, 0x0, sum = 4
6832 16:53:47.539111 best_step = 14
6833 16:53:47.539193
6834 16:53:47.542014 ==
6835 16:53:47.545750 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 16:53:47.549048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 16:53:47.549159 ==
6838 16:53:47.549242 RX Vref Scan: 1
6839 16:53:47.549326
6840 16:53:47.552322 RX Vref 0 -> 0, step: 1
6841 16:53:47.552422
6842 16:53:47.555487 RX Delay -311 -> 252, step: 8
6843 16:53:47.555592
6844 16:53:47.559217 Set Vref, RX VrefLevel [Byte0]: 53
6845 16:53:47.561960 [Byte1]: 50
6846 16:53:47.565854
6847 16:53:47.565938 Final RX Vref Byte 0 = 53 to rank0
6848 16:53:47.569030 Final RX Vref Byte 1 = 50 to rank0
6849 16:53:47.572789 Final RX Vref Byte 0 = 53 to rank1
6850 16:53:47.575399 Final RX Vref Byte 1 = 50 to rank1==
6851 16:53:47.579143 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 16:53:47.585783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 16:53:47.585868 ==
6854 16:53:47.585935 DQS Delay:
6855 16:53:47.589120 DQS0 = 32, DQS1 = 32
6856 16:53:47.589204 DQM Delay:
6857 16:53:47.589271 DQM0 = 14, DQM1 = 11
6858 16:53:47.592397 DQ Delay:
6859 16:53:47.595483 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6860 16:53:47.598963 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6861 16:53:47.599047 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6862 16:53:47.602067 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6863 16:53:47.605234
6864 16:53:47.605317
6865 16:53:47.611967 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6866 16:53:47.615133 CH1 RK0: MR19=C0C, MR18=8EC6
6867 16:53:47.621832 CH1_RK0: MR19=0xC0C, MR18=0x8EC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6868 16:53:47.621917 ==
6869 16:53:47.625433 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 16:53:47.628569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 16:53:47.628662 ==
6872 16:53:47.632368 [Gating] SW mode calibration
6873 16:53:47.638785 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6874 16:53:47.645265 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6875 16:53:47.648324 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 16:53:47.652125 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6877 16:53:47.658677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 16:53:47.661685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 16:53:47.665403 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 16:53:47.668793 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 16:53:47.675128 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 16:53:47.678353 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 16:53:47.681665 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 16:53:47.684923 Total UI for P1: 0, mck2ui 16
6885 16:53:47.688633 best dqsien dly found for B0: ( 0, 14, 24)
6886 16:53:47.692191 Total UI for P1: 0, mck2ui 16
6887 16:53:47.695161 best dqsien dly found for B1: ( 0, 14, 24)
6888 16:53:47.698367 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6889 16:53:47.704933 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6890 16:53:47.705021
6891 16:53:47.708808 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 16:53:47.712122 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6893 16:53:47.715385 [Gating] SW calibration Done
6894 16:53:47.715469 ==
6895 16:53:47.718564 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 16:53:47.721768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 16:53:47.721854 ==
6898 16:53:47.724817 RX Vref Scan: 0
6899 16:53:47.724901
6900 16:53:47.724967 RX Vref 0 -> 0, step: 1
6901 16:53:47.725029
6902 16:53:47.728480 RX Delay -410 -> 252, step: 16
6903 16:53:47.731660 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6904 16:53:47.738562 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6905 16:53:47.741403 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6906 16:53:47.744696 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6907 16:53:47.748317 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6908 16:53:47.754885 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6909 16:53:47.758365 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6910 16:53:47.761491 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6911 16:53:47.764931 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6912 16:53:47.771665 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6913 16:53:47.774810 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6914 16:53:47.778087 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6915 16:53:47.781191 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6916 16:53:47.787833 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6917 16:53:47.791655 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6918 16:53:47.794835 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6919 16:53:47.794910 ==
6920 16:53:47.797870 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 16:53:47.804468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 16:53:47.804553 ==
6923 16:53:47.804620 DQS Delay:
6924 16:53:47.807945 DQS0 = 35, DQS1 = 35
6925 16:53:47.808021 DQM Delay:
6926 16:53:47.808086 DQM0 = 17, DQM1 = 14
6927 16:53:47.811605 DQ Delay:
6928 16:53:47.814845 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6929 16:53:47.818131 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6930 16:53:47.818208 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6931 16:53:47.821399 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6932 16:53:47.824542
6933 16:53:47.824630
6934 16:53:47.824704 ==
6935 16:53:47.828324 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 16:53:47.831338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 16:53:47.831421 ==
6938 16:53:47.831488
6939 16:53:47.831554
6940 16:53:47.835122 TX Vref Scan disable
6941 16:53:47.835213 == TX Byte 0 ==
6942 16:53:47.838087 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6943 16:53:47.844813 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6944 16:53:47.844921 == TX Byte 1 ==
6945 16:53:47.847769 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6946 16:53:47.854504 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6947 16:53:47.854587 ==
6948 16:53:47.858478 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 16:53:47.861473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 16:53:47.861628 ==
6951 16:53:47.861786
6952 16:53:47.861871
6953 16:53:47.865189 TX Vref Scan disable
6954 16:53:47.865314 == TX Byte 0 ==
6955 16:53:47.867706 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6956 16:53:47.874728 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6957 16:53:47.874867 == TX Byte 1 ==
6958 16:53:47.877746 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6959 16:53:47.884578 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6960 16:53:47.884673
6961 16:53:47.884756 [DATLAT]
6962 16:53:47.884848 Freq=400, CH1 RK1
6963 16:53:47.887899
6964 16:53:47.887984 DATLAT Default: 0xe
6965 16:53:47.891267 0, 0xFFFF, sum = 0
6966 16:53:47.891387 1, 0xFFFF, sum = 0
6967 16:53:47.894512 2, 0xFFFF, sum = 0
6968 16:53:47.894612 3, 0xFFFF, sum = 0
6969 16:53:47.897471 4, 0xFFFF, sum = 0
6970 16:53:47.897610 5, 0xFFFF, sum = 0
6971 16:53:47.900828 6, 0xFFFF, sum = 0
6972 16:53:47.900934 7, 0xFFFF, sum = 0
6973 16:53:47.904459 8, 0xFFFF, sum = 0
6974 16:53:47.904581 9, 0xFFFF, sum = 0
6975 16:53:47.907728 10, 0xFFFF, sum = 0
6976 16:53:47.907813 11, 0xFFFF, sum = 0
6977 16:53:47.910854 12, 0xFFFF, sum = 0
6978 16:53:47.910932 13, 0x0, sum = 1
6979 16:53:47.914492 14, 0x0, sum = 2
6980 16:53:47.914602 15, 0x0, sum = 3
6981 16:53:47.917772 16, 0x0, sum = 4
6982 16:53:47.917864 best_step = 14
6983 16:53:47.917929
6984 16:53:47.917989 ==
6985 16:53:47.921089 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 16:53:47.927566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 16:53:47.927649 ==
6988 16:53:47.927712 RX Vref Scan: 0
6989 16:53:47.927772
6990 16:53:47.930802 RX Vref 0 -> 0, step: 1
6991 16:53:47.930874
6992 16:53:47.934055 RX Delay -311 -> 252, step: 8
6993 16:53:47.940629 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6994 16:53:47.944433 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6995 16:53:47.947352 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6996 16:53:47.950964 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6997 16:53:47.957709 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6998 16:53:47.960505 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6999 16:53:47.964214 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7000 16:53:47.967391 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7001 16:53:47.970954 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7002 16:53:47.977397 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7003 16:53:47.980651 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7004 16:53:47.983811 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7005 16:53:47.990694 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7006 16:53:47.993863 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7007 16:53:47.997117 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7008 16:53:48.000639 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7009 16:53:48.000732 ==
7010 16:53:48.004189 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 16:53:48.010779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 16:53:48.010881 ==
7013 16:53:48.010956 DQS Delay:
7014 16:53:48.013963 DQS0 = 28, DQS1 = 36
7015 16:53:48.014066 DQM Delay:
7016 16:53:48.014196 DQM0 = 10, DQM1 = 14
7017 16:53:48.017200 DQ Delay:
7018 16:53:48.020821 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7019 16:53:48.020897 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7020 16:53:48.023944 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7021 16:53:48.027201 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7022 16:53:48.030494
7023 16:53:48.030567
7024 16:53:48.037029 [DQSOSCAuto] RK1, (LSB)MR18= 0xc556, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7025 16:53:48.040254 CH1 RK1: MR19=C0C, MR18=C556
7026 16:53:48.046891 CH1_RK1: MR19=0xC0C, MR18=0xC556, DQSOSC=385, MR23=63, INC=398, DEC=265
7027 16:53:48.050520 [RxdqsGatingPostProcess] freq 400
7028 16:53:48.053623 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7029 16:53:48.057179 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 16:53:48.060604 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 16:53:48.063406 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 16:53:48.067028 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 16:53:48.070590 best DQS0 dly(2T, 0.5T) = (0, 10)
7034 16:53:48.073701 best DQS1 dly(2T, 0.5T) = (0, 10)
7035 16:53:48.077002 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7036 16:53:48.080037 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7037 16:53:48.083835 Pre-setting of DQS Precalculation
7038 16:53:48.087104 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7039 16:53:48.093782 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7040 16:53:48.103640 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7041 16:53:48.103745
7042 16:53:48.103845
7043 16:53:48.106826 [Calibration Summary] 800 Mbps
7044 16:53:48.106899 CH 0, Rank 0
7045 16:53:48.110596 SW Impedance : PASS
7046 16:53:48.110670 DUTY Scan : NO K
7047 16:53:48.113891 ZQ Calibration : PASS
7048 16:53:48.113990 Jitter Meter : NO K
7049 16:53:48.117139 CBT Training : PASS
7050 16:53:48.120486 Write leveling : PASS
7051 16:53:48.120566 RX DQS gating : PASS
7052 16:53:48.123466 RX DQ/DQS(RDDQC) : PASS
7053 16:53:48.127243 TX DQ/DQS : PASS
7054 16:53:48.127326 RX DATLAT : PASS
7055 16:53:48.130479 RX DQ/DQS(Engine): PASS
7056 16:53:48.133745 TX OE : NO K
7057 16:53:48.133829 All Pass.
7058 16:53:48.133895
7059 16:53:48.133957 CH 0, Rank 1
7060 16:53:48.136936 SW Impedance : PASS
7061 16:53:48.140139 DUTY Scan : NO K
7062 16:53:48.140222 ZQ Calibration : PASS
7063 16:53:48.143439 Jitter Meter : NO K
7064 16:53:48.146658 CBT Training : PASS
7065 16:53:48.146741 Write leveling : NO K
7066 16:53:48.149816 RX DQS gating : PASS
7067 16:53:48.153681 RX DQ/DQS(RDDQC) : PASS
7068 16:53:48.153765 TX DQ/DQS : PASS
7069 16:53:48.156737 RX DATLAT : PASS
7070 16:53:48.160237 RX DQ/DQS(Engine): PASS
7071 16:53:48.160329 TX OE : NO K
7072 16:53:48.160397 All Pass.
7073 16:53:48.163256
7074 16:53:48.163338 CH 1, Rank 0
7075 16:53:48.166788 SW Impedance : PASS
7076 16:53:48.166872 DUTY Scan : NO K
7077 16:53:48.169836 ZQ Calibration : PASS
7078 16:53:48.169918 Jitter Meter : NO K
7079 16:53:48.173390 CBT Training : PASS
7080 16:53:48.176428 Write leveling : PASS
7081 16:53:48.176511 RX DQS gating : PASS
7082 16:53:48.179987 RX DQ/DQS(RDDQC) : PASS
7083 16:53:48.182995 TX DQ/DQS : PASS
7084 16:53:48.183078 RX DATLAT : PASS
7085 16:53:48.186558 RX DQ/DQS(Engine): PASS
7086 16:53:48.189633 TX OE : NO K
7087 16:53:48.189719 All Pass.
7088 16:53:48.189786
7089 16:53:48.189849 CH 1, Rank 1
7090 16:53:48.193248 SW Impedance : PASS
7091 16:53:48.196473 DUTY Scan : NO K
7092 16:53:48.196548 ZQ Calibration : PASS
7093 16:53:48.199478 Jitter Meter : NO K
7094 16:53:48.202928 CBT Training : PASS
7095 16:53:48.203036 Write leveling : NO K
7096 16:53:48.206128 RX DQS gating : PASS
7097 16:53:48.209383 RX DQ/DQS(RDDQC) : PASS
7098 16:53:48.209490 TX DQ/DQS : PASS
7099 16:53:48.212541 RX DATLAT : PASS
7100 16:53:48.216323 RX DQ/DQS(Engine): PASS
7101 16:53:48.216423 TX OE : NO K
7102 16:53:48.219307 All Pass.
7103 16:53:48.219405
7104 16:53:48.219502 DramC Write-DBI off
7105 16:53:48.222511 PER_BANK_REFRESH: Hybrid Mode
7106 16:53:48.222609 TX_TRACKING: ON
7107 16:53:48.232841 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7108 16:53:48.236155 [FAST_K] Save calibration result to emmc
7109 16:53:48.239415 dramc_set_vcore_voltage set vcore to 725000
7110 16:53:48.242709 Read voltage for 1600, 0
7111 16:53:48.242783 Vio18 = 0
7112 16:53:48.245936 Vcore = 725000
7113 16:53:48.246035 Vdram = 0
7114 16:53:48.246133 Vddq = 0
7115 16:53:48.249190 Vmddr = 0
7116 16:53:48.252537 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7117 16:53:48.259468 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7118 16:53:48.259552 MEM_TYPE=3, freq_sel=13
7119 16:53:48.262520 sv_algorithm_assistance_LP4_3733
7120 16:53:48.265785 ============ PULL DRAM RESETB DOWN ============
7121 16:53:48.272432 ========== PULL DRAM RESETB DOWN end =========
7122 16:53:48.275905 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7123 16:53:48.278852 ===================================
7124 16:53:48.282574 LPDDR4 DRAM CONFIGURATION
7125 16:53:48.286122 ===================================
7126 16:53:48.286211 EX_ROW_EN[0] = 0x0
7127 16:53:48.289094 EX_ROW_EN[1] = 0x0
7128 16:53:48.292147 LP4Y_EN = 0x0
7129 16:53:48.292250 WORK_FSP = 0x1
7130 16:53:48.295752 WL = 0x5
7131 16:53:48.295830 RL = 0x5
7132 16:53:48.298803 BL = 0x2
7133 16:53:48.298881 RPST = 0x0
7134 16:53:48.302161 RD_PRE = 0x0
7135 16:53:48.302245 WR_PRE = 0x1
7136 16:53:48.305409 WR_PST = 0x1
7137 16:53:48.305495 DBI_WR = 0x0
7138 16:53:48.309259 DBI_RD = 0x0
7139 16:53:48.309343 OTF = 0x1
7140 16:53:48.312537 ===================================
7141 16:53:48.315860 ===================================
7142 16:53:48.318934 ANA top config
7143 16:53:48.322109 ===================================
7144 16:53:48.322192 DLL_ASYNC_EN = 0
7145 16:53:48.325441 ALL_SLAVE_EN = 0
7146 16:53:48.328730 NEW_RANK_MODE = 1
7147 16:53:48.331978 DLL_IDLE_MODE = 1
7148 16:53:48.335720 LP45_APHY_COMB_EN = 1
7149 16:53:48.335825 TX_ODT_DIS = 0
7150 16:53:48.338892 NEW_8X_MODE = 1
7151 16:53:48.341915 ===================================
7152 16:53:48.345176 ===================================
7153 16:53:48.348450 data_rate = 3200
7154 16:53:48.351836 CKR = 1
7155 16:53:48.355130 DQ_P2S_RATIO = 8
7156 16:53:48.358837 ===================================
7157 16:53:48.358947 CA_P2S_RATIO = 8
7158 16:53:48.362006 DQ_CA_OPEN = 0
7159 16:53:48.365311 DQ_SEMI_OPEN = 0
7160 16:53:48.368462 CA_SEMI_OPEN = 0
7161 16:53:48.371722 CA_FULL_RATE = 0
7162 16:53:48.375332 DQ_CKDIV4_EN = 0
7163 16:53:48.375434 CA_CKDIV4_EN = 0
7164 16:53:48.378366 CA_PREDIV_EN = 0
7165 16:53:48.381690 PH8_DLY = 12
7166 16:53:48.385218 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7167 16:53:48.388155 DQ_AAMCK_DIV = 4
7168 16:53:48.391644 CA_AAMCK_DIV = 4
7169 16:53:48.391721 CA_ADMCK_DIV = 4
7170 16:53:48.395151 DQ_TRACK_CA_EN = 0
7171 16:53:48.398217 CA_PICK = 1600
7172 16:53:48.401697 CA_MCKIO = 1600
7173 16:53:48.405435 MCKIO_SEMI = 0
7174 16:53:48.408308 PLL_FREQ = 3068
7175 16:53:48.411888 DQ_UI_PI_RATIO = 32
7176 16:53:48.414742 CA_UI_PI_RATIO = 0
7177 16:53:48.418689 ===================================
7178 16:53:48.421739 ===================================
7179 16:53:48.421815 memory_type:LPDDR4
7180 16:53:48.424910 GP_NUM : 10
7181 16:53:48.428244 SRAM_EN : 1
7182 16:53:48.428349 MD32_EN : 0
7183 16:53:48.431603 ===================================
7184 16:53:48.434834 [ANA_INIT] >>>>>>>>>>>>>>
7185 16:53:48.438119 <<<<<< [CONFIGURE PHASE]: ANA_TX
7186 16:53:48.441987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7187 16:53:48.444957 ===================================
7188 16:53:48.448135 data_rate = 3200,PCW = 0X7600
7189 16:53:48.448214 ===================================
7190 16:53:48.455159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7191 16:53:48.458317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 16:53:48.464638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7193 16:53:48.468502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7194 16:53:48.471863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7195 16:53:48.474953 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7196 16:53:48.478210 [ANA_INIT] flow start
7197 16:53:48.481294 [ANA_INIT] PLL >>>>>>>>
7198 16:53:48.481396 [ANA_INIT] PLL <<<<<<<<
7199 16:53:48.484979 [ANA_INIT] MIDPI >>>>>>>>
7200 16:53:48.488080 [ANA_INIT] MIDPI <<<<<<<<
7201 16:53:48.488160 [ANA_INIT] DLL >>>>>>>>
7202 16:53:48.491508 [ANA_INIT] DLL <<<<<<<<
7203 16:53:48.495148 [ANA_INIT] flow end
7204 16:53:48.498141 ============ LP4 DIFF to SE enter ============
7205 16:53:48.501235 ============ LP4 DIFF to SE exit ============
7206 16:53:48.504698 [ANA_INIT] <<<<<<<<<<<<<
7207 16:53:48.508259 [Flow] Enable top DCM control >>>>>
7208 16:53:48.511373 [Flow] Enable top DCM control <<<<<
7209 16:53:48.514903 Enable DLL master slave shuffle
7210 16:53:48.518006 ==============================================================
7211 16:53:48.521708 Gating Mode config
7212 16:53:48.527864 ==============================================================
7213 16:53:48.527951 Config description:
7214 16:53:48.538159 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7215 16:53:48.544782 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7216 16:53:48.547732 SELPH_MODE 0: By rank 1: By Phase
7217 16:53:48.554580 ==============================================================
7218 16:53:48.557715 GAT_TRACK_EN = 1
7219 16:53:48.560851 RX_GATING_MODE = 2
7220 16:53:48.564232 RX_GATING_TRACK_MODE = 2
7221 16:53:48.567901 SELPH_MODE = 1
7222 16:53:48.571199 PICG_EARLY_EN = 1
7223 16:53:48.574374 VALID_LAT_VALUE = 1
7224 16:53:48.577846 ==============================================================
7225 16:53:48.580970 Enter into Gating configuration >>>>
7226 16:53:48.584300 Exit from Gating configuration <<<<
7227 16:53:48.587502 Enter into DVFS_PRE_config >>>>>
7228 16:53:48.601198 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7229 16:53:48.601312 Exit from DVFS_PRE_config <<<<<
7230 16:53:48.604664 Enter into PICG configuration >>>>
7231 16:53:48.607754 Exit from PICG configuration <<<<
7232 16:53:48.611167 [RX_INPUT] configuration >>>>>
7233 16:53:48.614845 [RX_INPUT] configuration <<<<<
7234 16:53:48.621306 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7235 16:53:48.624769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7236 16:53:48.631385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 16:53:48.638070 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 16:53:48.644821 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 16:53:48.650966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 16:53:48.654315 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7241 16:53:48.658112 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7242 16:53:48.661486 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7243 16:53:48.667686 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7244 16:53:48.670872 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7245 16:53:48.674490 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7246 16:53:48.677718 ===================================
7247 16:53:48.681078 LPDDR4 DRAM CONFIGURATION
7248 16:53:48.684334 ===================================
7249 16:53:48.684421 EX_ROW_EN[0] = 0x0
7250 16:53:48.687510 EX_ROW_EN[1] = 0x0
7251 16:53:48.690745 LP4Y_EN = 0x0
7252 16:53:48.690830 WORK_FSP = 0x1
7253 16:53:48.694013 WL = 0x5
7254 16:53:48.694098 RL = 0x5
7255 16:53:48.697243 BL = 0x2
7256 16:53:48.697328 RPST = 0x0
7257 16:53:48.700768 RD_PRE = 0x0
7258 16:53:48.700883 WR_PRE = 0x1
7259 16:53:48.703931 WR_PST = 0x1
7260 16:53:48.704015 DBI_WR = 0x0
7261 16:53:48.707031 DBI_RD = 0x0
7262 16:53:48.707116 OTF = 0x1
7263 16:53:48.710740 ===================================
7264 16:53:48.714395 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7265 16:53:48.720650 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7266 16:53:48.724240 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7267 16:53:48.727444 ===================================
7268 16:53:48.731012 LPDDR4 DRAM CONFIGURATION
7269 16:53:48.734064 ===================================
7270 16:53:48.734151 EX_ROW_EN[0] = 0x10
7271 16:53:48.737184 EX_ROW_EN[1] = 0x0
7272 16:53:48.737331 LP4Y_EN = 0x0
7273 16:53:48.740478 WORK_FSP = 0x1
7274 16:53:48.740563 WL = 0x5
7275 16:53:48.744186 RL = 0x5
7276 16:53:48.747263 BL = 0x2
7277 16:53:48.747348 RPST = 0x0
7278 16:53:48.750501 RD_PRE = 0x0
7279 16:53:48.750586 WR_PRE = 0x1
7280 16:53:48.753710 WR_PST = 0x1
7281 16:53:48.753795 DBI_WR = 0x0
7282 16:53:48.757348 DBI_RD = 0x0
7283 16:53:48.757462 OTF = 0x1
7284 16:53:48.760569 ===================================
7285 16:53:48.767567 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7286 16:53:48.767655 ==
7287 16:53:48.770688 Dram Type= 6, Freq= 0, CH_0, rank 0
7288 16:53:48.773469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7289 16:53:48.773593 ==
7290 16:53:48.777258 [Duty_Offset_Calibration]
7291 16:53:48.780509 B0:2 B1:1 CA:1
7292 16:53:48.780594
7293 16:53:48.783748 [DutyScan_Calibration_Flow] k_type=0
7294 16:53:48.792173
7295 16:53:48.792259 ==CLK 0==
7296 16:53:48.795376 Final CLK duty delay cell = 0
7297 16:53:48.798701 [0] MAX Duty = 5187%(X100), DQS PI = 24
7298 16:53:48.801970 [0] MIN Duty = 4876%(X100), DQS PI = 48
7299 16:53:48.805662 [0] AVG Duty = 5031%(X100)
7300 16:53:48.805748
7301 16:53:48.808706 CH0 CLK Duty spec in!! Max-Min= 311%
7302 16:53:48.811764 [DutyScan_Calibration_Flow] ====Done====
7303 16:53:48.811849
7304 16:53:48.815377 [DutyScan_Calibration_Flow] k_type=1
7305 16:53:48.831040
7306 16:53:48.831134 ==DQS 0 ==
7307 16:53:48.834732 Final DQS duty delay cell = -4
7308 16:53:48.837673 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7309 16:53:48.841434 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7310 16:53:48.844751 [-4] AVG Duty = 4891%(X100)
7311 16:53:48.844835
7312 16:53:48.844945 ==DQS 1 ==
7313 16:53:48.847703 Final DQS duty delay cell = 0
7314 16:53:48.851458 [0] MAX Duty = 5187%(X100), DQS PI = 4
7315 16:53:48.854563 [0] MIN Duty = 5031%(X100), DQS PI = 54
7316 16:53:48.857771 [0] AVG Duty = 5109%(X100)
7317 16:53:48.857883
7318 16:53:48.861028 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7319 16:53:48.861114
7320 16:53:48.864247 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7321 16:53:48.867535 [DutyScan_Calibration_Flow] ====Done====
7322 16:53:48.867619
7323 16:53:48.870768 [DutyScan_Calibration_Flow] k_type=3
7324 16:53:48.887897
7325 16:53:48.887990 ==DQM 0 ==
7326 16:53:48.891193 Final DQM duty delay cell = 0
7327 16:53:48.894338 [0] MAX Duty = 5218%(X100), DQS PI = 34
7328 16:53:48.897613 [0] MIN Duty = 4876%(X100), DQS PI = 60
7329 16:53:48.900803 [0] AVG Duty = 5047%(X100)
7330 16:53:48.900888
7331 16:53:48.900955 ==DQM 1 ==
7332 16:53:48.904131 Final DQM duty delay cell = -4
7333 16:53:48.907466 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7334 16:53:48.911393 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7335 16:53:48.914318 [-4] AVG Duty = 4922%(X100)
7336 16:53:48.914403
7337 16:53:48.917443 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7338 16:53:48.917592
7339 16:53:48.920957 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7340 16:53:48.924617 [DutyScan_Calibration_Flow] ====Done====
7341 16:53:48.924730
7342 16:53:48.927601 [DutyScan_Calibration_Flow] k_type=2
7343 16:53:48.945565
7344 16:53:48.945661 ==DQ 0 ==
7345 16:53:48.948553 Final DQ duty delay cell = 0
7346 16:53:48.951848 [0] MAX Duty = 5062%(X100), DQS PI = 24
7347 16:53:48.955220 [0] MIN Duty = 4907%(X100), DQS PI = 0
7348 16:53:48.955310 [0] AVG Duty = 4984%(X100)
7349 16:53:48.955379
7350 16:53:48.958786 ==DQ 1 ==
7351 16:53:48.962006 Final DQ duty delay cell = 0
7352 16:53:48.965176 [0] MAX Duty = 5156%(X100), DQS PI = 22
7353 16:53:48.968926 [0] MIN Duty = 4907%(X100), DQS PI = 34
7354 16:53:48.969011 [0] AVG Duty = 5031%(X100)
7355 16:53:48.969079
7356 16:53:48.972316 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7357 16:53:48.975539
7358 16:53:48.978613 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7359 16:53:48.981755 [DutyScan_Calibration_Flow] ====Done====
7360 16:53:48.981839 ==
7361 16:53:48.985272 Dram Type= 6, Freq= 0, CH_1, rank 0
7362 16:53:48.988646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7363 16:53:48.988731 ==
7364 16:53:48.991851 [Duty_Offset_Calibration]
7365 16:53:48.991934 B0:1 B1:0 CA:1
7366 16:53:48.992000
7367 16:53:48.995252 [DutyScan_Calibration_Flow] k_type=0
7368 16:53:49.004827
7369 16:53:49.004928 ==CLK 0==
7370 16:53:49.008029 Final CLK duty delay cell = -4
7371 16:53:49.011194 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7372 16:53:49.014532 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7373 16:53:49.017908 [-4] AVG Duty = 4906%(X100)
7374 16:53:49.017990
7375 16:53:49.021329 CH1 CLK Duty spec in!! Max-Min= 125%
7376 16:53:49.024468 [DutyScan_Calibration_Flow] ====Done====
7377 16:53:49.024547
7378 16:53:49.027861 [DutyScan_Calibration_Flow] k_type=1
7379 16:53:49.044870
7380 16:53:49.044991 ==DQS 0 ==
7381 16:53:49.047898 Final DQS duty delay cell = 0
7382 16:53:49.051437 [0] MAX Duty = 5094%(X100), DQS PI = 22
7383 16:53:49.054462 [0] MIN Duty = 4875%(X100), DQS PI = 0
7384 16:53:49.057828 [0] AVG Duty = 4984%(X100)
7385 16:53:49.057909
7386 16:53:49.057974 ==DQS 1 ==
7387 16:53:49.061668 Final DQS duty delay cell = 0
7388 16:53:49.064915 [0] MAX Duty = 5281%(X100), DQS PI = 18
7389 16:53:49.067974 [0] MIN Duty = 4969%(X100), DQS PI = 8
7390 16:53:49.071234 [0] AVG Duty = 5125%(X100)
7391 16:53:49.071313
7392 16:53:49.074430 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7393 16:53:49.074504
7394 16:53:49.077651 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7395 16:53:49.081164 [DutyScan_Calibration_Flow] ====Done====
7396 16:53:49.081237
7397 16:53:49.084806 [DutyScan_Calibration_Flow] k_type=3
7398 16:53:49.101735
7399 16:53:49.101831 ==DQM 0 ==
7400 16:53:49.104869 Final DQM duty delay cell = 0
7401 16:53:49.108062 [0] MAX Duty = 5218%(X100), DQS PI = 18
7402 16:53:49.111417 [0] MIN Duty = 4969%(X100), DQS PI = 48
7403 16:53:49.111495 [0] AVG Duty = 5093%(X100)
7404 16:53:49.115247
7405 16:53:49.115322 ==DQM 1 ==
7406 16:53:49.118416 Final DQM duty delay cell = 0
7407 16:53:49.121803 [0] MAX Duty = 5093%(X100), DQS PI = 16
7408 16:53:49.124839 [0] MIN Duty = 4907%(X100), DQS PI = 34
7409 16:53:49.127908 [0] AVG Duty = 5000%(X100)
7410 16:53:49.127982
7411 16:53:49.131647 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7412 16:53:49.131720
7413 16:53:49.134982 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7414 16:53:49.137929 [DutyScan_Calibration_Flow] ====Done====
7415 16:53:49.138002
7416 16:53:49.141675 [DutyScan_Calibration_Flow] k_type=2
7417 16:53:49.157589
7418 16:53:49.157686 ==DQ 0 ==
7419 16:53:49.161217 Final DQ duty delay cell = -4
7420 16:53:49.164509 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7421 16:53:49.167783 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7422 16:53:49.170807 [-4] AVG Duty = 4968%(X100)
7423 16:53:49.170880
7424 16:53:49.170951 ==DQ 1 ==
7425 16:53:49.174519 Final DQ duty delay cell = 0
7426 16:53:49.177691 [0] MAX Duty = 5124%(X100), DQS PI = 16
7427 16:53:49.180960 [0] MIN Duty = 4938%(X100), DQS PI = 10
7428 16:53:49.184237 [0] AVG Duty = 5031%(X100)
7429 16:53:49.184310
7430 16:53:49.187412 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7431 16:53:49.187487
7432 16:53:49.190655 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7433 16:53:49.194183 [DutyScan_Calibration_Flow] ====Done====
7434 16:53:49.197349 nWR fixed to 30
7435 16:53:49.200636 [ModeRegInit_LP4] CH0 RK0
7436 16:53:49.200718 [ModeRegInit_LP4] CH0 RK1
7437 16:53:49.204691 [ModeRegInit_LP4] CH1 RK0
7438 16:53:49.207697 [ModeRegInit_LP4] CH1 RK1
7439 16:53:49.207770 match AC timing 5
7440 16:53:49.214164 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7441 16:53:49.217543 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7442 16:53:49.220804 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7443 16:53:49.228054 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7444 16:53:49.231177 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7445 16:53:49.231265 [MiockJmeterHQA]
7446 16:53:49.231341
7447 16:53:49.234069 [DramcMiockJmeter] u1RxGatingPI = 0
7448 16:53:49.237694 0 : 4258, 4029
7449 16:53:49.237779 4 : 4363, 4137
7450 16:53:49.240686 8 : 4253, 4026
7451 16:53:49.240767 12 : 4252, 4027
7452 16:53:49.240841 16 : 4252, 4027
7453 16:53:49.244301 20 : 4252, 4027
7454 16:53:49.244382 24 : 4255, 4029
7455 16:53:49.247281 28 : 4363, 4138
7456 16:53:49.247357 32 : 4255, 4029
7457 16:53:49.250934 36 : 4363, 4137
7458 16:53:49.251009 40 : 4250, 4027
7459 16:53:49.254058 44 : 4253, 4027
7460 16:53:49.254161 48 : 4250, 4027
7461 16:53:49.254255 52 : 4360, 4137
7462 16:53:49.257641 56 : 4250, 4027
7463 16:53:49.257717 60 : 4361, 4138
7464 16:53:49.260562 64 : 4250, 4027
7465 16:53:49.260650 68 : 4250, 4027
7466 16:53:49.264356 72 : 4249, 4027
7467 16:53:49.264433 76 : 4250, 4027
7468 16:53:49.267041 80 : 4360, 4138
7469 16:53:49.267118 84 : 4250, 4026
7470 16:53:49.267183 88 : 4361, 70
7471 16:53:49.270347 92 : 4250, 0
7472 16:53:49.270432 96 : 4363, 0
7473 16:53:49.273697 100 : 4250, 0
7474 16:53:49.273778 104 : 4250, 0
7475 16:53:49.273844 108 : 4250, 0
7476 16:53:49.277266 112 : 4250, 0
7477 16:53:49.277373 116 : 4250, 0
7478 16:53:49.277466 120 : 4250, 0
7479 16:53:49.280320 124 : 4361, 0
7480 16:53:49.280418 128 : 4361, 0
7481 16:53:49.284039 132 : 4248, 0
7482 16:53:49.284116 136 : 4250, 0
7483 16:53:49.284186 140 : 4361, 0
7484 16:53:49.287192 144 : 4361, 0
7485 16:53:49.287268 148 : 4250, 0
7486 16:53:49.290418 152 : 4253, 0
7487 16:53:49.290492 156 : 4250, 0
7488 16:53:49.290563 160 : 4250, 0
7489 16:53:49.293728 164 : 4249, 0
7490 16:53:49.293810 168 : 4250, 0
7491 16:53:49.296781 172 : 4255, 0
7492 16:53:49.296855 176 : 4360, 0
7493 16:53:49.296920 180 : 4360, 0
7494 16:53:49.300539 184 : 4248, 0
7495 16:53:49.300618 188 : 4361, 0
7496 16:53:49.303675 192 : 4361, 0
7497 16:53:49.303747 196 : 4361, 0
7498 16:53:49.303818 200 : 4253, 0
7499 16:53:49.306910 204 : 4250, 1297
7500 16:53:49.306981 208 : 4249, 4013
7501 16:53:49.310032 212 : 4252, 4029
7502 16:53:49.310103 216 : 4250, 4027
7503 16:53:49.313289 220 : 4361, 4137
7504 16:53:49.313360 224 : 4360, 4137
7505 16:53:49.317254 228 : 4248, 4024
7506 16:53:49.317333 232 : 4361, 4137
7507 16:53:49.317405 236 : 4360, 4138
7508 16:53:49.320554 240 : 4250, 4027
7509 16:53:49.320645 244 : 4250, 4027
7510 16:53:49.323813 248 : 4252, 4029
7511 16:53:49.323884 252 : 4250, 4027
7512 16:53:49.326996 256 : 4250, 4027
7513 16:53:49.327068 260 : 4250, 4027
7514 16:53:49.330176 264 : 4250, 4027
7515 16:53:49.330246 268 : 4250, 4027
7516 16:53:49.333333 272 : 4360, 4138
7517 16:53:49.333439 276 : 4360, 4137
7518 16:53:49.336688 280 : 4250, 4026
7519 16:53:49.336762 284 : 4361, 4137
7520 16:53:49.340190 288 : 4360, 4138
7521 16:53:49.340266 292 : 4250, 4027
7522 16:53:49.340336 296 : 4250, 4026
7523 16:53:49.343790 300 : 4250, 4027
7524 16:53:49.343867 304 : 4250, 4027
7525 16:53:49.346859 308 : 4249, 3934
7526 16:53:49.346932 312 : 4251, 1818
7527 16:53:49.346995
7528 16:53:49.350494 MIOCK jitter meter ch=0
7529 16:53:49.350579
7530 16:53:49.353708 1T = (312-88) = 224 dly cells
7531 16:53:49.360296 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7532 16:53:49.360381 ==
7533 16:53:49.363886 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 16:53:49.366864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 16:53:49.366947 ==
7536 16:53:49.373398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 16:53:49.376835 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 16:53:49.380019 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 16:53:49.386796 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 16:53:49.395720 [CA 0] Center 42 (12~73) winsize 62
7541 16:53:49.398910 [CA 1] Center 42 (12~73) winsize 62
7542 16:53:49.402080 [CA 2] Center 38 (8~68) winsize 61
7543 16:53:49.405799 [CA 3] Center 37 (8~67) winsize 60
7544 16:53:49.408852 [CA 4] Center 36 (6~66) winsize 61
7545 16:53:49.411946 [CA 5] Center 35 (6~64) winsize 59
7546 16:53:49.412019
7547 16:53:49.415840 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7548 16:53:49.415943
7549 16:53:49.418846 [CATrainingPosCal] consider 1 rank data
7550 16:53:49.422264 u2DelayCellTimex100 = 290/100 ps
7551 16:53:49.425499 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7552 16:53:49.432085 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7553 16:53:49.435296 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7554 16:53:49.438549 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7555 16:53:49.441824 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7556 16:53:49.445448 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7557 16:53:49.445526
7558 16:53:49.448325 CA PerBit enable=1, Macro0, CA PI delay=35
7559 16:53:49.448394
7560 16:53:49.452070 [CBTSetCACLKResult] CA Dly = 35
7561 16:53:49.455224 CS Dly: 9 (0~40)
7562 16:53:49.458719 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 16:53:49.461769 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 16:53:49.461849 ==
7565 16:53:49.465294 Dram Type= 6, Freq= 0, CH_0, rank 1
7566 16:53:49.468330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 16:53:49.472110 ==
7568 16:53:49.475347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7569 16:53:49.478161 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7570 16:53:49.484794 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7571 16:53:49.488663 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7572 16:53:49.498675 [CA 0] Center 43 (13~73) winsize 61
7573 16:53:49.501937 [CA 1] Center 43 (13~73) winsize 61
7574 16:53:49.505717 [CA 2] Center 38 (9~68) winsize 60
7575 16:53:49.508786 [CA 3] Center 38 (8~68) winsize 61
7576 16:53:49.511890 [CA 4] Center 36 (6~66) winsize 61
7577 16:53:49.515738 [CA 5] Center 35 (6~65) winsize 60
7578 16:53:49.515854
7579 16:53:49.518793 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7580 16:53:49.518871
7581 16:53:49.522115 [CATrainingPosCal] consider 2 rank data
7582 16:53:49.525258 u2DelayCellTimex100 = 290/100 ps
7583 16:53:49.529115 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7584 16:53:50.019991 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7585 16:53:50.020188 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7586 16:53:50.020292 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7587 16:53:50.020371 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7588 16:53:50.020449 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7589 16:53:50.020539
7590 16:53:50.020629 CA PerBit enable=1, Macro0, CA PI delay=35
7591 16:53:50.020739
7592 16:53:50.020797 [CBTSetCACLKResult] CA Dly = 35
7593 16:53:50.020855 CS Dly: 10 (0~42)
7594 16:53:50.020912 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7595 16:53:50.020998 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7596 16:53:50.021055
7597 16:53:50.021140 ----->DramcWriteLeveling(PI) begin...
7598 16:53:50.021198 ==
7599 16:53:50.021255 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 16:53:50.021311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 16:53:50.021367 ==
7602 16:53:50.021423 Write leveling (Byte 0): 34 => 34
7603 16:53:50.021478 Write leveling (Byte 1): 29 => 29
7604 16:53:50.021559 DramcWriteLeveling(PI) end<-----
7605 16:53:50.021661
7606 16:53:50.021716 ==
7607 16:53:50.021772 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 16:53:50.021827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 16:53:50.021882 ==
7610 16:53:50.021937 [Gating] SW mode calibration
7611 16:53:50.021993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7612 16:53:50.022050 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7613 16:53:50.022151 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 16:53:50.022232 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 16:53:50.022302 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7616 16:53:50.022360 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7617 16:53:50.022417 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7618 16:53:50.022472 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 16:53:50.022528 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7620 16:53:50.022610 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 16:53:50.022666 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 16:53:50.022722 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7623 16:53:50.022776 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7624 16:53:50.022831 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7625 16:53:50.022886 1 5 16 | B1->B0 | 3434 2625 | 1 1 | (1 0) (0 0)
7626 16:53:50.022941 1 5 20 | B1->B0 | 2b2b 2424 | 0 0 | (1 0) (0 0)
7627 16:53:50.022995 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7628 16:53:50.023117 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 16:53:50.023174 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 16:53:50.023229 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 16:53:50.023284 1 6 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
7632 16:53:50.023339 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7633 16:53:50.023393 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7634 16:53:50.023447 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7635 16:53:50.023502 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 16:53:50.023556 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 16:53:50.023611 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 16:53:50.023666 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 16:53:50.023721 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 16:53:50.023775 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7641 16:53:50.023830 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7642 16:53:50.023885 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7643 16:53:50.023939 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 16:53:50.023993 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 16:53:50.024047 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 16:53:50.024102 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 16:53:50.024172 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 16:53:50.024257 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 16:53:50.024342 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 16:53:50.024411 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 16:53:50.024465 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 16:53:50.024520 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 16:53:50.024574 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 16:53:50.024628 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 16:53:50.024682 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 16:53:50.024736 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7657 16:53:50.024791 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7658 16:53:50.024845 Total UI for P1: 0, mck2ui 16
7659 16:53:50.024900 best dqsien dly found for B0: ( 1, 9, 12)
7660 16:53:50.024955 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7661 16:53:50.025009 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 16:53:50.025064 Total UI for P1: 0, mck2ui 16
7663 16:53:50.025119 best dqsien dly found for B1: ( 1, 9, 18)
7664 16:53:50.025173 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7665 16:53:50.025228 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7666 16:53:50.025283
7667 16:53:50.025338 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7668 16:53:50.025393 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7669 16:53:50.025447 [Gating] SW calibration Done
7670 16:53:50.025502 ==
7671 16:53:50.025597 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 16:53:50.025653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 16:53:50.025708 ==
7674 16:53:50.025763 RX Vref Scan: 0
7675 16:53:50.025817
7676 16:53:50.025872 RX Vref 0 -> 0, step: 1
7677 16:53:50.025927
7678 16:53:50.025981 RX Delay 0 -> 252, step: 8
7679 16:53:50.026036 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7680 16:53:50.026091 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7681 16:53:50.026147 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7682 16:53:50.026201 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7683 16:53:50.026256 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7684 16:53:50.026310 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7685 16:53:50.026551 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7686 16:53:50.026616 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7687 16:53:50.026673 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7688 16:53:50.026728 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7689 16:53:50.026783 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7690 16:53:50.026838 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7691 16:53:50.026893 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7692 16:53:50.026948 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7693 16:53:50.027002 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7694 16:53:50.027057 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7695 16:53:50.027112 ==
7696 16:53:50.027167 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 16:53:50.027223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 16:53:50.027278 ==
7699 16:53:50.027333 DQS Delay:
7700 16:53:50.027387 DQS0 = 0, DQS1 = 0
7701 16:53:50.027442 DQM Delay:
7702 16:53:50.027497 DQM0 = 136, DQM1 = 130
7703 16:53:50.027552 DQ Delay:
7704 16:53:50.027606 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7705 16:53:50.027661 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7706 16:53:50.027715 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7707 16:53:50.027770 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7708 16:53:50.027824
7709 16:53:50.027878
7710 16:53:50.027933 ==
7711 16:53:50.027988 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 16:53:50.028043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 16:53:50.028098 ==
7714 16:53:50.028153
7715 16:53:50.028207
7716 16:53:50.028261 TX Vref Scan disable
7717 16:53:50.028316 == TX Byte 0 ==
7718 16:53:50.028371 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7719 16:53:50.028426 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7720 16:53:50.028481 == TX Byte 1 ==
7721 16:53:50.028535 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7722 16:53:50.028590 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7723 16:53:50.028645 ==
7724 16:53:50.028699 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 16:53:50.028754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 16:53:50.028809 ==
7727 16:53:50.028864
7728 16:53:50.028917 TX Vref early break, caculate TX vref
7729 16:53:50.028972 TX Vref=16, minBit 0, minWin=23, winSum=383
7730 16:53:50.029027 TX Vref=18, minBit 6, minWin=23, winSum=391
7731 16:53:50.029082 TX Vref=20, minBit 0, minWin=24, winSum=400
7732 16:53:50.029137 TX Vref=22, minBit 0, minWin=24, winSum=408
7733 16:53:50.029191 TX Vref=24, minBit 6, minWin=25, winSum=418
7734 16:53:50.030933 TX Vref=26, minBit 1, minWin=25, winSum=425
7735 16:53:50.034232 TX Vref=28, minBit 6, minWin=25, winSum=427
7736 16:53:50.037555 TX Vref=30, minBit 1, minWin=25, winSum=416
7737 16:53:50.040760 TX Vref=32, minBit 1, minWin=24, winSum=403
7738 16:53:50.047535 [TxChooseVref] Worse bit 6, Min win 25, Win sum 427, Final Vref 28
7739 16:53:50.047621
7740 16:53:50.050660 Final TX Range 0 Vref 28
7741 16:53:50.050775
7742 16:53:50.050879 ==
7743 16:53:50.054302 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 16:53:50.057531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 16:53:50.057618 ==
7746 16:53:50.057703
7747 16:53:50.057783
7748 16:53:50.060740 TX Vref Scan disable
7749 16:53:50.064111 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7750 16:53:50.067398 == TX Byte 0 ==
7751 16:53:50.070529 u2DelayCellOfst[0]=13 cells (4 PI)
7752 16:53:50.073784 u2DelayCellOfst[1]=16 cells (5 PI)
7753 16:53:50.077731 u2DelayCellOfst[2]=13 cells (4 PI)
7754 16:53:50.080742 u2DelayCellOfst[3]=10 cells (3 PI)
7755 16:53:50.084015 u2DelayCellOfst[4]=10 cells (3 PI)
7756 16:53:50.084102 u2DelayCellOfst[5]=0 cells (0 PI)
7757 16:53:50.087274 u2DelayCellOfst[6]=16 cells (5 PI)
7758 16:53:50.090553 u2DelayCellOfst[7]=13 cells (4 PI)
7759 16:53:50.097604 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7760 16:53:50.100718 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7761 16:53:50.100804 == TX Byte 1 ==
7762 16:53:50.104203 u2DelayCellOfst[8]=0 cells (0 PI)
7763 16:53:50.107235 u2DelayCellOfst[9]=3 cells (1 PI)
7764 16:53:50.110786 u2DelayCellOfst[10]=6 cells (2 PI)
7765 16:53:50.113941 u2DelayCellOfst[11]=3 cells (1 PI)
7766 16:53:50.117691 u2DelayCellOfst[12]=13 cells (4 PI)
7767 16:53:50.120545 u2DelayCellOfst[13]=10 cells (3 PI)
7768 16:53:50.124238 u2DelayCellOfst[14]=13 cells (4 PI)
7769 16:53:50.127213 u2DelayCellOfst[15]=13 cells (4 PI)
7770 16:53:50.130348 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7771 16:53:50.134154 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7772 16:53:50.137119 DramC Write-DBI on
7773 16:53:50.137208 ==
7774 16:53:50.140997 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 16:53:50.143566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 16:53:50.143652 ==
7777 16:53:50.143738
7778 16:53:50.143817
7779 16:53:50.147431 TX Vref Scan disable
7780 16:53:50.150546 == TX Byte 0 ==
7781 16:53:50.153661 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7782 16:53:50.157294 == TX Byte 1 ==
7783 16:53:50.160256 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7784 16:53:50.160343 DramC Write-DBI off
7785 16:53:50.160458
7786 16:53:50.163483 [DATLAT]
7787 16:53:50.163569 Freq=1600, CH0 RK0
7788 16:53:50.163655
7789 16:53:50.166858 DATLAT Default: 0xf
7790 16:53:50.166944 0, 0xFFFF, sum = 0
7791 16:53:50.170790 1, 0xFFFF, sum = 0
7792 16:53:50.170878 2, 0xFFFF, sum = 0
7793 16:53:50.173975 3, 0xFFFF, sum = 0
7794 16:53:50.174061 4, 0xFFFF, sum = 0
7795 16:53:50.177174 5, 0xFFFF, sum = 0
7796 16:53:50.177262 6, 0xFFFF, sum = 0
7797 16:53:50.180549 7, 0xFFFF, sum = 0
7798 16:53:50.180635 8, 0xFFFF, sum = 0
7799 16:53:50.183541 9, 0xFFFF, sum = 0
7800 16:53:50.186959 10, 0xFFFF, sum = 0
7801 16:53:50.187049 11, 0xFFFF, sum = 0
7802 16:53:50.190227 12, 0xFFFF, sum = 0
7803 16:53:50.190311 13, 0xFFFF, sum = 0
7804 16:53:50.193468 14, 0x0, sum = 1
7805 16:53:50.193571 15, 0x0, sum = 2
7806 16:53:50.196838 16, 0x0, sum = 3
7807 16:53:50.196923 17, 0x0, sum = 4
7808 16:53:50.196990 best_step = 15
7809 16:53:50.200091
7810 16:53:50.200174 ==
7811 16:53:50.203687 Dram Type= 6, Freq= 0, CH_0, rank 0
7812 16:53:50.206676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7813 16:53:50.206760 ==
7814 16:53:50.206826 RX Vref Scan: 1
7815 16:53:50.206889
7816 16:53:50.210318 Set Vref Range= 24 -> 127
7817 16:53:50.210411
7818 16:53:50.213399 RX Vref 24 -> 127, step: 1
7819 16:53:50.213482
7820 16:53:50.216994 RX Delay 19 -> 252, step: 4
7821 16:53:50.217077
7822 16:53:50.219960 Set Vref, RX VrefLevel [Byte0]: 24
7823 16:53:50.223517 [Byte1]: 24
7824 16:53:50.223600
7825 16:53:50.226615 Set Vref, RX VrefLevel [Byte0]: 25
7826 16:53:50.229890 [Byte1]: 25
7827 16:53:50.229977
7828 16:53:50.233612 Set Vref, RX VrefLevel [Byte0]: 26
7829 16:53:50.236928 [Byte1]: 26
7830 16:53:50.240600
7831 16:53:50.240684 Set Vref, RX VrefLevel [Byte0]: 27
7832 16:53:50.243747 [Byte1]: 27
7833 16:53:50.248204
7834 16:53:50.248287 Set Vref, RX VrefLevel [Byte0]: 28
7835 16:53:50.251412 [Byte1]: 28
7836 16:53:50.255345
7837 16:53:50.255427 Set Vref, RX VrefLevel [Byte0]: 29
7838 16:53:50.258980 [Byte1]: 29
7839 16:53:50.262818
7840 16:53:50.262903 Set Vref, RX VrefLevel [Byte0]: 30
7841 16:53:50.266369 [Byte1]: 30
7842 16:53:50.270422
7843 16:53:50.270532 Set Vref, RX VrefLevel [Byte0]: 31
7844 16:53:50.273654 [Byte1]: 31
7845 16:53:50.278133
7846 16:53:50.278221 Set Vref, RX VrefLevel [Byte0]: 32
7847 16:53:50.281423 [Byte1]: 32
7848 16:53:50.285855
7849 16:53:50.285939 Set Vref, RX VrefLevel [Byte0]: 33
7850 16:53:50.289033 [Byte1]: 33
7851 16:53:50.293101
7852 16:53:50.293184 Set Vref, RX VrefLevel [Byte0]: 34
7853 16:53:50.296957 [Byte1]: 34
7854 16:53:50.300966
7855 16:53:50.301049 Set Vref, RX VrefLevel [Byte0]: 35
7856 16:53:50.304214 [Byte1]: 35
7857 16:53:50.308424
7858 16:53:50.308520 Set Vref, RX VrefLevel [Byte0]: 36
7859 16:53:50.311619 [Byte1]: 36
7860 16:53:50.315818
7861 16:53:50.315901 Set Vref, RX VrefLevel [Byte0]: 37
7862 16:53:50.319353 [Byte1]: 37
7863 16:53:50.323445
7864 16:53:50.323528 Set Vref, RX VrefLevel [Byte0]: 38
7865 16:53:50.327123 [Byte1]: 38
7866 16:53:50.331343
7867 16:53:50.331427 Set Vref, RX VrefLevel [Byte0]: 39
7868 16:53:50.334322 [Byte1]: 39
7869 16:53:50.339109
7870 16:53:50.339195 Set Vref, RX VrefLevel [Byte0]: 40
7871 16:53:50.341929 [Byte1]: 40
7872 16:53:50.346521
7873 16:53:50.346604 Set Vref, RX VrefLevel [Byte0]: 41
7874 16:53:50.349657 [Byte1]: 41
7875 16:53:50.354230
7876 16:53:50.354313 Set Vref, RX VrefLevel [Byte0]: 42
7877 16:53:50.357366 [Byte1]: 42
7878 16:53:50.361297
7879 16:53:50.361420 Set Vref, RX VrefLevel [Byte0]: 43
7880 16:53:50.364607 [Byte1]: 43
7881 16:53:50.368903
7882 16:53:50.368997 Set Vref, RX VrefLevel [Byte0]: 44
7883 16:53:50.372498 [Byte1]: 44
7884 16:53:50.376836
7885 16:53:50.376919 Set Vref, RX VrefLevel [Byte0]: 45
7886 16:53:50.380006 [Byte1]: 45
7887 16:53:50.383954
7888 16:53:50.384037 Set Vref, RX VrefLevel [Byte0]: 46
7889 16:53:50.387182 [Byte1]: 46
7890 16:53:50.392239
7891 16:53:50.392323 Set Vref, RX VrefLevel [Byte0]: 47
7892 16:53:50.394731 [Byte1]: 47
7893 16:53:50.399438
7894 16:53:50.399521 Set Vref, RX VrefLevel [Byte0]: 48
7895 16:53:50.402834 [Byte1]: 48
7896 16:53:50.406724
7897 16:53:50.406807 Set Vref, RX VrefLevel [Byte0]: 49
7898 16:53:50.409964 [Byte1]: 49
7899 16:53:50.414377
7900 16:53:50.414460 Set Vref, RX VrefLevel [Byte0]: 50
7901 16:53:50.417507 [Byte1]: 50
7902 16:53:50.422304
7903 16:53:50.422387 Set Vref, RX VrefLevel [Byte0]: 51
7904 16:53:50.425272 [Byte1]: 51
7905 16:53:50.429396
7906 16:53:50.429479 Set Vref, RX VrefLevel [Byte0]: 52
7907 16:53:50.432964 [Byte1]: 52
7908 16:53:50.437350
7909 16:53:50.437434 Set Vref, RX VrefLevel [Byte0]: 53
7910 16:53:50.440288 [Byte1]: 53
7911 16:53:50.444458
7912 16:53:50.444543 Set Vref, RX VrefLevel [Byte0]: 54
7913 16:53:50.448155 [Byte1]: 54
7914 16:53:50.452464
7915 16:53:50.452548 Set Vref, RX VrefLevel [Byte0]: 55
7916 16:53:50.455498 [Byte1]: 55
7917 16:53:50.459867
7918 16:53:50.459951 Set Vref, RX VrefLevel [Byte0]: 56
7919 16:53:50.463091 [Byte1]: 56
7920 16:53:50.467767
7921 16:53:50.467851 Set Vref, RX VrefLevel [Byte0]: 57
7922 16:53:50.470761 [Byte1]: 57
7923 16:53:50.475194
7924 16:53:50.475278 Set Vref, RX VrefLevel [Byte0]: 58
7925 16:53:50.478253 [Byte1]: 58
7926 16:53:50.482486
7927 16:53:50.482570 Set Vref, RX VrefLevel [Byte0]: 59
7928 16:53:50.485818 [Byte1]: 59
7929 16:53:50.490284
7930 16:53:50.490368 Set Vref, RX VrefLevel [Byte0]: 60
7931 16:53:50.493433 [Byte1]: 60
7932 16:53:50.497778
7933 16:53:50.497861 Set Vref, RX VrefLevel [Byte0]: 61
7934 16:53:50.501201 [Byte1]: 61
7935 16:53:50.504992
7936 16:53:50.505077 Set Vref, RX VrefLevel [Byte0]: 62
7937 16:53:50.508305 [Byte1]: 62
7938 16:53:50.512864
7939 16:53:50.512948 Set Vref, RX VrefLevel [Byte0]: 63
7940 16:53:50.516223 [Byte1]: 63
7941 16:53:50.520540
7942 16:53:50.520617 Set Vref, RX VrefLevel [Byte0]: 64
7943 16:53:50.523631 [Byte1]: 64
7944 16:53:50.527857
7945 16:53:50.527933 Set Vref, RX VrefLevel [Byte0]: 65
7946 16:53:50.531408 [Byte1]: 65
7947 16:53:50.535819
7948 16:53:50.535897 Set Vref, RX VrefLevel [Byte0]: 66
7949 16:53:50.538755 [Byte1]: 66
7950 16:53:50.542998
7951 16:53:50.543075 Set Vref, RX VrefLevel [Byte0]: 67
7952 16:53:50.546469 [Byte1]: 67
7953 16:53:50.550622
7954 16:53:50.550699 Set Vref, RX VrefLevel [Byte0]: 68
7955 16:53:50.554455 [Byte1]: 68
7956 16:53:50.558609
7957 16:53:50.558686 Set Vref, RX VrefLevel [Byte0]: 69
7958 16:53:50.561774 [Byte1]: 69
7959 16:53:50.566226
7960 16:53:50.566312 Set Vref, RX VrefLevel [Byte0]: 70
7961 16:53:50.569453 [Byte1]: 70
7962 16:53:50.573176
7963 16:53:50.573261 Set Vref, RX VrefLevel [Byte0]: 71
7964 16:53:50.576615 [Byte1]: 71
7965 16:53:50.581384
7966 16:53:50.581490 Set Vref, RX VrefLevel [Byte0]: 72
7967 16:53:50.584284 [Byte1]: 72
7968 16:53:50.588713
7969 16:53:50.588794 Set Vref, RX VrefLevel [Byte0]: 73
7970 16:53:50.591939 [Byte1]: 73
7971 16:53:50.596354
7972 16:53:50.596428 Set Vref, RX VrefLevel [Byte0]: 74
7973 16:53:50.599395 [Byte1]: 74
7974 16:53:50.603884
7975 16:53:50.603960 Set Vref, RX VrefLevel [Byte0]: 75
7976 16:53:50.607126 [Byte1]: 75
7977 16:53:50.611162
7978 16:53:50.611233 Set Vref, RX VrefLevel [Byte0]: 76
7979 16:53:50.614500 [Byte1]: 76
7980 16:53:50.618641
7981 16:53:50.618712 Final RX Vref Byte 0 = 59 to rank0
7982 16:53:50.622461 Final RX Vref Byte 1 = 62 to rank0
7983 16:53:50.625717 Final RX Vref Byte 0 = 59 to rank1
7984 16:53:50.628716 Final RX Vref Byte 1 = 62 to rank1==
7985 16:53:50.632336 Dram Type= 6, Freq= 0, CH_0, rank 0
7986 16:53:50.639031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 16:53:50.639131 ==
7988 16:53:50.639287 DQS Delay:
7989 16:53:50.639354 DQS0 = 0, DQS1 = 0
7990 16:53:50.642167 DQM Delay:
7991 16:53:50.642243 DQM0 = 134, DQM1 = 128
7992 16:53:50.645275 DQ Delay:
7993 16:53:50.648800 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7994 16:53:50.652415 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7995 16:53:50.655229 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7996 16:53:50.658766 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7997 16:53:50.658858
7998 16:53:50.658942
7999 16:53:50.659041
8000 16:53:50.662026 [DramC_TX_OE_Calibration] TA2
8001 16:53:50.665130 Original DQ_B0 (3 6) =30, OEN = 27
8002 16:53:50.668860 Original DQ_B1 (3 6) =30, OEN = 27
8003 16:53:50.672024 24, 0x0, End_B0=24 End_B1=24
8004 16:53:50.672110 25, 0x0, End_B0=25 End_B1=25
8005 16:53:50.675267 26, 0x0, End_B0=26 End_B1=26
8006 16:53:50.678551 27, 0x0, End_B0=27 End_B1=27
8007 16:53:50.682255 28, 0x0, End_B0=28 End_B1=28
8008 16:53:50.682366 29, 0x0, End_B0=29 End_B1=29
8009 16:53:50.685367 30, 0x0, End_B0=30 End_B1=30
8010 16:53:50.689009 31, 0x4545, End_B0=30 End_B1=30
8011 16:53:50.692162 Byte0 end_step=30 best_step=27
8012 16:53:50.695519 Byte1 end_step=30 best_step=27
8013 16:53:50.698747 Byte0 TX OE(2T, 0.5T) = (3, 3)
8014 16:53:50.698884 Byte1 TX OE(2T, 0.5T) = (3, 3)
8015 16:53:50.701995
8016 16:53:50.702078
8017 16:53:50.708499 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
8018 16:53:50.711819 CH0 RK0: MR19=303, MR18=231F
8019 16:53:50.718977 CH0_RK0: MR19=0x303, MR18=0x231F, DQSOSC=392, MR23=63, INC=24, DEC=16
8020 16:53:50.719062
8021 16:53:50.722155 ----->DramcWriteLeveling(PI) begin...
8022 16:53:50.722240 ==
8023 16:53:50.725310 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 16:53:50.728641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 16:53:50.728734 ==
8026 16:53:50.731702 Write leveling (Byte 0): 37 => 37
8027 16:53:50.735413 Write leveling (Byte 1): 25 => 25
8028 16:53:50.738650 DramcWriteLeveling(PI) end<-----
8029 16:53:50.738734
8030 16:53:50.738804 ==
8031 16:53:50.742109 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 16:53:50.745116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 16:53:50.745209 ==
8034 16:53:50.748731 [Gating] SW mode calibration
8035 16:53:50.754944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8036 16:53:50.761908 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8037 16:53:50.764921 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 16:53:50.768498 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8039 16:53:50.774923 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8040 16:53:50.778494 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8041 16:53:50.781800 1 4 16 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8042 16:53:50.788223 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8043 16:53:50.791726 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8044 16:53:50.795291 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 16:53:50.801744 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 16:53:50.805076 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
8047 16:53:50.808208 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 16:53:50.815452 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
8049 16:53:50.818740 1 5 16 | B1->B0 | 3333 2525 | 0 0 | (1 0) (1 1)
8050 16:53:50.821760 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 16:53:50.828465 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8052 16:53:50.831719 1 5 28 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8053 16:53:50.835017 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 16:53:50.838234 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8055 16:53:50.844888 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 16:53:50.848351 1 6 12 | B1->B0 | 2424 3837 | 0 1 | (0 0) (1 1)
8057 16:53:50.851937 1 6 16 | B1->B0 | 3b3b 4645 | 0 1 | (0 0) (0 0)
8058 16:53:50.858025 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 16:53:50.861736 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 16:53:50.864612 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 16:53:50.871643 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 16:53:50.874655 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 16:53:50.877967 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 16:53:50.884858 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8065 16:53:50.888021 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8066 16:53:50.891332 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 16:53:50.897771 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 16:53:50.901347 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 16:53:50.904964 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 16:53:50.911449 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 16:53:50.914566 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 16:53:50.917943 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 16:53:50.924521 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 16:53:50.927697 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 16:53:50.931807 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 16:53:50.938381 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 16:53:50.941458 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 16:53:50.944692 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 16:53:50.951339 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 16:53:50.954794 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8081 16:53:50.957858 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8082 16:53:50.964586 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 16:53:50.964705 Total UI for P1: 0, mck2ui 16
8084 16:53:50.971238 best dqsien dly found for B0: ( 1, 9, 14)
8085 16:53:50.971328 Total UI for P1: 0, mck2ui 16
8086 16:53:50.974333 best dqsien dly found for B1: ( 1, 9, 14)
8087 16:53:50.981086 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8088 16:53:50.984760 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8089 16:53:50.984846
8090 16:53:50.987903 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8091 16:53:50.991168 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8092 16:53:50.994552 [Gating] SW calibration Done
8093 16:53:50.994636 ==
8094 16:53:50.997790 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 16:53:51.000983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 16:53:51.001068 ==
8097 16:53:51.004718 RX Vref Scan: 0
8098 16:53:51.004804
8099 16:53:51.004871 RX Vref 0 -> 0, step: 1
8100 16:53:51.004934
8101 16:53:51.007747 RX Delay 0 -> 252, step: 8
8102 16:53:51.011269 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8103 16:53:51.014254 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8104 16:53:51.021331 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8105 16:53:51.024514 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8106 16:53:51.027841 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8107 16:53:51.031151 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8108 16:53:51.034385 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8109 16:53:51.041028 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8110 16:53:51.044321 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8111 16:53:51.047735 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8112 16:53:51.050972 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8113 16:53:51.053994 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8114 16:53:51.060675 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8115 16:53:51.064231 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8116 16:53:51.067935 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8117 16:53:51.070859 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8118 16:53:51.070945 ==
8119 16:53:51.074080 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 16:53:51.080613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 16:53:51.080700 ==
8122 16:53:51.080794 DQS Delay:
8123 16:53:51.084388 DQS0 = 0, DQS1 = 0
8124 16:53:51.084504 DQM Delay:
8125 16:53:51.087694 DQM0 = 137, DQM1 = 128
8126 16:53:51.087812 DQ Delay:
8127 16:53:51.090928 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8128 16:53:51.094384 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8129 16:53:51.097650 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8130 16:53:51.100938 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8131 16:53:51.101014
8132 16:53:51.101108
8133 16:53:51.101167 ==
8134 16:53:51.104117 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 16:53:51.110521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 16:53:51.110606 ==
8137 16:53:51.110672
8138 16:53:51.110734
8139 16:53:51.110792 TX Vref Scan disable
8140 16:53:51.114272 == TX Byte 0 ==
8141 16:53:51.117812 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8142 16:53:51.124343 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8143 16:53:51.124524 == TX Byte 1 ==
8144 16:53:51.127430 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8145 16:53:51.133884 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8146 16:53:51.133969 ==
8147 16:53:51.137162 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 16:53:51.140526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 16:53:51.140610 ==
8150 16:53:51.155463
8151 16:53:51.159088 TX Vref early break, caculate TX vref
8152 16:53:51.162272 TX Vref=16, minBit 3, minWin=22, winSum=384
8153 16:53:51.165782 TX Vref=18, minBit 4, minWin=23, winSum=398
8154 16:53:51.168688 TX Vref=20, minBit 0, minWin=24, winSum=407
8155 16:53:51.172183 TX Vref=22, minBit 1, minWin=25, winSum=411
8156 16:53:51.175353 TX Vref=24, minBit 1, minWin=25, winSum=419
8157 16:53:51.182341 TX Vref=26, minBit 7, minWin=25, winSum=425
8158 16:53:51.185498 TX Vref=28, minBit 0, minWin=26, winSum=427
8159 16:53:51.189260 TX Vref=30, minBit 0, minWin=25, winSum=420
8160 16:53:51.192599 TX Vref=32, minBit 1, minWin=24, winSum=409
8161 16:53:51.195833 TX Vref=34, minBit 0, minWin=24, winSum=408
8162 16:53:51.198921 TX Vref=36, minBit 0, minWin=24, winSum=394
8163 16:53:51.205398 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8164 16:53:51.205521
8165 16:53:51.208892 Final TX Range 0 Vref 28
8166 16:53:51.208977
8167 16:53:51.209044 ==
8168 16:53:51.212210 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 16:53:51.215473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 16:53:51.215558 ==
8171 16:53:51.215626
8172 16:53:51.215687
8173 16:53:51.218809 TX Vref Scan disable
8174 16:53:51.225441 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8175 16:53:51.225583 == TX Byte 0 ==
8176 16:53:51.228564 u2DelayCellOfst[0]=10 cells (3 PI)
8177 16:53:51.232260 u2DelayCellOfst[1]=13 cells (4 PI)
8178 16:53:51.235332 u2DelayCellOfst[2]=10 cells (3 PI)
8179 16:53:51.238701 u2DelayCellOfst[3]=10 cells (3 PI)
8180 16:53:51.241814 u2DelayCellOfst[4]=6 cells (2 PI)
8181 16:53:51.245220 u2DelayCellOfst[5]=0 cells (0 PI)
8182 16:53:51.248495 u2DelayCellOfst[6]=13 cells (4 PI)
8183 16:53:51.251776 u2DelayCellOfst[7]=13 cells (4 PI)
8184 16:53:51.255215 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8185 16:53:51.258464 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8186 16:53:51.261724 == TX Byte 1 ==
8187 16:53:51.265332 u2DelayCellOfst[8]=3 cells (1 PI)
8188 16:53:51.268320 u2DelayCellOfst[9]=0 cells (0 PI)
8189 16:53:51.268405 u2DelayCellOfst[10]=6 cells (2 PI)
8190 16:53:51.272180 u2DelayCellOfst[11]=3 cells (1 PI)
8191 16:53:51.275382 u2DelayCellOfst[12]=13 cells (4 PI)
8192 16:53:51.278486 u2DelayCellOfst[13]=10 cells (3 PI)
8193 16:53:51.282188 u2DelayCellOfst[14]=13 cells (4 PI)
8194 16:53:51.285411 u2DelayCellOfst[15]=10 cells (3 PI)
8195 16:53:51.291597 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8196 16:53:51.295181 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8197 16:53:51.295258 DramC Write-DBI on
8198 16:53:51.295324 ==
8199 16:53:51.298278 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 16:53:51.304890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 16:53:51.304972 ==
8202 16:53:51.305039
8203 16:53:51.305101
8204 16:53:51.305181 TX Vref Scan disable
8205 16:53:51.309146 == TX Byte 0 ==
8206 16:53:51.312460 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8207 16:53:51.315813 == TX Byte 1 ==
8208 16:53:51.319180 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8209 16:53:51.322442 DramC Write-DBI off
8210 16:53:51.322516
8211 16:53:51.322582 [DATLAT]
8212 16:53:51.322647 Freq=1600, CH0 RK1
8213 16:53:51.322711
8214 16:53:51.325727 DATLAT Default: 0xf
8215 16:53:51.325809 0, 0xFFFF, sum = 0
8216 16:53:51.329063 1, 0xFFFF, sum = 0
8217 16:53:51.329139 2, 0xFFFF, sum = 0
8218 16:53:51.332618 3, 0xFFFF, sum = 0
8219 16:53:51.335696 4, 0xFFFF, sum = 0
8220 16:53:51.335767 5, 0xFFFF, sum = 0
8221 16:53:51.338771 6, 0xFFFF, sum = 0
8222 16:53:51.338845 7, 0xFFFF, sum = 0
8223 16:53:51.342412 8, 0xFFFF, sum = 0
8224 16:53:51.342486 9, 0xFFFF, sum = 0
8225 16:53:51.345677 10, 0xFFFF, sum = 0
8226 16:53:51.345752 11, 0xFFFF, sum = 0
8227 16:53:51.349079 12, 0xFFFF, sum = 0
8228 16:53:51.349189 13, 0xFFFF, sum = 0
8229 16:53:51.352313 14, 0x0, sum = 1
8230 16:53:51.352425 15, 0x0, sum = 2
8231 16:53:51.355570 16, 0x0, sum = 3
8232 16:53:51.355666 17, 0x0, sum = 4
8233 16:53:51.358885 best_step = 15
8234 16:53:51.358986
8235 16:53:51.359077 ==
8236 16:53:51.362154 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 16:53:51.365911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 16:53:51.365990 ==
8239 16:53:51.366057 RX Vref Scan: 0
8240 16:53:51.369098
8241 16:53:51.369172 RX Vref 0 -> 0, step: 1
8242 16:53:51.369237
8243 16:53:51.372355 RX Delay 19 -> 252, step: 4
8244 16:53:51.375849 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8245 16:53:51.382174 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8246 16:53:51.385394 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8247 16:53:51.389124 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8248 16:53:51.392126 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8249 16:53:51.395785 iDelay=191, Bit 5, Center 128 (75 ~ 182) 108
8250 16:53:51.402297 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8251 16:53:51.405459 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8252 16:53:51.408963 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8253 16:53:51.412033 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8254 16:53:51.415310 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8255 16:53:51.422439 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8256 16:53:51.425749 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8257 16:53:51.429128 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8258 16:53:51.432498 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8259 16:53:51.435610 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8260 16:53:51.438729 ==
8261 16:53:51.438809 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 16:53:51.445624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 16:53:51.445831 ==
8264 16:53:51.445927 DQS Delay:
8265 16:53:51.449237 DQS0 = 0, DQS1 = 0
8266 16:53:51.449322 DQM Delay:
8267 16:53:51.452345 DQM0 = 134, DQM1 = 127
8268 16:53:51.452429 DQ Delay:
8269 16:53:51.455609 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8270 16:53:51.458844 DQ4 =136, DQ5 =128, DQ6 =140, DQ7 =140
8271 16:53:51.462102 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8272 16:53:51.465304 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8273 16:53:51.465388
8274 16:53:51.465455
8275 16:53:51.465540
8276 16:53:51.468600 [DramC_TX_OE_Calibration] TA2
8277 16:53:51.471883 Original DQ_B0 (3 6) =30, OEN = 27
8278 16:53:51.475218 Original DQ_B1 (3 6) =30, OEN = 27
8279 16:53:51.478948 24, 0x0, End_B0=24 End_B1=24
8280 16:53:51.481961 25, 0x0, End_B0=25 End_B1=25
8281 16:53:51.482053 26, 0x0, End_B0=26 End_B1=26
8282 16:53:51.485703 27, 0x0, End_B0=27 End_B1=27
8283 16:53:51.488482 28, 0x0, End_B0=28 End_B1=28
8284 16:53:51.491814 29, 0x0, End_B0=29 End_B1=29
8285 16:53:51.491899 30, 0x0, End_B0=30 End_B1=30
8286 16:53:51.495434 31, 0x4545, End_B0=30 End_B1=30
8287 16:53:51.498569 Byte0 end_step=30 best_step=27
8288 16:53:51.502027 Byte1 end_step=30 best_step=27
8289 16:53:51.505143 Byte0 TX OE(2T, 0.5T) = (3, 3)
8290 16:53:51.508949 Byte1 TX OE(2T, 0.5T) = (3, 3)
8291 16:53:51.509032
8292 16:53:51.509099
8293 16:53:51.515389 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8294 16:53:51.518563 CH0 RK1: MR19=303, MR18=220A
8295 16:53:51.525208 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8296 16:53:51.528443 [RxdqsGatingPostProcess] freq 1600
8297 16:53:51.531837 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8298 16:53:51.535182 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 16:53:51.538361 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 16:53:51.542046 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 16:53:51.545165 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 16:53:51.548426 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 16:53:51.552171 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 16:53:51.554988 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 16:53:51.558709 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 16:53:51.562115 Pre-setting of DQS Precalculation
8307 16:53:51.565260 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8308 16:53:51.565345 ==
8309 16:53:51.568679 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 16:53:51.571896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 16:53:51.575309 ==
8312 16:53:51.578500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 16:53:51.581722 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 16:53:51.588538 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 16:53:51.594815 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 16:53:51.602449 [CA 0] Center 42 (12~72) winsize 61
8317 16:53:51.605362 [CA 1] Center 42 (13~72) winsize 60
8318 16:53:51.609037 [CA 2] Center 39 (9~69) winsize 61
8319 16:53:51.612039 [CA 3] Center 38 (9~67) winsize 59
8320 16:53:51.615746 [CA 4] Center 38 (9~68) winsize 60
8321 16:53:51.619016 [CA 5] Center 37 (8~67) winsize 60
8322 16:53:51.619101
8323 16:53:51.622222 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8324 16:53:51.622306
8325 16:53:51.625315 [CATrainingPosCal] consider 1 rank data
8326 16:53:51.628723 u2DelayCellTimex100 = 290/100 ps
8327 16:53:51.631963 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8328 16:53:51.638536 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8329 16:53:51.641924 CA2 delay=39 (9~69),Diff = 2 PI (6 cell)
8330 16:53:51.645724 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8331 16:53:51.648855 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8332 16:53:51.652200 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8333 16:53:51.652284
8334 16:53:51.655413 CA PerBit enable=1, Macro0, CA PI delay=37
8335 16:53:51.655497
8336 16:53:51.658574 [CBTSetCACLKResult] CA Dly = 37
8337 16:53:51.661691 CS Dly: 10 (0~41)
8338 16:53:51.665366 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 16:53:51.668361 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 16:53:51.668446 ==
8341 16:53:51.671580 Dram Type= 6, Freq= 0, CH_1, rank 1
8342 16:53:51.675115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 16:53:51.678358 ==
8344 16:53:51.681474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 16:53:51.684781 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 16:53:51.691876 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 16:53:51.698358 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 16:53:51.705772 [CA 0] Center 42 (12~72) winsize 61
8349 16:53:51.709067 [CA 1] Center 41 (12~71) winsize 60
8350 16:53:51.711963 [CA 2] Center 38 (9~68) winsize 60
8351 16:53:51.715427 [CA 3] Center 38 (8~68) winsize 61
8352 16:53:51.718462 [CA 4] Center 38 (8~68) winsize 61
8353 16:53:51.722085 [CA 5] Center 37 (8~67) winsize 60
8354 16:53:51.722170
8355 16:53:51.725218 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8356 16:53:51.725297
8357 16:53:51.728478 [CATrainingPosCal] consider 2 rank data
8358 16:53:51.732379 u2DelayCellTimex100 = 290/100 ps
8359 16:53:51.735061 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8360 16:53:51.742121 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8361 16:53:51.745303 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8362 16:53:51.748502 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8363 16:53:51.752128 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8364 16:53:51.755509 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8365 16:53:51.755597
8366 16:53:51.758657 CA PerBit enable=1, Macro0, CA PI delay=37
8367 16:53:51.758731
8368 16:53:51.762016 [CBTSetCACLKResult] CA Dly = 37
8369 16:53:51.765124 CS Dly: 12 (0~45)
8370 16:53:51.768295 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 16:53:51.771866 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 16:53:51.771952
8373 16:53:51.774869 ----->DramcWriteLeveling(PI) begin...
8374 16:53:51.774951 ==
8375 16:53:51.778625 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 16:53:51.785326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 16:53:51.785430 ==
8378 16:53:51.788605 Write leveling (Byte 0): 26 => 26
8379 16:53:51.788705 Write leveling (Byte 1): 28 => 28
8380 16:53:51.791761 DramcWriteLeveling(PI) end<-----
8381 16:53:51.791834
8382 16:53:51.791896 ==
8383 16:53:51.794921 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 16:53:51.801680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 16:53:51.801759 ==
8386 16:53:51.805373 [Gating] SW mode calibration
8387 16:53:51.811406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8388 16:53:51.814721 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8389 16:53:51.821970 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 16:53:51.825121 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 16:53:51.828077 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8392 16:53:51.835130 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8393 16:53:51.838409 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 16:53:51.841657 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 16:53:51.848109 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 16:53:51.851759 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 16:53:51.854979 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 16:53:51.858186 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 16:53:51.864927 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8400 16:53:51.868156 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 1) (1 0)
8401 16:53:51.871355 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 16:53:51.878261 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 16:53:51.881313 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 16:53:51.884786 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 16:53:51.891304 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 16:53:51.894563 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 16:53:51.897885 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
8408 16:53:51.904997 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
8409 16:53:51.908076 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 16:53:51.911529 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 16:53:51.918317 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 16:53:51.921362 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 16:53:51.924564 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 16:53:51.931585 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 16:53:51.934572 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8416 16:53:51.937797 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8417 16:53:51.944797 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 16:53:51.948052 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 16:53:51.951213 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 16:53:51.957516 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 16:53:51.960845 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 16:53:51.964153 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 16:53:51.971369 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 16:53:51.974477 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 16:53:51.977758 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 16:53:51.984610 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 16:53:51.987686 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 16:53:51.991241 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 16:53:51.997727 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 16:53:52.001131 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 16:53:52.004356 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 16:53:52.007697 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8433 16:53:52.014469 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 16:53:52.017281 Total UI for P1: 0, mck2ui 16
8435 16:53:52.020857 best dqsien dly found for B0: ( 1, 9, 12)
8436 16:53:52.023907 Total UI for P1: 0, mck2ui 16
8437 16:53:52.027692 best dqsien dly found for B1: ( 1, 9, 12)
8438 16:53:52.030581 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8439 16:53:52.034420 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8440 16:53:52.034498
8441 16:53:52.037444 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8442 16:53:52.040643 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8443 16:53:52.043810 [Gating] SW calibration Done
8444 16:53:52.043921 ==
8445 16:53:52.047765 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 16:53:52.050675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 16:53:52.050755 ==
8448 16:53:52.053972 RX Vref Scan: 0
8449 16:53:52.054049
8450 16:53:52.057619 RX Vref 0 -> 0, step: 1
8451 16:53:52.057695
8452 16:53:52.057759 RX Delay 0 -> 252, step: 8
8453 16:53:52.064069 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8454 16:53:52.067250 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8455 16:53:52.070366 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8456 16:53:52.074216 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8457 16:53:52.077353 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8458 16:53:52.084053 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8459 16:53:52.087059 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8460 16:53:52.090855 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8461 16:53:52.094042 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8462 16:53:52.097067 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8463 16:53:52.101034 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8464 16:53:52.107192 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8465 16:53:52.111251 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8466 16:53:52.114183 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8467 16:53:52.117383 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8468 16:53:52.121041 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8469 16:53:52.124412 ==
8470 16:53:52.127401 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 16:53:52.131205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 16:53:52.131286 ==
8473 16:53:52.131353 DQS Delay:
8474 16:53:52.134571 DQS0 = 0, DQS1 = 0
8475 16:53:52.134646 DQM Delay:
8476 16:53:52.137474 DQM0 = 136, DQM1 = 132
8477 16:53:52.137599 DQ Delay:
8478 16:53:52.140705 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8479 16:53:52.143706 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8480 16:53:52.147509 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8481 16:53:52.150667 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8482 16:53:52.150769
8483 16:53:52.150861
8484 16:53:52.150953 ==
8485 16:53:52.154002 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 16:53:52.160327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 16:53:52.160434 ==
8488 16:53:52.160530
8489 16:53:52.160621
8490 16:53:52.163427 TX Vref Scan disable
8491 16:53:52.163533 == TX Byte 0 ==
8492 16:53:52.167329 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8493 16:53:52.173886 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8494 16:53:52.174010 == TX Byte 1 ==
8495 16:53:52.177152 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8496 16:53:52.183522 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8497 16:53:52.183626 ==
8498 16:53:52.186801 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 16:53:52.190169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 16:53:52.190270 ==
8501 16:53:52.203067
8502 16:53:52.206245 TX Vref early break, caculate TX vref
8503 16:53:52.209471 TX Vref=16, minBit 1, minWin=22, winSum=376
8504 16:53:52.212803 TX Vref=18, minBit 1, minWin=23, winSum=385
8505 16:53:52.216089 TX Vref=20, minBit 0, minWin=24, winSum=399
8506 16:53:52.219270 TX Vref=22, minBit 0, minWin=24, winSum=405
8507 16:53:52.222880 TX Vref=24, minBit 0, minWin=25, winSum=417
8508 16:53:52.229416 TX Vref=26, minBit 0, minWin=25, winSum=423
8509 16:53:52.233074 TX Vref=28, minBit 1, minWin=25, winSum=426
8510 16:53:52.236260 TX Vref=30, minBit 0, minWin=25, winSum=420
8511 16:53:52.239437 TX Vref=32, minBit 0, minWin=24, winSum=409
8512 16:53:52.242998 TX Vref=34, minBit 0, minWin=24, winSum=401
8513 16:53:52.249475 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
8514 16:53:52.249601
8515 16:53:52.253116 Final TX Range 0 Vref 28
8516 16:53:52.253201
8517 16:53:52.253266 ==
8518 16:53:52.256392 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 16:53:52.259494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 16:53:52.259578 ==
8521 16:53:52.259645
8522 16:53:52.259707
8523 16:53:52.262702 TX Vref Scan disable
8524 16:53:52.268971 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8525 16:53:52.269057 == TX Byte 0 ==
8526 16:53:52.272337 u2DelayCellOfst[0]=16 cells (5 PI)
8527 16:53:52.275481 u2DelayCellOfst[1]=10 cells (3 PI)
8528 16:53:52.278892 u2DelayCellOfst[2]=0 cells (0 PI)
8529 16:53:52.282228 u2DelayCellOfst[3]=6 cells (2 PI)
8530 16:53:52.285489 u2DelayCellOfst[4]=6 cells (2 PI)
8531 16:53:52.289369 u2DelayCellOfst[5]=16 cells (5 PI)
8532 16:53:52.292189 u2DelayCellOfst[6]=16 cells (5 PI)
8533 16:53:52.292272 u2DelayCellOfst[7]=6 cells (2 PI)
8534 16:53:52.298664 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8535 16:53:52.302000 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8536 16:53:52.305658 == TX Byte 1 ==
8537 16:53:52.305741 u2DelayCellOfst[8]=0 cells (0 PI)
8538 16:53:52.308785 u2DelayCellOfst[9]=3 cells (1 PI)
8539 16:53:52.312403 u2DelayCellOfst[10]=13 cells (4 PI)
8540 16:53:52.315446 u2DelayCellOfst[11]=6 cells (2 PI)
8541 16:53:52.318753 u2DelayCellOfst[12]=16 cells (5 PI)
8542 16:53:52.322087 u2DelayCellOfst[13]=16 cells (5 PI)
8543 16:53:52.325409 u2DelayCellOfst[14]=16 cells (5 PI)
8544 16:53:52.328557 u2DelayCellOfst[15]=16 cells (5 PI)
8545 16:53:52.332292 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8546 16:53:52.338998 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8547 16:53:52.339081 DramC Write-DBI on
8548 16:53:52.339148 ==
8549 16:53:52.342370 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 16:53:52.345343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 16:53:52.348924 ==
8552 16:53:52.349033
8553 16:53:52.349127
8554 16:53:52.349216 TX Vref Scan disable
8555 16:53:52.352013 == TX Byte 0 ==
8556 16:53:52.355283 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8557 16:53:52.358931 == TX Byte 1 ==
8558 16:53:52.361921 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8559 16:53:52.365223 DramC Write-DBI off
8560 16:53:52.365307
8561 16:53:52.365373 [DATLAT]
8562 16:53:52.365436 Freq=1600, CH1 RK0
8563 16:53:52.365496
8564 16:53:52.369083 DATLAT Default: 0xf
8565 16:53:52.369169 0, 0xFFFF, sum = 0
8566 16:53:52.372209 1, 0xFFFF, sum = 0
8567 16:53:52.372293 2, 0xFFFF, sum = 0
8568 16:53:52.375556 3, 0xFFFF, sum = 0
8569 16:53:52.378839 4, 0xFFFF, sum = 0
8570 16:53:52.378925 5, 0xFFFF, sum = 0
8571 16:53:52.382232 6, 0xFFFF, sum = 0
8572 16:53:52.382318 7, 0xFFFF, sum = 0
8573 16:53:52.385433 8, 0xFFFF, sum = 0
8574 16:53:52.385577 9, 0xFFFF, sum = 0
8575 16:53:52.388663 10, 0xFFFF, sum = 0
8576 16:53:52.388747 11, 0xFFFF, sum = 0
8577 16:53:52.391949 12, 0xFFFF, sum = 0
8578 16:53:52.392036 13, 0xFFFF, sum = 0
8579 16:53:52.395223 14, 0x0, sum = 1
8580 16:53:52.395308 15, 0x0, sum = 2
8581 16:53:52.398421 16, 0x0, sum = 3
8582 16:53:52.398506 17, 0x0, sum = 4
8583 16:53:52.401771 best_step = 15
8584 16:53:52.401883
8585 16:53:52.401992 ==
8586 16:53:52.405704 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 16:53:52.408638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 16:53:52.408722 ==
8589 16:53:52.408789 RX Vref Scan: 1
8590 16:53:52.411916
8591 16:53:52.412000 Set Vref Range= 24 -> 127
8592 16:53:52.412066
8593 16:53:52.415324 RX Vref 24 -> 127, step: 1
8594 16:53:52.415407
8595 16:53:52.418620 RX Delay 27 -> 252, step: 4
8596 16:53:52.418703
8597 16:53:52.421865 Set Vref, RX VrefLevel [Byte0]: 24
8598 16:53:52.425184 [Byte1]: 24
8599 16:53:52.425268
8600 16:53:52.428448 Set Vref, RX VrefLevel [Byte0]: 25
8601 16:53:52.432280 [Byte1]: 25
8602 16:53:52.432363
8603 16:53:52.435346 Set Vref, RX VrefLevel [Byte0]: 26
8604 16:53:52.438549 [Byte1]: 26
8605 16:53:52.441957
8606 16:53:52.442046 Set Vref, RX VrefLevel [Byte0]: 27
8607 16:53:52.445683 [Byte1]: 27
8608 16:53:52.449974
8609 16:53:52.450057 Set Vref, RX VrefLevel [Byte0]: 28
8610 16:53:52.453110 [Byte1]: 28
8611 16:53:52.457455
8612 16:53:52.457562 Set Vref, RX VrefLevel [Byte0]: 29
8613 16:53:52.460812 [Byte1]: 29
8614 16:53:52.465106
8615 16:53:52.465190 Set Vref, RX VrefLevel [Byte0]: 30
8616 16:53:52.468392 [Byte1]: 30
8617 16:53:52.472401
8618 16:53:52.472484 Set Vref, RX VrefLevel [Byte0]: 31
8619 16:53:52.475525 [Byte1]: 31
8620 16:53:52.479813
8621 16:53:52.479893 Set Vref, RX VrefLevel [Byte0]: 32
8622 16:53:52.483127 [Byte1]: 32
8623 16:53:52.487646
8624 16:53:52.487719 Set Vref, RX VrefLevel [Byte0]: 33
8625 16:53:52.490729 [Byte1]: 33
8626 16:53:52.494875
8627 16:53:52.494951 Set Vref, RX VrefLevel [Byte0]: 34
8628 16:53:52.498140 [Byte1]: 34
8629 16:53:52.502674
8630 16:53:52.502751 Set Vref, RX VrefLevel [Byte0]: 35
8631 16:53:52.505996 [Byte1]: 35
8632 16:53:52.510090
8633 16:53:52.510166 Set Vref, RX VrefLevel [Byte0]: 36
8634 16:53:52.513286 [Byte1]: 36
8635 16:53:52.517634
8636 16:53:52.517709 Set Vref, RX VrefLevel [Byte0]: 37
8637 16:53:52.521114 [Byte1]: 37
8638 16:53:52.524908
8639 16:53:52.524988 Set Vref, RX VrefLevel [Byte0]: 38
8640 16:53:52.528183 [Byte1]: 38
8641 16:53:52.532696
8642 16:53:52.532779 Set Vref, RX VrefLevel [Byte0]: 39
8643 16:53:52.536031 [Byte1]: 39
8644 16:53:52.540469
8645 16:53:52.540552 Set Vref, RX VrefLevel [Byte0]: 40
8646 16:53:52.543453 [Byte1]: 40
8647 16:53:52.547791
8648 16:53:52.547871 Set Vref, RX VrefLevel [Byte0]: 41
8649 16:53:52.551378 [Byte1]: 41
8650 16:53:52.555252
8651 16:53:52.555334 Set Vref, RX VrefLevel [Byte0]: 42
8652 16:53:52.558816 [Byte1]: 42
8653 16:53:52.562973
8654 16:53:52.563102 Set Vref, RX VrefLevel [Byte0]: 43
8655 16:53:52.566199 [Byte1]: 43
8656 16:53:52.570331
8657 16:53:52.570413 Set Vref, RX VrefLevel [Byte0]: 44
8658 16:53:52.573480 [Byte1]: 44
8659 16:53:52.578101
8660 16:53:52.578175 Set Vref, RX VrefLevel [Byte0]: 45
8661 16:53:52.581155 [Byte1]: 45
8662 16:53:52.585681
8663 16:53:52.585762 Set Vref, RX VrefLevel [Byte0]: 46
8664 16:53:52.588725 [Byte1]: 46
8665 16:53:52.592862
8666 16:53:52.592943 Set Vref, RX VrefLevel [Byte0]: 47
8667 16:53:52.596030 [Byte1]: 47
8668 16:53:52.600693
8669 16:53:52.600771 Set Vref, RX VrefLevel [Byte0]: 48
8670 16:53:52.603974 [Byte1]: 48
8671 16:53:52.607799
8672 16:53:52.607879 Set Vref, RX VrefLevel [Byte0]: 49
8673 16:53:52.611196 [Byte1]: 49
8674 16:53:52.615227
8675 16:53:52.615303 Set Vref, RX VrefLevel [Byte0]: 50
8676 16:53:52.619001 [Byte1]: 50
8677 16:53:52.622854
8678 16:53:52.622941 Set Vref, RX VrefLevel [Byte0]: 51
8679 16:53:52.626534 [Byte1]: 51
8680 16:53:52.630851
8681 16:53:52.630935 Set Vref, RX VrefLevel [Byte0]: 52
8682 16:53:52.634174 [Byte1]: 52
8683 16:53:52.638074
8684 16:53:52.638159 Set Vref, RX VrefLevel [Byte0]: 53
8685 16:53:52.641270 [Byte1]: 53
8686 16:53:52.645851
8687 16:53:52.645935 Set Vref, RX VrefLevel [Byte0]: 54
8688 16:53:52.648832 [Byte1]: 54
8689 16:53:52.653120
8690 16:53:52.653205 Set Vref, RX VrefLevel [Byte0]: 55
8691 16:53:52.656813 [Byte1]: 55
8692 16:53:52.661139
8693 16:53:52.661223 Set Vref, RX VrefLevel [Byte0]: 56
8694 16:53:52.663995 [Byte1]: 56
8695 16:53:52.668447
8696 16:53:52.668532 Set Vref, RX VrefLevel [Byte0]: 57
8697 16:53:52.671481 [Byte1]: 57
8698 16:53:52.675918
8699 16:53:52.676002 Set Vref, RX VrefLevel [Byte0]: 58
8700 16:53:52.679261 [Byte1]: 58
8701 16:53:52.683173
8702 16:53:52.683258 Set Vref, RX VrefLevel [Byte0]: 59
8703 16:53:52.686348 [Byte1]: 59
8704 16:53:52.690605
8705 16:53:52.690694 Set Vref, RX VrefLevel [Byte0]: 60
8706 16:53:52.693766 [Byte1]: 60
8707 16:53:52.698166
8708 16:53:52.698249 Set Vref, RX VrefLevel [Byte0]: 61
8709 16:53:52.701416 [Byte1]: 61
8710 16:53:52.706060
8711 16:53:52.706145 Set Vref, RX VrefLevel [Byte0]: 62
8712 16:53:52.709220 [Byte1]: 62
8713 16:53:52.713147
8714 16:53:52.713231 Set Vref, RX VrefLevel [Byte0]: 63
8715 16:53:52.717104 [Byte1]: 63
8716 16:53:52.721108
8717 16:53:52.721192 Set Vref, RX VrefLevel [Byte0]: 64
8718 16:53:52.724205 [Byte1]: 64
8719 16:53:52.728419
8720 16:53:52.728525 Set Vref, RX VrefLevel [Byte0]: 65
8721 16:53:52.731647 [Byte1]: 65
8722 16:53:52.736179
8723 16:53:52.736263 Set Vref, RX VrefLevel [Byte0]: 66
8724 16:53:52.739464 [Byte1]: 66
8725 16:53:52.743519
8726 16:53:52.743628 Set Vref, RX VrefLevel [Byte0]: 67
8727 16:53:52.746906 [Byte1]: 67
8728 16:53:52.751379
8729 16:53:52.751487 Set Vref, RX VrefLevel [Byte0]: 68
8730 16:53:52.754412 [Byte1]: 68
8731 16:53:52.758718
8732 16:53:52.758802 Set Vref, RX VrefLevel [Byte0]: 69
8733 16:53:52.761734 [Byte1]: 69
8734 16:53:52.766425
8735 16:53:52.766511 Set Vref, RX VrefLevel [Byte0]: 70
8736 16:53:52.769739 [Byte1]: 70
8737 16:53:52.773474
8738 16:53:52.773596 Set Vref, RX VrefLevel [Byte0]: 71
8739 16:53:52.777074 [Byte1]: 71
8740 16:53:52.781216
8741 16:53:52.781300 Set Vref, RX VrefLevel [Byte0]: 72
8742 16:53:52.784304 [Byte1]: 72
8743 16:53:52.789060
8744 16:53:52.789144 Set Vref, RX VrefLevel [Byte0]: 73
8745 16:53:52.791924 [Byte1]: 73
8746 16:53:52.796114
8747 16:53:52.796207 Set Vref, RX VrefLevel [Byte0]: 74
8748 16:53:52.799754 [Byte1]: 74
8749 16:53:52.804201
8750 16:53:52.804285 Set Vref, RX VrefLevel [Byte0]: 75
8751 16:53:52.807326 [Byte1]: 75
8752 16:53:52.811412
8753 16:53:52.811496 Set Vref, RX VrefLevel [Byte0]: 76
8754 16:53:52.814668 [Byte1]: 76
8755 16:53:52.818714
8756 16:53:52.818798 Final RX Vref Byte 0 = 59 to rank0
8757 16:53:52.822107 Final RX Vref Byte 1 = 55 to rank0
8758 16:53:52.825949 Final RX Vref Byte 0 = 59 to rank1
8759 16:53:52.829238 Final RX Vref Byte 1 = 55 to rank1==
8760 16:53:52.832361 Dram Type= 6, Freq= 0, CH_1, rank 0
8761 16:53:52.836006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 16:53:52.838989 ==
8763 16:53:52.839074 DQS Delay:
8764 16:53:52.839146 DQS0 = 0, DQS1 = 0
8765 16:53:52.842220 DQM Delay:
8766 16:53:52.842304 DQM0 = 134, DQM1 = 131
8767 16:53:52.845642 DQ Delay:
8768 16:53:52.848787 DQ0 =140, DQ1 =130, DQ2 =124, DQ3 =130
8769 16:53:52.852086 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8770 16:53:52.855558 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8771 16:53:52.858660 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8772 16:53:52.858745
8773 16:53:52.858811
8774 16:53:52.858873
8775 16:53:52.861744 [DramC_TX_OE_Calibration] TA2
8776 16:53:52.865470 Original DQ_B0 (3 6) =30, OEN = 27
8777 16:53:52.868477 Original DQ_B1 (3 6) =30, OEN = 27
8778 16:53:52.871710 24, 0x0, End_B0=24 End_B1=24
8779 16:53:52.871796 25, 0x0, End_B0=25 End_B1=25
8780 16:53:52.875156 26, 0x0, End_B0=26 End_B1=26
8781 16:53:52.878346 27, 0x0, End_B0=27 End_B1=27
8782 16:53:52.881851 28, 0x0, End_B0=28 End_B1=28
8783 16:53:52.885658 29, 0x0, End_B0=29 End_B1=29
8784 16:53:52.885744 30, 0x0, End_B0=30 End_B1=30
8785 16:53:52.888753 31, 0x4141, End_B0=30 End_B1=30
8786 16:53:52.891911 Byte0 end_step=30 best_step=27
8787 16:53:52.895234 Byte1 end_step=30 best_step=27
8788 16:53:52.898379 Byte0 TX OE(2T, 0.5T) = (3, 3)
8789 16:53:52.901929 Byte1 TX OE(2T, 0.5T) = (3, 3)
8790 16:53:52.902013
8791 16:53:52.902080
8792 16:53:52.908401 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8793 16:53:52.911648 CH1 RK0: MR19=303, MR18=1523
8794 16:53:52.918189 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8795 16:53:52.918274
8796 16:53:52.922096 ----->DramcWriteLeveling(PI) begin...
8797 16:53:52.922182 ==
8798 16:53:52.925423 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 16:53:52.928630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 16:53:52.928725 ==
8801 16:53:52.931763 Write leveling (Byte 0): 27 => 27
8802 16:53:52.935011 Write leveling (Byte 1): 30 => 30
8803 16:53:52.938822 DramcWriteLeveling(PI) end<-----
8804 16:53:52.938946
8805 16:53:52.939047 ==
8806 16:53:52.941967 Dram Type= 6, Freq= 0, CH_1, rank 1
8807 16:53:52.945000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 16:53:52.945110 ==
8809 16:53:52.948854 [Gating] SW mode calibration
8810 16:53:52.955415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8811 16:53:52.961838 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8812 16:53:52.965030 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 16:53:52.968887 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 16:53:52.975588 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8815 16:53:52.978690 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8816 16:53:52.981730 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 16:53:52.988507 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 16:53:52.991687 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 16:53:52.994838 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 16:53:53.001812 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 16:53:53.005030 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 16:53:53.008367 1 5 8 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 0)
8823 16:53:53.015038 1 5 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8824 16:53:53.018907 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 16:53:53.021436 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 16:53:53.028874 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 16:53:53.031462 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 16:53:53.035470 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 16:53:53.041437 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 16:53:53.044725 1 6 8 | B1->B0 | 2a29 2323 | 1 0 | (0 0) (0 0)
8831 16:53:53.048503 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 16:53:53.054777 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 16:53:53.058158 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 16:53:53.061412 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 16:53:53.064577 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 16:53:53.071602 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 16:53:53.074706 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8838 16:53:53.078373 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8839 16:53:53.084605 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8840 16:53:53.088182 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8841 16:53:53.091261 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 16:53:53.098089 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 16:53:53.101237 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 16:53:53.104455 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 16:53:53.111512 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 16:53:53.114835 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 16:53:53.118086 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 16:53:53.124659 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 16:53:53.127756 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 16:53:53.131025 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 16:53:53.137642 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 16:53:53.141457 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 16:53:53.144233 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 16:53:53.151221 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8855 16:53:53.154347 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8856 16:53:53.157367 Total UI for P1: 0, mck2ui 16
8857 16:53:53.160938 best dqsien dly found for B1: ( 1, 9, 8)
8858 16:53:53.164310 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 16:53:53.167602 Total UI for P1: 0, mck2ui 16
8860 16:53:53.170920 best dqsien dly found for B0: ( 1, 9, 10)
8861 16:53:53.174169 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8862 16:53:53.177987 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8863 16:53:53.178087
8864 16:53:53.184456 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8865 16:53:53.187300 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8866 16:53:53.187391 [Gating] SW calibration Done
8867 16:53:53.191087 ==
8868 16:53:53.194444 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 16:53:53.197599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 16:53:53.197701 ==
8871 16:53:53.197832 RX Vref Scan: 0
8872 16:53:53.197909
8873 16:53:53.201076 RX Vref 0 -> 0, step: 1
8874 16:53:53.201161
8875 16:53:53.204115 RX Delay 0 -> 252, step: 8
8876 16:53:53.207810 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8877 16:53:53.210926 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8878 16:53:53.214074 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8879 16:53:53.220446 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8880 16:53:53.223660 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8881 16:53:53.227503 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8882 16:53:53.230711 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8883 16:53:53.234116 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8884 16:53:53.240680 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8885 16:53:53.244086 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8886 16:53:53.247363 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8887 16:53:53.250240 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8888 16:53:53.254261 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8889 16:53:53.260497 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8890 16:53:53.263699 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8891 16:53:53.267240 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8892 16:53:53.267349 ==
8893 16:53:53.270374 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 16:53:53.273780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 16:53:53.277110 ==
8896 16:53:53.277212 DQS Delay:
8897 16:53:53.277307 DQS0 = 0, DQS1 = 0
8898 16:53:53.280306 DQM Delay:
8899 16:53:53.280406 DQM0 = 136, DQM1 = 133
8900 16:53:53.283636 DQ Delay:
8901 16:53:53.287242 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8902 16:53:53.290217 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8903 16:53:53.293789 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8904 16:53:53.296866 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8905 16:53:53.296951
8906 16:53:53.297018
8907 16:53:53.297081 ==
8908 16:53:53.300422 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 16:53:53.304020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 16:53:53.304105 ==
8911 16:53:53.304173
8912 16:53:53.304234
8913 16:53:53.307180 TX Vref Scan disable
8914 16:53:53.310125 == TX Byte 0 ==
8915 16:53:53.313745 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8916 16:53:53.317299 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8917 16:53:53.320494 == TX Byte 1 ==
8918 16:53:53.323587 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8919 16:53:53.326845 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8920 16:53:53.326931 ==
8921 16:53:53.330194 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 16:53:53.337099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 16:53:53.337184 ==
8924 16:53:53.348248
8925 16:53:53.351666 TX Vref early break, caculate TX vref
8926 16:53:53.354818 TX Vref=16, minBit 0, minWin=22, winSum=381
8927 16:53:53.358135 TX Vref=18, minBit 0, minWin=24, winSum=393
8928 16:53:53.361346 TX Vref=20, minBit 0, minWin=24, winSum=399
8929 16:53:53.365169 TX Vref=22, minBit 2, minWin=24, winSum=407
8930 16:53:53.368249 TX Vref=24, minBit 2, minWin=24, winSum=417
8931 16:53:53.375069 TX Vref=26, minBit 0, minWin=26, winSum=422
8932 16:53:53.378316 TX Vref=28, minBit 0, minWin=26, winSum=429
8933 16:53:53.381500 TX Vref=30, minBit 1, minWin=25, winSum=417
8934 16:53:53.384751 TX Vref=32, minBit 6, minWin=24, winSum=410
8935 16:53:53.388045 TX Vref=34, minBit 0, minWin=24, winSum=402
8936 16:53:53.395155 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8937 16:53:53.395242
8938 16:53:53.398130 Final TX Range 0 Vref 28
8939 16:53:53.398217
8940 16:53:53.398303 ==
8941 16:53:53.401234 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 16:53:53.405044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 16:53:53.405130 ==
8944 16:53:53.405216
8945 16:53:53.405297
8946 16:53:53.408102 TX Vref Scan disable
8947 16:53:53.414967 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8948 16:53:53.415052 == TX Byte 0 ==
8949 16:53:53.417895 u2DelayCellOfst[0]=16 cells (5 PI)
8950 16:53:53.421492 u2DelayCellOfst[1]=10 cells (3 PI)
8951 16:53:53.424612 u2DelayCellOfst[2]=0 cells (0 PI)
8952 16:53:53.428238 u2DelayCellOfst[3]=6 cells (2 PI)
8953 16:53:53.431213 u2DelayCellOfst[4]=6 cells (2 PI)
8954 16:53:53.435106 u2DelayCellOfst[5]=16 cells (5 PI)
8955 16:53:53.435190 u2DelayCellOfst[6]=16 cells (5 PI)
8956 16:53:53.437834 u2DelayCellOfst[7]=6 cells (2 PI)
8957 16:53:53.444827 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8958 16:53:53.447933 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8959 16:53:53.448018 == TX Byte 1 ==
8960 16:53:53.451743 u2DelayCellOfst[8]=0 cells (0 PI)
8961 16:53:53.455014 u2DelayCellOfst[9]=3 cells (1 PI)
8962 16:53:53.458202 u2DelayCellOfst[10]=10 cells (3 PI)
8963 16:53:53.461402 u2DelayCellOfst[11]=3 cells (1 PI)
8964 16:53:53.464874 u2DelayCellOfst[12]=13 cells (4 PI)
8965 16:53:53.468163 u2DelayCellOfst[13]=16 cells (5 PI)
8966 16:53:53.471376 u2DelayCellOfst[14]=16 cells (5 PI)
8967 16:53:53.474593 u2DelayCellOfst[15]=16 cells (5 PI)
8968 16:53:53.477681 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8969 16:53:53.484599 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8970 16:53:53.484683 DramC Write-DBI on
8971 16:53:53.484750 ==
8972 16:53:53.487924 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 16:53:53.491349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 16:53:53.491434 ==
8975 16:53:53.491501
8976 16:53:53.494575
8977 16:53:53.494658 TX Vref Scan disable
8978 16:53:53.497680 == TX Byte 0 ==
8979 16:53:53.501425 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8980 16:53:53.504527 == TX Byte 1 ==
8981 16:53:53.507502 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8982 16:53:53.507588 DramC Write-DBI off
8983 16:53:53.507656
8984 16:53:53.511211 [DATLAT]
8985 16:53:53.511295 Freq=1600, CH1 RK1
8986 16:53:53.511362
8987 16:53:53.514305 DATLAT Default: 0xf
8988 16:53:53.514389 0, 0xFFFF, sum = 0
8989 16:53:53.518023 1, 0xFFFF, sum = 0
8990 16:53:53.518109 2, 0xFFFF, sum = 0
8991 16:53:53.521060 3, 0xFFFF, sum = 0
8992 16:53:53.521146 4, 0xFFFF, sum = 0
8993 16:53:53.524100 5, 0xFFFF, sum = 0
8994 16:53:53.527801 6, 0xFFFF, sum = 0
8995 16:53:53.527887 7, 0xFFFF, sum = 0
8996 16:53:53.530983 8, 0xFFFF, sum = 0
8997 16:53:53.531069 9, 0xFFFF, sum = 0
8998 16:53:53.534079 10, 0xFFFF, sum = 0
8999 16:53:53.534165 11, 0xFFFF, sum = 0
9000 16:53:53.537803 12, 0xFFFF, sum = 0
9001 16:53:53.537888 13, 0xFFFF, sum = 0
9002 16:53:53.541017 14, 0x0, sum = 1
9003 16:53:53.541103 15, 0x0, sum = 2
9004 16:53:53.544173 16, 0x0, sum = 3
9005 16:53:53.544251 17, 0x0, sum = 4
9006 16:53:53.547372 best_step = 15
9007 16:53:53.547449
9008 16:53:53.547513 ==
9009 16:53:53.551241 Dram Type= 6, Freq= 0, CH_1, rank 1
9010 16:53:53.554482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9011 16:53:53.554567 ==
9012 16:53:53.554636 RX Vref Scan: 0
9013 16:53:53.554736
9014 16:53:53.557723 RX Vref 0 -> 0, step: 1
9015 16:53:53.557798
9016 16:53:53.561151 RX Delay 19 -> 252, step: 4
9017 16:53:53.564484 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9018 16:53:53.567692 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
9019 16:53:53.574248 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9020 16:53:53.578031 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9021 16:53:53.581242 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9022 16:53:53.584247 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9023 16:53:53.587884 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9024 16:53:53.591171 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9025 16:53:53.597765 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9026 16:53:53.600963 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9027 16:53:53.604181 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9028 16:53:53.607848 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9029 16:53:53.614188 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
9030 16:53:53.617968 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9031 16:53:53.620908 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9032 16:53:53.624659 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9033 16:53:53.624738 ==
9034 16:53:53.627831 Dram Type= 6, Freq= 0, CH_1, rank 1
9035 16:53:53.634237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9036 16:53:53.634352 ==
9037 16:53:53.634455 DQS Delay:
9038 16:53:53.634552 DQS0 = 0, DQS1 = 0
9039 16:53:53.637368 DQM Delay:
9040 16:53:53.637448 DQM0 = 134, DQM1 = 130
9041 16:53:53.641020 DQ Delay:
9042 16:53:53.644360 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
9043 16:53:53.647568 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9044 16:53:53.650650 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9045 16:53:53.653921 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
9046 16:53:53.653998
9047 16:53:53.654062
9048 16:53:53.654122
9049 16:53:53.657299 [DramC_TX_OE_Calibration] TA2
9050 16:53:53.660436 Original DQ_B0 (3 6) =30, OEN = 27
9051 16:53:53.664320 Original DQ_B1 (3 6) =30, OEN = 27
9052 16:53:53.667648 24, 0x0, End_B0=24 End_B1=24
9053 16:53:53.667734 25, 0x0, End_B0=25 End_B1=25
9054 16:53:53.670905 26, 0x0, End_B0=26 End_B1=26
9055 16:53:53.674136 27, 0x0, End_B0=27 End_B1=27
9056 16:53:53.677289 28, 0x0, End_B0=28 End_B1=28
9057 16:53:53.677366 29, 0x0, End_B0=29 End_B1=29
9058 16:53:53.680710 30, 0x0, End_B0=30 End_B1=30
9059 16:53:53.683908 31, 0x4545, End_B0=30 End_B1=30
9060 16:53:53.687067 Byte0 end_step=30 best_step=27
9061 16:53:53.690558 Byte1 end_step=30 best_step=27
9062 16:53:53.693717 Byte0 TX OE(2T, 0.5T) = (3, 3)
9063 16:53:53.693819 Byte1 TX OE(2T, 0.5T) = (3, 3)
9064 16:53:53.697499
9065 16:53:53.697605
9066 16:53:53.704099 [DQSOSCAuto] RK1, (LSB)MR18= 0x2005, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
9067 16:53:53.707222 CH1 RK1: MR19=303, MR18=2005
9068 16:53:53.713632 CH1_RK1: MR19=0x303, MR18=0x2005, DQSOSC=393, MR23=63, INC=23, DEC=15
9069 16:53:53.717460 [RxdqsGatingPostProcess] freq 1600
9070 16:53:53.720430 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9071 16:53:53.723738 best DQS0 dly(2T, 0.5T) = (1, 1)
9072 16:53:53.727162 best DQS1 dly(2T, 0.5T) = (1, 1)
9073 16:53:53.730754 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9074 16:53:53.733900 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9075 16:53:53.736871 best DQS0 dly(2T, 0.5T) = (1, 1)
9076 16:53:53.740637 best DQS1 dly(2T, 0.5T) = (1, 1)
9077 16:53:53.743617 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9078 16:53:53.747178 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9079 16:53:53.750471 Pre-setting of DQS Precalculation
9080 16:53:53.753673 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9081 16:53:53.760290 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9082 16:53:53.766816 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9083 16:53:53.766900
9084 16:53:53.770711
9085 16:53:53.770795 [Calibration Summary] 3200 Mbps
9086 16:53:53.773999 CH 0, Rank 0
9087 16:53:53.774076 SW Impedance : PASS
9088 16:53:53.777265 DUTY Scan : NO K
9089 16:53:53.779862 ZQ Calibration : PASS
9090 16:53:53.779941 Jitter Meter : NO K
9091 16:53:53.783188 CBT Training : PASS
9092 16:53:53.787049 Write leveling : PASS
9093 16:53:53.787129 RX DQS gating : PASS
9094 16:53:53.790333 RX DQ/DQS(RDDQC) : PASS
9095 16:53:53.793314 TX DQ/DQS : PASS
9096 16:53:53.793394 RX DATLAT : PASS
9097 16:53:53.797010 RX DQ/DQS(Engine): PASS
9098 16:53:53.800189 TX OE : PASS
9099 16:53:53.800265 All Pass.
9100 16:53:53.800330
9101 16:53:53.800395 CH 0, Rank 1
9102 16:53:53.803260 SW Impedance : PASS
9103 16:53:53.806458 DUTY Scan : NO K
9104 16:53:53.806539 ZQ Calibration : PASS
9105 16:53:53.809754 Jitter Meter : NO K
9106 16:53:53.813464 CBT Training : PASS
9107 16:53:53.813600 Write leveling : PASS
9108 16:53:53.816779 RX DQS gating : PASS
9109 16:53:53.816858 RX DQ/DQS(RDDQC) : PASS
9110 16:53:53.820008 TX DQ/DQS : PASS
9111 16:53:53.822996 RX DATLAT : PASS
9112 16:53:53.823070 RX DQ/DQS(Engine): PASS
9113 16:53:53.826742 TX OE : PASS
9114 16:53:53.826824 All Pass.
9115 16:53:53.826927
9116 16:53:53.829869 CH 1, Rank 0
9117 16:53:53.829947 SW Impedance : PASS
9118 16:53:53.833435 DUTY Scan : NO K
9119 16:53:53.836397 ZQ Calibration : PASS
9120 16:53:53.836479 Jitter Meter : NO K
9121 16:53:53.840246 CBT Training : PASS
9122 16:53:53.843357 Write leveling : PASS
9123 16:53:53.843435 RX DQS gating : PASS
9124 16:53:53.846313 RX DQ/DQS(RDDQC) : PASS
9125 16:53:53.850226 TX DQ/DQS : PASS
9126 16:53:53.850308 RX DATLAT : PASS
9127 16:53:53.853160 RX DQ/DQS(Engine): PASS
9128 16:53:53.856212 TX OE : PASS
9129 16:53:53.856291 All Pass.
9130 16:53:53.856361
9131 16:53:53.856424 CH 1, Rank 1
9132 16:53:53.859966 SW Impedance : PASS
9133 16:53:53.863369 DUTY Scan : NO K
9134 16:53:53.863449 ZQ Calibration : PASS
9135 16:53:53.866630 Jitter Meter : NO K
9136 16:53:53.869676 CBT Training : PASS
9137 16:53:53.869757 Write leveling : PASS
9138 16:53:53.872799 RX DQS gating : PASS
9139 16:53:53.872880 RX DQ/DQS(RDDQC) : PASS
9140 16:53:53.876055 TX DQ/DQS : PASS
9141 16:53:53.879981 RX DATLAT : PASS
9142 16:53:53.880060 RX DQ/DQS(Engine): PASS
9143 16:53:53.882654 TX OE : PASS
9144 16:53:53.882734 All Pass.
9145 16:53:53.882800
9146 16:53:53.886573 DramC Write-DBI on
9147 16:53:53.889759 PER_BANK_REFRESH: Hybrid Mode
9148 16:53:53.889844 TX_TRACKING: ON
9149 16:53:53.899415 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9150 16:53:53.905978 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9151 16:53:53.913108 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9152 16:53:53.919470 [FAST_K] Save calibration result to emmc
9153 16:53:53.919555 sync common calibartion params.
9154 16:53:53.922843 sync cbt_mode0:1, 1:1
9155 16:53:53.926230 dram_init: ddr_geometry: 2
9156 16:53:53.926315 dram_init: ddr_geometry: 2
9157 16:53:53.929488 dram_init: ddr_geometry: 2
9158 16:53:53.932582 0:dram_rank_size:100000000
9159 16:53:53.936356 1:dram_rank_size:100000000
9160 16:53:53.939477 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9161 16:53:53.942505 DFS_SHUFFLE_HW_MODE: ON
9162 16:53:53.946133 dramc_set_vcore_voltage set vcore to 725000
9163 16:53:53.949239 Read voltage for 1600, 0
9164 16:53:53.949323 Vio18 = 0
9165 16:53:53.952882 Vcore = 725000
9166 16:53:53.952966 Vdram = 0
9167 16:53:53.953033 Vddq = 0
9168 16:53:53.953094 Vmddr = 0
9169 16:53:53.955945 switch to 3200 Mbps bootup
9170 16:53:53.959621 [DramcRunTimeConfig]
9171 16:53:53.959770 PHYPLL
9172 16:53:53.959869 DPM_CONTROL_AFTERK: ON
9173 16:53:53.962453 PER_BANK_REFRESH: ON
9174 16:53:53.966045 REFRESH_OVERHEAD_REDUCTION: ON
9175 16:53:53.966130 CMD_PICG_NEW_MODE: OFF
9176 16:53:53.969478 XRTWTW_NEW_MODE: ON
9177 16:53:53.972762 XRTRTR_NEW_MODE: ON
9178 16:53:53.972846 TX_TRACKING: ON
9179 16:53:53.976132 RDSEL_TRACKING: OFF
9180 16:53:53.976216 DQS Precalculation for DVFS: ON
9181 16:53:53.979753 RX_TRACKING: OFF
9182 16:53:53.979867 HW_GATING DBG: ON
9183 16:53:53.982991 ZQCS_ENABLE_LP4: ON
9184 16:53:53.983076 RX_PICG_NEW_MODE: ON
9185 16:53:53.986254 TX_PICG_NEW_MODE: ON
9186 16:53:53.989375 ENABLE_RX_DCM_DPHY: ON
9187 16:53:53.992696 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9188 16:53:53.992780 DUMMY_READ_FOR_TRACKING: OFF
9189 16:53:53.995984 !!! SPM_CONTROL_AFTERK: OFF
9190 16:53:53.999353 !!! SPM could not control APHY
9191 16:53:54.002543 IMPEDANCE_TRACKING: ON
9192 16:53:54.002627 TEMP_SENSOR: ON
9193 16:53:54.006306 HW_SAVE_FOR_SR: OFF
9194 16:53:54.006390 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9195 16:53:54.012430 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9196 16:53:54.012515 Read ODT Tracking: ON
9197 16:53:54.016099 Refresh Rate DeBounce: ON
9198 16:53:54.019382 DFS_NO_QUEUE_FLUSH: ON
9199 16:53:54.019492 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9200 16:53:54.022447 ENABLE_DFS_RUNTIME_MRW: OFF
9201 16:53:54.025648 DDR_RESERVE_NEW_MODE: ON
9202 16:53:54.028899 MR_CBT_SWITCH_FREQ: ON
9203 16:53:54.028982 =========================
9204 16:53:54.049086 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9205 16:53:54.052082 dram_init: ddr_geometry: 2
9206 16:53:54.070173 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9207 16:53:54.073356 dram_init: dram init end (result: 0)
9208 16:53:54.080525 DRAM-K: Full calibration passed in 24462 msecs
9209 16:53:54.083769 MRC: failed to locate region type 0.
9210 16:53:54.083853 DRAM rank0 size:0x100000000,
9211 16:53:54.086748 DRAM rank1 size=0x100000000
9212 16:53:54.097232 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9213 16:53:54.103749 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9214 16:53:54.109900 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9215 16:53:54.116813 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9216 16:53:54.119952 DRAM rank0 size:0x100000000,
9217 16:53:54.123028 DRAM rank1 size=0x100000000
9218 16:53:54.123106 CBMEM:
9219 16:53:54.126804 IMD: root @ 0xfffff000 254 entries.
9220 16:53:54.129996 IMD: root @ 0xffffec00 62 entries.
9221 16:53:54.133287 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9222 16:53:54.136540 WARNING: RO_VPD is uninitialized or empty.
9223 16:53:54.142912 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9224 16:53:54.150037 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9225 16:53:54.162757 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9226 16:53:54.174324 BS: romstage times (exec / console): total (unknown) / 23993 ms
9227 16:53:54.174412
9228 16:53:54.174478
9229 16:53:54.184483 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9230 16:53:54.187642 ARM64: Exception handlers installed.
9231 16:53:54.190864 ARM64: Testing exception
9232 16:53:54.194134 ARM64: Done test exception
9233 16:53:54.194217 Enumerating buses...
9234 16:53:54.197430 Show all devs... Before device enumeration.
9235 16:53:54.200824 Root Device: enabled 1
9236 16:53:54.203919 CPU_CLUSTER: 0: enabled 1
9237 16:53:54.204032 CPU: 00: enabled 1
9238 16:53:54.207205 Compare with tree...
9239 16:53:54.207288 Root Device: enabled 1
9240 16:53:54.210433 CPU_CLUSTER: 0: enabled 1
9241 16:53:54.213668 CPU: 00: enabled 1
9242 16:53:54.213752 Root Device scanning...
9243 16:53:54.216998 scan_static_bus for Root Device
9244 16:53:54.220082 CPU_CLUSTER: 0 enabled
9245 16:53:54.223859 scan_static_bus for Root Device done
9246 16:53:54.226796 scan_bus: bus Root Device finished in 8 msecs
9247 16:53:54.226880 done
9248 16:53:54.233812 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9249 16:53:54.237096 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9250 16:53:54.243757 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9251 16:53:54.250208 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9252 16:53:54.250291 Allocating resources...
9253 16:53:54.253348 Reading resources...
9254 16:53:54.257074 Root Device read_resources bus 0 link: 0
9255 16:53:54.260009 DRAM rank0 size:0x100000000,
9256 16:53:54.260113 DRAM rank1 size=0x100000000
9257 16:53:54.266964 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9258 16:53:54.267079 CPU: 00 missing read_resources
9259 16:53:54.273419 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9260 16:53:54.276770 Root Device read_resources bus 0 link: 0 done
9261 16:53:54.276854 Done reading resources.
9262 16:53:54.283590 Show resources in subtree (Root Device)...After reading.
9263 16:53:54.286829 Root Device child on link 0 CPU_CLUSTER: 0
9264 16:53:54.290109 CPU_CLUSTER: 0 child on link 0 CPU: 00
9265 16:53:54.299843 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9266 16:53:54.299949 CPU: 00
9267 16:53:54.303122 Root Device assign_resources, bus 0 link: 0
9268 16:53:54.306884 CPU_CLUSTER: 0 missing set_resources
9269 16:53:54.313473 Root Device assign_resources, bus 0 link: 0 done
9270 16:53:54.313604 Done setting resources.
9271 16:53:54.319887 Show resources in subtree (Root Device)...After assigning values.
9272 16:53:54.323083 Root Device child on link 0 CPU_CLUSTER: 0
9273 16:53:54.326660 CPU_CLUSTER: 0 child on link 0 CPU: 00
9274 16:53:54.336548 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9275 16:53:54.336635 CPU: 00
9276 16:53:54.340192 Done allocating resources.
9277 16:53:54.346757 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9278 16:53:54.346843 Enabling resources...
9279 16:53:54.346910 done.
9280 16:53:54.353302 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9281 16:53:54.353390 Initializing devices...
9282 16:53:54.356447 Root Device init
9283 16:53:54.356548 init hardware done!
9284 16:53:54.359657 0x00000018: ctrlr->caps
9285 16:53:54.363268 52.000 MHz: ctrlr->f_max
9286 16:53:54.363355 0.400 MHz: ctrlr->f_min
9287 16:53:54.366386 0x40ff8080: ctrlr->voltages
9288 16:53:54.366472 sclk: 390625
9289 16:53:54.369876 Bus Width = 1
9290 16:53:54.369986 sclk: 390625
9291 16:53:54.373123 Bus Width = 1
9292 16:53:54.373225 Early init status = 3
9293 16:53:54.379683 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9294 16:53:54.383405 in-header: 03 fc 00 00 01 00 00 00
9295 16:53:54.383510 in-data: 00
9296 16:53:54.389673 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9297 16:53:54.393412 in-header: 03 fd 00 00 00 00 00 00
9298 16:53:54.396691 in-data:
9299 16:53:54.399957 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9300 16:53:54.403657 in-header: 03 fc 00 00 01 00 00 00
9301 16:53:54.406921 in-data: 00
9302 16:53:54.410213 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9303 16:53:54.416130 in-header: 03 fd 00 00 00 00 00 00
9304 16:53:54.419353 in-data:
9305 16:53:54.422596 [SSUSB] Setting up USB HOST controller...
9306 16:53:54.425879 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9307 16:53:54.429130 [SSUSB] phy power-on done.
9308 16:53:54.432153 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9309 16:53:54.438965 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9310 16:53:54.442635 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9311 16:53:54.448748 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9312 16:53:54.456007 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9313 16:53:54.462384 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9314 16:53:54.468765 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9315 16:53:54.475857 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9316 16:53:54.478995 SPM: binary array size = 0x9dc
9317 16:53:54.482020 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9318 16:53:54.488786 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9319 16:53:54.495666 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9320 16:53:54.498859 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9321 16:53:54.505373 configure_display: Starting display init
9322 16:53:54.539074 anx7625_power_on_init: Init interface.
9323 16:53:54.542343 anx7625_disable_pd_protocol: Disabled PD feature.
9324 16:53:54.545898 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9325 16:53:54.573849 anx7625_start_dp_work: Secure OCM version=00
9326 16:53:54.576756 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9327 16:53:54.591345 sp_tx_get_edid_block: EDID Block = 1
9328 16:53:54.693828 Extracted contents:
9329 16:53:54.697330 header: 00 ff ff ff ff ff ff 00
9330 16:53:54.700551 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9331 16:53:54.704033 version: 01 04
9332 16:53:54.707179 basic params: 95 1f 11 78 0a
9333 16:53:54.710410 chroma info: 76 90 94 55 54 90 27 21 50 54
9334 16:53:54.713785 established: 00 00 00
9335 16:53:54.720252 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9336 16:53:54.723927 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9337 16:53:54.730550 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9338 16:53:54.737089 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9339 16:53:54.743871 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9340 16:53:54.746988 extensions: 00
9341 16:53:54.747072 checksum: fb
9342 16:53:54.747139
9343 16:53:54.750291 Manufacturer: IVO Model 57d Serial Number 0
9344 16:53:54.753599 Made week 0 of 2020
9345 16:53:54.753692 EDID version: 1.4
9346 16:53:54.757405 Digital display
9347 16:53:54.760326 6 bits per primary color channel
9348 16:53:54.760403 DisplayPort interface
9349 16:53:54.763445 Maximum image size: 31 cm x 17 cm
9350 16:53:54.767269 Gamma: 220%
9351 16:53:54.767346 Check DPMS levels
9352 16:53:54.770240 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9353 16:53:54.773803 First detailed timing is preferred timing
9354 16:53:54.777117 Established timings supported:
9355 16:53:54.780412 Standard timings supported:
9356 16:53:54.783483 Detailed timings
9357 16:53:54.786854 Hex of detail: 383680a07038204018303c0035ae10000019
9358 16:53:54.789808 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9359 16:53:54.796605 0780 0798 07c8 0820 hborder 0
9360 16:53:54.800102 0438 043b 0447 0458 vborder 0
9361 16:53:54.803173 -hsync -vsync
9362 16:53:54.803253 Did detailed timing
9363 16:53:54.809776 Hex of detail: 000000000000000000000000000000000000
9364 16:53:54.813383 Manufacturer-specified data, tag 0
9365 16:53:54.816439 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9366 16:53:54.820052 ASCII string: InfoVision
9367 16:53:54.823151 Hex of detail: 000000fe00523134304e574635205248200a
9368 16:53:54.826384 ASCII string: R140NWF5 RH
9369 16:53:54.826458 Checksum
9370 16:53:54.829705 Checksum: 0xfb (valid)
9371 16:53:54.832904 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9372 16:53:54.836167 DSI data_rate: 832800000 bps
9373 16:53:54.843349 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9374 16:53:54.846015 anx7625_parse_edid: pixelclock(138800).
9375 16:53:54.849352 hactive(1920), hsync(48), hfp(24), hbp(88)
9376 16:53:54.852664 vactive(1080), vsync(12), vfp(3), vbp(17)
9377 16:53:54.856479 anx7625_dsi_config: config dsi.
9378 16:53:54.863202 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9379 16:53:54.876096 anx7625_dsi_config: success to config DSI
9380 16:53:54.879084 anx7625_dp_start: MIPI phy setup OK.
9381 16:53:54.882879 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9382 16:53:54.886122 mtk_ddp_mode_set invalid vrefresh 60
9383 16:53:54.889545 main_disp_path_setup
9384 16:53:54.889633 ovl_layer_smi_id_en
9385 16:53:54.892773 ovl_layer_smi_id_en
9386 16:53:54.892872 ccorr_config
9387 16:53:54.892971 aal_config
9388 16:53:54.895825 gamma_config
9389 16:53:54.895901 postmask_config
9390 16:53:54.899667 dither_config
9391 16:53:54.902675 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9392 16:53:54.909444 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9393 16:53:54.912466 Root Device init finished in 552 msecs
9394 16:53:54.916132 CPU_CLUSTER: 0 init
9395 16:53:54.922344 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9396 16:53:54.925991 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9397 16:53:54.929031 APU_MBOX 0x190000b0 = 0x10001
9398 16:53:54.932283 APU_MBOX 0x190001b0 = 0x10001
9399 16:53:54.936089 APU_MBOX 0x190005b0 = 0x10001
9400 16:53:54.939426 APU_MBOX 0x190006b0 = 0x10001
9401 16:53:54.942115 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9402 16:53:54.955371 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9403 16:53:54.967260 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9404 16:53:54.973733 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9405 16:53:54.985832 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9406 16:53:54.994916 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9407 16:53:54.998077 CPU_CLUSTER: 0 init finished in 81 msecs
9408 16:53:55.001331 Devices initialized
9409 16:53:55.005218 Show all devs... After init.
9410 16:53:55.005304 Root Device: enabled 1
9411 16:53:55.008089 CPU_CLUSTER: 0: enabled 1
9412 16:53:55.011842 CPU: 00: enabled 1
9413 16:53:55.014746 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9414 16:53:55.017987 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9415 16:53:55.021583 ELOG: NV offset 0x57f000 size 0x1000
9416 16:53:55.028244 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9417 16:53:55.034495 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9418 16:53:55.038164 ELOG: Event(17) added with size 13 at 2023-06-03 16:53:55 UTC
9419 16:53:55.041247 out: cmd=0x121: 03 db 21 01 00 00 00 00
9420 16:53:55.045082 in-header: 03 d5 00 00 2c 00 00 00
9421 16:53:55.058197 in-data: 8a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9422 16:53:55.064607 ELOG: Event(A1) added with size 10 at 2023-06-03 16:53:55 UTC
9423 16:53:55.071338 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9424 16:53:55.077892 ELOG: Event(A0) added with size 9 at 2023-06-03 16:53:55 UTC
9425 16:53:55.081779 elog_add_boot_reason: Logged dev mode boot
9426 16:53:55.084930 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9427 16:53:55.088052 Finalize devices...
9428 16:53:55.088132 Devices finalized
9429 16:53:55.094881 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9430 16:53:55.097909 Writing coreboot table at 0xffe64000
9431 16:53:55.101709 0. 000000000010a000-0000000000113fff: RAMSTAGE
9432 16:53:55.104827 1. 0000000040000000-00000000400fffff: RAM
9433 16:53:55.111377 2. 0000000040100000-000000004032afff: RAMSTAGE
9434 16:53:55.114657 3. 000000004032b000-00000000545fffff: RAM
9435 16:53:55.118480 4. 0000000054600000-000000005465ffff: BL31
9436 16:53:55.121462 5. 0000000054660000-00000000ffe63fff: RAM
9437 16:53:55.128228 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9438 16:53:55.131390 7. 0000000100000000-000000023fffffff: RAM
9439 16:53:55.131475 Passing 5 GPIOs to payload:
9440 16:53:55.138205 NAME | PORT | POLARITY | VALUE
9441 16:53:55.141289 EC in RW | 0x000000aa | low | undefined
9442 16:53:55.147910 EC interrupt | 0x00000005 | low | undefined
9443 16:53:55.151077 TPM interrupt | 0x000000ab | high | undefined
9444 16:53:55.154306 SD card detect | 0x00000011 | high | undefined
9445 16:53:55.160926 speaker enable | 0x00000093 | high | undefined
9446 16:53:55.164323 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9447 16:53:55.167673 in-header: 03 f9 00 00 02 00 00 00
9448 16:53:55.167758 in-data: 02 00
9449 16:53:55.171663 ADC[4]: Raw value=905096 ID=7
9450 16:53:55.174160 ADC[3]: Raw value=213441 ID=1
9451 16:53:55.174245 RAM Code: 0x71
9452 16:53:55.177997 ADC[6]: Raw value=75701 ID=0
9453 16:53:55.181365 ADC[5]: Raw value=213072 ID=1
9454 16:53:55.181449 SKU Code: 0x1
9455 16:53:55.187785 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ce97
9456 16:53:55.190825 coreboot table: 964 bytes.
9457 16:53:55.194157 IMD ROOT 0. 0xfffff000 0x00001000
9458 16:53:55.197824 IMD SMALL 1. 0xffffe000 0x00001000
9459 16:53:55.201005 RO MCACHE 2. 0xffffc000 0x00001104
9460 16:53:55.204144 CONSOLE 3. 0xfff7c000 0x00080000
9461 16:53:55.207677 FMAP 4. 0xfff7b000 0x00000452
9462 16:53:55.210904 TIME STAMP 5. 0xfff7a000 0x00000910
9463 16:53:55.214084 VBOOT WORK 6. 0xfff66000 0x00014000
9464 16:53:55.217406 RAMOOPS 7. 0xffe66000 0x00100000
9465 16:53:55.221172 COREBOOT 8. 0xffe64000 0x00002000
9466 16:53:55.221255 IMD small region:
9467 16:53:55.224520 IMD ROOT 0. 0xffffec00 0x00000400
9468 16:53:55.227634 VPD 1. 0xffffeba0 0x0000004c
9469 16:53:55.230605 MMC STATUS 2. 0xffffeb80 0x00000004
9470 16:53:55.237381 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9471 16:53:55.240599 Probing TPM: done!
9472 16:53:55.244279 Connected to device vid:did:rid of 1ae0:0028:00
9473 16:53:55.254635 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9474 16:53:55.257692 Initialized TPM device CR50 revision 0
9475 16:53:55.261431 Checking cr50 for pending updates
9476 16:53:55.264703 Reading cr50 TPM mode
9477 16:53:55.273091 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9478 16:53:55.280345 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9479 16:53:55.320476 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9480 16:53:55.323499 Checking segment from ROM address 0x40100000
9481 16:53:55.326766 Checking segment from ROM address 0x4010001c
9482 16:53:55.333649 Loading segment from ROM address 0x40100000
9483 16:53:55.333734 code (compression=0)
9484 16:53:55.340300 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9485 16:53:55.350283 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9486 16:53:55.350369 it's not compressed!
9487 16:53:55.356671 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9488 16:53:55.360415 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9489 16:53:55.380510 Loading segment from ROM address 0x4010001c
9490 16:53:55.380598 Entry Point 0x80000000
9491 16:53:55.383845 Loaded segments
9492 16:53:55.386923 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9493 16:53:55.394235 Jumping to boot code at 0x80000000(0xffe64000)
9494 16:53:55.400638 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9495 16:53:55.406989 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9496 16:53:55.414565 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9497 16:53:55.418345 Checking segment from ROM address 0x40100000
9498 16:53:55.421464 Checking segment from ROM address 0x4010001c
9499 16:53:55.428272 Loading segment from ROM address 0x40100000
9500 16:53:55.428363 code (compression=1)
9501 16:53:55.434710 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9502 16:53:55.444873 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9503 16:53:55.444982 using LZMA
9504 16:53:55.453489 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9505 16:53:55.459668 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9506 16:53:55.462928 Loading segment from ROM address 0x4010001c
9507 16:53:55.463012 Entry Point 0x54601000
9508 16:53:55.466656 Loaded segments
9509 16:53:55.469818 NOTICE: MT8192 bl31_setup
9510 16:53:55.477099 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9511 16:53:55.480442 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9512 16:53:55.483727 WARNING: region 0:
9513 16:53:55.486931 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 16:53:55.487014 WARNING: region 1:
9515 16:53:55.493423 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9516 16:53:55.496691 WARNING: region 2:
9517 16:53:55.500005 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9518 16:53:55.503646 WARNING: region 3:
9519 16:53:55.506917 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9520 16:53:55.510244 WARNING: region 4:
9521 16:53:55.513386 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9522 16:53:55.516653 WARNING: region 5:
9523 16:53:55.519954 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 16:53:55.523696 WARNING: region 6:
9525 16:53:55.526809 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 16:53:55.526893 WARNING: region 7:
9527 16:53:55.533714 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 16:53:55.540646 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9529 16:53:55.543864 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9530 16:53:55.547034 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9531 16:53:55.553691 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9532 16:53:55.557291 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9533 16:53:55.560291 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9534 16:53:55.566932 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9535 16:53:55.570535 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9536 16:53:55.573677 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9537 16:53:55.580321 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9538 16:53:55.583513 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9539 16:53:55.587446 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9540 16:53:55.594159 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9541 16:53:55.597207 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9542 16:53:55.603841 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9543 16:53:55.607031 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9544 16:53:55.610852 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9545 16:53:55.617159 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9546 16:53:55.620546 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9547 16:53:55.623825 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9548 16:53:55.630324 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9549 16:53:55.633671 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9550 16:53:55.640559 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9551 16:53:55.644294 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9552 16:53:55.647667 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9553 16:53:55.654212 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9554 16:53:55.657346 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9555 16:53:55.664020 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9556 16:53:55.667398 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9557 16:53:55.670558 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9558 16:53:55.677001 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9559 16:53:55.680318 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9560 16:53:55.683459 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9561 16:53:55.690388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9562 16:53:55.693635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9563 16:53:55.696937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9564 16:53:55.700756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9565 16:53:55.707323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9566 16:53:55.710529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9567 16:53:55.713784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9568 16:53:55.717027 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9569 16:53:55.723951 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9570 16:53:55.727124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9571 16:53:55.730518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9572 16:53:55.733698 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9573 16:53:55.740238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9574 16:53:55.744003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9575 16:53:55.747164 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9576 16:53:55.753725 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9577 16:53:55.757148 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9578 16:53:55.760478 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9579 16:53:55.767402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9580 16:53:55.770517 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9581 16:53:55.777272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9582 16:53:55.780355 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9583 16:53:55.787235 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9584 16:53:55.790409 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9585 16:53:55.794203 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9586 16:53:55.800773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9587 16:53:55.804035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9588 16:53:55.810482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9589 16:53:55.814302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9590 16:53:55.820703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9591 16:53:55.823859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9592 16:53:55.830298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9593 16:53:55.833780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9594 16:53:55.837418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9595 16:53:55.843973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9596 16:53:55.847291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9597 16:53:55.853363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9598 16:53:55.857321 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9599 16:53:55.863696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9600 16:53:55.867477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9601 16:53:55.870608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9602 16:53:55.876842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9603 16:53:55.880470 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9604 16:53:55.887173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9605 16:53:55.890340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9606 16:53:55.897173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9607 16:53:55.900319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9608 16:53:55.904124 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9609 16:53:55.910483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9610 16:53:55.913764 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9611 16:53:55.920852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9612 16:53:55.924192 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9613 16:53:55.927395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9614 16:53:55.933858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9615 16:53:55.937107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9616 16:53:55.944093 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9617 16:53:55.947578 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9618 16:53:55.954241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9619 16:53:55.957312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9620 16:53:55.960681 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9621 16:53:55.967729 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9622 16:53:55.970730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9623 16:53:55.977200 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9624 16:53:55.981131 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9625 16:53:55.984029 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9626 16:53:55.990596 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9627 16:53:55.994377 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9628 16:53:55.997291 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9629 16:53:56.001009 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9630 16:53:56.007753 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9631 16:53:56.010827 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9632 16:53:56.017193 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9633 16:53:56.020470 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9634 16:53:56.024147 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9635 16:53:56.030608 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9636 16:53:56.033813 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9637 16:53:56.041028 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9638 16:53:56.044171 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9639 16:53:56.047238 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9640 16:53:56.054384 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9641 16:53:56.057707 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9642 16:53:56.063933 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9643 16:53:56.067227 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9644 16:53:56.070471 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9645 16:53:56.077295 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9646 16:53:56.080555 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9647 16:53:56.083829 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9648 16:53:56.087260 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9649 16:53:56.093516 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9650 16:53:56.097082 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9651 16:53:56.100580 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9652 16:53:56.104344 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9653 16:53:56.110657 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9654 16:53:56.114276 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9655 16:53:56.120436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9656 16:53:56.124129 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9657 16:53:56.127269 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9658 16:53:56.133902 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9659 16:53:56.137072 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9660 16:53:56.144090 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9661 16:53:56.147431 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9662 16:53:56.150631 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9663 16:53:56.157705 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9664 16:53:56.161173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9665 16:53:56.164314 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9666 16:53:56.171006 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9667 16:53:56.174259 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9668 16:53:56.180981 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9669 16:53:56.184360 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9670 16:53:56.187654 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9671 16:53:56.194214 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9672 16:53:56.197434 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9673 16:53:56.200833 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9674 16:53:56.207379 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9675 16:53:56.210881 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9676 16:53:56.217688 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9677 16:53:56.220671 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9678 16:53:56.224371 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9679 16:53:56.230673 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9680 16:53:56.234362 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9681 16:53:56.240867 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9682 16:53:56.243952 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9683 16:53:56.247809 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9684 16:53:56.254400 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9685 16:53:56.257703 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9686 16:53:56.260826 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9687 16:53:56.267276 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9688 16:53:56.271138 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9689 16:53:56.277873 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9690 16:53:56.280934 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9691 16:53:56.284122 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9692 16:53:56.290742 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9693 16:53:56.294101 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9694 16:53:56.300630 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9695 16:53:56.303921 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9696 16:53:56.307165 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9697 16:53:56.313997 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9698 16:53:56.317080 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9699 16:53:56.324360 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9700 16:53:56.327440 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9701 16:53:56.330394 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9702 16:53:56.337186 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9703 16:53:56.340423 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9704 16:53:56.347434 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9705 16:53:56.350628 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9706 16:53:56.353992 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9707 16:53:56.360358 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9708 16:53:56.363587 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9709 16:53:56.366873 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9710 16:53:56.373468 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9711 16:53:56.376788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9712 16:53:56.384102 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9713 16:53:56.387430 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9714 16:53:56.390647 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9715 16:53:56.397354 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9716 16:53:56.400648 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9717 16:53:56.407432 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9718 16:53:56.410537 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9719 16:53:56.416954 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9720 16:53:56.420083 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9721 16:53:56.423957 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9722 16:53:56.430003 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9723 16:53:56.433931 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9724 16:53:56.440174 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9725 16:53:56.443927 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9726 16:53:56.446971 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9727 16:53:56.453597 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9728 16:53:56.457075 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9729 16:53:56.463989 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9730 16:53:56.467251 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9731 16:53:56.470451 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9732 16:53:56.477143 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9733 16:53:56.480102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9734 16:53:56.486828 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9735 16:53:56.490683 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9736 16:53:56.493384 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9737 16:53:56.500089 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9738 16:53:56.503788 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9739 16:53:56.510146 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9740 16:53:56.513423 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9741 16:53:56.519931 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9742 16:53:56.523845 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9743 16:53:56.526922 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9744 16:53:56.533130 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9745 16:53:56.536697 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9746 16:53:56.543551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9747 16:53:56.546565 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9748 16:53:56.552945 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9749 16:53:56.556823 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9750 16:53:56.559994 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9751 16:53:56.566670 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9752 16:53:56.569778 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9753 16:53:56.576926 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9754 16:53:56.580069 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9755 16:53:56.583205 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9756 16:53:56.589838 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9757 16:53:56.593129 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9758 16:53:56.596227 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9759 16:53:56.600156 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9760 16:53:56.606464 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9761 16:53:56.609567 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9762 16:53:56.613269 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9763 16:53:56.619775 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9764 16:53:56.623142 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9765 16:53:56.626318 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9766 16:53:56.632808 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9767 16:53:56.636540 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9768 16:53:56.643233 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9769 16:53:56.646268 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9770 16:53:56.649918 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9771 16:53:56.656085 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9772 16:53:56.659445 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9773 16:53:56.662720 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9774 16:53:56.669628 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9775 16:53:56.672817 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9776 16:53:56.676182 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9777 16:53:56.683130 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9778 16:53:56.686226 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9779 16:53:56.692771 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9780 16:53:56.696117 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9781 16:53:56.699456 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9782 16:53:56.706157 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9783 16:53:56.709350 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9784 16:53:56.712631 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9785 16:53:56.719527 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9786 16:53:56.722837 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9787 16:53:56.726061 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9788 16:53:56.732392 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9789 16:53:56.735709 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9790 16:53:56.742789 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9791 16:53:56.745708 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9792 16:53:56.749323 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9793 16:53:56.755546 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9794 16:53:56.759352 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9795 16:53:56.762277 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9796 16:53:56.769389 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9797 16:53:56.772675 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9798 16:53:56.775604 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9799 16:53:56.779588 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9800 16:53:56.785628 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9801 16:53:56.789224 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9802 16:53:56.792311 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9803 16:53:56.795588 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9804 16:53:56.802147 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9805 16:53:56.805333 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9806 16:53:56.808729 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9807 16:53:56.812623 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9808 16:53:56.818745 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9809 16:53:56.821980 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9810 16:53:56.825287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9811 16:53:56.832333 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9812 16:53:56.835611 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9813 16:53:56.842211 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9814 16:53:56.845452 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9815 16:53:56.848598 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9816 16:53:56.855207 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9817 16:53:56.858804 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9818 16:53:56.865470 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9819 16:53:56.868327 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9820 16:53:56.871964 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9821 16:53:56.878804 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9822 16:53:56.881956 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9823 16:53:56.888928 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9824 16:53:56.891993 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9825 16:53:56.895041 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9826 16:53:56.902160 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9827 16:53:56.905352 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9828 16:53:56.912000 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9829 16:53:56.915332 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9830 16:53:56.921598 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9831 16:53:56.925102 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9832 16:53:56.928372 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9833 16:53:56.935422 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9834 16:53:56.938472 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9835 16:53:56.945026 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9836 16:53:56.948507 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9837 16:53:56.951734 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9838 16:53:56.958198 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9839 16:53:56.962009 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9840 16:53:56.968014 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9841 16:53:56.971920 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9842 16:53:56.974973 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9843 16:53:56.981486 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9844 16:53:56.984926 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9845 16:53:56.991469 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9846 16:53:56.995186 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9847 16:53:56.998414 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9848 16:53:57.005299 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9849 16:53:57.008310 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9850 16:53:57.014896 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9851 16:53:57.018073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9852 16:53:57.021386 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9853 16:53:57.028410 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9854 16:53:57.031708 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9855 16:53:57.038136 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9856 16:53:57.041153 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9857 16:53:57.045062 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9858 16:53:57.051715 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9859 16:53:57.055072 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9860 16:53:57.061398 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9861 16:53:57.064722 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9862 16:53:57.071680 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9863 16:53:57.074851 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9864 16:53:57.077914 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9865 16:53:57.084449 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9866 16:53:57.088160 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9867 16:53:57.094696 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9868 16:53:57.098220 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9869 16:53:57.100987 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9870 16:53:57.107707 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9871 16:53:57.111472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9872 16:53:57.117692 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9873 16:53:57.121646 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9874 16:53:57.124924 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9875 16:53:57.131055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9876 16:53:57.134392 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9877 16:53:57.141452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9878 16:53:57.144613 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9879 16:53:57.148256 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9880 16:53:57.154702 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9881 16:53:57.158067 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9882 16:53:57.164666 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9883 16:53:57.167820 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9884 16:53:57.174260 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9885 16:53:57.178132 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9886 16:53:57.181131 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9887 16:53:57.187581 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9888 16:53:57.191295 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9889 16:53:57.197768 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9890 16:53:57.200830 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9891 16:53:57.207438 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9892 16:53:57.210895 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9893 16:53:57.214441 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9894 16:53:57.220763 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9895 16:53:57.224524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9896 16:53:57.230930 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9897 16:53:57.234112 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9898 16:53:57.240598 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9899 16:53:57.243865 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9900 16:53:57.247700 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9901 16:53:57.254321 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9902 16:53:57.257341 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9903 16:53:57.264137 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9904 16:53:57.267310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9905 16:53:57.273741 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9906 16:53:57.277486 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9907 16:53:57.283911 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9908 16:53:57.287119 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9909 16:53:57.290395 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9910 16:53:57.297129 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9911 16:53:57.300319 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9912 16:53:57.306958 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9913 16:53:57.310556 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9914 16:53:57.316665 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9915 16:53:57.320381 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9916 16:53:57.323941 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9917 16:53:57.330230 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9918 16:53:57.333347 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9919 16:53:57.340611 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9920 16:53:57.343846 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9921 16:53:57.350453 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9922 16:53:57.353742 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9923 16:53:57.356876 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9924 16:53:57.363511 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9925 16:53:57.366701 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9926 16:53:57.373145 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9927 16:53:57.376440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9928 16:53:57.383672 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9929 16:53:57.387023 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9930 16:53:57.390131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9931 16:53:57.396342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9932 16:53:57.400027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9933 16:53:57.406402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9934 16:53:57.409406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9935 16:53:57.416112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9936 16:53:57.419998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9937 16:53:57.426008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9938 16:53:57.429717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9939 16:53:57.436519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9940 16:53:57.439640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9941 16:53:57.446025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9942 16:53:57.449268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9943 16:53:57.456466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9944 16:53:57.459753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9945 16:53:57.465883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9946 16:53:57.469612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9947 16:53:57.475961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9948 16:53:57.479291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9949 16:53:57.482980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9950 16:53:57.489742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9951 16:53:57.493003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9952 16:53:57.500021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9953 16:53:57.503302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9954 16:53:57.509446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9955 16:53:57.512621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9956 16:53:57.519294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9957 16:53:57.523126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9958 16:53:57.529106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9959 16:53:57.532760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9960 16:53:57.539181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9961 16:53:57.546034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9962 16:53:57.549620 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9963 16:53:57.549729 INFO: [APUAPC] vio 0
9964 16:53:57.556865 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9965 16:53:57.560069 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9966 16:53:57.563494 INFO: [APUAPC] D0_APC_0: 0x400510
9967 16:53:57.566694 INFO: [APUAPC] D0_APC_1: 0x0
9968 16:53:57.569742 INFO: [APUAPC] D0_APC_2: 0x1540
9969 16:53:57.572977 INFO: [APUAPC] D0_APC_3: 0x0
9970 16:53:57.576148 INFO: [APUAPC] D1_APC_0: 0xffffffff
9971 16:53:57.579903 INFO: [APUAPC] D1_APC_1: 0xffffffff
9972 16:53:57.583235 INFO: [APUAPC] D1_APC_2: 0x3fffff
9973 16:53:57.586402 INFO: [APUAPC] D1_APC_3: 0x0
9974 16:53:57.589599 INFO: [APUAPC] D2_APC_0: 0xffffffff
9975 16:53:57.592970 INFO: [APUAPC] D2_APC_1: 0xffffffff
9976 16:53:57.596216 INFO: [APUAPC] D2_APC_2: 0x3fffff
9977 16:53:57.599463 INFO: [APUAPC] D2_APC_3: 0x0
9978 16:53:57.603209 INFO: [APUAPC] D3_APC_0: 0xffffffff
9979 16:53:57.606532 INFO: [APUAPC] D3_APC_1: 0xffffffff
9980 16:53:57.609655 INFO: [APUAPC] D3_APC_2: 0x3fffff
9981 16:53:57.612914 INFO: [APUAPC] D3_APC_3: 0x0
9982 16:53:57.616680 INFO: [APUAPC] D4_APC_0: 0xffffffff
9983 16:53:57.619753 INFO: [APUAPC] D4_APC_1: 0xffffffff
9984 16:53:57.622853 INFO: [APUAPC] D4_APC_2: 0x3fffff
9985 16:53:57.622962 INFO: [APUAPC] D4_APC_3: 0x0
9986 16:53:57.626371 INFO: [APUAPC] D5_APC_0: 0xffffffff
9987 16:53:57.632806 INFO: [APUAPC] D5_APC_1: 0xffffffff
9988 16:53:57.635963 INFO: [APUAPC] D5_APC_2: 0x3fffff
9989 16:53:57.636047 INFO: [APUAPC] D5_APC_3: 0x0
9990 16:53:57.639667 INFO: [APUAPC] D6_APC_0: 0xffffffff
9991 16:53:57.642720 INFO: [APUAPC] D6_APC_1: 0xffffffff
9992 16:53:57.645903 INFO: [APUAPC] D6_APC_2: 0x3fffff
9993 16:53:57.649666 INFO: [APUAPC] D6_APC_3: 0x0
9994 16:53:57.652769 INFO: [APUAPC] D7_APC_0: 0xffffffff
9995 16:53:57.656362 INFO: [APUAPC] D7_APC_1: 0xffffffff
9996 16:53:57.659428 INFO: [APUAPC] D7_APC_2: 0x3fffff
9997 16:53:57.662748 INFO: [APUAPC] D7_APC_3: 0x0
9998 16:53:57.666220 INFO: [APUAPC] D8_APC_0: 0xffffffff
9999 16:53:57.669378 INFO: [APUAPC] D8_APC_1: 0xffffffff
10000 16:53:57.672484 INFO: [APUAPC] D8_APC_2: 0x3fffff
10001 16:53:57.675742 INFO: [APUAPC] D8_APC_3: 0x0
10002 16:53:57.679099 INFO: [APUAPC] D9_APC_0: 0xffffffff
10003 16:53:57.682832 INFO: [APUAPC] D9_APC_1: 0xffffffff
10004 16:53:57.686037 INFO: [APUAPC] D9_APC_2: 0x3fffff
10005 16:53:57.689230 INFO: [APUAPC] D9_APC_3: 0x0
10006 16:53:57.692491 INFO: [APUAPC] D10_APC_0: 0xffffffff
10007 16:53:57.695706 INFO: [APUAPC] D10_APC_1: 0xffffffff
10008 16:53:57.699051 INFO: [APUAPC] D10_APC_2: 0x3fffff
10009 16:53:57.702680 INFO: [APUAPC] D10_APC_3: 0x0
10010 16:53:57.706003 INFO: [APUAPC] D11_APC_0: 0xffffffff
10011 16:53:57.709177 INFO: [APUAPC] D11_APC_1: 0xffffffff
10012 16:53:57.712552 INFO: [APUAPC] D11_APC_2: 0x3fffff
10013 16:53:57.715806 INFO: [APUAPC] D11_APC_3: 0x0
10014 16:53:57.718884 INFO: [APUAPC] D12_APC_0: 0xffffffff
10015 16:53:57.722726 INFO: [APUAPC] D12_APC_1: 0xffffffff
10016 16:53:57.725851 INFO: [APUAPC] D12_APC_2: 0x3fffff
10017 16:53:57.728835 INFO: [APUAPC] D12_APC_3: 0x0
10018 16:53:57.732446 INFO: [APUAPC] D13_APC_0: 0xffffffff
10019 16:53:57.735690 INFO: [APUAPC] D13_APC_1: 0xffffffff
10020 16:53:57.738746 INFO: [APUAPC] D13_APC_2: 0x3fffff
10021 16:53:57.742377 INFO: [APUAPC] D13_APC_3: 0x0
10022 16:53:57.745465 INFO: [APUAPC] D14_APC_0: 0xffffffff
10023 16:53:57.748603 INFO: [APUAPC] D14_APC_1: 0xffffffff
10024 16:53:57.752343 INFO: [APUAPC] D14_APC_2: 0x3fffff
10025 16:53:57.755086 INFO: [APUAPC] D14_APC_3: 0x0
10026 16:53:57.758870 INFO: [APUAPC] D15_APC_0: 0xffffffff
10027 16:53:57.762032 INFO: [APUAPC] D15_APC_1: 0xffffffff
10028 16:53:57.765637 INFO: [APUAPC] D15_APC_2: 0x3fffff
10029 16:53:57.769045 INFO: [APUAPC] D15_APC_3: 0x0
10030 16:53:57.772388 INFO: [APUAPC] APC_CON: 0x4
10031 16:53:57.775480 INFO: [NOCDAPC] D0_APC_0: 0x0
10032 16:53:57.778735 INFO: [NOCDAPC] D0_APC_1: 0x0
10033 16:53:57.781922 INFO: [NOCDAPC] D1_APC_0: 0x0
10034 16:53:57.785193 INFO: [NOCDAPC] D1_APC_1: 0xfff
10035 16:53:57.788360 INFO: [NOCDAPC] D2_APC_0: 0x0
10036 16:53:57.788444 INFO: [NOCDAPC] D2_APC_1: 0xfff
10037 16:53:57.792166 INFO: [NOCDAPC] D3_APC_0: 0x0
10038 16:53:57.795281 INFO: [NOCDAPC] D3_APC_1: 0xfff
10039 16:53:57.798679 INFO: [NOCDAPC] D4_APC_0: 0x0
10040 16:53:57.801965 INFO: [NOCDAPC] D4_APC_1: 0xfff
10041 16:53:57.805109 INFO: [NOCDAPC] D5_APC_0: 0x0
10042 16:53:57.808328 INFO: [NOCDAPC] D5_APC_1: 0xfff
10043 16:53:57.811709 INFO: [NOCDAPC] D6_APC_0: 0x0
10044 16:53:57.814889 INFO: [NOCDAPC] D6_APC_1: 0xfff
10045 16:53:57.818292 INFO: [NOCDAPC] D7_APC_0: 0x0
10046 16:53:57.821410 INFO: [NOCDAPC] D7_APC_1: 0xfff
10047 16:53:57.825191 INFO: [NOCDAPC] D8_APC_0: 0x0
10048 16:53:57.825302 INFO: [NOCDAPC] D8_APC_1: 0xfff
10049 16:53:57.828406 INFO: [NOCDAPC] D9_APC_0: 0x0
10050 16:53:57.831675 INFO: [NOCDAPC] D9_APC_1: 0xfff
10051 16:53:57.834651 INFO: [NOCDAPC] D10_APC_0: 0x0
10052 16:53:57.838284 INFO: [NOCDAPC] D10_APC_1: 0xfff
10053 16:53:57.841293 INFO: [NOCDAPC] D11_APC_0: 0x0
10054 16:53:57.844980 INFO: [NOCDAPC] D11_APC_1: 0xfff
10055 16:53:57.847917 INFO: [NOCDAPC] D12_APC_0: 0x0
10056 16:53:57.851035 INFO: [NOCDAPC] D12_APC_1: 0xfff
10057 16:53:57.854881 INFO: [NOCDAPC] D13_APC_0: 0x0
10058 16:53:57.858200 INFO: [NOCDAPC] D13_APC_1: 0xfff
10059 16:53:57.861375 INFO: [NOCDAPC] D14_APC_0: 0x0
10060 16:53:57.864754 INFO: [NOCDAPC] D14_APC_1: 0xfff
10061 16:53:57.867756 INFO: [NOCDAPC] D15_APC_0: 0x0
10062 16:53:57.870993 INFO: [NOCDAPC] D15_APC_1: 0xfff
10063 16:53:57.871077 INFO: [NOCDAPC] APC_CON: 0x4
10064 16:53:57.874858 INFO: [APUAPC] set_apusys_apc done
10065 16:53:57.878119 INFO: [DEVAPC] devapc_init done
10066 16:53:57.884386 INFO: GICv3 without legacy support detected.
10067 16:53:57.887671 INFO: ARM GICv3 driver initialized in EL3
10068 16:53:57.890888 INFO: Maximum SPI INTID supported: 639
10069 16:53:57.894751 INFO: BL31: Initializing runtime services
10070 16:53:57.901122 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10071 16:53:57.904364 INFO: SPM: enable CPC mode
10072 16:53:57.907712 INFO: mcdi ready for mcusys-off-idle and system suspend
10073 16:53:57.914600 INFO: BL31: Preparing for EL3 exit to normal world
10074 16:53:57.917981 INFO: Entry point address = 0x80000000
10075 16:53:57.918066 INFO: SPSR = 0x8
10076 16:53:57.924662
10077 16:53:57.924745
10078 16:53:57.924811
10079 16:53:57.927833 Starting depthcharge on Spherion...
10080 16:53:57.927943
10081 16:53:57.928037 Wipe memory regions:
10082 16:53:57.928126
10083 16:53:57.928913 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10084 16:53:57.929041 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10085 16:53:57.929153 Setting prompt string to ['asurada:']
10086 16:53:57.929262 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10087 16:53:57.930995 [0x00000040000000, 0x00000054600000)
10088 16:53:58.053515
10089 16:53:58.053691 [0x00000054660000, 0x00000080000000)
10090 16:53:58.314147
10091 16:53:58.314285 [0x000000821a7280, 0x000000ffe64000)
10092 16:53:59.059009
10093 16:53:59.059186 [0x00000100000000, 0x00000240000000)
10094 16:54:00.949885
10095 16:54:00.952832 Initializing XHCI USB controller at 0x11200000.
10096 16:54:01.990683
10097 16:54:01.993866 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10098 16:54:01.993981
10099 16:54:01.994081
10100 16:54:01.994174
10101 16:54:01.994503 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10103 16:54:02.094872 asurada: tftpboot 192.168.201.1 10576315/tftp-deploy-hgos60m6/kernel/image.itb 10576315/tftp-deploy-hgos60m6/kernel/cmdline
10104 16:54:02.095057 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10105 16:54:02.095172 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10106 16:54:02.099328 tftpboot 192.168.201.1 10576315/tftp-deploy-hgos60m6/kernel/image.ittp-deploy-hgos60m6/kernel/cmdline
10107 16:54:02.099440
10108 16:54:02.099557 Waiting for link
10109 16:54:02.260528
10110 16:54:02.260703 R8152: Initializing
10111 16:54:02.260811
10112 16:54:02.263532 Version 9 (ocp_data = 6010)
10113 16:54:02.263637
10114 16:54:02.266574 R8152: Done initializing
10115 16:54:02.266682
10116 16:54:02.266791 Adding net device
10117 16:54:04.212291
10118 16:54:04.212459 done.
10119 16:54:04.212567
10120 16:54:04.212643 MAC: 00:e0:4c:78:7a:aa
10121 16:54:04.212707
10122 16:54:04.215660 Sending DHCP discover... done.
10123 16:54:04.215773
10124 16:54:11.778521 Waiting for reply... done.
10125 16:54:11.779072
10126 16:54:11.779459 Sending DHCP request... done.
10127 16:54:11.780228
10128 16:54:11.784475 Waiting for reply... done.
10129 16:54:11.784942
10130 16:54:11.785326 My ip is 192.168.201.12
10131 16:54:11.785741
10132 16:54:11.788325 The DHCP server ip is 192.168.201.1
10133 16:54:11.788767
10134 16:54:11.794711 TFTP server IP predefined by user: 192.168.201.1
10135 16:54:11.795177
10136 16:54:11.801493 Bootfile predefined by user: 10576315/tftp-deploy-hgos60m6/kernel/image.itb
10137 16:54:11.801959
10138 16:54:11.802291 Sending tftp read request... done.
10139 16:54:11.804823
10140 16:54:11.810163 Waiting for the transfer...
10141 16:54:11.810603
10142 16:54:12.085520 00000000 ################################################################
10143 16:54:12.085733
10144 16:54:12.328558 00080000 ################################################################
10145 16:54:12.328697
10146 16:54:12.574787 00100000 ################################################################
10147 16:54:12.574947
10148 16:54:12.822001 00180000 ################################################################
10149 16:54:12.822165
10150 16:54:13.069596 00200000 ################################################################
10151 16:54:13.069757
10152 16:54:13.316181 00280000 ################################################################
10153 16:54:13.316324
10154 16:54:13.565971 00300000 ################################################################
10155 16:54:13.566141
10156 16:54:13.812120 00380000 ################################################################
10157 16:54:13.812315
10158 16:54:14.065878 00400000 ################################################################
10159 16:54:14.066029
10160 16:54:14.330120 00480000 ################################################################
10161 16:54:14.330259
10162 16:54:14.582021 00500000 ################################################################
10163 16:54:14.582154
10164 16:54:14.831975 00580000 ################################################################
10165 16:54:14.832111
10166 16:54:15.097095 00600000 ################################################################
10167 16:54:15.097235
10168 16:54:15.349455 00680000 ################################################################
10169 16:54:15.349632
10170 16:54:15.607936 00700000 ################################################################
10171 16:54:15.608103
10172 16:54:15.850212 00780000 ################################################################
10173 16:54:15.850376
10174 16:54:16.102329 00800000 ################################################################
10175 16:54:16.102495
10176 16:54:16.351671 00880000 ################################################################
10177 16:54:16.351818
10178 16:54:16.607774 00900000 ################################################################
10179 16:54:16.607920
10180 16:54:16.865178 00980000 ################################################################
10181 16:54:16.865317
10182 16:54:17.125584 00a00000 ################################################################
10183 16:54:17.125739
10184 16:54:17.380072 00a80000 ################################################################
10185 16:54:17.380206
10186 16:54:17.643612 00b00000 ################################################################
10187 16:54:17.643764
10188 16:54:17.892394 00b80000 ################################################################
10189 16:54:17.892539
10190 16:54:18.149617 00c00000 ################################################################
10191 16:54:18.149790
10192 16:54:18.400503 00c80000 ################################################################
10193 16:54:18.400672
10194 16:54:18.664385 00d00000 ################################################################
10195 16:54:18.664550
10196 16:54:18.941794 00d80000 ################################################################
10197 16:54:18.941935
10198 16:54:19.218665 00e00000 ################################################################
10199 16:54:19.218800
10200 16:54:19.496687 00e80000 ################################################################
10201 16:54:19.496850
10202 16:54:19.787803 00f00000 ################################################################
10203 16:54:19.787951
10204 16:54:20.063529 00f80000 ################################################################
10205 16:54:20.063684
10206 16:54:20.333710 01000000 ################################################################
10207 16:54:20.333859
10208 16:54:20.592182 01080000 ################################################################
10209 16:54:20.592338
10210 16:54:20.846707 01100000 ################################################################
10211 16:54:20.846850
10212 16:54:21.106571 01180000 ################################################################
10213 16:54:21.106749
10214 16:54:21.378791 01200000 ################################################################
10215 16:54:21.378927
10216 16:54:21.656185 01280000 ################################################################
10217 16:54:21.656317
10218 16:54:21.913292 01300000 ################################################################
10219 16:54:21.913446
10220 16:54:22.163934 01380000 ################################################################
10221 16:54:22.164085
10222 16:54:22.413675 01400000 ################################################################
10223 16:54:22.413826
10224 16:54:22.664485 01480000 ################################################################
10225 16:54:22.664661
10226 16:54:22.915504 01500000 ################################################################
10227 16:54:22.915678
10228 16:54:23.184892 01580000 ################################################################
10229 16:54:23.185080
10230 16:54:23.458166 01600000 ################################################################
10231 16:54:23.458305
10232 16:54:23.752360 01680000 ################################################################
10233 16:54:23.752538
10234 16:54:24.034379 01700000 ################################################################
10235 16:54:24.034558
10236 16:54:24.314266 01780000 ################################################################
10237 16:54:24.314433
10238 16:54:24.575739 01800000 ################################################################
10239 16:54:24.575913
10240 16:54:24.838109 01880000 ################################################################
10241 16:54:24.838271
10242 16:54:25.108913 01900000 ################################################################
10243 16:54:25.109063
10244 16:54:25.370539 01980000 ################################################################
10245 16:54:25.370687
10246 16:54:25.615983 01a00000 ############################################################## done.
10247 16:54:25.616155
10248 16:54:25.619865 The bootfile was 27769270 bytes long.
10249 16:54:25.619958
10250 16:54:25.620027 Sending tftp read request... done.
10251 16:54:25.622990
10252 16:54:25.623082 Waiting for the transfer...
10253 16:54:25.623150
10254 16:54:25.626279 00000000 # done.
10255 16:54:25.626362
10256 16:54:25.632770 Command line loaded dynamically from TFTP file: 10576315/tftp-deploy-hgos60m6/kernel/cmdline
10257 16:54:25.632864
10258 16:54:25.649480 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576315/extract-nfsrootfs-ku2096k5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10259 16:54:25.649612
10260 16:54:25.649699 Loading FIT.
10261 16:54:25.652645
10262 16:54:25.652731 Image ramdisk-1 has 17636840 bytes.
10263 16:54:25.656235
10264 16:54:25.656321 Image fdt-1 has 46924 bytes.
10265 16:54:25.656407
10266 16:54:25.659467 Image kernel-1 has 10083474 bytes.
10267 16:54:25.659554
10268 16:54:25.669417 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10269 16:54:25.669506
10270 16:54:25.685756 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10271 16:54:25.685848
10272 16:54:25.692434 Choosing best match conf-1 for compat google,spherion-rev2.
10273 16:54:25.696056
10274 16:54:25.700570 Connected to device vid:did:rid of 1ae0:0028:00
10275 16:54:25.709097
10276 16:54:25.712053 tpm_get_response: command 0x17b, return code 0x0
10277 16:54:25.712140
10278 16:54:25.715216 ec_init: CrosEC protocol v3 supported (256, 248)
10279 16:54:25.719796
10280 16:54:25.722901 tpm_cleanup: add release locality here.
10281 16:54:25.722987
10282 16:54:25.723086 Shutting down all USB controllers.
10283 16:54:25.723186
10284 16:54:25.726089 Removing current net device
10285 16:54:25.726189
10286 16:54:25.733116 Exiting depthcharge with code 4 at timestamp: 57089481
10287 16:54:25.733217
10288 16:54:25.736465 LZMA decompressing kernel-1 to 0x821a6718
10289 16:54:25.736567
10290 16:54:25.739524 LZMA decompressing kernel-1 to 0x40000000
10291 16:54:27.005380
10292 16:54:27.005548 jumping to kernel
10293 16:54:27.005970 end: 2.2.4 bootloader-commands (duration 00:00:29) [common]
10294 16:54:27.006072 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10295 16:54:27.006151 Setting prompt string to ['Linux version [0-9]']
10296 16:54:27.006221 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10297 16:54:27.006293 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10298 16:54:27.559876
10299 16:54:27.563037 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10300 16:54:27.566425 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10301 16:54:27.566519 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10302 16:54:27.566612 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10303 16:54:27.566693 Using line separator: #'\n'#
10304 16:54:27.566757 No login prompt set.
10305 16:54:27.566825 Parsing kernel messages
10306 16:54:27.566884 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10307 16:54:27.566990 [login-action] Waiting for messages, (timeout 00:03:56)
10308 16:54:27.586062 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
10309 16:54:27.589264 [ 0.000000] random: crng init done
10310 16:54:27.595799 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10311 16:54:27.599049 [ 0.000000] efi: UEFI not found.
10312 16:54:27.605961 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10313 16:54:27.612683 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10314 16:54:27.622573 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10315 16:54:27.632714 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10316 16:54:27.635733 [ 0.000000] NUMA: No NUMA configuration found
10317 16:54:27.645947 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10318 16:54:27.648942 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10319 16:54:27.652348 [ 0.000000] Zone ranges:
10320 16:54:27.659056 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10321 16:54:27.662346 [ 0.000000] DMA32 empty
10322 16:54:27.665624 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10323 16:54:27.672293 [ 0.000000] Movable zone start for each node
10324 16:54:27.675675 [ 0.000000] Early memory node ranges
10325 16:54:27.681923 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10326 16:54:27.688574 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10327 16:54:27.695163 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10328 16:54:27.698350 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10329 16:54:27.705559 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10330 16:54:27.711843 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10331 16:54:27.718712 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10332 16:54:27.725212 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10333 16:54:27.731372 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10334 16:54:27.735212 [ 0.000000] psci: probing for conduit method from DT.
10335 16:54:27.741682 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10336 16:54:27.744717 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10337 16:54:27.751348 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10338 16:54:27.754815 [ 0.000000] psci: SMC Calling Convention v1.2
10339 16:54:27.761146 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10340 16:54:27.764465 [ 0.000000] Detected VIPT I-cache on CPU0
10341 16:54:27.771658 [ 0.000000] CPU features: detected: GIC system register CPU interface
10342 16:54:27.778172 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10343 16:54:27.784542 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10344 16:54:27.791614 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10345 16:54:27.797583 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10346 16:54:27.804122 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10347 16:54:27.811210 [ 0.000000] alternatives: applying boot alternatives
10348 16:54:27.814376 [ 0.000000] Fallback order for Node 0: 0
10349 16:54:27.820664 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10350 16:54:27.824419 [ 0.000000] Policy zone: Normal
10351 16:54:27.844251 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576315/extract-nfsrootfs-ku2096k5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10352 16:54:27.853985 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10353 16:54:27.860659 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10354 16:54:27.866969 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10355 16:54:27.873644 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10356 16:54:27.880843 [ 0.000000] software IO TLB: area num 8.
10357 16:54:27.887617 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10358 16:54:27.900430 [ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10359 16:54:27.906767 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10360 16:54:27.913406 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10361 16:54:27.917244 [ 0.000000] rcu: RCU event tracing is enabled.
10362 16:54:27.923656 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10363 16:54:27.930053 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10364 16:54:27.933635 [ 0.000000] Tracing variant of Tasks RCU enabled.
10365 16:54:27.943266 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10366 16:54:27.950094 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10367 16:54:27.953808 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10368 16:54:27.960197 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10369 16:54:27.963227 [ 0.000000] GICv3: 608 SPIs implemented
10370 16:54:27.966877 [ 0.000000] GICv3: 0 Extended SPIs implemented
10371 16:54:27.973278 [ 0.000000] Root IRQ handler: gic_handle_irq
10372 16:54:27.976609 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10373 16:54:27.983055 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10374 16:54:27.992938 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10375 16:54:28.006487 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10376 16:54:28.013017 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10377 16:54:28.019483 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10378 16:54:28.029312 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10379 16:54:28.039127 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10380 16:54:28.042605 [ 0.000956] Console: colour dummy device 80x25
10381 16:54:28.053062 [ 0.001024] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10382 16:54:28.056101 [ 0.001032] pid_max: default: 32768 minimum: 301
10383 16:54:28.063024 [ 0.001073] LSM: Security Framework initializing
10384 16:54:28.069659 [ 0.001177] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 16:54:28.079661 [ 0.001228] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 16:54:28.086373 [ 0.002470] cblist_init_generic: Setting adjustable number of callback queues.
10387 16:54:28.093035 [ 0.002481] cblist_init_generic: Setting shift to 3 and lim to 1.
10388 16:54:28.095796 [ 0.002524] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 16:54:28.102822 [ 0.002629] rcu: Hierarchical SRCU implementation.
10390 16:54:28.106062 [ 0.002631] rcu: Max phase no-delay instances is 1000.
10391 16:54:28.112355 [ 0.004258] EFI services will not be available.
10392 16:54:28.116088 [ 0.004479] smp: Bringing up secondary CPUs ...
10393 16:54:28.119368 [ 0.004772] Detected VIPT I-cache on CPU1
10394 16:54:28.125952 [ 0.004845] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10395 16:54:28.132301 [ 0.004875] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10396 16:54:28.139283 [ 0.005219] Detected VIPT I-cache on CPU2
10397 16:54:28.145804 [ 0.005269] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10398 16:54:28.152289 [ 0.005285] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10399 16:54:28.155675 [ 0.005549] Detected VIPT I-cache on CPU3
10400 16:54:28.162547 [ 0.005598] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10401 16:54:28.169106 [ 0.005612] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10402 16:54:28.172191 [ 0.005919] CPU features: detected: Spectre-v4
10403 16:54:28.178878 [ 0.005925] CPU features: detected: Spectre-BHB
10404 16:54:28.182053 [ 0.005931] Detected PIPT I-cache on CPU4
10405 16:54:28.189225 [ 0.005989] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10406 16:54:28.195806 [ 0.006006] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10407 16:54:28.199130 [ 0.006307] Detected PIPT I-cache on CPU5
10408 16:54:28.204970 [ 0.006369] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10409 16:54:28.212115 [ 0.006385] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10410 16:54:28.218856 [ 0.006671] Detected PIPT I-cache on CPU6
10411 16:54:28.225272 [ 0.006735] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10412 16:54:28.231916 [ 0.006752] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10413 16:54:28.235126 [ 0.007054] Detected PIPT I-cache on CPU7
10414 16:54:28.241519 [ 0.007119] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10415 16:54:28.248515 [ 0.007135] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10416 16:54:28.251527 [ 0.007182] smp: Brought up 1 node, 8 CPUs
10417 16:54:28.258094 [ 0.007188] SMP: Total of 8 processors activated.
10418 16:54:28.261948 [ 0.007191] CPU features: detected: 32-bit EL0 Support
10419 16:54:28.271841 [ 0.007193] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10420 16:54:28.278377 [ 0.007196] CPU features: detected: Common not Private translations
10421 16:54:28.281414 [ 0.007198] CPU features: detected: CRC32 instructions
10422 16:54:28.287833 [ 0.007201] CPU features: detected: RCpc load-acquire (LDAPR)
10423 16:54:28.294605 [ 0.007203] CPU features: detected: LSE atomic instructions
10424 16:54:28.297787 [ 0.007204] CPU features: detected: Privileged Access Never
10425 16:54:28.304371 [ 0.007206] CPU features: detected: RAS Extension Support
10426 16:54:28.311365 [ 0.007209] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10427 16:54:28.314747 [ 0.007276] CPU: All CPU(s) started at EL2
10428 16:54:28.321272 [ 0.007278] alternatives: applying system-wide alternatives
10429 16:54:28.324152 [ 0.012246] devtmpfs: initialized
10430 16:54:28.334173 [ 0.017459] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10431 16:54:28.340723 [ 0.017473] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10432 16:54:28.347309 [ 0.018513] pinctrl core: initialized pinctrl subsystem
10433 16:54:28.350897 [ 0.019687] DMI not present or invalid.
10434 16:54:28.354126 [ 0.020024] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10435 16:54:28.363921 [ 0.020761] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10436 16:54:28.370808 [ 0.020980] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10437 16:54:28.377574 [ 0.021155] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10438 16:54:28.384074 [ 0.021181] audit: initializing netlink subsys (disabled)
10439 16:54:28.390832 [ 0.021251] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10440 16:54:28.397151 [ 0.021937] thermal_sys: Registered thermal governor 'step_wise'
10441 16:54:28.403704 [ 0.021941] thermal_sys: Registered thermal governor 'power_allocator'
10442 16:54:28.406932 [ 0.021968] cpuidle: using governor menu
10443 16:54:28.414151 [ 0.022030] NET: Registered PF_QIPCRTR protocol family
10444 16:54:28.420683 [ 0.022140] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10445 16:54:28.427087 [ 0.022245] ASID allocator initialised with 32768 entries
10446 16:54:28.430232 [ 0.023167] Serial: AMBA PL011 UART driver
10447 16:54:28.433965 [ 0.027433] Trying to register duplicate clock ID: 134
10448 16:54:28.436903 [ 0.079446] KASLR enabled
10449 16:54:28.443515 [ 0.084387] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10450 16:54:28.449964 [ 0.084391] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10451 16:54:28.457119 [ 0.084395] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10452 16:54:28.463322 [ 0.084398] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10453 16:54:28.470610 [ 0.084401] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10454 16:54:28.476922 [ 0.084403] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10455 16:54:28.483559 [ 0.084406] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10456 16:54:28.490222 [ 0.084408] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10457 16:54:28.493195 [ 0.085375] ACPI: Interpreter disabled.
10458 16:54:28.496360 [ 0.087694] iommu: Default domain type: Translated
10459 16:54:28.503146 [ 0.087698] iommu: DMA domain TLB invalidation policy: strict mode
10460 16:54:28.506323 [ 0.087873] SCSI subsystem initialized
10461 16:54:28.512854 [ 0.088062] usbcore: registered new interface driver usbfs
10462 16:54:28.519480 [ 0.088079] usbcore: registered new interface driver hub
10463 16:54:28.522925 [ 0.088092] usbcore: registered new device driver usb
10464 16:54:28.529385 [ 0.088895] pps_core: LinuxPPS API ver. 1 registered
10465 16:54:28.539617 [ 0.088898] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10466 16:54:28.542650 [ 0.088905] PTP clock support registered
10467 16:54:28.545910 [ 0.088988] EDAC MC: Ver: 3.0.0
10468 16:54:28.549177 [ 0.090883] FPGA manager framework
10469 16:54:28.555925 [ 0.090924] Advanced Linux Sound Architecture Driver Initialized.
10470 16:54:28.556038 [ 0.091388] vgaarb: loaded
10471 16:54:28.562479 [ 0.091603] clocksource: Switched to clocksource arch_sys_counter
10472 16:54:28.566279 [ 0.091726] VFS: Disk quotas dquot_6.6.0
10473 16:54:28.572758 [ 0.091756] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10474 16:54:28.575645 [ 0.091857] pnp: PnP ACPI: disabled
10475 16:54:28.582629 [ 0.094687] NET: Registered PF_INET protocol family
10476 16:54:28.589318 [ 0.095078] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10477 16:54:28.598802 [ 0.099604] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10478 16:54:28.605760 [ 0.099678] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10479 16:54:28.615453 [ 0.099696] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10480 16:54:28.622605 [ 0.100269] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10481 16:54:28.629131 [ 0.102408] TCP: Hash tables configured (established 65536 bind 65536)
10482 16:54:28.635683 [ 0.102520] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10483 16:54:28.641763 [ 0.102712] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 16:54:28.648843 [ 0.102969] NET: Registered PF_UNIX/PF_LOCAL protocol family
10485 16:54:28.651938 [ 0.103171] RPC: Registered named UNIX socket transport module.
10486 16:54:28.659279 [ 0.103174] RPC: Registered udp transport module.
10487 16:54:28.661928 [ 0.103175] RPC: Registered tcp transport module.
10488 16:54:28.669097 [ 0.103177] RPC: Registered tcp NFSv4.1 backchannel transport module.
10489 16:54:28.671975 [ 0.103183] PCI: CLS 0 bytes, default 64
10490 16:54:28.675278 [ 0.103358] Unpacking initramfs...
10491 16:54:28.685263 [ 0.120173] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10492 16:54:28.692177 [ 0.120398] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10493 16:54:28.698377 [ 0.120804] kvm [1]: IPA Size Limit: 40 bits
10494 16:54:28.701906 [ 0.120825] kvm [1]: GICv3: no GICV resource entry
10495 16:54:28.705660 [ 0.120829] kvm [1]: disabling GICv2 emulation
10496 16:54:28.711493 [ 0.120842] kvm [1]: GIC system register CPU interface enabled
10497 16:54:28.715249 [ 0.120929] kvm [1]: vgic interrupt IRQ18
10498 16:54:28.721711 [ 0.121027] kvm [1]: VHE mode initialized successfully
10499 16:54:28.725000 [ 0.121916] Initialise system trusted keyrings
10500 16:54:28.731509 [ 0.122000] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10501 16:54:28.738178 [ 0.125300] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10502 16:54:28.741330 [ 0.125617] NFS: Registering the id_resolver key type
10503 16:54:28.748320 [ 0.125635] Key type id_resolver registered
10504 16:54:28.751425 [ 0.125637] Key type id_legacy registered
10505 16:54:28.758531 [ 0.125674] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10506 16:54:28.765069 [ 0.125678] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10507 16:54:28.771515 [ 0.125753] 9p: Installing v9fs 9p2000 file system support
10508 16:54:28.774740 [ 0.158742] Key type asymmetric registered
10509 16:54:28.781477 [ 0.158749] Asymmetric key parser 'x509' registered
10510 16:54:28.787728 [ 0.158799] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10511 16:54:28.791501 [ 0.158804] io scheduler mq-deadline registered
10512 16:54:28.794604 [ 0.158807] io scheduler kyber registered
10513 16:54:28.797878 [ 0.171289] EINJ: ACPI disabled.
10514 16:54:28.807820 [ 0.192964] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 16:54:28.818258 [ 0.193103] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 16:54:28.824369 [ 0.202872] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10517 16:54:28.830942 [ 0.204282] printk: console [ttyS0] disabled
10518 16:54:28.838035 [ 0.224428] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10519 16:54:28.844542 [ 0.831110] Freeing initrd memory: 17220K
10520 16:54:28.847710 [ 0.835480] printk: console [ttyS0] enabled
10521 16:54:28.854019 [ 1.514973] SuperH (H)SCI(F) driver initialized
10522 16:54:28.857200 [ 1.519962] msm_serial: driver initialized
10523 16:54:28.870436 [ 1.528555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10524 16:54:28.877200 [ 1.536842] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10525 16:54:28.886663 [ 1.545125] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10526 16:54:28.896964 [ 1.553493] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10527 16:54:28.903227 [ 1.561938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10528 16:54:28.913254 [ 1.570390] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10529 16:54:28.919946 [ 1.578670] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10530 16:54:28.929771 [ 1.587200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10531 16:54:28.936284 [ 1.595482] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10532 16:54:28.945479 [ 1.610286] loop: module loaded
10533 16:54:28.954049 [ 1.615926] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10534 16:54:28.976936 [ 1.638269] mtk-pmic-keys: Failed to locate of_node [id: -1]
10535 16:54:28.980024 [ 1.644564] megasas: 07.719.03.00-rc1
10536 16:54:28.991874 [ 1.653735] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10537 16:54:29.002786 [ 1.662996] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10538 16:54:29.009006 [ 1.664691] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10539 16:54:29.018237 [ 1.679827] tun: Universal TUN/TAP device driver, 1.6
10540 16:54:29.025657 [ 1.680923] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10541 16:54:29.030063 [ 1.685619] thunder_xcv, ver 1.0
10542 16:54:29.030176 [ 1.694285] thunder_bgx, ver 1.0
10543 16:54:29.033537 [ 1.697521] nicpf, ver 1.0
10544 16:54:29.042697 [ 1.701263] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10545 16:54:29.056450 [ 1.708478] hns3: Copyright (c) 2017 Huawei Corporation.
10546 16:54:29.057043 [ 1.713808] hclge is initializing
10547 16:54:29.057149 [ 1.717129] e1000: Intel(R) PRO/1000 Network Driver
10548 16:54:29.061116 [ 1.721998] e1000: Copyright (c) 1999-2006 Intel Corporation.
10549 16:54:29.069094 [ 1.727750] e1000e: Intel(R) PRO/1000 Network Driver
10550 16:54:29.075450 [ 1.732706] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10551 16:54:29.078853 [ 1.738630] igb: Intel(R) Gigabit Ethernet Network Driver
10552 16:54:29.082055 [ 1.744020] igb: Copyright (c) 2007-2014 Intel Corporation.
10553 16:54:29.091972 [ 1.745129] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10554 16:54:29.098820 [ 1.749594] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10555 16:54:29.105233 [ 1.766609] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10556 16:54:29.108905 [ 1.772808] sky2: driver version 1.30
10557 16:54:29.115925 [ 1.777519] VFIO - User Level meta-driver version: 0.3
10558 16:54:29.123709 [ 1.785384] usbcore: registered new interface driver usb-storage
10559 16:54:29.130747 [ 1.791563] usbcore: registered new device driver onboard-usb-hub
10560 16:54:29.138550 [ 1.800300] mt6397-rtc mt6359-rtc: registered as rtc0
10561 16:54:29.149303 [ 1.805507] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:54:29 UTC (1685811269)
10562 16:54:29.152063 [ 1.814805] i2c_dev: i2c /dev entries driver
10563 16:54:29.168185 [ 1.826203] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10564 16:54:29.174483 [ 1.836134] sdhci: Secure Digital Host Controller Interface driver
10565 16:54:29.181315 [ 1.842310] sdhci: Copyright(c) Pierre Ossman
10566 16:54:29.187967 [ 1.847472] Synopsys Designware Multimedia Card Interface Driver
10567 16:54:29.191175 [ 1.853925] mmc0: CQHCI version 5.10
10568 16:54:29.197615 [ 1.854368] sdhci-pltfm: SDHCI platform and OF driver helper
10569 16:54:29.204746 [ 1.865242] ledtrig-cpu: registered to indicate activity on CPUs
10570 16:54:29.210894 [ 1.872121] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10571 16:54:29.217546 [ 1.879259] usbcore: registered new interface driver usbhid
10572 16:54:29.221101 [ 1.884826] usbhid: USB HID core driver
10573 16:54:29.227278 [ 1.888814] spi_master spi0: will run message pump with realtime priority
10574 16:54:29.272207 [ 1.927514] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10575 16:54:29.287496 [ 1.942325] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10576 16:54:29.294735 [ 1.955626] mmc0: Command Queue Engine enabled
10577 16:54:29.298000 [ 1.957246] cros-ec-spi spi0.0: Chrome EC device registered
10578 16:54:29.305296 [ 1.960081] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10579 16:54:29.311509 [ 1.972497] mmcblk0: mmc0:0001 DA4128 116 GiB
10580 16:54:29.320832 [ 1.982528] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10581 16:54:29.330879 [ 1.982921] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10582 16:54:29.334652 [ 1.990619] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10583 16:54:29.340663 [ 1.999333] NET: Registered PF_PACKET protocol family
10584 16:54:29.344208 [ 2.003286] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10585 16:54:29.350780 [ 2.007375] 9pnet: Installing 9P2000 support
10586 16:54:29.357616 [ 2.013025] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10587 16:54:29.360837 [ 2.016540] Key type dns_resolver registered
10588 16:54:29.364104 [ 2.027505] registered taskstats version 1
10589 16:54:29.370681 [ 2.031630] Loading compiled-in X.509 certificates
10590 16:54:29.403973 [ 2.059254] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 16:54:29.414161 [ 2.069826] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 16:54:29.423873 [ 2.082147] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10593 16:54:29.435856 [ 2.097470] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10594 16:54:29.442459 [ 2.104107] xhci-mtk 11200000.usb: xHCI Host Controller
10595 16:54:29.449210 [ 2.109345] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10596 16:54:29.459184 [ 2.116931] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10597 16:54:29.466014 [ 2.126115] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10598 16:54:29.469265 [ 2.131944] xhci-mtk 11200000.usb: xHCI Host Controller
10599 16:54:29.479151 [ 2.137170] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10600 16:54:29.485706 [ 2.144559] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10601 16:54:29.488677 [ 2.152014] hub 1-0:1.0: USB hub found
10602 16:54:29.492420 [ 2.155779] hub 1-0:1.0: 1 port detected
10603 16:54:29.502042 [ 2.159856] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10604 16:54:29.505889 [ 2.168182] hub 2-0:1.0: USB hub found
10605 16:54:29.508516 [ 2.171938] hub 2-0:1.0: 1 port detected
10606 16:54:29.517389 [ 2.178951] mtk-msdc 11f70000.mmc: Got CD GPIO
10607 16:54:29.534885 [ 2.193061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10608 16:54:29.541456 [ 2.200835] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10609 16:54:29.551361 [ 2.208550] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10610 16:54:29.558077 [ 2.217951] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10611 16:54:29.567681 [ 2.225771] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10612 16:54:29.574281 [ 2.233552] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10613 16:54:29.581533 [ 2.241207] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10614 16:54:29.591248 [ 2.248768] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10615 16:54:29.597818 [ 2.256328] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10616 16:54:29.608534 [ 2.266685] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10617 16:54:29.615169 [ 2.274795] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10618 16:54:29.625262 [ 2.282891] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10619 16:54:29.631827 [ 2.290974] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10620 16:54:29.642290 [ 2.299055] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10621 16:54:29.648751 [ 2.307138] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10622 16:54:29.655370 [ 2.315220] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10623 16:54:29.665169 [ 2.323303] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10624 16:54:29.671751 [ 2.331386] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10625 16:54:29.681860 [ 2.339468] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10626 16:54:29.688456 [ 2.347550] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10627 16:54:29.698509 [ 2.355634] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10628 16:54:29.705449 [ 2.363717] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10629 16:54:29.711865 [ 2.371800] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10630 16:54:29.722164 [ 2.379889] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10631 16:54:29.728517 [ 2.388534] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10632 16:54:29.735180 [ 2.395751] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10633 16:54:29.741973 [ 2.402606] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10634 16:54:29.748571 [ 2.409501] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10635 16:54:29.755230 [ 2.416605] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10636 16:54:29.765443 [ 2.423310] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10637 16:54:29.775301 [ 2.432194] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10638 16:54:29.781776 [ 2.441061] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10639 16:54:29.791966 [ 2.450102] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10640 16:54:29.801963 [ 2.459323] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10641 16:54:29.811784 [ 2.468536] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10642 16:54:29.818632 [ 2.477403] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10643 16:54:29.828769 [ 2.486616] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10644 16:54:29.838501 [ 2.495483] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10645 16:54:29.848251 [ 2.504524] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10646 16:54:29.858578 [ 2.514430] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10647 16:54:29.868143 [ 2.525537] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10648 16:54:29.874717 [ 2.535200] Trying to probe devices needed for running init ...
10649 16:54:29.918149 [ 2.579849] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10650 16:54:30.074245 [ 2.735757] hub 1-1:1.0: USB hub found
10651 16:54:30.077319 [ 2.739826] hub 1-1:1.0: 4 ports detected
10652 16:54:30.198267 [ 2.860226] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10653 16:54:30.228309 [ 2.890234] hub 2-1:1.0: USB hub found
10654 16:54:30.231528 [ 2.894467] hub 2-1:1.0: 3 ports detected
10655 16:54:30.397613 [ 3.055874] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10656 16:54:30.530260 [ 3.191969] hub 1-1.4:1.0: USB hub found
10657 16:54:30.533924 [ 3.196357] hub 1-1.4:1.0: 2 ports detected
10658 16:54:30.609937 [ 3.271907] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10659 16:54:30.829411 [ 3.487847] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10660 16:54:31.012925 [ 3.671848] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10661 16:54:42.150701 [ 14.816448] ALSA device list:
10662 16:54:42.153996 [ 14.819422] No soundcards found.
10663 16:54:42.168560 [ 14.831626] Freeing unused kernel memory: 8384K
10664 16:54:42.172088 [ 14.836298] Run /init as init process
10665 16:54:42.182188 Loading, please wait...
10666 16:54:42.200601 Starting version 247.3-7+deb11u2
10667 16:54:42.519345 [ 15.178954] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10668 16:54:42.530634 [ 15.193316] remoteproc remoteproc0: scp is available
10669 16:54:42.540561 [ 15.199461] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10670 16:54:42.547328 [ 15.209081] remoteproc remoteproc0: powering up scp
10671 16:54:42.557063 [ 15.214042] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10672 16:54:42.564298 [ 15.218430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 16:54:42.570552 [ 15.223628] remoteproc remoteproc0: request_firmware failed: -2
10674 16:54:42.577284 [ 15.237922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 16:54:42.586911 [ 15.246022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 16:54:42.613016 [ 15.272657] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10677 16:54:42.619605 [ 15.280031] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10678 16:54:42.629379 [ 15.288473] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10679 16:54:42.635983 [ 15.297617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 16:54:42.642614 [ 15.302046] mc: Linux media interface: v0.10
10681 16:54:42.649545 [ 15.305548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 16:54:42.656186 [ 15.311786] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10683 16:54:42.662462 [ 15.317502] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10684 16:54:42.672462 [ 15.317582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 16:54:42.678998 [ 15.317593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 16:54:42.685472 [ 15.317600] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 16:54:42.695925 [ 15.319865] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10688 16:54:42.703215 [ 15.323011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 16:54:42.709838 [ 15.326890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 16:54:42.719572 [ 15.342122] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10691 16:54:42.723312 [ 15.342122] Fallback method does not support PEC.
10692 16:54:42.730367 [ 15.343946] usbcore: registered new interface driver r8152
10693 16:54:42.736778 [ 15.347748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 16:54:42.743583 [ 15.347757] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 16:54:42.750454 [ 15.366155] videodev: Linux video capture interface: v2.00
10696 16:54:42.756688 [ 15.370633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 16:54:42.766795 [ 15.372809] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10698 16:54:42.773201 [ 15.395950] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10699 16:54:42.783166 [ 15.397009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 16:54:42.790069 [ 15.420963] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10701 16:54:42.799670 [ 15.424829] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10702 16:54:42.806453 [ 15.425171] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10703 16:54:42.816715 [ 15.425913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 16:54:42.823194 [ 15.425923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 16:54:42.829948 [ 15.428099] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10706 16:54:42.836404 [ 15.434437] pci_bus 0000:00: root bus resource [bus 00-ff]
10707 16:54:42.843296 [ 15.442952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 16:54:42.852994 [ 15.448805] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10709 16:54:42.859769 [ 15.450772] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10710 16:54:42.869661 [ 15.452032] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10711 16:54:42.876443 [ 15.452054] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10712 16:54:42.883079 [ 15.457432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 16:54:42.893388 [ 15.467203] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10714 16:54:42.899436 [ 15.467276] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10715 16:54:42.905970 [ 15.476623] usbcore: registered new interface driver cdc_ether
10716 16:54:42.912575 [ 15.483916] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10717 16:54:42.919849 [ 15.498892] usbcore: registered new interface driver r8153_ecm
10718 16:54:42.923202 [ 15.504473] r8152 2-1.3:1.0 eth0: v1.12.13
10719 16:54:42.925875 [ 15.504739] pci 0000:00:00.0: supports D1 D2
10720 16:54:42.932557 [ 15.504753] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10721 16:54:42.942801 [ 15.507469] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10722 16:54:42.949643 [ 15.507577] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10723 16:54:42.956064 [ 15.507622] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10724 16:54:42.962133 [ 15.507643] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10725 16:54:42.968932 [ 15.507661] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10726 16:54:42.972524 [ 15.507772] pci 0000:01:00.0: supports D1 D2
10727 16:54:42.978888 [ 15.507776] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10728 16:54:42.982244 [ 15.510450] Bluetooth: Core ver 2.22
10729 16:54:42.988788 [ 15.510521] NET: Registered PF_BLUETOOTH protocol family
10730 16:54:42.995281 [ 15.510524] Bluetooth: HCI device and connection manager initialized
10731 16:54:42.999051 [ 15.510539] Bluetooth: HCI socket layer initialized
10732 16:54:43.005262 [ 15.510544] Bluetooth: L2CAP socket layer initialized
10733 16:54:43.009125 [ 15.510554] Bluetooth: SCO socket layer initialized
10734 16:54:43.015545 [ 15.522325] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10735 16:54:43.022249 [ 15.523677] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10736 16:54:43.031621 [ 15.523712] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10737 16:54:43.038290 [ 15.523720] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10738 16:54:43.048420 [ 15.523734] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10739 16:54:43.055025 [ 15.523750] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10740 16:54:43.061881 [ 15.523766] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10741 16:54:43.068364 [ 15.523781] pci 0000:00:00.0: PCI bridge to [bus 01]
10742 16:54:43.075107 [ 15.523789] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10743 16:54:43.081444 [ 15.523943] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10744 16:54:43.088284 [ 15.524778] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10745 16:54:43.091696 [ 15.524987] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10746 16:54:43.098256 [ 15.537036] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10747 16:54:43.111536 [ 15.545960] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10748 16:54:43.117973 [ 15.553692] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10749 16:54:43.121280 [ 15.562364] usbcore: registered new interface driver uvcvideo
10750 16:54:43.127776 [ 15.568887] usbcore: registered new interface driver btusb
10751 16:54:43.138208 [ 15.569608] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10752 16:54:43.144633 [ 15.569619] Bluetooth: hci0: Failed to load firmware file (-2)
10753 16:54:43.151440 [ 15.569624] Bluetooth: hci0: Failed to set up firmware (-2)
10754 16:54:43.160985 [ 15.569629] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10755 16:54:43.177405 [ 15.837549] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10756 16:54:43.193934 [ 15.857188] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10757 16:54:43.204325 [ 15.863883] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10758 16:54:43.210261 [ 15.872513] cfg80211: failed to load regulatory.db
10759 16:54:43.254462 [ 15.914086] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10760 16:54:43.257412 [ 15.921340] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10761 16:54:43.284220 [ 15.947804] mt7921e 0000:01:00.0: ASIC revision: 79610010
10762 16:54:43.390443 [ 16.047182] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10763 16:54:43.394026 Begin: Loading essential drivers ... done.
10764 16:54:43.397060 Begin: Running /scripts/init-premount ... done.
10765 16:54:43.403916 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10766 16:54:43.413670 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10767 16:54:43.416828 Device /sys/class/net/enx00e04c787aaa found
10768 16:54:43.416913 done.
10769 16:54:43.464572 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10770 16:54:43.509795 [ 16.166266] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 16:54:43.629032 [ 16.285498] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 16:54:43.744494 [ 16.401483] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 16:54:43.860595 [ 16.517351] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 16:54:43.976452 [ 16.633264] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 16:54:44.092274 [ 16.749280] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 16:54:44.208502 [ 16.865181] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 16:54:44.324239 [ 16.981170] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 16:54:44.440287 [ 17.097044] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 16:54:44.484806 [ 17.148213] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10780 16:54:44.547707 [ 17.211083] mt7921e 0000:01:00.0: hardware init failed
10781 16:54:44.642407 IP-Config: no response after 2 secs - giving up
10782 16:54:44.676032 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10783 16:54:44.682215 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10784 16:54:44.688936 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10785 16:54:44.695815 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10786 16:54:44.702076 host : mt8192-asurada-spherion-r0-cbg-0
10787 16:54:44.708900 domain : lava-rack
10788 16:54:44.712055 rootserver: 192.168.201.1 rootpath:
10789 16:54:44.715256 filename :
10790 16:54:44.732182 done.
10791 16:54:44.740218 Begin: Running /scripts/nfs-bottom ... done.
10792 16:54:44.757157 Begin: Running /scripts/init-bottom ... done.
10793 16:54:45.893300 [ 18.556871] NET: Registered PF_INET6 protocol family
10794 16:54:45.900086 [ 18.563544] Segment Routing with IPv6
10795 16:54:45.903196 [ 18.567243] In-situ OAM (IOAM) with IPv6
10796 16:54:46.010833 [ 18.657863] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10797 16:54:46.017906 [ 18.681317] systemd[1]: Detected architecture arm64.
10798 16:54:46.036260
10799 16:54:46.039440 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10800 16:54:46.039555
10801 16:54:46.053866 [ 18.717540] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10802 16:54:46.595771 [ 19.256032] systemd[1]: Queued start job for default target Graphical Interface.
10803 16:54:46.629580 [ 19.293044] systemd[1]: Created slice system-getty.slice.
10804 16:54:46.636249 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10805 16:54:46.653130 [ 19.316575] systemd[1]: Created slice system-modprobe.slice.
10806 16:54:46.659924 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10807 16:54:46.677882 [ 19.341029] systemd[1]: Created slice system-serial\x2dgetty.slice.
10808 16:54:46.687832 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10809 16:54:46.702028 [ 19.364942] systemd[1]: Created slice User and Session Slice.
10810 16:54:46.708689 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10811 16:54:46.728822 [ 19.388343] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10812 16:54:46.735089 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10813 16:54:46.751804 [ 19.412048] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10814 16:54:46.758451 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10815 16:54:46.779240 [ 19.436005] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10816 16:54:46.785893 [ 19.447717] systemd[1]: Reached target Local Encrypted Volumes.
10817 16:54:46.792571 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10818 16:54:46.804700 [ 19.468234] systemd[1]: Reached target Paths.
10819 16:54:46.807919 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10820 16:54:46.824293 [ 19.487928] systemd[1]: Reached target Remote File Systems.
10821 16:54:46.830797 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10822 16:54:46.844134 [ 19.507928] systemd[1]: Reached target Slices.
10823 16:54:46.847809 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10824 16:54:46.864192 [ 19.527934] systemd[1]: Reached target Swap.
10825 16:54:46.867303 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10826 16:54:46.884314 [ 19.548189] systemd[1]: Listening on initctl Compatibility Named Pipe.
10827 16:54:46.894801 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10828 16:54:46.901459 [ 19.563306] systemd[1]: Listening on Journal Audit Socket.
10829 16:54:46.907456 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10830 16:54:46.921507 [ 19.584918] systemd[1]: Listening on Journal Socket (/dev/log).
10831 16:54:46.928003 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10832 16:54:46.944978 [ 19.608744] systemd[1]: Listening on Journal Socket.
10833 16:54:46.951588 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10834 16:54:46.965693 [ 19.629198] systemd[1]: Listening on Network Service Netlink Socket.
10835 16:54:46.975499 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10836 16:54:46.990850 [ 19.654272] systemd[1]: Listening on udev Control Socket.
10837 16:54:46.996967 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10838 16:54:47.012499 [ 19.676136] systemd[1]: Listening on udev Kernel Socket.
10839 16:54:47.019159 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10840 16:54:47.068529 [ 19.732284] systemd[1]: Mounting Huge Pages File System...
10841 16:54:47.075102 Mounting [0;1;39mHuge Pages File System[0m...
10842 16:54:47.090545 [ 19.754316] systemd[1]: Mounting POSIX Message Queue File System...
10843 16:54:47.097149 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10844 16:54:47.115030 [ 19.778525] systemd[1]: Mounting Kernel Debug File System...
10845 16:54:47.121409 Mounting [0;1;39mKernel Debug File System[0m...
10846 16:54:47.140000 [ 19.800135] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10847 16:54:47.153214 [ 19.813709] systemd[1]: Starting Create list of static device nodes for the current kernel...
10848 16:54:47.160295 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10849 16:54:47.179242 [ 19.842714] systemd[1]: Starting Load Kernel Module configfs...
10850 16:54:47.185360 Starting [0;1;39mLoad Kernel Module configfs[0m...
10851 16:54:47.240932 [ 19.904446] systemd[1]: Starting Load Kernel Module drm...
10852 16:54:47.247335 Starting [0;1;39mLoad Kernel Module drm[0m...
10853 16:54:47.263078 [ 19.926826] systemd[1]: Starting Load Kernel Module fuse...
10854 16:54:47.269857 Starting [0;1;39mLoad Kernel Module fuse[0m...
10855 16:54:47.306729 [ 19.967295] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10856 16:54:47.309885 [ 19.967663] fuse: init (API version 7.37)
10857 16:54:47.332373 [ 19.996323] systemd[1]: Starting Journal Service...
10858 16:54:47.336204 Starting [0;1;39mJournal Service[0m...
10859 16:54:47.358863 [ 20.022300] systemd[1]: Starting Load Kernel Modules...
10860 16:54:47.365471 Starting [0;1;39mLoad Kernel Modules[0m...
10861 16:54:47.386450 [ 20.046925] systemd[1]: Starting Remount Root and Kernel File Systems...
10862 16:54:47.389487 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10863 16:54:47.407787 [ 20.071219] systemd[1]: Starting Coldplug All udev Devices...
10864 16:54:47.414103 Starting [0;1;39mColdplug All udev Devices[0m...
10865 16:54:47.435758 [ 20.099461] systemd[1]: Mounted Huge Pages File System.
10866 16:54:47.442250 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10867 16:54:47.456463 [ 20.120289] systemd[1]: Mounted POSIX Message Queue File System.
10868 16:54:47.462947 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10869 16:54:47.480426 [ 20.144314] systemd[1]: Mounted Kernel Debug File System.
10870 16:54:47.487247 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10871 16:54:47.497771 [ 20.156811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 16:54:47.507431 [ 20.166500] systemd[1]: Finished Create list of static device nodes for the current kernel.
10873 16:54:47.514052 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10874 16:54:47.525335 [ 20.185654] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 16:54:47.532870 [ 20.196788] systemd[1]: modprobe@configfs.service: Succeeded.
10876 16:54:47.539400 [ 20.203124] systemd[1]: Finished Load Kernel Module configfs.
10877 16:54:47.545947 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10878 16:54:47.561303 [ 20.224901] systemd[1]: modprobe@drm.service: Succeeded.
10879 16:54:47.568582 [ 20.231153] systemd[1]: Finished Load Kernel Module drm.
10880 16:54:47.575176 [ 20.232218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 16:54:47.581727 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10882 16:54:47.597756 [ 20.260873] systemd[1]: modprobe@fuse.service: Succeeded.
10883 16:54:47.607533 [ 20.266181] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 16:54:47.610576 [ 20.266837] systemd[1]: Finished Load Kernel Module fuse.
10885 16:54:47.617179 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10886 16:54:47.635202 [ 20.295771] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 16:54:47.641954 [ 20.305751] systemd[1]: Finished Load Kernel Modules.
10888 16:54:47.648541 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10889 16:54:47.662116 [ 20.325196] systemd[1]: Finished Remount Root and Kernel File Systems.
10890 16:54:47.671813 [ 20.327511] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 16:54:47.678506 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10892 16:54:47.702873 [ 20.362917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 16:54:47.709157 [ 20.372482] systemd[1]: Mounting FUSE Control File System...
10894 16:54:47.715692 Mounting [0;1;39mFUSE Control File System[0m...
10895 16:54:47.732931 [ 20.393437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 16:54:47.739764 [ 20.394270] systemd[1]: Mounting Kernel Configuration File System...
10897 16:54:47.746495 Mounting [0;1;39mKernel Configuration File System[0m...
10898 16:54:47.762252 [ 20.422964] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 16:54:47.775970 [ 20.436395] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10900 16:54:47.786855 [ 20.445041] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10901 16:54:47.793279 [ 20.451983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 16:54:47.816740 [ 20.480502] systemd[1]: Starting Load/Save Random Seed...
10903 16:54:47.827065 [ 20.485680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 16:54:47.830050 Starting [0;1;39mLoad/Save Random Seed[0m...
10905 16:54:47.847672 [ 20.510984] systemd[1]: Starting Apply Kernel Variables...
10906 16:54:47.857431 Startin[ 20.517034] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 16:54:47.860755 g [0;1;39mApply Kernel Variables[0m...
10908 16:54:47.890153 [ 20.550673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 16:54:47.897134 [ 20.560499] systemd[1]: Starting Create System Users...
10910 16:54:47.903519 Starting [0;1;39mCreate System Users[0m...
10911 16:54:47.921085 [ 20.581387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 16:54:47.931177 [ 20.594839] systemd[1]: Mounted FUSE Control File System.
10913 16:54:47.937831 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10914 16:54:47.951853 [ 20.611973] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 16:54:47.958016 [ 20.621310] systemd[1]: Mounted Kernel Configuration File System.
10916 16:54:47.964514 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10917 16:54:47.980381 [ 20.640930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 16:54:47.986902 [ 20.650908] systemd[1]: Finished Load/Save Random Seed.
10919 16:54:47.993364 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10920 16:54:48.009173 [ 20.670047] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 16:54:48.016446 [ 20.680283] systemd[1]: Finished Apply Kernel Variables.
10922 16:54:48.022823 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10923 16:54:48.037345 [ 20.701020] systemd[1]: Finished Create System Users.
10924 16:54:48.043784 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10925 16:54:48.060521 [ 20.720653] systemd[1]: Condition check resulted in First Boot Complete being skipped.
10926 16:54:48.100681 [ 20.764442] systemd[1]: Starting Create Static Device Nodes in /dev...
10927 16:54:48.107719 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10928 16:54:48.132763 [ 20.786869] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10929 16:54:48.142843 [ 20.802779] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10930 16:54:48.145890 [ 20.803083] systemd[1]: Started Journal Service.
10931 16:54:48.152481 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10932 16:54:48.170875 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10933 16:54:48.184289 See 'systemctl status systemd-udev-trigger.service' for details.
10934 16:54:48.204149 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10935 16:54:48.216930 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10936 16:54:48.232233 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10937 16:54:48.276941 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10938 16:54:48.300434 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10939 16:54:48.323831 [ 20.984197] systemd-journald[302]: Received client request to flush runtime journal.
10940 16:54:49.710783 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10941 16:54:49.756618 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10942 16:54:49.776079 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10943 16:54:49.801418 Starting [0;1;39mNetwork Service[0m...
10944 16:54:50.120509 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10945 16:54:50.167663 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10946 16:54:50.193183 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10947 16:54:50.356992 [ 23.021169] remoteproc remoteproc0: powering up scp
10948 16:54:50.388393 [ 23.049249] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10949 16:54:50.395282 [ 23.058945] remoteproc remoteproc0: request_firmware failed: -2
10950 16:54:50.401576 [ 23.064916] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10951 16:54:50.523176 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10952 16:54:50.536288 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10953 16:54:50.573674 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10954 16:54:50.614383 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10955 16:54:50.631355 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10956 16:54:50.684427 Starting [0;1;39mNetwork Name Resolution[0m...
10957 16:54:50.708386 Starting [0;1;39mNetwork Time Synchronization[0m...
10958 16:54:50.726398 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10959 16:54:50.748362 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10960 16:54:50.776871 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10961 16:54:50.792393 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10962 16:54:51.154589 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10963 16:54:51.172379 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10964 16:54:51.191018 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10965 16:54:51.207747 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10966 16:54:51.227893 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10967 16:54:51.269185 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10968 16:54:51.293919 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10969 16:54:51.313328 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10970 16:54:51.333278 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10971 16:54:51.347922 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10972 16:54:51.368872 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10973 16:54:51.379686 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10974 16:54:51.395566 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10975 16:54:51.440514 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10976 16:54:51.535576 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10977 16:54:51.572099 Starting [0;1;39mUser Login Management[0m...
10978 16:54:51.588629 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10979 16:54:51.604752 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10980 16:54:51.622991 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10981 16:54:51.672491 Starting [0;1;39mPermit User Sessions[0m...
10982 16:54:51.775742 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10983 16:54:51.809062 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10984 16:54:51.845839 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10985 16:54:51.863483 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10986 16:54:51.888813 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10987 16:54:51.905392 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10988 16:54:51.924716 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10989 16:54:51.939493 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10990 16:54:51.991574 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10991 16:54:52.029849 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10992 16:54:52.137873
10993 16:54:52.138013
10994 16:54:52.140958 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10995 16:54:52.141064
10996 16:54:52.144109 debian-bullseye-arm64 login: root (automatic login)
10997 16:54:52.144219
10998 16:54:52.144313
10999 16:54:52.435401 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023 aarch64
11000 16:54:52.435572
11001 16:54:52.442380 The programs included with the Debian GNU/Linux system are free software;
11002 16:54:52.448492 the exact distribution terms for each program are described in the
11003 16:54:52.452287 individual files in /usr/share/doc/*/copyright.
11004 16:54:52.452411
11005 16:54:52.458946 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11006 16:54:52.459126 permitted by applicable law.
11007 16:54:53.224117 Matched prompt #10: / #
11009 16:54:53.224397 Setting prompt string to ['/ #']
11010 16:54:53.224496 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11012 16:54:53.224699 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11013 16:54:53.224792 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
11014 16:54:53.224868 Setting prompt string to ['/ #']
11015 16:54:53.224931 Forcing a shell prompt, looking for ['/ #']
11017 16:54:53.275156 / #
11018 16:54:53.275304 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11019 16:54:53.275401 Waiting using forced prompt support (timeout 00:02:30)
11020 16:54:53.280098
11021 16:54:53.280390 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11022 16:54:53.280486 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11024 16:54:53.380827 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576315/extract-nfsrootfs-ku2096k5'
11025 16:54:53.386335 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576315/extract-nfsrootfs-ku2096k5'
11027 16:54:53.486977 / # export NFS_SERVER_IP='192.168.201.1'
11028 16:54:53.491976 export NFS_SERVER_IP='192.168.201.1'
11029 16:54:53.492282 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11030 16:54:53.492392 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11031 16:54:53.492487 end: 2 depthcharge-action (duration 00:01:30) [common]
11032 16:54:53.492608 start: 3 lava-test-retry (timeout 00:07:50) [common]
11033 16:54:53.492699 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11034 16:54:53.492779 Using namespace: common
11036 16:54:53.593103 / # #
11037 16:54:53.593302 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11038 16:54:53.598150 #
11039 16:54:53.598413 Using /lava-10576315
11041 16:54:53.698745 / # export SHELL=/bin/bash
11042 16:54:53.704033 export SHELL=/bin/bash
11044 16:54:53.804583 / # . /lava-10576315/environment
11045 16:54:53.809655 . /lava-10576315/environment
11047 16:54:53.913342 / # /lava-10576315/bin/lava-test-runner /lava-10576315/0
11048 16:54:53.913515 Test shell timeout: 10s (minimum of the action and connection timeout)
11049 16:54:53.918396 /lava-10576315/bin/lava-test-runner /lava-10576315/0
11050 16:54:54.153335 + export TESTRUN_ID=0_timesync-off
11051 16:54:54.156372 + TESTRUN_ID=0_timesync-off
11052 16:54:54.159919 + cd /lava-10576315/0/tests/0_timesync-off
11053 16:54:54.163426 ++ cat uuid
11054 16:54:54.163518 + UUID=10576315_1.6.2.3.1
11055 16:54:54.166448 + set +x
11056 16:54:54.169651 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10576315_1.6.2.3.1>
11057 16:54:54.169918 Received signal: <STARTRUN> 0_timesync-off 10576315_1.6.2.3.1
11058 16:54:54.169995 Starting test lava.0_timesync-off (10576315_1.6.2.3.1)
11059 16:54:54.170081 Skipping test definition patterns.
11060 16:54:54.172780 + systemctl stop systemd-timesyncd
11061 16:54:54.202360 + set +x
11062 16:54:54.205448 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10576315_1.6.2.3.1>
11063 16:54:54.205745 Received signal: <ENDRUN> 0_timesync-off 10576315_1.6.2.3.1
11064 16:54:54.205836 Ending use of test pattern.
11065 16:54:54.205901 Ending test lava.0_timesync-off (10576315_1.6.2.3.1), duration 0.04
11067 16:54:54.276333 + export TESTRUN_ID=1_kselftest-rtc
11068 16:54:54.279429 + TESTRUN_ID=1_kselftest-rtc
11069 16:54:54.283339 + cd /lava-10576315/0/tests/1_kselftest-rtc
11070 16:54:54.286540 ++ cat uuid
11071 16:54:54.289832 + UUID=10576315_1.6.2.3.5
11072 16:54:54.289931 + set +x
11073 16:54:54.296134 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10576315_1.6.2.3.5>
11074 16:54:54.296395 Received signal: <STARTRUN> 1_kselftest-rtc 10576315_1.6.2.3.5
11075 16:54:54.296497 Starting test lava.1_kselftest-rtc (10576315_1.6.2.3.5)
11076 16:54:54.296602 Skipping test definition patterns.
11077 16:54:54.299765 + cd ./automated/linux/kselftest/
11078 16:54:54.326165 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11079 16:54:54.353641 INFO: install_deps skipped
11080 16:54:54.496915 --2023-06-03 16:54:54-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11081 16:54:54.505909 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11082 16:54:54.648871 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11083 16:54:54.791282 HTTP request sent, awaiting response... 200 OK
11084 16:54:54.794891 Length: 2713064 (2.6M) [application/octet-stream]
11085 16:54:54.797716 Saving to: 'kselftest.tar.xz'
11086 16:54:54.797802
11087 16:54:54.797870
11088 16:54:55.079926 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11089 16:54:55.364415 kselftest.tar.xz 1%[ ] 49.22K 171KB/s
11090 16:54:55.699034 kselftest.tar.xz 8%[> ] 218.91K 382KB/s
11091 16:54:55.937093 kselftest.tar.xz 31%[=====> ] 825.54K 910KB/s
11092 16:54:56.080461 kselftest.tar.xz 77%[==============> ] 2.00M 1.75MB/s
11093 16:54:56.086767 kselftest.tar.xz 100%[===================>] 2.59M 2.01MB/s in 1.3s
11094 16:54:56.086863
11095 16:54:56.328014 2023-06-03 16:54:56 (2.01 MB/s) - 'kselftest.tar.xz' saved [2713064/2713064]
11096 16:54:56.328184
11097 16:55:01.174512 skiplist:
11098 16:55:01.177549 ========================================
11099 16:55:01.180578 ========================================
11100 16:55:01.218472 rtc:rtctest
11101 16:55:01.236210 ============== Tests to run ===============
11102 16:55:01.236353 rtc:rtctest
11103 16:55:01.239408 ===========End Tests to run ===============
11104 16:55:01.326448 [ 33.991752] kselftest: Running tests in rtc
11105 16:55:01.334868 TAP version 13
11106 16:55:01.350072 1..1
11107 16:55:01.376082 # selftests: rtc: rtctest
11108 16:55:01.729024 # TAP version 13
11109 16:55:01.729169 # 1..8
11110 16:55:01.732165 # # Starting 8 tests from 2 test cases.
11111 16:55:01.735847 # # RUN rtc.date_read ...
11112 16:55:01.742849 # # rtctest.c:49:date_read:Current RTC date/time is 03/06/2023 16:55:01.
11113 16:55:01.745963 # # OK rtc.date_read
11114 16:55:01.749152 # ok 1 rtc.date_read
11115 16:55:01.752361 # # RUN rtc.date_read_loop ...
11116 16:55:01.761980 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11117 16:55:13.363285 [ 46.033292] vpu: disabling
11118 16:55:13.366520 [ 46.036095] vproc2: disabling
11119 16:55:13.370088 [ 46.039105] vproc1: disabling
11120 16:55:13.373295 [ 46.042109] vaud18: disabling
11121 16:55:13.376518 [ 46.045253] vsram_others: disabling
11122 16:55:13.380260 [ 46.048856] va09: disabling
11123 16:55:13.383255 [ 46.051700] vsram_md: disabling
11124 16:55:13.386272 [ 46.054929] Vgpu: disabling
11125 16:55:31.647663 # # rtctest.c:115:date_read_loop:Performed 2664 RTC time reads.
11126 16:55:31.651045 # # OK rtc.date_read_loop
11127 16:55:31.654577 # ok 2 rtc.date_read_loop
11128 16:55:31.657983 # # RUN rtc.uie_read ...
11129 16:55:34.629105 # # OK rtc.uie_read
11130 16:55:34.632568 # ok 3 rtc.uie_read
11131 16:55:34.635662 # # RUN rtc.uie_select ...
11132 16:55:37.629119 # # OK rtc.uie_select
11133 16:55:37.632144 # ok 4 rtc.uie_select
11134 16:55:37.635232 # # RUN rtc.alarm_alm_set ...
11135 16:55:37.641954 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 16:55:41.
11136 16:55:37.645420 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11137 16:55:37.652423 # # alarm_alm_set: Test terminated by assertion
11138 16:55:37.655427 # # FAIL rtc.alarm_alm_set
11139 16:55:37.655513 # not ok 5 rtc.alarm_alm_set
11140 16:55:37.661880 # # RUN rtc.alarm_wkalm_set ...
11141 16:55:37.668780 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 03/06/2023 16:55:41.
11142 16:55:40.631283 # # OK rtc.alarm_wkalm_set
11143 16:55:40.631442 # ok 6 rtc.alarm_wkalm_set
11144 16:55:40.638332 # # RUN rtc.alarm_alm_set_minute ...
11145 16:55:40.641291 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 16:56:00.
11146 16:55:40.647897 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11147 16:55:40.654794 # # alarm_alm_set_minute: Test terminated by assertion
11148 16:55:40.657740 # # FAIL rtc.alarm_alm_set_minute
11149 16:55:40.661211 # not ok 7 rtc.alarm_alm_set_minute
11150 16:55:40.664211 # # RUN rtc.alarm_wkalm_set_minute ...
11151 16:55:40.670965 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 03/06/2023 16:56:00.
11152 16:55:59.629214 # # OK rtc.alarm_wkalm_set_minute
11153 16:55:59.633098 # ok 8 rtc.alarm_wkalm_set_minute
11154 16:55:59.636188 # # FAILED: 6 / 8 tests passed.
11155 16:55:59.639390 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11156 16:55:59.642241 not ok 1 selftests: rtc: rtctest # exit=1
11157 16:56:00.126981 rtc_rtctest_rtc_date_read pass
11158 16:56:00.130057 rtc_rtctest_rtc_date_read_loop pass
11159 16:56:00.133498 rtc_rtctest_rtc_uie_read pass
11160 16:56:00.137357 rtc_rtctest_rtc_uie_select pass
11161 16:56:00.140516 rtc_rtctest_rtc_alarm_alm_set fail
11162 16:56:00.143701 rtc_rtctest_rtc_alarm_wkalm_set pass
11163 16:56:00.147002 rtc_rtctest_rtc_alarm_alm_set_minute fail
11164 16:56:00.150161 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11165 16:56:00.154012 rtc_rtctest fail
11166 16:56:00.156960 + ../../utils/send-to-lava.sh ./output/result.txt
11167 16:56:00.209138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11168 16:56:00.209525 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11170 16:56:00.250826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11171 16:56:00.251139 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11173 16:56:00.283727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11174 16:56:00.283985 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11176 16:56:00.326738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11177 16:56:00.327024 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11179 16:56:00.364966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11180 16:56:00.365225 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11182 16:56:00.403496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11183 16:56:00.403777 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11185 16:56:00.437712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11186 16:56:00.438034 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11188 16:56:00.474154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11189 16:56:00.474412 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11191 16:56:00.502634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11192 16:56:00.502749 + set +x
11193 16:56:00.503026 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11195 16:56:00.509276 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10576315_1.6.2.3.5>
11196 16:56:00.509362 <LAVA_TEST_RUNNER EXIT>
11197 16:56:00.509610 Received signal: <ENDRUN> 1_kselftest-rtc 10576315_1.6.2.3.5
11198 16:56:00.509720 Ending use of test pattern.
11199 16:56:00.509821 Ending test lava.1_kselftest-rtc (10576315_1.6.2.3.5), duration 66.21
11201 16:56:00.510194 ok: lava_test_shell seems to have completed
11202 16:56:00.510436 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11203 16:56:00.510555 end: 3.1 lava-test-shell (duration 00:01:07) [common]
11204 16:56:00.510644 end: 3 lava-test-retry (duration 00:01:07) [common]
11205 16:56:00.510759 start: 4 finalize (timeout 00:06:43) [common]
11206 16:56:00.511082 start: 4.1 power-off (timeout 00:00:30) [common]
11207 16:56:00.511424 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11208 16:56:00.589578 >> Command sent successfully.
11209 16:56:00.592340 Returned 0 in 0 seconds
11210 16:56:00.692814 end: 4.1 power-off (duration 00:00:00) [common]
11212 16:56:00.693249 start: 4.2 read-feedback (timeout 00:06:43) [common]
11213 16:56:00.693657 Listened to connection for namespace 'common' for up to 1s
11214 16:56:00.694006 Listened to connection for namespace 'common' for up to 1s
11215 16:56:01.693631 Finalising connection for namespace 'common'
11216 16:56:01.693828 Disconnecting from shell: Finalise
11217 16:56:01.693931 / #
11218 16:56:01.794235 end: 4.2 read-feedback (duration 00:00:01) [common]
11219 16:56:01.794408 end: 4 finalize (duration 00:00:01) [common]
11220 16:56:01.794566 Cleaning after the job
11221 16:56:01.794730 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/ramdisk
11222 16:56:01.796970 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/kernel
11223 16:56:01.806549 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/dtb
11224 16:56:01.806790 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/nfsrootfs
11225 16:56:01.878152 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576315/tftp-deploy-hgos60m6/modules
11226 16:56:01.883837 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576315
11227 16:56:02.406135 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576315
11228 16:56:02.406324 Job finished correctly