Boot log: mt8192-asurada-spherion-r0

    1 16:43:06.778915  lava-dispatcher, installed at version: 2023.03
    2 16:43:06.779128  start: 0 validate
    3 16:43:06.779264  Start time: 2023-06-03 16:43:06.779257+00:00 (UTC)
    4 16:43:06.779397  Using caching service: 'http://localhost/cache/?uri=%s'
    5 16:43:06.779529  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
    6 16:43:07.066879  Using caching service: 'http://localhost/cache/?uri=%s'
    7 16:43:07.067128  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 16:43:07.348879  Using caching service: 'http://localhost/cache/?uri=%s'
    9 16:43:07.349708  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 16:43:26.347432  Using caching service: 'http://localhost/cache/?uri=%s'
   11 16:43:26.348098  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 16:43:26.931421  Using caching service: 'http://localhost/cache/?uri=%s'
   13 16:43:26.932056  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   14 16:43:27.234929  validate duration: 20.46
   16 16:43:27.236384  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 16:43:27.236977  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 16:43:27.237495  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 16:43:27.238170  Not decompressing ramdisk as can be used compressed.
   20 16:43:27.238791  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
   21 16:43:27.239334  saving as /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/ramdisk/initrd.cpio.gz
   22 16:43:27.239840  total size: 4665601 (4MB)
   23 16:43:36.632296  progress   0% (0MB)
   24 16:43:36.639667  progress   5% (0MB)
   25 16:43:36.646252  progress  10% (0MB)
   26 16:43:36.652836  progress  15% (0MB)
   27 16:43:36.659634  progress  20% (0MB)
   28 16:43:36.664441  progress  25% (1MB)
   29 16:43:36.668159  progress  30% (1MB)
   30 16:43:36.671356  progress  35% (1MB)
   31 16:43:36.674076  progress  40% (1MB)
   32 16:43:36.676897  progress  45% (2MB)
   33 16:43:36.679195  progress  50% (2MB)
   34 16:43:36.681296  progress  55% (2MB)
   35 16:43:36.683236  progress  60% (2MB)
   36 16:43:36.685176  progress  65% (2MB)
   37 16:43:36.686899  progress  70% (3MB)
   38 16:43:36.688584  progress  75% (3MB)
   39 16:43:36.690261  progress  80% (3MB)
   40 16:43:36.691992  progress  85% (3MB)
   41 16:43:36.693498  progress  90% (4MB)
   42 16:43:36.694997  progress  95% (4MB)
   43 16:43:36.696431  progress 100% (4MB)
   44 16:43:36.696606  4MB downloaded in 9.46s (0.47MB/s)
   45 16:43:36.696772  end: 1.1.1 http-download (duration 00:00:09) [common]
   47 16:43:36.697049  end: 1.1 download-retry (duration 00:00:09) [common]
   48 16:43:36.697156  start: 1.2 download-retry (timeout 00:09:51) [common]
   49 16:43:36.697256  start: 1.2.1 http-download (timeout 00:09:51) [common]
   50 16:43:36.697400  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   51 16:43:36.697481  saving as /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/kernel/Image
   52 16:43:36.697550  total size: 45746688 (43MB)
   53 16:43:36.697618  No compression specified
   54 16:43:36.987744  progress   0% (0MB)
   55 16:43:37.031786  progress   5% (2MB)
   56 16:43:37.049025  progress  10% (4MB)
   57 16:43:37.061502  progress  15% (6MB)
   58 16:43:37.073159  progress  20% (8MB)
   59 16:43:37.084868  progress  25% (10MB)
   60 16:43:37.096292  progress  30% (13MB)
   61 16:43:37.108066  progress  35% (15MB)
   62 16:43:37.119649  progress  40% (17MB)
   63 16:43:37.131491  progress  45% (19MB)
   64 16:43:37.143187  progress  50% (21MB)
   65 16:43:37.155163  progress  55% (24MB)
   66 16:43:37.167000  progress  60% (26MB)
   67 16:43:37.178678  progress  65% (28MB)
   68 16:43:37.190238  progress  70% (30MB)
   69 16:43:37.201940  progress  75% (32MB)
   70 16:43:37.213421  progress  80% (34MB)
   71 16:43:37.225134  progress  85% (37MB)
   72 16:43:37.236965  progress  90% (39MB)
   73 16:43:37.248570  progress  95% (41MB)
   74 16:43:37.260080  progress 100% (43MB)
   75 16:43:37.260217  43MB downloaded in 0.56s (77.54MB/s)
   76 16:43:37.260359  end: 1.2.1 http-download (duration 00:00:01) [common]
   78 16:43:37.260585  end: 1.2 download-retry (duration 00:00:01) [common]
   79 16:43:37.260675  start: 1.3 download-retry (timeout 00:09:50) [common]
   80 16:43:37.260765  start: 1.3.1 http-download (timeout 00:09:50) [common]
   81 16:43:37.260894  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   82 16:43:37.260964  saving as /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/dtb/mt8192-asurada-spherion-r0.dtb
   83 16:43:37.261025  total size: 46924 (0MB)
   84 16:43:37.261085  No compression specified
   85 16:43:37.552621  progress  69% (0MB)
   86 16:43:37.554102  progress 100% (0MB)
   87 16:43:37.554959  0MB downloaded in 0.29s (0.15MB/s)
   88 16:43:37.555696  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 16:43:37.556874  end: 1.3 download-retry (duration 00:00:00) [common]
   91 16:43:37.557325  start: 1.4 download-retry (timeout 00:09:50) [common]
   92 16:43:37.557827  start: 1.4.1 http-download (timeout 00:09:50) [common]
   93 16:43:37.558409  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
   94 16:43:37.558770  saving as /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/nfsrootfs/full.rootfs.tar
   95 16:43:37.559091  total size: 200770336 (191MB)
   96 16:43:37.559492  Using unxz to decompress xz
   97 16:43:37.867792  progress   0% (0MB)
   98 16:43:38.436350  progress   5% (9MB)
   99 16:43:38.948151  progress  10% (19MB)
  100 16:43:39.530863  progress  15% (28MB)
  101 16:43:39.896355  progress  20% (38MB)
  102 16:43:40.218371  progress  25% (47MB)
  103 16:43:40.805465  progress  30% (57MB)
  104 16:43:41.349676  progress  35% (67MB)
  105 16:43:41.928695  progress  40% (76MB)
  106 16:43:42.474941  progress  45% (86MB)
  107 16:43:43.049809  progress  50% (95MB)
  108 16:43:43.679149  progress  55% (105MB)
  109 16:43:44.338249  progress  60% (114MB)
  110 16:43:44.457725  progress  65% (124MB)
  111 16:43:44.597931  progress  70% (134MB)
  112 16:43:44.695039  progress  75% (143MB)
  113 16:43:44.768589  progress  80% (153MB)
  114 16:43:44.837361  progress  85% (162MB)
  115 16:43:44.936410  progress  90% (172MB)
  116 16:43:45.212688  progress  95% (181MB)
  117 16:43:45.780506  progress 100% (191MB)
  118 16:43:45.785205  191MB downloaded in 8.23s (23.28MB/s)
  119 16:43:45.785607  end: 1.4.1 http-download (duration 00:00:08) [common]
  121 16:43:45.785917  end: 1.4 download-retry (duration 00:00:08) [common]
  122 16:43:45.786009  start: 1.5 download-retry (timeout 00:09:41) [common]
  123 16:43:45.786100  start: 1.5.1 http-download (timeout 00:09:41) [common]
  124 16:43:45.786241  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
  125 16:43:45.786315  saving as /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/modules/modules.tar
  126 16:43:45.786377  total size: 8545664 (8MB)
  127 16:43:45.786440  Using unxz to decompress xz
  128 16:43:46.080617  progress   0% (0MB)
  129 16:43:46.137938  progress   5% (0MB)
  130 16:43:46.164189  progress  10% (0MB)
  131 16:43:46.190050  progress  15% (1MB)
  132 16:43:46.214431  progress  20% (1MB)
  133 16:43:46.239888  progress  25% (2MB)
  134 16:43:46.264910  progress  30% (2MB)
  135 16:43:46.290184  progress  35% (2MB)
  136 16:43:46.314863  progress  40% (3MB)
  137 16:43:46.339785  progress  45% (3MB)
  138 16:43:46.363528  progress  50% (4MB)
  139 16:43:46.386658  progress  55% (4MB)
  140 16:43:46.411412  progress  60% (4MB)
  141 16:43:46.436324  progress  65% (5MB)
  142 16:43:46.461398  progress  70% (5MB)
  143 16:43:46.488373  progress  75% (6MB)
  144 16:43:46.517746  progress  80% (6MB)
  145 16:43:46.539980  progress  85% (6MB)
  146 16:43:46.564764  progress  90% (7MB)
  147 16:43:46.588117  progress  95% (7MB)
  148 16:43:46.611653  progress 100% (8MB)
  149 16:43:46.617449  8MB downloaded in 0.83s (9.81MB/s)
  150 16:43:46.617762  end: 1.5.1 http-download (duration 00:00:01) [common]
  152 16:43:46.618180  end: 1.5 download-retry (duration 00:00:01) [common]
  153 16:43:46.618301  start: 1.6 prepare-tftp-overlay (timeout 00:09:41) [common]
  154 16:43:46.618458  start: 1.6.1 extract-nfsrootfs (timeout 00:09:41) [common]
  155 16:43:50.633473  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10576285/extract-nfsrootfs-7_pn6cuh
  156 16:43:50.633666  end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
  157 16:43:50.633764  start: 1.6.2 lava-overlay (timeout 00:09:37) [common]
  158 16:43:50.633981  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1
  159 16:43:50.634102  makedir: /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin
  160 16:43:50.634200  makedir: /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/tests
  161 16:43:50.634293  makedir: /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/results
  162 16:43:50.634393  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-add-keys
  163 16:43:50.634528  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-add-sources
  164 16:43:50.634650  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-background-process-start
  165 16:43:50.634771  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-background-process-stop
  166 16:43:50.634890  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-common-functions
  167 16:43:50.635007  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-echo-ipv4
  168 16:43:50.635125  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-install-packages
  169 16:43:50.635339  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-installed-packages
  170 16:43:50.635457  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-os-build
  171 16:43:50.635574  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-probe-channel
  172 16:43:50.635690  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-probe-ip
  173 16:43:50.635806  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-target-ip
  174 16:43:50.635922  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-target-mac
  175 16:43:50.636037  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-target-storage
  176 16:43:50.636155  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-test-case
  177 16:43:50.636275  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-test-event
  178 16:43:50.636391  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-test-feedback
  179 16:43:50.636509  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-test-raise
  180 16:43:50.636625  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-test-reference
  181 16:43:50.636743  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-test-runner
  182 16:43:50.636863  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-test-set
  183 16:43:50.636988  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-test-shell
  184 16:43:50.637222  Updating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-add-keys (debian)
  185 16:43:50.637404  Updating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-add-sources (debian)
  186 16:43:50.637616  Updating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-install-packages (debian)
  187 16:43:50.637756  Updating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-installed-packages (debian)
  188 16:43:50.637892  Updating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/bin/lava-os-build (debian)
  189 16:43:50.638007  Creating /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/environment
  190 16:43:50.638104  LAVA metadata
  191 16:43:50.638172  - LAVA_JOB_ID=10576285
  192 16:43:50.638234  - LAVA_DISPATCHER_IP=192.168.201.1
  193 16:43:50.638333  start: 1.6.2.1 lava-vland-overlay (timeout 00:09:37) [common]
  194 16:43:50.638398  skipped lava-vland-overlay
  195 16:43:50.638471  end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
  196 16:43:50.638549  start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:37) [common]
  197 16:43:50.638608  skipped lava-multinode-overlay
  198 16:43:50.638677  end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  199 16:43:50.638752  start: 1.6.2.3 test-definition (timeout 00:09:37) [common]
  200 16:43:50.638823  Loading test definitions
  201 16:43:50.638913  start: 1.6.2.3.1 inline-repo-action (timeout 00:09:37) [common]
  202 16:43:50.638983  Using /lava-10576285 at stage 0
  203 16:43:50.639277  uuid=10576285_1.6.2.3.1 testdef=None
  204 16:43:50.639363  end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
  205 16:43:50.639445  start: 1.6.2.3.2 test-overlay (timeout 00:09:37) [common]
  206 16:43:50.639876  end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
  208 16:43:50.640091  start: 1.6.2.3.3 test-install-overlay (timeout 00:09:37) [common]
  209 16:43:50.640836  end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
  211 16:43:50.641067  start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:37) [common]
  212 16:43:50.641612  runner path: /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/0/tests/0_timesync-off test_uuid 10576285_1.6.2.3.1
  213 16:43:50.641759  end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  215 16:43:50.641976  start: 1.6.2.3.5 git-repo-action (timeout 00:09:37) [common]
  216 16:43:50.642047  Using /lava-10576285 at stage 0
  217 16:43:50.642142  Fetching tests from https://github.com/kernelci/test-definitions.git
  218 16:43:50.642216  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/0/tests/1_kselftest-tpm2'
  219 16:43:54.063357  Running '/usr/bin/git checkout kernelci.org
  220 16:43:54.132104  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
  221 16:43:54.132835  uuid=10576285_1.6.2.3.5 testdef=None
  222 16:43:54.132991  end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
  224 16:43:54.133239  start: 1.6.2.3.6 test-overlay (timeout 00:09:33) [common]
  225 16:43:54.134457  end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
  227 16:43:54.134827  start: 1.6.2.3.7 test-install-overlay (timeout 00:09:33) [common]
  228 16:43:54.135961  end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
  230 16:43:54.136193  start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:33) [common]
  231 16:43:54.137101  runner path: /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/0/tests/1_kselftest-tpm2 test_uuid 10576285_1.6.2.3.5
  232 16:43:54.137191  BOARD='mt8192-asurada-spherion-r0'
  233 16:43:54.137256  BRANCH='cip-gitlab'
  234 16:43:54.137332  SKIPFILE='/dev/null'
  235 16:43:54.137393  SKIP_INSTALL='True'
  236 16:43:54.137449  TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
  237 16:43:54.137506  TST_CASENAME=''
  238 16:43:54.137561  TST_CMDFILES='tpm2'
  239 16:43:54.137700  end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
  241 16:43:54.137901  Creating lava-test-runner.conf files
  242 16:43:54.137964  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576285/lava-overlay-c8fkzxd1/lava-10576285/0 for stage 0
  243 16:43:54.138061  - 0_timesync-off
  244 16:43:54.138133  - 1_kselftest-tpm2
  245 16:43:54.138225  end: 1.6.2.3 test-definition (duration 00:00:03) [common]
  246 16:43:54.138313  start: 1.6.2.4 compress-overlay (timeout 00:09:33) [common]
  247 16:44:01.742001  end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
  248 16:44:01.742179  start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:25) [common]
  249 16:44:01.742286  end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  250 16:44:01.742387  end: 1.6.2 lava-overlay (duration 00:00:11) [common]
  251 16:44:01.742475  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:25) [common]
  252 16:44:01.856537  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  253 16:44:01.856910  start: 1.6.4 extract-modules (timeout 00:09:25) [common]
  254 16:44:01.857024  extracting modules file /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576285/extract-nfsrootfs-7_pn6cuh
  255 16:44:02.054925  extracting modules file /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576285/extract-overlay-ramdisk-lc6_3j03/ramdisk
  256 16:44:02.257727  end: 1.6.4 extract-modules (duration 00:00:00) [common]
  257 16:44:02.257904  start: 1.6.5 apply-overlay-tftp (timeout 00:09:25) [common]
  258 16:44:02.257999  [common] Applying overlay to NFS
  259 16:44:02.258069  [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576285/compress-overlay-0vipfu00/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576285/extract-nfsrootfs-7_pn6cuh
  260 16:44:03.137994  end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
  261 16:44:03.138164  start: 1.6.6 configure-preseed-file (timeout 00:09:24) [common]
  262 16:44:03.138262  end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
  263 16:44:03.138356  start: 1.6.7 compress-ramdisk (timeout 00:09:24) [common]
  264 16:44:03.138436  Building ramdisk /var/lib/lava/dispatcher/tmp/10576285/extract-overlay-ramdisk-lc6_3j03/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576285/extract-overlay-ramdisk-lc6_3j03/ramdisk
  265 16:44:03.422719  >> 117799 blocks

  266 16:44:05.271961  rename /var/lib/lava/dispatcher/tmp/10576285/extract-overlay-ramdisk-lc6_3j03/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/ramdisk/ramdisk.cpio.gz
  267 16:44:05.272398  end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
  268 16:44:05.272520  start: 1.6.8 prepare-kernel (timeout 00:09:22) [common]
  269 16:44:05.272668  start: 1.6.8.1 prepare-fit (timeout 00:09:22) [common]
  270 16:44:05.272811  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/kernel/Image'
  271 16:44:16.597032  Returned 0 in 11 seconds
  272 16:44:16.697927  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/kernel/image.itb
  273 16:44:17.020949  output: FIT description: Kernel Image image with one or more FDT blobs
  274 16:44:17.021304  output: Created:         Sat Jun  3 17:44:16 2023
  275 16:44:17.021382  output:  Image 0 (kernel-1)
  276 16:44:17.021452  output:   Description:  
  277 16:44:17.021515  output:   Created:      Sat Jun  3 17:44:16 2023
  278 16:44:17.021576  output:   Type:         Kernel Image
  279 16:44:17.021636  output:   Compression:  lzma compressed
  280 16:44:17.021691  output:   Data Size:    10083474 Bytes = 9847.14 KiB = 9.62 MiB
  281 16:44:17.021749  output:   Architecture: AArch64
  282 16:44:17.021806  output:   OS:           Linux
  283 16:44:17.021866  output:   Load Address: 0x00000000
  284 16:44:17.021922  output:   Entry Point:  0x00000000
  285 16:44:17.021979  output:   Hash algo:    crc32
  286 16:44:17.022031  output:   Hash value:   b48eba69
  287 16:44:17.022084  output:  Image 1 (fdt-1)
  288 16:44:17.022137  output:   Description:  mt8192-asurada-spherion-r0
  289 16:44:17.022189  output:   Created:      Sat Jun  3 17:44:16 2023
  290 16:44:17.022241  output:   Type:         Flat Device Tree
  291 16:44:17.022293  output:   Compression:  uncompressed
  292 16:44:17.022345  output:   Data Size:    46924 Bytes = 45.82 KiB = 0.04 MiB
  293 16:44:17.022398  output:   Architecture: AArch64
  294 16:44:17.022450  output:   Hash algo:    crc32
  295 16:44:17.022502  output:   Hash value:   1df858fa
  296 16:44:17.022554  output:  Image 2 (ramdisk-1)
  297 16:44:17.022606  output:   Description:  unavailable
  298 16:44:17.022658  output:   Created:      Sat Jun  3 17:44:16 2023
  299 16:44:17.022710  output:   Type:         RAMDisk Image
  300 16:44:17.022763  output:   Compression:  Unknown Compression
  301 16:44:17.022815  output:   Data Size:    17637521 Bytes = 17224.14 KiB = 16.82 MiB
  302 16:44:17.022867  output:   Architecture: AArch64
  303 16:44:17.022919  output:   OS:           Linux
  304 16:44:17.022971  output:   Load Address: unavailable
  305 16:44:17.023023  output:   Entry Point:  unavailable
  306 16:44:17.023075  output:   Hash algo:    crc32
  307 16:44:17.023127  output:   Hash value:   cb67e1a8
  308 16:44:17.023185  output:  Default Configuration: 'conf-1'
  309 16:44:17.023276  output:  Configuration 0 (conf-1)
  310 16:44:17.023328  output:   Description:  mt8192-asurada-spherion-r0
  311 16:44:17.023381  output:   Kernel:       kernel-1
  312 16:44:17.023433  output:   Init Ramdisk: ramdisk-1
  313 16:44:17.023484  output:   FDT:          fdt-1
  314 16:44:17.023536  output:   Loadables:    kernel-1
  315 16:44:17.023588  output: 
  316 16:44:17.023789  end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
  317 16:44:17.023891  end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
  318 16:44:17.023991  end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
  319 16:44:17.024089  start: 1.7 lxc-create-udev-rule-action (timeout 00:09:10) [common]
  320 16:44:17.024168  No LXC device requested
  321 16:44:17.024246  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  322 16:44:17.024334  start: 1.8 deploy-device-env (timeout 00:09:10) [common]
  323 16:44:17.024409  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  324 16:44:17.024477  Checking files for TFTP limit of 4294967296 bytes.
  325 16:44:17.024968  end: 1 tftp-deploy (duration 00:00:50) [common]
  326 16:44:17.025076  start: 2 depthcharge-action (timeout 00:05:00) [common]
  327 16:44:17.025168  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  328 16:44:17.025291  substitutions:
  329 16:44:17.025360  - {DTB}: 10576285/tftp-deploy-reorxb3r/dtb/mt8192-asurada-spherion-r0.dtb
  330 16:44:17.025426  - {INITRD}: 10576285/tftp-deploy-reorxb3r/ramdisk/ramdisk.cpio.gz
  331 16:44:17.025484  - {KERNEL}: 10576285/tftp-deploy-reorxb3r/kernel/Image
  332 16:44:17.025541  - {LAVA_MAC}: None
  333 16:44:17.025599  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10576285/extract-nfsrootfs-7_pn6cuh
  334 16:44:17.025656  - {NFS_SERVER_IP}: 192.168.201.1
  335 16:44:17.025711  - {PRESEED_CONFIG}: None
  336 16:44:17.025766  - {PRESEED_LOCAL}: None
  337 16:44:17.025820  - {RAMDISK}: 10576285/tftp-deploy-reorxb3r/ramdisk/ramdisk.cpio.gz
  338 16:44:17.025874  - {ROOT_PART}: None
  339 16:44:17.025928  - {ROOT}: None
  340 16:44:17.025983  - {SERVER_IP}: 192.168.201.1
  341 16:44:17.026036  - {TEE}: None
  342 16:44:17.026089  Parsed boot commands:
  343 16:44:17.026145  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  344 16:44:17.026319  Parsed boot commands: tftpboot 192.168.201.1 10576285/tftp-deploy-reorxb3r/kernel/image.itb 10576285/tftp-deploy-reorxb3r/kernel/cmdline 
  345 16:44:17.026408  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  346 16:44:17.026493  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  347 16:44:17.026585  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  348 16:44:17.026670  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  349 16:44:17.026739  Not connected, no need to disconnect.
  350 16:44:17.026814  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  351 16:44:17.026894  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  352 16:44:17.026962  [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
  353 16:44:17.030465  Setting prompt string to ['lava-test: # ']
  354 16:44:17.030803  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  355 16:44:17.030906  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  356 16:44:17.030999  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  357 16:44:17.031094  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  358 16:44:17.031330  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
  359 16:44:22.170375  >> Command sent successfully.

  360 16:44:22.172707  Returned 0 in 5 seconds
  361 16:44:22.273395  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  363 16:44:22.274891  end: 2.2.2 reset-device (duration 00:00:05) [common]
  364 16:44:22.275628  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  365 16:44:22.276095  Setting prompt string to 'Starting depthcharge on Spherion...'
  366 16:44:22.276457  Changing prompt to 'Starting depthcharge on Spherion...'
  367 16:44:22.276843  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  368 16:44:22.278146  [Enter `^Ec?' for help]

  369 16:44:22.448672  

  370 16:44:22.449195  

  371 16:44:22.449537  F0: 102B 0000

  372 16:44:22.449854  

  373 16:44:22.450158  F3: 1001 0000 [0200]

  374 16:44:22.452404  

  375 16:44:22.452832  F3: 1001 0000

  376 16:44:22.453174  

  377 16:44:22.453491  F7: 102D 0000

  378 16:44:22.453794  

  379 16:44:22.455311  F1: 0000 0000

  380 16:44:22.455742  

  381 16:44:22.456081  V0: 0000 0000 [0001]

  382 16:44:22.456399  

  383 16:44:22.458530  00: 0007 8000

  384 16:44:22.459000  

  385 16:44:22.459424  01: 0000 0000

  386 16:44:22.459772  

  387 16:44:22.462651  BP: 0C00 0209 [0000]

  388 16:44:22.463305  

  389 16:44:22.463675  G0: 1182 0000

  390 16:44:22.464026  

  391 16:44:22.465955  EC: 0000 0021 [4000]

  392 16:44:22.466419  

  393 16:44:22.466760  S7: 0000 0000 [0000]

  394 16:44:22.467077  

  395 16:44:22.469441  CC: 0000 0000 [0001]

  396 16:44:22.469908  

  397 16:44:22.470288  T0: 0000 0040 [010F]

  398 16:44:22.470642  

  399 16:44:22.470955  Jump to BL

  400 16:44:22.471447  

  401 16:44:22.496672  

  402 16:44:22.497117  

  403 16:44:22.497461  

  404 16:44:22.503108  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  405 16:44:22.506271  ARM64: Exception handlers installed.

  406 16:44:22.510097  ARM64: Testing exception

  407 16:44:22.513818  ARM64: Done test exception

  408 16:44:22.520147  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  409 16:44:22.530809  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  410 16:44:22.537482  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  411 16:44:22.547410  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  412 16:44:22.554127  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  413 16:44:22.560731  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  414 16:44:22.572599  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  415 16:44:22.579330  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  416 16:44:22.598574  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  417 16:44:22.601768  WDT: Last reset was cold boot

  418 16:44:22.605409  SPI1(PAD0) initialized at 2873684 Hz

  419 16:44:22.608646  SPI5(PAD0) initialized at 992727 Hz

  420 16:44:22.612134  VBOOT: Loading verstage.

  421 16:44:22.618626  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  422 16:44:22.621855  FMAP: Found "FLASH" version 1.1 at 0x20000.

  423 16:44:22.624953  FMAP: base = 0x0 size = 0x800000 #areas = 25

  424 16:44:22.628365  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  425 16:44:22.636073  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  426 16:44:22.642787  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  427 16:44:22.653701  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  428 16:44:22.654353  

  429 16:44:22.654955  

  430 16:44:22.663101  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  431 16:44:22.666500  ARM64: Exception handlers installed.

  432 16:44:22.669719  ARM64: Testing exception

  433 16:44:22.670408  ARM64: Done test exception

  434 16:44:22.677462  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  435 16:44:22.680387  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  436 16:44:22.694675  Probing TPM: . done!

  437 16:44:22.695146  TPM ready after 0 ms

  438 16:44:22.702216  Connected to device vid:did:rid of 1ae0:0028:00

  439 16:44:22.709154  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523

  440 16:44:22.766573  Initialized TPM device CR50 revision 0

  441 16:44:22.778649  tlcl_send_startup: Startup return code is 0

  442 16:44:22.779110  TPM: setup succeeded

  443 16:44:22.790171  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  444 16:44:22.798696  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  445 16:44:22.810829  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  446 16:44:22.821191  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  447 16:44:22.824492  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  448 16:44:22.828436  in-header: 03 07 00 00 08 00 00 00 

  449 16:44:22.832126  in-data: aa e4 47 04 13 02 00 00 

  450 16:44:22.836374  Chrome EC: UHEPI supported

  451 16:44:22.843753  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  452 16:44:22.846557  in-header: 03 95 00 00 08 00 00 00 

  453 16:44:22.850083  in-data: 18 20 20 08 00 00 00 00 

  454 16:44:22.850563  Phase 1

  455 16:44:22.854048  FMAP: area GBB found @ 3f5000 (12032 bytes)

  456 16:44:22.861740  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  457 16:44:22.865017  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  458 16:44:22.868133  Recovery requested (1009000e)

  459 16:44:22.875638  TPM: Extending digest for VBOOT: boot mode into PCR 0

  460 16:44:22.881582  tlcl_extend: response is 0

  461 16:44:22.891931  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  462 16:44:22.895505  tlcl_extend: response is 0

  463 16:44:22.901835  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  464 16:44:22.922330  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  465 16:44:22.928994  BS: bootblock times (exec / console): total (unknown) / 148 ms

  466 16:44:22.929541  

  467 16:44:22.929891  

  468 16:44:22.938822  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  469 16:44:22.941689  ARM64: Exception handlers installed.

  470 16:44:22.945097  ARM64: Testing exception

  471 16:44:22.945535  ARM64: Done test exception

  472 16:44:22.968165  pmic_efuse_setting: Set efuses in 11 msecs

  473 16:44:22.971053  pmwrap_interface_init: Select PMIF_VLD_RDY

  474 16:44:22.977436  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  475 16:44:22.981009  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  476 16:44:22.987463  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  477 16:44:22.990972  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  478 16:44:22.994587  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  479 16:44:23.001885  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  480 16:44:23.004993  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  481 16:44:23.008866  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  482 16:44:23.016531  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  483 16:44:23.020138  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  484 16:44:23.023757  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  485 16:44:23.027375  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  486 16:44:23.035330  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  487 16:44:23.038624  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  488 16:44:23.046283  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  489 16:44:23.049574  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  490 16:44:23.057041  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  491 16:44:23.064072  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  492 16:44:23.067691  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  493 16:44:23.074768  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  494 16:44:23.078209  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  495 16:44:23.085281  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  496 16:44:23.089065  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  497 16:44:23.096258  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  498 16:44:23.099854  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  499 16:44:23.107023  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  500 16:44:23.111430  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  501 16:44:23.118372  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  502 16:44:23.121628  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  503 16:44:23.125574  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  504 16:44:23.132334  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  505 16:44:23.135620  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  506 16:44:23.143081  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  507 16:44:23.146294  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  508 16:44:23.149924  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  509 16:44:23.157424  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  510 16:44:23.161301  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  511 16:44:23.164731  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  512 16:44:23.172440  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  513 16:44:23.175856  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  514 16:44:23.179302  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  515 16:44:23.182870  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  516 16:44:23.189867  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  517 16:44:23.193863  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  518 16:44:23.197139  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  519 16:44:23.200832  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  520 16:44:23.205232  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  521 16:44:23.208819  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  522 16:44:23.215410  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  523 16:44:23.219332  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  524 16:44:23.222782  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  525 16:44:23.230717  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  526 16:44:23.237771  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  527 16:44:23.245074  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  528 16:44:23.252094  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  529 16:44:23.259322  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  530 16:44:23.263584  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  531 16:44:23.267419  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  532 16:44:23.275036  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  533 16:44:23.281764  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0

  534 16:44:23.285125  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  535 16:44:23.292080  [RTC]rtc_osc_init,62: osc32con val = 0xde6b

  536 16:44:23.295251  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  537 16:44:23.305189  [RTC]rtc_get_frequency_meter,154: input=15, output=853

  538 16:44:23.315121  [RTC]rtc_get_frequency_meter,154: input=7, output=725

  539 16:44:23.323942  [RTC]rtc_get_frequency_meter,154: input=11, output=789

  540 16:44:23.333372  [RTC]rtc_get_frequency_meter,154: input=13, output=821

  541 16:44:23.342513  [RTC]rtc_get_frequency_meter,154: input=12, output=804

  542 16:44:23.352580  [RTC]rtc_get_frequency_meter,154: input=11, output=789

  543 16:44:23.363118  [RTC]rtc_get_frequency_meter,154: input=12, output=805

  544 16:44:23.366389  [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12

  545 16:44:23.370278  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b

  546 16:44:23.373338  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  547 16:44:23.380363  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  548 16:44:23.383950  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  549 16:44:23.388190  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  550 16:44:23.390846  ADC[4]: Raw value=904433 ID=7

  551 16:44:23.395033  ADC[3]: Raw value=213916 ID=1

  552 16:44:23.395199  RAM Code: 0x71

  553 16:44:23.398479  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  554 16:44:23.406416  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  555 16:44:23.413413  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  556 16:44:23.420738  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  557 16:44:23.424230  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  558 16:44:23.428113  in-header: 03 07 00 00 08 00 00 00 

  559 16:44:23.432086  in-data: aa e4 47 04 13 02 00 00 

  560 16:44:23.432354  Chrome EC: UHEPI supported

  561 16:44:23.438474  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  562 16:44:23.442903  in-header: 03 95 00 00 08 00 00 00 

  563 16:44:23.446202  in-data: 18 20 20 08 00 00 00 00 

  564 16:44:23.450225  MRC: failed to locate region type 0.

  565 16:44:23.457638  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  566 16:44:23.457908  DRAM-K: Running full calibration

  567 16:44:23.464595  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  568 16:44:23.468243  header.status = 0x0

  569 16:44:23.468595  header.version = 0x6 (expected: 0x6)

  570 16:44:23.472562  header.size = 0xd00 (expected: 0xd00)

  571 16:44:23.475693  header.flags = 0x0

  572 16:44:23.482493  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  573 16:44:23.499916  read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps

  574 16:44:23.507349  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  575 16:44:23.507805  dram_init: ddr_geometry: 2

  576 16:44:23.510519  [EMI] MDL number = 2

  577 16:44:23.514037  [EMI] Get MDL freq = 0

  578 16:44:23.514471  dram_init: ddr_type: 0

  579 16:44:23.517728  is_discrete_lpddr4: 1

  580 16:44:23.521246  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  581 16:44:23.521590  

  582 16:44:23.521929  

  583 16:44:23.522232  [Bian_co] ETT version 0.0.0.1

  584 16:44:23.528695   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  585 16:44:23.529057  

  586 16:44:23.532248  dramc_set_vcore_voltage set vcore to 650000

  587 16:44:23.532688  Read voltage for 800, 4

  588 16:44:23.536115  Vio18 = 0

  589 16:44:23.536458  Vcore = 650000

  590 16:44:23.536763  Vdram = 0

  591 16:44:23.537061  Vddq = 0

  592 16:44:23.541049  Vmddr = 0

  593 16:44:23.541394  dram_init: config_dvfs: 1

  594 16:44:23.546923  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  595 16:44:23.550246  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  596 16:44:23.553443  [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9

  597 16:44:23.559933  freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9

  598 16:44:23.563325  [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9

  599 16:44:23.566920  freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9

  600 16:44:23.570418  MEM_TYPE=3, freq_sel=18

  601 16:44:23.570773  sv_algorithm_assistance_LP4_1600 

  602 16:44:23.577580  ============ PULL DRAM RESETB DOWN ============

  603 16:44:23.581274  ========== PULL DRAM RESETB DOWN end =========

  604 16:44:23.584554  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  605 16:44:23.588389  =================================== 

  606 16:44:23.591222  LPDDR4 DRAM CONFIGURATION

  607 16:44:23.595233  =================================== 

  608 16:44:23.595351  EX_ROW_EN[0]    = 0x0

  609 16:44:23.598027  EX_ROW_EN[1]    = 0x0

  610 16:44:23.598139  LP4Y_EN      = 0x0

  611 16:44:23.601359  WORK_FSP     = 0x0

  612 16:44:23.601468  WL           = 0x2

  613 16:44:23.604803  RL           = 0x2

  614 16:44:23.604916  BL           = 0x2

  615 16:44:23.608480  RPST         = 0x0

  616 16:44:23.608593  RD_PRE       = 0x0

  617 16:44:23.611572  WR_PRE       = 0x1

  618 16:44:23.611690  WR_PST       = 0x0

  619 16:44:23.614769  DBI_WR       = 0x0

  620 16:44:23.614882  DBI_RD       = 0x0

  621 16:44:23.617808  OTF          = 0x1

  622 16:44:23.621646  =================================== 

  623 16:44:23.624578  =================================== 

  624 16:44:23.624725  ANA top config

  625 16:44:23.628511  =================================== 

  626 16:44:23.631084  DLL_ASYNC_EN            =  0

  627 16:44:23.634428  ALL_SLAVE_EN            =  1

  628 16:44:23.637905  NEW_RANK_MODE           =  1

  629 16:44:23.641497  DLL_IDLE_MODE           =  1

  630 16:44:23.641600  LP45_APHY_COMB_EN       =  1

  631 16:44:23.644967  TX_ODT_DIS              =  1

  632 16:44:23.648342  NEW_8X_MODE             =  1

  633 16:44:23.652181  =================================== 

  634 16:44:23.654694  =================================== 

  635 16:44:23.658117  data_rate                  = 1600

  636 16:44:23.661104  CKR                        = 1

  637 16:44:23.661647  DQ_P2S_RATIO               = 8

  638 16:44:23.665195  =================================== 

  639 16:44:23.668092  CA_P2S_RATIO               = 8

  640 16:44:23.671295  DQ_CA_OPEN                 = 0

  641 16:44:23.674907  DQ_SEMI_OPEN               = 0

  642 16:44:23.679254  CA_SEMI_OPEN               = 0

  643 16:44:23.679775  CA_FULL_RATE               = 0

  644 16:44:23.682373  DQ_CKDIV4_EN               = 1

  645 16:44:23.685391  CA_CKDIV4_EN               = 1

  646 16:44:23.688875  CA_PREDIV_EN               = 0

  647 16:44:23.692008  PH8_DLY                    = 0

  648 16:44:23.692461  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  649 16:44:23.695908  DQ_AAMCK_DIV               = 4

  650 16:44:23.698864  CA_AAMCK_DIV               = 4

  651 16:44:23.701903  CA_ADMCK_DIV               = 4

  652 16:44:23.705281  DQ_TRACK_CA_EN             = 0

  653 16:44:23.709382  CA_PICK                    = 800

  654 16:44:23.711911  CA_MCKIO                   = 800

  655 16:44:23.712443  MCKIO_SEMI                 = 0

  656 16:44:23.715057  PLL_FREQ                   = 3068

  657 16:44:23.718912  DQ_UI_PI_RATIO             = 32

  658 16:44:23.722268  CA_UI_PI_RATIO             = 0

  659 16:44:23.727082  =================================== 

  660 16:44:23.727707  =================================== 

  661 16:44:23.730364  memory_type:LPDDR4         

  662 16:44:23.734900  GP_NUM     : 10       

  663 16:44:23.735371  SRAM_EN    : 1       

  664 16:44:23.738216  MD32_EN    : 0       

  665 16:44:23.742285  =================================== 

  666 16:44:23.742745  [ANA_INIT] >>>>>>>>>>>>>> 

  667 16:44:23.745908  <<<<<< [CONFIGURE PHASE]: ANA_TX

  668 16:44:23.749600  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  669 16:44:23.752945  =================================== 

  670 16:44:23.756317  data_rate = 1600,PCW = 0X7600

  671 16:44:23.759511  =================================== 

  672 16:44:23.762683  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  673 16:44:23.766561  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  674 16:44:23.772589  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  675 16:44:23.776209  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  676 16:44:23.779414  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  677 16:44:23.782685  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  678 16:44:23.786273  [ANA_INIT] flow start 

  679 16:44:23.789542  [ANA_INIT] PLL >>>>>>>> 

  680 16:44:23.790056  [ANA_INIT] PLL <<<<<<<< 

  681 16:44:23.792638  [ANA_INIT] MIDPI >>>>>>>> 

  682 16:44:23.796271  [ANA_INIT] MIDPI <<<<<<<< 

  683 16:44:23.799093  [ANA_INIT] DLL >>>>>>>> 

  684 16:44:23.799640  [ANA_INIT] flow end 

  685 16:44:23.802629  ============ LP4 DIFF to SE enter ============

  686 16:44:23.809138  ============ LP4 DIFF to SE exit  ============

  687 16:44:23.809631  [ANA_INIT] <<<<<<<<<<<<< 

  688 16:44:23.812982  [Flow] Enable top DCM control >>>>> 

  689 16:44:23.815757  [Flow] Enable top DCM control <<<<< 

  690 16:44:23.819139  Enable DLL master slave shuffle 

  691 16:44:23.825711  ============================================================== 

  692 16:44:23.826169  Gating Mode config

  693 16:44:23.832776  ============================================================== 

  694 16:44:23.835610  Config description: 

  695 16:44:23.845934  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  696 16:44:23.852855  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  697 16:44:23.856342  SELPH_MODE            0: By rank         1: By Phase 

  698 16:44:23.862833  ============================================================== 

  699 16:44:23.865858  GAT_TRACK_EN                 =  1

  700 16:44:23.866361  RX_GATING_MODE               =  2

  701 16:44:23.868959  RX_GATING_TRACK_MODE         =  2

  702 16:44:23.872611  SELPH_MODE                   =  1

  703 16:44:23.875499  PICG_EARLY_EN                =  1

  704 16:44:23.879277  VALID_LAT_VALUE              =  1

  705 16:44:23.885802  ============================================================== 

  706 16:44:23.888952  Enter into Gating configuration >>>> 

  707 16:44:23.892744  Exit from Gating configuration <<<< 

  708 16:44:23.895254  Enter into  DVFS_PRE_config >>>>> 

  709 16:44:23.905390  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  710 16:44:23.909209  Exit from  DVFS_PRE_config <<<<< 

  711 16:44:23.912246  Enter into PICG configuration >>>> 

  712 16:44:23.915684  Exit from PICG configuration <<<< 

  713 16:44:23.918793  [RX_INPUT] configuration >>>>> 

  714 16:44:23.922009  [RX_INPUT] configuration <<<<< 

  715 16:44:23.925501  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  716 16:44:23.932288  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  717 16:44:23.938317  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  718 16:44:23.942453  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  719 16:44:23.948658  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  720 16:44:23.955035  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  721 16:44:23.958406  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  722 16:44:23.965381  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  723 16:44:23.968450  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  724 16:44:23.971911  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  725 16:44:23.975277  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  726 16:44:23.982209  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  727 16:44:23.985076  =================================== 

  728 16:44:23.985509  LPDDR4 DRAM CONFIGURATION

  729 16:44:23.988351  =================================== 

  730 16:44:23.991731  EX_ROW_EN[0]    = 0x0

  731 16:44:23.994893  EX_ROW_EN[1]    = 0x0

  732 16:44:23.995571  LP4Y_EN      = 0x0

  733 16:44:23.998298  WORK_FSP     = 0x0

  734 16:44:23.998751  WL           = 0x2

  735 16:44:24.001647  RL           = 0x2

  736 16:44:24.002183  BL           = 0x2

  737 16:44:24.004555  RPST         = 0x0

  738 16:44:24.005033  RD_PRE       = 0x0

  739 16:44:24.008324  WR_PRE       = 0x1

  740 16:44:24.008836  WR_PST       = 0x0

  741 16:44:24.011411  DBI_WR       = 0x0

  742 16:44:24.012045  DBI_RD       = 0x0

  743 16:44:24.014394  OTF          = 0x1

  744 16:44:24.017921  =================================== 

  745 16:44:24.021409  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  746 16:44:24.024551  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  747 16:44:24.031639  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  748 16:44:24.034840  =================================== 

  749 16:44:24.035538  LPDDR4 DRAM CONFIGURATION

  750 16:44:24.037734  =================================== 

  751 16:44:24.041145  EX_ROW_EN[0]    = 0x10

  752 16:44:24.044581  EX_ROW_EN[1]    = 0x0

  753 16:44:24.045049  LP4Y_EN      = 0x0

  754 16:44:24.048402  WORK_FSP     = 0x0

  755 16:44:24.048971  WL           = 0x2

  756 16:44:24.051680  RL           = 0x2

  757 16:44:24.052204  BL           = 0x2

  758 16:44:24.054730  RPST         = 0x0

  759 16:44:24.055308  RD_PRE       = 0x0

  760 16:44:24.057952  WR_PRE       = 0x1

  761 16:44:24.058377  WR_PST       = 0x0

  762 16:44:24.061043  DBI_WR       = 0x0

  763 16:44:24.061552  DBI_RD       = 0x0

  764 16:44:24.064878  OTF          = 0x1

  765 16:44:24.068214  =================================== 

  766 16:44:24.074286  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  767 16:44:24.077896  nWR fixed to 40

  768 16:44:24.078336  [ModeRegInit_LP4] CH0 RK0

  769 16:44:24.081021  [ModeRegInit_LP4] CH0 RK1

  770 16:44:24.085046  [ModeRegInit_LP4] CH1 RK0

  771 16:44:24.088014  [ModeRegInit_LP4] CH1 RK1

  772 16:44:24.088543  match AC timing 13

  773 16:44:24.090937  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  774 16:44:24.097874  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  775 16:44:24.101035  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  776 16:44:24.107495  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  777 16:44:24.110588  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  778 16:44:24.110675  [EMI DOE] emi_dcm 0

  779 16:44:24.117345  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  780 16:44:24.117432  ==

  781 16:44:24.120528  Dram Type= 6, Freq= 0, CH_0, rank 0

  782 16:44:24.124455  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  783 16:44:24.124541  ==

  784 16:44:24.131138  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  785 16:44:24.133916  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  786 16:44:24.144662  [CA 0] Center 37 (7~68) winsize 62

  787 16:44:24.147957  [CA 1] Center 37 (6~68) winsize 63

  788 16:44:24.151047  [CA 2] Center 34 (4~65) winsize 62

  789 16:44:24.154151  [CA 3] Center 34 (4~65) winsize 62

  790 16:44:24.157703  [CA 4] Center 33 (3~64) winsize 62

  791 16:44:24.160881  [CA 5] Center 33 (3~64) winsize 62

  792 16:44:24.160994  

  793 16:44:24.164327  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  794 16:44:24.164504  

  795 16:44:24.167277  [CATrainingPosCal] consider 1 rank data

  796 16:44:24.170638  u2DelayCellTimex100 = 270/100 ps

  797 16:44:24.174256  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  798 16:44:24.180932  CA1 delay=37 (6~68),Diff = 4 PI (28 cell)

  799 16:44:24.184603  CA2 delay=34 (4~65),Diff = 1 PI (7 cell)

  800 16:44:24.187521  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  801 16:44:24.190768  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

  802 16:44:24.194402  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  803 16:44:24.194486  

  804 16:44:24.197604  CA PerBit enable=1, Macro0, CA PI delay=33

  805 16:44:24.197691  

  806 16:44:24.200591  [CBTSetCACLKResult] CA Dly = 33

  807 16:44:24.200674  CS Dly: 5 (0~36)

  808 16:44:24.204039  ==

  809 16:44:24.207840  Dram Type= 6, Freq= 0, CH_0, rank 1

  810 16:44:24.210986  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  811 16:44:24.211095  ==

  812 16:44:24.217779  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  813 16:44:24.220860  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  814 16:44:24.230885  [CA 0] Center 38 (7~69) winsize 63

  815 16:44:24.234688  [CA 1] Center 37 (7~68) winsize 62

  816 16:44:24.237994  [CA 2] Center 35 (4~66) winsize 63

  817 16:44:24.240933  [CA 3] Center 35 (4~66) winsize 63

  818 16:44:24.244273  [CA 4] Center 34 (3~65) winsize 63

  819 16:44:24.247476  [CA 5] Center 33 (3~64) winsize 62

  820 16:44:24.247907  

  821 16:44:24.250772  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  822 16:44:24.251354  

  823 16:44:24.253867  [CATrainingPosCal] consider 2 rank data

  824 16:44:24.257881  u2DelayCellTimex100 = 270/100 ps

  825 16:44:24.260516  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  826 16:44:24.267436  CA1 delay=37 (7~68),Diff = 4 PI (28 cell)

  827 16:44:24.270901  CA2 delay=34 (4~65),Diff = 1 PI (7 cell)

  828 16:44:24.273991  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  829 16:44:24.277167  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

  830 16:44:24.280895  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  831 16:44:24.281439  

  832 16:44:24.283684  CA PerBit enable=1, Macro0, CA PI delay=33

  833 16:44:24.284131  

  834 16:44:24.287370  [CBTSetCACLKResult] CA Dly = 33

  835 16:44:24.287925  CS Dly: 6 (0~38)

  836 16:44:24.291261  

  837 16:44:24.293706  ----->DramcWriteLeveling(PI) begin...

  838 16:44:24.294318  ==

  839 16:44:24.297616  Dram Type= 6, Freq= 0, CH_0, rank 0

  840 16:44:24.300948  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  841 16:44:24.301383  ==

  842 16:44:24.304745  Write leveling (Byte 0): 30 => 30

  843 16:44:24.308468  Write leveling (Byte 1): 30 => 30

  844 16:44:24.308937  DramcWriteLeveling(PI) end<-----

  845 16:44:24.309283  

  846 16:44:24.309604  ==

  847 16:44:24.311846  Dram Type= 6, Freq= 0, CH_0, rank 0

  848 16:44:24.319301  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  849 16:44:24.319745  ==

  850 16:44:24.320094  [Gating] SW mode calibration

  851 16:44:24.329261  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  852 16:44:24.332826  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  853 16:44:24.335916   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  854 16:44:24.342543   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  855 16:44:24.346184   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  856 16:44:24.349133   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  857 16:44:24.355905   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  858 16:44:24.359297   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  859 16:44:24.362537   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  860 16:44:24.368769   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  861 16:44:24.372709   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  862 16:44:24.376042   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  863 16:44:24.379236   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  864 16:44:24.385868   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  865 16:44:24.389053   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  866 16:44:24.392124   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  867 16:44:24.399024   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  868 16:44:24.402105   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  869 16:44:24.405500   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  870 16:44:24.412644   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

  871 16:44:24.415444   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  872 16:44:24.418961   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  873 16:44:24.426171   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  874 16:44:24.428806   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  875 16:44:24.432195   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  876 16:44:24.438884   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  877 16:44:24.442043   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  878 16:44:24.445326   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  879 16:44:24.452282   0  9  8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)

  880 16:44:24.455234   0  9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)

  881 16:44:24.458872   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  882 16:44:24.465476   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  883 16:44:24.468753   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  884 16:44:24.472002   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  885 16:44:24.478451   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

  886 16:44:24.481827   0 10  4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)

  887 16:44:24.485462   0 10  8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)

  888 16:44:24.491718   0 10 12 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)

  889 16:44:24.494932   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  890 16:44:24.498433   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  891 16:44:24.504887   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  892 16:44:24.508204   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  893 16:44:24.511445   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  894 16:44:24.518099   0 11  4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)

  895 16:44:24.521634   0 11  8 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)

  896 16:44:24.524919   0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)

  897 16:44:24.531657   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  898 16:44:24.534810   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  899 16:44:24.538064   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  900 16:44:24.544906   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  901 16:44:24.547958   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  902 16:44:24.551576   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

  903 16:44:24.558052   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  904 16:44:24.561530   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  905 16:44:24.564523   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  906 16:44:24.571022   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  907 16:44:24.574566   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  908 16:44:24.577888   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  909 16:44:24.581191   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  910 16:44:24.587717   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  911 16:44:24.590892   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  912 16:44:24.594112   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  913 16:44:24.600737   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  914 16:44:24.604685   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  915 16:44:24.607605   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  916 16:44:24.614045   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  917 16:44:24.617254   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  918 16:44:24.620541   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  919 16:44:24.627440   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  920 16:44:24.630793  Total UI for P1: 0, mck2ui 16

  921 16:44:24.634294  best dqsien dly found for B0: ( 0, 14,  4)

  922 16:44:24.637078   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  923 16:44:24.640683  Total UI for P1: 0, mck2ui 16

  924 16:44:24.643859  best dqsien dly found for B1: ( 0, 14,  8)

  925 16:44:24.647139  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

  926 16:44:24.650532  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

  927 16:44:24.650616  

  928 16:44:24.654383  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

  929 16:44:24.657230  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

  930 16:44:24.660883  [Gating] SW calibration Done

  931 16:44:24.660966  ==

  932 16:44:24.663604  Dram Type= 6, Freq= 0, CH_0, rank 0

  933 16:44:24.667035  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  934 16:44:24.670196  ==

  935 16:44:24.670314  RX Vref Scan: 0

  936 16:44:24.670415  

  937 16:44:24.674297  RX Vref 0 -> 0, step: 1

  938 16:44:24.674408  

  939 16:44:24.674493  RX Delay -130 -> 252, step: 16

  940 16:44:24.681057  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

  941 16:44:24.684357  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

  942 16:44:24.687851  iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224

  943 16:44:24.690898  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

  944 16:44:24.694066  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

  945 16:44:24.701073  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  946 16:44:24.704414  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

  947 16:44:24.707423  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

  948 16:44:24.710913  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

  949 16:44:24.714000  iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240

  950 16:44:24.721178  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

  951 16:44:24.724374  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

  952 16:44:24.727458  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

  953 16:44:24.730755  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

  954 16:44:24.737489  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

  955 16:44:24.740727  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

  956 16:44:24.741158  ==

  957 16:44:24.744748  Dram Type= 6, Freq= 0, CH_0, rank 0

  958 16:44:24.747583  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  959 16:44:24.748016  ==

  960 16:44:24.750572  DQS Delay:

  961 16:44:24.750995  DQS0 = 0, DQS1 = 0

  962 16:44:24.751389  DQM Delay:

  963 16:44:24.753988  DQM0 = 92, DQM1 = 75

  964 16:44:24.754417  DQ Delay:

  965 16:44:24.757590  DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93

  966 16:44:24.761312  DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93

  967 16:44:24.763982  DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69

  968 16:44:24.767450  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

  969 16:44:24.767891  

  970 16:44:24.768260  

  971 16:44:24.768635  ==

  972 16:44:24.770567  Dram Type= 6, Freq= 0, CH_0, rank 0

  973 16:44:24.777297  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  974 16:44:24.777728  ==

  975 16:44:24.778065  

  976 16:44:24.778378  

  977 16:44:24.778674  	TX Vref Scan disable

  978 16:44:24.780890   == TX Byte 0 ==

  979 16:44:24.783951  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  980 16:44:24.791131  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  981 16:44:24.791605   == TX Byte 1 ==

  982 16:44:24.794067  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  983 16:44:24.797512  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  984 16:44:24.800431  ==

  985 16:44:24.803920  Dram Type= 6, Freq= 0, CH_0, rank 0

  986 16:44:24.807064  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  987 16:44:24.807552  ==

  988 16:44:24.819313  TX Vref=22, minBit 4, minWin=26, winSum=439

  989 16:44:24.823416  TX Vref=24, minBit 1, minWin=27, winSum=443

  990 16:44:24.826610  TX Vref=26, minBit 1, minWin=27, winSum=446

  991 16:44:24.830065  TX Vref=28, minBit 1, minWin=27, winSum=449

  992 16:44:24.832644  TX Vref=30, minBit 1, minWin=27, winSum=453

  993 16:44:24.839749  TX Vref=32, minBit 1, minWin=27, winSum=453

  994 16:44:24.842728  [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 30

  995 16:44:24.843165  

  996 16:44:24.846182  Final TX Range 1 Vref 30

  997 16:44:24.846794  

  998 16:44:24.847303  ==

  999 16:44:24.849334  Dram Type= 6, Freq= 0, CH_0, rank 0

 1000 16:44:24.852714  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1001 16:44:24.853145  ==

 1002 16:44:24.855860  

 1003 16:44:24.856284  

 1004 16:44:24.856683  	TX Vref Scan disable

 1005 16:44:24.859160   == TX Byte 0 ==

 1006 16:44:24.862550  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1007 16:44:24.869699  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1008 16:44:24.870136   == TX Byte 1 ==

 1009 16:44:24.872386  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1010 16:44:24.879373  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1011 16:44:24.879816  

 1012 16:44:24.880155  [DATLAT]

 1013 16:44:24.880467  Freq=800, CH0 RK0

 1014 16:44:24.880768  

 1015 16:44:24.883144  DATLAT Default: 0xa

 1016 16:44:24.883618  0, 0xFFFF, sum = 0

 1017 16:44:24.885868  1, 0xFFFF, sum = 0

 1018 16:44:24.886297  2, 0xFFFF, sum = 0

 1019 16:44:24.889705  3, 0xFFFF, sum = 0

 1020 16:44:24.892400  4, 0xFFFF, sum = 0

 1021 16:44:24.892834  5, 0xFFFF, sum = 0

 1022 16:44:24.895931  6, 0xFFFF, sum = 0

 1023 16:44:24.896364  7, 0xFFFF, sum = 0

 1024 16:44:24.899135  8, 0xFFFF, sum = 0

 1025 16:44:24.899681  9, 0x0, sum = 1

 1026 16:44:24.902515  10, 0x0, sum = 2

 1027 16:44:24.902962  11, 0x0, sum = 3

 1028 16:44:24.903356  12, 0x0, sum = 4

 1029 16:44:24.905658  best_step = 10

 1030 16:44:24.906275  

 1031 16:44:24.906822  ==

 1032 16:44:24.909252  Dram Type= 6, Freq= 0, CH_0, rank 0

 1033 16:44:24.912560  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1034 16:44:24.913288  ==

 1035 16:44:24.915584  RX Vref Scan: 1

 1036 16:44:24.916260  

 1037 16:44:24.918859  Set Vref Range= 32 -> 127

 1038 16:44:24.919571  

 1039 16:44:24.920207  RX Vref 32 -> 127, step: 1

 1040 16:44:24.920818  

 1041 16:44:24.922198  RX Delay -111 -> 252, step: 8

 1042 16:44:24.922860  

 1043 16:44:24.925521  Set Vref, RX VrefLevel [Byte0]: 32

 1044 16:44:24.929382                           [Byte1]: 32

 1045 16:44:24.932046  

 1046 16:44:24.932677  Set Vref, RX VrefLevel [Byte0]: 33

 1047 16:44:24.935578                           [Byte1]: 33

 1048 16:44:24.940482  

 1049 16:44:24.940918  Set Vref, RX VrefLevel [Byte0]: 34

 1050 16:44:24.942959                           [Byte1]: 34

 1051 16:44:24.947460  

 1052 16:44:24.947882  Set Vref, RX VrefLevel [Byte0]: 35

 1053 16:44:24.950591                           [Byte1]: 35

 1054 16:44:24.955261  

 1055 16:44:24.955762  Set Vref, RX VrefLevel [Byte0]: 36

 1056 16:44:24.958266                           [Byte1]: 36

 1057 16:44:24.963421  

 1058 16:44:24.963862  Set Vref, RX VrefLevel [Byte0]: 37

 1059 16:44:24.966646                           [Byte1]: 37

 1060 16:44:24.970953  

 1061 16:44:24.971735  Set Vref, RX VrefLevel [Byte0]: 38

 1062 16:44:24.974089                           [Byte1]: 38

 1063 16:44:24.978244  

 1064 16:44:24.981616  Set Vref, RX VrefLevel [Byte0]: 39

 1065 16:44:24.982051                           [Byte1]: 39

 1066 16:44:24.986483  

 1067 16:44:24.986907  Set Vref, RX VrefLevel [Byte0]: 40

 1068 16:44:24.990160                           [Byte1]: 40

 1069 16:44:24.993981  

 1070 16:44:24.994405  Set Vref, RX VrefLevel [Byte0]: 41

 1071 16:44:24.997141                           [Byte1]: 41

 1072 16:44:25.001636  

 1073 16:44:25.002084  Set Vref, RX VrefLevel [Byte0]: 42

 1074 16:44:25.004425                           [Byte1]: 42

 1075 16:44:25.008538  

 1076 16:44:25.008964  Set Vref, RX VrefLevel [Byte0]: 43

 1077 16:44:25.012173                           [Byte1]: 43

 1078 16:44:25.017072  

 1079 16:44:25.017535  Set Vref, RX VrefLevel [Byte0]: 44

 1080 16:44:25.020577                           [Byte1]: 44

 1081 16:44:25.024040  

 1082 16:44:25.024467  Set Vref, RX VrefLevel [Byte0]: 45

 1083 16:44:25.026934                           [Byte1]: 45

 1084 16:44:25.031580  

 1085 16:44:25.032081  Set Vref, RX VrefLevel [Byte0]: 46

 1086 16:44:25.034856                           [Byte1]: 46

 1087 16:44:25.039134  

 1088 16:44:25.039654  Set Vref, RX VrefLevel [Byte0]: 47

 1089 16:44:25.042692                           [Byte1]: 47

 1090 16:44:25.047288  

 1091 16:44:25.047893  Set Vref, RX VrefLevel [Byte0]: 48

 1092 16:44:25.050407                           [Byte1]: 48

 1093 16:44:25.054926  

 1094 16:44:25.055548  Set Vref, RX VrefLevel [Byte0]: 49

 1095 16:44:25.058282                           [Byte1]: 49

 1096 16:44:25.062418  

 1097 16:44:25.062994  Set Vref, RX VrefLevel [Byte0]: 50

 1098 16:44:25.065681                           [Byte1]: 50

 1099 16:44:25.069640  

 1100 16:44:25.070269  Set Vref, RX VrefLevel [Byte0]: 51

 1101 16:44:25.073486                           [Byte1]: 51

 1102 16:44:25.077455  

 1103 16:44:25.078016  Set Vref, RX VrefLevel [Byte0]: 52

 1104 16:44:25.080995                           [Byte1]: 52

 1105 16:44:25.084892  

 1106 16:44:25.085498  Set Vref, RX VrefLevel [Byte0]: 53

 1107 16:44:25.089176                           [Byte1]: 53

 1108 16:44:25.092849  

 1109 16:44:25.093367  Set Vref, RX VrefLevel [Byte0]: 54

 1110 16:44:25.096054                           [Byte1]: 54

 1111 16:44:25.100665  

 1112 16:44:25.101221  Set Vref, RX VrefLevel [Byte0]: 55

 1113 16:44:25.103974                           [Byte1]: 55

 1114 16:44:25.108407  

 1115 16:44:25.108915  Set Vref, RX VrefLevel [Byte0]: 56

 1116 16:44:25.111665                           [Byte1]: 56

 1117 16:44:25.115622  

 1118 16:44:25.116220  Set Vref, RX VrefLevel [Byte0]: 57

 1119 16:44:25.119073                           [Byte1]: 57

 1120 16:44:25.123602  

 1121 16:44:25.124155  Set Vref, RX VrefLevel [Byte0]: 58

 1122 16:44:25.126400                           [Byte1]: 58

 1123 16:44:25.131357  

 1124 16:44:25.131930  Set Vref, RX VrefLevel [Byte0]: 59

 1125 16:44:25.134425                           [Byte1]: 59

 1126 16:44:25.138381  

 1127 16:44:25.139060  Set Vref, RX VrefLevel [Byte0]: 60

 1128 16:44:25.141604                           [Byte1]: 60

 1129 16:44:25.146578  

 1130 16:44:25.147139  Set Vref, RX VrefLevel [Byte0]: 61

 1131 16:44:25.149406                           [Byte1]: 61

 1132 16:44:25.153787  

 1133 16:44:25.154366  Set Vref, RX VrefLevel [Byte0]: 62

 1134 16:44:25.157542                           [Byte1]: 62

 1135 16:44:25.161760  

 1136 16:44:25.162311  Set Vref, RX VrefLevel [Byte0]: 63

 1137 16:44:25.164800                           [Byte1]: 63

 1138 16:44:25.168942  

 1139 16:44:25.169548  Set Vref, RX VrefLevel [Byte0]: 64

 1140 16:44:25.172566                           [Byte1]: 64

 1141 16:44:25.176858  

 1142 16:44:25.177434  Set Vref, RX VrefLevel [Byte0]: 65

 1143 16:44:25.180499                           [Byte1]: 65

 1144 16:44:25.184649  

 1145 16:44:25.185133  Set Vref, RX VrefLevel [Byte0]: 66

 1146 16:44:25.187884                           [Byte1]: 66

 1147 16:44:25.192507  

 1148 16:44:25.193096  Set Vref, RX VrefLevel [Byte0]: 67

 1149 16:44:25.195297                           [Byte1]: 67

 1150 16:44:25.200468  

 1151 16:44:25.200886  Set Vref, RX VrefLevel [Byte0]: 68

 1152 16:44:25.203783                           [Byte1]: 68

 1153 16:44:25.207461  

 1154 16:44:25.210690  Set Vref, RX VrefLevel [Byte0]: 69

 1155 16:44:25.211273                           [Byte1]: 69

 1156 16:44:25.214941  

 1157 16:44:25.215464  Set Vref, RX VrefLevel [Byte0]: 70

 1158 16:44:25.218916                           [Byte1]: 70

 1159 16:44:25.222717  

 1160 16:44:25.223164  Set Vref, RX VrefLevel [Byte0]: 71

 1161 16:44:25.226569                           [Byte1]: 71

 1162 16:44:25.230446  

 1163 16:44:25.230867  Set Vref, RX VrefLevel [Byte0]: 72

 1164 16:44:25.233606                           [Byte1]: 72

 1165 16:44:25.238429  

 1166 16:44:25.238850  Set Vref, RX VrefLevel [Byte0]: 73

 1167 16:44:25.241322                           [Byte1]: 73

 1168 16:44:25.246186  

 1169 16:44:25.246609  Set Vref, RX VrefLevel [Byte0]: 74

 1170 16:44:25.248702                           [Byte1]: 74

 1171 16:44:25.253464  

 1172 16:44:25.253885  Final RX Vref Byte 0 = 54 to rank0

 1173 16:44:25.257326  Final RX Vref Byte 1 = 60 to rank0

 1174 16:44:25.260011  Final RX Vref Byte 0 = 54 to rank1

 1175 16:44:25.263298  Final RX Vref Byte 1 = 60 to rank1==

 1176 16:44:25.266432  Dram Type= 6, Freq= 0, CH_0, rank 0

 1177 16:44:25.273072  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1178 16:44:25.273705  ==

 1179 16:44:25.274151  DQS Delay:

 1180 16:44:25.277028  DQS0 = 0, DQS1 = 0

 1181 16:44:25.277504  DQM Delay:

 1182 16:44:25.277876  DQM0 = 88, DQM1 = 77

 1183 16:44:25.279701  DQ Delay:

 1184 16:44:25.282876  DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84

 1185 16:44:25.286122  DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96

 1186 16:44:25.289609  DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =76

 1187 16:44:25.293078  DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84

 1188 16:44:25.293531  

 1189 16:44:25.293943  

 1190 16:44:25.299718  [DQSOSCAuto] RK0, (LSB)MR18= 0x2e27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps

 1191 16:44:25.302709  CH0 RK0: MR19=606, MR18=2E27

 1192 16:44:25.309220  CH0_RK0: MR19=0x606, MR18=0x2E27, DQSOSC=398, MR23=63, INC=93, DEC=62

 1193 16:44:25.310019  

 1194 16:44:25.312892  ----->DramcWriteLeveling(PI) begin...

 1195 16:44:25.313379  ==

 1196 16:44:25.315918  Dram Type= 6, Freq= 0, CH_0, rank 1

 1197 16:44:25.319669  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1198 16:44:25.320177  ==

 1199 16:44:25.322911  Write leveling (Byte 0): 30 => 30

 1200 16:44:25.326312  Write leveling (Byte 1): 29 => 29

 1201 16:44:25.329396  DramcWriteLeveling(PI) end<-----

 1202 16:44:25.329819  

 1203 16:44:25.330152  ==

 1204 16:44:25.333004  Dram Type= 6, Freq= 0, CH_0, rank 1

 1205 16:44:25.336355  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1206 16:44:25.336778  ==

 1207 16:44:25.338983  [Gating] SW mode calibration

 1208 16:44:25.345740  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1209 16:44:25.352719  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1210 16:44:25.356474   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1211 16:44:25.402965   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1212 16:44:25.403611   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1213 16:44:25.404415   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1214 16:44:25.405062   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1215 16:44:25.405622   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1216 16:44:25.406158   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1217 16:44:25.406674   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1218 16:44:25.407266   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1219 16:44:25.407610   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1220 16:44:25.407911   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1221 16:44:25.447488   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1222 16:44:25.448040   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1223 16:44:25.448870   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1224 16:44:25.449410   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1225 16:44:25.449750   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1226 16:44:25.450122   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1227 16:44:25.450436   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1228 16:44:25.450735   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)

 1229 16:44:25.451026   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1230 16:44:25.451498   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1231 16:44:25.451810   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1232 16:44:25.453491   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1233 16:44:25.457089   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1234 16:44:25.463586   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1235 16:44:25.466833   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1236 16:44:25.470240   0  9  8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)

 1237 16:44:25.476981   0  9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)

 1238 16:44:25.480218   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1239 16:44:25.483232   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1240 16:44:25.490002   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1241 16:44:25.493222   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1242 16:44:25.496779   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1243 16:44:25.503335   0 10  4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)

 1244 16:44:25.506871   0 10  8 | B1->B0 | 3030 2424 | 1 0 | (0 1) (0 0)

 1245 16:44:25.509716   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1246 16:44:25.516089   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1247 16:44:25.519977   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1248 16:44:25.523316   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1249 16:44:25.529506   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1250 16:44:25.532913   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1251 16:44:25.536391   0 11  4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)

 1252 16:44:25.539749   0 11  8 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)

 1253 16:44:25.546621   0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)

 1254 16:44:25.550452   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1255 16:44:25.553432   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1256 16:44:25.557161   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1257 16:44:25.564462   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1258 16:44:25.567797   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1259 16:44:25.571585   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1260 16:44:25.578355   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1261 16:44:25.581867   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1262 16:44:25.585492   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1263 16:44:25.588814   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1264 16:44:25.595248   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1265 16:44:25.598643   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1266 16:44:25.602216   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1267 16:44:25.608749   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1268 16:44:25.611834   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1269 16:44:25.615304   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1270 16:44:25.621357   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1271 16:44:25.624965   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1272 16:44:25.628439   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1273 16:44:25.634382   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1274 16:44:25.638175   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1275 16:44:25.641135   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1276 16:44:25.647769   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1277 16:44:25.648192  Total UI for P1: 0, mck2ui 16

 1278 16:44:25.654621  best dqsien dly found for B0: ( 0, 14,  4)

 1279 16:44:25.657711   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1280 16:44:25.661225  Total UI for P1: 0, mck2ui 16

 1281 16:44:25.664634  best dqsien dly found for B1: ( 0, 14,  8)

 1282 16:44:25.668123  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1283 16:44:25.671591  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1284 16:44:25.672012  

 1285 16:44:25.674244  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1286 16:44:25.677751  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1287 16:44:25.680959  [Gating] SW calibration Done

 1288 16:44:25.681409  ==

 1289 16:44:25.684119  Dram Type= 6, Freq= 0, CH_0, rank 1

 1290 16:44:25.687232  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1291 16:44:25.691014  ==

 1292 16:44:25.691461  RX Vref Scan: 0

 1293 16:44:25.691787  

 1294 16:44:25.694122  RX Vref 0 -> 0, step: 1

 1295 16:44:25.694538  

 1296 16:44:25.697362  RX Delay -130 -> 252, step: 16

 1297 16:44:25.700768  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

 1298 16:44:25.704046  iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240

 1299 16:44:25.707380  iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224

 1300 16:44:25.710648  iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240

 1301 16:44:25.717770  iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240

 1302 16:44:25.720382  iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224

 1303 16:44:25.724174  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1304 16:44:25.727313  iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224

 1305 16:44:25.730557  iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240

 1306 16:44:25.737471  iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224

 1307 16:44:25.740260  iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224

 1308 16:44:25.743572  iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240

 1309 16:44:25.747145  iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240

 1310 16:44:25.750937  iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240

 1311 16:44:25.757116  iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240

 1312 16:44:25.760245  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

 1313 16:44:25.760871  ==

 1314 16:44:25.763602  Dram Type= 6, Freq= 0, CH_0, rank 1

 1315 16:44:25.767150  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1316 16:44:25.767696  ==

 1317 16:44:25.770739  DQS Delay:

 1318 16:44:25.771233  DQS0 = 0, DQS1 = 0

 1319 16:44:25.771585  DQM Delay:

 1320 16:44:25.773524  DQM0 = 85, DQM1 = 77

 1321 16:44:25.773898  DQ Delay:

 1322 16:44:25.776859  DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85

 1323 16:44:25.780622  DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93

 1324 16:44:25.783651  DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69

 1325 16:44:25.787011  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1326 16:44:25.787519  

 1327 16:44:25.787855  

 1328 16:44:25.788200  ==

 1329 16:44:25.790061  Dram Type= 6, Freq= 0, CH_0, rank 1

 1330 16:44:25.796831  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1331 16:44:25.797381  ==

 1332 16:44:25.797873  

 1333 16:44:25.798328  

 1334 16:44:25.798782  	TX Vref Scan disable

 1335 16:44:25.800337   == TX Byte 0 ==

 1336 16:44:25.803677  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1337 16:44:25.807240  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1338 16:44:25.810887   == TX Byte 1 ==

 1339 16:44:25.813879  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1340 16:44:25.816925  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1341 16:44:25.820769  ==

 1342 16:44:25.823643  Dram Type= 6, Freq= 0, CH_0, rank 1

 1343 16:44:25.827046  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1344 16:44:25.827697  ==

 1345 16:44:25.839479  TX Vref=22, minBit 1, minWin=27, winSum=442

 1346 16:44:25.842684  TX Vref=24, minBit 1, minWin=27, winSum=442

 1347 16:44:25.846134  TX Vref=26, minBit 2, minWin=27, winSum=448

 1348 16:44:25.849226  TX Vref=28, minBit 1, minWin=27, winSum=447

 1349 16:44:25.852527  TX Vref=30, minBit 7, minWin=27, winSum=449

 1350 16:44:25.859258  TX Vref=32, minBit 1, minWin=27, winSum=446

 1351 16:44:25.862497  [TxChooseVref] Worse bit 7, Min win 27, Win sum 449, Final Vref 30

 1352 16:44:25.862996  

 1353 16:44:25.865578  Final TX Range 1 Vref 30

 1354 16:44:25.866066  

 1355 16:44:25.866421  ==

 1356 16:44:25.869140  Dram Type= 6, Freq= 0, CH_0, rank 1

 1357 16:44:25.872494  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1358 16:44:25.872953  ==

 1359 16:44:25.875919  

 1360 16:44:25.876330  

 1361 16:44:25.876652  	TX Vref Scan disable

 1362 16:44:25.879808   == TX Byte 0 ==

 1363 16:44:25.882875  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1364 16:44:25.889704  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1365 16:44:25.890374   == TX Byte 1 ==

 1366 16:44:25.892390  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1367 16:44:25.899086  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1368 16:44:25.899613  

 1369 16:44:25.900016  [DATLAT]

 1370 16:44:25.900378  Freq=800, CH0 RK1

 1371 16:44:25.900676  

 1372 16:44:25.902671  DATLAT Default: 0xa

 1373 16:44:25.903078  0, 0xFFFF, sum = 0

 1374 16:44:25.906059  1, 0xFFFF, sum = 0

 1375 16:44:25.906571  2, 0xFFFF, sum = 0

 1376 16:44:25.908865  3, 0xFFFF, sum = 0

 1377 16:44:25.912010  4, 0xFFFF, sum = 0

 1378 16:44:25.912426  5, 0xFFFF, sum = 0

 1379 16:44:25.915587  6, 0xFFFF, sum = 0

 1380 16:44:25.916062  7, 0xFFFF, sum = 0

 1381 16:44:25.919153  8, 0xFFFF, sum = 0

 1382 16:44:25.919619  9, 0x0, sum = 1

 1383 16:44:25.922315  10, 0x0, sum = 2

 1384 16:44:25.922727  11, 0x0, sum = 3

 1385 16:44:25.923111  12, 0x0, sum = 4

 1386 16:44:25.925470  best_step = 10

 1387 16:44:25.925878  

 1388 16:44:25.926198  ==

 1389 16:44:25.929265  Dram Type= 6, Freq= 0, CH_0, rank 1

 1390 16:44:25.932496  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1391 16:44:25.932920  ==

 1392 16:44:25.935515  RX Vref Scan: 0

 1393 16:44:25.936068  

 1394 16:44:25.936405  RX Vref 0 -> 0, step: 1

 1395 16:44:25.939011  

 1396 16:44:25.939505  RX Delay -95 -> 252, step: 8

 1397 16:44:25.945821  iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216

 1398 16:44:25.949498  iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224

 1399 16:44:25.952414  iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224

 1400 16:44:25.955544  iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224

 1401 16:44:25.959575  iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224

 1402 16:44:25.965940  iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224

 1403 16:44:25.969033  iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224

 1404 16:44:25.972155  iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224

 1405 16:44:25.975569  iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232

 1406 16:44:25.978949  iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224

 1407 16:44:25.985684  iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224

 1408 16:44:25.989617  iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224

 1409 16:44:25.992290  iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224

 1410 16:44:25.995501  iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224

 1411 16:44:26.002385  iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224

 1412 16:44:26.005299  iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232

 1413 16:44:26.005719  ==

 1414 16:44:26.009022  Dram Type= 6, Freq= 0, CH_0, rank 1

 1415 16:44:26.012234  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1416 16:44:26.012654  ==

 1417 16:44:26.012979  DQS Delay:

 1418 16:44:26.015427  DQS0 = 0, DQS1 = 0

 1419 16:44:26.015843  DQM Delay:

 1420 16:44:26.018723  DQM0 = 86, DQM1 = 77

 1421 16:44:26.019139  DQ Delay:

 1422 16:44:26.022078  DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80

 1423 16:44:26.025516  DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96

 1424 16:44:26.028481  DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72

 1425 16:44:26.032132  DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84

 1426 16:44:26.032510  

 1427 16:44:26.032893  

 1428 16:44:26.042081  [DQSOSCAuto] RK1, (LSB)MR18= 0x2521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps

 1429 16:44:26.042607  CH0 RK1: MR19=606, MR18=2521

 1430 16:44:26.048240  CH0_RK1: MR19=0x606, MR18=0x2521, DQSOSC=400, MR23=63, INC=92, DEC=61

 1431 16:44:26.051596  [RxdqsGatingPostProcess] freq 800

 1432 16:44:26.058608  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1433 16:44:26.061568  Pre-setting of DQS Precalculation

 1434 16:44:26.064903  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1435 16:44:26.065342  ==

 1436 16:44:26.068774  Dram Type= 6, Freq= 0, CH_1, rank 0

 1437 16:44:26.075299  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1438 16:44:26.075767  ==

 1439 16:44:26.078126  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1440 16:44:26.084803  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1441 16:44:26.095030  [CA 0] Center 36 (6~67) winsize 62

 1442 16:44:26.097644  [CA 1] Center 37 (6~68) winsize 63

 1443 16:44:26.100738  [CA 2] Center 35 (5~65) winsize 61

 1444 16:44:26.103931  [CA 3] Center 34 (4~65) winsize 62

 1445 16:44:26.107809  [CA 4] Center 34 (4~65) winsize 62

 1446 16:44:26.110852  [CA 5] Center 34 (3~65) winsize 63

 1447 16:44:26.111460  

 1448 16:44:26.113785  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1449 16:44:26.114349  

 1450 16:44:26.117081  [CATrainingPosCal] consider 1 rank data

 1451 16:44:26.120828  u2DelayCellTimex100 = 270/100 ps

 1452 16:44:26.124276  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1453 16:44:26.130517  CA1 delay=37 (6~68),Diff = 3 PI (21 cell)

 1454 16:44:26.134068  CA2 delay=35 (5~65),Diff = 1 PI (7 cell)

 1455 16:44:26.137465  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1456 16:44:26.141139  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1457 16:44:26.144035  CA5 delay=34 (3~65),Diff = 0 PI (0 cell)

 1458 16:44:26.144516  

 1459 16:44:26.146886  CA PerBit enable=1, Macro0, CA PI delay=34

 1460 16:44:26.147625  

 1461 16:44:26.150610  [CBTSetCACLKResult] CA Dly = 34

 1462 16:44:26.153609  CS Dly: 5 (0~36)

 1463 16:44:26.154061  ==

 1464 16:44:26.157151  Dram Type= 6, Freq= 0, CH_1, rank 1

 1465 16:44:26.160501  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1466 16:44:26.160945  ==

 1467 16:44:26.164423  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1468 16:44:26.170227  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1469 16:44:26.180384  [CA 0] Center 36 (6~67) winsize 62

 1470 16:44:26.183816  [CA 1] Center 36 (6~67) winsize 62

 1471 16:44:26.187491  [CA 2] Center 34 (4~65) winsize 62

 1472 16:44:26.190212  [CA 3] Center 34 (3~65) winsize 63

 1473 16:44:26.193476  [CA 4] Center 34 (3~65) winsize 63

 1474 16:44:26.197119  [CA 5] Center 34 (3~65) winsize 63

 1475 16:44:26.197538  

 1476 16:44:26.200246  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1477 16:44:26.200667  

 1478 16:44:26.203553  [CATrainingPosCal] consider 2 rank data

 1479 16:44:26.206690  u2DelayCellTimex100 = 270/100 ps

 1480 16:44:26.210542  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1481 16:44:26.213477  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1482 16:44:26.217775  CA2 delay=35 (5~65),Diff = 1 PI (7 cell)

 1483 16:44:26.220934  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1484 16:44:26.224444  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1485 16:44:26.228819  CA5 delay=34 (3~65),Diff = 0 PI (0 cell)

 1486 16:44:26.229240  

 1487 16:44:26.235165  CA PerBit enable=1, Macro0, CA PI delay=34

 1488 16:44:26.235633  

 1489 16:44:26.235965  [CBTSetCACLKResult] CA Dly = 34

 1490 16:44:26.239079  CS Dly: 5 (0~37)

 1491 16:44:26.239577  

 1492 16:44:26.242927  ----->DramcWriteLeveling(PI) begin...

 1493 16:44:26.243438  ==

 1494 16:44:26.246815  Dram Type= 6, Freq= 0, CH_1, rank 0

 1495 16:44:26.250095  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1496 16:44:26.250589  ==

 1497 16:44:26.254001  Write leveling (Byte 0): 26 => 26

 1498 16:44:26.256476  Write leveling (Byte 1): 26 => 26

 1499 16:44:26.260507  DramcWriteLeveling(PI) end<-----

 1500 16:44:26.261094  

 1501 16:44:26.261521  ==

 1502 16:44:26.263267  Dram Type= 6, Freq= 0, CH_1, rank 0

 1503 16:44:26.266712  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1504 16:44:26.267151  ==

 1505 16:44:26.269816  [Gating] SW mode calibration

 1506 16:44:26.276781  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1507 16:44:26.282915  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1508 16:44:26.286414   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1509 16:44:26.289652   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1510 16:44:26.296514   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1511 16:44:26.299418   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1512 16:44:26.303030   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1513 16:44:26.306562   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1514 16:44:26.313004   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1515 16:44:26.316268   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1516 16:44:26.319578   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1517 16:44:26.326397   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1518 16:44:26.329383   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1519 16:44:26.333786   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1520 16:44:26.339762   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1521 16:44:26.343302   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1522 16:44:26.346923   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1523 16:44:26.352969   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1524 16:44:26.356150   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1525 16:44:26.359373   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

 1526 16:44:26.366220   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1527 16:44:26.369482   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1528 16:44:26.373210   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1529 16:44:26.379525   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1530 16:44:26.382746   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1531 16:44:26.385834   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1532 16:44:26.392466   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1533 16:44:26.396022   0  9  4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)

 1534 16:44:26.399016   0  9  8 | B1->B0 | 3131 3333 | 1 0 | (1 1) (0 0)

 1535 16:44:26.406028   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1536 16:44:26.409448   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1537 16:44:26.412636   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1538 16:44:26.418611   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1539 16:44:26.422161   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1540 16:44:26.425414   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1541 16:44:26.431947   0 10  4 | B1->B0 | 3434 2f2f | 1 1 | (0 1) (1 1)

 1542 16:44:26.435268   0 10  8 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)

 1543 16:44:26.438716   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1544 16:44:26.445820   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1545 16:44:26.448767   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1546 16:44:26.452056   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1547 16:44:26.458388   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1548 16:44:26.462142   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1549 16:44:26.465149   0 11  4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)

 1550 16:44:26.472106   0 11  8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)

 1551 16:44:26.474895   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1552 16:44:26.478148   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1553 16:44:26.484988   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1554 16:44:26.488238   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1555 16:44:26.491733   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1556 16:44:26.498616   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1557 16:44:26.501803   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1558 16:44:26.505010   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1559 16:44:26.511829   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1560 16:44:26.514665   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1561 16:44:26.518443   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1562 16:44:26.525005   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1563 16:44:26.528331   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1564 16:44:26.531713   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1565 16:44:26.538097   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1566 16:44:26.541769   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1567 16:44:26.544949   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1568 16:44:26.551038   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1569 16:44:26.554492   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1570 16:44:26.559093   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1571 16:44:26.561849   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1572 16:44:26.568287   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1573 16:44:26.571023   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1574 16:44:26.575227   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1575 16:44:26.577917  Total UI for P1: 0, mck2ui 16

 1576 16:44:26.581132  best dqsien dly found for B0: ( 0, 14,  4)

 1577 16:44:26.584399  Total UI for P1: 0, mck2ui 16

 1578 16:44:26.587729  best dqsien dly found for B1: ( 0, 14,  4)

 1579 16:44:26.591428  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1580 16:44:26.594906  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1581 16:44:26.597766  

 1582 16:44:26.600758  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1583 16:44:26.604415  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1584 16:44:26.607872  [Gating] SW calibration Done

 1585 16:44:26.608380  ==

 1586 16:44:26.611306  Dram Type= 6, Freq= 0, CH_1, rank 0

 1587 16:44:26.614733  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1588 16:44:26.615248  ==

 1589 16:44:26.615663  RX Vref Scan: 0

 1590 16:44:26.616104  

 1591 16:44:26.617791  RX Vref 0 -> 0, step: 1

 1592 16:44:26.618219  

 1593 16:44:26.620740  RX Delay -130 -> 252, step: 16

 1594 16:44:26.624231  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1595 16:44:26.627729  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

 1596 16:44:26.634462  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1597 16:44:26.637703  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1598 16:44:26.640682  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1599 16:44:26.644600  iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224

 1600 16:44:26.647437  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1601 16:44:26.653961  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

 1602 16:44:26.657464  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1603 16:44:26.660973  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1604 16:44:26.663661  iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240

 1605 16:44:26.667521  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1606 16:44:26.674134  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1607 16:44:26.677461  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1608 16:44:26.680430  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1609 16:44:26.683848  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1610 16:44:26.684303  ==

 1611 16:44:26.687017  Dram Type= 6, Freq= 0, CH_1, rank 0

 1612 16:44:26.693923  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1613 16:44:26.694356  ==

 1614 16:44:26.694697  DQS Delay:

 1615 16:44:26.697418  DQS0 = 0, DQS1 = 0

 1616 16:44:26.697867  DQM Delay:

 1617 16:44:26.698206  DQM0 = 87, DQM1 = 84

 1618 16:44:26.700415  DQ Delay:

 1619 16:44:26.703869  DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85

 1620 16:44:26.707156  DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85

 1621 16:44:26.710573  DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77

 1622 16:44:26.713615  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1623 16:44:26.714044  

 1624 16:44:26.714417  

 1625 16:44:26.714757  ==

 1626 16:44:26.717380  Dram Type= 6, Freq= 0, CH_1, rank 0

 1627 16:44:26.720422  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1628 16:44:26.720932  ==

 1629 16:44:26.721310  

 1630 16:44:26.721625  

 1631 16:44:26.723536  	TX Vref Scan disable

 1632 16:44:26.727621   == TX Byte 0 ==

 1633 16:44:26.730726  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1634 16:44:26.733969  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1635 16:44:26.737439   == TX Byte 1 ==

 1636 16:44:26.740100  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1637 16:44:26.743497  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1638 16:44:26.743923  ==

 1639 16:44:26.747115  Dram Type= 6, Freq= 0, CH_1, rank 0

 1640 16:44:26.750382  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1641 16:44:26.753237  ==

 1642 16:44:26.764799  TX Vref=22, minBit 0, minWin=27, winSum=443

 1643 16:44:26.767763  TX Vref=24, minBit 0, minWin=27, winSum=447

 1644 16:44:26.771563  TX Vref=26, minBit 4, minWin=27, winSum=453

 1645 16:44:26.774424  TX Vref=28, minBit 4, minWin=27, winSum=452

 1646 16:44:26.777413  TX Vref=30, minBit 5, minWin=27, winSum=453

 1647 16:44:26.784405  TX Vref=32, minBit 6, minWin=27, winSum=454

 1648 16:44:26.787756  [TxChooseVref] Worse bit 6, Min win 27, Win sum 454, Final Vref 32

 1649 16:44:26.788183  

 1650 16:44:26.790853  Final TX Range 1 Vref 32

 1651 16:44:26.791313  

 1652 16:44:26.791652  ==

 1653 16:44:26.794543  Dram Type= 6, Freq= 0, CH_1, rank 0

 1654 16:44:26.798204  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1655 16:44:26.798630  ==

 1656 16:44:26.798962  

 1657 16:44:26.799324  

 1658 16:44:26.801501  	TX Vref Scan disable

 1659 16:44:26.804848   == TX Byte 0 ==

 1660 16:44:26.808234  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1661 16:44:26.811725  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1662 16:44:26.814686   == TX Byte 1 ==

 1663 16:44:26.818004  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1664 16:44:26.821526  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1665 16:44:26.822083  

 1666 16:44:26.824655  [DATLAT]

 1667 16:44:26.825259  Freq=800, CH1 RK0

 1668 16:44:26.825746  

 1669 16:44:26.828125  DATLAT Default: 0xa

 1670 16:44:26.828542  0, 0xFFFF, sum = 0

 1671 16:44:26.831280  1, 0xFFFF, sum = 0

 1672 16:44:26.831763  2, 0xFFFF, sum = 0

 1673 16:44:26.834998  3, 0xFFFF, sum = 0

 1674 16:44:26.835511  4, 0xFFFF, sum = 0

 1675 16:44:26.838295  5, 0xFFFF, sum = 0

 1676 16:44:26.838743  6, 0xFFFF, sum = 0

 1677 16:44:26.841316  7, 0xFFFF, sum = 0

 1678 16:44:26.844289  8, 0xFFFF, sum = 0

 1679 16:44:26.844726  9, 0x0, sum = 1

 1680 16:44:26.845209  10, 0x0, sum = 2

 1681 16:44:26.847783  11, 0x0, sum = 3

 1682 16:44:26.848220  12, 0x0, sum = 4

 1683 16:44:26.851280  best_step = 10

 1684 16:44:26.851755  

 1685 16:44:26.852184  ==

 1686 16:44:26.854926  Dram Type= 6, Freq= 0, CH_1, rank 0

 1687 16:44:26.857968  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1688 16:44:26.858414  ==

 1689 16:44:26.861131  RX Vref Scan: 1

 1690 16:44:26.861560  

 1691 16:44:26.861901  Set Vref Range= 32 -> 127

 1692 16:44:26.864731  

 1693 16:44:26.865159  RX Vref 32 -> 127, step: 1

 1694 16:44:26.865494  

 1695 16:44:26.867647  RX Delay -95 -> 252, step: 8

 1696 16:44:26.868078  

 1697 16:44:26.871483  Set Vref, RX VrefLevel [Byte0]: 32

 1698 16:44:26.874481                           [Byte1]: 32

 1699 16:44:26.874909  

 1700 16:44:26.877857  Set Vref, RX VrefLevel [Byte0]: 33

 1701 16:44:26.881107                           [Byte1]: 33

 1702 16:44:26.884939  

 1703 16:44:26.885389  Set Vref, RX VrefLevel [Byte0]: 34

 1704 16:44:26.888171                           [Byte1]: 34

 1705 16:44:26.892493  

 1706 16:44:26.892921  Set Vref, RX VrefLevel [Byte0]: 35

 1707 16:44:26.895804                           [Byte1]: 35

 1708 16:44:26.899708  

 1709 16:44:26.900138  Set Vref, RX VrefLevel [Byte0]: 36

 1710 16:44:26.903209                           [Byte1]: 36

 1711 16:44:26.907777  

 1712 16:44:26.908206  Set Vref, RX VrefLevel [Byte0]: 37

 1713 16:44:26.911091                           [Byte1]: 37

 1714 16:44:26.914807  

 1715 16:44:26.914890  Set Vref, RX VrefLevel [Byte0]: 38

 1716 16:44:26.917970                           [Byte1]: 38

 1717 16:44:26.922722  

 1718 16:44:26.922805  Set Vref, RX VrefLevel [Byte0]: 39

 1719 16:44:26.925451                           [Byte1]: 39

 1720 16:44:26.930506  

 1721 16:44:26.930589  Set Vref, RX VrefLevel [Byte0]: 40

 1722 16:44:26.933206                           [Byte1]: 40

 1723 16:44:26.937393  

 1724 16:44:26.937476  Set Vref, RX VrefLevel [Byte0]: 41

 1725 16:44:26.940615                           [Byte1]: 41

 1726 16:44:26.945019  

 1727 16:44:26.945104  Set Vref, RX VrefLevel [Byte0]: 42

 1728 16:44:26.948898                           [Byte1]: 42

 1729 16:44:26.952623  

 1730 16:44:26.952702  Set Vref, RX VrefLevel [Byte0]: 43

 1731 16:44:26.956178                           [Byte1]: 43

 1732 16:44:26.960284  

 1733 16:44:26.960367  Set Vref, RX VrefLevel [Byte0]: 44

 1734 16:44:26.963667                           [Byte1]: 44

 1735 16:44:26.967788  

 1736 16:44:26.967872  Set Vref, RX VrefLevel [Byte0]: 45

 1737 16:44:26.971184                           [Byte1]: 45

 1738 16:44:26.975865  

 1739 16:44:26.975948  Set Vref, RX VrefLevel [Byte0]: 46

 1740 16:44:26.978868                           [Byte1]: 46

 1741 16:44:26.983465  

 1742 16:44:26.983567  Set Vref, RX VrefLevel [Byte0]: 47

 1743 16:44:26.986464                           [Byte1]: 47

 1744 16:44:26.991072  

 1745 16:44:26.991215  Set Vref, RX VrefLevel [Byte0]: 48

 1746 16:44:26.994004                           [Byte1]: 48

 1747 16:44:26.998226  

 1748 16:44:26.998387  Set Vref, RX VrefLevel [Byte0]: 49

 1749 16:44:27.001484                           [Byte1]: 49

 1750 16:44:27.005819  

 1751 16:44:27.005903  Set Vref, RX VrefLevel [Byte0]: 50

 1752 16:44:27.009232                           [Byte1]: 50

 1753 16:44:27.013487  

 1754 16:44:27.013576  Set Vref, RX VrefLevel [Byte0]: 51

 1755 16:44:27.017213                           [Byte1]: 51

 1756 16:44:27.021291  

 1757 16:44:27.021393  Set Vref, RX VrefLevel [Byte0]: 52

 1758 16:44:27.024320                           [Byte1]: 52

 1759 16:44:27.029098  

 1760 16:44:27.031645  Set Vref, RX VrefLevel [Byte0]: 53

 1761 16:44:27.035091                           [Byte1]: 53

 1762 16:44:27.035226  

 1763 16:44:27.039656  Set Vref, RX VrefLevel [Byte0]: 54

 1764 16:44:27.042020                           [Byte1]: 54

 1765 16:44:27.042405  

 1766 16:44:27.045430  Set Vref, RX VrefLevel [Byte0]: 55

 1767 16:44:27.048605                           [Byte1]: 55

 1768 16:44:27.049034  

 1769 16:44:27.051955  Set Vref, RX VrefLevel [Byte0]: 56

 1770 16:44:27.055152                           [Byte1]: 56

 1771 16:44:27.060228  

 1772 16:44:27.060675  Set Vref, RX VrefLevel [Byte0]: 57

 1773 16:44:27.062594                           [Byte1]: 57

 1774 16:44:27.067030  

 1775 16:44:27.067492  Set Vref, RX VrefLevel [Byte0]: 58

 1776 16:44:27.070453                           [Byte1]: 58

 1777 16:44:27.075290  

 1778 16:44:27.075736  Set Vref, RX VrefLevel [Byte0]: 59

 1779 16:44:27.077954                           [Byte1]: 59

 1780 16:44:27.082305  

 1781 16:44:27.082748  Set Vref, RX VrefLevel [Byte0]: 60

 1782 16:44:27.085506                           [Byte1]: 60

 1783 16:44:27.089623  

 1784 16:44:27.090050  Set Vref, RX VrefLevel [Byte0]: 61

 1785 16:44:27.093404                           [Byte1]: 61

 1786 16:44:27.097913  

 1787 16:44:27.098345  Set Vref, RX VrefLevel [Byte0]: 62

 1788 16:44:27.100738                           [Byte1]: 62

 1789 16:44:27.104972  

 1790 16:44:27.105400  Set Vref, RX VrefLevel [Byte0]: 63

 1791 16:44:27.109038                           [Byte1]: 63

 1792 16:44:27.112591  

 1793 16:44:27.113036  Set Vref, RX VrefLevel [Byte0]: 64

 1794 16:44:27.115891                           [Byte1]: 64

 1795 16:44:27.120064  

 1796 16:44:27.120491  Set Vref, RX VrefLevel [Byte0]: 65

 1797 16:44:27.123705                           [Byte1]: 65

 1798 16:44:27.127699  

 1799 16:44:27.130999  Set Vref, RX VrefLevel [Byte0]: 66

 1800 16:44:27.134151                           [Byte1]: 66

 1801 16:44:27.134577  

 1802 16:44:27.137318  Set Vref, RX VrefLevel [Byte0]: 67

 1803 16:44:27.140806                           [Byte1]: 67

 1804 16:44:27.141276  

 1805 16:44:27.144047  Set Vref, RX VrefLevel [Byte0]: 68

 1806 16:44:27.147338                           [Byte1]: 68

 1807 16:44:27.150704  

 1808 16:44:27.151122  Set Vref, RX VrefLevel [Byte0]: 69

 1809 16:44:27.154030                           [Byte1]: 69

 1810 16:44:27.158565  

 1811 16:44:27.159027  Set Vref, RX VrefLevel [Byte0]: 70

 1812 16:44:27.161203                           [Byte1]: 70

 1813 16:44:27.166781  

 1814 16:44:27.167254  Set Vref, RX VrefLevel [Byte0]: 71

 1815 16:44:27.169130                           [Byte1]: 71

 1816 16:44:27.173209  

 1817 16:44:27.173657  Set Vref, RX VrefLevel [Byte0]: 72

 1818 16:44:27.176521                           [Byte1]: 72

 1819 16:44:27.181047  

 1820 16:44:27.181477  Set Vref, RX VrefLevel [Byte0]: 73

 1821 16:44:27.184519                           [Byte1]: 73

 1822 16:44:27.188595  

 1823 16:44:27.189080  Set Vref, RX VrefLevel [Byte0]: 74

 1824 16:44:27.192081                           [Byte1]: 74

 1825 16:44:27.196766  

 1826 16:44:27.197227  Final RX Vref Byte 0 = 59 to rank0

 1827 16:44:27.199954  Final RX Vref Byte 1 = 59 to rank0

 1828 16:44:27.202968  Final RX Vref Byte 0 = 59 to rank1

 1829 16:44:27.205980  Final RX Vref Byte 1 = 59 to rank1==

 1830 16:44:27.209475  Dram Type= 6, Freq= 0, CH_1, rank 0

 1831 16:44:27.216776  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1832 16:44:27.217291  ==

 1833 16:44:27.217691  DQS Delay:

 1834 16:44:27.218011  DQS0 = 0, DQS1 = 0

 1835 16:44:27.219349  DQM Delay:

 1836 16:44:27.219773  DQM0 = 86, DQM1 = 81

 1837 16:44:27.223093  DQ Delay:

 1838 16:44:27.226178  DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84

 1839 16:44:27.226570  DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84

 1840 16:44:27.229644  DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72

 1841 16:44:27.233484  DQ12 =88, DQ13 =92, DQ14 =84, DQ15 =88

 1842 16:44:27.236371  

 1843 16:44:27.236844  

 1844 16:44:27.242848  [DQSOSCAuto] RK0, (LSB)MR18= 0x1427, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps

 1845 16:44:27.246320  CH1 RK0: MR19=606, MR18=1427

 1846 16:44:27.253231  CH1_RK0: MR19=0x606, MR18=0x1427, DQSOSC=400, MR23=63, INC=92, DEC=61

 1847 16:44:27.253657  

 1848 16:44:27.256128  ----->DramcWriteLeveling(PI) begin...

 1849 16:44:27.256557  ==

 1850 16:44:27.259831  Dram Type= 6, Freq= 0, CH_1, rank 1

 1851 16:44:27.262848  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1852 16:44:27.263393  ==

 1853 16:44:27.266431  Write leveling (Byte 0): 25 => 25

 1854 16:44:27.269401  Write leveling (Byte 1): 27 => 27

 1855 16:44:27.272523  DramcWriteLeveling(PI) end<-----

 1856 16:44:27.272982  

 1857 16:44:27.273313  ==

 1858 16:44:27.276480  Dram Type= 6, Freq= 0, CH_1, rank 1

 1859 16:44:27.279591  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1860 16:44:27.280016  ==

 1861 16:44:27.282407  [Gating] SW mode calibration

 1862 16:44:27.289087  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1863 16:44:27.295476  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1864 16:44:27.299319   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1865 16:44:27.302895   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1866 16:44:27.309793   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1867 16:44:27.312409   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1868 16:44:27.315663   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1869 16:44:27.322759   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1870 16:44:27.325400   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1871 16:44:27.332250   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1872 16:44:27.334942   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1873 16:44:27.338543   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1874 16:44:27.345532   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1875 16:44:27.348558   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1876 16:44:27.351723   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1877 16:44:27.358490   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1878 16:44:27.361916   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1879 16:44:27.365065   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1880 16:44:27.371633   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1881 16:44:27.374829   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)

 1882 16:44:27.377996   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1883 16:44:27.381386   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1884 16:44:27.387902   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1885 16:44:27.391167   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1886 16:44:27.394701   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1887 16:44:27.402532   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1888 16:44:27.405002   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1889 16:44:27.408312   0  9  4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)

 1890 16:44:27.414729   0  9  8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)

 1891 16:44:27.418341   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1892 16:44:27.421625   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1893 16:44:27.427818   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1894 16:44:27.430963   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1895 16:44:27.434251   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1896 16:44:27.441714   0 10  0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 1)

 1897 16:44:27.444319   0 10  4 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)

 1898 16:44:27.447452   0 10  8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1899 16:44:27.454632   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1900 16:44:27.458078   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1901 16:44:27.461198   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1902 16:44:27.467607   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1903 16:44:27.471110   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1904 16:44:27.474113   0 11  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 1905 16:44:27.480568   0 11  4 | B1->B0 | 2626 3a3a | 0 0 | (0 0) (0 0)

 1906 16:44:27.484148   0 11  8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)

 1907 16:44:27.487492   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1908 16:44:27.493955   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1909 16:44:27.497480   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1910 16:44:27.500935   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1911 16:44:27.507766   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1912 16:44:27.510490   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1913 16:44:27.514459   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1914 16:44:27.520713   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1915 16:44:27.523909   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1916 16:44:27.526987   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1917 16:44:27.533750   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1918 16:44:27.536763   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1919 16:44:27.540596   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1920 16:44:27.547079   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1921 16:44:27.550454   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1922 16:44:27.553867   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1923 16:44:27.560025   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1924 16:44:27.563731   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1925 16:44:27.567257   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1926 16:44:27.573954   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1927 16:44:27.576793   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1928 16:44:27.580783   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1929 16:44:27.586593   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1930 16:44:27.587095  Total UI for P1: 0, mck2ui 16

 1931 16:44:27.589998  best dqsien dly found for B0: ( 0, 14,  0)

 1932 16:44:27.593391  Total UI for P1: 0, mck2ui 16

 1933 16:44:27.596567  best dqsien dly found for B1: ( 0, 14,  2)

 1934 16:44:27.600005  best DQS0 dly(MCK, UI, PI) = (0, 14, 0)

 1935 16:44:27.606568  best DQS1 dly(MCK, UI, PI) = (0, 14, 2)

 1936 16:44:27.606994  

 1937 16:44:27.610027  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)

 1938 16:44:27.613054  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1939 16:44:27.617085  [Gating] SW calibration Done

 1940 16:44:27.617614  ==

 1941 16:44:27.620777  Dram Type= 6, Freq= 0, CH_1, rank 1

 1942 16:44:27.623015  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1943 16:44:27.623561  ==

 1944 16:44:27.627009  RX Vref Scan: 0

 1945 16:44:27.627512  

 1946 16:44:27.627890  RX Vref 0 -> 0, step: 1

 1947 16:44:27.628212  

 1948 16:44:27.629745  RX Delay -130 -> 252, step: 16

 1949 16:44:27.632988  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

 1950 16:44:27.639781  iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256

 1951 16:44:27.643015  iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240

 1952 16:44:27.646389  iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224

 1953 16:44:27.649415  iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240

 1954 16:44:27.653122  iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224

 1955 16:44:27.656358  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1956 16:44:27.662933  iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240

 1957 16:44:27.666139  iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240

 1958 16:44:27.669188  iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240

 1959 16:44:27.672935  iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240

 1960 16:44:27.679085  iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240

 1961 16:44:27.682574  iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224

 1962 16:44:27.685879  iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224

 1963 16:44:27.689508  iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240

 1964 16:44:27.692729  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

 1965 16:44:27.695851  ==

 1966 16:44:27.699253  Dram Type= 6, Freq= 0, CH_1, rank 1

 1967 16:44:27.702737  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1968 16:44:27.703236  ==

 1969 16:44:27.703578  DQS Delay:

 1970 16:44:27.705847  DQS0 = 0, DQS1 = 0

 1971 16:44:27.706299  DQM Delay:

 1972 16:44:27.709015  DQM0 = 83, DQM1 = 81

 1973 16:44:27.709452  DQ Delay:

 1974 16:44:27.712388  DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77

 1975 16:44:27.715819  DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85

 1976 16:44:27.719061  DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69

 1977 16:44:27.722744  DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85

 1978 16:44:27.723315  

 1979 16:44:27.723689  

 1980 16:44:27.724000  ==

 1981 16:44:27.726048  Dram Type= 6, Freq= 0, CH_1, rank 1

 1982 16:44:27.729390  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1983 16:44:27.729824  ==

 1984 16:44:27.730158  

 1985 16:44:27.730465  

 1986 16:44:27.732562  	TX Vref Scan disable

 1987 16:44:27.735382   == TX Byte 0 ==

 1988 16:44:27.738919  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1989 16:44:27.742164  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1990 16:44:27.745350   == TX Byte 1 ==

 1991 16:44:27.748850  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1992 16:44:27.752369  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1993 16:44:27.752794  ==

 1994 16:44:27.755657  Dram Type= 6, Freq= 0, CH_1, rank 1

 1995 16:44:27.762099  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1996 16:44:27.762522  ==

 1997 16:44:27.773704  TX Vref=22, minBit 0, minWin=27, winSum=444

 1998 16:44:27.777107  TX Vref=24, minBit 1, minWin=27, winSum=450

 1999 16:44:27.780707  TX Vref=26, minBit 0, minWin=28, winSum=454

 2000 16:44:27.783480  TX Vref=28, minBit 5, minWin=27, winSum=455

 2001 16:44:27.786673  TX Vref=30, minBit 0, minWin=28, winSum=456

 2002 16:44:27.793568  TX Vref=32, minBit 0, minWin=27, winSum=455

 2003 16:44:27.797309  [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30

 2004 16:44:27.797731  

 2005 16:44:27.800239  Final TX Range 1 Vref 30

 2006 16:44:27.800657  

 2007 16:44:27.800985  ==

 2008 16:44:27.803567  Dram Type= 6, Freq= 0, CH_1, rank 1

 2009 16:44:27.807216  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2010 16:44:27.807656  ==

 2011 16:44:27.809791  

 2012 16:44:27.810222  

 2013 16:44:27.810649  	TX Vref Scan disable

 2014 16:44:27.813980   == TX Byte 0 ==

 2015 16:44:27.817239  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 2016 16:44:27.820398  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 2017 16:44:27.823289   == TX Byte 1 ==

 2018 16:44:27.826828  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 2019 16:44:27.833706  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 2020 16:44:27.834160  

 2021 16:44:27.834527  [DATLAT]

 2022 16:44:27.834849  Freq=800, CH1 RK1

 2023 16:44:27.835260  

 2024 16:44:27.836833  DATLAT Default: 0xa

 2025 16:44:27.837296  0, 0xFFFF, sum = 0

 2026 16:44:27.840184  1, 0xFFFF, sum = 0

 2027 16:44:27.840621  2, 0xFFFF, sum = 0

 2028 16:44:27.843519  3, 0xFFFF, sum = 0

 2029 16:44:27.847359  4, 0xFFFF, sum = 0

 2030 16:44:27.847795  5, 0xFFFF, sum = 0

 2031 16:44:27.849986  6, 0xFFFF, sum = 0

 2032 16:44:27.850420  7, 0xFFFF, sum = 0

 2033 16:44:27.853193  8, 0xFFFF, sum = 0

 2034 16:44:27.853670  9, 0x0, sum = 1

 2035 16:44:27.856651  10, 0x0, sum = 2

 2036 16:44:27.857198  11, 0x0, sum = 3

 2037 16:44:27.857575  12, 0x0, sum = 4

 2038 16:44:27.860060  best_step = 10

 2039 16:44:27.860486  

 2040 16:44:27.860822  ==

 2041 16:44:27.863478  Dram Type= 6, Freq= 0, CH_1, rank 1

 2042 16:44:27.866831  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2043 16:44:27.867407  ==

 2044 16:44:27.870846  RX Vref Scan: 0

 2045 16:44:27.871413  

 2046 16:44:27.873088  RX Vref 0 -> 0, step: 1

 2047 16:44:27.873538  

 2048 16:44:27.873876  RX Delay -95 -> 252, step: 8

 2049 16:44:27.880582  iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232

 2050 16:44:27.883413  iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232

 2051 16:44:27.886988  iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232

 2052 16:44:27.890112  iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224

 2053 16:44:27.893390  iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232

 2054 16:44:27.900029  iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224

 2055 16:44:27.903220  iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224

 2056 16:44:27.906597  iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232

 2057 16:44:27.910244  iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224

 2058 16:44:27.914081  iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224

 2059 16:44:27.920041  iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232

 2060 16:44:27.923448  iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224

 2061 16:44:27.926447  iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216

 2062 16:44:27.929902  iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224

 2063 16:44:27.937313  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 2064 16:44:27.939977  iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224

 2065 16:44:27.940413  ==

 2066 16:44:27.942950  Dram Type= 6, Freq= 0, CH_1, rank 1

 2067 16:44:27.946226  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2068 16:44:27.946660  ==

 2069 16:44:27.950014  DQS Delay:

 2070 16:44:27.950445  DQS0 = 0, DQS1 = 0

 2071 16:44:27.950784  DQM Delay:

 2072 16:44:27.953365  DQM0 = 86, DQM1 = 83

 2073 16:44:27.953877  DQ Delay:

 2074 16:44:27.956286  DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80

 2075 16:44:27.959753  DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84

 2076 16:44:27.963450  DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80

 2077 16:44:27.966785  DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =88

 2078 16:44:27.967259  

 2079 16:44:27.967639  

 2080 16:44:27.977325  [DQSOSCAuto] RK1, (LSB)MR18= 0x203c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps

 2081 16:44:27.977759  CH1 RK1: MR19=606, MR18=203C

 2082 16:44:27.982927  CH1_RK1: MR19=0x606, MR18=0x203C, DQSOSC=394, MR23=63, INC=95, DEC=63

 2083 16:44:27.987403  [RxdqsGatingPostProcess] freq 800

 2084 16:44:27.992899  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2085 16:44:27.996600  Pre-setting of DQS Precalculation

 2086 16:44:27.999558  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2087 16:44:28.007279  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2088 16:44:28.015994  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2089 16:44:28.016508  

 2090 16:44:28.016843  

 2091 16:44:28.019544  [Calibration Summary] 1600 Mbps

 2092 16:44:28.019974  CH 0, Rank 0

 2093 16:44:28.022953  SW Impedance     : PASS

 2094 16:44:28.023469  DUTY Scan        : NO K

 2095 16:44:28.025824  ZQ Calibration   : PASS

 2096 16:44:28.029448  Jitter Meter     : NO K

 2097 16:44:28.029875  CBT Training     : PASS

 2098 16:44:28.032792  Write leveling   : PASS

 2099 16:44:28.035985  RX DQS gating    : PASS

 2100 16:44:28.036468  RX DQ/DQS(RDDQC) : PASS

 2101 16:44:28.039730  TX DQ/DQS        : PASS

 2102 16:44:28.040249  RX DATLAT        : PASS

 2103 16:44:28.042925  RX DQ/DQS(Engine): PASS

 2104 16:44:28.045956  TX OE            : NO K

 2105 16:44:28.046380  All Pass.

 2106 16:44:28.046713  

 2107 16:44:28.047023  CH 0, Rank 1

 2108 16:44:28.049198  SW Impedance     : PASS

 2109 16:44:28.052980  DUTY Scan        : NO K

 2110 16:44:28.053515  ZQ Calibration   : PASS

 2111 16:44:28.055941  Jitter Meter     : NO K

 2112 16:44:28.059541  CBT Training     : PASS

 2113 16:44:28.059965  Write leveling   : PASS

 2114 16:44:28.062739  RX DQS gating    : PASS

 2115 16:44:28.065834  RX DQ/DQS(RDDQC) : PASS

 2116 16:44:28.066348  TX DQ/DQS        : PASS

 2117 16:44:28.069844  RX DATLAT        : PASS

 2118 16:44:28.072261  RX DQ/DQS(Engine): PASS

 2119 16:44:28.072687  TX OE            : NO K

 2120 16:44:28.075742  All Pass.

 2121 16:44:28.076221  

 2122 16:44:28.076565  CH 1, Rank 0

 2123 16:44:28.079249  SW Impedance     : PASS

 2124 16:44:28.079678  DUTY Scan        : NO K

 2125 16:44:28.082241  ZQ Calibration   : PASS

 2126 16:44:28.085554  Jitter Meter     : NO K

 2127 16:44:28.085979  CBT Training     : PASS

 2128 16:44:28.088813  Write leveling   : PASS

 2129 16:44:28.089373  RX DQS gating    : PASS

 2130 16:44:28.092330  RX DQ/DQS(RDDQC) : PASS

 2131 16:44:28.096009  TX DQ/DQS        : PASS

 2132 16:44:28.096434  RX DATLAT        : PASS

 2133 16:44:28.098709  RX DQ/DQS(Engine): PASS

 2134 16:44:28.102105  TX OE            : NO K

 2135 16:44:28.102529  All Pass.

 2136 16:44:28.102860  

 2137 16:44:28.103169  CH 1, Rank 1

 2138 16:44:28.105985  SW Impedance     : PASS

 2139 16:44:28.109108  DUTY Scan        : NO K

 2140 16:44:28.109642  ZQ Calibration   : PASS

 2141 16:44:28.112252  Jitter Meter     : NO K

 2142 16:44:28.115530  CBT Training     : PASS

 2143 16:44:28.115963  Write leveling   : PASS

 2144 16:44:28.118758  RX DQS gating    : PASS

 2145 16:44:28.122684  RX DQ/DQS(RDDQC) : PASS

 2146 16:44:28.123273  TX DQ/DQS        : PASS

 2147 16:44:28.125449  RX DATLAT        : PASS

 2148 16:44:28.129556  RX DQ/DQS(Engine): PASS

 2149 16:44:28.130079  TX OE            : NO K

 2150 16:44:28.132142  All Pass.

 2151 16:44:28.132565  

 2152 16:44:28.132898  DramC Write-DBI off

 2153 16:44:28.135999  	PER_BANK_REFRESH: Hybrid Mode

 2154 16:44:28.136424  TX_TRACKING: ON

 2155 16:44:28.138672  [GetDramInforAfterCalByMRR] Vendor 6.

 2156 16:44:28.145321  [GetDramInforAfterCalByMRR] Revision 606.

 2157 16:44:28.148587  [GetDramInforAfterCalByMRR] Revision 2 0.

 2158 16:44:28.149011  MR0 0x3b3b

 2159 16:44:28.149344  MR8 0x5151

 2160 16:44:28.151841  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2161 16:44:28.152264  

 2162 16:44:28.155665  MR0 0x3b3b

 2163 16:44:28.156087  MR8 0x5151

 2164 16:44:28.159121  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2165 16:44:28.159706  

 2166 16:44:28.168402  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2167 16:44:28.172131  [FAST_K] Save calibration result to emmc

 2168 16:44:28.175343  [FAST_K] Save calibration result to emmc

 2169 16:44:28.178608  dram_init: config_dvfs: 1

 2170 16:44:28.182118  dramc_set_vcore_voltage set vcore to 662500

 2171 16:44:28.185365  Read voltage for 1200, 2

 2172 16:44:28.185791  Vio18 = 0

 2173 16:44:28.186125  Vcore = 662500

 2174 16:44:28.188508  Vdram = 0

 2175 16:44:28.189041  Vddq = 0

 2176 16:44:28.189384  Vmddr = 0

 2177 16:44:28.195652  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2178 16:44:28.198520  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2179 16:44:28.201791  MEM_TYPE=3, freq_sel=15

 2180 16:44:28.205687  sv_algorithm_assistance_LP4_1600 

 2181 16:44:28.208501  ============ PULL DRAM RESETB DOWN ============

 2182 16:44:28.211699  ========== PULL DRAM RESETB DOWN end =========

 2183 16:44:28.218744  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2184 16:44:28.221883  =================================== 

 2185 16:44:28.222312  LPDDR4 DRAM CONFIGURATION

 2186 16:44:28.225171  =================================== 

 2187 16:44:28.228663  EX_ROW_EN[0]    = 0x0

 2188 16:44:28.231644  EX_ROW_EN[1]    = 0x0

 2189 16:44:28.232065  LP4Y_EN      = 0x0

 2190 16:44:28.235055  WORK_FSP     = 0x0

 2191 16:44:28.235541  WL           = 0x4

 2192 16:44:28.238416  RL           = 0x4

 2193 16:44:28.238941  BL           = 0x2

 2194 16:44:28.241828  RPST         = 0x0

 2195 16:44:28.242359  RD_PRE       = 0x0

 2196 16:44:28.244817  WR_PRE       = 0x1

 2197 16:44:28.245270  WR_PST       = 0x0

 2198 16:44:28.247710  DBI_WR       = 0x0

 2199 16:44:28.248159  DBI_RD       = 0x0

 2200 16:44:28.251525  OTF          = 0x1

 2201 16:44:28.254561  =================================== 

 2202 16:44:28.257856  =================================== 

 2203 16:44:28.258278  ANA top config

 2204 16:44:28.261452  =================================== 

 2205 16:44:28.264796  DLL_ASYNC_EN            =  0

 2206 16:44:28.267912  ALL_SLAVE_EN            =  0

 2207 16:44:28.270877  NEW_RANK_MODE           =  1

 2208 16:44:28.271353  DLL_IDLE_MODE           =  1

 2209 16:44:28.274600  LP45_APHY_COMB_EN       =  1

 2210 16:44:28.277665  TX_ODT_DIS              =  1

 2211 16:44:28.281240  NEW_8X_MODE             =  1

 2212 16:44:28.284606  =================================== 

 2213 16:44:28.287221  =================================== 

 2214 16:44:28.290469  data_rate                  = 2400

 2215 16:44:28.290555  CKR                        = 1

 2216 16:44:28.294074  DQ_P2S_RATIO               = 8

 2217 16:44:28.297171  =================================== 

 2218 16:44:28.300691  CA_P2S_RATIO               = 8

 2219 16:44:28.303839  DQ_CA_OPEN                 = 0

 2220 16:44:28.307095  DQ_SEMI_OPEN               = 0

 2221 16:44:28.310872  CA_SEMI_OPEN               = 0

 2222 16:44:28.310960  CA_FULL_RATE               = 0

 2223 16:44:28.314429  DQ_CKDIV4_EN               = 0

 2224 16:44:28.317081  CA_CKDIV4_EN               = 0

 2225 16:44:28.320448  CA_PREDIV_EN               = 0

 2226 16:44:28.323596  PH8_DLY                    = 17

 2227 16:44:28.327696  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2228 16:44:28.330123  DQ_AAMCK_DIV               = 4

 2229 16:44:28.330206  CA_AAMCK_DIV               = 4

 2230 16:44:28.333626  CA_ADMCK_DIV               = 4

 2231 16:44:28.337527  DQ_TRACK_CA_EN             = 0

 2232 16:44:28.340224  CA_PICK                    = 1200

 2233 16:44:28.343761  CA_MCKIO                   = 1200

 2234 16:44:28.347006  MCKIO_SEMI                 = 0

 2235 16:44:28.350171  PLL_FREQ                   = 2366

 2236 16:44:28.350254  DQ_UI_PI_RATIO             = 32

 2237 16:44:28.353961  CA_UI_PI_RATIO             = 0

 2238 16:44:28.357472  =================================== 

 2239 16:44:28.360366  =================================== 

 2240 16:44:28.363913  memory_type:LPDDR4         

 2241 16:44:28.366534  GP_NUM     : 10       

 2242 16:44:28.366622  SRAM_EN    : 1       

 2243 16:44:28.370284  MD32_EN    : 0       

 2244 16:44:28.373474  =================================== 

 2245 16:44:28.376550  [ANA_INIT] >>>>>>>>>>>>>> 

 2246 16:44:28.376653  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2247 16:44:28.380148  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2248 16:44:28.383205  =================================== 

 2249 16:44:28.386799  data_rate = 2400,PCW = 0X5b00

 2250 16:44:28.389774  =================================== 

 2251 16:44:28.393287  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2252 16:44:28.400534  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2253 16:44:28.406828  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2254 16:44:28.409771  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2255 16:44:28.413367  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2256 16:44:28.416264  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2257 16:44:28.419564  [ANA_INIT] flow start 

 2258 16:44:28.419647  [ANA_INIT] PLL >>>>>>>> 

 2259 16:44:28.422711  [ANA_INIT] PLL <<<<<<<< 

 2260 16:44:28.426419  [ANA_INIT] MIDPI >>>>>>>> 

 2261 16:44:28.429545  [ANA_INIT] MIDPI <<<<<<<< 

 2262 16:44:28.429690  [ANA_INIT] DLL >>>>>>>> 

 2263 16:44:28.433827  [ANA_INIT] DLL <<<<<<<< 

 2264 16:44:28.433978  [ANA_INIT] flow end 

 2265 16:44:28.440054  ============ LP4 DIFF to SE enter ============

 2266 16:44:28.442953  ============ LP4 DIFF to SE exit  ============

 2267 16:44:28.446170  [ANA_INIT] <<<<<<<<<<<<< 

 2268 16:44:28.450009  [Flow] Enable top DCM control >>>>> 

 2269 16:44:28.452829  [Flow] Enable top DCM control <<<<< 

 2270 16:44:28.456311  Enable DLL master slave shuffle 

 2271 16:44:28.459813  ============================================================== 

 2272 16:44:28.463153  Gating Mode config

 2273 16:44:28.466093  ============================================================== 

 2274 16:44:28.469938  Config description: 

 2275 16:44:28.479346  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2276 16:44:28.485971  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2277 16:44:28.489381  SELPH_MODE            0: By rank         1: By Phase 

 2278 16:44:28.495958  ============================================================== 

 2279 16:44:28.499849  GAT_TRACK_EN                 =  1

 2280 16:44:28.503089  RX_GATING_MODE               =  2

 2281 16:44:28.506312  RX_GATING_TRACK_MODE         =  2

 2282 16:44:28.509141  SELPH_MODE                   =  1

 2283 16:44:28.512533  PICG_EARLY_EN                =  1

 2284 16:44:28.515777  VALID_LAT_VALUE              =  1

 2285 16:44:28.518951  ============================================================== 

 2286 16:44:28.522883  Enter into Gating configuration >>>> 

 2287 16:44:28.525892  Exit from Gating configuration <<<< 

 2288 16:44:28.528881  Enter into  DVFS_PRE_config >>>>> 

 2289 16:44:28.542389  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2290 16:44:28.542851  Exit from  DVFS_PRE_config <<<<< 

 2291 16:44:28.545465  Enter into PICG configuration >>>> 

 2292 16:44:28.548677  Exit from PICG configuration <<<< 

 2293 16:44:28.552260  [RX_INPUT] configuration >>>>> 

 2294 16:44:28.555450  [RX_INPUT] configuration <<<<< 

 2295 16:44:28.562465  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2296 16:44:28.565451  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2297 16:44:28.573146  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2298 16:44:28.578878  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2299 16:44:28.585238  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2300 16:44:28.592012  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2301 16:44:28.595668  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2302 16:44:28.598512  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2303 16:44:28.601932  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2304 16:44:28.608938  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2305 16:44:28.611927  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2306 16:44:28.615201  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2307 16:44:28.618991  =================================== 

 2308 16:44:28.622374  LPDDR4 DRAM CONFIGURATION

 2309 16:44:28.625755  =================================== 

 2310 16:44:28.626178  EX_ROW_EN[0]    = 0x0

 2311 16:44:28.628548  EX_ROW_EN[1]    = 0x0

 2312 16:44:28.632285  LP4Y_EN      = 0x0

 2313 16:44:28.632704  WORK_FSP     = 0x0

 2314 16:44:28.635699  WL           = 0x4

 2315 16:44:28.636223  RL           = 0x4

 2316 16:44:28.638611  BL           = 0x2

 2317 16:44:28.639032  RPST         = 0x0

 2318 16:44:28.642098  RD_PRE       = 0x0

 2319 16:44:28.642679  WR_PRE       = 0x1

 2320 16:44:28.645310  WR_PST       = 0x0

 2321 16:44:28.645730  DBI_WR       = 0x0

 2322 16:44:28.648461  DBI_RD       = 0x0

 2323 16:44:28.648884  OTF          = 0x1

 2324 16:44:28.652067  =================================== 

 2325 16:44:28.655138  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2326 16:44:28.661958  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2327 16:44:28.665089  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2328 16:44:28.668617  =================================== 

 2329 16:44:28.671427  LPDDR4 DRAM CONFIGURATION

 2330 16:44:28.674763  =================================== 

 2331 16:44:28.675233  EX_ROW_EN[0]    = 0x10

 2332 16:44:28.678638  EX_ROW_EN[1]    = 0x0

 2333 16:44:28.681459  LP4Y_EN      = 0x0

 2334 16:44:28.681882  WORK_FSP     = 0x0

 2335 16:44:28.684625  WL           = 0x4

 2336 16:44:28.685025  RL           = 0x4

 2337 16:44:28.688306  BL           = 0x2

 2338 16:44:28.688732  RPST         = 0x0

 2339 16:44:28.691377  RD_PRE       = 0x0

 2340 16:44:28.691800  WR_PRE       = 0x1

 2341 16:44:28.694628  WR_PST       = 0x0

 2342 16:44:28.695054  DBI_WR       = 0x0

 2343 16:44:28.697935  DBI_RD       = 0x0

 2344 16:44:28.698357  OTF          = 0x1

 2345 16:44:28.701287  =================================== 

 2346 16:44:28.708264  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2347 16:44:28.708688  ==

 2348 16:44:28.711337  Dram Type= 6, Freq= 0, CH_0, rank 0

 2349 16:44:28.714433  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2350 16:44:28.717712  ==

 2351 16:44:28.718136  [Duty_Offset_Calibration]

 2352 16:44:28.721190  	B0:2	B1:0	CA:4

 2353 16:44:28.721612  

 2354 16:44:28.724623  [DutyScan_Calibration_Flow] k_type=0

 2355 16:44:28.732253  

 2356 16:44:28.732677  ==CLK 0==

 2357 16:44:28.735577  Final CLK duty delay cell = -4

 2358 16:44:28.738817  [-4] MAX Duty = 5031%(X100), DQS PI = 14

 2359 16:44:28.742268  [-4] MIN Duty = 4844%(X100), DQS PI = 8

 2360 16:44:28.745219  [-4] AVG Duty = 4937%(X100)

 2361 16:44:28.745635  

 2362 16:44:28.748589  CH0 CLK Duty spec in!! Max-Min= 187%

 2363 16:44:28.752565  [DutyScan_Calibration_Flow] ====Done====

 2364 16:44:28.752980  

 2365 16:44:28.754916  [DutyScan_Calibration_Flow] k_type=1

 2366 16:44:28.771952  

 2367 16:44:28.772466  ==DQS 0 ==

 2368 16:44:28.774822  Final DQS duty delay cell = 0

 2369 16:44:28.778161  [0] MAX Duty = 5156%(X100), DQS PI = 18

 2370 16:44:28.781652  [0] MIN Duty = 5093%(X100), DQS PI = 2

 2371 16:44:28.785192  [0] AVG Duty = 5124%(X100)

 2372 16:44:28.785608  

 2373 16:44:28.785935  ==DQS 1 ==

 2374 16:44:28.788584  Final DQS duty delay cell = 0

 2375 16:44:28.792036  [0] MAX Duty = 5125%(X100), DQS PI = 48

 2376 16:44:28.794851  [0] MIN Duty = 5000%(X100), DQS PI = 0

 2377 16:44:28.798106  [0] AVG Duty = 5062%(X100)

 2378 16:44:28.798522  

 2379 16:44:28.801209  CH0 DQS 0 Duty spec in!! Max-Min= 63%

 2380 16:44:28.801639  

 2381 16:44:28.804865  CH0 DQS 1 Duty spec in!! Max-Min= 125%

 2382 16:44:28.808874  [DutyScan_Calibration_Flow] ====Done====

 2383 16:44:28.809289  

 2384 16:44:28.811526  [DutyScan_Calibration_Flow] k_type=3

 2385 16:44:28.827697  

 2386 16:44:28.827954  ==DQM 0 ==

 2387 16:44:28.831205  Final DQM duty delay cell = 0

 2388 16:44:28.834261  [0] MAX Duty = 5125%(X100), DQS PI = 20

 2389 16:44:28.837504  [0] MIN Duty = 4875%(X100), DQS PI = 42

 2390 16:44:28.841314  [0] AVG Duty = 5000%(X100)

 2391 16:44:28.841395  

 2392 16:44:28.841458  ==DQM 1 ==

 2393 16:44:28.844175  Final DQM duty delay cell = 0

 2394 16:44:28.847439  [0] MAX Duty = 4969%(X100), DQS PI = 2

 2395 16:44:28.850866  [0] MIN Duty = 4876%(X100), DQS PI = 28

 2396 16:44:28.854919  [0] AVG Duty = 4922%(X100)

 2397 16:44:28.855000  

 2398 16:44:28.857778  CH0 DQM 0 Duty spec in!! Max-Min= 250%

 2399 16:44:28.857878  

 2400 16:44:28.861102  CH0 DQM 1 Duty spec in!! Max-Min= 93%

 2401 16:44:28.864849  [DutyScan_Calibration_Flow] ====Done====

 2402 16:44:28.865272  

 2403 16:44:28.868399  [DutyScan_Calibration_Flow] k_type=2

 2404 16:44:28.884850  

 2405 16:44:28.885327  ==DQ 0 ==

 2406 16:44:28.887804  Final DQ duty delay cell = 0

 2407 16:44:28.891280  [0] MAX Duty = 5125%(X100), DQS PI = 18

 2408 16:44:28.894282  [0] MIN Duty = 5000%(X100), DQS PI = 8

 2409 16:44:28.894698  [0] AVG Duty = 5062%(X100)

 2410 16:44:28.895024  

 2411 16:44:28.898480  ==DQ 1 ==

 2412 16:44:28.901402  Final DQ duty delay cell = 0

 2413 16:44:28.904191  [0] MAX Duty = 5156%(X100), DQS PI = 4

 2414 16:44:28.907714  [0] MIN Duty = 4938%(X100), DQS PI = 16

 2415 16:44:28.908233  [0] AVG Duty = 5047%(X100)

 2416 16:44:28.908690  

 2417 16:44:28.910968  CH0 DQ 0 Duty spec in!! Max-Min= 125%

 2418 16:44:28.911427  

 2419 16:44:28.917947  CH0 DQ 1 Duty spec in!! Max-Min= 218%

 2420 16:44:28.920922  [DutyScan_Calibration_Flow] ====Done====

 2421 16:44:28.921355  ==

 2422 16:44:28.924611  Dram Type= 6, Freq= 0, CH_1, rank 0

 2423 16:44:28.928270  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2424 16:44:28.928820  ==

 2425 16:44:28.930851  [Duty_Offset_Calibration]

 2426 16:44:28.931325  	B0:0	B1:-1	CA:3

 2427 16:44:28.931671  

 2428 16:44:28.934160  [DutyScan_Calibration_Flow] k_type=0

 2429 16:44:28.943656  

 2430 16:44:28.944081  ==CLK 0==

 2431 16:44:28.947281  Final CLK duty delay cell = -4

 2432 16:44:28.950866  [-4] MAX Duty = 5000%(X100), DQS PI = 0

 2433 16:44:28.953828  [-4] MIN Duty = 4876%(X100), DQS PI = 36

 2434 16:44:28.957502  [-4] AVG Duty = 4938%(X100)

 2435 16:44:28.957928  

 2436 16:44:28.960490  CH1 CLK Duty spec in!! Max-Min= 124%

 2437 16:44:28.963454  [DutyScan_Calibration_Flow] ====Done====

 2438 16:44:28.963882  

 2439 16:44:28.966945  [DutyScan_Calibration_Flow] k_type=1

 2440 16:44:28.982577  

 2441 16:44:28.983231  ==DQS 0 ==

 2442 16:44:28.985885  Final DQS duty delay cell = 0

 2443 16:44:28.989343  [0] MAX Duty = 5187%(X100), DQS PI = 18

 2444 16:44:28.992193  [0] MIN Duty = 4907%(X100), DQS PI = 38

 2445 16:44:28.995982  [0] AVG Duty = 5047%(X100)

 2446 16:44:28.996407  

 2447 16:44:28.996738  ==DQS 1 ==

 2448 16:44:28.998854  Final DQS duty delay cell = -4

 2449 16:44:29.002011  [-4] MAX Duty = 5031%(X100), DQS PI = 32

 2450 16:44:29.005114  [-4] MIN Duty = 4875%(X100), DQS PI = 0

 2451 16:44:29.008894  [-4] AVG Duty = 4953%(X100)

 2452 16:44:29.009359  

 2453 16:44:29.012289  CH1 DQS 0 Duty spec in!! Max-Min= 280%

 2454 16:44:29.012746  

 2455 16:44:29.015653  CH1 DQS 1 Duty spec in!! Max-Min= 156%

 2456 16:44:29.018582  [DutyScan_Calibration_Flow] ====Done====

 2457 16:44:29.019245  

 2458 16:44:29.022135  [DutyScan_Calibration_Flow] k_type=3

 2459 16:44:29.039326  

 2460 16:44:29.039842  ==DQM 0 ==

 2461 16:44:29.042282  Final DQM duty delay cell = 0

 2462 16:44:29.045786  [0] MAX Duty = 5031%(X100), DQS PI = 28

 2463 16:44:29.049146  [0] MIN Duty = 4813%(X100), DQS PI = 38

 2464 16:44:29.052554  [0] AVG Duty = 4922%(X100)

 2465 16:44:29.053023  

 2466 16:44:29.053358  ==DQM 1 ==

 2467 16:44:29.055538  Final DQM duty delay cell = 0

 2468 16:44:29.059271  [0] MAX Duty = 5000%(X100), DQS PI = 34

 2469 16:44:29.062458  [0] MIN Duty = 4844%(X100), DQS PI = 0

 2470 16:44:29.066002  [0] AVG Duty = 4922%(X100)

 2471 16:44:29.066525  

 2472 16:44:29.069157  CH1 DQM 0 Duty spec in!! Max-Min= 218%

 2473 16:44:29.069647  

 2474 16:44:29.072639  CH1 DQM 1 Duty spec in!! Max-Min= 156%

 2475 16:44:29.075906  [DutyScan_Calibration_Flow] ====Done====

 2476 16:44:29.076584  

 2477 16:44:29.078935  [DutyScan_Calibration_Flow] k_type=2

 2478 16:44:29.094806  

 2479 16:44:29.095287  ==DQ 0 ==

 2480 16:44:29.098440  Final DQ duty delay cell = -4

 2481 16:44:29.101554  [-4] MAX Duty = 5031%(X100), DQS PI = 30

 2482 16:44:29.105099  [-4] MIN Duty = 4844%(X100), DQS PI = 36

 2483 16:44:29.108197  [-4] AVG Duty = 4937%(X100)

 2484 16:44:29.108627  

 2485 16:44:29.108959  ==DQ 1 ==

 2486 16:44:29.111271  Final DQ duty delay cell = 0

 2487 16:44:29.114616  [0] MAX Duty = 5031%(X100), DQS PI = 34

 2488 16:44:29.117999  [0] MIN Duty = 4876%(X100), DQS PI = 0

 2489 16:44:29.121214  [0] AVG Duty = 4953%(X100)

 2490 16:44:29.121636  

 2491 16:44:29.124977  CH1 DQ 0 Duty spec in!! Max-Min= 187%

 2492 16:44:29.125398  

 2493 16:44:29.127734  CH1 DQ 1 Duty spec in!! Max-Min= 155%

 2494 16:44:29.131501  [DutyScan_Calibration_Flow] ====Done====

 2495 16:44:29.134527  nWR fixed to 30

 2496 16:44:29.138026  [ModeRegInit_LP4] CH0 RK0

 2497 16:44:29.138546  [ModeRegInit_LP4] CH0 RK1

 2498 16:44:29.141187  [ModeRegInit_LP4] CH1 RK0

 2499 16:44:29.144782  [ModeRegInit_LP4] CH1 RK1

 2500 16:44:29.145306  match AC timing 7

 2501 16:44:29.150860  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2502 16:44:29.154612  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2503 16:44:29.157602  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2504 16:44:29.164167  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2505 16:44:29.167749  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2506 16:44:29.168173  ==

 2507 16:44:29.171625  Dram Type= 6, Freq= 0, CH_0, rank 0

 2508 16:44:29.174469  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2509 16:44:29.174996  ==

 2510 16:44:29.181681  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2511 16:44:29.187959  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2512 16:44:29.195079  [CA 0] Center 39 (9~70) winsize 62

 2513 16:44:29.198445  [CA 1] Center 39 (9~70) winsize 62

 2514 16:44:29.202391  [CA 2] Center 35 (5~66) winsize 62

 2515 16:44:29.204948  [CA 3] Center 35 (5~66) winsize 62

 2516 16:44:29.208693  [CA 4] Center 33 (3~64) winsize 62

 2517 16:44:29.211837  [CA 5] Center 33 (3~63) winsize 61

 2518 16:44:29.212257  

 2519 16:44:29.214817  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2520 16:44:29.215266  

 2521 16:44:29.218692  [CATrainingPosCal] consider 1 rank data

 2522 16:44:29.221486  u2DelayCellTimex100 = 270/100 ps

 2523 16:44:29.224727  CA0 delay=39 (9~70),Diff = 6 PI (28 cell)

 2524 16:44:29.231468  CA1 delay=39 (9~70),Diff = 6 PI (28 cell)

 2525 16:44:29.234709  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2526 16:44:29.238363  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2527 16:44:29.241297  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 2528 16:44:29.245014  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 2529 16:44:29.245562  

 2530 16:44:29.248626  CA PerBit enable=1, Macro0, CA PI delay=33

 2531 16:44:29.249079  

 2532 16:44:29.251962  [CBTSetCACLKResult] CA Dly = 33

 2533 16:44:29.254810  CS Dly: 7 (0~38)

 2534 16:44:29.255257  ==

 2535 16:44:29.258285  Dram Type= 6, Freq= 0, CH_0, rank 1

 2536 16:44:29.261179  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2537 16:44:29.261616  ==

 2538 16:44:29.265085  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2539 16:44:29.271612  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2540 16:44:29.281304  [CA 0] Center 39 (9~70) winsize 62

 2541 16:44:29.284309  [CA 1] Center 39 (9~70) winsize 62

 2542 16:44:29.287611  [CA 2] Center 35 (5~66) winsize 62

 2543 16:44:29.290820  [CA 3] Center 35 (5~66) winsize 62

 2544 16:44:29.293987  [CA 4] Center 34 (4~65) winsize 62

 2545 16:44:29.297389  [CA 5] Center 33 (3~64) winsize 62

 2546 16:44:29.297810  

 2547 16:44:29.300934  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 2548 16:44:29.301467  

 2549 16:44:29.303990  [CATrainingPosCal] consider 2 rank data

 2550 16:44:29.307460  u2DelayCellTimex100 = 270/100 ps

 2551 16:44:29.310667  CA0 delay=39 (9~70),Diff = 6 PI (28 cell)

 2552 16:44:29.317488  CA1 delay=39 (9~70),Diff = 6 PI (28 cell)

 2553 16:44:29.320729  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2554 16:44:29.324534  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2555 16:44:29.327527  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 2556 16:44:29.330919  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 2557 16:44:29.331396  

 2558 16:44:29.333976  CA PerBit enable=1, Macro0, CA PI delay=33

 2559 16:44:29.334419  

 2560 16:44:29.337207  [CBTSetCACLKResult] CA Dly = 33

 2561 16:44:29.340626  CS Dly: 8 (0~41)

 2562 16:44:29.341208  

 2563 16:44:29.343475  ----->DramcWriteLeveling(PI) begin...

 2564 16:44:29.343900  ==

 2565 16:44:29.346961  Dram Type= 6, Freq= 0, CH_0, rank 0

 2566 16:44:29.350497  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2567 16:44:29.350927  ==

 2568 16:44:29.353543  Write leveling (Byte 0): 32 => 32

 2569 16:44:29.356856  Write leveling (Byte 1): 25 => 25

 2570 16:44:29.360547  DramcWriteLeveling(PI) end<-----

 2571 16:44:29.361059  

 2572 16:44:29.361415  ==

 2573 16:44:29.363517  Dram Type= 6, Freq= 0, CH_0, rank 0

 2574 16:44:29.366790  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2575 16:44:29.367242  ==

 2576 16:44:29.370072  [Gating] SW mode calibration

 2577 16:44:29.377015  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2578 16:44:29.383658  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2579 16:44:29.387281   0 15  0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 2580 16:44:29.390277   0 15  4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)

 2581 16:44:29.396504   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2582 16:44:29.399788   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2583 16:44:29.403144   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2584 16:44:29.409845   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2585 16:44:29.413023   0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 2586 16:44:29.416179   0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)

 2587 16:44:29.423158   1  0  0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)

 2588 16:44:29.426275   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 2589 16:44:29.429628   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2590 16:44:29.436239   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2591 16:44:29.439460   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2592 16:44:29.443043   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2593 16:44:29.449596   1  0 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)

 2594 16:44:29.452774   1  0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 2595 16:44:29.456034   1  1  0 | B1->B0 | 2b2b 4646 | 0 0 | (1 1) (0 0)

 2596 16:44:29.463092   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2597 16:44:29.465885   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2598 16:44:29.469615   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2599 16:44:29.476428   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2600 16:44:29.479227   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2601 16:44:29.482697   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2602 16:44:29.489572   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2603 16:44:29.492218   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2604 16:44:29.495774   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2605 16:44:29.502241   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2606 16:44:29.506097   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2607 16:44:29.509089   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2608 16:44:29.515345   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2609 16:44:29.518518   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2610 16:44:29.522600   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2611 16:44:29.529179   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2612 16:44:29.532793   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2613 16:44:29.535577   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2614 16:44:29.542129   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2615 16:44:29.545196   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2616 16:44:29.548675   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2617 16:44:29.552136   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2618 16:44:29.559130   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 2619 16:44:29.561957  Total UI for P1: 0, mck2ui 16

 2620 16:44:29.564976  best dqsien dly found for B0: ( 1,  3, 26)

 2621 16:44:29.568441   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2622 16:44:29.571688   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2623 16:44:29.578464   1  4  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2624 16:44:29.581606  Total UI for P1: 0, mck2ui 16

 2625 16:44:29.584951  best dqsien dly found for B1: ( 1,  4,  2)

 2626 16:44:29.588303  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2627 16:44:29.591621  best DQS1 dly(MCK, UI, PI) = (1, 4, 2)

 2628 16:44:29.591704  

 2629 16:44:29.594608  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2630 16:44:29.598116  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)

 2631 16:44:29.601377  [Gating] SW calibration Done

 2632 16:44:29.601454  ==

 2633 16:44:29.604629  Dram Type= 6, Freq= 0, CH_0, rank 0

 2634 16:44:29.608135  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2635 16:44:29.608213  ==

 2636 16:44:29.611081  RX Vref Scan: 0

 2637 16:44:29.611225  

 2638 16:44:29.611305  RX Vref 0 -> 0, step: 1

 2639 16:44:29.611387  

 2640 16:44:29.614507  RX Delay -40 -> 252, step: 8

 2641 16:44:29.621204  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 2642 16:44:29.624913  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2643 16:44:29.628247  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2644 16:44:29.631025  iDelay=200, Bit 3, Center 111 (40 ~ 183) 144

 2645 16:44:29.635362  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2646 16:44:29.641340  iDelay=200, Bit 5, Center 111 (40 ~ 183) 144

 2647 16:44:29.644258  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 2648 16:44:29.647515  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2649 16:44:29.651129  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2650 16:44:29.654486  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2651 16:44:29.660929  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 2652 16:44:29.664028  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 2653 16:44:29.667361  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 2654 16:44:29.670590  iDelay=200, Bit 13, Center 111 (40 ~ 183) 144

 2655 16:44:29.674051  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2656 16:44:29.680584  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 2657 16:44:29.680666  ==

 2658 16:44:29.683970  Dram Type= 6, Freq= 0, CH_0, rank 0

 2659 16:44:29.687514  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2660 16:44:29.687596  ==

 2661 16:44:29.687687  DQS Delay:

 2662 16:44:29.690746  DQS0 = 0, DQS1 = 0

 2663 16:44:29.690823  DQM Delay:

 2664 16:44:29.694205  DQM0 = 118, DQM1 = 107

 2665 16:44:29.694355  DQ Delay:

 2666 16:44:29.697383  DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111

 2667 16:44:29.700524  DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127

 2668 16:44:29.703979  DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103

 2669 16:44:29.707519  DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111

 2670 16:44:29.707600  

 2671 16:44:29.707664  

 2672 16:44:29.707723  ==

 2673 16:44:29.710723  Dram Type= 6, Freq= 0, CH_0, rank 0

 2674 16:44:29.717888  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2675 16:44:29.717968  ==

 2676 16:44:29.718031  

 2677 16:44:29.718091  

 2678 16:44:29.720891  	TX Vref Scan disable

 2679 16:44:29.720985   == TX Byte 0 ==

 2680 16:44:29.723853  Update DQ  dly =850 (3 ,2, 18)  DQ  OEN =(2 ,7)

 2681 16:44:29.730490  Update DQM dly =850 (3 ,2, 18)  DQM OEN =(2 ,7)

 2682 16:44:29.730567   == TX Byte 1 ==

 2683 16:44:29.734154  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 2684 16:44:29.740463  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 2685 16:44:29.740647  ==

 2686 16:44:29.743813  Dram Type= 6, Freq= 0, CH_0, rank 0

 2687 16:44:29.747136  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2688 16:44:29.747247  ==

 2689 16:44:29.759926  TX Vref=22, minBit 4, minWin=25, winSum=414

 2690 16:44:29.763445  TX Vref=24, minBit 10, minWin=25, winSum=419

 2691 16:44:29.766984  TX Vref=26, minBit 4, minWin=26, winSum=426

 2692 16:44:29.770061  TX Vref=28, minBit 5, minWin=26, winSum=431

 2693 16:44:29.773278  TX Vref=30, minBit 5, minWin=26, winSum=433

 2694 16:44:29.779954  TX Vref=32, minBit 4, minWin=26, winSum=428

 2695 16:44:29.783659  [TxChooseVref] Worse bit 5, Min win 26, Win sum 433, Final Vref 30

 2696 16:44:29.784137  

 2697 16:44:29.787103  Final TX Range 1 Vref 30

 2698 16:44:29.787558  

 2699 16:44:29.787910  ==

 2700 16:44:29.790262  Dram Type= 6, Freq= 0, CH_0, rank 0

 2701 16:44:29.793326  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2702 16:44:29.793955  ==

 2703 16:44:29.796226  

 2704 16:44:29.796756  

 2705 16:44:29.797290  	TX Vref Scan disable

 2706 16:44:29.800388   == TX Byte 0 ==

 2707 16:44:29.803579  Update DQ  dly =850 (3 ,2, 18)  DQ  OEN =(2 ,7)

 2708 16:44:29.806588  Update DQM dly =850 (3 ,2, 18)  DQM OEN =(2 ,7)

 2709 16:44:29.809883   == TX Byte 1 ==

 2710 16:44:29.813425  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 2711 16:44:29.819791  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 2712 16:44:29.820217  

 2713 16:44:29.820566  [DATLAT]

 2714 16:44:29.821084  Freq=1200, CH0 RK0

 2715 16:44:29.821613  

 2716 16:44:29.823533  DATLAT Default: 0xd

 2717 16:44:29.824093  0, 0xFFFF, sum = 0

 2718 16:44:29.826094  1, 0xFFFF, sum = 0

 2719 16:44:29.829912  2, 0xFFFF, sum = 0

 2720 16:44:29.830505  3, 0xFFFF, sum = 0

 2721 16:44:29.832851  4, 0xFFFF, sum = 0

 2722 16:44:29.833284  5, 0xFFFF, sum = 0

 2723 16:44:29.836040  6, 0xFFFF, sum = 0

 2724 16:44:29.836467  7, 0xFFFF, sum = 0

 2725 16:44:29.839794  8, 0xFFFF, sum = 0

 2726 16:44:29.840221  9, 0xFFFF, sum = 0

 2727 16:44:29.843032  10, 0xFFFF, sum = 0

 2728 16:44:29.843499  11, 0xFFFF, sum = 0

 2729 16:44:29.846028  12, 0x0, sum = 1

 2730 16:44:29.846454  13, 0x0, sum = 2

 2731 16:44:29.849331  14, 0x0, sum = 3

 2732 16:44:29.849762  15, 0x0, sum = 4

 2733 16:44:29.852678  best_step = 13

 2734 16:44:29.853103  

 2735 16:44:29.853431  ==

 2736 16:44:29.856427  Dram Type= 6, Freq= 0, CH_0, rank 0

 2737 16:44:29.859460  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2738 16:44:29.859899  ==

 2739 16:44:29.860234  RX Vref Scan: 1

 2740 16:44:29.860548  

 2741 16:44:29.863007  Set Vref Range= 32 -> 127

 2742 16:44:29.863454  

 2743 16:44:29.866684  RX Vref 32 -> 127, step: 1

 2744 16:44:29.867264  

 2745 16:44:29.869493  RX Delay -21 -> 252, step: 4

 2746 16:44:29.869912  

 2747 16:44:29.873104  Set Vref, RX VrefLevel [Byte0]: 32

 2748 16:44:29.875951                           [Byte1]: 32

 2749 16:44:29.876574  

 2750 16:44:29.879971  Set Vref, RX VrefLevel [Byte0]: 33

 2751 16:44:29.883031                           [Byte1]: 33

 2752 16:44:29.886762  

 2753 16:44:29.887219  Set Vref, RX VrefLevel [Byte0]: 34

 2754 16:44:29.892624                           [Byte1]: 34

 2755 16:44:29.893047  

 2756 16:44:29.896137  Set Vref, RX VrefLevel [Byte0]: 35

 2757 16:44:29.899476                           [Byte1]: 35

 2758 16:44:29.899913  

 2759 16:44:29.903129  Set Vref, RX VrefLevel [Byte0]: 36

 2760 16:44:29.905755                           [Byte1]: 36

 2761 16:44:29.910131  

 2762 16:44:29.910550  Set Vref, RX VrefLevel [Byte0]: 37

 2763 16:44:29.913408                           [Byte1]: 37

 2764 16:44:29.918171  

 2765 16:44:29.918590  Set Vref, RX VrefLevel [Byte0]: 38

 2766 16:44:29.921408                           [Byte1]: 38

 2767 16:44:29.926039  

 2768 16:44:29.926459  Set Vref, RX VrefLevel [Byte0]: 39

 2769 16:44:29.929195                           [Byte1]: 39

 2770 16:44:29.933809  

 2771 16:44:29.934229  Set Vref, RX VrefLevel [Byte0]: 40

 2772 16:44:29.937320                           [Byte1]: 40

 2773 16:44:29.941884  

 2774 16:44:29.942497  Set Vref, RX VrefLevel [Byte0]: 41

 2775 16:44:29.945055                           [Byte1]: 41

 2776 16:44:29.949851  

 2777 16:44:29.950272  Set Vref, RX VrefLevel [Byte0]: 42

 2778 16:44:29.952903                           [Byte1]: 42

 2779 16:44:29.958095  

 2780 16:44:29.958665  Set Vref, RX VrefLevel [Byte0]: 43

 2781 16:44:29.961233                           [Byte1]: 43

 2782 16:44:29.965516  

 2783 16:44:29.966147  Set Vref, RX VrefLevel [Byte0]: 44

 2784 16:44:29.968747                           [Byte1]: 44

 2785 16:44:29.973593  

 2786 16:44:29.974011  Set Vref, RX VrefLevel [Byte0]: 45

 2787 16:44:29.976876                           [Byte1]: 45

 2788 16:44:29.981514  

 2789 16:44:29.981936  Set Vref, RX VrefLevel [Byte0]: 46

 2790 16:44:29.984936                           [Byte1]: 46

 2791 16:44:29.989327  

 2792 16:44:29.989744  Set Vref, RX VrefLevel [Byte0]: 47

 2793 16:44:29.992428                           [Byte1]: 47

 2794 16:44:29.997281  

 2795 16:44:29.997702  Set Vref, RX VrefLevel [Byte0]: 48

 2796 16:44:30.000629                           [Byte1]: 48

 2797 16:44:30.005706  

 2798 16:44:30.006123  Set Vref, RX VrefLevel [Byte0]: 49

 2799 16:44:30.008433                           [Byte1]: 49

 2800 16:44:30.012987  

 2801 16:44:30.013459  Set Vref, RX VrefLevel [Byte0]: 50

 2802 16:44:30.016740                           [Byte1]: 50

 2803 16:44:30.020797  

 2804 16:44:30.021215  Set Vref, RX VrefLevel [Byte0]: 51

 2805 16:44:30.024567                           [Byte1]: 51

 2806 16:44:30.028928  

 2807 16:44:30.029354  Set Vref, RX VrefLevel [Byte0]: 52

 2808 16:44:30.032904                           [Byte1]: 52

 2809 16:44:30.036841  

 2810 16:44:30.037270  Set Vref, RX VrefLevel [Byte0]: 53

 2811 16:44:30.040327                           [Byte1]: 53

 2812 16:44:30.044808  

 2813 16:44:30.045236  Set Vref, RX VrefLevel [Byte0]: 54

 2814 16:44:30.047993                           [Byte1]: 54

 2815 16:44:30.052716  

 2816 16:44:30.053155  Set Vref, RX VrefLevel [Byte0]: 55

 2817 16:44:30.056680                           [Byte1]: 55

 2818 16:44:30.060924  

 2819 16:44:30.061356  Set Vref, RX VrefLevel [Byte0]: 56

 2820 16:44:30.063990                           [Byte1]: 56

 2821 16:44:30.068447  

 2822 16:44:30.068890  Set Vref, RX VrefLevel [Byte0]: 57

 2823 16:44:30.072021                           [Byte1]: 57

 2824 16:44:30.076765  

 2825 16:44:30.077204  Set Vref, RX VrefLevel [Byte0]: 58

 2826 16:44:30.080131                           [Byte1]: 58

 2827 16:44:30.084507  

 2828 16:44:30.084940  Set Vref, RX VrefLevel [Byte0]: 59

 2829 16:44:30.087638                           [Byte1]: 59

 2830 16:44:30.092504  

 2831 16:44:30.092939  Set Vref, RX VrefLevel [Byte0]: 60

 2832 16:44:30.097047                           [Byte1]: 60

 2833 16:44:30.100503  

 2834 16:44:30.100939  Set Vref, RX VrefLevel [Byte0]: 61

 2835 16:44:30.103617                           [Byte1]: 61

 2836 16:44:30.107982  

 2837 16:44:30.108416  Set Vref, RX VrefLevel [Byte0]: 62

 2838 16:44:30.111505                           [Byte1]: 62

 2839 16:44:30.116109  

 2840 16:44:30.116545  Set Vref, RX VrefLevel [Byte0]: 63

 2841 16:44:30.122702                           [Byte1]: 63

 2842 16:44:30.123132  

 2843 16:44:30.125812  Set Vref, RX VrefLevel [Byte0]: 64

 2844 16:44:30.129347                           [Byte1]: 64

 2845 16:44:30.129851  

 2846 16:44:30.132632  Set Vref, RX VrefLevel [Byte0]: 65

 2847 16:44:30.135870                           [Byte1]: 65

 2848 16:44:30.140175  

 2849 16:44:30.140603  Set Vref, RX VrefLevel [Byte0]: 66

 2850 16:44:30.143236                           [Byte1]: 66

 2851 16:44:30.147816  

 2852 16:44:30.148443  Set Vref, RX VrefLevel [Byte0]: 67

 2853 16:44:30.151138                           [Byte1]: 67

 2854 16:44:30.155697  

 2855 16:44:30.156121  Set Vref, RX VrefLevel [Byte0]: 68

 2856 16:44:30.159066                           [Byte1]: 68

 2857 16:44:30.163666  

 2858 16:44:30.164086  Set Vref, RX VrefLevel [Byte0]: 69

 2859 16:44:30.167095                           [Byte1]: 69

 2860 16:44:30.172043  

 2861 16:44:30.172479  Set Vref, RX VrefLevel [Byte0]: 70

 2862 16:44:30.174928                           [Byte1]: 70

 2863 16:44:30.179471  

 2864 16:44:30.179896  Final RX Vref Byte 0 = 56 to rank0

 2865 16:44:30.182567  Final RX Vref Byte 1 = 59 to rank0

 2866 16:44:30.186449  Final RX Vref Byte 0 = 56 to rank1

 2867 16:44:30.189421  Final RX Vref Byte 1 = 59 to rank1==

 2868 16:44:30.192456  Dram Type= 6, Freq= 0, CH_0, rank 0

 2869 16:44:30.199289  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2870 16:44:30.199735  ==

 2871 16:44:30.200126  DQS Delay:

 2872 16:44:30.202585  DQS0 = 0, DQS1 = 0

 2873 16:44:30.203230  DQM Delay:

 2874 16:44:30.203763  DQM0 = 117, DQM1 = 105

 2875 16:44:30.205911  DQ Delay:

 2876 16:44:30.209276  DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =112

 2877 16:44:30.212452  DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =120

 2878 16:44:30.216225  DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100

 2879 16:44:30.219543  DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114

 2880 16:44:30.219965  

 2881 16:44:30.220293  

 2882 16:44:30.225986  [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps

 2883 16:44:30.229603  CH0 RK0: MR19=403, MR18=4FF

 2884 16:44:30.236098  CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26

 2885 16:44:30.236521  

 2886 16:44:30.239486  ----->DramcWriteLeveling(PI) begin...

 2887 16:44:30.239916  ==

 2888 16:44:30.242785  Dram Type= 6, Freq= 0, CH_0, rank 1

 2889 16:44:30.245720  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2890 16:44:30.249274  ==

 2891 16:44:30.249694  Write leveling (Byte 0): 33 => 33

 2892 16:44:30.253005  Write leveling (Byte 1): 25 => 25

 2893 16:44:30.256085  DramcWriteLeveling(PI) end<-----

 2894 16:44:30.256507  

 2895 16:44:30.256836  ==

 2896 16:44:30.259077  Dram Type= 6, Freq= 0, CH_0, rank 1

 2897 16:44:30.265990  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2898 16:44:30.266458  ==

 2899 16:44:30.266795  [Gating] SW mode calibration

 2900 16:44:30.275502  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2901 16:44:30.279489  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2902 16:44:30.286138   0 15  0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)

 2903 16:44:30.289078   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2904 16:44:30.292222   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2905 16:44:30.295818   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2906 16:44:30.302254   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2907 16:44:30.305792   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2908 16:44:30.309695   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 2909 16:44:30.315424   0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)

 2910 16:44:30.319156   1  0  0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)

 2911 16:44:30.322446   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2912 16:44:30.328814   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2913 16:44:30.331887   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2914 16:44:30.335264   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2915 16:44:30.341694   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2916 16:44:30.345223   1  0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)

 2917 16:44:30.349213   1  0 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)

 2918 16:44:30.355288   1  1  0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)

 2919 16:44:30.358584   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2920 16:44:30.362756   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2921 16:44:30.368789   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2922 16:44:30.371804   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2923 16:44:30.375407   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2924 16:44:30.381826   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2925 16:44:30.384884   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2926 16:44:30.388611   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2927 16:44:30.395141   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2928 16:44:30.398463   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2929 16:44:30.401945   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2930 16:44:30.408280   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2931 16:44:30.411512   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2932 16:44:30.414987   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2933 16:44:30.421827   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2934 16:44:30.424829   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2935 16:44:30.428215   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2936 16:44:30.434618   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2937 16:44:30.438006   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2938 16:44:30.441505   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2939 16:44:30.447818   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2940 16:44:30.451163   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2941 16:44:30.455688   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2942 16:44:30.458520  Total UI for P1: 0, mck2ui 16

 2943 16:44:30.461651  best dqsien dly found for B0: ( 1,  3, 22)

 2944 16:44:30.468032   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2945 16:44:30.471160   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2946 16:44:30.474651  Total UI for P1: 0, mck2ui 16

 2947 16:44:30.478142  best dqsien dly found for B1: ( 1,  3, 30)

 2948 16:44:30.482105  best DQS0 dly(MCK, UI, PI) = (1, 3, 22)

 2949 16:44:30.484165  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2950 16:44:30.484795  

 2951 16:44:30.487534  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)

 2952 16:44:30.491370  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2953 16:44:30.494136  [Gating] SW calibration Done

 2954 16:44:30.494849  ==

 2955 16:44:30.497413  Dram Type= 6, Freq= 0, CH_0, rank 1

 2956 16:44:30.500690  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2957 16:44:30.504170  ==

 2958 16:44:30.504798  RX Vref Scan: 0

 2959 16:44:30.505441  

 2960 16:44:30.507292  RX Vref 0 -> 0, step: 1

 2961 16:44:30.507714  

 2962 16:44:30.508044  RX Delay -40 -> 252, step: 8

 2963 16:44:30.514361  iDelay=200, Bit 0, Center 111 (40 ~ 183) 144

 2964 16:44:30.517703  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2965 16:44:30.521204  iDelay=200, Bit 2, Center 115 (48 ~ 183) 136

 2966 16:44:30.524338  iDelay=200, Bit 3, Center 111 (40 ~ 183) 144

 2967 16:44:30.527523  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2968 16:44:30.534227  iDelay=200, Bit 5, Center 111 (40 ~ 183) 144

 2969 16:44:30.537394  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2970 16:44:30.541284  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2971 16:44:30.544445  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2972 16:44:30.547485  iDelay=200, Bit 9, Center 91 (24 ~ 159) 136

 2973 16:44:30.554699  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 2974 16:44:30.557431  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 2975 16:44:30.561234  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2976 16:44:30.564433  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 2977 16:44:30.567778  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2978 16:44:30.574089  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 2979 16:44:30.574515  ==

 2980 16:44:30.577270  Dram Type= 6, Freq= 0, CH_0, rank 1

 2981 16:44:30.580908  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2982 16:44:30.581426  ==

 2983 16:44:30.581876  DQS Delay:

 2984 16:44:30.584161  DQS0 = 0, DQS1 = 0

 2985 16:44:30.584587  DQM Delay:

 2986 16:44:30.587807  DQM0 = 117, DQM1 = 109

 2987 16:44:30.588275  DQ Delay:

 2988 16:44:30.590751  DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111

 2989 16:44:30.593635  DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127

 2990 16:44:30.597238  DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103

 2991 16:44:30.600413  DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115

 2992 16:44:30.600498  

 2993 16:44:30.603474  

 2994 16:44:30.603566  ==

 2995 16:44:30.607056  Dram Type= 6, Freq= 0, CH_0, rank 1

 2996 16:44:30.610556  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2997 16:44:30.610644  ==

 2998 16:44:30.610715  

 2999 16:44:30.610776  

 3000 16:44:30.613937  	TX Vref Scan disable

 3001 16:44:30.614020   == TX Byte 0 ==

 3002 16:44:30.620534  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 3003 16:44:30.624146  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 3004 16:44:30.624238   == TX Byte 1 ==

 3005 16:44:30.630048  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3006 16:44:30.633455  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3007 16:44:30.633537  ==

 3008 16:44:30.636521  Dram Type= 6, Freq= 0, CH_0, rank 1

 3009 16:44:30.640028  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3010 16:44:30.640102  ==

 3011 16:44:30.653479  TX Vref=22, minBit 14, minWin=25, winSum=417

 3012 16:44:30.656691  TX Vref=24, minBit 8, minWin=25, winSum=423

 3013 16:44:30.659746  TX Vref=26, minBit 5, minWin=26, winSum=428

 3014 16:44:30.663636  TX Vref=28, minBit 2, minWin=26, winSum=430

 3015 16:44:30.667097  TX Vref=30, minBit 8, minWin=26, winSum=430

 3016 16:44:30.673177  TX Vref=32, minBit 5, minWin=26, winSum=425

 3017 16:44:30.676824  [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 28

 3018 16:44:30.677256  

 3019 16:44:30.679868  Final TX Range 1 Vref 28

 3020 16:44:30.680311  

 3021 16:44:30.680728  ==

 3022 16:44:30.683234  Dram Type= 6, Freq= 0, CH_0, rank 1

 3023 16:44:30.686915  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3024 16:44:30.687392  ==

 3025 16:44:30.690214  

 3026 16:44:30.690659  

 3027 16:44:30.690995  	TX Vref Scan disable

 3028 16:44:30.693185   == TX Byte 0 ==

 3029 16:44:30.696560  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 3030 16:44:30.703423  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 3031 16:44:30.703880   == TX Byte 1 ==

 3032 16:44:30.706362  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3033 16:44:30.713166  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3034 16:44:30.713691  

 3035 16:44:30.714027  [DATLAT]

 3036 16:44:30.714339  Freq=1200, CH0 RK1

 3037 16:44:30.714646  

 3038 16:44:30.716432  DATLAT Default: 0xd

 3039 16:44:30.719710  0, 0xFFFF, sum = 0

 3040 16:44:30.720186  1, 0xFFFF, sum = 0

 3041 16:44:30.723228  2, 0xFFFF, sum = 0

 3042 16:44:30.723666  3, 0xFFFF, sum = 0

 3043 16:44:30.726684  4, 0xFFFF, sum = 0

 3044 16:44:30.727117  5, 0xFFFF, sum = 0

 3045 16:44:30.729624  6, 0xFFFF, sum = 0

 3046 16:44:30.730116  7, 0xFFFF, sum = 0

 3047 16:44:30.733073  8, 0xFFFF, sum = 0

 3048 16:44:30.733671  9, 0xFFFF, sum = 0

 3049 16:44:30.736457  10, 0xFFFF, sum = 0

 3050 16:44:30.736892  11, 0xFFFF, sum = 0

 3051 16:44:30.739759  12, 0x0, sum = 1

 3052 16:44:30.740195  13, 0x0, sum = 2

 3053 16:44:30.743150  14, 0x0, sum = 3

 3054 16:44:30.743622  15, 0x0, sum = 4

 3055 16:44:30.746191  best_step = 13

 3056 16:44:30.746621  

 3057 16:44:30.746972  ==

 3058 16:44:30.750012  Dram Type= 6, Freq= 0, CH_0, rank 1

 3059 16:44:30.752569  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3060 16:44:30.753014  ==

 3061 16:44:30.753375  RX Vref Scan: 0

 3062 16:44:30.756437  

 3063 16:44:30.756886  RX Vref 0 -> 0, step: 1

 3064 16:44:30.757240  

 3065 16:44:30.759572  RX Delay -21 -> 252, step: 4

 3066 16:44:30.766176  iDelay=195, Bit 0, Center 114 (47 ~ 182) 136

 3067 16:44:30.769479  iDelay=195, Bit 1, Center 118 (51 ~ 186) 136

 3068 16:44:30.772629  iDelay=195, Bit 2, Center 112 (47 ~ 178) 132

 3069 16:44:30.776364  iDelay=195, Bit 3, Center 114 (47 ~ 182) 136

 3070 16:44:30.779457  iDelay=195, Bit 4, Center 118 (51 ~ 186) 136

 3071 16:44:30.785711  iDelay=195, Bit 5, Center 110 (43 ~ 178) 136

 3072 16:44:30.789523  iDelay=195, Bit 6, Center 126 (59 ~ 194) 136

 3073 16:44:30.792846  iDelay=195, Bit 7, Center 122 (55 ~ 190) 136

 3074 16:44:30.796134  iDelay=195, Bit 8, Center 96 (31 ~ 162) 132

 3075 16:44:30.800415  iDelay=195, Bit 9, Center 92 (27 ~ 158) 132

 3076 16:44:30.802711  iDelay=195, Bit 10, Center 110 (43 ~ 178) 136

 3077 16:44:30.808977  iDelay=195, Bit 11, Center 102 (35 ~ 170) 136

 3078 16:44:30.813085  iDelay=195, Bit 12, Center 112 (47 ~ 178) 132

 3079 16:44:30.815860  iDelay=195, Bit 13, Center 110 (43 ~ 178) 136

 3080 16:44:30.818885  iDelay=195, Bit 14, Center 118 (55 ~ 182) 128

 3081 16:44:30.825838  iDelay=195, Bit 15, Center 112 (47 ~ 178) 132

 3082 16:44:30.826273  ==

 3083 16:44:30.829188  Dram Type= 6, Freq= 0, CH_0, rank 1

 3084 16:44:30.832056  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3085 16:44:30.832514  ==

 3086 16:44:30.832859  DQS Delay:

 3087 16:44:30.835312  DQS0 = 0, DQS1 = 0

 3088 16:44:30.835772  DQM Delay:

 3089 16:44:30.839316  DQM0 = 116, DQM1 = 106

 3090 16:44:30.839746  DQ Delay:

 3091 16:44:30.842158  DQ0 =114, DQ1 =118, DQ2 =112, DQ3 =114

 3092 16:44:30.845924  DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122

 3093 16:44:30.848645  DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102

 3094 16:44:30.852185  DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112

 3095 16:44:30.852635  

 3096 16:44:30.852977  

 3097 16:44:30.862183  [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps

 3098 16:44:30.865401  CH0 RK1: MR19=303, MR18=FDFB

 3099 16:44:30.872653  CH0_RK1: MR19=0x303, MR18=0xFDFB, DQSOSC=411, MR23=63, INC=38, DEC=25

 3100 16:44:30.873082  [RxdqsGatingPostProcess] freq 1200

 3101 16:44:30.879266  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3102 16:44:30.882549  best DQS0 dly(2T, 0.5T) = (0, 11)

 3103 16:44:30.885566  best DQS1 dly(2T, 0.5T) = (0, 12)

 3104 16:44:30.889250  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3105 16:44:30.892084  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3106 16:44:30.895356  best DQS0 dly(2T, 0.5T) = (0, 11)

 3107 16:44:30.898658  best DQS1 dly(2T, 0.5T) = (0, 11)

 3108 16:44:30.901843  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3109 16:44:30.905117  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3110 16:44:30.908430  Pre-setting of DQS Precalculation

 3111 16:44:30.911798  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3112 16:44:30.912268  ==

 3113 16:44:30.915087  Dram Type= 6, Freq= 0, CH_1, rank 0

 3114 16:44:30.918769  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3115 16:44:30.919229  ==

 3116 16:44:30.925894  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3117 16:44:30.931630  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3118 16:44:30.940152  [CA 0] Center 38 (8~68) winsize 61

 3119 16:44:30.942964  [CA 1] Center 37 (7~68) winsize 62

 3120 16:44:30.946519  [CA 2] Center 35 (5~65) winsize 61

 3121 16:44:30.949611  [CA 3] Center 34 (4~64) winsize 61

 3122 16:44:30.952866  [CA 4] Center 34 (4~65) winsize 62

 3123 16:44:30.956048  [CA 5] Center 33 (4~63) winsize 60

 3124 16:44:30.956471  

 3125 16:44:30.959423  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3126 16:44:30.959869  

 3127 16:44:30.963248  [CATrainingPosCal] consider 1 rank data

 3128 16:44:30.966516  u2DelayCellTimex100 = 270/100 ps

 3129 16:44:30.969603  CA0 delay=38 (8~68),Diff = 5 PI (24 cell)

 3130 16:44:30.972856  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3131 16:44:30.979796  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3132 16:44:30.983137  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3133 16:44:30.986248  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 3134 16:44:30.989395  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3135 16:44:30.989853  

 3136 16:44:30.992977  CA PerBit enable=1, Macro0, CA PI delay=33

 3137 16:44:30.993401  

 3138 16:44:30.996117  [CBTSetCACLKResult] CA Dly = 33

 3139 16:44:30.996589  CS Dly: 5 (0~36)

 3140 16:44:30.999274  ==

 3141 16:44:31.002535  Dram Type= 6, Freq= 0, CH_1, rank 1

 3142 16:44:31.005785  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3143 16:44:31.006211  ==

 3144 16:44:31.009197  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3145 16:44:31.016018  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3146 16:44:31.025118  [CA 0] Center 37 (7~68) winsize 62

 3147 16:44:31.029000  [CA 1] Center 38 (8~68) winsize 61

 3148 16:44:31.031663  [CA 2] Center 35 (5~65) winsize 61

 3149 16:44:31.035337  [CA 3] Center 33 (3~64) winsize 62

 3150 16:44:31.038283  [CA 4] Center 33 (3~64) winsize 62

 3151 16:44:31.041872  [CA 5] Center 33 (3~63) winsize 61

 3152 16:44:31.042297  

 3153 16:44:31.045118  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 3154 16:44:31.045540  

 3155 16:44:31.048335  [CATrainingPosCal] consider 2 rank data

 3156 16:44:31.051863  u2DelayCellTimex100 = 270/100 ps

 3157 16:44:31.055063  CA0 delay=38 (8~68),Diff = 5 PI (24 cell)

 3158 16:44:31.061899  CA1 delay=38 (8~68),Diff = 5 PI (24 cell)

 3159 16:44:31.065578  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3160 16:44:31.068365  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3161 16:44:31.071641  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3162 16:44:31.074700  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3163 16:44:31.075137  

 3164 16:44:31.078276  CA PerBit enable=1, Macro0, CA PI delay=33

 3165 16:44:31.078694  

 3166 16:44:31.081620  [CBTSetCACLKResult] CA Dly = 33

 3167 16:44:31.082091  CS Dly: 6 (0~38)

 3168 16:44:31.085755  

 3169 16:44:31.088268  ----->DramcWriteLeveling(PI) begin...

 3170 16:44:31.088729  ==

 3171 16:44:31.091834  Dram Type= 6, Freq= 0, CH_1, rank 0

 3172 16:44:31.094800  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3173 16:44:31.095493  ==

 3174 16:44:31.098677  Write leveling (Byte 0): 25 => 25

 3175 16:44:31.101315  Write leveling (Byte 1): 29 => 29

 3176 16:44:31.104635  DramcWriteLeveling(PI) end<-----

 3177 16:44:31.105057  

 3178 16:44:31.105388  ==

 3179 16:44:31.107900  Dram Type= 6, Freq= 0, CH_1, rank 0

 3180 16:44:31.111609  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3181 16:44:31.112035  ==

 3182 16:44:31.115010  [Gating] SW mode calibration

 3183 16:44:31.121522  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3184 16:44:31.127754  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3185 16:44:31.131747   0 15  0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 3186 16:44:31.135280   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3187 16:44:31.141082   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3188 16:44:31.144432   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3189 16:44:31.147959   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3190 16:44:31.154654   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3191 16:44:31.157712   0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 3192 16:44:31.161398   0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)

 3193 16:44:31.167906   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3194 16:44:31.170789   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3195 16:44:31.174181   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3196 16:44:31.180688   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3197 16:44:31.183867   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3198 16:44:31.187837   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3199 16:44:31.193995   1  0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 3200 16:44:31.197331   1  0 28 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)

 3201 16:44:31.200401   1  1  0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 3202 16:44:31.207778   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3203 16:44:31.210297   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3204 16:44:31.213729   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3205 16:44:31.220278   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3206 16:44:31.223771   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3207 16:44:31.226656   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3208 16:44:31.233309   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3209 16:44:31.236930   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3210 16:44:31.240213   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3211 16:44:31.247220   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3212 16:44:31.250129   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3213 16:44:31.253290   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3214 16:44:31.259896   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3215 16:44:31.263278   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3216 16:44:31.266328   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3217 16:44:31.273008   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3218 16:44:31.276495   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3219 16:44:31.279085   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3220 16:44:31.285776   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3221 16:44:31.289355   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3222 16:44:31.292652   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3223 16:44:31.299988   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3224 16:44:31.302638   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3225 16:44:31.305772  Total UI for P1: 0, mck2ui 16

 3226 16:44:31.309446  best dqsien dly found for B0: ( 1,  3, 26)

 3227 16:44:31.312581  Total UI for P1: 0, mck2ui 16

 3228 16:44:31.315706  best dqsien dly found for B1: ( 1,  3, 26)

 3229 16:44:31.319538  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3230 16:44:31.322473  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3231 16:44:31.322609  

 3232 16:44:31.325922  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3233 16:44:31.329034  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3234 16:44:31.332695  [Gating] SW calibration Done

 3235 16:44:31.332872  ==

 3236 16:44:31.335670  Dram Type= 6, Freq= 0, CH_1, rank 0

 3237 16:44:31.339493  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3238 16:44:31.339748  ==

 3239 16:44:31.343135  RX Vref Scan: 0

 3240 16:44:31.343467  

 3241 16:44:31.345735  RX Vref 0 -> 0, step: 1

 3242 16:44:31.346048  

 3243 16:44:31.346354  RX Delay -40 -> 252, step: 8

 3244 16:44:31.352561  iDelay=200, Bit 0, Center 123 (48 ~ 199) 152

 3245 16:44:31.355684  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 3246 16:44:31.359145  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3247 16:44:31.362682  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 3248 16:44:31.366642  iDelay=200, Bit 4, Center 111 (40 ~ 183) 144

 3249 16:44:31.373112  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3250 16:44:31.375766  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 3251 16:44:31.379002  iDelay=200, Bit 7, Center 111 (40 ~ 183) 144

 3252 16:44:31.382405  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3253 16:44:31.385731  iDelay=200, Bit 9, Center 103 (32 ~ 175) 144

 3254 16:44:31.392398  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3255 16:44:31.395779  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3256 16:44:31.398962  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3257 16:44:31.402153  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3258 16:44:31.408877  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3259 16:44:31.412287  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 3260 16:44:31.412719  ==

 3261 16:44:31.415515  Dram Type= 6, Freq= 0, CH_1, rank 0

 3262 16:44:31.419166  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3263 16:44:31.419704  ==

 3264 16:44:31.420047  DQS Delay:

 3265 16:44:31.422360  DQS0 = 0, DQS1 = 0

 3266 16:44:31.422728  DQM Delay:

 3267 16:44:31.425849  DQM0 = 116, DQM1 = 112

 3268 16:44:31.426306  DQ Delay:

 3269 16:44:31.429278  DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115

 3270 16:44:31.432129  DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111

 3271 16:44:31.435297  DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107

 3272 16:44:31.441836  DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119

 3273 16:44:31.442258  

 3274 16:44:31.442599  

 3275 16:44:31.442911  ==

 3276 16:44:31.445614  Dram Type= 6, Freq= 0, CH_1, rank 0

 3277 16:44:31.449017  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3278 16:44:31.449458  ==

 3279 16:44:31.449886  

 3280 16:44:31.450288  

 3281 16:44:31.452056  	TX Vref Scan disable

 3282 16:44:31.452488   == TX Byte 0 ==

 3283 16:44:31.458589  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3284 16:44:31.462632  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3285 16:44:31.463128   == TX Byte 1 ==

 3286 16:44:31.468534  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 3287 16:44:31.472060  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 3288 16:44:31.472527  ==

 3289 16:44:31.475460  Dram Type= 6, Freq= 0, CH_1, rank 0

 3290 16:44:31.478405  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3291 16:44:31.478935  ==

 3292 16:44:31.491293  TX Vref=22, minBit 3, minWin=25, winSum=411

 3293 16:44:31.494830  TX Vref=24, minBit 3, minWin=25, winSum=422

 3294 16:44:31.498283  TX Vref=26, minBit 3, minWin=25, winSum=421

 3295 16:44:31.501479  TX Vref=28, minBit 8, minWin=26, winSum=429

 3296 16:44:31.504487  TX Vref=30, minBit 7, minWin=26, winSum=429

 3297 16:44:31.511131  TX Vref=32, minBit 2, minWin=26, winSum=430

 3298 16:44:31.514642  [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 32

 3299 16:44:31.515067  

 3300 16:44:31.518102  Final TX Range 1 Vref 32

 3301 16:44:31.518522  

 3302 16:44:31.518851  ==

 3303 16:44:31.521366  Dram Type= 6, Freq= 0, CH_1, rank 0

 3304 16:44:31.524617  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3305 16:44:31.525042  ==

 3306 16:44:31.528303  

 3307 16:44:31.528722  

 3308 16:44:31.529052  	TX Vref Scan disable

 3309 16:44:31.531047   == TX Byte 0 ==

 3310 16:44:31.534492  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3311 16:44:31.537624  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3312 16:44:31.541614   == TX Byte 1 ==

 3313 16:44:31.544654  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3314 16:44:31.547980  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3315 16:44:31.551127  

 3316 16:44:31.551746  [DATLAT]

 3317 16:44:31.552260  Freq=1200, CH1 RK0

 3318 16:44:31.552590  

 3319 16:44:31.554721  DATLAT Default: 0xd

 3320 16:44:31.555139  0, 0xFFFF, sum = 0

 3321 16:44:31.558057  1, 0xFFFF, sum = 0

 3322 16:44:31.558484  2, 0xFFFF, sum = 0

 3323 16:44:31.561007  3, 0xFFFF, sum = 0

 3324 16:44:31.561441  4, 0xFFFF, sum = 0

 3325 16:44:31.564438  5, 0xFFFF, sum = 0

 3326 16:44:31.567869  6, 0xFFFF, sum = 0

 3327 16:44:31.568295  7, 0xFFFF, sum = 0

 3328 16:44:31.570950  8, 0xFFFF, sum = 0

 3329 16:44:31.571418  9, 0xFFFF, sum = 0

 3330 16:44:31.574023  10, 0xFFFF, sum = 0

 3331 16:44:31.574539  11, 0xFFFF, sum = 0

 3332 16:44:31.577936  12, 0x0, sum = 1

 3333 16:44:31.578366  13, 0x0, sum = 2

 3334 16:44:31.581143  14, 0x0, sum = 3

 3335 16:44:31.581571  15, 0x0, sum = 4

 3336 16:44:31.581908  best_step = 13

 3337 16:44:31.584197  

 3338 16:44:31.584615  ==

 3339 16:44:31.587753  Dram Type= 6, Freq= 0, CH_1, rank 0

 3340 16:44:31.590702  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3341 16:44:31.591123  ==

 3342 16:44:31.591485  RX Vref Scan: 1

 3343 16:44:31.591794  

 3344 16:44:31.594319  Set Vref Range= 32 -> 127

 3345 16:44:31.594737  

 3346 16:44:31.597719  RX Vref 32 -> 127, step: 1

 3347 16:44:31.598275  

 3348 16:44:31.600988  RX Delay -13 -> 252, step: 4

 3349 16:44:31.601600  

 3350 16:44:31.604727  Set Vref, RX VrefLevel [Byte0]: 32

 3351 16:44:31.607496                           [Byte1]: 32

 3352 16:44:31.607903  

 3353 16:44:31.611050  Set Vref, RX VrefLevel [Byte0]: 33

 3354 16:44:31.613997                           [Byte1]: 33

 3355 16:44:31.617172  

 3356 16:44:31.617590  Set Vref, RX VrefLevel [Byte0]: 34

 3357 16:44:31.620928                           [Byte1]: 34

 3358 16:44:31.625025  

 3359 16:44:31.625442  Set Vref, RX VrefLevel [Byte0]: 35

 3360 16:44:31.628869                           [Byte1]: 35

 3361 16:44:31.633630  

 3362 16:44:31.634046  Set Vref, RX VrefLevel [Byte0]: 36

 3363 16:44:31.636461                           [Byte1]: 36

 3364 16:44:31.640871  

 3365 16:44:31.641284  Set Vref, RX VrefLevel [Byte0]: 37

 3366 16:44:31.644383                           [Byte1]: 37

 3367 16:44:31.648901  

 3368 16:44:31.649317  Set Vref, RX VrefLevel [Byte0]: 38

 3369 16:44:31.652176                           [Byte1]: 38

 3370 16:44:31.656825  

 3371 16:44:31.657259  Set Vref, RX VrefLevel [Byte0]: 39

 3372 16:44:31.659999                           [Byte1]: 39

 3373 16:44:31.665181  

 3374 16:44:31.667848  Set Vref, RX VrefLevel [Byte0]: 40

 3375 16:44:31.671412                           [Byte1]: 40

 3376 16:44:31.671850  

 3377 16:44:31.674346  Set Vref, RX VrefLevel [Byte0]: 41

 3378 16:44:31.677709                           [Byte1]: 41

 3379 16:44:31.678123  

 3380 16:44:31.681040  Set Vref, RX VrefLevel [Byte0]: 42

 3381 16:44:31.684863                           [Byte1]: 42

 3382 16:44:31.688371  

 3383 16:44:31.688784  Set Vref, RX VrefLevel [Byte0]: 43

 3384 16:44:31.691844                           [Byte1]: 43

 3385 16:44:31.696006  

 3386 16:44:31.696418  Set Vref, RX VrefLevel [Byte0]: 44

 3387 16:44:31.699538                           [Byte1]: 44

 3388 16:44:31.704064  

 3389 16:44:31.704474  Set Vref, RX VrefLevel [Byte0]: 45

 3390 16:44:31.707462                           [Byte1]: 45

 3391 16:44:31.712291  

 3392 16:44:31.712819  Set Vref, RX VrefLevel [Byte0]: 46

 3393 16:44:31.715476                           [Byte1]: 46

 3394 16:44:31.719861  

 3395 16:44:31.720343  Set Vref, RX VrefLevel [Byte0]: 47

 3396 16:44:31.723274                           [Byte1]: 47

 3397 16:44:31.728164  

 3398 16:44:31.728577  Set Vref, RX VrefLevel [Byte0]: 48

 3399 16:44:31.731009                           [Byte1]: 48

 3400 16:44:31.735661  

 3401 16:44:31.736075  Set Vref, RX VrefLevel [Byte0]: 49

 3402 16:44:31.739255                           [Byte1]: 49

 3403 16:44:31.743882  

 3404 16:44:31.744388  Set Vref, RX VrefLevel [Byte0]: 50

 3405 16:44:31.746720                           [Byte1]: 50

 3406 16:44:31.751255  

 3407 16:44:31.751670  Set Vref, RX VrefLevel [Byte0]: 51

 3408 16:44:31.754949                           [Byte1]: 51

 3409 16:44:31.759926  

 3410 16:44:31.760341  Set Vref, RX VrefLevel [Byte0]: 52

 3411 16:44:31.762509                           [Byte1]: 52

 3412 16:44:31.767674  

 3413 16:44:31.768195  Set Vref, RX VrefLevel [Byte0]: 53

 3414 16:44:31.770124                           [Byte1]: 53

 3415 16:44:31.774778  

 3416 16:44:31.775237  Set Vref, RX VrefLevel [Byte0]: 54

 3417 16:44:31.778395                           [Byte1]: 54

 3418 16:44:31.782847  

 3419 16:44:31.783327  Set Vref, RX VrefLevel [Byte0]: 55

 3420 16:44:31.786547                           [Byte1]: 55

 3421 16:44:31.791480  

 3422 16:44:31.791892  Set Vref, RX VrefLevel [Byte0]: 56

 3423 16:44:31.794372                           [Byte1]: 56

 3424 16:44:31.798638  

 3425 16:44:31.799050  Set Vref, RX VrefLevel [Byte0]: 57

 3426 16:44:31.802301                           [Byte1]: 57

 3427 16:44:31.806300  

 3428 16:44:31.806736  Set Vref, RX VrefLevel [Byte0]: 58

 3429 16:44:31.810477                           [Byte1]: 58

 3430 16:44:31.814055  

 3431 16:44:31.814472  Set Vref, RX VrefLevel [Byte0]: 59

 3432 16:44:31.817370                           [Byte1]: 59

 3433 16:44:31.822083  

 3434 16:44:31.822501  Set Vref, RX VrefLevel [Byte0]: 60

 3435 16:44:31.825610                           [Byte1]: 60

 3436 16:44:31.831675  

 3437 16:44:31.832092  Set Vref, RX VrefLevel [Byte0]: 61

 3438 16:44:31.833367                           [Byte1]: 61

 3439 16:44:31.838432  

 3440 16:44:31.838849  Set Vref, RX VrefLevel [Byte0]: 62

 3441 16:44:31.841656                           [Byte1]: 62

 3442 16:44:31.846008  

 3443 16:44:31.846491  Set Vref, RX VrefLevel [Byte0]: 63

 3444 16:44:31.849355                           [Byte1]: 63

 3445 16:44:31.853824  

 3446 16:44:31.854236  Set Vref, RX VrefLevel [Byte0]: 64

 3447 16:44:31.857338                           [Byte1]: 64

 3448 16:44:31.861685  

 3449 16:44:31.864972  Set Vref, RX VrefLevel [Byte0]: 65

 3450 16:44:31.865389                           [Byte1]: 65

 3451 16:44:31.870129  

 3452 16:44:31.870649  Final RX Vref Byte 0 = 53 to rank0

 3453 16:44:31.873247  Final RX Vref Byte 1 = 51 to rank0

 3454 16:44:31.876624  Final RX Vref Byte 0 = 53 to rank1

 3455 16:44:31.879365  Final RX Vref Byte 1 = 51 to rank1==

 3456 16:44:31.882807  Dram Type= 6, Freq= 0, CH_1, rank 0

 3457 16:44:31.889353  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3458 16:44:31.889788  ==

 3459 16:44:31.890117  DQS Delay:

 3460 16:44:31.890422  DQS0 = 0, DQS1 = 0

 3461 16:44:31.892659  DQM Delay:

 3462 16:44:31.893073  DQM0 = 115, DQM1 = 112

 3463 16:44:31.896083  DQ Delay:

 3464 16:44:31.899514  DQ0 =122, DQ1 =112, DQ2 =106, DQ3 =114

 3465 16:44:31.902684  DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110

 3466 16:44:31.906101  DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106

 3467 16:44:31.909461  DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120

 3468 16:44:31.909919  

 3469 16:44:31.910257  

 3470 16:44:31.919805  [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps

 3471 16:44:31.920223  CH1 RK0: MR19=304, MR18=F400

 3472 16:44:31.925757  CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26

 3473 16:44:31.926236  

 3474 16:44:31.929500  ----->DramcWriteLeveling(PI) begin...

 3475 16:44:31.929920  ==

 3476 16:44:31.932401  Dram Type= 6, Freq= 0, CH_1, rank 1

 3477 16:44:31.939399  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3478 16:44:31.939892  ==

 3479 16:44:31.942369  Write leveling (Byte 0): 24 => 24

 3480 16:44:31.942793  Write leveling (Byte 1): 28 => 28

 3481 16:44:31.946048  DramcWriteLeveling(PI) end<-----

 3482 16:44:31.946477  

 3483 16:44:31.946812  ==

 3484 16:44:31.949200  Dram Type= 6, Freq= 0, CH_1, rank 1

 3485 16:44:31.955659  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3486 16:44:31.956093  ==

 3487 16:44:31.959010  [Gating] SW mode calibration

 3488 16:44:31.966032  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3489 16:44:31.969247  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3490 16:44:31.975620   0 15  0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 3491 16:44:31.979208   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3492 16:44:31.982426   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3493 16:44:31.988916   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3494 16:44:31.992542   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3495 16:44:31.995533   0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)

 3496 16:44:32.002481   0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)

 3497 16:44:32.005472   0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)

 3498 16:44:32.009053   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3499 16:44:32.015884   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3500 16:44:32.018894   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3501 16:44:32.022340   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3502 16:44:32.028803   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3503 16:44:32.031955   1  0 20 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)

 3504 16:44:32.035153   1  0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 3505 16:44:32.041882   1  0 28 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)

 3506 16:44:32.045279   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3507 16:44:32.049096   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3508 16:44:32.055081   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3509 16:44:32.058524   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3510 16:44:32.061450   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3511 16:44:32.068178   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3512 16:44:32.071481   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3513 16:44:32.074485   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3514 16:44:32.081295   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3515 16:44:32.084548   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3516 16:44:32.087571   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3517 16:44:32.094322   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3518 16:44:32.097719   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3519 16:44:32.100972   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3520 16:44:32.107890   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3521 16:44:32.110497   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3522 16:44:32.113963   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3523 16:44:32.120793   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3524 16:44:32.123927   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3525 16:44:32.126895   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3526 16:44:32.133877   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3527 16:44:32.137268   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3528 16:44:32.140241   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3529 16:44:32.146800   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 3530 16:44:32.150038  Total UI for P1: 0, mck2ui 16

 3531 16:44:32.153515  best dqsien dly found for B0: ( 1,  3, 24)

 3532 16:44:32.156904   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3533 16:44:32.159862  Total UI for P1: 0, mck2ui 16

 3534 16:44:32.163164  best dqsien dly found for B1: ( 1,  3, 26)

 3535 16:44:32.167367  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 3536 16:44:32.170171  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3537 16:44:32.170590  

 3538 16:44:32.173819  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3539 16:44:32.176575  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3540 16:44:32.179910  [Gating] SW calibration Done

 3541 16:44:32.180330  ==

 3542 16:44:32.183095  Dram Type= 6, Freq= 0, CH_1, rank 1

 3543 16:44:32.189836  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3544 16:44:32.190262  ==

 3545 16:44:32.190592  RX Vref Scan: 0

 3546 16:44:32.190906  

 3547 16:44:32.193007  RX Vref 0 -> 0, step: 1

 3548 16:44:32.193609  

 3549 16:44:32.196445  RX Delay -40 -> 252, step: 8

 3550 16:44:32.199569  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 3551 16:44:32.202826  iDelay=200, Bit 1, Center 115 (40 ~ 191) 152

 3552 16:44:32.206087  iDelay=200, Bit 2, Center 103 (32 ~ 175) 144

 3553 16:44:32.212681  iDelay=200, Bit 3, Center 111 (40 ~ 183) 144

 3554 16:44:32.216493  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 3555 16:44:32.219676  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3556 16:44:32.222743  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 3557 16:44:32.225938  iDelay=200, Bit 7, Center 115 (40 ~ 191) 152

 3558 16:44:32.229253  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3559 16:44:32.235614  iDelay=200, Bit 9, Center 103 (32 ~ 175) 144

 3560 16:44:32.239223  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3561 16:44:32.242721  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3562 16:44:32.245321  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3563 16:44:32.252257  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3564 16:44:32.255398  iDelay=200, Bit 14, Center 115 (48 ~ 183) 136

 3565 16:44:32.259106  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 3566 16:44:32.259562  ==

 3567 16:44:32.262215  Dram Type= 6, Freq= 0, CH_1, rank 1

 3568 16:44:32.265255  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3569 16:44:32.268901  ==

 3570 16:44:32.269392  DQS Delay:

 3571 16:44:32.269729  DQS0 = 0, DQS1 = 0

 3572 16:44:32.271799  DQM Delay:

 3573 16:44:32.272220  DQM0 = 116, DQM1 = 111

 3574 16:44:32.275159  DQ Delay:

 3575 16:44:32.278537  DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =111

 3576 16:44:32.281899  DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115

 3577 16:44:32.285158  DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107

 3578 16:44:32.288769  DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119

 3579 16:44:32.289189  

 3580 16:44:32.289536  

 3581 16:44:32.289910  ==

 3582 16:44:32.291684  Dram Type= 6, Freq= 0, CH_1, rank 1

 3583 16:44:32.295231  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3584 16:44:32.295690  ==

 3585 16:44:32.296027  

 3586 16:44:32.298658  

 3587 16:44:32.299203  	TX Vref Scan disable

 3588 16:44:32.302088   == TX Byte 0 ==

 3589 16:44:32.305091  Update DQ  dly =841 (3 ,1, 41)  DQ  OEN =(2 ,6)

 3590 16:44:32.308672  Update DQM dly =841 (3 ,1, 41)  DQM OEN =(2 ,6)

 3591 16:44:32.311590   == TX Byte 1 ==

 3592 16:44:32.314943  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3593 16:44:32.318155  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3594 16:44:32.318597  ==

 3595 16:44:32.321485  Dram Type= 6, Freq= 0, CH_1, rank 1

 3596 16:44:32.327856  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3597 16:44:32.328321  ==

 3598 16:44:32.338799  TX Vref=22, minBit 3, minWin=25, winSum=416

 3599 16:44:32.342143  TX Vref=24, minBit 9, minWin=25, winSum=421

 3600 16:44:32.345944  TX Vref=26, minBit 1, minWin=26, winSum=426

 3601 16:44:32.348606  TX Vref=28, minBit 0, minWin=26, winSum=430

 3602 16:44:32.352156  TX Vref=30, minBit 1, minWin=26, winSum=434

 3603 16:44:32.358829  TX Vref=32, minBit 2, minWin=26, winSum=433

 3604 16:44:32.362343  [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30

 3605 16:44:32.362790  

 3606 16:44:32.365113  Final TX Range 1 Vref 30

 3607 16:44:32.365544  

 3608 16:44:32.365883  ==

 3609 16:44:32.369146  Dram Type= 6, Freq= 0, CH_1, rank 1

 3610 16:44:32.372230  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3611 16:44:32.374967  ==

 3612 16:44:32.375435  

 3613 16:44:32.375791  

 3614 16:44:32.376112  	TX Vref Scan disable

 3615 16:44:32.378473   == TX Byte 0 ==

 3616 16:44:32.382131  Update DQ  dly =841 (3 ,1, 41)  DQ  OEN =(2 ,6)

 3617 16:44:32.388656  Update DQM dly =841 (3 ,1, 41)  DQM OEN =(2 ,6)

 3618 16:44:32.389245   == TX Byte 1 ==

 3619 16:44:32.391840  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3620 16:44:32.398862  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3621 16:44:32.399492  

 3622 16:44:32.399887  [DATLAT]

 3623 16:44:32.400234  Freq=1200, CH1 RK1

 3624 16:44:32.400583  

 3625 16:44:32.401975  DATLAT Default: 0xd

 3626 16:44:32.404799  0, 0xFFFF, sum = 0

 3627 16:44:32.405238  1, 0xFFFF, sum = 0

 3628 16:44:32.407999  2, 0xFFFF, sum = 0

 3629 16:44:32.408461  3, 0xFFFF, sum = 0

 3630 16:44:32.411585  4, 0xFFFF, sum = 0

 3631 16:44:32.412040  5, 0xFFFF, sum = 0

 3632 16:44:32.414665  6, 0xFFFF, sum = 0

 3633 16:44:32.415098  7, 0xFFFF, sum = 0

 3634 16:44:32.418290  8, 0xFFFF, sum = 0

 3635 16:44:32.418726  9, 0xFFFF, sum = 0

 3636 16:44:32.421492  10, 0xFFFF, sum = 0

 3637 16:44:32.421926  11, 0xFFFF, sum = 0

 3638 16:44:32.424727  12, 0x0, sum = 1

 3639 16:44:32.425286  13, 0x0, sum = 2

 3640 16:44:32.427983  14, 0x0, sum = 3

 3641 16:44:32.428415  15, 0x0, sum = 4

 3642 16:44:32.431630  best_step = 13

 3643 16:44:32.432211  

 3644 16:44:32.432561  ==

 3645 16:44:32.434755  Dram Type= 6, Freq= 0, CH_1, rank 1

 3646 16:44:32.437908  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3647 16:44:32.438361  ==

 3648 16:44:32.441507  RX Vref Scan: 0

 3649 16:44:32.442021  

 3650 16:44:32.442366  RX Vref 0 -> 0, step: 1

 3651 16:44:32.442688  

 3652 16:44:32.444341  RX Delay -13 -> 252, step: 4

 3653 16:44:32.451128  iDelay=195, Bit 0, Center 116 (47 ~ 186) 140

 3654 16:44:32.454389  iDelay=195, Bit 1, Center 112 (43 ~ 182) 140

 3655 16:44:32.457389  iDelay=195, Bit 2, Center 106 (39 ~ 174) 136

 3656 16:44:32.460941  iDelay=195, Bit 3, Center 114 (47 ~ 182) 136

 3657 16:44:32.464183  iDelay=195, Bit 4, Center 114 (47 ~ 182) 136

 3658 16:44:32.470720  iDelay=195, Bit 5, Center 124 (55 ~ 194) 140

 3659 16:44:32.474124  iDelay=195, Bit 6, Center 120 (51 ~ 190) 140

 3660 16:44:32.477232  iDelay=195, Bit 7, Center 112 (43 ~ 182) 140

 3661 16:44:32.481274  iDelay=195, Bit 8, Center 100 (39 ~ 162) 124

 3662 16:44:32.484096  iDelay=195, Bit 9, Center 102 (39 ~ 166) 128

 3663 16:44:32.490356  iDelay=195, Bit 10, Center 114 (51 ~ 178) 128

 3664 16:44:32.494258  iDelay=195, Bit 11, Center 106 (43 ~ 170) 128

 3665 16:44:32.497919  iDelay=195, Bit 12, Center 118 (55 ~ 182) 128

 3666 16:44:32.500675  iDelay=195, Bit 13, Center 118 (55 ~ 182) 128

 3667 16:44:32.507426  iDelay=195, Bit 14, Center 116 (55 ~ 178) 124

 3668 16:44:32.510310  iDelay=195, Bit 15, Center 120 (55 ~ 186) 132

 3669 16:44:32.510840  ==

 3670 16:44:32.514392  Dram Type= 6, Freq= 0, CH_1, rank 1

 3671 16:44:32.517180  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3672 16:44:32.517710  ==

 3673 16:44:32.520239  DQS Delay:

 3674 16:44:32.520696  DQS0 = 0, DQS1 = 0

 3675 16:44:32.521042  DQM Delay:

 3676 16:44:32.523770  DQM0 = 114, DQM1 = 111

 3677 16:44:32.524198  DQ Delay:

 3678 16:44:32.527039  DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114

 3679 16:44:32.529892  DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =112

 3680 16:44:32.536723  DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106

 3681 16:44:32.539775  DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120

 3682 16:44:32.540212  

 3683 16:44:32.540546  

 3684 16:44:32.546855  [DQSOSCAuto] RK1, (LSB)MR18= 0xf80a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps

 3685 16:44:32.549965  CH1 RK1: MR19=304, MR18=F80A

 3686 16:44:32.556500  CH1_RK1: MR19=0x304, MR18=0xF80A, DQSOSC=406, MR23=63, INC=39, DEC=26

 3687 16:44:32.559657  [RxdqsGatingPostProcess] freq 1200

 3688 16:44:32.566257  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3689 16:44:32.566784  best DQS0 dly(2T, 0.5T) = (0, 11)

 3690 16:44:32.570308  best DQS1 dly(2T, 0.5T) = (0, 11)

 3691 16:44:32.572953  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3692 16:44:32.576331  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3693 16:44:32.579809  best DQS0 dly(2T, 0.5T) = (0, 11)

 3694 16:44:32.582741  best DQS1 dly(2T, 0.5T) = (0, 11)

 3695 16:44:32.585845  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3696 16:44:32.589374  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3697 16:44:32.592564  Pre-setting of DQS Precalculation

 3698 16:44:32.599234  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3699 16:44:32.605655  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3700 16:44:32.612333  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3701 16:44:32.612898  

 3702 16:44:32.613247  

 3703 16:44:32.615404  [Calibration Summary] 2400 Mbps

 3704 16:44:32.615850  CH 0, Rank 0

 3705 16:44:32.619061  SW Impedance     : PASS

 3706 16:44:32.621970  DUTY Scan        : NO K

 3707 16:44:32.622397  ZQ Calibration   : PASS

 3708 16:44:32.625221  Jitter Meter     : NO K

 3709 16:44:32.628843  CBT Training     : PASS

 3710 16:44:32.629274  Write leveling   : PASS

 3711 16:44:32.632103  RX DQS gating    : PASS

 3712 16:44:32.635675  RX DQ/DQS(RDDQC) : PASS

 3713 16:44:32.636105  TX DQ/DQS        : PASS

 3714 16:44:32.638754  RX DATLAT        : PASS

 3715 16:44:32.642298  RX DQ/DQS(Engine): PASS

 3716 16:44:32.642815  TX OE            : NO K

 3717 16:44:32.643163  All Pass.

 3718 16:44:32.645197  

 3719 16:44:32.645650  CH 0, Rank 1

 3720 16:44:32.648614  SW Impedance     : PASS

 3721 16:44:32.649042  DUTY Scan        : NO K

 3722 16:44:32.652059  ZQ Calibration   : PASS

 3723 16:44:32.655591  Jitter Meter     : NO K

 3724 16:44:32.656075  CBT Training     : PASS

 3725 16:44:32.658534  Write leveling   : PASS

 3726 16:44:32.661724  RX DQS gating    : PASS

 3727 16:44:32.662155  RX DQ/DQS(RDDQC) : PASS

 3728 16:44:32.665191  TX DQ/DQS        : PASS

 3729 16:44:32.665761  RX DATLAT        : PASS

 3730 16:44:32.668110  RX DQ/DQS(Engine): PASS

 3731 16:44:32.671600  TX OE            : NO K

 3732 16:44:32.672028  All Pass.

 3733 16:44:32.672366  

 3734 16:44:32.672721  CH 1, Rank 0

 3735 16:44:32.675293  SW Impedance     : PASS

 3736 16:44:32.678357  DUTY Scan        : NO K

 3737 16:44:32.678785  ZQ Calibration   : PASS

 3738 16:44:32.681314  Jitter Meter     : NO K

 3739 16:44:32.684793  CBT Training     : PASS

 3740 16:44:32.685238  Write leveling   : PASS

 3741 16:44:32.688092  RX DQS gating    : PASS

 3742 16:44:32.691606  RX DQ/DQS(RDDQC) : PASS

 3743 16:44:32.692179  TX DQ/DQS        : PASS

 3744 16:44:32.694793  RX DATLAT        : PASS

 3745 16:44:32.698051  RX DQ/DQS(Engine): PASS

 3746 16:44:32.698478  TX OE            : NO K

 3747 16:44:32.701151  All Pass.

 3748 16:44:32.701711  

 3749 16:44:32.702053  CH 1, Rank 1

 3750 16:44:32.704855  SW Impedance     : PASS

 3751 16:44:32.705288  DUTY Scan        : NO K

 3752 16:44:32.707900  ZQ Calibration   : PASS

 3753 16:44:32.711636  Jitter Meter     : NO K

 3754 16:44:32.712067  CBT Training     : PASS

 3755 16:44:32.714535  Write leveling   : PASS

 3756 16:44:32.717978  RX DQS gating    : PASS

 3757 16:44:32.718501  RX DQ/DQS(RDDQC) : PASS

 3758 16:44:32.721439  TX DQ/DQS        : PASS

 3759 16:44:32.724376  RX DATLAT        : PASS

 3760 16:44:32.724807  RX DQ/DQS(Engine): PASS

 3761 16:44:32.727912  TX OE            : NO K

 3762 16:44:32.728356  All Pass.

 3763 16:44:32.728728  

 3764 16:44:32.730583  DramC Write-DBI off

 3765 16:44:32.734261  	PER_BANK_REFRESH: Hybrid Mode

 3766 16:44:32.734798  TX_TRACKING: ON

 3767 16:44:32.744044  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3768 16:44:32.747145  [FAST_K] Save calibration result to emmc

 3769 16:44:32.750852  dramc_set_vcore_voltage set vcore to 650000

 3770 16:44:32.753880  Read voltage for 600, 5

 3771 16:44:32.754415  Vio18 = 0

 3772 16:44:32.754765  Vcore = 650000

 3773 16:44:32.757484  Vdram = 0

 3774 16:44:32.758039  Vddq = 0

 3775 16:44:32.758518  Vmddr = 0

 3776 16:44:32.763873  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3777 16:44:32.767923  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3778 16:44:32.770991  MEM_TYPE=3, freq_sel=19

 3779 16:44:32.774463  sv_algorithm_assistance_LP4_1600 

 3780 16:44:32.777059  ============ PULL DRAM RESETB DOWN ============

 3781 16:44:32.780905  ========== PULL DRAM RESETB DOWN end =========

 3782 16:44:32.786918  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3783 16:44:32.790581  =================================== 

 3784 16:44:32.793612  LPDDR4 DRAM CONFIGURATION

 3785 16:44:32.797553  =================================== 

 3786 16:44:32.798081  EX_ROW_EN[0]    = 0x0

 3787 16:44:32.800681  EX_ROW_EN[1]    = 0x0

 3788 16:44:32.801221  LP4Y_EN      = 0x0

 3789 16:44:32.803292  WORK_FSP     = 0x0

 3790 16:44:32.803798  WL           = 0x2

 3791 16:44:32.806951  RL           = 0x2

 3792 16:44:32.807426  BL           = 0x2

 3793 16:44:32.810559  RPST         = 0x0

 3794 16:44:32.810987  RD_PRE       = 0x0

 3795 16:44:32.813836  WR_PRE       = 0x1

 3796 16:44:32.814358  WR_PST       = 0x0

 3797 16:44:32.816510  DBI_WR       = 0x0

 3798 16:44:32.820225  DBI_RD       = 0x0

 3799 16:44:32.820735  OTF          = 0x1

 3800 16:44:32.823208  =================================== 

 3801 16:44:32.826240  =================================== 

 3802 16:44:32.826665  ANA top config

 3803 16:44:32.829457  =================================== 

 3804 16:44:32.833569  DLL_ASYNC_EN            =  0

 3805 16:44:32.836546  ALL_SLAVE_EN            =  1

 3806 16:44:32.839577  NEW_RANK_MODE           =  1

 3807 16:44:32.842974  DLL_IDLE_MODE           =  1

 3808 16:44:32.843415  LP45_APHY_COMB_EN       =  1

 3809 16:44:32.846202  TX_ODT_DIS              =  1

 3810 16:44:32.849726  NEW_8X_MODE             =  1

 3811 16:44:32.852942  =================================== 

 3812 16:44:32.856183  =================================== 

 3813 16:44:32.859514  data_rate                  = 1200

 3814 16:44:32.863149  CKR                        = 1

 3815 16:44:32.863609  DQ_P2S_RATIO               = 8

 3816 16:44:32.866191  =================================== 

 3817 16:44:32.869313  CA_P2S_RATIO               = 8

 3818 16:44:32.872840  DQ_CA_OPEN                 = 0

 3819 16:44:32.876975  DQ_SEMI_OPEN               = 0

 3820 16:44:32.879290  CA_SEMI_OPEN               = 0

 3821 16:44:32.882401  CA_FULL_RATE               = 0

 3822 16:44:32.882836  DQ_CKDIV4_EN               = 1

 3823 16:44:32.885769  CA_CKDIV4_EN               = 1

 3824 16:44:32.889320  CA_PREDIV_EN               = 0

 3825 16:44:32.892438  PH8_DLY                    = 0

 3826 16:44:32.896109  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3827 16:44:32.899342  DQ_AAMCK_DIV               = 4

 3828 16:44:32.899862  CA_AAMCK_DIV               = 4

 3829 16:44:32.902435  CA_ADMCK_DIV               = 4

 3830 16:44:32.905740  DQ_TRACK_CA_EN             = 0

 3831 16:44:32.909049  CA_PICK                    = 600

 3832 16:44:32.912745  CA_MCKIO                   = 600

 3833 16:44:32.915791  MCKIO_SEMI                 = 0

 3834 16:44:32.919080  PLL_FREQ                   = 2288

 3835 16:44:32.922160  DQ_UI_PI_RATIO             = 32

 3836 16:44:32.922586  CA_UI_PI_RATIO             = 0

 3837 16:44:32.925544  =================================== 

 3838 16:44:32.929050  =================================== 

 3839 16:44:32.932705  memory_type:LPDDR4         

 3840 16:44:32.935493  GP_NUM     : 10       

 3841 16:44:32.935955  SRAM_EN    : 1       

 3842 16:44:32.938852  MD32_EN    : 0       

 3843 16:44:32.942183  =================================== 

 3844 16:44:32.945854  [ANA_INIT] >>>>>>>>>>>>>> 

 3845 16:44:32.948618  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3846 16:44:32.951864  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3847 16:44:32.955360  =================================== 

 3848 16:44:32.955810  data_rate = 1200,PCW = 0X5800

 3849 16:44:32.958427  =================================== 

 3850 16:44:32.961522  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3851 16:44:32.968285  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3852 16:44:32.975222  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3853 16:44:32.978066  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3854 16:44:32.981605  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3855 16:44:32.984891  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3856 16:44:32.988069  [ANA_INIT] flow start 

 3857 16:44:32.991498  [ANA_INIT] PLL >>>>>>>> 

 3858 16:44:32.991925  [ANA_INIT] PLL <<<<<<<< 

 3859 16:44:32.994773  [ANA_INIT] MIDPI >>>>>>>> 

 3860 16:44:32.998417  [ANA_INIT] MIDPI <<<<<<<< 

 3861 16:44:32.998867  [ANA_INIT] DLL >>>>>>>> 

 3862 16:44:33.001520  [ANA_INIT] flow end 

 3863 16:44:33.004514  ============ LP4 DIFF to SE enter ============

 3864 16:44:33.007841  ============ LP4 DIFF to SE exit  ============

 3865 16:44:33.011291  [ANA_INIT] <<<<<<<<<<<<< 

 3866 16:44:33.014913  [Flow] Enable top DCM control >>>>> 

 3867 16:44:33.017806  [Flow] Enable top DCM control <<<<< 

 3868 16:44:33.021435  Enable DLL master slave shuffle 

 3869 16:44:33.028424  ============================================================== 

 3870 16:44:33.028981  Gating Mode config

 3871 16:44:33.035042  ============================================================== 

 3872 16:44:33.037944  Config description: 

 3873 16:44:33.044239  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3874 16:44:33.051009  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3875 16:44:33.057794  SELPH_MODE            0: By rank         1: By Phase 

 3876 16:44:33.064993  ============================================================== 

 3877 16:44:33.065519  GAT_TRACK_EN                 =  1

 3878 16:44:33.067970  RX_GATING_MODE               =  2

 3879 16:44:33.070715  RX_GATING_TRACK_MODE         =  2

 3880 16:44:33.074363  SELPH_MODE                   =  1

 3881 16:44:33.077251  PICG_EARLY_EN                =  1

 3882 16:44:33.080556  VALID_LAT_VALUE              =  1

 3883 16:44:33.087234  ============================================================== 

 3884 16:44:33.090282  Enter into Gating configuration >>>> 

 3885 16:44:33.093549  Exit from Gating configuration <<<< 

 3886 16:44:33.096878  Enter into  DVFS_PRE_config >>>>> 

 3887 16:44:33.107065  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3888 16:44:33.109999  Exit from  DVFS_PRE_config <<<<< 

 3889 16:44:33.113741  Enter into PICG configuration >>>> 

 3890 16:44:33.116940  Exit from PICG configuration <<<< 

 3891 16:44:33.120023  [RX_INPUT] configuration >>>>> 

 3892 16:44:33.123771  [RX_INPUT] configuration <<<<< 

 3893 16:44:33.126385  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3894 16:44:33.133397  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3895 16:44:33.140403  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3896 16:44:33.146376  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3897 16:44:33.149986  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3898 16:44:33.156317  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3899 16:44:33.159758  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3900 16:44:33.166331  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3901 16:44:33.169661  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3902 16:44:33.172878  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3903 16:44:33.176545  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3904 16:44:33.182647  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3905 16:44:33.186689  =================================== 

 3906 16:44:33.189215  LPDDR4 DRAM CONFIGURATION

 3907 16:44:33.192829  =================================== 

 3908 16:44:33.193260  EX_ROW_EN[0]    = 0x0

 3909 16:44:33.195806  EX_ROW_EN[1]    = 0x0

 3910 16:44:33.196235  LP4Y_EN      = 0x0

 3911 16:44:33.198818  WORK_FSP     = 0x0

 3912 16:44:33.199282  WL           = 0x2

 3913 16:44:33.202248  RL           = 0x2

 3914 16:44:33.202726  BL           = 0x2

 3915 16:44:33.206079  RPST         = 0x0

 3916 16:44:33.206447  RD_PRE       = 0x0

 3917 16:44:33.209298  WR_PRE       = 0x1

 3918 16:44:33.209756  WR_PST       = 0x0

 3919 16:44:33.212151  DBI_WR       = 0x0

 3920 16:44:33.215603  DBI_RD       = 0x0

 3921 16:44:33.216046  OTF          = 0x1

 3922 16:44:33.218965  =================================== 

 3923 16:44:33.222305  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3924 16:44:33.226045  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3925 16:44:33.232559  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3926 16:44:33.235565  =================================== 

 3927 16:44:33.238518  LPDDR4 DRAM CONFIGURATION

 3928 16:44:33.242021  =================================== 

 3929 16:44:33.242609  EX_ROW_EN[0]    = 0x10

 3930 16:44:33.245791  EX_ROW_EN[1]    = 0x0

 3931 16:44:33.246305  LP4Y_EN      = 0x0

 3932 16:44:33.249274  WORK_FSP     = 0x0

 3933 16:44:33.249810  WL           = 0x2

 3934 16:44:33.251858  RL           = 0x2

 3935 16:44:33.252287  BL           = 0x2

 3936 16:44:33.255465  RPST         = 0x0

 3937 16:44:33.258427  RD_PRE       = 0x0

 3938 16:44:33.259021  WR_PRE       = 0x1

 3939 16:44:33.262047  WR_PST       = 0x0

 3940 16:44:33.262469  DBI_WR       = 0x0

 3941 16:44:33.265011  DBI_RD       = 0x0

 3942 16:44:33.265526  OTF          = 0x1

 3943 16:44:33.268618  =================================== 

 3944 16:44:33.274693  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3945 16:44:33.278924  nWR fixed to 30

 3946 16:44:33.281976  [ModeRegInit_LP4] CH0 RK0

 3947 16:44:33.282493  [ModeRegInit_LP4] CH0 RK1

 3948 16:44:33.285611  [ModeRegInit_LP4] CH1 RK0

 3949 16:44:33.288786  [ModeRegInit_LP4] CH1 RK1

 3950 16:44:33.289209  match AC timing 17

 3951 16:44:33.295916  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3952 16:44:33.298415  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3953 16:44:33.301987  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3954 16:44:33.308472  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3955 16:44:33.311231  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3956 16:44:33.311635  ==

 3957 16:44:33.314540  Dram Type= 6, Freq= 0, CH_0, rank 0

 3958 16:44:33.317988  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3959 16:44:33.321336  ==

 3960 16:44:33.324711  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3961 16:44:33.331277  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3962 16:44:33.334538  [CA 0] Center 36 (6~67) winsize 62

 3963 16:44:33.337714  [CA 1] Center 36 (6~67) winsize 62

 3964 16:44:33.340918  [CA 2] Center 34 (4~65) winsize 62

 3965 16:44:33.344887  [CA 3] Center 34 (4~65) winsize 62

 3966 16:44:33.347997  [CA 4] Center 34 (3~65) winsize 63

 3967 16:44:33.350877  [CA 5] Center 34 (4~64) winsize 61

 3968 16:44:33.351318  

 3969 16:44:33.353889  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3970 16:44:33.354387  

 3971 16:44:33.357390  [CATrainingPosCal] consider 1 rank data

 3972 16:44:33.360660  u2DelayCellTimex100 = 270/100 ps

 3973 16:44:33.363906  CA0 delay=36 (6~67),Diff = 2 PI (19 cell)

 3974 16:44:33.367022  CA1 delay=36 (6~67),Diff = 2 PI (19 cell)

 3975 16:44:33.373693  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 3976 16:44:33.377233  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 3977 16:44:33.380408  CA4 delay=34 (3~65),Diff = 0 PI (0 cell)

 3978 16:44:33.384194  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3979 16:44:33.384625  

 3980 16:44:33.386783  CA PerBit enable=1, Macro0, CA PI delay=34

 3981 16:44:33.387252  

 3982 16:44:33.390252  [CBTSetCACLKResult] CA Dly = 34

 3983 16:44:33.390680  CS Dly: 5 (0~36)

 3984 16:44:33.393905  ==

 3985 16:44:33.397053  Dram Type= 6, Freq= 0, CH_0, rank 1

 3986 16:44:33.400172  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3987 16:44:33.400623  ==

 3988 16:44:33.406938  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3989 16:44:33.410311  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 3990 16:44:33.413950  [CA 0] Center 36 (6~67) winsize 62

 3991 16:44:33.417363  [CA 1] Center 36 (6~67) winsize 62

 3992 16:44:33.421082  [CA 2] Center 34 (4~65) winsize 62

 3993 16:44:33.423976  [CA 3] Center 34 (4~65) winsize 62

 3994 16:44:33.427400  [CA 4] Center 34 (3~65) winsize 63

 3995 16:44:33.430918  [CA 5] Center 34 (3~65) winsize 63

 3996 16:44:33.431467  

 3997 16:44:33.433843  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3998 16:44:33.434282  

 3999 16:44:33.437248  [CATrainingPosCal] consider 2 rank data

 4000 16:44:33.440530  u2DelayCellTimex100 = 270/100 ps

 4001 16:44:33.444143  CA0 delay=36 (6~67),Diff = 2 PI (19 cell)

 4002 16:44:33.447246  CA1 delay=36 (6~67),Diff = 2 PI (19 cell)

 4003 16:44:33.453996  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4004 16:44:33.457116  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4005 16:44:33.460822  CA4 delay=34 (3~65),Diff = 0 PI (0 cell)

 4006 16:44:33.463789  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 4007 16:44:33.464218  

 4008 16:44:33.467582  CA PerBit enable=1, Macro0, CA PI delay=34

 4009 16:44:33.468013  

 4010 16:44:33.470560  [CBTSetCACLKResult] CA Dly = 34

 4011 16:44:33.470990  CS Dly: 5 (0~37)

 4012 16:44:33.473561  

 4013 16:44:33.477200  ----->DramcWriteLeveling(PI) begin...

 4014 16:44:33.477732  ==

 4015 16:44:33.480460  Dram Type= 6, Freq= 0, CH_0, rank 0

 4016 16:44:33.483683  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4017 16:44:33.484130  ==

 4018 16:44:33.486951  Write leveling (Byte 0): 33 => 33

 4019 16:44:33.490286  Write leveling (Byte 1): 27 => 27

 4020 16:44:33.493604  DramcWriteLeveling(PI) end<-----

 4021 16:44:33.494070  

 4022 16:44:33.494539  ==

 4023 16:44:33.496973  Dram Type= 6, Freq= 0, CH_0, rank 0

 4024 16:44:33.499626  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4025 16:44:33.500197  ==

 4026 16:44:33.503406  [Gating] SW mode calibration

 4027 16:44:33.510076  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4028 16:44:33.516737  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4029 16:44:33.520381   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4030 16:44:33.523141   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4031 16:44:33.529496   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4032 16:44:33.532829   0  9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)

 4033 16:44:33.535898   0  9 16 | B1->B0 | 2c2c 2626 | 0 0 | (1 1) (0 0)

 4034 16:44:33.543276   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4035 16:44:33.546071   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4036 16:44:33.548871   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4037 16:44:33.555544   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4038 16:44:33.559050   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4039 16:44:33.562344   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4040 16:44:33.568795   0 10 12 | B1->B0 | 2525 3131 | 0 1 | (0 0) (0 0)

 4041 16:44:33.572174   0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)

 4042 16:44:33.575363   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4043 16:44:33.581852   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4044 16:44:33.585521   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4045 16:44:33.591882   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4046 16:44:33.595482   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4047 16:44:33.598133   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4048 16:44:33.604911   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4049 16:44:33.608022   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4050 16:44:33.611270   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4051 16:44:33.617934   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4052 16:44:33.621532   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4053 16:44:33.625287   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4054 16:44:33.631246   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4055 16:44:33.634964   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4056 16:44:33.638203   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4057 16:44:33.644393   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4058 16:44:33.647689   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4059 16:44:33.650932   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4060 16:44:33.657703   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4061 16:44:33.661362   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4062 16:44:33.664159   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4063 16:44:33.670903   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4064 16:44:33.673821   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4065 16:44:33.677117   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4066 16:44:33.680353  Total UI for P1: 0, mck2ui 16

 4067 16:44:33.684420  best dqsien dly found for B0: ( 0, 13, 12)

 4068 16:44:33.690516   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4069 16:44:33.690948  Total UI for P1: 0, mck2ui 16

 4070 16:44:33.697040  best dqsien dly found for B1: ( 0, 13, 16)

 4071 16:44:33.700999  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4072 16:44:33.703804  best DQS1 dly(MCK, UI, PI) = (0, 13, 16)

 4073 16:44:33.704247  

 4074 16:44:33.707199  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4075 16:44:33.710298  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4076 16:44:33.713483  [Gating] SW calibration Done

 4077 16:44:33.713911  ==

 4078 16:44:33.716828  Dram Type= 6, Freq= 0, CH_0, rank 0

 4079 16:44:33.719888  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4080 16:44:33.720322  ==

 4081 16:44:33.723403  RX Vref Scan: 0

 4082 16:44:33.723830  

 4083 16:44:33.724169  RX Vref 0 -> 0, step: 1

 4084 16:44:33.726259  

 4085 16:44:33.726689  RX Delay -230 -> 252, step: 16

 4086 16:44:33.733285  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4087 16:44:33.736475  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4088 16:44:33.739439  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4089 16:44:33.743595  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4090 16:44:33.749798  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4091 16:44:33.752868  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4092 16:44:33.756070  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4093 16:44:33.759665  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4094 16:44:33.766341  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4095 16:44:33.769383  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4096 16:44:33.772476  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4097 16:44:33.775672  iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336

 4098 16:44:33.782128  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4099 16:44:33.785467  iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320

 4100 16:44:33.788953  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4101 16:44:33.792296  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4102 16:44:33.792746  ==

 4103 16:44:33.795106  Dram Type= 6, Freq= 0, CH_0, rank 0

 4104 16:44:33.802020  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4105 16:44:33.802580  ==

 4106 16:44:33.802993  DQS Delay:

 4107 16:44:33.805656  DQS0 = 0, DQS1 = 0

 4108 16:44:33.806175  DQM Delay:

 4109 16:44:33.806517  DQM0 = 43, DQM1 = 34

 4110 16:44:33.808846  DQ Delay:

 4111 16:44:33.812078  DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41

 4112 16:44:33.815255  DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49

 4113 16:44:33.818324  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33

 4114 16:44:33.821968  DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41

 4115 16:44:33.822460  

 4116 16:44:33.822876  

 4117 16:44:33.823449  ==

 4118 16:44:33.825187  Dram Type= 6, Freq= 0, CH_0, rank 0

 4119 16:44:33.828400  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4120 16:44:33.828840  ==

 4121 16:44:33.829196  

 4122 16:44:33.829622  

 4123 16:44:33.831787  	TX Vref Scan disable

 4124 16:44:33.834770   == TX Byte 0 ==

 4125 16:44:33.838297  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4126 16:44:33.841636  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4127 16:44:33.845109   == TX Byte 1 ==

 4128 16:44:33.848577  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4129 16:44:33.851875  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4130 16:44:33.852305  ==

 4131 16:44:33.855324  Dram Type= 6, Freq= 0, CH_0, rank 0

 4132 16:44:33.861146  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4133 16:44:33.861571  ==

 4134 16:44:33.861982  

 4135 16:44:33.862296  

 4136 16:44:33.862593  	TX Vref Scan disable

 4137 16:44:33.865495   == TX Byte 0 ==

 4138 16:44:33.869012  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4139 16:44:33.875446  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4140 16:44:33.875957   == TX Byte 1 ==

 4141 16:44:33.878976  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4142 16:44:33.885324  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4143 16:44:33.885748  

 4144 16:44:33.886084  [DATLAT]

 4145 16:44:33.886621  Freq=600, CH0 RK0

 4146 16:44:33.886955  

 4147 16:44:33.888808  DATLAT Default: 0x9

 4148 16:44:33.892692  0, 0xFFFF, sum = 0

 4149 16:44:33.893225  1, 0xFFFF, sum = 0

 4150 16:44:33.895289  2, 0xFFFF, sum = 0

 4151 16:44:33.895723  3, 0xFFFF, sum = 0

 4152 16:44:33.898728  4, 0xFFFF, sum = 0

 4153 16:44:33.899321  5, 0xFFFF, sum = 0

 4154 16:44:33.901868  6, 0xFFFF, sum = 0

 4155 16:44:33.902292  7, 0xFFFF, sum = 0

 4156 16:44:33.904943  8, 0x0, sum = 1

 4157 16:44:33.905370  9, 0x0, sum = 2

 4158 16:44:33.908360  10, 0x0, sum = 3

 4159 16:44:33.908787  11, 0x0, sum = 4

 4160 16:44:33.909122  best_step = 9

 4161 16:44:33.909432  

 4162 16:44:33.911406  ==

 4163 16:44:33.914755  Dram Type= 6, Freq= 0, CH_0, rank 0

 4164 16:44:33.918401  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4165 16:44:33.918877  ==

 4166 16:44:33.919488  RX Vref Scan: 1

 4167 16:44:33.919813  

 4168 16:44:33.921504  RX Vref 0 -> 0, step: 1

 4169 16:44:33.921920  

 4170 16:44:33.924645  RX Delay -195 -> 252, step: 8

 4171 16:44:33.925162  

 4172 16:44:33.929327  Set Vref, RX VrefLevel [Byte0]: 56

 4173 16:44:33.931044                           [Byte1]: 59

 4174 16:44:33.931495  

 4175 16:44:33.934487  Final RX Vref Byte 0 = 56 to rank0

 4176 16:44:33.937768  Final RX Vref Byte 1 = 59 to rank0

 4177 16:44:33.941013  Final RX Vref Byte 0 = 56 to rank1

 4178 16:44:33.944671  Final RX Vref Byte 1 = 59 to rank1==

 4179 16:44:33.948159  Dram Type= 6, Freq= 0, CH_0, rank 0

 4180 16:44:33.951291  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4181 16:44:33.954857  ==

 4182 16:44:33.954990  DQS Delay:

 4183 16:44:33.955103  DQS0 = 0, DQS1 = 0

 4184 16:44:33.958213  DQM Delay:

 4185 16:44:33.958327  DQM0 = 40, DQM1 = 31

 4186 16:44:33.960809  DQ Delay:

 4187 16:44:33.964091  DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36

 4188 16:44:33.964195  DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44

 4189 16:44:33.967634  DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =28

 4190 16:44:33.973847  DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40

 4191 16:44:33.974088  

 4192 16:44:33.974280  

 4193 16:44:33.980300  [DQSOSCAuto] RK0, (LSB)MR18= 0x453c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps

 4194 16:44:33.984026  CH0 RK0: MR19=808, MR18=453C

 4195 16:44:33.991459  CH0_RK0: MR19=0x808, MR18=0x453C, DQSOSC=396, MR23=63, INC=167, DEC=111

 4196 16:44:33.991882  

 4197 16:44:33.994357  ----->DramcWriteLeveling(PI) begin...

 4198 16:44:33.994786  ==

 4199 16:44:33.997392  Dram Type= 6, Freq= 0, CH_0, rank 1

 4200 16:44:34.000845  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4201 16:44:34.001269  ==

 4202 16:44:34.003906  Write leveling (Byte 0): 34 => 34

 4203 16:44:34.006991  Write leveling (Byte 1): 31 => 31

 4204 16:44:34.010497  DramcWriteLeveling(PI) end<-----

 4205 16:44:34.011134  

 4206 16:44:34.011537  ==

 4207 16:44:34.013982  Dram Type= 6, Freq= 0, CH_0, rank 1

 4208 16:44:34.017202  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4209 16:44:34.017626  ==

 4210 16:44:34.020615  [Gating] SW mode calibration

 4211 16:44:34.027010  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4212 16:44:34.033634  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4213 16:44:34.037059   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4214 16:44:34.043586   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4215 16:44:34.047055   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4216 16:44:34.050240   0  9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)

 4217 16:44:34.056795   0  9 16 | B1->B0 | 2d2d 2626 | 0 0 | (1 1) (0 0)

 4218 16:44:34.060217   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4219 16:44:34.063287   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4220 16:44:34.070459   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4221 16:44:34.073535   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4222 16:44:34.076354   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4223 16:44:34.083234   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4224 16:44:34.086553   0 10 12 | B1->B0 | 2828 3636 | 0 1 | (0 0) (0 0)

 4225 16:44:34.089361   0 10 16 | B1->B0 | 3f3f 4545 | 1 0 | (0 0) (0 0)

 4226 16:44:34.096209   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4227 16:44:34.099350   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4228 16:44:34.102839   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4229 16:44:34.109255   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4230 16:44:34.112547   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4231 16:44:34.116047   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4232 16:44:34.122183   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4233 16:44:34.126355   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4234 16:44:34.129022   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4235 16:44:34.135626   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4236 16:44:34.139183   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4237 16:44:34.142358   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4238 16:44:34.149119   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4239 16:44:34.152021   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4240 16:44:34.155548   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4241 16:44:34.162038   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4242 16:44:34.165628   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4243 16:44:34.168467   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4244 16:44:34.175713   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4245 16:44:34.178957   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4246 16:44:34.181644   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4247 16:44:34.188499   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4248 16:44:34.191603   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4249 16:44:34.195205   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4250 16:44:34.198210  Total UI for P1: 0, mck2ui 16

 4251 16:44:34.201379  best dqsien dly found for B0: ( 0, 13, 12)

 4252 16:44:34.204685  Total UI for P1: 0, mck2ui 16

 4253 16:44:34.208393  best dqsien dly found for B1: ( 0, 13, 12)

 4254 16:44:34.211433  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4255 16:44:34.214805  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4256 16:44:34.218157  

 4257 16:44:34.221475  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4258 16:44:34.225170  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4259 16:44:34.228099  [Gating] SW calibration Done

 4260 16:44:34.228550  ==

 4261 16:44:34.231480  Dram Type= 6, Freq= 0, CH_0, rank 1

 4262 16:44:34.234920  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4263 16:44:34.235378  ==

 4264 16:44:34.235719  RX Vref Scan: 0

 4265 16:44:34.236032  

 4266 16:44:34.238316  RX Vref 0 -> 0, step: 1

 4267 16:44:34.238740  

 4268 16:44:34.241494  RX Delay -230 -> 252, step: 16

 4269 16:44:34.244445  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4270 16:44:34.251337  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4271 16:44:34.254493  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4272 16:44:34.258388  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4273 16:44:34.261195  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4274 16:44:34.264571  iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336

 4275 16:44:34.270768  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4276 16:44:34.274089  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4277 16:44:34.277654  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4278 16:44:34.280867  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4279 16:44:34.287068  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4280 16:44:34.290494  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4281 16:44:34.294170  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4282 16:44:34.298148  iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320

 4283 16:44:34.303925  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4284 16:44:34.307604  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4285 16:44:34.308036  ==

 4286 16:44:34.310554  Dram Type= 6, Freq= 0, CH_0, rank 1

 4287 16:44:34.313739  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4288 16:44:34.314211  ==

 4289 16:44:34.316654  DQS Delay:

 4290 16:44:34.317081  DQS0 = 0, DQS1 = 0

 4291 16:44:34.320190  DQM Delay:

 4292 16:44:34.320621  DQM0 = 40, DQM1 = 34

 4293 16:44:34.320998  DQ Delay:

 4294 16:44:34.323424  DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33

 4295 16:44:34.326750  DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49

 4296 16:44:34.330476  DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25

 4297 16:44:34.333646  DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41

 4298 16:44:34.334077  

 4299 16:44:34.334416  

 4300 16:44:34.336989  ==

 4301 16:44:34.337417  Dram Type= 6, Freq= 0, CH_0, rank 1

 4302 16:44:34.343123  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4303 16:44:34.343597  ==

 4304 16:44:34.343938  

 4305 16:44:34.344250  

 4306 16:44:34.346310  	TX Vref Scan disable

 4307 16:44:34.346738   == TX Byte 0 ==

 4308 16:44:34.353174  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4309 16:44:34.356776  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4310 16:44:34.357209   == TX Byte 1 ==

 4311 16:44:34.363647  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4312 16:44:34.366077  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4313 16:44:34.366511  ==

 4314 16:44:34.369444  Dram Type= 6, Freq= 0, CH_0, rank 1

 4315 16:44:34.372924  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4316 16:44:34.373486  ==

 4317 16:44:34.373835  

 4318 16:44:34.374148  

 4319 16:44:34.375931  	TX Vref Scan disable

 4320 16:44:34.379624   == TX Byte 0 ==

 4321 16:44:34.382946  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4322 16:44:34.389568  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4323 16:44:34.389990   == TX Byte 1 ==

 4324 16:44:34.392665  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4325 16:44:34.399168  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4326 16:44:34.399748  

 4327 16:44:34.400092  [DATLAT]

 4328 16:44:34.400403  Freq=600, CH0 RK1

 4329 16:44:34.400705  

 4330 16:44:34.402870  DATLAT Default: 0x9

 4331 16:44:34.403361  0, 0xFFFF, sum = 0

 4332 16:44:34.405932  1, 0xFFFF, sum = 0

 4333 16:44:34.406360  2, 0xFFFF, sum = 0

 4334 16:44:34.409085  3, 0xFFFF, sum = 0

 4335 16:44:34.412156  4, 0xFFFF, sum = 0

 4336 16:44:34.412613  5, 0xFFFF, sum = 0

 4337 16:44:34.415993  6, 0xFFFF, sum = 0

 4338 16:44:34.416425  7, 0xFFFF, sum = 0

 4339 16:44:34.418718  8, 0x0, sum = 1

 4340 16:44:34.419165  9, 0x0, sum = 2

 4341 16:44:34.419557  10, 0x0, sum = 3

 4342 16:44:34.422077  11, 0x0, sum = 4

 4343 16:44:34.422505  best_step = 9

 4344 16:44:34.422840  

 4345 16:44:34.423154  ==

 4346 16:44:34.425468  Dram Type= 6, Freq= 0, CH_0, rank 1

 4347 16:44:34.431974  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4348 16:44:34.432402  ==

 4349 16:44:34.432737  RX Vref Scan: 0

 4350 16:44:34.433067  

 4351 16:44:34.435505  RX Vref 0 -> 0, step: 1

 4352 16:44:34.435933  

 4353 16:44:34.438710  RX Delay -195 -> 252, step: 8

 4354 16:44:34.445082  iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296

 4355 16:44:34.448646  iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304

 4356 16:44:34.451655  iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304

 4357 16:44:34.455739  iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304

 4358 16:44:34.458146  iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304

 4359 16:44:34.464853  iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304

 4360 16:44:34.467950  iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304

 4361 16:44:34.471416  iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304

 4362 16:44:34.474760  iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320

 4363 16:44:34.481392  iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320

 4364 16:44:34.484912  iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304

 4365 16:44:34.487561  iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304

 4366 16:44:34.491578  iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312

 4367 16:44:34.497771  iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312

 4368 16:44:34.500772  iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312

 4369 16:44:34.504147  iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312

 4370 16:44:34.504446  ==

 4371 16:44:34.507575  Dram Type= 6, Freq= 0, CH_0, rank 1

 4372 16:44:34.514035  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4373 16:44:34.514354  ==

 4374 16:44:34.514592  DQS Delay:

 4375 16:44:34.514810  DQS0 = 0, DQS1 = 0

 4376 16:44:34.517327  DQM Delay:

 4377 16:44:34.517721  DQM0 = 40, DQM1 = 34

 4378 16:44:34.520646  DQ Delay:

 4379 16:44:34.524153  DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36

 4380 16:44:34.527082  DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =44

 4381 16:44:34.531268  DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28

 4382 16:44:34.533638  DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40

 4383 16:44:34.534057  

 4384 16:44:34.534384  

 4385 16:44:34.540723  [DQSOSCAuto] RK1, (LSB)MR18= 0x403b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps

 4386 16:44:34.543636  CH0 RK1: MR19=808, MR18=403B

 4387 16:44:34.550264  CH0_RK1: MR19=0x808, MR18=0x403B, DQSOSC=397, MR23=63, INC=166, DEC=110

 4388 16:44:34.553414  [RxdqsGatingPostProcess] freq 600

 4389 16:44:34.557082  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4390 16:44:34.560104  Pre-setting of DQS Precalculation

 4391 16:44:34.566495  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4392 16:44:34.566920  ==

 4393 16:44:34.569751  Dram Type= 6, Freq= 0, CH_1, rank 0

 4394 16:44:34.573743  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4395 16:44:34.574372  ==

 4396 16:44:34.580312  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4397 16:44:34.586459  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4398 16:44:34.589985  [CA 0] Center 35 (5~66) winsize 62

 4399 16:44:34.592959  [CA 1] Center 35 (5~66) winsize 62

 4400 16:44:34.596168  [CA 2] Center 34 (4~65) winsize 62

 4401 16:44:34.599477  [CA 3] Center 34 (4~64) winsize 61

 4402 16:44:34.603016  [CA 4] Center 34 (4~65) winsize 62

 4403 16:44:34.606485  [CA 5] Center 33 (3~64) winsize 62

 4404 16:44:34.606996  

 4405 16:44:34.609865  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4406 16:44:34.610376  

 4407 16:44:34.612687  [CATrainingPosCal] consider 1 rank data

 4408 16:44:34.616088  u2DelayCellTimex100 = 270/100 ps

 4409 16:44:34.619219  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4410 16:44:34.622898  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4411 16:44:34.626171  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4412 16:44:34.629213  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 4413 16:44:34.632613  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4414 16:44:34.639462  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4415 16:44:34.639886  

 4416 16:44:34.642626  CA PerBit enable=1, Macro0, CA PI delay=33

 4417 16:44:34.643148  

 4418 16:44:34.645390  [CBTSetCACLKResult] CA Dly = 33

 4419 16:44:34.645817  CS Dly: 4 (0~35)

 4420 16:44:34.646207  ==

 4421 16:44:34.648728  Dram Type= 6, Freq= 0, CH_1, rank 1

 4422 16:44:34.651926  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4423 16:44:34.655360  ==

 4424 16:44:34.658656  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4425 16:44:34.665366  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 4426 16:44:34.668711  [CA 0] Center 35 (5~66) winsize 62

 4427 16:44:34.671692  [CA 1] Center 36 (6~66) winsize 61

 4428 16:44:34.676042  [CA 2] Center 34 (4~65) winsize 62

 4429 16:44:34.678506  [CA 3] Center 34 (3~65) winsize 63

 4430 16:44:34.681951  [CA 4] Center 34 (3~65) winsize 63

 4431 16:44:34.684822  [CA 5] Center 34 (3~65) winsize 63

 4432 16:44:34.685297  

 4433 16:44:34.688317  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 4434 16:44:34.688814  

 4435 16:44:34.691370  [CATrainingPosCal] consider 2 rank data

 4436 16:44:34.695576  u2DelayCellTimex100 = 270/100 ps

 4437 16:44:34.697942  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4438 16:44:34.704696  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 4439 16:44:34.707932  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4440 16:44:34.711130  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 4441 16:44:34.714694  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4442 16:44:34.717586  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4443 16:44:34.718012  

 4444 16:44:34.721451  CA PerBit enable=1, Macro0, CA PI delay=33

 4445 16:44:34.721877  

 4446 16:44:34.724849  [CBTSetCACLKResult] CA Dly = 33

 4447 16:44:34.725417  CS Dly: 5 (0~37)

 4448 16:44:34.727817  

 4449 16:44:34.730772  ----->DramcWriteLeveling(PI) begin...

 4450 16:44:34.731242  ==

 4451 16:44:34.734435  Dram Type= 6, Freq= 0, CH_1, rank 0

 4452 16:44:34.738328  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4453 16:44:34.738755  ==

 4454 16:44:34.740974  Write leveling (Byte 0): 28 => 28

 4455 16:44:34.744400  Write leveling (Byte 1): 30 => 30

 4456 16:44:34.747862  DramcWriteLeveling(PI) end<-----

 4457 16:44:34.748409  

 4458 16:44:34.748832  ==

 4459 16:44:34.751389  Dram Type= 6, Freq= 0, CH_1, rank 0

 4460 16:44:34.754001  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4461 16:44:34.754438  ==

 4462 16:44:34.757521  [Gating] SW mode calibration

 4463 16:44:34.764158  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4464 16:44:34.770459  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4465 16:44:34.773666   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4466 16:44:34.776857   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4467 16:44:34.783527   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4468 16:44:34.787000   0  9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)

 4469 16:44:34.790392   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4470 16:44:34.796771   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4471 16:44:34.799839   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4472 16:44:34.804473   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4473 16:44:34.809963   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4474 16:44:34.813726   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4475 16:44:34.816730   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4476 16:44:34.823636   0 10 12 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (1 1)

 4477 16:44:34.826917   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4478 16:44:34.830746   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4479 16:44:34.836449   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4480 16:44:34.839593   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4481 16:44:34.843146   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4482 16:44:34.849528   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4483 16:44:34.852873   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4484 16:44:34.856851   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 4485 16:44:34.862544   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4486 16:44:34.865969   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4487 16:44:34.869249   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4488 16:44:34.876033   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4489 16:44:34.879289   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4490 16:44:34.882430   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4491 16:44:34.888963   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4492 16:44:34.892717   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4493 16:44:34.895388   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4494 16:44:34.901968   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4495 16:44:34.905397   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4496 16:44:34.908918   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4497 16:44:34.915278   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4498 16:44:34.918885   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4499 16:44:34.921661   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4500 16:44:34.929421   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 4501 16:44:34.931991   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4502 16:44:34.935101  Total UI for P1: 0, mck2ui 16

 4503 16:44:34.938463  best dqsien dly found for B0: ( 0, 13, 14)

 4504 16:44:34.942118  Total UI for P1: 0, mck2ui 16

 4505 16:44:34.945130  best dqsien dly found for B1: ( 0, 13, 12)

 4506 16:44:34.947875  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4507 16:44:34.951631  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4508 16:44:34.952096  

 4509 16:44:34.954707  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4510 16:44:34.961429  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4511 16:44:34.961963  [Gating] SW calibration Done

 4512 16:44:34.964551  ==

 4513 16:44:34.964969  Dram Type= 6, Freq= 0, CH_1, rank 0

 4514 16:44:34.971330  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4515 16:44:34.971752  ==

 4516 16:44:34.972085  RX Vref Scan: 0

 4517 16:44:34.972395  

 4518 16:44:34.974585  RX Vref 0 -> 0, step: 1

 4519 16:44:34.975002  

 4520 16:44:34.978300  RX Delay -230 -> 252, step: 16

 4521 16:44:34.980934  iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336

 4522 16:44:34.984514  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4523 16:44:34.990743  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4524 16:44:34.994540  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4525 16:44:34.997601  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4526 16:44:35.001077  iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336

 4527 16:44:35.007421  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4528 16:44:35.010496  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4529 16:44:35.013977  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4530 16:44:35.017463  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4531 16:44:35.023671  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4532 16:44:35.027494  iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336

 4533 16:44:35.030152  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4534 16:44:35.034007  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4535 16:44:35.040425  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4536 16:44:35.043374  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4537 16:44:35.043852  ==

 4538 16:44:35.046637  Dram Type= 6, Freq= 0, CH_1, rank 0

 4539 16:44:35.050326  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4540 16:44:35.050865  ==

 4541 16:44:35.053589  DQS Delay:

 4542 16:44:35.054134  DQS0 = 0, DQS1 = 0

 4543 16:44:35.054573  DQM Delay:

 4544 16:44:35.056763  DQM0 = 42, DQM1 = 38

 4545 16:44:35.057194  DQ Delay:

 4546 16:44:35.059789  DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41

 4547 16:44:35.063251  DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41

 4548 16:44:35.066483  DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33

 4549 16:44:35.069909  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41

 4550 16:44:35.070343  

 4551 16:44:35.070778  

 4552 16:44:35.071215  ==

 4553 16:44:35.072793  Dram Type= 6, Freq= 0, CH_1, rank 0

 4554 16:44:35.079610  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4555 16:44:35.080153  ==

 4556 16:44:35.080594  

 4557 16:44:35.081002  

 4558 16:44:35.081398  	TX Vref Scan disable

 4559 16:44:35.083615   == TX Byte 0 ==

 4560 16:44:35.086864  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4561 16:44:35.093332  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4562 16:44:35.093768   == TX Byte 1 ==

 4563 16:44:35.096707  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4564 16:44:35.103215  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4565 16:44:35.103653  ==

 4566 16:44:35.106415  Dram Type= 6, Freq= 0, CH_1, rank 0

 4567 16:44:35.109775  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4568 16:44:35.110209  ==

 4569 16:44:35.110638  

 4570 16:44:35.111037  

 4571 16:44:35.113114  	TX Vref Scan disable

 4572 16:44:35.116363   == TX Byte 0 ==

 4573 16:44:35.119492  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4574 16:44:35.123081  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4575 16:44:35.126235   == TX Byte 1 ==

 4576 16:44:35.129432  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4577 16:44:35.132615  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4578 16:44:35.133038  

 4579 16:44:35.136039  [DATLAT]

 4580 16:44:35.136457  Freq=600, CH1 RK0

 4581 16:44:35.136790  

 4582 16:44:35.139147  DATLAT Default: 0x9

 4583 16:44:35.139622  0, 0xFFFF, sum = 0

 4584 16:44:35.142794  1, 0xFFFF, sum = 0

 4585 16:44:35.143248  2, 0xFFFF, sum = 0

 4586 16:44:35.145821  3, 0xFFFF, sum = 0

 4587 16:44:35.146247  4, 0xFFFF, sum = 0

 4588 16:44:35.149197  5, 0xFFFF, sum = 0

 4589 16:44:35.149620  6, 0xFFFF, sum = 0

 4590 16:44:35.152372  7, 0xFFFF, sum = 0

 4591 16:44:35.152795  8, 0x0, sum = 1

 4592 16:44:35.155825  9, 0x0, sum = 2

 4593 16:44:35.156249  10, 0x0, sum = 3

 4594 16:44:35.159253  11, 0x0, sum = 4

 4595 16:44:35.159678  best_step = 9

 4596 16:44:35.160007  

 4597 16:44:35.160314  ==

 4598 16:44:35.162291  Dram Type= 6, Freq= 0, CH_1, rank 0

 4599 16:44:35.166081  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4600 16:44:35.166506  ==

 4601 16:44:35.169151  RX Vref Scan: 1

 4602 16:44:35.169592  

 4603 16:44:35.172765  RX Vref 0 -> 0, step: 1

 4604 16:44:35.173186  

 4605 16:44:35.173520  RX Delay -179 -> 252, step: 8

 4606 16:44:35.175766  

 4607 16:44:35.176184  Set Vref, RX VrefLevel [Byte0]: 53

 4608 16:44:35.179404                           [Byte1]: 51

 4609 16:44:35.184525  

 4610 16:44:35.185041  Final RX Vref Byte 0 = 53 to rank0

 4611 16:44:35.187281  Final RX Vref Byte 1 = 51 to rank0

 4612 16:44:35.190255  Final RX Vref Byte 0 = 53 to rank1

 4613 16:44:35.193683  Final RX Vref Byte 1 = 51 to rank1==

 4614 16:44:35.197191  Dram Type= 6, Freq= 0, CH_1, rank 0

 4615 16:44:35.203595  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4616 16:44:35.204035  ==

 4617 16:44:35.204370  DQS Delay:

 4618 16:44:35.207405  DQS0 = 0, DQS1 = 0

 4619 16:44:35.207825  DQM Delay:

 4620 16:44:35.208158  DQM0 = 42, DQM1 = 34

 4621 16:44:35.211624  DQ Delay:

 4622 16:44:35.214470  DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40

 4623 16:44:35.216936  DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36

 4624 16:44:35.220587  DQ8 =16, DQ9 =24, DQ10 =32, DQ11 =28

 4625 16:44:35.223681  DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44

 4626 16:44:35.224198  

 4627 16:44:35.224545  

 4628 16:44:35.230678  [DQSOSCAuto] RK0, (LSB)MR18= 0x2741, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps

 4629 16:44:35.233574  CH1 RK0: MR19=808, MR18=2741

 4630 16:44:35.240555  CH1_RK0: MR19=0x808, MR18=0x2741, DQSOSC=397, MR23=63, INC=166, DEC=110

 4631 16:44:35.241025  

 4632 16:44:35.243298  ----->DramcWriteLeveling(PI) begin...

 4633 16:44:35.243786  ==

 4634 16:44:35.246651  Dram Type= 6, Freq= 0, CH_1, rank 1

 4635 16:44:35.249828  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4636 16:44:35.250259  ==

 4637 16:44:35.253474  Write leveling (Byte 0): 27 => 27

 4638 16:44:35.256774  Write leveling (Byte 1): 30 => 30

 4639 16:44:35.260991  DramcWriteLeveling(PI) end<-----

 4640 16:44:35.261630  

 4641 16:44:35.262111  ==

 4642 16:44:35.263086  Dram Type= 6, Freq= 0, CH_1, rank 1

 4643 16:44:35.270195  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4644 16:44:35.270732  ==

 4645 16:44:35.271223  [Gating] SW mode calibration

 4646 16:44:35.279750  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4647 16:44:35.283353  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4648 16:44:35.285916   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4649 16:44:35.292473   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4650 16:44:35.296227   0  9  8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 4651 16:44:35.299790   0  9 12 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 1)

 4652 16:44:35.305986   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4653 16:44:35.309173   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4654 16:44:35.312206   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4655 16:44:35.318929   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4656 16:44:35.321958   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4657 16:44:35.325738   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4658 16:44:35.332309   0 10  8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 4659 16:44:35.335483   0 10 12 | B1->B0 | 3030 3a3a | 0 0 | (1 1) (1 1)

 4660 16:44:35.338596   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4661 16:44:35.344812   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4662 16:44:35.348714   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4663 16:44:35.351696   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4664 16:44:35.358745   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4665 16:44:35.362492   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4666 16:44:35.364822   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4667 16:44:35.372199   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4668 16:44:35.375450   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4669 16:44:35.378611   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4670 16:44:35.384705   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4671 16:44:35.387765   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4672 16:44:35.391706   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4673 16:44:35.398047   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4674 16:44:35.401634   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4675 16:44:35.404789   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4676 16:44:35.411358   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4677 16:44:35.414864   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4678 16:44:35.417869   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4679 16:44:35.424495   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4680 16:44:35.428602   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4681 16:44:35.431197   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4682 16:44:35.437513   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4683 16:44:35.440743   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4684 16:44:35.444583  Total UI for P1: 0, mck2ui 16

 4685 16:44:35.447322  best dqsien dly found for B0: ( 0, 13,  8)

 4686 16:44:35.450682   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4687 16:44:35.454435  Total UI for P1: 0, mck2ui 16

 4688 16:44:35.457743  best dqsien dly found for B1: ( 0, 13, 12)

 4689 16:44:35.460496  best DQS0 dly(MCK, UI, PI) = (0, 13, 8)

 4690 16:44:35.467466  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4691 16:44:35.468000  

 4692 16:44:35.470358  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)

 4693 16:44:35.473512  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4694 16:44:35.477822  [Gating] SW calibration Done

 4695 16:44:35.478390  ==

 4696 16:44:35.480825  Dram Type= 6, Freq= 0, CH_1, rank 1

 4697 16:44:35.483707  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4698 16:44:35.484136  ==

 4699 16:44:35.486676  RX Vref Scan: 0

 4700 16:44:35.487122  

 4701 16:44:35.487476  RX Vref 0 -> 0, step: 1

 4702 16:44:35.487791  

 4703 16:44:35.490104  RX Delay -230 -> 252, step: 16

 4704 16:44:35.494069  iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336

 4705 16:44:35.500164  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4706 16:44:35.503409  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4707 16:44:35.507326  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4708 16:44:35.509880  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4709 16:44:35.516454  iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336

 4710 16:44:35.519700  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4711 16:44:35.523238  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4712 16:44:35.526450  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4713 16:44:35.533389  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4714 16:44:35.536342  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4715 16:44:35.539371  iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336

 4716 16:44:35.542738  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4717 16:44:35.549544  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4718 16:44:35.553061  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4719 16:44:35.555743  iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336

 4720 16:44:35.556167  ==

 4721 16:44:35.559259  Dram Type= 6, Freq= 0, CH_1, rank 1

 4722 16:44:35.562878  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4723 16:44:35.563449  ==

 4724 16:44:35.566243  DQS Delay:

 4725 16:44:35.566770  DQS0 = 0, DQS1 = 0

 4726 16:44:35.569103  DQM Delay:

 4727 16:44:35.569525  DQM0 = 43, DQM1 = 38

 4728 16:44:35.569855  DQ Delay:

 4729 16:44:35.572629  DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41

 4730 16:44:35.576569  DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41

 4731 16:44:35.579199  DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33

 4732 16:44:35.582591  DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49

 4733 16:44:35.583129  

 4734 16:44:35.586061  

 4735 16:44:35.586575  ==

 4736 16:44:35.589475  Dram Type= 6, Freq= 0, CH_1, rank 1

 4737 16:44:35.592455  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4738 16:44:35.592982  ==

 4739 16:44:35.593326  

 4740 16:44:35.593636  

 4741 16:44:35.595938  	TX Vref Scan disable

 4742 16:44:35.596459   == TX Byte 0 ==

 4743 16:44:35.602551  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4744 16:44:35.605547  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4745 16:44:35.606013   == TX Byte 1 ==

 4746 16:44:35.612546  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4747 16:44:35.615613  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4748 16:44:35.616148  ==

 4749 16:44:35.618692  Dram Type= 6, Freq= 0, CH_1, rank 1

 4750 16:44:35.622246  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4751 16:44:35.622725  ==

 4752 16:44:35.623217  

 4753 16:44:35.623580  

 4754 16:44:35.625308  	TX Vref Scan disable

 4755 16:44:35.628470   == TX Byte 0 ==

 4756 16:44:35.631736  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4757 16:44:35.638464  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4758 16:44:35.638896   == TX Byte 1 ==

 4759 16:44:35.642228  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4760 16:44:35.648476  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4761 16:44:35.649020  

 4762 16:44:35.649369  [DATLAT]

 4763 16:44:35.649688  Freq=600, CH1 RK1

 4764 16:44:35.649996  

 4765 16:44:35.651837  DATLAT Default: 0x9

 4766 16:44:35.655041  0, 0xFFFF, sum = 0

 4767 16:44:35.655683  1, 0xFFFF, sum = 0

 4768 16:44:35.657990  2, 0xFFFF, sum = 0

 4769 16:44:35.658427  3, 0xFFFF, sum = 0

 4770 16:44:35.661384  4, 0xFFFF, sum = 0

 4771 16:44:35.661845  5, 0xFFFF, sum = 0

 4772 16:44:35.665125  6, 0xFFFF, sum = 0

 4773 16:44:35.665665  7, 0xFFFF, sum = 0

 4774 16:44:35.667885  8, 0x0, sum = 1

 4775 16:44:35.668322  9, 0x0, sum = 2

 4776 16:44:35.671614  10, 0x0, sum = 3

 4777 16:44:35.672156  11, 0x0, sum = 4

 4778 16:44:35.672506  best_step = 9

 4779 16:44:35.672822  

 4780 16:44:35.675290  ==

 4781 16:44:35.678038  Dram Type= 6, Freq= 0, CH_1, rank 1

 4782 16:44:35.681212  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4783 16:44:35.681758  ==

 4784 16:44:35.682108  RX Vref Scan: 0

 4785 16:44:35.682429  

 4786 16:44:35.684184  RX Vref 0 -> 0, step: 1

 4787 16:44:35.684613  

 4788 16:44:35.687482  RX Delay -179 -> 252, step: 8

 4789 16:44:35.694159  iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312

 4790 16:44:35.697659  iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320

 4791 16:44:35.701453  iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320

 4792 16:44:35.704620  iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320

 4793 16:44:35.710378  iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320

 4794 16:44:35.714096  iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312

 4795 16:44:35.718233  iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312

 4796 16:44:35.720503  iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320

 4797 16:44:35.723874  iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312

 4798 16:44:35.730639  iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312

 4799 16:44:35.733788  iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312

 4800 16:44:35.737484  iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312

 4801 16:44:35.740441  iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304

 4802 16:44:35.746915  iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312

 4803 16:44:35.750643  iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312

 4804 16:44:35.753559  iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320

 4805 16:44:35.753991  ==

 4806 16:44:35.757243  Dram Type= 6, Freq= 0, CH_1, rank 1

 4807 16:44:35.763629  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4808 16:44:35.764163  ==

 4809 16:44:35.764514  DQS Delay:

 4810 16:44:35.764833  DQS0 = 0, DQS1 = 0

 4811 16:44:35.766759  DQM Delay:

 4812 16:44:35.767224  DQM0 = 38, DQM1 = 35

 4813 16:44:35.770509  DQ Delay:

 4814 16:44:35.773114  DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36

 4815 16:44:35.776605  DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36

 4816 16:44:35.779822  DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24

 4817 16:44:35.783255  DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44

 4818 16:44:35.783798  

 4819 16:44:35.784142  

 4820 16:44:35.789803  [DQSOSCAuto] RK1, (LSB)MR18= 0x3359, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps

 4821 16:44:35.792931  CH1 RK1: MR19=808, MR18=3359

 4822 16:44:35.799508  CH1_RK1: MR19=0x808, MR18=0x3359, DQSOSC=393, MR23=63, INC=169, DEC=113

 4823 16:44:35.803399  [RxdqsGatingPostProcess] freq 600

 4824 16:44:35.806432  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4825 16:44:35.809441  Pre-setting of DQS Precalculation

 4826 16:44:35.816140  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4827 16:44:35.822535  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4828 16:44:35.829262  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4829 16:44:35.829704  

 4830 16:44:35.830135  

 4831 16:44:35.832306  [Calibration Summary] 1200 Mbps

 4832 16:44:35.832739  CH 0, Rank 0

 4833 16:44:35.836249  SW Impedance     : PASS

 4834 16:44:35.838860  DUTY Scan        : NO K

 4835 16:44:35.839322  ZQ Calibration   : PASS

 4836 16:44:35.842302  Jitter Meter     : NO K

 4837 16:44:35.846279  CBT Training     : PASS

 4838 16:44:35.846713  Write leveling   : PASS

 4839 16:44:35.849827  RX DQS gating    : PASS

 4840 16:44:35.852421  RX DQ/DQS(RDDQC) : PASS

 4841 16:44:35.852909  TX DQ/DQS        : PASS

 4842 16:44:35.855663  RX DATLAT        : PASS

 4843 16:44:35.858642  RX DQ/DQS(Engine): PASS

 4844 16:44:35.859075  TX OE            : NO K

 4845 16:44:35.862791  All Pass.

 4846 16:44:35.863254  

 4847 16:44:35.863677  CH 0, Rank 1

 4848 16:44:35.865643  SW Impedance     : PASS

 4849 16:44:35.866077  DUTY Scan        : NO K

 4850 16:44:35.868846  ZQ Calibration   : PASS

 4851 16:44:35.871964  Jitter Meter     : NO K

 4852 16:44:35.872401  CBT Training     : PASS

 4853 16:44:35.875099  Write leveling   : PASS

 4854 16:44:35.878946  RX DQS gating    : PASS

 4855 16:44:35.879540  RX DQ/DQS(RDDQC) : PASS

 4856 16:44:35.882789  TX DQ/DQS        : PASS

 4857 16:44:35.885589  RX DATLAT        : PASS

 4858 16:44:35.886255  RX DQ/DQS(Engine): PASS

 4859 16:44:35.888528  TX OE            : NO K

 4860 16:44:35.888959  All Pass.

 4861 16:44:35.889298  

 4862 16:44:35.892018  CH 1, Rank 0

 4863 16:44:35.892480  SW Impedance     : PASS

 4864 16:44:35.895155  DUTY Scan        : NO K

 4865 16:44:35.898264  ZQ Calibration   : PASS

 4866 16:44:35.898716  Jitter Meter     : NO K

 4867 16:44:35.901829  CBT Training     : PASS

 4868 16:44:35.904838  Write leveling   : PASS

 4869 16:44:35.905269  RX DQS gating    : PASS

 4870 16:44:35.908495  RX DQ/DQS(RDDQC) : PASS

 4871 16:44:35.909037  TX DQ/DQS        : PASS

 4872 16:44:35.911711  RX DATLAT        : PASS

 4873 16:44:35.915330  RX DQ/DQS(Engine): PASS

 4874 16:44:35.915858  TX OE            : NO K

 4875 16:44:35.917985  All Pass.

 4876 16:44:35.918410  

 4877 16:44:35.918744  CH 1, Rank 1

 4878 16:44:35.921242  SW Impedance     : PASS

 4879 16:44:35.921667  DUTY Scan        : NO K

 4880 16:44:35.924451  ZQ Calibration   : PASS

 4881 16:44:35.928515  Jitter Meter     : NO K

 4882 16:44:35.928938  CBT Training     : PASS

 4883 16:44:35.931489  Write leveling   : PASS

 4884 16:44:35.934994  RX DQS gating    : PASS

 4885 16:44:35.935466  RX DQ/DQS(RDDQC) : PASS

 4886 16:44:35.938055  TX DQ/DQS        : PASS

 4887 16:44:35.941126  RX DATLAT        : PASS

 4888 16:44:35.941660  RX DQ/DQS(Engine): PASS

 4889 16:44:35.944445  TX OE            : NO K

 4890 16:44:35.945005  All Pass.

 4891 16:44:35.945363  

 4892 16:44:35.947627  DramC Write-DBI off

 4893 16:44:35.951301  	PER_BANK_REFRESH: Hybrid Mode

 4894 16:44:35.951744  TX_TRACKING: ON

 4895 16:44:35.961215  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4896 16:44:35.964832  [FAST_K] Save calibration result to emmc

 4897 16:44:35.967507  dramc_set_vcore_voltage set vcore to 662500

 4898 16:44:35.970406  Read voltage for 933, 3

 4899 16:44:35.970827  Vio18 = 0

 4900 16:44:35.973907  Vcore = 662500

 4901 16:44:35.974336  Vdram = 0

 4902 16:44:35.974699  Vddq = 0

 4903 16:44:35.975015  Vmddr = 0

 4904 16:44:35.980661  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4905 16:44:35.986882  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4906 16:44:35.987334  MEM_TYPE=3, freq_sel=17

 4907 16:44:35.990511  sv_algorithm_assistance_LP4_1600 

 4908 16:44:35.993883  ============ PULL DRAM RESETB DOWN ============

 4909 16:44:36.000251  ========== PULL DRAM RESETB DOWN end =========

 4910 16:44:36.003941  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4911 16:44:36.006708  =================================== 

 4912 16:44:36.010593  LPDDR4 DRAM CONFIGURATION

 4913 16:44:36.013488  =================================== 

 4914 16:44:36.014023  EX_ROW_EN[0]    = 0x0

 4915 16:44:36.016808  EX_ROW_EN[1]    = 0x0

 4916 16:44:36.017254  LP4Y_EN      = 0x0

 4917 16:44:36.020244  WORK_FSP     = 0x0

 4918 16:44:36.023331  WL           = 0x3

 4919 16:44:36.023760  RL           = 0x3

 4920 16:44:36.027008  BL           = 0x2

 4921 16:44:36.027462  RPST         = 0x0

 4922 16:44:36.029650  RD_PRE       = 0x0

 4923 16:44:36.030067  WR_PRE       = 0x1

 4924 16:44:36.034067  WR_PST       = 0x0

 4925 16:44:36.034587  DBI_WR       = 0x0

 4926 16:44:36.036594  DBI_RD       = 0x0

 4927 16:44:36.037014  OTF          = 0x1

 4928 16:44:36.039496  =================================== 

 4929 16:44:36.043276  =================================== 

 4930 16:44:36.046358  ANA top config

 4931 16:44:36.049590  =================================== 

 4932 16:44:36.050138  DLL_ASYNC_EN            =  0

 4933 16:44:36.052758  ALL_SLAVE_EN            =  1

 4934 16:44:36.056053  NEW_RANK_MODE           =  1

 4935 16:44:36.059105  DLL_IDLE_MODE           =  1

 4936 16:44:36.062464  LP45_APHY_COMB_EN       =  1

 4937 16:44:36.062882  TX_ODT_DIS              =  1

 4938 16:44:36.066160  NEW_8X_MODE             =  1

 4939 16:44:36.069139  =================================== 

 4940 16:44:36.073049  =================================== 

 4941 16:44:36.076053  data_rate                  = 1866

 4942 16:44:36.078951  CKR                        = 1

 4943 16:44:36.082335  DQ_P2S_RATIO               = 8

 4944 16:44:36.086325  =================================== 

 4945 16:44:36.088870  CA_P2S_RATIO               = 8

 4946 16:44:36.089303  DQ_CA_OPEN                 = 0

 4947 16:44:36.092246  DQ_SEMI_OPEN               = 0

 4948 16:44:36.095436  CA_SEMI_OPEN               = 0

 4949 16:44:36.098877  CA_FULL_RATE               = 0

 4950 16:44:36.102540  DQ_CKDIV4_EN               = 1

 4951 16:44:36.105210  CA_CKDIV4_EN               = 1

 4952 16:44:36.105774  CA_PREDIV_EN               = 0

 4953 16:44:36.109265  PH8_DLY                    = 0

 4954 16:44:36.112158  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4955 16:44:36.115361  DQ_AAMCK_DIV               = 4

 4956 16:44:36.118320  CA_AAMCK_DIV               = 4

 4957 16:44:36.121836  CA_ADMCK_DIV               = 4

 4958 16:44:36.122262  DQ_TRACK_CA_EN             = 0

 4959 16:44:36.124933  CA_PICK                    = 933

 4960 16:44:36.128466  CA_MCKIO                   = 933

 4961 16:44:36.131735  MCKIO_SEMI                 = 0

 4962 16:44:36.134952  PLL_FREQ                   = 3732

 4963 16:44:36.138022  DQ_UI_PI_RATIO             = 32

 4964 16:44:36.142144  CA_UI_PI_RATIO             = 0

 4965 16:44:36.145415  =================================== 

 4966 16:44:36.148283  =================================== 

 4967 16:44:36.148949  memory_type:LPDDR4         

 4968 16:44:36.151089  GP_NUM     : 10       

 4969 16:44:36.154588  SRAM_EN    : 1       

 4970 16:44:36.155017  MD32_EN    : 0       

 4971 16:44:36.158055  =================================== 

 4972 16:44:36.161240  [ANA_INIT] >>>>>>>>>>>>>> 

 4973 16:44:36.164834  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4974 16:44:36.167750  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4975 16:44:36.171227  =================================== 

 4976 16:44:36.174432  data_rate = 1866,PCW = 0X8f00

 4977 16:44:36.177834  =================================== 

 4978 16:44:36.181496  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4979 16:44:36.187843  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4980 16:44:36.190903  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4981 16:44:36.197788  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4982 16:44:36.200653  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4983 16:44:36.204246  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4984 16:44:36.204840  [ANA_INIT] flow start 

 4985 16:44:36.207276  [ANA_INIT] PLL >>>>>>>> 

 4986 16:44:36.210874  [ANA_INIT] PLL <<<<<<<< 

 4987 16:44:36.211499  [ANA_INIT] MIDPI >>>>>>>> 

 4988 16:44:36.214123  [ANA_INIT] MIDPI <<<<<<<< 

 4989 16:44:36.218207  [ANA_INIT] DLL >>>>>>>> 

 4990 16:44:36.218738  [ANA_INIT] flow end 

 4991 16:44:36.224246  ============ LP4 DIFF to SE enter ============

 4992 16:44:36.227218  ============ LP4 DIFF to SE exit  ============

 4993 16:44:36.230123  [ANA_INIT] <<<<<<<<<<<<< 

 4994 16:44:36.233719  [Flow] Enable top DCM control >>>>> 

 4995 16:44:36.237836  [Flow] Enable top DCM control <<<<< 

 4996 16:44:36.238271  Enable DLL master slave shuffle 

 4997 16:44:36.243753  ============================================================== 

 4998 16:44:36.247335  Gating Mode config

 4999 16:44:36.250530  ============================================================== 

 5000 16:44:36.253822  Config description: 

 5001 16:44:36.263235  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 5002 16:44:36.271140  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 5003 16:44:36.273713  SELPH_MODE            0: By rank         1: By Phase 

 5004 16:44:36.280038  ============================================================== 

 5005 16:44:36.283048  GAT_TRACK_EN                 =  1

 5006 16:44:36.286484  RX_GATING_MODE               =  2

 5007 16:44:36.289854  RX_GATING_TRACK_MODE         =  2

 5008 16:44:36.292805  SELPH_MODE                   =  1

 5009 16:44:36.295905  PICG_EARLY_EN                =  1

 5010 16:44:36.299742  VALID_LAT_VALUE              =  1

 5011 16:44:36.302701  ============================================================== 

 5012 16:44:36.305996  Enter into Gating configuration >>>> 

 5013 16:44:36.309340  Exit from Gating configuration <<<< 

 5014 16:44:36.312892  Enter into  DVFS_PRE_config >>>>> 

 5015 16:44:36.325500  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 5016 16:44:36.329314  Exit from  DVFS_PRE_config <<<<< 

 5017 16:44:36.329751  Enter into PICG configuration >>>> 

 5018 16:44:36.332364  Exit from PICG configuration <<<< 

 5019 16:44:36.335258  [RX_INPUT] configuration >>>>> 

 5020 16:44:36.338789  [RX_INPUT] configuration <<<<< 

 5021 16:44:36.345545  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 5022 16:44:36.348971  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 5023 16:44:36.355643  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 5024 16:44:36.362264  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 5025 16:44:36.368922  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5026 16:44:36.375569  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5027 16:44:36.378308  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5028 16:44:36.381751  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5029 16:44:36.388097  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5030 16:44:36.392063  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5031 16:44:36.394878  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5032 16:44:36.398282  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5033 16:44:36.401325  =================================== 

 5034 16:44:36.405173  LPDDR4 DRAM CONFIGURATION

 5035 16:44:36.407933  =================================== 

 5036 16:44:36.411564  EX_ROW_EN[0]    = 0x0

 5037 16:44:36.412093  EX_ROW_EN[1]    = 0x0

 5038 16:44:36.415057  LP4Y_EN      = 0x0

 5039 16:44:36.415659  WORK_FSP     = 0x0

 5040 16:44:36.417698  WL           = 0x3

 5041 16:44:36.418125  RL           = 0x3

 5042 16:44:36.421515  BL           = 0x2

 5043 16:44:36.424450  RPST         = 0x0

 5044 16:44:36.424892  RD_PRE       = 0x0

 5045 16:44:36.427570  WR_PRE       = 0x1

 5046 16:44:36.427997  WR_PST       = 0x0

 5047 16:44:36.431276  DBI_WR       = 0x0

 5048 16:44:36.431789  DBI_RD       = 0x0

 5049 16:44:36.434362  OTF          = 0x1

 5050 16:44:36.438595  =================================== 

 5051 16:44:36.440855  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5052 16:44:36.444113  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5053 16:44:36.447251  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5054 16:44:36.450926  =================================== 

 5055 16:44:36.454692  LPDDR4 DRAM CONFIGURATION

 5056 16:44:36.457989  =================================== 

 5057 16:44:36.460428  EX_ROW_EN[0]    = 0x10

 5058 16:44:36.460902  EX_ROW_EN[1]    = 0x0

 5059 16:44:36.463713  LP4Y_EN      = 0x0

 5060 16:44:36.464182  WORK_FSP     = 0x0

 5061 16:44:36.467808  WL           = 0x3

 5062 16:44:36.470269  RL           = 0x3

 5063 16:44:36.470738  BL           = 0x2

 5064 16:44:36.474263  RPST         = 0x0

 5065 16:44:36.474836  RD_PRE       = 0x0

 5066 16:44:36.477139  WR_PRE       = 0x1

 5067 16:44:36.477610  WR_PST       = 0x0

 5068 16:44:36.480405  DBI_WR       = 0x0

 5069 16:44:36.480968  DBI_RD       = 0x0

 5070 16:44:36.483731  OTF          = 0x1

 5071 16:44:36.487214  =================================== 

 5072 16:44:36.493547  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5073 16:44:36.496925  nWR fixed to 30

 5074 16:44:36.497452  [ModeRegInit_LP4] CH0 RK0

 5075 16:44:36.500421  [ModeRegInit_LP4] CH0 RK1

 5076 16:44:36.503383  [ModeRegInit_LP4] CH1 RK0

 5077 16:44:36.506709  [ModeRegInit_LP4] CH1 RK1

 5078 16:44:36.507150  match AC timing 9

 5079 16:44:36.510020  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5080 16:44:36.516699  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5081 16:44:36.519883  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5082 16:44:36.526336  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5083 16:44:36.529251  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5084 16:44:36.529721  ==

 5085 16:44:36.532807  Dram Type= 6, Freq= 0, CH_0, rank 0

 5086 16:44:36.536176  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5087 16:44:36.536747  ==

 5088 16:44:36.542667  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5089 16:44:36.549153  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5090 16:44:36.552282  [CA 0] Center 37 (7~68) winsize 62

 5091 16:44:36.556088  [CA 1] Center 37 (7~68) winsize 62

 5092 16:44:36.559302  [CA 2] Center 34 (4~65) winsize 62

 5093 16:44:36.562499  [CA 3] Center 34 (4~65) winsize 62

 5094 16:44:36.565895  [CA 4] Center 32 (2~63) winsize 62

 5095 16:44:36.569106  [CA 5] Center 32 (2~63) winsize 62

 5096 16:44:36.569676  

 5097 16:44:36.572254  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5098 16:44:36.572816  

 5099 16:44:36.575429  [CATrainingPosCal] consider 1 rank data

 5100 16:44:36.579055  u2DelayCellTimex100 = 270/100 ps

 5101 16:44:36.582087  CA0 delay=37 (7~68),Diff = 5 PI (31 cell)

 5102 16:44:36.585075  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5103 16:44:36.588400  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5104 16:44:36.591790  CA3 delay=34 (4~65),Diff = 2 PI (12 cell)

 5105 16:44:36.598251  CA4 delay=32 (2~63),Diff = 0 PI (0 cell)

 5106 16:44:36.601633  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 5107 16:44:36.602106  

 5108 16:44:36.605250  CA PerBit enable=1, Macro0, CA PI delay=32

 5109 16:44:36.605813  

 5110 16:44:36.608592  [CBTSetCACLKResult] CA Dly = 32

 5111 16:44:36.609155  CS Dly: 5 (0~36)

 5112 16:44:36.609528  ==

 5113 16:44:36.611590  Dram Type= 6, Freq= 0, CH_0, rank 1

 5114 16:44:36.618187  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5115 16:44:36.618771  ==

 5116 16:44:36.621214  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5117 16:44:36.627846  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5118 16:44:36.631096  [CA 0] Center 37 (7~68) winsize 62

 5119 16:44:36.634930  [CA 1] Center 37 (7~68) winsize 62

 5120 16:44:36.638003  [CA 2] Center 35 (5~65) winsize 61

 5121 16:44:36.640972  [CA 3] Center 34 (4~65) winsize 62

 5122 16:44:36.644132  [CA 4] Center 33 (3~64) winsize 62

 5123 16:44:36.647555  [CA 5] Center 32 (2~63) winsize 62

 5124 16:44:36.648119  

 5125 16:44:36.650991  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5126 16:44:36.651592  

 5127 16:44:36.654771  [CATrainingPosCal] consider 2 rank data

 5128 16:44:36.657985  u2DelayCellTimex100 = 270/100 ps

 5129 16:44:36.663726  CA0 delay=37 (7~68),Diff = 5 PI (31 cell)

 5130 16:44:36.667273  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5131 16:44:36.670383  CA2 delay=35 (5~65),Diff = 3 PI (18 cell)

 5132 16:44:36.674100  CA3 delay=34 (4~65),Diff = 2 PI (12 cell)

 5133 16:44:36.677091  CA4 delay=33 (3~63),Diff = 1 PI (6 cell)

 5134 16:44:36.680015  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 5135 16:44:36.680571  

 5136 16:44:36.683745  CA PerBit enable=1, Macro0, CA PI delay=32

 5137 16:44:36.684214  

 5138 16:44:36.687296  [CBTSetCACLKResult] CA Dly = 32

 5139 16:44:36.689941  CS Dly: 6 (0~39)

 5140 16:44:36.690407  

 5141 16:44:36.693734  ----->DramcWriteLeveling(PI) begin...

 5142 16:44:36.694305  ==

 5143 16:44:36.697203  Dram Type= 6, Freq= 0, CH_0, rank 0

 5144 16:44:36.699930  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5145 16:44:36.700444  ==

 5146 16:44:36.703073  Write leveling (Byte 0): 32 => 32

 5147 16:44:36.706661  Write leveling (Byte 1): 30 => 30

 5148 16:44:36.710386  DramcWriteLeveling(PI) end<-----

 5149 16:44:36.710946  

 5150 16:44:36.711352  ==

 5151 16:44:36.713027  Dram Type= 6, Freq= 0, CH_0, rank 0

 5152 16:44:36.716441  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5153 16:44:36.717031  ==

 5154 16:44:36.719662  [Gating] SW mode calibration

 5155 16:44:36.726208  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5156 16:44:36.732812  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5157 16:44:36.735892   0 14  0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)

 5158 16:44:36.742666   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5159 16:44:36.746226   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5160 16:44:36.749212   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5161 16:44:36.755824   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5162 16:44:36.759394   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5163 16:44:36.762595   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5164 16:44:36.769566   0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)

 5165 16:44:36.772733   0 15  0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)

 5166 16:44:36.775898   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5167 16:44:36.782303   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5168 16:44:36.785444   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5169 16:44:36.788556   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5170 16:44:36.795812   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5171 16:44:36.799121   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5172 16:44:36.801658   0 15 28 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)

 5173 16:44:36.808383   1  0  0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)

 5174 16:44:36.812213   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5175 16:44:36.815024   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5176 16:44:36.821541   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5177 16:44:36.825212   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5178 16:44:36.828379   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5179 16:44:36.834905   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5180 16:44:36.838226   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5181 16:44:36.841591   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5182 16:44:36.848602   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5183 16:44:36.851467   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5184 16:44:36.854916   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5185 16:44:36.861227   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5186 16:44:36.864798   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5187 16:44:36.867500   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5188 16:44:36.874601   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5189 16:44:36.877594   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5190 16:44:36.881174   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5191 16:44:36.887647   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5192 16:44:36.891152   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5193 16:44:36.894268   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5194 16:44:36.900584   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5195 16:44:36.903806   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5196 16:44:36.907213   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5197 16:44:36.913607   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5198 16:44:36.917064  Total UI for P1: 0, mck2ui 16

 5199 16:44:36.920289  best dqsien dly found for B0: ( 1,  2, 26)

 5200 16:44:36.923757  Total UI for P1: 0, mck2ui 16

 5201 16:44:36.927096  best dqsien dly found for B1: ( 1,  2, 30)

 5202 16:44:36.929933  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5203 16:44:36.934489  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5204 16:44:36.935068  

 5205 16:44:36.937027  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5206 16:44:36.939945  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5207 16:44:36.943318  [Gating] SW calibration Done

 5208 16:44:36.943789  ==

 5209 16:44:36.946942  Dram Type= 6, Freq= 0, CH_0, rank 0

 5210 16:44:36.949797  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5211 16:44:36.950370  ==

 5212 16:44:36.953231  RX Vref Scan: 0

 5213 16:44:36.953802  

 5214 16:44:36.956687  RX Vref 0 -> 0, step: 1

 5215 16:44:36.957262  

 5216 16:44:36.957636  RX Delay -80 -> 252, step: 8

 5217 16:44:36.962967  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5218 16:44:36.966578  iDelay=208, Bit 1, Center 103 (8 ~ 199) 192

 5219 16:44:36.969758  iDelay=208, Bit 2, Center 95 (0 ~ 191) 192

 5220 16:44:36.973243  iDelay=208, Bit 3, Center 95 (0 ~ 191) 192

 5221 16:44:36.976023  iDelay=208, Bit 4, Center 103 (8 ~ 199) 192

 5222 16:44:36.983367  iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192

 5223 16:44:36.986234  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5224 16:44:36.989320  iDelay=208, Bit 7, Center 111 (16 ~ 207) 192

 5225 16:44:36.993038  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5226 16:44:36.996048  iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184

 5227 16:44:37.002887  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5228 16:44:37.005906  iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184

 5229 16:44:37.009264  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5230 16:44:37.012872  iDelay=208, Bit 13, Center 95 (0 ~ 191) 192

 5231 16:44:37.015905  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5232 16:44:37.019022  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5233 16:44:37.022362  ==

 5234 16:44:37.025324  Dram Type= 6, Freq= 0, CH_0, rank 0

 5235 16:44:37.028975  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5236 16:44:37.029453  ==

 5237 16:44:37.029828  DQS Delay:

 5238 16:44:37.031825  DQS0 = 0, DQS1 = 0

 5239 16:44:37.032296  DQM Delay:

 5240 16:44:37.035343  DQM0 = 101, DQM1 = 88

 5241 16:44:37.035815  DQ Delay:

 5242 16:44:37.038369  DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95

 5243 16:44:37.041852  DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111

 5244 16:44:37.045775  DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83

 5245 16:44:37.048856  DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95

 5246 16:44:37.049328  

 5247 16:44:37.049698  

 5248 16:44:37.050044  ==

 5249 16:44:37.051827  Dram Type= 6, Freq= 0, CH_0, rank 0

 5250 16:44:37.054955  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5251 16:44:37.058861  ==

 5252 16:44:37.059456  

 5253 16:44:37.059805  

 5254 16:44:37.060121  	TX Vref Scan disable

 5255 16:44:37.061441   == TX Byte 0 ==

 5256 16:44:37.065370  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5257 16:44:37.068548  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5258 16:44:37.071700   == TX Byte 1 ==

 5259 16:44:37.075253  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5260 16:44:37.078353  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5261 16:44:37.082063  ==

 5262 16:44:37.082584  Dram Type= 6, Freq= 0, CH_0, rank 0

 5263 16:44:37.088624  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5264 16:44:37.089156  ==

 5265 16:44:37.089499  

 5266 16:44:37.089813  

 5267 16:44:37.091363  	TX Vref Scan disable

 5268 16:44:37.091781   == TX Byte 0 ==

 5269 16:44:37.098141  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5270 16:44:37.101058  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5271 16:44:37.101481   == TX Byte 1 ==

 5272 16:44:37.107929  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5273 16:44:37.111311  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5274 16:44:37.111826  

 5275 16:44:37.112157  [DATLAT]

 5276 16:44:37.114860  Freq=933, CH0 RK0

 5277 16:44:37.115488  

 5278 16:44:37.115868  DATLAT Default: 0xd

 5279 16:44:37.117927  0, 0xFFFF, sum = 0

 5280 16:44:37.118507  1, 0xFFFF, sum = 0

 5281 16:44:37.120798  2, 0xFFFF, sum = 0

 5282 16:44:37.121269  3, 0xFFFF, sum = 0

 5283 16:44:37.124569  4, 0xFFFF, sum = 0

 5284 16:44:37.124991  5, 0xFFFF, sum = 0

 5285 16:44:37.127959  6, 0xFFFF, sum = 0

 5286 16:44:37.131313  7, 0xFFFF, sum = 0

 5287 16:44:37.131752  8, 0xFFFF, sum = 0

 5288 16:44:37.134478  9, 0xFFFF, sum = 0

 5289 16:44:37.134912  10, 0x0, sum = 1

 5290 16:44:37.138079  11, 0x0, sum = 2

 5291 16:44:37.138514  12, 0x0, sum = 3

 5292 16:44:37.138981  13, 0x0, sum = 4

 5293 16:44:37.140674  best_step = 11

 5294 16:44:37.141135  

 5295 16:44:37.141556  ==

 5296 16:44:37.143929  Dram Type= 6, Freq= 0, CH_0, rank 0

 5297 16:44:37.147428  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5298 16:44:37.147874  ==

 5299 16:44:37.151121  RX Vref Scan: 1

 5300 16:44:37.151612  

 5301 16:44:37.154209  RX Vref 0 -> 0, step: 1

 5302 16:44:37.154738  

 5303 16:44:37.155222  RX Delay -61 -> 252, step: 4

 5304 16:44:37.155633  

 5305 16:44:37.157460  Set Vref, RX VrefLevel [Byte0]: 56

 5306 16:44:37.160657                           [Byte1]: 59

 5307 16:44:37.165471  

 5308 16:44:37.166001  Final RX Vref Byte 0 = 56 to rank0

 5309 16:44:37.168628  Final RX Vref Byte 1 = 59 to rank0

 5310 16:44:37.171919  Final RX Vref Byte 0 = 56 to rank1

 5311 16:44:37.174960  Final RX Vref Byte 1 = 59 to rank1==

 5312 16:44:37.178754  Dram Type= 6, Freq= 0, CH_0, rank 0

 5313 16:44:37.185049  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5314 16:44:37.185581  ==

 5315 16:44:37.186016  DQS Delay:

 5316 16:44:37.188404  DQS0 = 0, DQS1 = 0

 5317 16:44:37.188929  DQM Delay:

 5318 16:44:37.189371  DQM0 = 98, DQM1 = 87

 5319 16:44:37.191237  DQ Delay:

 5320 16:44:37.195291  DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94

 5321 16:44:37.197870  DQ4 =102, DQ5 =90, DQ6 =110, DQ7 =106

 5322 16:44:37.201419  DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82

 5323 16:44:37.204733  DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =94

 5324 16:44:37.205270  

 5325 16:44:37.205704  

 5326 16:44:37.211167  [DQSOSCAuto] RK0, (LSB)MR18= 0x1c16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps

 5327 16:44:37.214476  CH0 RK0: MR19=505, MR18=1C16

 5328 16:44:37.221200  CH0_RK0: MR19=0x505, MR18=0x1C16, DQSOSC=412, MR23=63, INC=63, DEC=42

 5329 16:44:37.221733  

 5330 16:44:37.225407  ----->DramcWriteLeveling(PI) begin...

 5331 16:44:37.225940  ==

 5332 16:44:37.227586  Dram Type= 6, Freq= 0, CH_0, rank 1

 5333 16:44:37.230565  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5334 16:44:37.234087  ==

 5335 16:44:37.234621  Write leveling (Byte 0): 29 => 29

 5336 16:44:37.238230  Write leveling (Byte 1): 28 => 28

 5337 16:44:37.240812  DramcWriteLeveling(PI) end<-----

 5338 16:44:37.241347  

 5339 16:44:37.241780  ==

 5340 16:44:37.243638  Dram Type= 6, Freq= 0, CH_0, rank 1

 5341 16:44:37.250512  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5342 16:44:37.251060  ==

 5343 16:44:37.253875  [Gating] SW mode calibration

 5344 16:44:37.260354  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5345 16:44:37.263336  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5346 16:44:37.270097   0 14  0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)

 5347 16:44:37.273419   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5348 16:44:37.276706   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5349 16:44:37.283239   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5350 16:44:37.286831   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5351 16:44:37.289890   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5352 16:44:37.296105   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5353 16:44:37.299631   0 14 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)

 5354 16:44:37.302894   0 15  0 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)

 5355 16:44:37.309492   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5356 16:44:37.312809   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5357 16:44:37.316056   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5358 16:44:37.322653   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5359 16:44:37.325834   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5360 16:44:37.329652   0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)

 5361 16:44:37.336159   0 15 28 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)

 5362 16:44:37.338894   1  0  0 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)

 5363 16:44:37.343003   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5364 16:44:37.348646   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5365 16:44:37.352312   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5366 16:44:37.355368   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5367 16:44:37.362093   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5368 16:44:37.365226   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5369 16:44:37.368924   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5370 16:44:37.375843   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5371 16:44:37.378607   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5372 16:44:37.381912   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5373 16:44:37.388562   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5374 16:44:37.392357   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5375 16:44:37.395278   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5376 16:44:37.402241   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5377 16:44:37.405503   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5378 16:44:37.408112   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5379 16:44:37.414855   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5380 16:44:37.418434   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5381 16:44:37.421444   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5382 16:44:37.427971   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5383 16:44:37.431529   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5384 16:44:37.434869   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5385 16:44:37.441077   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5386 16:44:37.444566   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5387 16:44:37.447884  Total UI for P1: 0, mck2ui 16

 5388 16:44:37.451427  best dqsien dly found for B0: ( 1,  2, 28)

 5389 16:44:37.455367   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5390 16:44:37.457799  Total UI for P1: 0, mck2ui 16

 5391 16:44:37.461325  best dqsien dly found for B1: ( 1,  3,  0)

 5392 16:44:37.463985  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5393 16:44:37.467994  best DQS1 dly(MCK, UI, PI) = (1, 3, 0)

 5394 16:44:37.468558  

 5395 16:44:37.474098  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5396 16:44:37.477816  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5397 16:44:37.481038  [Gating] SW calibration Done

 5398 16:44:37.481597  ==

 5399 16:44:37.484518  Dram Type= 6, Freq= 0, CH_0, rank 1

 5400 16:44:37.487799  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5401 16:44:37.488353  ==

 5402 16:44:37.488759  RX Vref Scan: 0

 5403 16:44:37.489096  

 5404 16:44:37.490456  RX Vref 0 -> 0, step: 1

 5405 16:44:37.490926  

 5406 16:44:37.494372  RX Delay -80 -> 252, step: 8

 5407 16:44:37.497025  iDelay=200, Bit 0, Center 95 (0 ~ 191) 192

 5408 16:44:37.500668  iDelay=200, Bit 1, Center 99 (0 ~ 199) 200

 5409 16:44:37.507028  iDelay=200, Bit 2, Center 95 (0 ~ 191) 192

 5410 16:44:37.510737  iDelay=200, Bit 3, Center 95 (0 ~ 191) 192

 5411 16:44:37.513388  iDelay=200, Bit 4, Center 103 (8 ~ 199) 192

 5412 16:44:37.517088  iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192

 5413 16:44:37.520511  iDelay=200, Bit 6, Center 103 (8 ~ 199) 192

 5414 16:44:37.523241  iDelay=200, Bit 7, Center 107 (16 ~ 199) 184

 5415 16:44:37.530088  iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184

 5416 16:44:37.533255  iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176

 5417 16:44:37.536575  iDelay=200, Bit 10, Center 91 (0 ~ 183) 184

 5418 16:44:37.539764  iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184

 5419 16:44:37.543588  iDelay=200, Bit 12, Center 95 (0 ~ 191) 192

 5420 16:44:37.549799  iDelay=200, Bit 13, Center 95 (0 ~ 191) 192

 5421 16:44:37.554088  iDelay=200, Bit 14, Center 99 (8 ~ 191) 184

 5422 16:44:37.556871  iDelay=200, Bit 15, Center 95 (0 ~ 191) 192

 5423 16:44:37.557451  ==

 5424 16:44:37.559721  Dram Type= 6, Freq= 0, CH_0, rank 1

 5425 16:44:37.562892  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5426 16:44:37.563537  ==

 5427 16:44:37.566229  DQS Delay:

 5428 16:44:37.566769  DQS0 = 0, DQS1 = 0

 5429 16:44:37.569139  DQM Delay:

 5430 16:44:37.569612  DQM0 = 98, DQM1 = 90

 5431 16:44:37.570083  DQ Delay:

 5432 16:44:37.573086  DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95

 5433 16:44:37.575970  DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =107

 5434 16:44:37.579404  DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83

 5435 16:44:37.582724  DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95

 5436 16:44:37.583331  

 5437 16:44:37.586012  

 5438 16:44:37.586585  ==

 5439 16:44:37.589034  Dram Type= 6, Freq= 0, CH_0, rank 1

 5440 16:44:37.592109  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5441 16:44:37.592611  ==

 5442 16:44:37.593103  

 5443 16:44:37.593557  

 5444 16:44:37.595667  	TX Vref Scan disable

 5445 16:44:37.596144   == TX Byte 0 ==

 5446 16:44:37.602072  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5447 16:44:37.605486  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5448 16:44:37.606066   == TX Byte 1 ==

 5449 16:44:37.611975  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5450 16:44:37.615553  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5451 16:44:37.616134  ==

 5452 16:44:37.618396  Dram Type= 6, Freq= 0, CH_0, rank 1

 5453 16:44:37.622231  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5454 16:44:37.622812  ==

 5455 16:44:37.623416  

 5456 16:44:37.623874  

 5457 16:44:37.625341  	TX Vref Scan disable

 5458 16:44:37.628139   == TX Byte 0 ==

 5459 16:44:37.631731  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5460 16:44:37.635065  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5461 16:44:37.638366   == TX Byte 1 ==

 5462 16:44:37.641697  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5463 16:44:37.645154  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5464 16:44:37.645644  

 5465 16:44:37.648331  [DATLAT]

 5466 16:44:37.648758  Freq=933, CH0 RK1

 5467 16:44:37.649186  

 5468 16:44:37.651759  DATLAT Default: 0xb

 5469 16:44:37.652190  0, 0xFFFF, sum = 0

 5470 16:44:37.654877  1, 0xFFFF, sum = 0

 5471 16:44:37.655354  2, 0xFFFF, sum = 0

 5472 16:44:37.657945  3, 0xFFFF, sum = 0

 5473 16:44:37.658382  4, 0xFFFF, sum = 0

 5474 16:44:37.661223  5, 0xFFFF, sum = 0

 5475 16:44:37.665000  6, 0xFFFF, sum = 0

 5476 16:44:37.665576  7, 0xFFFF, sum = 0

 5477 16:44:37.668328  8, 0xFFFF, sum = 0

 5478 16:44:37.668868  9, 0xFFFF, sum = 0

 5479 16:44:37.671048  10, 0x0, sum = 1

 5480 16:44:37.671640  11, 0x0, sum = 2

 5481 16:44:37.674485  12, 0x0, sum = 3

 5482 16:44:37.674925  13, 0x0, sum = 4

 5483 16:44:37.675466  best_step = 11

 5484 16:44:37.675880  

 5485 16:44:37.677530  ==

 5486 16:44:37.681529  Dram Type= 6, Freq= 0, CH_0, rank 1

 5487 16:44:37.684483  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5488 16:44:37.685034  ==

 5489 16:44:37.685474  RX Vref Scan: 0

 5490 16:44:37.685878  

 5491 16:44:37.689024  RX Vref 0 -> 0, step: 1

 5492 16:44:37.689560  

 5493 16:44:37.691324  RX Delay -53 -> 252, step: 4

 5494 16:44:37.693997  iDelay=199, Bit 0, Center 98 (11 ~ 186) 176

 5495 16:44:37.701181  iDelay=199, Bit 1, Center 98 (7 ~ 190) 184

 5496 16:44:37.704212  iDelay=199, Bit 2, Center 92 (3 ~ 182) 180

 5497 16:44:37.707468  iDelay=199, Bit 3, Center 96 (7 ~ 186) 180

 5498 16:44:37.710804  iDelay=199, Bit 4, Center 100 (11 ~ 190) 180

 5499 16:44:37.713966  iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184

 5500 16:44:37.720400  iDelay=199, Bit 6, Center 108 (19 ~ 198) 180

 5501 16:44:37.723899  iDelay=199, Bit 7, Center 106 (19 ~ 194) 176

 5502 16:44:37.727368  iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180

 5503 16:44:37.730579  iDelay=199, Bit 9, Center 76 (-9 ~ 162) 172

 5504 16:44:37.733810  iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180

 5505 16:44:37.737281  iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176

 5506 16:44:37.743358  iDelay=199, Bit 12, Center 94 (7 ~ 182) 176

 5507 16:44:37.747274  iDelay=199, Bit 13, Center 92 (3 ~ 182) 180

 5508 16:44:37.750394  iDelay=199, Bit 14, Center 102 (15 ~ 190) 176

 5509 16:44:37.753978  iDelay=199, Bit 15, Center 96 (7 ~ 186) 180

 5510 16:44:37.754560  ==

 5511 16:44:37.757141  Dram Type= 6, Freq= 0, CH_0, rank 1

 5512 16:44:37.763593  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5513 16:44:37.764163  ==

 5514 16:44:37.764541  DQS Delay:

 5515 16:44:37.766751  DQS0 = 0, DQS1 = 0

 5516 16:44:37.767245  DQM Delay:

 5517 16:44:37.767657  DQM0 = 98, DQM1 = 88

 5518 16:44:37.770248  DQ Delay:

 5519 16:44:37.773349  DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =96

 5520 16:44:37.777051  DQ4 =100, DQ5 =86, DQ6 =108, DQ7 =106

 5521 16:44:37.780262  DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82

 5522 16:44:37.783201  DQ12 =94, DQ13 =92, DQ14 =102, DQ15 =96

 5523 16:44:37.783767  

 5524 16:44:37.784140  

 5525 16:44:37.790416  [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps

 5526 16:44:37.793298  CH0 RK1: MR19=505, MR18=1412

 5527 16:44:37.799773  CH0_RK1: MR19=0x505, MR18=0x1412, DQSOSC=415, MR23=63, INC=62, DEC=41

 5528 16:44:37.803300  [RxdqsGatingPostProcess] freq 933

 5529 16:44:37.809671  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5530 16:44:37.810225  best DQS0 dly(2T, 0.5T) = (0, 10)

 5531 16:44:37.813195  best DQS1 dly(2T, 0.5T) = (0, 10)

 5532 16:44:37.816314  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5533 16:44:37.819332  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5534 16:44:37.822525  best DQS0 dly(2T, 0.5T) = (0, 10)

 5535 16:44:37.826219  best DQS1 dly(2T, 0.5T) = (0, 11)

 5536 16:44:37.829082  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5537 16:44:37.832452  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5538 16:44:37.835868  Pre-setting of DQS Precalculation

 5539 16:44:37.842427  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5540 16:44:37.842866  ==

 5541 16:44:37.846113  Dram Type= 6, Freq= 0, CH_1, rank 0

 5542 16:44:37.848828  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5543 16:44:37.849254  ==

 5544 16:44:37.855712  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5545 16:44:37.859293  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5546 16:44:37.863098  [CA 0] Center 36 (6~67) winsize 62

 5547 16:44:37.866660  [CA 1] Center 36 (6~67) winsize 62

 5548 16:44:37.870065  [CA 2] Center 34 (4~65) winsize 62

 5549 16:44:37.872839  [CA 3] Center 34 (3~65) winsize 63

 5550 16:44:37.876858  [CA 4] Center 34 (4~65) winsize 62

 5551 16:44:37.880040  [CA 5] Center 33 (3~64) winsize 62

 5552 16:44:37.880602  

 5553 16:44:37.883090  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5554 16:44:37.883693  

 5555 16:44:37.886460  [CATrainingPosCal] consider 1 rank data

 5556 16:44:37.889691  u2DelayCellTimex100 = 270/100 ps

 5557 16:44:37.893465  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5558 16:44:37.899505  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5559 16:44:37.902995  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5560 16:44:37.906058  CA3 delay=34 (3~65),Diff = 1 PI (6 cell)

 5561 16:44:37.909382  CA4 delay=34 (4~65),Diff = 1 PI (6 cell)

 5562 16:44:37.912712  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5563 16:44:37.913274  

 5564 16:44:37.916140  CA PerBit enable=1, Macro0, CA PI delay=33

 5565 16:44:37.916704  

 5566 16:44:37.918937  [CBTSetCACLKResult] CA Dly = 33

 5567 16:44:37.922438  CS Dly: 5 (0~36)

 5568 16:44:37.923014  ==

 5569 16:44:37.925476  Dram Type= 6, Freq= 0, CH_1, rank 1

 5570 16:44:37.929005  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5571 16:44:37.929472  ==

 5572 16:44:37.935858  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5573 16:44:37.938512  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 5574 16:44:37.943213  [CA 0] Center 36 (6~66) winsize 61

 5575 16:44:37.946096  [CA 1] Center 36 (6~67) winsize 62

 5576 16:44:37.949464  [CA 2] Center 34 (4~64) winsize 61

 5577 16:44:37.953201  [CA 3] Center 33 (3~64) winsize 62

 5578 16:44:37.956162  [CA 4] Center 33 (3~64) winsize 62

 5579 16:44:37.959588  [CA 5] Center 33 (3~64) winsize 62

 5580 16:44:37.960020  

 5581 16:44:37.962796  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 5582 16:44:37.963469  

 5583 16:44:37.966014  [CATrainingPosCal] consider 2 rank data

 5584 16:44:37.970244  u2DelayCellTimex100 = 270/100 ps

 5585 16:44:37.972513  CA0 delay=36 (6~66),Diff = 3 PI (18 cell)

 5586 16:44:37.979251  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5587 16:44:37.982705  CA2 delay=34 (4~64),Diff = 1 PI (6 cell)

 5588 16:44:37.986642  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5589 16:44:37.989596  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5590 16:44:37.992424  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5591 16:44:37.992859  

 5592 16:44:37.995732  CA PerBit enable=1, Macro0, CA PI delay=33

 5593 16:44:37.996272  

 5594 16:44:37.998929  [CBTSetCACLKResult] CA Dly = 33

 5595 16:44:38.002844  CS Dly: 6 (0~38)

 5596 16:44:38.003452  

 5597 16:44:38.005833  ----->DramcWriteLeveling(PI) begin...

 5598 16:44:38.006414  ==

 5599 16:44:38.008614  Dram Type= 6, Freq= 0, CH_1, rank 0

 5600 16:44:38.012682  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5601 16:44:38.013348  ==

 5602 16:44:38.015603  Write leveling (Byte 0): 27 => 27

 5603 16:44:38.018801  Write leveling (Byte 1): 31 => 31

 5604 16:44:38.022425  DramcWriteLeveling(PI) end<-----

 5605 16:44:38.022902  

 5606 16:44:38.023310  ==

 5607 16:44:38.025256  Dram Type= 6, Freq= 0, CH_1, rank 0

 5608 16:44:38.029071  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5609 16:44:38.029549  ==

 5610 16:44:38.032009  [Gating] SW mode calibration

 5611 16:44:38.038507  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5612 16:44:38.045318  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5613 16:44:38.048206   0 14  0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 5614 16:44:38.051920   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5615 16:44:38.058010   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5616 16:44:38.061256   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5617 16:44:38.064893   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5618 16:44:38.071276   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5619 16:44:38.075460   0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)

 5620 16:44:38.077772   0 14 28 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 1)

 5621 16:44:38.084684   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5622 16:44:38.088284   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5623 16:44:38.091163   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5624 16:44:38.097848   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5625 16:44:38.101368   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5626 16:44:38.103847   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5627 16:44:38.110451   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5628 16:44:38.114170   0 15 28 | B1->B0 | 3737 4444 | 0 1 | (0 0) (0 0)

 5629 16:44:38.117547   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5630 16:44:38.123960   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5631 16:44:38.127553   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5632 16:44:38.130882   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5633 16:44:38.137136   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5634 16:44:38.140805   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5635 16:44:38.143664   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5636 16:44:38.150625   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5637 16:44:38.154016   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5638 16:44:38.157141   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5639 16:44:38.163826   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5640 16:44:38.166730   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5641 16:44:38.170499   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5642 16:44:38.177112   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5643 16:44:38.180527   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5644 16:44:38.183597   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5645 16:44:38.190606   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5646 16:44:38.193641   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5647 16:44:38.196898   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5648 16:44:38.203542   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5649 16:44:38.207132   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5650 16:44:38.209980   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5651 16:44:38.216687   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5652 16:44:38.219713   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5653 16:44:38.223408  Total UI for P1: 0, mck2ui 16

 5654 16:44:38.226249  best dqsien dly found for B0: ( 1,  2, 24)

 5655 16:44:38.229967   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5656 16:44:38.233033  Total UI for P1: 0, mck2ui 16

 5657 16:44:38.236374  best dqsien dly found for B1: ( 1,  2, 28)

 5658 16:44:38.239901  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5659 16:44:38.245911  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5660 16:44:38.246474  

 5661 16:44:38.249193  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5662 16:44:38.252640  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5663 16:44:38.255706  [Gating] SW calibration Done

 5664 16:44:38.256174  ==

 5665 16:44:38.259078  Dram Type= 6, Freq= 0, CH_1, rank 0

 5666 16:44:38.262568  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5667 16:44:38.263103  ==

 5668 16:44:38.266349  RX Vref Scan: 0

 5669 16:44:38.266865  

 5670 16:44:38.267234  RX Vref 0 -> 0, step: 1

 5671 16:44:38.267555  

 5672 16:44:38.269218  RX Delay -80 -> 252, step: 8

 5673 16:44:38.272153  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5674 16:44:38.278784  iDelay=208, Bit 1, Center 95 (0 ~ 191) 192

 5675 16:44:38.282805  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5676 16:44:38.285401  iDelay=208, Bit 3, Center 99 (0 ~ 199) 200

 5677 16:44:38.289239  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5678 16:44:38.291844  iDelay=208, Bit 5, Center 111 (16 ~ 207) 192

 5679 16:44:38.295447  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5680 16:44:38.301901  iDelay=208, Bit 7, Center 95 (0 ~ 191) 192

 5681 16:44:38.305387  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5682 16:44:38.308751  iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192

 5683 16:44:38.311724  iDelay=208, Bit 10, Center 95 (0 ~ 191) 192

 5684 16:44:38.314979  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5685 16:44:38.318373  iDelay=208, Bit 12, Center 103 (8 ~ 199) 192

 5686 16:44:38.325008  iDelay=208, Bit 13, Center 103 (8 ~ 199) 192

 5687 16:44:38.328331  iDelay=208, Bit 14, Center 103 (8 ~ 199) 192

 5688 16:44:38.331369  iDelay=208, Bit 15, Center 103 (8 ~ 199) 192

 5689 16:44:38.331802  ==

 5690 16:44:38.335098  Dram Type= 6, Freq= 0, CH_1, rank 0

 5691 16:44:38.338603  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5692 16:44:38.339125  ==

 5693 16:44:38.342213  DQS Delay:

 5694 16:44:38.342738  DQS0 = 0, DQS1 = 0

 5695 16:44:38.345133  DQM Delay:

 5696 16:44:38.345657  DQM0 = 100, DQM1 = 96

 5697 16:44:38.348165  DQ Delay:

 5698 16:44:38.351531  DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99

 5699 16:44:38.355367  DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95

 5700 16:44:38.358333  DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91

 5701 16:44:38.362009  DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103

 5702 16:44:38.362526  

 5703 16:44:38.362857  

 5704 16:44:38.363168  ==

 5705 16:44:38.365311  Dram Type= 6, Freq= 0, CH_1, rank 0

 5706 16:44:38.367499  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5707 16:44:38.367925  ==

 5708 16:44:38.368259  

 5709 16:44:38.368568  

 5710 16:44:38.371531  	TX Vref Scan disable

 5711 16:44:38.374464   == TX Byte 0 ==

 5712 16:44:38.377907  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5713 16:44:38.381303  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5714 16:44:38.384861   == TX Byte 1 ==

 5715 16:44:38.387591  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5716 16:44:38.391112  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5717 16:44:38.391680  ==

 5718 16:44:38.394425  Dram Type= 6, Freq= 0, CH_1, rank 0

 5719 16:44:38.397738  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5720 16:44:38.400732  ==

 5721 16:44:38.401165  

 5722 16:44:38.401499  

 5723 16:44:38.401807  	TX Vref Scan disable

 5724 16:44:38.404779   == TX Byte 0 ==

 5725 16:44:38.407737  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5726 16:44:38.414796  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5727 16:44:38.415362   == TX Byte 1 ==

 5728 16:44:38.417842  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5729 16:44:38.424318  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5730 16:44:38.424889  

 5731 16:44:38.425257  [DATLAT]

 5732 16:44:38.425603  Freq=933, CH1 RK0

 5733 16:44:38.425934  

 5734 16:44:38.427216  DATLAT Default: 0xd

 5735 16:44:38.430587  0, 0xFFFF, sum = 0

 5736 16:44:38.431062  1, 0xFFFF, sum = 0

 5737 16:44:38.434204  2, 0xFFFF, sum = 0

 5738 16:44:38.434677  3, 0xFFFF, sum = 0

 5739 16:44:38.437739  4, 0xFFFF, sum = 0

 5740 16:44:38.438213  5, 0xFFFF, sum = 0

 5741 16:44:38.440484  6, 0xFFFF, sum = 0

 5742 16:44:38.440959  7, 0xFFFF, sum = 0

 5743 16:44:38.444487  8, 0xFFFF, sum = 0

 5744 16:44:38.445057  9, 0xFFFF, sum = 0

 5745 16:44:38.447335  10, 0x0, sum = 1

 5746 16:44:38.447810  11, 0x0, sum = 2

 5747 16:44:38.450358  12, 0x0, sum = 3

 5748 16:44:38.450832  13, 0x0, sum = 4

 5749 16:44:38.453764  best_step = 11

 5750 16:44:38.454352  

 5751 16:44:38.454720  ==

 5752 16:44:38.457708  Dram Type= 6, Freq= 0, CH_1, rank 0

 5753 16:44:38.460567  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5754 16:44:38.461107  ==

 5755 16:44:38.461447  RX Vref Scan: 1

 5756 16:44:38.463483  

 5757 16:44:38.463905  RX Vref 0 -> 0, step: 1

 5758 16:44:38.464240  

 5759 16:44:38.466928  RX Delay -53 -> 252, step: 4

 5760 16:44:38.467497  

 5761 16:44:38.470307  Set Vref, RX VrefLevel [Byte0]: 53

 5762 16:44:38.473189                           [Byte1]: 51

 5763 16:44:38.476865  

 5764 16:44:38.477384  Final RX Vref Byte 0 = 53 to rank0

 5765 16:44:38.480499  Final RX Vref Byte 1 = 51 to rank0

 5766 16:44:38.483418  Final RX Vref Byte 0 = 53 to rank1

 5767 16:44:38.487278  Final RX Vref Byte 1 = 51 to rank1==

 5768 16:44:38.490632  Dram Type= 6, Freq= 0, CH_1, rank 0

 5769 16:44:38.497067  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5770 16:44:38.497636  ==

 5771 16:44:38.498011  DQS Delay:

 5772 16:44:38.499798  DQS0 = 0, DQS1 = 0

 5773 16:44:38.500265  DQM Delay:

 5774 16:44:38.500634  DQM0 = 98, DQM1 = 94

 5775 16:44:38.503718  DQ Delay:

 5776 16:44:38.506802  DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =100

 5777 16:44:38.510223  DQ4 =94, DQ5 =108, DQ6 =108, DQ7 =94

 5778 16:44:38.513519  DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =88

 5779 16:44:38.516279  DQ12 =102, DQ13 =104, DQ14 =100, DQ15 =104

 5780 16:44:38.516780  

 5781 16:44:38.517314  

 5782 16:44:38.523303  [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps

 5783 16:44:38.526867  CH1 RK0: MR19=505, MR18=717

 5784 16:44:38.533303  CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42

 5785 16:44:38.533914  

 5786 16:44:38.536086  ----->DramcWriteLeveling(PI) begin...

 5787 16:44:38.536671  ==

 5788 16:44:38.540835  Dram Type= 6, Freq= 0, CH_1, rank 1

 5789 16:44:38.542929  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5790 16:44:38.543440  ==

 5791 16:44:38.546262  Write leveling (Byte 0): 27 => 27

 5792 16:44:38.549836  Write leveling (Byte 1): 27 => 27

 5793 16:44:38.553292  DramcWriteLeveling(PI) end<-----

 5794 16:44:38.553854  

 5795 16:44:38.554220  ==

 5796 16:44:38.556577  Dram Type= 6, Freq= 0, CH_1, rank 1

 5797 16:44:38.562470  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5798 16:44:38.562945  ==

 5799 16:44:38.563363  [Gating] SW mode calibration

 5800 16:44:38.572780  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5801 16:44:38.576026  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5802 16:44:38.582610   0 14  0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 5803 16:44:38.586040   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5804 16:44:38.588969   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5805 16:44:38.595435   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5806 16:44:38.598701   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5807 16:44:38.602196   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5808 16:44:38.608816   0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)

 5809 16:44:38.611791   0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)

 5810 16:44:38.615284   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5811 16:44:38.622004   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5812 16:44:38.625393   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5813 16:44:38.628617   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5814 16:44:38.634663   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5815 16:44:38.638364   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5816 16:44:38.641279   0 15 24 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)

 5817 16:44:38.648222   0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)

 5818 16:44:38.651295   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5819 16:44:38.654797   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5820 16:44:38.661440   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5821 16:44:38.664457   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5822 16:44:38.667765   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5823 16:44:38.674713   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5824 16:44:38.677841   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5825 16:44:38.680851   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5826 16:44:38.687460   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5827 16:44:38.690929   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5828 16:44:38.694369   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5829 16:44:38.700916   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5830 16:44:38.704014   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5831 16:44:38.707304   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5832 16:44:38.714249   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5833 16:44:38.717494   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5834 16:44:38.720132   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5835 16:44:38.726608   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5836 16:44:38.730420   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5837 16:44:38.733884   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5838 16:44:38.741011   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5839 16:44:38.743858   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5840 16:44:38.746658   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5841 16:44:38.753510   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5842 16:44:38.756916  Total UI for P1: 0, mck2ui 16

 5843 16:44:38.759904  best dqsien dly found for B0: ( 1,  2, 24)

 5844 16:44:38.763265   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5845 16:44:38.766348  Total UI for P1: 0, mck2ui 16

 5846 16:44:38.770207  best dqsien dly found for B1: ( 1,  2, 26)

 5847 16:44:38.773123  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5848 16:44:38.776919  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5849 16:44:38.777485  

 5850 16:44:38.780081  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5851 16:44:38.782928  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5852 16:44:38.786524  [Gating] SW calibration Done

 5853 16:44:38.787084  ==

 5854 16:44:38.789446  Dram Type= 6, Freq= 0, CH_1, rank 1

 5855 16:44:38.795740  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5856 16:44:38.796211  ==

 5857 16:44:38.796581  RX Vref Scan: 0

 5858 16:44:38.796926  

 5859 16:44:38.799398  RX Vref 0 -> 0, step: 1

 5860 16:44:38.799863  

 5861 16:44:38.802483  RX Delay -80 -> 252, step: 8

 5862 16:44:38.805909  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5863 16:44:38.810240  iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200

 5864 16:44:38.812920  iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192

 5865 16:44:38.815953  iDelay=208, Bit 3, Center 95 (0 ~ 191) 192

 5866 16:44:38.822623  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5867 16:44:38.825508  iDelay=208, Bit 5, Center 107 (8 ~ 207) 200

 5868 16:44:38.829237  iDelay=208, Bit 6, Center 103 (8 ~ 199) 192

 5869 16:44:38.832868  iDelay=208, Bit 7, Center 95 (0 ~ 191) 192

 5870 16:44:38.835516  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5871 16:44:38.838570  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5872 16:44:38.845638  iDelay=208, Bit 10, Center 95 (0 ~ 191) 192

 5873 16:44:38.849281  iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192

 5874 16:44:38.851697  iDelay=208, Bit 12, Center 103 (8 ~ 199) 192

 5875 16:44:38.855123  iDelay=208, Bit 13, Center 103 (8 ~ 199) 192

 5876 16:44:38.858446  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5877 16:44:38.865505  iDelay=208, Bit 15, Center 103 (8 ~ 199) 192

 5878 16:44:38.866075  ==

 5879 16:44:38.868162  Dram Type= 6, Freq= 0, CH_1, rank 1

 5880 16:44:38.871542  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5881 16:44:38.872072  ==

 5882 16:44:38.872464  DQS Delay:

 5883 16:44:38.874878  DQS0 = 0, DQS1 = 0

 5884 16:44:38.875505  DQM Delay:

 5885 16:44:38.878487  DQM0 = 97, DQM1 = 94

 5886 16:44:38.879051  DQ Delay:

 5887 16:44:38.881527  DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95

 5888 16:44:38.884916  DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95

 5889 16:44:38.887998  DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87

 5890 16:44:38.891695  DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103

 5891 16:44:38.892261  

 5892 16:44:38.892634  

 5893 16:44:38.892976  ==

 5894 16:44:38.894413  Dram Type= 6, Freq= 0, CH_1, rank 1

 5895 16:44:38.901883  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5896 16:44:38.902471  ==

 5897 16:44:38.902873  

 5898 16:44:38.903265  

 5899 16:44:38.903610  	TX Vref Scan disable

 5900 16:44:38.904579   == TX Byte 0 ==

 5901 16:44:38.908148  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5902 16:44:38.915134  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5903 16:44:38.915742   == TX Byte 1 ==

 5904 16:44:38.918165  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5905 16:44:38.925001  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5906 16:44:38.925590  ==

 5907 16:44:38.927751  Dram Type= 6, Freq= 0, CH_1, rank 1

 5908 16:44:38.930801  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5909 16:44:38.931338  ==

 5910 16:44:38.931914  

 5911 16:44:38.932281  

 5912 16:44:38.934183  	TX Vref Scan disable

 5913 16:44:38.937462   == TX Byte 0 ==

 5914 16:44:38.941702  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5915 16:44:38.943932  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5916 16:44:38.948179   == TX Byte 1 ==

 5917 16:44:38.950619  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5918 16:44:38.954234  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5919 16:44:38.954801  

 5920 16:44:38.955207  [DATLAT]

 5921 16:44:38.957998  Freq=933, CH1 RK1

 5922 16:44:38.958561  

 5923 16:44:38.960935  DATLAT Default: 0xb

 5924 16:44:38.961402  0, 0xFFFF, sum = 0

 5925 16:44:38.964083  1, 0xFFFF, sum = 0

 5926 16:44:38.964609  2, 0xFFFF, sum = 0

 5927 16:44:38.967269  3, 0xFFFF, sum = 0

 5928 16:44:38.967743  4, 0xFFFF, sum = 0

 5929 16:44:38.971110  5, 0xFFFF, sum = 0

 5930 16:44:38.971714  6, 0xFFFF, sum = 0

 5931 16:44:38.974807  7, 0xFFFF, sum = 0

 5932 16:44:38.975448  8, 0xFFFF, sum = 0

 5933 16:44:38.977432  9, 0xFFFF, sum = 0

 5934 16:44:38.978000  10, 0x0, sum = 1

 5935 16:44:38.980471  11, 0x0, sum = 2

 5936 16:44:38.980946  12, 0x0, sum = 3

 5937 16:44:38.983868  13, 0x0, sum = 4

 5938 16:44:38.984344  best_step = 11

 5939 16:44:38.984709  

 5940 16:44:38.985045  ==

 5941 16:44:38.986726  Dram Type= 6, Freq= 0, CH_1, rank 1

 5942 16:44:38.990334  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5943 16:44:38.993425  ==

 5944 16:44:38.993890  RX Vref Scan: 0

 5945 16:44:38.994255  

 5946 16:44:38.997367  RX Vref 0 -> 0, step: 1

 5947 16:44:38.997941  

 5948 16:44:39.000123  RX Delay -53 -> 252, step: 4

 5949 16:44:39.003905  iDelay=203, Bit 0, Center 102 (11 ~ 194) 184

 5950 16:44:39.007115  iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192

 5951 16:44:39.013324  iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188

 5952 16:44:39.016966  iDelay=203, Bit 3, Center 96 (3 ~ 190) 188

 5953 16:44:39.019706  iDelay=203, Bit 4, Center 98 (3 ~ 194) 192

 5954 16:44:39.023717  iDelay=203, Bit 5, Center 108 (15 ~ 202) 188

 5955 16:44:39.026922  iDelay=203, Bit 6, Center 106 (15 ~ 198) 184

 5956 16:44:39.029970  iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188

 5957 16:44:39.036575  iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180

 5958 16:44:39.039638  iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184

 5959 16:44:39.043053  iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188

 5960 16:44:39.046285  iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184

 5961 16:44:39.049534  iDelay=203, Bit 12, Center 100 (11 ~ 190) 180

 5962 16:44:39.056723  iDelay=203, Bit 13, Center 102 (11 ~ 194) 184

 5963 16:44:39.059294  iDelay=203, Bit 14, Center 96 (7 ~ 186) 180

 5964 16:44:39.062832  iDelay=203, Bit 15, Center 100 (7 ~ 194) 188

 5965 16:44:39.063436  ==

 5966 16:44:39.065993  Dram Type= 6, Freq= 0, CH_1, rank 1

 5967 16:44:39.069482  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5968 16:44:39.069957  ==

 5969 16:44:39.073188  DQS Delay:

 5970 16:44:39.073653  DQS0 = 0, DQS1 = 0

 5971 16:44:39.075955  DQM Delay:

 5972 16:44:39.076517  DQM0 = 98, DQM1 = 92

 5973 16:44:39.079316  DQ Delay:

 5974 16:44:39.079879  DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =96

 5975 16:44:39.082278  DQ4 =98, DQ5 =108, DQ6 =106, DQ7 =92

 5976 16:44:39.086404  DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86

 5977 16:44:39.092330  DQ12 =100, DQ13 =102, DQ14 =96, DQ15 =100

 5978 16:44:39.092894  

 5979 16:44:39.093265  

 5980 16:44:39.098867  [DQSOSCAuto] RK1, (LSB)MR18= 0xa20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps

 5981 16:44:39.102846  CH1 RK1: MR19=505, MR18=A20

 5982 16:44:39.109150  CH1_RK1: MR19=0x505, MR18=0xA20, DQSOSC=411, MR23=63, INC=64, DEC=42

 5983 16:44:39.112019  [RxdqsGatingPostProcess] freq 933

 5984 16:44:39.115499  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5985 16:44:39.118917  best DQS0 dly(2T, 0.5T) = (0, 10)

 5986 16:44:39.122285  best DQS1 dly(2T, 0.5T) = (0, 10)

 5987 16:44:39.125771  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5988 16:44:39.128816  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5989 16:44:39.132869  best DQS0 dly(2T, 0.5T) = (0, 10)

 5990 16:44:39.135266  best DQS1 dly(2T, 0.5T) = (0, 10)

 5991 16:44:39.138351  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5992 16:44:39.141698  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5993 16:44:39.145142  Pre-setting of DQS Precalculation

 5994 16:44:39.149047  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5995 16:44:39.158570  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5996 16:44:39.165296  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5997 16:44:39.165861  

 5998 16:44:39.166259  

 5999 16:44:39.167810  [Calibration Summary] 1866 Mbps

 6000 16:44:39.168278  CH 0, Rank 0

 6001 16:44:39.171680  SW Impedance     : PASS

 6002 16:44:39.172147  DUTY Scan        : NO K

 6003 16:44:39.174732  ZQ Calibration   : PASS

 6004 16:44:39.178537  Jitter Meter     : NO K

 6005 16:44:39.179102  CBT Training     : PASS

 6006 16:44:39.180989  Write leveling   : PASS

 6007 16:44:39.184199  RX DQS gating    : PASS

 6008 16:44:39.184669  RX DQ/DQS(RDDQC) : PASS

 6009 16:44:39.187452  TX DQ/DQS        : PASS

 6010 16:44:39.191308  RX DATLAT        : PASS

 6011 16:44:39.191873  RX DQ/DQS(Engine): PASS

 6012 16:44:39.194919  TX OE            : NO K

 6013 16:44:39.195514  All Pass.

 6014 16:44:39.195950  

 6015 16:44:39.197530  CH 0, Rank 1

 6016 16:44:39.197995  SW Impedance     : PASS

 6017 16:44:39.200699  DUTY Scan        : NO K

 6018 16:44:39.204345  ZQ Calibration   : PASS

 6019 16:44:39.204813  Jitter Meter     : NO K

 6020 16:44:39.207255  CBT Training     : PASS

 6021 16:44:39.210903  Write leveling   : PASS

 6022 16:44:39.211473  RX DQS gating    : PASS

 6023 16:44:39.213788  RX DQ/DQS(RDDQC) : PASS

 6024 16:44:39.218852  TX DQ/DQS        : PASS

 6025 16:44:39.219409  RX DATLAT        : PASS

 6026 16:44:39.221270  RX DQ/DQS(Engine): PASS

 6027 16:44:39.224114  TX OE            : NO K

 6028 16:44:39.224545  All Pass.

 6029 16:44:39.224883  

 6030 16:44:39.225196  CH 1, Rank 0

 6031 16:44:39.226884  SW Impedance     : PASS

 6032 16:44:39.230595  DUTY Scan        : NO K

 6033 16:44:39.231014  ZQ Calibration   : PASS

 6034 16:44:39.233721  Jitter Meter     : NO K

 6035 16:44:39.237107  CBT Training     : PASS

 6036 16:44:39.237589  Write leveling   : PASS

 6037 16:44:39.239951  RX DQS gating    : PASS

 6038 16:44:39.240374  RX DQ/DQS(RDDQC) : PASS

 6039 16:44:39.243572  TX DQ/DQS        : PASS

 6040 16:44:39.246991  RX DATLAT        : PASS

 6041 16:44:39.247558  RX DQ/DQS(Engine): PASS

 6042 16:44:39.250280  TX OE            : NO K

 6043 16:44:39.250710  All Pass.

 6044 16:44:39.251049  

 6045 16:44:39.254775  CH 1, Rank 1

 6046 16:44:39.255357  SW Impedance     : PASS

 6047 16:44:39.256610  DUTY Scan        : NO K

 6048 16:44:39.259921  ZQ Calibration   : PASS

 6049 16:44:39.260495  Jitter Meter     : NO K

 6050 16:44:39.263570  CBT Training     : PASS

 6051 16:44:39.267014  Write leveling   : PASS

 6052 16:44:39.267669  RX DQS gating    : PASS

 6053 16:44:39.270233  RX DQ/DQS(RDDQC) : PASS

 6054 16:44:39.272829  TX DQ/DQS        : PASS

 6055 16:44:39.273303  RX DATLAT        : PASS

 6056 16:44:39.276137  RX DQ/DQS(Engine): PASS

 6057 16:44:39.279405  TX OE            : NO K

 6058 16:44:39.279882  All Pass.

 6059 16:44:39.280252  

 6060 16:44:39.283627  DramC Write-DBI off

 6061 16:44:39.284056  	PER_BANK_REFRESH: Hybrid Mode

 6062 16:44:39.286186  TX_TRACKING: ON

 6063 16:44:39.296089  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6064 16:44:39.299507  [FAST_K] Save calibration result to emmc

 6065 16:44:39.302920  dramc_set_vcore_voltage set vcore to 650000

 6066 16:44:39.303377  Read voltage for 400, 6

 6067 16:44:39.305884  Vio18 = 0

 6068 16:44:39.306310  Vcore = 650000

 6069 16:44:39.306645  Vdram = 0

 6070 16:44:39.309237  Vddq = 0

 6071 16:44:39.309765  Vmddr = 0

 6072 16:44:39.316273  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6073 16:44:39.319131  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6074 16:44:39.322675  MEM_TYPE=3, freq_sel=20

 6075 16:44:39.325770  sv_algorithm_assistance_LP4_800 

 6076 16:44:39.328781  ============ PULL DRAM RESETB DOWN ============

 6077 16:44:39.332305  ========== PULL DRAM RESETB DOWN end =========

 6078 16:44:39.339321  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6079 16:44:39.342749  =================================== 

 6080 16:44:39.343056  LPDDR4 DRAM CONFIGURATION

 6081 16:44:39.345398  =================================== 

 6082 16:44:39.348569  EX_ROW_EN[0]    = 0x0

 6083 16:44:39.351583  EX_ROW_EN[1]    = 0x0

 6084 16:44:39.351814  LP4Y_EN      = 0x0

 6085 16:44:39.355076  WORK_FSP     = 0x0

 6086 16:44:39.355288  WL           = 0x2

 6087 16:44:39.358359  RL           = 0x2

 6088 16:44:39.358513  BL           = 0x2

 6089 16:44:39.361541  RPST         = 0x0

 6090 16:44:39.361695  RD_PRE       = 0x0

 6091 16:44:39.365772  WR_PRE       = 0x1

 6092 16:44:39.365906  WR_PST       = 0x0

 6093 16:44:39.368432  DBI_WR       = 0x0

 6094 16:44:39.368549  DBI_RD       = 0x0

 6095 16:44:39.371898  OTF          = 0x1

 6096 16:44:39.375013  =================================== 

 6097 16:44:39.377825  =================================== 

 6098 16:44:39.377919  ANA top config

 6099 16:44:39.381029  =================================== 

 6100 16:44:39.384369  DLL_ASYNC_EN            =  0

 6101 16:44:39.387764  ALL_SLAVE_EN            =  1

 6102 16:44:39.391366  NEW_RANK_MODE           =  1

 6103 16:44:39.391451  DLL_IDLE_MODE           =  1

 6104 16:44:39.394351  LP45_APHY_COMB_EN       =  1

 6105 16:44:39.398304  TX_ODT_DIS              =  1

 6106 16:44:39.400759  NEW_8X_MODE             =  1

 6107 16:44:39.404126  =================================== 

 6108 16:44:39.407366  =================================== 

 6109 16:44:39.410906  data_rate                  =  800

 6110 16:44:39.414240  CKR                        = 1

 6111 16:44:39.414323  DQ_P2S_RATIO               = 4

 6112 16:44:39.417246  =================================== 

 6113 16:44:39.420585  CA_P2S_RATIO               = 4

 6114 16:44:39.423656  DQ_CA_OPEN                 = 0

 6115 16:44:39.427088  DQ_SEMI_OPEN               = 1

 6116 16:44:39.431099  CA_SEMI_OPEN               = 1

 6117 16:44:39.433699  CA_FULL_RATE               = 0

 6118 16:44:39.433782  DQ_CKDIV4_EN               = 0

 6119 16:44:39.436968  CA_CKDIV4_EN               = 1

 6120 16:44:39.440143  CA_PREDIV_EN               = 0

 6121 16:44:39.443813  PH8_DLY                    = 0

 6122 16:44:39.447359  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6123 16:44:39.450446  DQ_AAMCK_DIV               = 0

 6124 16:44:39.450529  CA_AAMCK_DIV               = 0

 6125 16:44:39.453318  CA_ADMCK_DIV               = 4

 6126 16:44:39.456736  DQ_TRACK_CA_EN             = 0

 6127 16:44:39.460040  CA_PICK                    = 800

 6128 16:44:39.463149  CA_MCKIO                   = 400

 6129 16:44:39.466786  MCKIO_SEMI                 = 400

 6130 16:44:39.469795  PLL_FREQ                   = 3016

 6131 16:44:39.473424  DQ_UI_PI_RATIO             = 32

 6132 16:44:39.473507  CA_UI_PI_RATIO             = 32

 6133 16:44:39.476629  =================================== 

 6134 16:44:39.479934  =================================== 

 6135 16:44:39.483565  memory_type:LPDDR4         

 6136 16:44:39.486577  GP_NUM     : 10       

 6137 16:44:39.486657  SRAM_EN    : 1       

 6138 16:44:39.490155  MD32_EN    : 0       

 6139 16:44:39.493275  =================================== 

 6140 16:44:39.496721  [ANA_INIT] >>>>>>>>>>>>>> 

 6141 16:44:39.499523  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6142 16:44:39.503119  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6143 16:44:39.505931  =================================== 

 6144 16:44:39.506012  data_rate = 800,PCW = 0X7400

 6145 16:44:39.509679  =================================== 

 6146 16:44:39.515971  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6147 16:44:39.519332  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6148 16:44:39.532374  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6149 16:44:39.536242  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6150 16:44:39.539532  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6151 16:44:39.542303  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6152 16:44:39.545693  [ANA_INIT] flow start 

 6153 16:44:39.545776  [ANA_INIT] PLL >>>>>>>> 

 6154 16:44:39.548918  [ANA_INIT] PLL <<<<<<<< 

 6155 16:44:39.551856  [ANA_INIT] MIDPI >>>>>>>> 

 6156 16:44:39.555560  [ANA_INIT] MIDPI <<<<<<<< 

 6157 16:44:39.555644  [ANA_INIT] DLL >>>>>>>> 

 6158 16:44:39.558785  [ANA_INIT] flow end 

 6159 16:44:39.562566  ============ LP4 DIFF to SE enter ============

 6160 16:44:39.565582  ============ LP4 DIFF to SE exit  ============

 6161 16:44:39.568928  [ANA_INIT] <<<<<<<<<<<<< 

 6162 16:44:39.572238  [Flow] Enable top DCM control >>>>> 

 6163 16:44:39.575079  [Flow] Enable top DCM control <<<<< 

 6164 16:44:39.578884  Enable DLL master slave shuffle 

 6165 16:44:39.584791  ============================================================== 

 6166 16:44:39.584925  Gating Mode config

 6167 16:44:39.592105  ============================================================== 

 6168 16:44:39.595223  Config description: 

 6169 16:44:39.601751  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6170 16:44:39.608333  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6171 16:44:39.615161  SELPH_MODE            0: By rank         1: By Phase 

 6172 16:44:39.621588  ============================================================== 

 6173 16:44:39.621828  GAT_TRACK_EN                 =  0

 6174 16:44:39.624594  RX_GATING_MODE               =  2

 6175 16:44:39.628392  RX_GATING_TRACK_MODE         =  2

 6176 16:44:39.631640  SELPH_MODE                   =  1

 6177 16:44:39.634849  PICG_EARLY_EN                =  1

 6178 16:44:39.638243  VALID_LAT_VALUE              =  1

 6179 16:44:39.644463  ============================================================== 

 6180 16:44:39.647750  Enter into Gating configuration >>>> 

 6181 16:44:39.651285  Exit from Gating configuration <<<< 

 6182 16:44:39.654767  Enter into  DVFS_PRE_config >>>>> 

 6183 16:44:39.665000  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6184 16:44:39.667946  Exit from  DVFS_PRE_config <<<<< 

 6185 16:44:39.671243  Enter into PICG configuration >>>> 

 6186 16:44:39.674372  Exit from PICG configuration <<<< 

 6187 16:44:39.677229  [RX_INPUT] configuration >>>>> 

 6188 16:44:39.680847  [RX_INPUT] configuration <<<<< 

 6189 16:44:39.684165  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6190 16:44:39.691165  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6191 16:44:39.697650  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6192 16:44:39.704016  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6193 16:44:39.710040  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6194 16:44:39.713458  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6195 16:44:39.720216  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6196 16:44:39.723654  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6197 16:44:39.726765  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6198 16:44:39.729866  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6199 16:44:39.736733  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6200 16:44:39.739881  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6201 16:44:39.743444  =================================== 

 6202 16:44:39.746621  LPDDR4 DRAM CONFIGURATION

 6203 16:44:39.749805  =================================== 

 6204 16:44:39.750230  EX_ROW_EN[0]    = 0x0

 6205 16:44:39.752813  EX_ROW_EN[1]    = 0x0

 6206 16:44:39.753118  LP4Y_EN      = 0x0

 6207 16:44:39.756184  WORK_FSP     = 0x0

 6208 16:44:39.756489  WL           = 0x2

 6209 16:44:39.759280  RL           = 0x2

 6210 16:44:39.759518  BL           = 0x2

 6211 16:44:39.762562  RPST         = 0x0

 6212 16:44:39.766313  RD_PRE       = 0x0

 6213 16:44:39.766504  WR_PRE       = 0x1

 6214 16:44:39.769803  WR_PST       = 0x0

 6215 16:44:39.769965  DBI_WR       = 0x0

 6216 16:44:39.772683  DBI_RD       = 0x0

 6217 16:44:39.772835  OTF          = 0x1

 6218 16:44:39.776008  =================================== 

 6219 16:44:39.779084  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6220 16:44:39.785970  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6221 16:44:39.789417  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6222 16:44:39.792443  =================================== 

 6223 16:44:39.795579  LPDDR4 DRAM CONFIGURATION

 6224 16:44:39.799472  =================================== 

 6225 16:44:39.799643  EX_ROW_EN[0]    = 0x10

 6226 16:44:39.802386  EX_ROW_EN[1]    = 0x0

 6227 16:44:39.802527  LP4Y_EN      = 0x0

 6228 16:44:39.805710  WORK_FSP     = 0x0

 6229 16:44:39.805879  WL           = 0x2

 6230 16:44:39.808763  RL           = 0x2

 6231 16:44:39.812089  BL           = 0x2

 6232 16:44:39.812260  RPST         = 0x0

 6233 16:44:39.815347  RD_PRE       = 0x0

 6234 16:44:39.815518  WR_PRE       = 0x1

 6235 16:44:39.818691  WR_PST       = 0x0

 6236 16:44:39.818868  DBI_WR       = 0x0

 6237 16:44:39.822773  DBI_RD       = 0x0

 6238 16:44:39.822961  OTF          = 0x1

 6239 16:44:39.825097  =================================== 

 6240 16:44:39.832618  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6241 16:44:39.836068  nWR fixed to 30

 6242 16:44:39.839532  [ModeRegInit_LP4] CH0 RK0

 6243 16:44:39.839755  [ModeRegInit_LP4] CH0 RK1

 6244 16:44:39.842413  [ModeRegInit_LP4] CH1 RK0

 6245 16:44:39.845782  [ModeRegInit_LP4] CH1 RK1

 6246 16:44:39.846033  match AC timing 19

 6247 16:44:39.852028  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6248 16:44:39.855861  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6249 16:44:39.859119  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6250 16:44:39.865748  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6251 16:44:39.869412  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6252 16:44:39.869975  ==

 6253 16:44:39.872617  Dram Type= 6, Freq= 0, CH_0, rank 0

 6254 16:44:39.875847  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6255 16:44:39.876414  ==

 6256 16:44:39.882334  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6257 16:44:39.889157  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6258 16:44:39.892096  [CA 0] Center 36 (8~64) winsize 57

 6259 16:44:39.895515  [CA 1] Center 36 (8~64) winsize 57

 6260 16:44:39.898856  [CA 2] Center 36 (8~64) winsize 57

 6261 16:44:39.902430  [CA 3] Center 36 (8~64) winsize 57

 6262 16:44:39.905444  [CA 4] Center 36 (8~64) winsize 57

 6263 16:44:39.908389  [CA 5] Center 36 (8~64) winsize 57

 6264 16:44:39.908865  

 6265 16:44:39.912123  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6266 16:44:39.912691  

 6267 16:44:39.915479  [CATrainingPosCal] consider 1 rank data

 6268 16:44:39.918852  u2DelayCellTimex100 = 270/100 ps

 6269 16:44:39.921765  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6270 16:44:39.925023  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6271 16:44:39.928765  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6272 16:44:39.931586  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6273 16:44:39.934915  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6274 16:44:39.938665  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6275 16:44:39.939279  

 6276 16:44:39.944846  CA PerBit enable=1, Macro0, CA PI delay=36

 6277 16:44:39.945414  

 6278 16:44:39.945792  [CBTSetCACLKResult] CA Dly = 36

 6279 16:44:39.948746  CS Dly: 1 (0~32)

 6280 16:44:39.949275  ==

 6281 16:44:39.952348  Dram Type= 6, Freq= 0, CH_0, rank 1

 6282 16:44:39.954733  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6283 16:44:39.955259  ==

 6284 16:44:39.961362  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6285 16:44:39.967997  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6286 16:44:39.971684  [CA 0] Center 36 (8~64) winsize 57

 6287 16:44:39.974815  [CA 1] Center 36 (8~64) winsize 57

 6288 16:44:39.978246  [CA 2] Center 36 (8~64) winsize 57

 6289 16:44:39.981186  [CA 3] Center 36 (8~64) winsize 57

 6290 16:44:39.984670  [CA 4] Center 36 (8~64) winsize 57

 6291 16:44:39.985232  [CA 5] Center 36 (8~64) winsize 57

 6292 16:44:39.985607  

 6293 16:44:39.991039  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6294 16:44:39.991670  

 6295 16:44:39.994589  [CATrainingPosCal] consider 2 rank data

 6296 16:44:39.998455  u2DelayCellTimex100 = 270/100 ps

 6297 16:44:40.000980  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6298 16:44:40.004249  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6299 16:44:40.007223  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6300 16:44:40.010947  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6301 16:44:40.013957  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6302 16:44:40.017605  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6303 16:44:40.018167  

 6304 16:44:40.020880  CA PerBit enable=1, Macro0, CA PI delay=36

 6305 16:44:40.021443  

 6306 16:44:40.024137  [CBTSetCACLKResult] CA Dly = 36

 6307 16:44:40.027634  CS Dly: 1 (0~32)

 6308 16:44:40.028204  

 6309 16:44:40.030691  ----->DramcWriteLeveling(PI) begin...

 6310 16:44:40.031307  ==

 6311 16:44:40.033636  Dram Type= 6, Freq= 0, CH_0, rank 0

 6312 16:44:40.037604  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6313 16:44:40.038173  ==

 6314 16:44:40.041803  Write leveling (Byte 0): 40 => 8

 6315 16:44:40.043814  Write leveling (Byte 1): 40 => 8

 6316 16:44:40.047296  DramcWriteLeveling(PI) end<-----

 6317 16:44:40.047869  

 6318 16:44:40.048243  ==

 6319 16:44:40.050049  Dram Type= 6, Freq= 0, CH_0, rank 0

 6320 16:44:40.053937  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6321 16:44:40.054523  ==

 6322 16:44:40.057012  [Gating] SW mode calibration

 6323 16:44:40.063780  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6324 16:44:40.069961  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6325 16:44:40.073236   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6326 16:44:40.079890   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6327 16:44:40.083559   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6328 16:44:40.086748   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6329 16:44:40.093670   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6330 16:44:40.096562   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6331 16:44:40.099910   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6332 16:44:40.106535   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6333 16:44:40.110011   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6334 16:44:40.113250  Total UI for P1: 0, mck2ui 16

 6335 16:44:40.116380  best dqsien dly found for B0: ( 0, 14, 24)

 6336 16:44:40.119639  Total UI for P1: 0, mck2ui 16

 6337 16:44:40.123350  best dqsien dly found for B1: ( 0, 14, 24)

 6338 16:44:40.126312  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6339 16:44:40.129407  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6340 16:44:40.129983  

 6341 16:44:40.132732  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6342 16:44:40.135985  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6343 16:44:40.139873  [Gating] SW calibration Done

 6344 16:44:40.140438  ==

 6345 16:44:40.142754  Dram Type= 6, Freq= 0, CH_0, rank 0

 6346 16:44:40.148825  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6347 16:44:40.149376  ==

 6348 16:44:40.149746  RX Vref Scan: 0

 6349 16:44:40.150088  

 6350 16:44:40.152414  RX Vref 0 -> 0, step: 1

 6351 16:44:40.152922  

 6352 16:44:40.155447  RX Delay -410 -> 252, step: 16

 6353 16:44:40.159093  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6354 16:44:40.162135  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6355 16:44:40.168484  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6356 16:44:40.171796  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6357 16:44:40.175361  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6358 16:44:40.179056  iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496

 6359 16:44:40.184971  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6360 16:44:40.188464  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6361 16:44:40.191687  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6362 16:44:40.195015  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6363 16:44:40.201527  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6364 16:44:40.204588  iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512

 6365 16:44:40.208602  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6366 16:44:40.214907  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6367 16:44:40.218136  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6368 16:44:40.221362  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6369 16:44:40.221882  ==

 6370 16:44:40.224762  Dram Type= 6, Freq= 0, CH_0, rank 0

 6371 16:44:40.231140  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6372 16:44:40.231711  ==

 6373 16:44:40.232040  DQS Delay:

 6374 16:44:40.234309  DQS0 = 35, DQS1 = 59

 6375 16:44:40.234769  DQM Delay:

 6376 16:44:40.235125  DQM0 = 4, DQM1 = 17

 6377 16:44:40.237936  DQ Delay:

 6378 16:44:40.238503  DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0

 6379 16:44:40.240845  DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16

 6380 16:44:40.244432  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16

 6381 16:44:40.247282  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6382 16:44:40.247697  

 6383 16:44:40.248018  

 6384 16:44:40.251010  ==

 6385 16:44:40.253837  Dram Type= 6, Freq= 0, CH_0, rank 0

 6386 16:44:40.257398  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6387 16:44:40.257922  ==

 6388 16:44:40.258254  

 6389 16:44:40.258557  

 6390 16:44:40.260909  	TX Vref Scan disable

 6391 16:44:40.261428   == TX Byte 0 ==

 6392 16:44:40.263721  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6393 16:44:40.270663  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6394 16:44:40.271222   == TX Byte 1 ==

 6395 16:44:40.273563  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6396 16:44:40.280199  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6397 16:44:40.280710  ==

 6398 16:44:40.283714  Dram Type= 6, Freq= 0, CH_0, rank 0

 6399 16:44:40.287165  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6400 16:44:40.287778  ==

 6401 16:44:40.288142  

 6402 16:44:40.288475  

 6403 16:44:40.290395  	TX Vref Scan disable

 6404 16:44:40.290846   == TX Byte 0 ==

 6405 16:44:40.297000  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6406 16:44:40.300188  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6407 16:44:40.300752   == TX Byte 1 ==

 6408 16:44:40.306680  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6409 16:44:40.310054  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6410 16:44:40.310646  

 6411 16:44:40.311015  [DATLAT]

 6412 16:44:40.313607  Freq=400, CH0 RK0

 6413 16:44:40.314074  

 6414 16:44:40.314434  DATLAT Default: 0xf

 6415 16:44:40.317050  0, 0xFFFF, sum = 0

 6416 16:44:40.317634  1, 0xFFFF, sum = 0

 6417 16:44:40.319502  2, 0xFFFF, sum = 0

 6418 16:44:40.319969  3, 0xFFFF, sum = 0

 6419 16:44:40.323319  4, 0xFFFF, sum = 0

 6420 16:44:40.323883  5, 0xFFFF, sum = 0

 6421 16:44:40.326105  6, 0xFFFF, sum = 0

 6422 16:44:40.326574  7, 0xFFFF, sum = 0

 6423 16:44:40.330007  8, 0xFFFF, sum = 0

 6424 16:44:40.330575  9, 0xFFFF, sum = 0

 6425 16:44:40.332749  10, 0xFFFF, sum = 0

 6426 16:44:40.336106  11, 0xFFFF, sum = 0

 6427 16:44:40.336578  12, 0xFFFF, sum = 0

 6428 16:44:40.339558  13, 0x0, sum = 1

 6429 16:44:40.340213  14, 0x0, sum = 2

 6430 16:44:40.343452  15, 0x0, sum = 3

 6431 16:44:40.343967  16, 0x0, sum = 4

 6432 16:44:40.344500  best_step = 14

 6433 16:44:40.344932  

 6434 16:44:40.346284  ==

 6435 16:44:40.349060  Dram Type= 6, Freq= 0, CH_0, rank 0

 6436 16:44:40.352458  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6437 16:44:40.352945  ==

 6438 16:44:40.353469  RX Vref Scan: 1

 6439 16:44:40.353894  

 6440 16:44:40.355794  RX Vref 0 -> 0, step: 1

 6441 16:44:40.356253  

 6442 16:44:40.359912  RX Delay -359 -> 252, step: 8

 6443 16:44:40.360353  

 6444 16:44:40.363258  Set Vref, RX VrefLevel [Byte0]: 56

 6445 16:44:40.366034                           [Byte1]: 59

 6446 16:44:40.370245  

 6447 16:44:40.370766  Final RX Vref Byte 0 = 56 to rank0

 6448 16:44:40.372775  Final RX Vref Byte 1 = 59 to rank0

 6449 16:44:40.376396  Final RX Vref Byte 0 = 56 to rank1

 6450 16:44:40.379751  Final RX Vref Byte 1 = 59 to rank1==

 6451 16:44:40.383929  Dram Type= 6, Freq= 0, CH_0, rank 0

 6452 16:44:40.389633  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6453 16:44:40.390170  ==

 6454 16:44:40.390508  DQS Delay:

 6455 16:44:40.393005  DQS0 = 44, DQS1 = 60

 6456 16:44:40.393527  DQM Delay:

 6457 16:44:40.393856  DQM0 = 11, DQM1 = 16

 6458 16:44:40.395877  DQ Delay:

 6459 16:44:40.399479  DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4

 6460 16:44:40.402897  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20

 6461 16:44:40.406256  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12

 6462 16:44:40.409086  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6463 16:44:40.409612  

 6464 16:44:40.409944  

 6465 16:44:40.415880  [DQSOSCAuto] RK0, (LSB)MR18= 0x8c80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps

 6466 16:44:40.418767  CH0 RK0: MR19=C0C, MR18=8C80

 6467 16:44:40.425580  CH0_RK0: MR19=0xC0C, MR18=0x8C80, DQSOSC=392, MR23=63, INC=384, DEC=256

 6468 16:44:40.426124  ==

 6469 16:44:40.428911  Dram Type= 6, Freq= 0, CH_0, rank 1

 6470 16:44:40.432566  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6471 16:44:40.433090  ==

 6472 16:44:40.435239  [Gating] SW mode calibration

 6473 16:44:40.441904  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6474 16:44:40.448451  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6475 16:44:40.451751   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6476 16:44:40.455147   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6477 16:44:40.462004   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6478 16:44:40.465096   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6479 16:44:40.472365   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6480 16:44:40.474850   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6481 16:44:40.478310   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6482 16:44:40.484545   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6483 16:44:40.488052   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6484 16:44:40.491258  Total UI for P1: 0, mck2ui 16

 6485 16:44:40.494411  best dqsien dly found for B0: ( 0, 14, 24)

 6486 16:44:40.498329  Total UI for P1: 0, mck2ui 16

 6487 16:44:40.501244  best dqsien dly found for B1: ( 0, 14, 24)

 6488 16:44:40.504234  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6489 16:44:40.508093  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6490 16:44:40.508661  

 6491 16:44:40.510661  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6492 16:44:40.513926  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6493 16:44:40.517471  [Gating] SW calibration Done

 6494 16:44:40.518034  ==

 6495 16:44:40.520717  Dram Type= 6, Freq= 0, CH_0, rank 1

 6496 16:44:40.527702  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6497 16:44:40.528271  ==

 6498 16:44:40.528642  RX Vref Scan: 0

 6499 16:44:40.528986  

 6500 16:44:40.530311  RX Vref 0 -> 0, step: 1

 6501 16:44:40.530773  

 6502 16:44:40.533849  RX Delay -410 -> 252, step: 16

 6503 16:44:40.537011  iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480

 6504 16:44:40.540187  iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480

 6505 16:44:40.547254  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6506 16:44:40.550187  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6507 16:44:40.553483  iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480

 6508 16:44:40.556818  iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496

 6509 16:44:40.563323  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6510 16:44:40.567160  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6511 16:44:40.569776  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6512 16:44:40.573950  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6513 16:44:40.579854  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6514 16:44:40.583452  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6515 16:44:40.586993  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6516 16:44:40.589743  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6517 16:44:40.596242  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6518 16:44:40.599278  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6519 16:44:40.599747  ==

 6520 16:44:40.603013  Dram Type= 6, Freq= 0, CH_0, rank 1

 6521 16:44:40.606153  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6522 16:44:40.609457  ==

 6523 16:44:40.609917  DQS Delay:

 6524 16:44:40.610281  DQS0 = 35, DQS1 = 59

 6525 16:44:40.612830  DQM Delay:

 6526 16:44:40.613394  DQM0 = 7, DQM1 = 16

 6527 16:44:40.616105  DQ Delay:

 6528 16:44:40.616669  DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0

 6529 16:44:40.619288  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6530 16:44:40.622871  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6531 16:44:40.625632  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6532 16:44:40.626098  

 6533 16:44:40.626462  

 6534 16:44:40.626798  ==

 6535 16:44:40.629146  Dram Type= 6, Freq= 0, CH_0, rank 1

 6536 16:44:40.635613  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6537 16:44:40.636195  ==

 6538 16:44:40.636569  

 6539 16:44:40.636903  

 6540 16:44:40.638961  	TX Vref Scan disable

 6541 16:44:40.639554   == TX Byte 0 ==

 6542 16:44:40.642310  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6543 16:44:40.648926  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6544 16:44:40.649477   == TX Byte 1 ==

 6545 16:44:40.652000  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6546 16:44:40.658611  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6547 16:44:40.659371  ==

 6548 16:44:40.662045  Dram Type= 6, Freq= 0, CH_0, rank 1

 6549 16:44:40.665314  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6550 16:44:40.665886  ==

 6551 16:44:40.666260  

 6552 16:44:40.666605  

 6553 16:44:40.668238  	TX Vref Scan disable

 6554 16:44:40.668702   == TX Byte 0 ==

 6555 16:44:40.671993  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6556 16:44:40.678361  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6557 16:44:40.678930   == TX Byte 1 ==

 6558 16:44:40.681410  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6559 16:44:40.688559  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6560 16:44:40.689143  

 6561 16:44:40.689512  [DATLAT]

 6562 16:44:40.689857  Freq=400, CH0 RK1

 6563 16:44:40.691287  

 6564 16:44:40.691748  DATLAT Default: 0xe

 6565 16:44:40.695134  0, 0xFFFF, sum = 0

 6566 16:44:40.695630  1, 0xFFFF, sum = 0

 6567 16:44:40.697790  2, 0xFFFF, sum = 0

 6568 16:44:40.698215  3, 0xFFFF, sum = 0

 6569 16:44:40.701049  4, 0xFFFF, sum = 0

 6570 16:44:40.701580  5, 0xFFFF, sum = 0

 6571 16:44:40.704401  6, 0xFFFF, sum = 0

 6572 16:44:40.704827  7, 0xFFFF, sum = 0

 6573 16:44:40.707746  8, 0xFFFF, sum = 0

 6574 16:44:40.708170  9, 0xFFFF, sum = 0

 6575 16:44:40.711927  10, 0xFFFF, sum = 0

 6576 16:44:40.712454  11, 0xFFFF, sum = 0

 6577 16:44:40.714888  12, 0xFFFF, sum = 0

 6578 16:44:40.715437  13, 0x0, sum = 1

 6579 16:44:40.717590  14, 0x0, sum = 2

 6580 16:44:40.718117  15, 0x0, sum = 3

 6581 16:44:40.721156  16, 0x0, sum = 4

 6582 16:44:40.721686  best_step = 14

 6583 16:44:40.722021  

 6584 16:44:40.722328  ==

 6585 16:44:40.724368  Dram Type= 6, Freq= 0, CH_0, rank 1

 6586 16:44:40.730812  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6587 16:44:40.731359  ==

 6588 16:44:40.731700  RX Vref Scan: 0

 6589 16:44:40.732009  

 6590 16:44:40.733928  RX Vref 0 -> 0, step: 1

 6591 16:44:40.734349  

 6592 16:44:40.737323  RX Delay -359 -> 252, step: 8

 6593 16:44:40.743738  iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472

 6594 16:44:40.747399  iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480

 6595 16:44:40.750400  iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480

 6596 16:44:40.757504  iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472

 6597 16:44:40.760994  iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480

 6598 16:44:40.763763  iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480

 6599 16:44:40.767110  iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480

 6600 16:44:40.773524  iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472

 6601 16:44:40.777276  iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488

 6602 16:44:40.780101  iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488

 6603 16:44:40.784007  iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488

 6604 16:44:40.790054  iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488

 6605 16:44:40.793732  iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488

 6606 16:44:40.796555  iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488

 6607 16:44:40.800031  iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488

 6608 16:44:40.806434  iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488

 6609 16:44:40.807001  ==

 6610 16:44:40.809687  Dram Type= 6, Freq= 0, CH_0, rank 1

 6611 16:44:40.813091  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6612 16:44:40.813663  ==

 6613 16:44:40.816483  DQS Delay:

 6614 16:44:40.817049  DQS0 = 40, DQS1 = 60

 6615 16:44:40.817418  DQM Delay:

 6616 16:44:40.819623  DQM0 = 6, DQM1 = 16

 6617 16:44:40.820189  DQ Delay:

 6618 16:44:40.823349  DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =4

 6619 16:44:40.826633  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12

 6620 16:44:40.829229  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6621 16:44:40.832299  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6622 16:44:40.832764  

 6623 16:44:40.833124  

 6624 16:44:40.842341  [DQSOSCAuto] RK1, (LSB)MR18= 0x8b85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps

 6625 16:44:40.842812  CH0 RK1: MR19=C0C, MR18=8B85

 6626 16:44:40.849245  CH0_RK1: MR19=0xC0C, MR18=0x8B85, DQSOSC=392, MR23=63, INC=384, DEC=256

 6627 16:44:40.852107  [RxdqsGatingPostProcess] freq 400

 6628 16:44:40.859023  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6629 16:44:40.862445  best DQS0 dly(2T, 0.5T) = (0, 10)

 6630 16:44:40.865861  best DQS1 dly(2T, 0.5T) = (0, 10)

 6631 16:44:40.868976  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6632 16:44:40.872159  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6633 16:44:40.875258  best DQS0 dly(2T, 0.5T) = (0, 10)

 6634 16:44:40.879257  best DQS1 dly(2T, 0.5T) = (0, 10)

 6635 16:44:40.882496  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6636 16:44:40.885279  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6637 16:44:40.885744  Pre-setting of DQS Precalculation

 6638 16:44:40.892182  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6639 16:44:40.892767  ==

 6640 16:44:40.895095  Dram Type= 6, Freq= 0, CH_1, rank 0

 6641 16:44:40.898892  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6642 16:44:40.899484  ==

 6643 16:44:40.905129  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6644 16:44:40.912128  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6645 16:44:40.915015  [CA 0] Center 36 (8~64) winsize 57

 6646 16:44:40.918259  [CA 1] Center 36 (8~64) winsize 57

 6647 16:44:40.921772  [CA 2] Center 36 (8~64) winsize 57

 6648 16:44:40.924649  [CA 3] Center 36 (8~64) winsize 57

 6649 16:44:40.927807  [CA 4] Center 36 (8~64) winsize 57

 6650 16:44:40.928244  [CA 5] Center 36 (8~64) winsize 57

 6651 16:44:40.931260  

 6652 16:44:40.934982  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6653 16:44:40.935445  

 6654 16:44:40.938086  [CATrainingPosCal] consider 1 rank data

 6655 16:44:40.941145  u2DelayCellTimex100 = 270/100 ps

 6656 16:44:40.944476  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6657 16:44:40.947437  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6658 16:44:40.951002  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6659 16:44:40.954534  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6660 16:44:40.957712  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6661 16:44:40.961213  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6662 16:44:40.961782  

 6663 16:44:40.964444  CA PerBit enable=1, Macro0, CA PI delay=36

 6664 16:44:40.967316  

 6665 16:44:40.967788  [CBTSetCACLKResult] CA Dly = 36

 6666 16:44:40.971712  CS Dly: 1 (0~32)

 6667 16:44:40.972278  ==

 6668 16:44:40.974033  Dram Type= 6, Freq= 0, CH_1, rank 1

 6669 16:44:40.977489  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6670 16:44:40.978061  ==

 6671 16:44:40.984061  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6672 16:44:40.990516  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 6673 16:44:40.993957  [CA 0] Center 36 (8~64) winsize 57

 6674 16:44:40.997194  [CA 1] Center 36 (8~64) winsize 57

 6675 16:44:41.000300  [CA 2] Center 36 (8~64) winsize 57

 6676 16:44:41.003854  [CA 3] Center 36 (8~64) winsize 57

 6677 16:44:41.004324  [CA 4] Center 36 (8~64) winsize 57

 6678 16:44:41.006849  [CA 5] Center 36 (8~64) winsize 57

 6679 16:44:41.007458  

 6680 16:44:41.013261  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 6681 16:44:41.013736  

 6682 16:44:41.016975  [CATrainingPosCal] consider 2 rank data

 6683 16:44:41.020465  u2DelayCellTimex100 = 270/100 ps

 6684 16:44:41.023425  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6685 16:44:41.026484  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6686 16:44:41.030403  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6687 16:44:41.033207  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6688 16:44:41.036207  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6689 16:44:41.039854  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6690 16:44:41.040418  

 6691 16:44:41.043430  CA PerBit enable=1, Macro0, CA PI delay=36

 6692 16:44:41.044009  

 6693 16:44:41.046560  [CBTSetCACLKResult] CA Dly = 36

 6694 16:44:41.049746  CS Dly: 1 (0~32)

 6695 16:44:41.050274  

 6696 16:44:41.053136  ----->DramcWriteLeveling(PI) begin...

 6697 16:44:41.053550  ==

 6698 16:44:41.056381  Dram Type= 6, Freq= 0, CH_1, rank 0

 6699 16:44:41.059999  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6700 16:44:41.060581  ==

 6701 16:44:41.063223  Write leveling (Byte 0): 40 => 8

 6702 16:44:41.066454  Write leveling (Byte 1): 40 => 8

 6703 16:44:41.069651  DramcWriteLeveling(PI) end<-----

 6704 16:44:41.070219  

 6705 16:44:41.070663  ==

 6706 16:44:41.073048  Dram Type= 6, Freq= 0, CH_1, rank 0

 6707 16:44:41.075725  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6708 16:44:41.076201  ==

 6709 16:44:41.079812  [Gating] SW mode calibration

 6710 16:44:41.085952  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6711 16:44:41.092343  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6712 16:44:41.095924   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6713 16:44:41.102593   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6714 16:44:41.105639   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6715 16:44:41.108949   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6716 16:44:41.116230   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6717 16:44:41.119141   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6718 16:44:41.122687   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6719 16:44:41.128487   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6720 16:44:41.131865   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6721 16:44:41.135162  Total UI for P1: 0, mck2ui 16

 6722 16:44:41.139302  best dqsien dly found for B0: ( 0, 14, 24)

 6723 16:44:41.141976  Total UI for P1: 0, mck2ui 16

 6724 16:44:41.145213  best dqsien dly found for B1: ( 0, 14, 24)

 6725 16:44:41.148391  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6726 16:44:41.151726  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6727 16:44:41.152194  

 6728 16:44:41.154832  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6729 16:44:41.161540  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6730 16:44:41.162157  [Gating] SW calibration Done

 6731 16:44:41.162536  ==

 6732 16:44:41.164701  Dram Type= 6, Freq= 0, CH_1, rank 0

 6733 16:44:41.171442  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6734 16:44:41.172014  ==

 6735 16:44:41.172386  RX Vref Scan: 0

 6736 16:44:41.172731  

 6737 16:44:41.174961  RX Vref 0 -> 0, step: 1

 6738 16:44:41.175466  

 6739 16:44:41.177975  RX Delay -410 -> 252, step: 16

 6740 16:44:41.181318  iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496

 6741 16:44:41.184330  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6742 16:44:41.190915  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6743 16:44:41.194144  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6744 16:44:41.197876  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6745 16:44:41.201484  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6746 16:44:41.207368  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6747 16:44:41.211525  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6748 16:44:41.214357  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6749 16:44:41.218351  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6750 16:44:41.224698  iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496

 6751 16:44:41.227384  iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512

 6752 16:44:41.230456  iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512

 6753 16:44:41.238050  iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512

 6754 16:44:41.240186  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6755 16:44:41.244033  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6756 16:44:41.244519  ==

 6757 16:44:41.247115  Dram Type= 6, Freq= 0, CH_1, rank 0

 6758 16:44:41.250482  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6759 16:44:41.253662  ==

 6760 16:44:41.254230  DQS Delay:

 6761 16:44:41.254599  DQS0 = 35, DQS1 = 51

 6762 16:44:41.257243  DQM Delay:

 6763 16:44:41.257815  DQM0 = 6, DQM1 = 13

 6764 16:44:41.260403  DQ Delay:

 6765 16:44:41.260976  DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0

 6766 16:44:41.264627  DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0

 6767 16:44:41.266862  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6768 16:44:41.269920  DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16

 6769 16:44:41.270481  

 6770 16:44:41.270850  

 6771 16:44:41.273783  ==

 6772 16:44:41.277194  Dram Type= 6, Freq= 0, CH_1, rank 0

 6773 16:44:41.280250  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6774 16:44:41.280828  ==

 6775 16:44:41.281205  

 6776 16:44:41.281547  

 6777 16:44:41.283293  	TX Vref Scan disable

 6778 16:44:41.283868   == TX Byte 0 ==

 6779 16:44:41.286814  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6780 16:44:41.293444  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6781 16:44:41.294040   == TX Byte 1 ==

 6782 16:44:41.296346  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6783 16:44:41.302977  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6784 16:44:41.303611  ==

 6785 16:44:41.305960  Dram Type= 6, Freq= 0, CH_1, rank 0

 6786 16:44:41.309515  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6787 16:44:41.310002  ==

 6788 16:44:41.310379  

 6789 16:44:41.310725  

 6790 16:44:41.312810  	TX Vref Scan disable

 6791 16:44:41.313275   == TX Byte 0 ==

 6792 16:44:41.317064  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6793 16:44:41.322640  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6794 16:44:41.323259   == TX Byte 1 ==

 6795 16:44:41.325940  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6796 16:44:41.332410  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6797 16:44:41.332983  

 6798 16:44:41.333349  [DATLAT]

 6799 16:44:41.335794  Freq=400, CH1 RK0

 6800 16:44:41.336264  

 6801 16:44:41.336636  DATLAT Default: 0xf

 6802 16:44:41.338793  0, 0xFFFF, sum = 0

 6803 16:44:41.339297  1, 0xFFFF, sum = 0

 6804 16:44:41.342125  2, 0xFFFF, sum = 0

 6805 16:44:41.342600  3, 0xFFFF, sum = 0

 6806 16:44:41.346112  4, 0xFFFF, sum = 0

 6807 16:44:41.346709  5, 0xFFFF, sum = 0

 6808 16:44:41.348941  6, 0xFFFF, sum = 0

 6809 16:44:41.349570  7, 0xFFFF, sum = 0

 6810 16:44:41.352046  8, 0xFFFF, sum = 0

 6811 16:44:41.352522  9, 0xFFFF, sum = 0

 6812 16:44:41.355643  10, 0xFFFF, sum = 0

 6813 16:44:41.356074  11, 0xFFFF, sum = 0

 6814 16:44:41.358770  12, 0xFFFF, sum = 0

 6815 16:44:41.359348  13, 0x0, sum = 1

 6816 16:44:41.362288  14, 0x0, sum = 2

 6817 16:44:41.362828  15, 0x0, sum = 3

 6818 16:44:41.366014  16, 0x0, sum = 4

 6819 16:44:41.366554  best_step = 14

 6820 16:44:41.366894  

 6821 16:44:41.367252  ==

 6822 16:44:41.368932  Dram Type= 6, Freq= 0, CH_1, rank 0

 6823 16:44:41.376335  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6824 16:44:41.376869  ==

 6825 16:44:41.377205  RX Vref Scan: 1

 6826 16:44:41.377520  

 6827 16:44:41.378483  RX Vref 0 -> 0, step: 1

 6828 16:44:41.378907  

 6829 16:44:41.382526  RX Delay -343 -> 252, step: 8

 6830 16:44:41.383056  

 6831 16:44:41.385216  Set Vref, RX VrefLevel [Byte0]: 53

 6832 16:44:41.389028                           [Byte1]: 51

 6833 16:44:41.392148  

 6834 16:44:41.392675  Final RX Vref Byte 0 = 53 to rank0

 6835 16:44:41.395298  Final RX Vref Byte 1 = 51 to rank0

 6836 16:44:41.398596  Final RX Vref Byte 0 = 53 to rank1

 6837 16:44:41.402204  Final RX Vref Byte 1 = 51 to rank1==

 6838 16:44:41.405523  Dram Type= 6, Freq= 0, CH_1, rank 0

 6839 16:44:41.412160  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6840 16:44:41.412724  ==

 6841 16:44:41.413071  DQS Delay:

 6842 16:44:41.415106  DQS0 = 44, DQS1 = 56

 6843 16:44:41.415591  DQM Delay:

 6844 16:44:41.415940  DQM0 = 9, DQM1 = 14

 6845 16:44:41.419325  DQ Delay:

 6846 16:44:41.422000  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6847 16:44:41.422421  DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4

 6848 16:44:41.424944  DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8

 6849 16:44:41.428239  DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20

 6850 16:44:41.428699  

 6851 16:44:41.429042  

 6852 16:44:41.438768  [DQSOSCAuto] RK0, (LSB)MR18= 0x6d93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps

 6853 16:44:41.441571  CH1 RK0: MR19=C0C, MR18=6D93

 6854 16:44:41.448371  CH1_RK0: MR19=0xC0C, MR18=0x6D93, DQSOSC=391, MR23=63, INC=386, DEC=257

 6855 16:44:41.448959  ==

 6856 16:44:41.451603  Dram Type= 6, Freq= 0, CH_1, rank 1

 6857 16:44:41.455297  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6858 16:44:41.455957  ==

 6859 16:44:41.458405  [Gating] SW mode calibration

 6860 16:44:41.464581  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6861 16:44:41.471687  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6862 16:44:41.474837   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6863 16:44:41.478484   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6864 16:44:41.484572   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6865 16:44:41.487557   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6866 16:44:41.490859   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6867 16:44:41.497868   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6868 16:44:41.500645   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6869 16:44:41.503723   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6870 16:44:41.510457   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6871 16:44:41.511018  Total UI for P1: 0, mck2ui 16

 6872 16:44:41.516979  best dqsien dly found for B0: ( 0, 14, 24)

 6873 16:44:41.517449  Total UI for P1: 0, mck2ui 16

 6874 16:44:41.523892  best dqsien dly found for B1: ( 0, 14, 24)

 6875 16:44:41.527570  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6876 16:44:41.530299  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6877 16:44:41.530769  

 6878 16:44:41.533848  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6879 16:44:41.537057  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6880 16:44:41.540603  [Gating] SW calibration Done

 6881 16:44:41.541165  ==

 6882 16:44:41.543373  Dram Type= 6, Freq= 0, CH_1, rank 1

 6883 16:44:41.547295  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6884 16:44:41.547865  ==

 6885 16:44:41.550010  RX Vref Scan: 0

 6886 16:44:41.550477  

 6887 16:44:41.552961  RX Vref 0 -> 0, step: 1

 6888 16:44:41.553427  

 6889 16:44:41.553794  RX Delay -410 -> 252, step: 16

 6890 16:44:41.560980  iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512

 6891 16:44:41.563299  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6892 16:44:41.566889  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6893 16:44:41.573287  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6894 16:44:41.576357  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6895 16:44:41.579595  iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512

 6896 16:44:41.583053  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6897 16:44:41.589822  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6898 16:44:41.593424  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6899 16:44:41.595862  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6900 16:44:41.599528  iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496

 6901 16:44:41.606087  iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512

 6902 16:44:41.609248  iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512

 6903 16:44:41.612658  iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512

 6904 16:44:41.616199  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6905 16:44:41.622577  iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512

 6906 16:44:41.623334  ==

 6907 16:44:41.626270  Dram Type= 6, Freq= 0, CH_1, rank 1

 6908 16:44:41.628867  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6909 16:44:41.629357  ==

 6910 16:44:41.632329  DQS Delay:

 6911 16:44:41.632918  DQS0 = 43, DQS1 = 51

 6912 16:44:41.633297  DQM Delay:

 6913 16:44:41.635368  DQM0 = 9, DQM1 = 14

 6914 16:44:41.635834  DQ Delay:

 6915 16:44:41.638658  DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8

 6916 16:44:41.642165  DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8

 6917 16:44:41.645646  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6918 16:44:41.648657  DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24

 6919 16:44:41.649131  

 6920 16:44:41.649502  

 6921 16:44:41.649844  ==

 6922 16:44:41.651819  Dram Type= 6, Freq= 0, CH_1, rank 1

 6923 16:44:41.655293  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6924 16:44:41.659336  ==

 6925 16:44:41.659900  

 6926 16:44:41.660269  

 6927 16:44:41.660610  	TX Vref Scan disable

 6928 16:44:41.662600   == TX Byte 0 ==

 6929 16:44:41.665376  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6930 16:44:41.668810  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6931 16:44:41.671725   == TX Byte 1 ==

 6932 16:44:41.675728  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6933 16:44:41.678231  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6934 16:44:41.678702  ==

 6935 16:44:41.681810  Dram Type= 6, Freq= 0, CH_1, rank 1

 6936 16:44:41.688130  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6937 16:44:41.688800  ==

 6938 16:44:41.689333  

 6939 16:44:41.689693  

 6940 16:44:41.690029  	TX Vref Scan disable

 6941 16:44:41.691261   == TX Byte 0 ==

 6942 16:44:41.694975  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6943 16:44:41.698121  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6944 16:44:41.700981   == TX Byte 1 ==

 6945 16:44:41.704767  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6946 16:44:41.708306  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6947 16:44:41.708998  

 6948 16:44:41.711056  [DATLAT]

 6949 16:44:41.711591  Freq=400, CH1 RK1

 6950 16:44:41.711965  

 6951 16:44:41.714624  DATLAT Default: 0xe

 6952 16:44:41.715236  0, 0xFFFF, sum = 0

 6953 16:44:41.717859  1, 0xFFFF, sum = 0

 6954 16:44:41.718434  2, 0xFFFF, sum = 0

 6955 16:44:41.721153  3, 0xFFFF, sum = 0

 6956 16:44:41.721730  4, 0xFFFF, sum = 0

 6957 16:44:41.723915  5, 0xFFFF, sum = 0

 6958 16:44:41.724389  6, 0xFFFF, sum = 0

 6959 16:44:41.727593  7, 0xFFFF, sum = 0

 6960 16:44:41.731327  8, 0xFFFF, sum = 0

 6961 16:44:41.731918  9, 0xFFFF, sum = 0

 6962 16:44:41.733767  10, 0xFFFF, sum = 0

 6963 16:44:41.734248  11, 0xFFFF, sum = 0

 6964 16:44:41.737734  12, 0xFFFF, sum = 0

 6965 16:44:41.738208  13, 0x0, sum = 1

 6966 16:44:41.740604  14, 0x0, sum = 2

 6967 16:44:41.741076  15, 0x0, sum = 3

 6968 16:44:41.743897  16, 0x0, sum = 4

 6969 16:44:41.744371  best_step = 14

 6970 16:44:41.744740  

 6971 16:44:41.745080  ==

 6972 16:44:41.747870  Dram Type= 6, Freq= 0, CH_1, rank 1

 6973 16:44:41.750479  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6974 16:44:41.751028  ==

 6975 16:44:41.754175  RX Vref Scan: 0

 6976 16:44:41.754642  

 6977 16:44:41.756929  RX Vref 0 -> 0, step: 1

 6978 16:44:41.757546  

 6979 16:44:41.757965  RX Delay -343 -> 252, step: 8

 6980 16:44:41.766098  iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488

 6981 16:44:41.769520  iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496

 6982 16:44:41.772357  iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496

 6983 16:44:41.778938  iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496

 6984 16:44:41.782437  iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488

 6985 16:44:41.785732  iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488

 6986 16:44:41.788993  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6987 16:44:41.795355  iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496

 6988 16:44:41.799386  iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488

 6989 16:44:41.802003  iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488

 6990 16:44:41.805560  iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496

 6991 16:44:41.812174  iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480

 6992 16:44:41.816019  iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480

 6993 16:44:41.819079  iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480

 6994 16:44:41.822304  iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488

 6995 16:44:41.828792  iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496

 6996 16:44:41.829398  ==

 6997 16:44:41.831689  Dram Type= 6, Freq= 0, CH_1, rank 1

 6998 16:44:41.835054  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6999 16:44:41.835554  ==

 7000 16:44:41.835925  DQS Delay:

 7001 16:44:41.838697  DQS0 = 48, DQS1 = 52

 7002 16:44:41.839165  DQM Delay:

 7003 16:44:41.841888  DQM0 = 11, DQM1 = 11

 7004 16:44:41.842414  DQ Delay:

 7005 16:44:41.845410  DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8

 7006 16:44:41.848234  DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8

 7007 16:44:41.851706  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4

 7008 16:44:41.854795  DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20

 7009 16:44:41.855288  

 7010 16:44:41.855660  

 7011 16:44:41.865005  [DQSOSCAuto] RK1, (LSB)MR18= 0x77ad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps

 7012 16:44:41.865581  CH1 RK1: MR19=C0C, MR18=77AD

 7013 16:44:41.871631  CH1_RK1: MR19=0xC0C, MR18=0x77AD, DQSOSC=388, MR23=63, INC=392, DEC=261

 7014 16:44:41.875079  [RxdqsGatingPostProcess] freq 400

 7015 16:44:41.881206  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 7016 16:44:41.884852  best DQS0 dly(2T, 0.5T) = (0, 10)

 7017 16:44:41.887974  best DQS1 dly(2T, 0.5T) = (0, 10)

 7018 16:44:41.891576  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7019 16:44:41.894345  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7020 16:44:41.897658  best DQS0 dly(2T, 0.5T) = (0, 10)

 7021 16:44:41.900993  best DQS1 dly(2T, 0.5T) = (0, 10)

 7022 16:44:41.904274  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7023 16:44:41.907510  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7024 16:44:41.907982  Pre-setting of DQS Precalculation

 7025 16:44:41.914300  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 7026 16:44:41.921415  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 7027 16:44:41.927763  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 7028 16:44:41.928336  

 7029 16:44:41.928703  

 7030 16:44:41.930758  [Calibration Summary] 800 Mbps

 7031 16:44:41.933704  CH 0, Rank 0

 7032 16:44:41.934271  SW Impedance     : PASS

 7033 16:44:41.936736  DUTY Scan        : NO K

 7034 16:44:41.940247  ZQ Calibration   : PASS

 7035 16:44:41.940808  Jitter Meter     : NO K

 7036 16:44:41.943715  CBT Training     : PASS

 7037 16:44:41.947006  Write leveling   : PASS

 7038 16:44:41.947634  RX DQS gating    : PASS

 7039 16:44:41.950139  RX DQ/DQS(RDDQC) : PASS

 7040 16:44:41.953613  TX DQ/DQS        : PASS

 7041 16:44:41.954083  RX DATLAT        : PASS

 7042 16:44:41.956896  RX DQ/DQS(Engine): PASS

 7043 16:44:41.959762  TX OE            : NO K

 7044 16:44:41.960231  All Pass.

 7045 16:44:41.960599  

 7046 16:44:41.960939  CH 0, Rank 1

 7047 16:44:41.962992  SW Impedance     : PASS

 7048 16:44:41.966816  DUTY Scan        : NO K

 7049 16:44:41.967430  ZQ Calibration   : PASS

 7050 16:44:41.969814  Jitter Meter     : NO K

 7051 16:44:41.974404  CBT Training     : PASS

 7052 16:44:41.974980  Write leveling   : NO K

 7053 16:44:41.976169  RX DQS gating    : PASS

 7054 16:44:41.979963  RX DQ/DQS(RDDQC) : PASS

 7055 16:44:41.980536  TX DQ/DQS        : PASS

 7056 16:44:41.982927  RX DATLAT        : PASS

 7057 16:44:41.983421  RX DQ/DQS(Engine): PASS

 7058 16:44:41.986308  TX OE            : NO K

 7059 16:44:41.987022  All Pass.

 7060 16:44:41.987444  

 7061 16:44:41.990547  CH 1, Rank 0

 7062 16:44:41.992894  SW Impedance     : PASS

 7063 16:44:41.993467  DUTY Scan        : NO K

 7064 16:44:41.996024  ZQ Calibration   : PASS

 7065 16:44:41.996595  Jitter Meter     : NO K

 7066 16:44:41.999451  CBT Training     : PASS

 7067 16:44:42.002308  Write leveling   : PASS

 7068 16:44:42.002781  RX DQS gating    : PASS

 7069 16:44:42.005738  RX DQ/DQS(RDDQC) : PASS

 7070 16:44:42.009418  TX DQ/DQS        : PASS

 7071 16:44:42.009995  RX DATLAT        : PASS

 7072 16:44:42.012486  RX DQ/DQS(Engine): PASS

 7073 16:44:42.016236  TX OE            : NO K

 7074 16:44:42.016999  All Pass.

 7075 16:44:42.017396  

 7076 16:44:42.017740  CH 1, Rank 1

 7077 16:44:42.018798  SW Impedance     : PASS

 7078 16:44:42.022545  DUTY Scan        : NO K

 7079 16:44:42.023116  ZQ Calibration   : PASS

 7080 16:44:42.025693  Jitter Meter     : NO K

 7081 16:44:42.029117  CBT Training     : PASS

 7082 16:44:42.029728  Write leveling   : NO K

 7083 16:44:42.032425  RX DQS gating    : PASS

 7084 16:44:42.036009  RX DQ/DQS(RDDQC) : PASS

 7085 16:44:42.036584  TX DQ/DQS        : PASS

 7086 16:44:42.038946  RX DATLAT        : PASS

 7087 16:44:42.042144  RX DQ/DQS(Engine): PASS

 7088 16:44:42.042712  TX OE            : NO K

 7089 16:44:42.045599  All Pass.

 7090 16:44:42.046203  

 7091 16:44:42.046577  DramC Write-DBI off

 7092 16:44:42.049582  	PER_BANK_REFRESH: Hybrid Mode

 7093 16:44:42.050171  TX_TRACKING: ON

 7094 16:44:42.058683  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7095 16:44:42.061863  [FAST_K] Save calibration result to emmc

 7096 16:44:42.065772  dramc_set_vcore_voltage set vcore to 725000

 7097 16:44:42.068358  Read voltage for 1600, 0

 7098 16:44:42.068945  Vio18 = 0

 7099 16:44:42.072473  Vcore = 725000

 7100 16:44:42.072938  Vdram = 0

 7101 16:44:42.073304  Vddq = 0

 7102 16:44:42.075324  Vmddr = 0

 7103 16:44:42.078227  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7104 16:44:42.085027  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7105 16:44:42.085605  MEM_TYPE=3, freq_sel=13

 7106 16:44:42.088691  sv_algorithm_assistance_LP4_3733 

 7107 16:44:42.095348  ============ PULL DRAM RESETB DOWN ============

 7108 16:44:42.098280  ========== PULL DRAM RESETB DOWN end =========

 7109 16:44:42.101779  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7110 16:44:42.105141  =================================== 

 7111 16:44:42.107833  LPDDR4 DRAM CONFIGURATION

 7112 16:44:42.111648  =================================== 

 7113 16:44:42.114564  EX_ROW_EN[0]    = 0x0

 7114 16:44:42.115030  EX_ROW_EN[1]    = 0x0

 7115 16:44:42.117604  LP4Y_EN      = 0x0

 7116 16:44:42.118070  WORK_FSP     = 0x1

 7117 16:44:42.120976  WL           = 0x5

 7118 16:44:42.121650  RL           = 0x5

 7119 16:44:42.124707  BL           = 0x2

 7120 16:44:42.125277  RPST         = 0x0

 7121 16:44:42.127573  RD_PRE       = 0x0

 7122 16:44:42.128143  WR_PRE       = 0x1

 7123 16:44:42.130879  WR_PST       = 0x1

 7124 16:44:42.131479  DBI_WR       = 0x0

 7125 16:44:42.133895  DBI_RD       = 0x0

 7126 16:44:42.137355  OTF          = 0x1

 7127 16:44:42.140837  =================================== 

 7128 16:44:42.144442  =================================== 

 7129 16:44:42.145015  ANA top config

 7130 16:44:42.147514  =================================== 

 7131 16:44:42.150795  DLL_ASYNC_EN            =  0

 7132 16:44:42.153747  ALL_SLAVE_EN            =  0

 7133 16:44:42.154345  NEW_RANK_MODE           =  1

 7134 16:44:42.156942  DLL_IDLE_MODE           =  1

 7135 16:44:42.160742  LP45_APHY_COMB_EN       =  1

 7136 16:44:42.163437  TX_ODT_DIS              =  0

 7137 16:44:42.163913  NEW_8X_MODE             =  1

 7138 16:44:42.167367  =================================== 

 7139 16:44:42.170286  =================================== 

 7140 16:44:42.173167  data_rate                  = 3200

 7141 16:44:42.177012  CKR                        = 1

 7142 16:44:42.179881  DQ_P2S_RATIO               = 8

 7143 16:44:42.183564  =================================== 

 7144 16:44:42.186549  CA_P2S_RATIO               = 8

 7145 16:44:42.190385  DQ_CA_OPEN                 = 0

 7146 16:44:42.193041  DQ_SEMI_OPEN               = 0

 7147 16:44:42.193603  CA_SEMI_OPEN               = 0

 7148 16:44:42.196248  CA_FULL_RATE               = 0

 7149 16:44:42.200241  DQ_CKDIV4_EN               = 0

 7150 16:44:42.202962  CA_CKDIV4_EN               = 0

 7151 16:44:42.206583  CA_PREDIV_EN               = 0

 7152 16:44:42.209820  PH8_DLY                    = 12

 7153 16:44:42.210386  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7154 16:44:42.213092  DQ_AAMCK_DIV               = 4

 7155 16:44:42.216310  CA_AAMCK_DIV               = 4

 7156 16:44:42.220025  CA_ADMCK_DIV               = 4

 7157 16:44:42.223087  DQ_TRACK_CA_EN             = 0

 7158 16:44:42.226148  CA_PICK                    = 1600

 7159 16:44:42.229624  CA_MCKIO                   = 1600

 7160 16:44:42.230191  MCKIO_SEMI                 = 0

 7161 16:44:42.232908  PLL_FREQ                   = 3068

 7162 16:44:42.236172  DQ_UI_PI_RATIO             = 32

 7163 16:44:42.239389  CA_UI_PI_RATIO             = 0

 7164 16:44:42.242447  =================================== 

 7165 16:44:42.246545  =================================== 

 7166 16:44:42.249169  memory_type:LPDDR4         

 7167 16:44:42.249736  GP_NUM     : 10       

 7168 16:44:42.252277  SRAM_EN    : 1       

 7169 16:44:42.255708  MD32_EN    : 0       

 7170 16:44:42.258800  =================================== 

 7171 16:44:42.259307  [ANA_INIT] >>>>>>>>>>>>>> 

 7172 16:44:42.262746  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7173 16:44:42.265657  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7174 16:44:42.268911  =================================== 

 7175 16:44:42.272241  data_rate = 3200,PCW = 0X7600

 7176 16:44:42.275609  =================================== 

 7177 16:44:42.278962  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7178 16:44:42.285155  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7179 16:44:42.291880  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7180 16:44:42.295450  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7181 16:44:42.298606  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7182 16:44:42.301939  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7183 16:44:42.305004  [ANA_INIT] flow start 

 7184 16:44:42.305596  [ANA_INIT] PLL >>>>>>>> 

 7185 16:44:42.308478  [ANA_INIT] PLL <<<<<<<< 

 7186 16:44:42.311703  [ANA_INIT] MIDPI >>>>>>>> 

 7187 16:44:42.315691  [ANA_INIT] MIDPI <<<<<<<< 

 7188 16:44:42.316264  [ANA_INIT] DLL >>>>>>>> 

 7189 16:44:42.318516  [ANA_INIT] DLL <<<<<<<< 

 7190 16:44:42.318983  [ANA_INIT] flow end 

 7191 16:44:42.324649  ============ LP4 DIFF to SE enter ============

 7192 16:44:42.328715  ============ LP4 DIFF to SE exit  ============

 7193 16:44:42.331325  [ANA_INIT] <<<<<<<<<<<<< 

 7194 16:44:42.335422  [Flow] Enable top DCM control >>>>> 

 7195 16:44:42.338441  [Flow] Enable top DCM control <<<<< 

 7196 16:44:42.341607  Enable DLL master slave shuffle 

 7197 16:44:42.344701  ============================================================== 

 7198 16:44:42.348491  Gating Mode config

 7199 16:44:42.351406  ============================================================== 

 7200 16:44:42.353989  Config description: 

 7201 16:44:42.364469  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7202 16:44:42.371339  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7203 16:44:42.374114  SELPH_MODE            0: By rank         1: By Phase 

 7204 16:44:42.380331  ============================================================== 

 7205 16:44:42.385135  GAT_TRACK_EN                 =  1

 7206 16:44:42.387422  RX_GATING_MODE               =  2

 7207 16:44:42.390846  RX_GATING_TRACK_MODE         =  2

 7208 16:44:42.393613  SELPH_MODE                   =  1

 7209 16:44:42.397234  PICG_EARLY_EN                =  1

 7210 16:44:42.400186  VALID_LAT_VALUE              =  1

 7211 16:44:42.404007  ============================================================== 

 7212 16:44:42.406745  Enter into Gating configuration >>>> 

 7213 16:44:42.410473  Exit from Gating configuration <<<< 

 7214 16:44:42.413300  Enter into  DVFS_PRE_config >>>>> 

 7215 16:44:42.426851  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7216 16:44:42.430476  Exit from  DVFS_PRE_config <<<<< 

 7217 16:44:42.433113  Enter into PICG configuration >>>> 

 7218 16:44:42.436984  Exit from PICG configuration <<<< 

 7219 16:44:42.437575  [RX_INPUT] configuration >>>>> 

 7220 16:44:42.439655  [RX_INPUT] configuration <<<<< 

 7221 16:44:42.446583  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7222 16:44:42.449911  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7223 16:44:42.456144  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7224 16:44:42.463376  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7225 16:44:42.469319  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7226 16:44:42.475897  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7227 16:44:42.479625  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7228 16:44:42.482762  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7229 16:44:42.489263  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7230 16:44:42.492442  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7231 16:44:42.496586  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7232 16:44:42.502250  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7233 16:44:42.505639  =================================== 

 7234 16:44:42.506224  LPDDR4 DRAM CONFIGURATION

 7235 16:44:42.508887  =================================== 

 7236 16:44:42.512252  EX_ROW_EN[0]    = 0x0

 7237 16:44:42.512740  EX_ROW_EN[1]    = 0x0

 7238 16:44:42.515465  LP4Y_EN      = 0x0

 7239 16:44:42.515934  WORK_FSP     = 0x1

 7240 16:44:42.519229  WL           = 0x5

 7241 16:44:42.519791  RL           = 0x5

 7242 16:44:42.522372  BL           = 0x2

 7243 16:44:42.525410  RPST         = 0x0

 7244 16:44:42.525972  RD_PRE       = 0x0

 7245 16:44:42.528878  WR_PRE       = 0x1

 7246 16:44:42.529445  WR_PST       = 0x1

 7247 16:44:42.532068  DBI_WR       = 0x0

 7248 16:44:42.532629  DBI_RD       = 0x0

 7249 16:44:42.535087  OTF          = 0x1

 7250 16:44:42.538519  =================================== 

 7251 16:44:42.541893  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7252 16:44:42.545265  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7253 16:44:42.551626  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7254 16:44:42.555165  =================================== 

 7255 16:44:42.555862  LPDDR4 DRAM CONFIGURATION

 7256 16:44:42.558276  =================================== 

 7257 16:44:42.562092  EX_ROW_EN[0]    = 0x10

 7258 16:44:42.562658  EX_ROW_EN[1]    = 0x0

 7259 16:44:42.564860  LP4Y_EN      = 0x0

 7260 16:44:42.568133  WORK_FSP     = 0x1

 7261 16:44:42.568696  WL           = 0x5

 7262 16:44:42.571396  RL           = 0x5

 7263 16:44:42.571951  BL           = 0x2

 7264 16:44:42.574832  RPST         = 0x0

 7265 16:44:42.575433  RD_PRE       = 0x0

 7266 16:44:42.577676  WR_PRE       = 0x1

 7267 16:44:42.578146  WR_PST       = 0x1

 7268 16:44:42.581304  DBI_WR       = 0x0

 7269 16:44:42.581885  DBI_RD       = 0x0

 7270 16:44:42.585604  OTF          = 0x1

 7271 16:44:42.587659  =================================== 

 7272 16:44:42.594491  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7273 16:44:42.595056  ==

 7274 16:44:42.598077  Dram Type= 6, Freq= 0, CH_0, rank 0

 7275 16:44:42.601131  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7276 16:44:42.601600  ==

 7277 16:44:42.604406  [Duty_Offset_Calibration]

 7278 16:44:42.604865  	B0:2	B1:0	CA:4

 7279 16:44:42.605229  

 7280 16:44:42.608110  [DutyScan_Calibration_Flow] k_type=0

 7281 16:44:42.617673  

 7282 16:44:42.618243  ==CLK 0==

 7283 16:44:42.621008  Final CLK duty delay cell = -4

 7284 16:44:42.624019  [-4] MAX Duty = 5031%(X100), DQS PI = 30

 7285 16:44:42.627846  [-4] MIN Duty = 4844%(X100), DQS PI = 8

 7286 16:44:42.630733  [-4] AVG Duty = 4937%(X100)

 7287 16:44:42.631350  

 7288 16:44:42.634150  CH0 CLK Duty spec in!! Max-Min= 187%

 7289 16:44:42.637565  [DutyScan_Calibration_Flow] ====Done====

 7290 16:44:42.638033  

 7291 16:44:42.640137  [DutyScan_Calibration_Flow] k_type=1

 7292 16:44:42.657249  

 7293 16:44:42.657806  ==DQS 0 ==

 7294 16:44:42.659957  Final DQS duty delay cell = -4

 7295 16:44:42.664139  [-4] MAX Duty = 4938%(X100), DQS PI = 48

 7296 16:44:42.666918  [-4] MIN Duty = 4782%(X100), DQS PI = 4

 7297 16:44:42.670523  [-4] AVG Duty = 4860%(X100)

 7298 16:44:42.671086  

 7299 16:44:42.671516  ==DQS 1 ==

 7300 16:44:42.673150  Final DQS duty delay cell = 0

 7301 16:44:42.676438  [0] MAX Duty = 5187%(X100), DQS PI = 2

 7302 16:44:42.680270  [0] MIN Duty = 4969%(X100), DQS PI = 10

 7303 16:44:42.683616  [0] AVG Duty = 5078%(X100)

 7304 16:44:42.684198  

 7305 16:44:42.686299  CH0 DQS 0 Duty spec in!! Max-Min= 156%

 7306 16:44:42.686861  

 7307 16:44:42.689636  CH0 DQS 1 Duty spec in!! Max-Min= 218%

 7308 16:44:42.692730  [DutyScan_Calibration_Flow] ====Done====

 7309 16:44:42.693197  

 7310 16:44:42.696079  [DutyScan_Calibration_Flow] k_type=3

 7311 16:44:42.714384  

 7312 16:44:42.714945  ==DQM 0 ==

 7313 16:44:42.717541  Final DQM duty delay cell = 0

 7314 16:44:42.721015  [0] MAX Duty = 5124%(X100), DQS PI = 20

 7315 16:44:42.724510  [0] MIN Duty = 4875%(X100), DQS PI = 56

 7316 16:44:42.727422  [0] AVG Duty = 4999%(X100)

 7317 16:44:42.727992  

 7318 16:44:42.728365  ==DQM 1 ==

 7319 16:44:42.731016  Final DQM duty delay cell = 0

 7320 16:44:42.734218  [0] MAX Duty = 4969%(X100), DQS PI = 0

 7321 16:44:42.737715  [0] MIN Duty = 4813%(X100), DQS PI = 16

 7322 16:44:42.740789  [0] AVG Duty = 4891%(X100)

 7323 16:44:42.741250  

 7324 16:44:42.743621  CH0 DQM 0 Duty spec in!! Max-Min= 249%

 7325 16:44:42.744087  

 7326 16:44:42.747122  CH0 DQM 1 Duty spec in!! Max-Min= 156%

 7327 16:44:42.750955  [DutyScan_Calibration_Flow] ====Done====

 7328 16:44:42.751591  

 7329 16:44:42.753794  [DutyScan_Calibration_Flow] k_type=2

 7330 16:44:42.772164  

 7331 16:44:42.772723  ==DQ 0 ==

 7332 16:44:42.774354  Final DQ duty delay cell = 0

 7333 16:44:42.777949  [0] MAX Duty = 5124%(X100), DQS PI = 20

 7334 16:44:42.781692  [0] MIN Duty = 4938%(X100), DQS PI = 12

 7335 16:44:42.784538  [0] AVG Duty = 5031%(X100)

 7336 16:44:42.785180  

 7337 16:44:42.785552  ==DQ 1 ==

 7338 16:44:42.788109  Final DQ duty delay cell = 0

 7339 16:44:42.790978  [0] MAX Duty = 5187%(X100), DQS PI = 2

 7340 16:44:42.794659  [0] MIN Duty = 4938%(X100), DQS PI = 12

 7341 16:44:42.795435  [0] AVG Duty = 5062%(X100)

 7342 16:44:42.797460  

 7343 16:44:42.801118  CH0 DQ 0 Duty spec in!! Max-Min= 186%

 7344 16:44:42.801583  

 7345 16:44:42.804171  CH0 DQ 1 Duty spec in!! Max-Min= 249%

 7346 16:44:42.808127  [DutyScan_Calibration_Flow] ====Done====

 7347 16:44:42.808694  ==

 7348 16:44:42.810793  Dram Type= 6, Freq= 0, CH_1, rank 0

 7349 16:44:42.814442  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7350 16:44:42.815033  ==

 7351 16:44:42.817305  [Duty_Offset_Calibration]

 7352 16:44:42.817877  	B0:0	B1:-1	CA:3

 7353 16:44:42.818243  

 7354 16:44:42.820932  [DutyScan_Calibration_Flow] k_type=0

 7355 16:44:42.831098  

 7356 16:44:42.831705  ==CLK 0==

 7357 16:44:42.834824  Final CLK duty delay cell = -4

 7358 16:44:42.837442  [-4] MAX Duty = 5031%(X100), DQS PI = 28

 7359 16:44:42.840453  [-4] MIN Duty = 4844%(X100), DQS PI = 38

 7360 16:44:42.843810  [-4] AVG Duty = 4937%(X100)

 7361 16:44:42.844262  

 7362 16:44:42.846960  CH1 CLK Duty spec in!! Max-Min= 187%

 7363 16:44:42.850407  [DutyScan_Calibration_Flow] ====Done====

 7364 16:44:42.850813  

 7365 16:44:42.853853  [DutyScan_Calibration_Flow] k_type=1

 7366 16:44:42.870198  

 7367 16:44:42.870714  ==DQS 0 ==

 7368 16:44:42.873090  Final DQS duty delay cell = 0

 7369 16:44:42.876548  [0] MAX Duty = 5250%(X100), DQS PI = 28

 7370 16:44:42.880110  [0] MIN Duty = 4907%(X100), DQS PI = 58

 7371 16:44:42.883900  [0] AVG Duty = 5078%(X100)

 7372 16:44:42.884418  

 7373 16:44:42.884738  ==DQS 1 ==

 7374 16:44:42.887046  Final DQS duty delay cell = -4

 7375 16:44:42.889772  [-4] MAX Duty = 5031%(X100), DQS PI = 30

 7376 16:44:42.893323  [-4] MIN Duty = 4844%(X100), DQS PI = 0

 7377 16:44:42.896161  [-4] AVG Duty = 4937%(X100)

 7378 16:44:42.896615  

 7379 16:44:42.900207  CH1 DQS 0 Duty spec in!! Max-Min= 343%

 7380 16:44:42.900698  

 7381 16:44:42.903159  CH1 DQS 1 Duty spec in!! Max-Min= 187%

 7382 16:44:42.906461  [DutyScan_Calibration_Flow] ====Done====

 7383 16:44:42.906993  

 7384 16:44:42.909521  [DutyScan_Calibration_Flow] k_type=3

 7385 16:44:42.927302  

 7386 16:44:42.927874  ==DQM 0 ==

 7387 16:44:42.930676  Final DQM duty delay cell = 0

 7388 16:44:42.933979  [0] MAX Duty = 5062%(X100), DQS PI = 32

 7389 16:44:42.936930  [0] MIN Duty = 4782%(X100), DQS PI = 40

 7390 16:44:42.940560  [0] AVG Duty = 4922%(X100)

 7391 16:44:42.941117  

 7392 16:44:42.941531  ==DQM 1 ==

 7393 16:44:42.943998  Final DQM duty delay cell = 0

 7394 16:44:42.947133  [0] MAX Duty = 5000%(X100), DQS PI = 30

 7395 16:44:42.950618  [0] MIN Duty = 4813%(X100), DQS PI = 0

 7396 16:44:42.953880  [0] AVG Duty = 4906%(X100)

 7397 16:44:42.954506  

 7398 16:44:42.957373  CH1 DQM 0 Duty spec in!! Max-Min= 280%

 7399 16:44:42.958015  

 7400 16:44:42.959943  CH1 DQM 1 Duty spec in!! Max-Min= 187%

 7401 16:44:42.963636  [DutyScan_Calibration_Flow] ====Done====

 7402 16:44:42.964106  

 7403 16:44:42.966909  [DutyScan_Calibration_Flow] k_type=2

 7404 16:44:42.983882  

 7405 16:44:42.984442  ==DQ 0 ==

 7406 16:44:42.986526  Final DQ duty delay cell = -4

 7407 16:44:42.990318  [-4] MAX Duty = 4969%(X100), DQS PI = 32

 7408 16:44:42.992858  [-4] MIN Duty = 4813%(X100), DQS PI = 36

 7409 16:44:42.996381  [-4] AVG Duty = 4891%(X100)

 7410 16:44:42.996811  

 7411 16:44:42.997148  ==DQ 1 ==

 7412 16:44:42.999444  Final DQ duty delay cell = 0

 7413 16:44:43.003354  [0] MAX Duty = 5062%(X100), DQS PI = 32

 7414 16:44:43.006634  [0] MIN Duty = 4875%(X100), DQS PI = 0

 7415 16:44:43.009763  [0] AVG Duty = 4968%(X100)

 7416 16:44:43.010325  

 7417 16:44:43.013119  CH1 DQ 0 Duty spec in!! Max-Min= 156%

 7418 16:44:43.013593  

 7419 16:44:43.016161  CH1 DQ 1 Duty spec in!! Max-Min= 187%

 7420 16:44:43.019286  [DutyScan_Calibration_Flow] ====Done====

 7421 16:44:43.022923  nWR fixed to 30

 7422 16:44:43.025820  [ModeRegInit_LP4] CH0 RK0

 7423 16:44:43.026249  [ModeRegInit_LP4] CH0 RK1

 7424 16:44:43.029135  [ModeRegInit_LP4] CH1 RK0

 7425 16:44:43.033034  [ModeRegInit_LP4] CH1 RK1

 7426 16:44:43.033552  match AC timing 5

 7427 16:44:43.039235  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7428 16:44:43.042495  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7429 16:44:43.045656  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7430 16:44:43.052990  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7431 16:44:43.055763  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7432 16:44:43.059360  [MiockJmeterHQA]

 7433 16:44:43.059831  

 7434 16:44:43.062780  [DramcMiockJmeter] u1RxGatingPI = 0

 7435 16:44:43.063240  0 : 4366, 4137

 7436 16:44:43.063591  4 : 4252, 4027

 7437 16:44:43.066444  8 : 4363, 4137

 7438 16:44:43.066872  12 : 4252, 4026

 7439 16:44:43.069315  16 : 4253, 4027

 7440 16:44:43.069841  20 : 4366, 4140

 7441 16:44:43.072392  24 : 4360, 4138

 7442 16:44:43.072920  28 : 4252, 4027

 7443 16:44:43.073260  32 : 4250, 4027

 7444 16:44:43.075346  36 : 4249, 4027

 7445 16:44:43.075774  40 : 4363, 4138

 7446 16:44:43.078756  44 : 4250, 4027

 7447 16:44:43.079216  48 : 4361, 4137

 7448 16:44:43.081904  52 : 4252, 4027

 7449 16:44:43.082333  56 : 4250, 4027

 7450 16:44:43.085219  60 : 4250, 4027

 7451 16:44:43.085757  64 : 4252, 4029

 7452 16:44:43.086104  68 : 4361, 4138

 7453 16:44:43.089201  72 : 4253, 4029

 7454 16:44:43.089730  76 : 4361, 4137

 7455 16:44:43.091709  80 : 4250, 4026

 7456 16:44:43.092139  84 : 4250, 4027

 7457 16:44:43.095380  88 : 4250, 4027

 7458 16:44:43.095903  92 : 4361, 4138

 7459 16:44:43.099588  96 : 4250, 3411

 7460 16:44:43.100117  100 : 4361, 0

 7461 16:44:43.100463  104 : 4361, 0

 7462 16:44:43.101703  108 : 4253, 0

 7463 16:44:43.102132  112 : 4250, 0

 7464 16:44:43.105362  116 : 4361, 0

 7465 16:44:43.105795  120 : 4250, 0

 7466 16:44:43.106134  124 : 4250, 0

 7467 16:44:43.108218  128 : 4250, 0

 7468 16:44:43.108647  132 : 4253, 0

 7469 16:44:43.111758  136 : 4361, 0

 7470 16:44:43.112283  140 : 4250, 0

 7471 16:44:43.112624  144 : 4250, 0

 7472 16:44:43.114806  148 : 4250, 0

 7473 16:44:43.115256  152 : 4361, 0

 7474 16:44:43.115598  156 : 4361, 0

 7475 16:44:43.118304  160 : 4250, 0

 7476 16:44:43.118828  164 : 4250, 0

 7477 16:44:43.121889  168 : 4250, 0

 7478 16:44:43.122421  172 : 4250, 0

 7479 16:44:43.122762  176 : 4250, 0

 7480 16:44:43.125071  180 : 4249, 0

 7481 16:44:43.125498  184 : 4253, 0

 7482 16:44:43.128095  188 : 4361, 0

 7483 16:44:43.128637  192 : 4360, 0

 7484 16:44:43.128979  196 : 4248, 0

 7485 16:44:43.131522  200 : 4360, 0

 7486 16:44:43.131948  204 : 4361, 0

 7487 16:44:43.135406  208 : 4361, 0

 7488 16:44:43.135832  212 : 4250, 0

 7489 16:44:43.136170  216 : 4250, 0

 7490 16:44:43.138096  220 : 4250, 416

 7491 16:44:43.138522  224 : 4250, 3971

 7492 16:44:43.141219  228 : 4250, 4027

 7493 16:44:43.141643  232 : 4250, 4027

 7494 16:44:43.145051  236 : 4252, 4030

 7495 16:44:43.145586  240 : 4250, 4026

 7496 16:44:43.147964  244 : 4250, 4027

 7497 16:44:43.148390  248 : 4253, 4029

 7498 16:44:43.151208  252 : 4250, 4027

 7499 16:44:43.151641  256 : 4361, 4137

 7500 16:44:43.151979  260 : 4361, 4137

 7501 16:44:43.155135  264 : 4249, 4027

 7502 16:44:43.155597  268 : 4363, 4140

 7503 16:44:43.157818  272 : 4360, 4137

 7504 16:44:43.158245  276 : 4250, 4026

 7505 16:44:43.161313  280 : 4250, 4027

 7506 16:44:43.161855  284 : 4253, 4029

 7507 16:44:43.164808  288 : 4250, 4027

 7508 16:44:43.165339  292 : 4250, 4026

 7509 16:44:43.167685  296 : 4250, 4027

 7510 16:44:43.168113  300 : 4250, 4027

 7511 16:44:43.171288  304 : 4250, 4027

 7512 16:44:43.171716  308 : 4361, 4138

 7513 16:44:43.174515  312 : 4361, 4138

 7514 16:44:43.174994  316 : 4248, 4024

 7515 16:44:43.177809  320 : 4363, 4140

 7516 16:44:43.178338  324 : 4361, 4138

 7517 16:44:43.178680  328 : 4250, 4026

 7518 16:44:43.180837  332 : 4250, 4016

 7519 16:44:43.181263  336 : 4253, 2052

 7520 16:44:43.181597  

 7521 16:44:43.184676  	MIOCK jitter meter	ch=0

 7522 16:44:43.185198  

 7523 16:44:43.187265  1T = (336-100) = 236 dly cells

 7524 16:44:43.193942  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps

 7525 16:44:43.194483  ==

 7526 16:44:43.197788  Dram Type= 6, Freq= 0, CH_0, rank 0

 7527 16:44:43.200629  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7528 16:44:43.201159  ==

 7529 16:44:43.207019  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7530 16:44:43.210419  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7531 16:44:43.214082  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7532 16:44:43.220053  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7533 16:44:43.229768  [CA 0] Center 43 (13~73) winsize 61

 7534 16:44:43.232977  [CA 1] Center 43 (13~73) winsize 61

 7535 16:44:43.236611  [CA 2] Center 38 (9~67) winsize 59

 7536 16:44:43.239546  [CA 3] Center 37 (8~67) winsize 60

 7537 16:44:43.243882  [CA 4] Center 35 (6~65) winsize 60

 7538 16:44:43.246610  [CA 5] Center 35 (5~66) winsize 62

 7539 16:44:43.247082  

 7540 16:44:43.249871  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7541 16:44:43.250346  

 7542 16:44:43.252842  [CATrainingPosCal] consider 1 rank data

 7543 16:44:43.256290  u2DelayCellTimex100 = 275/100 ps

 7544 16:44:43.263317  CA0 delay=43 (13~73),Diff = 8 PI (28 cell)

 7545 16:44:43.265967  CA1 delay=43 (13~73),Diff = 8 PI (28 cell)

 7546 16:44:43.269456  CA2 delay=38 (9~67),Diff = 3 PI (10 cell)

 7547 16:44:43.273389  CA3 delay=37 (8~67),Diff = 2 PI (7 cell)

 7548 16:44:43.276817  CA4 delay=35 (6~65),Diff = 0 PI (0 cell)

 7549 16:44:43.279447  CA5 delay=35 (5~66),Diff = 0 PI (0 cell)

 7550 16:44:43.279912  

 7551 16:44:43.282640  CA PerBit enable=1, Macro0, CA PI delay=35

 7552 16:44:43.283260  

 7553 16:44:43.286314  [CBTSetCACLKResult] CA Dly = 35

 7554 16:44:43.289488  CS Dly: 11 (0~42)

 7555 16:44:43.292126  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7556 16:44:43.295763  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7557 16:44:43.296328  ==

 7558 16:44:43.299368  Dram Type= 6, Freq= 0, CH_0, rank 1

 7559 16:44:43.305489  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7560 16:44:43.306054  ==

 7561 16:44:43.309572  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7562 16:44:43.315901  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7563 16:44:43.318956  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7564 16:44:43.325588  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7565 16:44:43.333254  [CA 0] Center 43 (13~74) winsize 62

 7566 16:44:43.336781  [CA 1] Center 43 (13~73) winsize 61

 7567 16:44:43.339744  [CA 2] Center 38 (9~68) winsize 60

 7568 16:44:43.343717  [CA 3] Center 38 (9~68) winsize 60

 7569 16:44:43.346398  [CA 4] Center 36 (6~67) winsize 62

 7570 16:44:43.349904  [CA 5] Center 36 (6~66) winsize 61

 7571 16:44:43.350460  

 7572 16:44:43.353128  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7573 16:44:43.353597  

 7574 16:44:43.356332  [CATrainingPosCal] consider 2 rank data

 7575 16:44:43.359554  u2DelayCellTimex100 = 275/100 ps

 7576 16:44:43.363134  CA0 delay=43 (13~73),Diff = 8 PI (28 cell)

 7577 16:44:43.370643  CA1 delay=43 (13~73),Diff = 8 PI (28 cell)

 7578 16:44:43.372763  CA2 delay=38 (9~67),Diff = 3 PI (10 cell)

 7579 16:44:43.376103  CA3 delay=38 (9~67),Diff = 3 PI (10 cell)

 7580 16:44:43.379487  CA4 delay=35 (6~65),Diff = 0 PI (0 cell)

 7581 16:44:43.382816  CA5 delay=36 (6~66),Diff = 1 PI (3 cell)

 7582 16:44:43.383411  

 7583 16:44:43.386438  CA PerBit enable=1, Macro0, CA PI delay=35

 7584 16:44:43.386998  

 7585 16:44:43.389803  [CBTSetCACLKResult] CA Dly = 35

 7586 16:44:43.393341  CS Dly: 12 (0~44)

 7587 16:44:43.396061  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7588 16:44:43.399469  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7589 16:44:43.400040  

 7590 16:44:43.402301  ----->DramcWriteLeveling(PI) begin...

 7591 16:44:43.402805  ==

 7592 16:44:43.406095  Dram Type= 6, Freq= 0, CH_0, rank 0

 7593 16:44:43.412846  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7594 16:44:43.413371  ==

 7595 16:44:43.415730  Write leveling (Byte 0): 33 => 33

 7596 16:44:43.419293  Write leveling (Byte 1): 26 => 26

 7597 16:44:43.419811  DramcWriteLeveling(PI) end<-----

 7598 16:44:43.422691  

 7599 16:44:43.423247  ==

 7600 16:44:43.426063  Dram Type= 6, Freq= 0, CH_0, rank 0

 7601 16:44:43.429449  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7602 16:44:43.429976  ==

 7603 16:44:43.432472  [Gating] SW mode calibration

 7604 16:44:43.439237  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7605 16:44:43.442382  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7606 16:44:43.448994   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7607 16:44:43.452177   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7608 16:44:43.455481   1  4  8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)

 7609 16:44:43.461733   1  4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)

 7610 16:44:43.465819   1  4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 7611 16:44:43.468399   1  4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)

 7612 16:44:43.475687   1  4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 7613 16:44:43.478521   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7614 16:44:43.482668   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7615 16:44:43.488828   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7616 16:44:43.491884   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 7617 16:44:43.498338   1  5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)

 7618 16:44:43.501585   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)

 7619 16:44:43.505501   1  5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)

 7620 16:44:43.511952   1  5 24 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)

 7621 16:44:43.515156   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7622 16:44:43.518225   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7623 16:44:43.524401   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7624 16:44:43.527816   1  6  8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)

 7625 16:44:43.531136   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 7626 16:44:43.537975   1  6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 7627 16:44:43.541029   1  6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)

 7628 16:44:43.544247   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7629 16:44:43.550683   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7630 16:44:43.553933   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7631 16:44:43.557803   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7632 16:44:43.564458   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7633 16:44:43.567251   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7634 16:44:43.570707   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 7635 16:44:43.577372   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7636 16:44:43.580319   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7637 16:44:43.583446   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7638 16:44:43.590924   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7639 16:44:43.593625   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7640 16:44:43.597822   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7641 16:44:43.603992   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7642 16:44:43.606888   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7643 16:44:43.609948   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7644 16:44:43.616588   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7645 16:44:43.619835   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7646 16:44:43.623345   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7647 16:44:43.629899   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7648 16:44:43.633214   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7649 16:44:43.636182   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7650 16:44:43.643253   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 7651 16:44:43.643845  Total UI for P1: 0, mck2ui 16

 7652 16:44:43.649205  best dqsien dly found for B0: ( 1,  9, 10)

 7653 16:44:43.653378   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7654 16:44:43.656070   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7655 16:44:43.659088  Total UI for P1: 0, mck2ui 16

 7656 16:44:43.662976  best dqsien dly found for B1: ( 1,  9, 20)

 7657 16:44:43.665618  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 7658 16:44:43.669790  best DQS1 dly(MCK, UI, PI) = (1, 9, 20)

 7659 16:44:43.670371  

 7660 16:44:43.675778  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 7661 16:44:43.679018  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)

 7662 16:44:43.682646  [Gating] SW calibration Done

 7663 16:44:43.683117  ==

 7664 16:44:43.685227  Dram Type= 6, Freq= 0, CH_0, rank 0

 7665 16:44:43.688949  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7666 16:44:43.689538  ==

 7667 16:44:43.689913  RX Vref Scan: 0

 7668 16:44:43.692018  

 7669 16:44:43.692489  RX Vref 0 -> 0, step: 1

 7670 16:44:43.692863  

 7671 16:44:43.695272  RX Delay 0 -> 252, step: 8

 7672 16:44:43.698527  iDelay=192, Bit 0, Center 131 (80 ~ 183) 104

 7673 16:44:43.702480  iDelay=192, Bit 1, Center 135 (80 ~ 191) 112

 7674 16:44:43.708620  iDelay=192, Bit 2, Center 127 (72 ~ 183) 112

 7675 16:44:43.711482  iDelay=192, Bit 3, Center 131 (80 ~ 183) 104

 7676 16:44:43.715532  iDelay=192, Bit 4, Center 135 (80 ~ 191) 112

 7677 16:44:43.718426  iDelay=192, Bit 5, Center 119 (64 ~ 175) 112

 7678 16:44:43.721980  iDelay=192, Bit 6, Center 139 (88 ~ 191) 104

 7679 16:44:43.728461  iDelay=192, Bit 7, Center 139 (88 ~ 191) 104

 7680 16:44:43.731303  iDelay=192, Bit 8, Center 115 (64 ~ 167) 104

 7681 16:44:43.734782  iDelay=192, Bit 9, Center 111 (56 ~ 167) 112

 7682 16:44:43.738067  iDelay=192, Bit 10, Center 127 (80 ~ 175) 96

 7683 16:44:43.741421  iDelay=192, Bit 11, Center 123 (72 ~ 175) 104

 7684 16:44:43.749002  iDelay=192, Bit 12, Center 135 (80 ~ 191) 112

 7685 16:44:43.751103  iDelay=192, Bit 13, Center 131 (80 ~ 183) 104

 7686 16:44:43.754691  iDelay=192, Bit 14, Center 135 (80 ~ 191) 112

 7687 16:44:43.757776  iDelay=192, Bit 15, Center 131 (80 ~ 183) 104

 7688 16:44:43.758318  ==

 7689 16:44:43.761508  Dram Type= 6, Freq= 0, CH_0, rank 0

 7690 16:44:43.767802  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7691 16:44:43.768230  ==

 7692 16:44:43.768565  DQS Delay:

 7693 16:44:43.771061  DQS0 = 0, DQS1 = 0

 7694 16:44:43.771504  DQM Delay:

 7695 16:44:43.775136  DQM0 = 132, DQM1 = 126

 7696 16:44:43.775745  DQ Delay:

 7697 16:44:43.777621  DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131

 7698 16:44:43.780857  DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139

 7699 16:44:43.783899  DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123

 7700 16:44:43.787144  DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131

 7701 16:44:43.787582  

 7702 16:44:43.787913  

 7703 16:44:43.788222  ==

 7704 16:44:43.790672  Dram Type= 6, Freq= 0, CH_0, rank 0

 7705 16:44:43.797685  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7706 16:44:43.798256  ==

 7707 16:44:43.798626  

 7708 16:44:43.798963  

 7709 16:44:43.800891  	TX Vref Scan disable

 7710 16:44:43.801352   == TX Byte 0 ==

 7711 16:44:43.803845  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 7712 16:44:43.810626  Update DQM dly =989 (3 ,6, 29)  DQM OEN =(3 ,3)

 7713 16:44:43.811221   == TX Byte 1 ==

 7714 16:44:43.814196  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 7715 16:44:43.820166  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 7716 16:44:43.820732  ==

 7717 16:44:43.824139  Dram Type= 6, Freq= 0, CH_0, rank 0

 7718 16:44:43.826704  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7719 16:44:43.827192  ==

 7720 16:44:43.840714  

 7721 16:44:43.844576  TX Vref early break, caculate TX vref

 7722 16:44:43.847223  TX Vref=16, minBit 1, minWin=21, winSum=359

 7723 16:44:43.850979  TX Vref=18, minBit 0, minWin=22, winSum=372

 7724 16:44:43.853769  TX Vref=20, minBit 1, minWin=22, winSum=380

 7725 16:44:43.856922  TX Vref=22, minBit 1, minWin=22, winSum=391

 7726 16:44:43.860312  TX Vref=24, minBit 1, minWin=23, winSum=397

 7727 16:44:43.867301  TX Vref=26, minBit 1, minWin=23, winSum=407

 7728 16:44:43.870237  TX Vref=28, minBit 4, minWin=23, winSum=411

 7729 16:44:43.874279  TX Vref=30, minBit 4, minWin=24, winSum=408

 7730 16:44:43.877359  TX Vref=32, minBit 0, minWin=23, winSum=395

 7731 16:44:43.880210  TX Vref=34, minBit 0, minWin=23, winSum=389

 7732 16:44:43.886652  [TxChooseVref] Worse bit 4, Min win 24, Win sum 408, Final Vref 30

 7733 16:44:43.887271  

 7734 16:44:43.890444  Final TX Range 0 Vref 30

 7735 16:44:43.891015  

 7736 16:44:43.891450  ==

 7737 16:44:43.893662  Dram Type= 6, Freq= 0, CH_0, rank 0

 7738 16:44:43.896417  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7739 16:44:43.896889  ==

 7740 16:44:43.897258  

 7741 16:44:43.897600  

 7742 16:44:43.899735  	TX Vref Scan disable

 7743 16:44:43.906559  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 7744 16:44:43.906986   == TX Byte 0 ==

 7745 16:44:43.910353  u2DelayCellOfst[0]=14 cells (4 PI)

 7746 16:44:43.912761  u2DelayCellOfst[1]=17 cells (5 PI)

 7747 16:44:43.916329  u2DelayCellOfst[2]=14 cells (4 PI)

 7748 16:44:43.920358  u2DelayCellOfst[3]=14 cells (4 PI)

 7749 16:44:43.922763  u2DelayCellOfst[4]=10 cells (3 PI)

 7750 16:44:43.926668  u2DelayCellOfst[5]=0 cells (0 PI)

 7751 16:44:43.930224  u2DelayCellOfst[6]=17 cells (5 PI)

 7752 16:44:43.933092  u2DelayCellOfst[7]=17 cells (5 PI)

 7753 16:44:43.935908  Update DQ  dly =987 (3 ,6, 27)  DQ  OEN =(3 ,3)

 7754 16:44:43.940137  Update DQM dly =989 (3 ,6, 29)  DQM OEN =(3 ,3)

 7755 16:44:43.942667   == TX Byte 1 ==

 7756 16:44:43.946140  u2DelayCellOfst[8]=0 cells (0 PI)

 7757 16:44:43.950047  u2DelayCellOfst[9]=0 cells (0 PI)

 7758 16:44:43.952340  u2DelayCellOfst[10]=3 cells (1 PI)

 7759 16:44:43.956191  u2DelayCellOfst[11]=0 cells (0 PI)

 7760 16:44:43.956722  u2DelayCellOfst[12]=7 cells (2 PI)

 7761 16:44:43.959156  u2DelayCellOfst[13]=7 cells (2 PI)

 7762 16:44:43.962198  u2DelayCellOfst[14]=14 cells (4 PI)

 7763 16:44:43.965622  u2DelayCellOfst[15]=10 cells (3 PI)

 7764 16:44:43.972977  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 7765 16:44:43.975538  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 7766 16:44:43.976012  DramC Write-DBI on

 7767 16:44:43.978926  ==

 7768 16:44:43.982181  Dram Type= 6, Freq= 0, CH_0, rank 0

 7769 16:44:43.985001  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7770 16:44:43.985483  ==

 7771 16:44:43.985854  

 7772 16:44:43.986204  

 7773 16:44:43.988521  	TX Vref Scan disable

 7774 16:44:43.988952   == TX Byte 0 ==

 7775 16:44:43.995585  Update DQM dly =733 (2 ,6, 29)  DQM OEN =(3 ,3)

 7776 16:44:43.996120   == TX Byte 1 ==

 7777 16:44:43.998424  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 7778 16:44:44.002122  DramC Write-DBI off

 7779 16:44:44.002552  

 7780 16:44:44.002887  [DATLAT]

 7781 16:44:44.004769  Freq=1600, CH0 RK0

 7782 16:44:44.005224  

 7783 16:44:44.005570  DATLAT Default: 0xf

 7784 16:44:44.008052  0, 0xFFFF, sum = 0

 7785 16:44:44.008489  1, 0xFFFF, sum = 0

 7786 16:44:44.011775  2, 0xFFFF, sum = 0

 7787 16:44:44.014698  3, 0xFFFF, sum = 0

 7788 16:44:44.015270  4, 0xFFFF, sum = 0

 7789 16:44:44.018426  5, 0xFFFF, sum = 0

 7790 16:44:44.018967  6, 0xFFFF, sum = 0

 7791 16:44:44.021468  7, 0xFFFF, sum = 0

 7792 16:44:44.022034  8, 0xFFFF, sum = 0

 7793 16:44:44.024852  9, 0xFFFF, sum = 0

 7794 16:44:44.025285  10, 0xFFFF, sum = 0

 7795 16:44:44.028094  11, 0xFFFF, sum = 0

 7796 16:44:44.028629  12, 0xFFFF, sum = 0

 7797 16:44:44.031699  13, 0xFFFF, sum = 0

 7798 16:44:44.032242  14, 0x0, sum = 1

 7799 16:44:44.034450  15, 0x0, sum = 2

 7800 16:44:44.034994  16, 0x0, sum = 3

 7801 16:44:44.037817  17, 0x0, sum = 4

 7802 16:44:44.038252  best_step = 15

 7803 16:44:44.038590  

 7804 16:44:44.038902  ==

 7805 16:44:44.041500  Dram Type= 6, Freq= 0, CH_0, rank 0

 7806 16:44:44.048013  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7807 16:44:44.048549  ==

 7808 16:44:44.048892  RX Vref Scan: 1

 7809 16:44:44.049210  

 7810 16:44:44.050998  Set Vref Range= 24 -> 127

 7811 16:44:44.051465  

 7812 16:44:44.054371  RX Vref 24 -> 127, step: 1

 7813 16:44:44.054902  

 7814 16:44:44.055287  RX Delay 11 -> 252, step: 4

 7815 16:44:44.057796  

 7816 16:44:44.058221  Set Vref, RX VrefLevel [Byte0]: 24

 7817 16:44:44.060704                           [Byte1]: 24

 7818 16:44:44.065317  

 7819 16:44:44.065838  Set Vref, RX VrefLevel [Byte0]: 25

 7820 16:44:44.068526                           [Byte1]: 25

 7821 16:44:44.073562  

 7822 16:44:44.074094  Set Vref, RX VrefLevel [Byte0]: 26

 7823 16:44:44.076102                           [Byte1]: 26

 7824 16:44:44.080308  

 7825 16:44:44.080867  Set Vref, RX VrefLevel [Byte0]: 27

 7826 16:44:44.083348                           [Byte1]: 27

 7827 16:44:44.088602  

 7828 16:44:44.089067  Set Vref, RX VrefLevel [Byte0]: 28

 7829 16:44:44.090916                           [Byte1]: 28

 7830 16:44:44.095802  

 7831 16:44:44.096380  Set Vref, RX VrefLevel [Byte0]: 29

 7832 16:44:44.098914                           [Byte1]: 29

 7833 16:44:44.103310  

 7834 16:44:44.103885  Set Vref, RX VrefLevel [Byte0]: 30

 7835 16:44:44.106836                           [Byte1]: 30

 7836 16:44:44.110861  

 7837 16:44:44.111362  Set Vref, RX VrefLevel [Byte0]: 31

 7838 16:44:44.113918                           [Byte1]: 31

 7839 16:44:44.118854  

 7840 16:44:44.119470  Set Vref, RX VrefLevel [Byte0]: 32

 7841 16:44:44.121650                           [Byte1]: 32

 7842 16:44:44.126338  

 7843 16:44:44.126914  Set Vref, RX VrefLevel [Byte0]: 33

 7844 16:44:44.129172                           [Byte1]: 33

 7845 16:44:44.133865  

 7846 16:44:44.134436  Set Vref, RX VrefLevel [Byte0]: 34

 7847 16:44:44.137620                           [Byte1]: 34

 7848 16:44:44.141631  

 7849 16:44:44.142205  Set Vref, RX VrefLevel [Byte0]: 35

 7850 16:44:44.144508                           [Byte1]: 35

 7851 16:44:44.149164  

 7852 16:44:44.149744  Set Vref, RX VrefLevel [Byte0]: 36

 7853 16:44:44.152115                           [Byte1]: 36

 7854 16:44:44.156684  

 7855 16:44:44.157150  Set Vref, RX VrefLevel [Byte0]: 37

 7856 16:44:44.159625                           [Byte1]: 37

 7857 16:44:44.164555  

 7858 16:44:44.165130  Set Vref, RX VrefLevel [Byte0]: 38

 7859 16:44:44.167496                           [Byte1]: 38

 7860 16:44:44.172006  

 7861 16:44:44.172575  Set Vref, RX VrefLevel [Byte0]: 39

 7862 16:44:44.175765                           [Byte1]: 39

 7863 16:44:44.179508  

 7864 16:44:44.179980  Set Vref, RX VrefLevel [Byte0]: 40

 7865 16:44:44.182650                           [Byte1]: 40

 7866 16:44:44.187395  

 7867 16:44:44.187964  Set Vref, RX VrefLevel [Byte0]: 41

 7868 16:44:44.190093                           [Byte1]: 41

 7869 16:44:44.194732  

 7870 16:44:44.195377  Set Vref, RX VrefLevel [Byte0]: 42

 7871 16:44:44.197613                           [Byte1]: 42

 7872 16:44:44.202302  

 7873 16:44:44.202838  Set Vref, RX VrefLevel [Byte0]: 43

 7874 16:44:44.205297                           [Byte1]: 43

 7875 16:44:44.210167  

 7876 16:44:44.210716  Set Vref, RX VrefLevel [Byte0]: 44

 7877 16:44:44.213348                           [Byte1]: 44

 7878 16:44:44.217313  

 7879 16:44:44.217779  Set Vref, RX VrefLevel [Byte0]: 45

 7880 16:44:44.220309                           [Byte1]: 45

 7881 16:44:44.224711  

 7882 16:44:44.225135  Set Vref, RX VrefLevel [Byte0]: 46

 7883 16:44:44.228092                           [Byte1]: 46

 7884 16:44:44.232715  

 7885 16:44:44.233141  Set Vref, RX VrefLevel [Byte0]: 47

 7886 16:44:44.235858                           [Byte1]: 47

 7887 16:44:44.240118  

 7888 16:44:44.240583  Set Vref, RX VrefLevel [Byte0]: 48

 7889 16:44:44.243698                           [Byte1]: 48

 7890 16:44:44.247471  

 7891 16:44:44.247972  Set Vref, RX VrefLevel [Byte0]: 49

 7892 16:44:44.250715                           [Byte1]: 49

 7893 16:44:44.255742  

 7894 16:44:44.256163  Set Vref, RX VrefLevel [Byte0]: 50

 7895 16:44:44.258706                           [Byte1]: 50

 7896 16:44:44.262955  

 7897 16:44:44.263437  Set Vref, RX VrefLevel [Byte0]: 51

 7898 16:44:44.266137                           [Byte1]: 51

 7899 16:44:44.270835  

 7900 16:44:44.271409  Set Vref, RX VrefLevel [Byte0]: 52

 7901 16:44:44.274213                           [Byte1]: 52

 7902 16:44:44.278126  

 7903 16:44:44.278645  Set Vref, RX VrefLevel [Byte0]: 53

 7904 16:44:44.281542                           [Byte1]: 53

 7905 16:44:44.285960  

 7906 16:44:44.286480  Set Vref, RX VrefLevel [Byte0]: 54

 7907 16:44:44.289057                           [Byte1]: 54

 7908 16:44:44.294033  

 7909 16:44:44.294453  Set Vref, RX VrefLevel [Byte0]: 55

 7910 16:44:44.296880                           [Byte1]: 55

 7911 16:44:44.301537  

 7912 16:44:44.302076  Set Vref, RX VrefLevel [Byte0]: 56

 7913 16:44:44.304168                           [Byte1]: 56

 7914 16:44:44.308657  

 7915 16:44:44.309174  Set Vref, RX VrefLevel [Byte0]: 57

 7916 16:44:44.311884                           [Byte1]: 57

 7917 16:44:44.317290  

 7918 16:44:44.317810  Set Vref, RX VrefLevel [Byte0]: 58

 7919 16:44:44.319434                           [Byte1]: 58

 7920 16:44:44.324567  

 7921 16:44:44.325085  Set Vref, RX VrefLevel [Byte0]: 59

 7922 16:44:44.327521                           [Byte1]: 59

 7923 16:44:44.331278  

 7924 16:44:44.331701  Set Vref, RX VrefLevel [Byte0]: 60

 7925 16:44:44.335022                           [Byte1]: 60

 7926 16:44:44.339333  

 7927 16:44:44.339847  Set Vref, RX VrefLevel [Byte0]: 61

 7928 16:44:44.342935                           [Byte1]: 61

 7929 16:44:44.347114  

 7930 16:44:44.347676  Set Vref, RX VrefLevel [Byte0]: 62

 7931 16:44:44.350179                           [Byte1]: 62

 7932 16:44:44.354191  

 7933 16:44:44.354661  Set Vref, RX VrefLevel [Byte0]: 63

 7934 16:44:44.357471                           [Byte1]: 63

 7935 16:44:44.362321  

 7936 16:44:44.362908  Set Vref, RX VrefLevel [Byte0]: 64

 7937 16:44:44.365164                           [Byte1]: 64

 7938 16:44:44.369260  

 7939 16:44:44.369726  Set Vref, RX VrefLevel [Byte0]: 65

 7940 16:44:44.372718                           [Byte1]: 65

 7941 16:44:44.377745  

 7942 16:44:44.378264  Set Vref, RX VrefLevel [Byte0]: 66

 7943 16:44:44.380858                           [Byte1]: 66

 7944 16:44:44.384995  

 7945 16:44:44.385461  Set Vref, RX VrefLevel [Byte0]: 67

 7946 16:44:44.387833                           [Byte1]: 67

 7947 16:44:44.392622  

 7948 16:44:44.393181  Set Vref, RX VrefLevel [Byte0]: 68

 7949 16:44:44.395647                           [Byte1]: 68

 7950 16:44:44.400176  

 7951 16:44:44.400784  Set Vref, RX VrefLevel [Byte0]: 69

 7952 16:44:44.403669                           [Byte1]: 69

 7953 16:44:44.407631  

 7954 16:44:44.408097  Set Vref, RX VrefLevel [Byte0]: 70

 7955 16:44:44.410976                           [Byte1]: 70

 7956 16:44:44.415658  

 7957 16:44:44.416141  Set Vref, RX VrefLevel [Byte0]: 71

 7958 16:44:44.419279                           [Byte1]: 71

 7959 16:44:44.423768  

 7960 16:44:44.424478  Set Vref, RX VrefLevel [Byte0]: 72

 7961 16:44:44.426238                           [Byte1]: 72

 7962 16:44:44.431031  

 7963 16:44:44.431630  Set Vref, RX VrefLevel [Byte0]: 73

 7964 16:44:44.433746                           [Byte1]: 73

 7965 16:44:44.438350  

 7966 16:44:44.438915  Set Vref, RX VrefLevel [Byte0]: 74

 7967 16:44:44.441413                           [Byte1]: 74

 7968 16:44:44.446097  

 7969 16:44:44.446560  Set Vref, RX VrefLevel [Byte0]: 75

 7970 16:44:44.452065                           [Byte1]: 75

 7971 16:44:44.452614  

 7972 16:44:44.456165  Set Vref, RX VrefLevel [Byte0]: 76

 7973 16:44:44.458973                           [Byte1]: 76

 7974 16:44:44.459557  

 7975 16:44:44.462527  Set Vref, RX VrefLevel [Byte0]: 77

 7976 16:44:44.465522                           [Byte1]: 77

 7977 16:44:44.469015  

 7978 16:44:44.469580  Final RX Vref Byte 0 = 54 to rank0

 7979 16:44:44.471781  Final RX Vref Byte 1 = 61 to rank0

 7980 16:44:44.476112  Final RX Vref Byte 0 = 54 to rank1

 7981 16:44:44.478871  Final RX Vref Byte 1 = 61 to rank1==

 7982 16:44:44.481666  Dram Type= 6, Freq= 0, CH_0, rank 0

 7983 16:44:44.488786  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7984 16:44:44.489379  ==

 7985 16:44:44.489750  DQS Delay:

 7986 16:44:44.491447  DQS0 = 0, DQS1 = 0

 7987 16:44:44.491914  DQM Delay:

 7988 16:44:44.492285  DQM0 = 129, DQM1 = 123

 7989 16:44:44.495122  DQ Delay:

 7990 16:44:44.498462  DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =126

 7991 16:44:44.501934  DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134

 7992 16:44:44.504553  DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120

 7993 16:44:44.508155  DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130

 7994 16:44:44.508625  

 7995 16:44:44.508990  

 7996 16:44:44.509327  

 7997 16:44:44.511018  [DramC_TX_OE_Calibration] TA2

 7998 16:44:44.514913  Original DQ_B0 (3 6) =30, OEN = 27

 7999 16:44:44.517731  Original DQ_B1 (3 6) =30, OEN = 27

 8000 16:44:44.520785  24, 0x0, End_B0=24 End_B1=24

 8001 16:44:44.524547  25, 0x0, End_B0=25 End_B1=25

 8002 16:44:44.525099  26, 0x0, End_B0=26 End_B1=26

 8003 16:44:44.528363  27, 0x0, End_B0=27 End_B1=27

 8004 16:44:44.531444  28, 0x0, End_B0=28 End_B1=28

 8005 16:44:44.534135  29, 0x0, End_B0=29 End_B1=29

 8006 16:44:44.537599  30, 0x0, End_B0=30 End_B1=30

 8007 16:44:44.538175  31, 0x4141, End_B0=30 End_B1=30

 8008 16:44:44.540757  Byte0 end_step=30  best_step=27

 8009 16:44:44.543778  Byte1 end_step=30  best_step=27

 8010 16:44:44.547533  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8011 16:44:44.550678  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8012 16:44:44.551104  

 8013 16:44:44.551469  

 8014 16:44:44.557458  [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps

 8015 16:44:44.560571  CH0 RK0: MR19=303, MR18=1916

 8016 16:44:44.566996  CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15

 8017 16:44:44.567565  

 8018 16:44:44.570634  ----->DramcWriteLeveling(PI) begin...

 8019 16:44:44.571161  ==

 8020 16:44:44.573995  Dram Type= 6, Freq= 0, CH_0, rank 1

 8021 16:44:44.577767  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8022 16:44:44.578311  ==

 8023 16:44:44.580726  Write leveling (Byte 0): 34 => 34

 8024 16:44:44.584034  Write leveling (Byte 1): 26 => 26

 8025 16:44:44.586831  DramcWriteLeveling(PI) end<-----

 8026 16:44:44.587387  

 8027 16:44:44.587723  ==

 8028 16:44:44.590363  Dram Type= 6, Freq= 0, CH_0, rank 1

 8029 16:44:44.596745  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8030 16:44:44.597270  ==

 8031 16:44:44.599846  [Gating] SW mode calibration

 8032 16:44:44.606681  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8033 16:44:44.609707  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8034 16:44:44.616510   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8035 16:44:44.619498   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8036 16:44:44.623226   1  4  8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)

 8037 16:44:44.630053   1  4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 8038 16:44:44.632579   1  4 16 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)

 8039 16:44:44.636115   1  4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 8040 16:44:44.642544   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8041 16:44:44.646638   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8042 16:44:44.649404   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8043 16:44:44.655909   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8044 16:44:44.658926   1  5  8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)

 8045 16:44:44.662315   1  5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)

 8046 16:44:44.669189   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)

 8047 16:44:44.672847   1  5 20 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)

 8048 16:44:44.675855   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8049 16:44:44.682838   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8050 16:44:44.685641   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8051 16:44:44.689075   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8052 16:44:44.695411   1  6  8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)

 8053 16:44:44.699052   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 8054 16:44:44.701804   1  6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)

 8055 16:44:44.708544   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8056 16:44:44.711261   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8057 16:44:44.715147   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8058 16:44:44.721638   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8059 16:44:44.725166   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8060 16:44:44.728111   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8061 16:44:44.734562   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8062 16:44:44.739444   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 8063 16:44:44.741286   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8064 16:44:44.747888   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8065 16:44:44.751084   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8066 16:44:44.754214   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8067 16:44:44.761124   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8068 16:44:44.764086   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8069 16:44:44.767706   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8070 16:44:44.774150   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8071 16:44:44.778042   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8072 16:44:44.780961   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8073 16:44:44.787405   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8074 16:44:44.791079   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8075 16:44:44.794101   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8076 16:44:44.801198   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8077 16:44:44.804083   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 8078 16:44:44.807611  Total UI for P1: 0, mck2ui 16

 8079 16:44:44.810590  best dqsien dly found for B0: ( 1,  9,  6)

 8080 16:44:44.813994   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8081 16:44:44.819987   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8082 16:44:44.823862   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8083 16:44:44.827059  Total UI for P1: 0, mck2ui 16

 8084 16:44:44.830808  best dqsien dly found for B1: ( 1,  9, 18)

 8085 16:44:44.833703  best DQS0 dly(MCK, UI, PI) = (1, 9, 6)

 8086 16:44:44.837429  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 8087 16:44:44.838103  

 8088 16:44:44.840378  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8089 16:44:44.843375  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 8090 16:44:44.846567  [Gating] SW calibration Done

 8091 16:44:44.847043  ==

 8092 16:44:44.850300  Dram Type= 6, Freq= 0, CH_0, rank 1

 8093 16:44:44.856672  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8094 16:44:44.857227  ==

 8095 16:44:44.857571  RX Vref Scan: 0

 8096 16:44:44.857905  

 8097 16:44:44.859697  RX Vref 0 -> 0, step: 1

 8098 16:44:44.860125  

 8099 16:44:44.863736  RX Delay 0 -> 252, step: 8

 8100 16:44:44.866267  iDelay=200, Bit 0, Center 127 (72 ~ 183) 112

 8101 16:44:44.869411  iDelay=200, Bit 1, Center 131 (72 ~ 191) 120

 8102 16:44:44.872903  iDelay=200, Bit 2, Center 127 (72 ~ 183) 112

 8103 16:44:44.876475  iDelay=200, Bit 3, Center 127 (72 ~ 183) 112

 8104 16:44:44.882616  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 8105 16:44:44.885912  iDelay=200, Bit 5, Center 119 (64 ~ 175) 112

 8106 16:44:44.889509  iDelay=200, Bit 6, Center 139 (88 ~ 191) 104

 8107 16:44:44.892869  iDelay=200, Bit 7, Center 139 (80 ~ 199) 120

 8108 16:44:44.899772  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8109 16:44:44.902697  iDelay=200, Bit 9, Center 111 (56 ~ 167) 112

 8110 16:44:44.905678  iDelay=200, Bit 10, Center 127 (72 ~ 183) 112

 8111 16:44:44.908842  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8112 16:44:44.911929  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8113 16:44:44.919246  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8114 16:44:44.922392  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8115 16:44:44.925673  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8116 16:44:44.926207  ==

 8117 16:44:44.929223  Dram Type= 6, Freq= 0, CH_0, rank 1

 8118 16:44:44.931883  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8119 16:44:44.935305  ==

 8120 16:44:44.935729  DQS Delay:

 8121 16:44:44.936064  DQS0 = 0, DQS1 = 0

 8122 16:44:44.938292  DQM Delay:

 8123 16:44:44.938712  DQM0 = 130, DQM1 = 127

 8124 16:44:44.941637  DQ Delay:

 8125 16:44:44.944785  DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127

 8126 16:44:44.948191  DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139

 8127 16:44:44.951622  DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119

 8128 16:44:44.954900  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135

 8129 16:44:44.955400  

 8130 16:44:44.955746  

 8131 16:44:44.956059  ==

 8132 16:44:44.958013  Dram Type= 6, Freq= 0, CH_0, rank 1

 8133 16:44:44.961285  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8134 16:44:44.964672  ==

 8135 16:44:44.965095  

 8136 16:44:44.965423  

 8137 16:44:44.965730  	TX Vref Scan disable

 8138 16:44:44.967865   == TX Byte 0 ==

 8139 16:44:44.971603  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 8140 16:44:44.974609  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 8141 16:44:44.978615   == TX Byte 1 ==

 8142 16:44:44.981434  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8143 16:44:44.987526  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8144 16:44:44.987961  ==

 8145 16:44:44.990794  Dram Type= 6, Freq= 0, CH_0, rank 1

 8146 16:44:44.994273  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8147 16:44:44.994713  ==

 8148 16:44:45.009069  

 8149 16:44:45.012793  TX Vref early break, caculate TX vref

 8150 16:44:45.015498  TX Vref=16, minBit 0, minWin=23, winSum=378

 8151 16:44:45.018657  TX Vref=18, minBit 3, minWin=22, winSum=382

 8152 16:44:45.021732  TX Vref=20, minBit 0, minWin=23, winSum=389

 8153 16:44:45.025327  TX Vref=22, minBit 0, minWin=24, winSum=398

 8154 16:44:45.028501  TX Vref=24, minBit 0, minWin=24, winSum=405

 8155 16:44:45.035663  TX Vref=26, minBit 1, minWin=25, winSum=412

 8156 16:44:45.038209  TX Vref=28, minBit 1, minWin=24, winSum=411

 8157 16:44:45.041895  TX Vref=30, minBit 0, minWin=24, winSum=407

 8158 16:44:45.044832  TX Vref=32, minBit 4, minWin=24, winSum=401

 8159 16:44:45.048306  TX Vref=34, minBit 3, minWin=23, winSum=392

 8160 16:44:45.054581  TX Vref=36, minBit 0, minWin=23, winSum=381

 8161 16:44:45.057776  [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 26

 8162 16:44:45.058204  

 8163 16:44:45.061224  Final TX Range 0 Vref 26

 8164 16:44:45.061649  

 8165 16:44:45.061983  ==

 8166 16:44:45.064675  Dram Type= 6, Freq= 0, CH_0, rank 1

 8167 16:44:45.067907  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8168 16:44:45.071215  ==

 8169 16:44:45.071638  

 8170 16:44:45.071971  

 8171 16:44:45.072277  	TX Vref Scan disable

 8172 16:44:45.077874  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8173 16:44:45.078302   == TX Byte 0 ==

 8174 16:44:45.081148  u2DelayCellOfst[0]=14 cells (4 PI)

 8175 16:44:45.084957  u2DelayCellOfst[1]=17 cells (5 PI)

 8176 16:44:45.088110  u2DelayCellOfst[2]=10 cells (3 PI)

 8177 16:44:45.091241  u2DelayCellOfst[3]=14 cells (4 PI)

 8178 16:44:45.094546  u2DelayCellOfst[4]=7 cells (2 PI)

 8179 16:44:45.097506  u2DelayCellOfst[5]=0 cells (0 PI)

 8180 16:44:45.100967  u2DelayCellOfst[6]=17 cells (5 PI)

 8181 16:44:45.104362  u2DelayCellOfst[7]=17 cells (5 PI)

 8182 16:44:45.107452  Update DQ  dly =988 (3 ,6, 28)  DQ  OEN =(3 ,3)

 8183 16:44:45.111085  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 8184 16:44:45.114514   == TX Byte 1 ==

 8185 16:44:45.117664  u2DelayCellOfst[8]=0 cells (0 PI)

 8186 16:44:45.120782  u2DelayCellOfst[9]=0 cells (0 PI)

 8187 16:44:45.123977  u2DelayCellOfst[10]=3 cells (1 PI)

 8188 16:44:45.127215  u2DelayCellOfst[11]=3 cells (1 PI)

 8189 16:44:45.130826  u2DelayCellOfst[12]=7 cells (2 PI)

 8190 16:44:45.133957  u2DelayCellOfst[13]=10 cells (3 PI)

 8191 16:44:45.137114  u2DelayCellOfst[14]=14 cells (4 PI)

 8192 16:44:45.140661  u2DelayCellOfst[15]=10 cells (3 PI)

 8193 16:44:45.144544  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8194 16:44:45.147052  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8195 16:44:45.150349  DramC Write-DBI on

 8196 16:44:45.150871  ==

 8197 16:44:45.153617  Dram Type= 6, Freq= 0, CH_0, rank 1

 8198 16:44:45.156820  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8199 16:44:45.157345  ==

 8200 16:44:45.157700  

 8201 16:44:45.158054  

 8202 16:44:45.160276  	TX Vref Scan disable

 8203 16:44:45.163652   == TX Byte 0 ==

 8204 16:44:45.166274  Update DQM dly =734 (2 ,6, 30)  DQM OEN =(3 ,3)

 8205 16:44:45.166701   == TX Byte 1 ==

 8206 16:44:45.173354  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8207 16:44:45.173887  DramC Write-DBI off

 8208 16:44:45.174228  

 8209 16:44:45.174536  [DATLAT]

 8210 16:44:45.176425  Freq=1600, CH0 RK1

 8211 16:44:45.176852  

 8212 16:44:45.179640  DATLAT Default: 0xf

 8213 16:44:45.180074  0, 0xFFFF, sum = 0

 8214 16:44:45.183310  1, 0xFFFF, sum = 0

 8215 16:44:45.183785  2, 0xFFFF, sum = 0

 8216 16:44:45.186287  3, 0xFFFF, sum = 0

 8217 16:44:45.186718  4, 0xFFFF, sum = 0

 8218 16:44:45.189390  5, 0xFFFF, sum = 0

 8219 16:44:45.189820  6, 0xFFFF, sum = 0

 8220 16:44:45.192938  7, 0xFFFF, sum = 0

 8221 16:44:45.193472  8, 0xFFFF, sum = 0

 8222 16:44:45.196659  9, 0xFFFF, sum = 0

 8223 16:44:45.197088  10, 0xFFFF, sum = 0

 8224 16:44:45.199706  11, 0xFFFF, sum = 0

 8225 16:44:45.203027  12, 0xFFFF, sum = 0

 8226 16:44:45.203485  13, 0xFFFF, sum = 0

 8227 16:44:45.206421  14, 0x0, sum = 1

 8228 16:44:45.206964  15, 0x0, sum = 2

 8229 16:44:45.207360  16, 0x0, sum = 3

 8230 16:44:45.209399  17, 0x0, sum = 4

 8231 16:44:45.209830  best_step = 15

 8232 16:44:45.210167  

 8233 16:44:45.213212  ==

 8234 16:44:45.213740  Dram Type= 6, Freq= 0, CH_0, rank 1

 8235 16:44:45.219068  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8236 16:44:45.219584  ==

 8237 16:44:45.219930  RX Vref Scan: 0

 8238 16:44:45.220249  

 8239 16:44:45.222576  RX Vref 0 -> 0, step: 1

 8240 16:44:45.223004  

 8241 16:44:45.225910  RX Delay 11 -> 252, step: 4

 8242 16:44:45.230006  iDelay=187, Bit 0, Center 128 (79 ~ 178) 100

 8243 16:44:45.232930  iDelay=187, Bit 1, Center 132 (79 ~ 186) 108

 8244 16:44:45.238878  iDelay=187, Bit 2, Center 124 (71 ~ 178) 108

 8245 16:44:45.241898  iDelay=187, Bit 3, Center 124 (71 ~ 178) 108

 8246 16:44:45.245646  iDelay=187, Bit 4, Center 132 (83 ~ 182) 100

 8247 16:44:45.248770  iDelay=187, Bit 5, Center 118 (63 ~ 174) 112

 8248 16:44:45.252184  iDelay=187, Bit 6, Center 136 (87 ~ 186) 100

 8249 16:44:45.259043  iDelay=187, Bit 7, Center 134 (83 ~ 186) 104

 8250 16:44:45.261984  iDelay=187, Bit 8, Center 114 (63 ~ 166) 104

 8251 16:44:45.265787  iDelay=187, Bit 9, Center 110 (59 ~ 162) 104

 8252 16:44:45.268377  iDelay=187, Bit 10, Center 126 (71 ~ 182) 112

 8253 16:44:45.276359  iDelay=187, Bit 11, Center 118 (67 ~ 170) 104

 8254 16:44:45.278648  iDelay=187, Bit 12, Center 126 (75 ~ 178) 104

 8255 16:44:45.281667  iDelay=187, Bit 13, Center 130 (79 ~ 182) 104

 8256 16:44:45.285117  iDelay=187, Bit 14, Center 134 (83 ~ 186) 104

 8257 16:44:45.288453  iDelay=187, Bit 15, Center 132 (79 ~ 186) 108

 8258 16:44:45.291685  ==

 8259 16:44:45.295064  Dram Type= 6, Freq= 0, CH_0, rank 1

 8260 16:44:45.298599  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8261 16:44:45.299133  ==

 8262 16:44:45.299526  DQS Delay:

 8263 16:44:45.301381  DQS0 = 0, DQS1 = 0

 8264 16:44:45.301819  DQM Delay:

 8265 16:44:45.304917  DQM0 = 128, DQM1 = 123

 8266 16:44:45.305446  DQ Delay:

 8267 16:44:45.308308  DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =124

 8268 16:44:45.311259  DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134

 8269 16:44:45.314741  DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118

 8270 16:44:45.317553  DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132

 8271 16:44:45.318002  

 8272 16:44:45.318368  

 8273 16:44:45.321414  

 8274 16:44:45.321933  [DramC_TX_OE_Calibration] TA2

 8275 16:44:45.324259  Original DQ_B0 (3 6) =30, OEN = 27

 8276 16:44:45.327882  Original DQ_B1 (3 6) =30, OEN = 27

 8277 16:44:45.331108  24, 0x0, End_B0=24 End_B1=24

 8278 16:44:45.334330  25, 0x0, End_B0=25 End_B1=25

 8279 16:44:45.338255  26, 0x0, End_B0=26 End_B1=26

 8280 16:44:45.338784  27, 0x0, End_B0=27 End_B1=27

 8281 16:44:45.341037  28, 0x0, End_B0=28 End_B1=28

 8282 16:44:45.344591  29, 0x0, End_B0=29 End_B1=29

 8283 16:44:45.347639  30, 0x0, End_B0=30 End_B1=30

 8284 16:44:45.351411  31, 0x4141, End_B0=30 End_B1=30

 8285 16:44:45.351933  Byte0 end_step=30  best_step=27

 8286 16:44:45.354070  Byte1 end_step=30  best_step=27

 8287 16:44:45.357660  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8288 16:44:45.361088  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8289 16:44:45.361512  

 8290 16:44:45.361841  

 8291 16:44:45.367723  [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps

 8292 16:44:45.370698  CH0 RK1: MR19=303, MR18=1210

 8293 16:44:45.377579  CH0_RK1: MR19=0x303, MR18=0x1210, DQSOSC=400, MR23=63, INC=23, DEC=15

 8294 16:44:45.381191  [RxdqsGatingPostProcess] freq 1600

 8295 16:44:45.387455  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8296 16:44:45.390673  best DQS0 dly(2T, 0.5T) = (1, 1)

 8297 16:44:45.393830  best DQS1 dly(2T, 0.5T) = (1, 1)

 8298 16:44:45.397526  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8299 16:44:45.398063  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8300 16:44:45.400178  best DQS0 dly(2T, 0.5T) = (1, 1)

 8301 16:44:45.403337  best DQS1 dly(2T, 0.5T) = (1, 1)

 8302 16:44:45.407284  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8303 16:44:45.410037  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8304 16:44:45.413365  Pre-setting of DQS Precalculation

 8305 16:44:45.420327  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8306 16:44:45.420852  ==

 8307 16:44:45.423166  Dram Type= 6, Freq= 0, CH_1, rank 0

 8308 16:44:45.426688  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8309 16:44:45.427112  ==

 8310 16:44:45.434445  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8311 16:44:45.436563  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8312 16:44:45.439999  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8313 16:44:45.446726  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8314 16:44:45.455422  [CA 0] Center 42 (12~72) winsize 61

 8315 16:44:45.458815  [CA 1] Center 42 (13~72) winsize 60

 8316 16:44:45.461638  [CA 2] Center 38 (9~67) winsize 59

 8317 16:44:45.465313  [CA 3] Center 36 (7~66) winsize 60

 8318 16:44:45.468484  [CA 4] Center 38 (8~68) winsize 61

 8319 16:44:45.471615  [CA 5] Center 36 (7~66) winsize 60

 8320 16:44:45.472158  

 8321 16:44:45.475022  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8322 16:44:45.475524  

 8323 16:44:45.478697  [CATrainingPosCal] consider 1 rank data

 8324 16:44:45.481923  u2DelayCellTimex100 = 275/100 ps

 8325 16:44:45.488375  CA0 delay=42 (12~72),Diff = 6 PI (21 cell)

 8326 16:44:45.491144  CA1 delay=42 (13~72),Diff = 6 PI (21 cell)

 8327 16:44:45.494846  CA2 delay=38 (9~67),Diff = 2 PI (7 cell)

 8328 16:44:45.498563  CA3 delay=36 (7~66),Diff = 0 PI (0 cell)

 8329 16:44:45.501380  CA4 delay=38 (8~68),Diff = 2 PI (7 cell)

 8330 16:44:45.504763  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8331 16:44:45.505336  

 8332 16:44:45.507670  CA PerBit enable=1, Macro0, CA PI delay=36

 8333 16:44:45.508122  

 8334 16:44:45.511509  [CBTSetCACLKResult] CA Dly = 36

 8335 16:44:45.514752  CS Dly: 8 (0~39)

 8336 16:44:45.517923  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8337 16:44:45.521192  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8338 16:44:45.521720  ==

 8339 16:44:45.524386  Dram Type= 6, Freq= 0, CH_1, rank 1

 8340 16:44:45.530824  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8341 16:44:45.531398  ==

 8342 16:44:45.534027  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8343 16:44:45.540530  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8344 16:44:45.544106  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8345 16:44:45.551256  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8346 16:44:45.559143  [CA 0] Center 42 (12~72) winsize 61

 8347 16:44:45.562219  [CA 1] Center 42 (13~72) winsize 60

 8348 16:44:45.565264  [CA 2] Center 38 (8~68) winsize 61

 8349 16:44:45.568810  [CA 3] Center 37 (7~67) winsize 61

 8350 16:44:45.571024  [CA 4] Center 37 (8~67) winsize 60

 8351 16:44:45.575065  [CA 5] Center 37 (7~67) winsize 61

 8352 16:44:45.575682  

 8353 16:44:45.578187  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8354 16:44:45.578751  

 8355 16:44:45.584854  [CATrainingPosCal] consider 2 rank data

 8356 16:44:45.585621  u2DelayCellTimex100 = 275/100 ps

 8357 16:44:45.591137  CA0 delay=42 (12~72),Diff = 6 PI (21 cell)

 8358 16:44:45.594401  CA1 delay=42 (13~72),Diff = 6 PI (21 cell)

 8359 16:44:45.597909  CA2 delay=38 (9~67),Diff = 2 PI (7 cell)

 8360 16:44:45.601005  CA3 delay=36 (7~66),Diff = 0 PI (0 cell)

 8361 16:44:45.604540  CA4 delay=37 (8~67),Diff = 1 PI (3 cell)

 8362 16:44:45.607668  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8363 16:44:45.608074  

 8364 16:44:45.610826  CA PerBit enable=1, Macro0, CA PI delay=36

 8365 16:44:45.611268  

 8366 16:44:45.614186  [CBTSetCACLKResult] CA Dly = 36

 8367 16:44:45.617489  CS Dly: 9 (0~42)

 8368 16:44:45.620531  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8369 16:44:45.624122  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8370 16:44:45.624632  

 8371 16:44:45.627606  ----->DramcWriteLeveling(PI) begin...

 8372 16:44:45.628057  ==

 8373 16:44:45.630492  Dram Type= 6, Freq= 0, CH_1, rank 0

 8374 16:44:45.637752  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8375 16:44:45.638274  ==

 8376 16:44:45.640637  Write leveling (Byte 0): 26 => 26

 8377 16:44:45.643368  Write leveling (Byte 1): 25 => 25

 8378 16:44:45.647067  DramcWriteLeveling(PI) end<-----

 8379 16:44:45.647525  

 8380 16:44:45.647853  ==

 8381 16:44:45.650638  Dram Type= 6, Freq= 0, CH_1, rank 0

 8382 16:44:45.654354  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8383 16:44:45.654869  ==

 8384 16:44:45.657321  [Gating] SW mode calibration

 8385 16:44:45.663610  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8386 16:44:45.669997  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8387 16:44:45.673371   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8388 16:44:45.677024   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8389 16:44:45.683680   1  4  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8390 16:44:45.686542   1  4 12 | B1->B0 | 2424 3333 | 0 1 | (1 1) (1 1)

 8391 16:44:45.690051   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8392 16:44:45.696348   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8393 16:44:45.699681   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8394 16:44:45.703224   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8395 16:44:45.709431   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8396 16:44:45.712785   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8397 16:44:45.716140   1  5  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 8398 16:44:45.722943   1  5 12 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)

 8399 16:44:45.726049   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8400 16:44:45.729154   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8401 16:44:45.736073   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8402 16:44:45.739253   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8403 16:44:45.742953   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8404 16:44:45.749063   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8405 16:44:45.752170   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8406 16:44:45.756218   1  6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)

 8407 16:44:45.762215   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8408 16:44:45.765776   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8409 16:44:45.769142   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8410 16:44:45.775364   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8411 16:44:45.779263   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8412 16:44:45.781986   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8413 16:44:45.788870   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8414 16:44:45.791885   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8415 16:44:45.795025   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8416 16:44:45.801970   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8417 16:44:45.805036   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8418 16:44:45.808296   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8419 16:44:45.814843   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8420 16:44:45.818011   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8421 16:44:45.821305   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8422 16:44:45.828180   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8423 16:44:45.831261   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8424 16:44:45.834802   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8425 16:44:45.841164   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8426 16:44:45.844477   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8427 16:44:45.847680   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8428 16:44:45.854506   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8429 16:44:45.857915   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8430 16:44:45.861381   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8431 16:44:45.867795   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8432 16:44:45.868348  Total UI for P1: 0, mck2ui 16

 8433 16:44:45.874315  best dqsien dly found for B0: ( 1,  9, 10)

 8434 16:44:45.877488   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8435 16:44:45.880674  Total UI for P1: 0, mck2ui 16

 8436 16:44:45.883853  best dqsien dly found for B1: ( 1,  9, 14)

 8437 16:44:45.887222  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8438 16:44:45.890548  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8439 16:44:45.891065  

 8440 16:44:45.894190  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8441 16:44:45.897292  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8442 16:44:45.900529  [Gating] SW calibration Done

 8443 16:44:45.901055  ==

 8444 16:44:45.903630  Dram Type= 6, Freq= 0, CH_1, rank 0

 8445 16:44:45.910278  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8446 16:44:45.910806  ==

 8447 16:44:45.911207  RX Vref Scan: 0

 8448 16:44:45.911685  

 8449 16:44:45.913402  RX Vref 0 -> 0, step: 1

 8450 16:44:45.913873  

 8451 16:44:45.916638  RX Delay 0 -> 252, step: 8

 8452 16:44:45.920475  iDelay=200, Bit 0, Center 139 (88 ~ 191) 104

 8453 16:44:45.923726  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8454 16:44:45.926733  iDelay=200, Bit 2, Center 123 (64 ~ 183) 120

 8455 16:44:45.930219  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8456 16:44:45.936421  iDelay=200, Bit 4, Center 127 (72 ~ 183) 112

 8457 16:44:45.940082  iDelay=200, Bit 5, Center 143 (88 ~ 199) 112

 8458 16:44:45.943348  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8459 16:44:45.946554  iDelay=200, Bit 7, Center 127 (72 ~ 183) 112

 8460 16:44:45.953184  iDelay=200, Bit 8, Center 115 (64 ~ 167) 104

 8461 16:44:45.956071  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8462 16:44:45.959799  iDelay=200, Bit 10, Center 127 (72 ~ 183) 112

 8463 16:44:45.962769  iDelay=200, Bit 11, Center 123 (64 ~ 183) 120

 8464 16:44:45.966279  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8465 16:44:45.973241  iDelay=200, Bit 13, Center 143 (88 ~ 199) 112

 8466 16:44:45.975906  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8467 16:44:45.979619  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8468 16:44:45.980184  ==

 8469 16:44:45.982745  Dram Type= 6, Freq= 0, CH_1, rank 0

 8470 16:44:45.986419  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8471 16:44:45.989058  ==

 8472 16:44:45.989643  DQS Delay:

 8473 16:44:45.990020  DQS0 = 0, DQS1 = 0

 8474 16:44:45.992360  DQM Delay:

 8475 16:44:45.992922  DQM0 = 134, DQM1 = 129

 8476 16:44:45.995626  DQ Delay:

 8477 16:44:45.998905  DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135

 8478 16:44:46.002195  DQ4 =127, DQ5 =143, DQ6 =147, DQ7 =127

 8479 16:44:46.006000  DQ8 =115, DQ9 =119, DQ10 =127, DQ11 =123

 8480 16:44:46.008601  DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135

 8481 16:44:46.009075  

 8482 16:44:46.009447  

 8483 16:44:46.009791  ==

 8484 16:44:46.012214  Dram Type= 6, Freq= 0, CH_1, rank 0

 8485 16:44:46.015622  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8486 16:44:46.018820  ==

 8487 16:44:46.019322  

 8488 16:44:46.019697  

 8489 16:44:46.020044  	TX Vref Scan disable

 8490 16:44:46.021799   == TX Byte 0 ==

 8491 16:44:46.024928  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8492 16:44:46.028508  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8493 16:44:46.031679   == TX Byte 1 ==

 8494 16:44:46.035445  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8495 16:44:46.039077  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8496 16:44:46.041354  ==

 8497 16:44:46.045132  Dram Type= 6, Freq= 0, CH_1, rank 0

 8498 16:44:46.048093  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8499 16:44:46.048614  ==

 8500 16:44:46.061820  

 8501 16:44:46.064685  TX Vref early break, caculate TX vref

 8502 16:44:46.067899  TX Vref=16, minBit 8, minWin=21, winSum=366

 8503 16:44:46.072125  TX Vref=18, minBit 8, minWin=22, winSum=377

 8504 16:44:46.074454  TX Vref=20, minBit 8, minWin=23, winSum=385

 8505 16:44:46.078177  TX Vref=22, minBit 8, minWin=23, winSum=392

 8506 16:44:46.081069  TX Vref=24, minBit 8, minWin=24, winSum=408

 8507 16:44:46.087521  TX Vref=26, minBit 1, minWin=25, winSum=414

 8508 16:44:46.091104  TX Vref=28, minBit 0, minWin=26, winSum=420

 8509 16:44:46.094093  TX Vref=30, minBit 0, minWin=25, winSum=417

 8510 16:44:46.097594  TX Vref=32, minBit 15, minWin=24, winSum=409

 8511 16:44:46.101414  TX Vref=34, minBit 0, minWin=24, winSum=399

 8512 16:44:46.107322  TX Vref=36, minBit 9, minWin=22, winSum=385

 8513 16:44:46.110307  [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 28

 8514 16:44:46.110822  

 8515 16:44:46.113629  Final TX Range 0 Vref 28

 8516 16:44:46.114081  

 8517 16:44:46.114447  ==

 8518 16:44:46.116964  Dram Type= 6, Freq= 0, CH_1, rank 0

 8519 16:44:46.123780  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8520 16:44:46.124236  ==

 8521 16:44:46.124579  

 8522 16:44:46.124894  

 8523 16:44:46.125196  	TX Vref Scan disable

 8524 16:44:46.130150  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8525 16:44:46.130600   == TX Byte 0 ==

 8526 16:44:46.133694  u2DelayCellOfst[0]=17 cells (5 PI)

 8527 16:44:46.137253  u2DelayCellOfst[1]=10 cells (3 PI)

 8528 16:44:46.140655  u2DelayCellOfst[2]=0 cells (0 PI)

 8529 16:44:46.143510  u2DelayCellOfst[3]=7 cells (2 PI)

 8530 16:44:46.147098  u2DelayCellOfst[4]=7 cells (2 PI)

 8531 16:44:46.150226  u2DelayCellOfst[5]=17 cells (5 PI)

 8532 16:44:46.153607  u2DelayCellOfst[6]=17 cells (5 PI)

 8533 16:44:46.157262  u2DelayCellOfst[7]=7 cells (2 PI)

 8534 16:44:46.160348  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8535 16:44:46.163674  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8536 16:44:46.167274   == TX Byte 1 ==

 8537 16:44:46.170158  u2DelayCellOfst[8]=0 cells (0 PI)

 8538 16:44:46.173377  u2DelayCellOfst[9]=3 cells (1 PI)

 8539 16:44:46.176715  u2DelayCellOfst[10]=10 cells (3 PI)

 8540 16:44:46.180733  u2DelayCellOfst[11]=7 cells (2 PI)

 8541 16:44:46.183523  u2DelayCellOfst[12]=14 cells (4 PI)

 8542 16:44:46.186635  u2DelayCellOfst[13]=14 cells (4 PI)

 8543 16:44:46.190193  u2DelayCellOfst[14]=17 cells (5 PI)

 8544 16:44:46.190721  u2DelayCellOfst[15]=17 cells (5 PI)

 8545 16:44:46.196269  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8546 16:44:46.199853  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8547 16:44:46.203400  DramC Write-DBI on

 8548 16:44:46.203955  ==

 8549 16:44:46.206842  Dram Type= 6, Freq= 0, CH_1, rank 0

 8550 16:44:46.209917  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8551 16:44:46.210487  ==

 8552 16:44:46.210854  

 8553 16:44:46.211238  

 8554 16:44:46.213235  	TX Vref Scan disable

 8555 16:44:46.213717   == TX Byte 0 ==

 8556 16:44:46.219888  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 8557 16:44:46.220310   == TX Byte 1 ==

 8558 16:44:46.225941  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8559 16:44:46.226377  DramC Write-DBI off

 8560 16:44:46.226710  

 8561 16:44:46.227013  [DATLAT]

 8562 16:44:46.229273  Freq=1600, CH1 RK0

 8563 16:44:46.229689  

 8564 16:44:46.232922  DATLAT Default: 0xf

 8565 16:44:46.233338  0, 0xFFFF, sum = 0

 8566 16:44:46.236101  1, 0xFFFF, sum = 0

 8567 16:44:46.236524  2, 0xFFFF, sum = 0

 8568 16:44:46.238815  3, 0xFFFF, sum = 0

 8569 16:44:46.239258  4, 0xFFFF, sum = 0

 8570 16:44:46.242474  5, 0xFFFF, sum = 0

 8571 16:44:46.242998  6, 0xFFFF, sum = 0

 8572 16:44:46.246121  7, 0xFFFF, sum = 0

 8573 16:44:46.246672  8, 0xFFFF, sum = 0

 8574 16:44:46.248962  9, 0xFFFF, sum = 0

 8575 16:44:46.249389  10, 0xFFFF, sum = 0

 8576 16:44:46.252693  11, 0xFFFF, sum = 0

 8577 16:44:46.253230  12, 0xFFFF, sum = 0

 8578 16:44:46.255838  13, 0xFFFF, sum = 0

 8579 16:44:46.256338  14, 0x0, sum = 1

 8580 16:44:46.259103  15, 0x0, sum = 2

 8581 16:44:46.259564  16, 0x0, sum = 3

 8582 16:44:46.262404  17, 0x0, sum = 4

 8583 16:44:46.262831  best_step = 15

 8584 16:44:46.263165  

 8585 16:44:46.263528  ==

 8586 16:44:46.266049  Dram Type= 6, Freq= 0, CH_1, rank 0

 8587 16:44:46.272042  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8588 16:44:46.272471  ==

 8589 16:44:46.272807  RX Vref Scan: 1

 8590 16:44:46.273117  

 8591 16:44:46.275470  Set Vref Range= 24 -> 127

 8592 16:44:46.275894  

 8593 16:44:46.278541  RX Vref 24 -> 127, step: 1

 8594 16:44:46.278961  

 8595 16:44:46.282090  RX Delay 19 -> 252, step: 4

 8596 16:44:46.282612  

 8597 16:44:46.285198  Set Vref, RX VrefLevel [Byte0]: 24

 8598 16:44:46.285621                           [Byte1]: 24

 8599 16:44:46.289472  

 8600 16:44:46.293005  Set Vref, RX VrefLevel [Byte0]: 25

 8601 16:44:46.296316                           [Byte1]: 25

 8602 16:44:46.296837  

 8603 16:44:46.299676  Set Vref, RX VrefLevel [Byte0]: 26

 8604 16:44:46.302762                           [Byte1]: 26

 8605 16:44:46.303212  

 8606 16:44:46.306082  Set Vref, RX VrefLevel [Byte0]: 27

 8607 16:44:46.309303                           [Byte1]: 27

 8608 16:44:46.309727  

 8609 16:44:46.312882  Set Vref, RX VrefLevel [Byte0]: 28

 8610 16:44:46.316658                           [Byte1]: 28

 8611 16:44:46.319901  

 8612 16:44:46.320325  Set Vref, RX VrefLevel [Byte0]: 29

 8613 16:44:46.323668                           [Byte1]: 29

 8614 16:44:46.327821  

 8615 16:44:46.328243  Set Vref, RX VrefLevel [Byte0]: 30

 8616 16:44:46.331079                           [Byte1]: 30

 8617 16:44:46.335356  

 8618 16:44:46.335781  Set Vref, RX VrefLevel [Byte0]: 31

 8619 16:44:46.338144                           [Byte1]: 31

 8620 16:44:46.342764  

 8621 16:44:46.343208  Set Vref, RX VrefLevel [Byte0]: 32

 8622 16:44:46.346561                           [Byte1]: 32

 8623 16:44:46.350056  

 8624 16:44:46.350588  Set Vref, RX VrefLevel [Byte0]: 33

 8625 16:44:46.353849                           [Byte1]: 33

 8626 16:44:46.357867  

 8627 16:44:46.358314  Set Vref, RX VrefLevel [Byte0]: 34

 8628 16:44:46.361036                           [Byte1]: 34

 8629 16:44:46.365641  

 8630 16:44:46.366205  Set Vref, RX VrefLevel [Byte0]: 35

 8631 16:44:46.368875                           [Byte1]: 35

 8632 16:44:46.373164  

 8633 16:44:46.373601  Set Vref, RX VrefLevel [Byte0]: 36

 8634 16:44:46.375941                           [Byte1]: 36

 8635 16:44:46.380761  

 8636 16:44:46.381482  Set Vref, RX VrefLevel [Byte0]: 37

 8637 16:44:46.383943                           [Byte1]: 37

 8638 16:44:46.388423  

 8639 16:44:46.388954  Set Vref, RX VrefLevel [Byte0]: 38

 8640 16:44:46.391207                           [Byte1]: 38

 8641 16:44:46.395535  

 8642 16:44:46.395961  Set Vref, RX VrefLevel [Byte0]: 39

 8643 16:44:46.398881                           [Byte1]: 39

 8644 16:44:46.403771  

 8645 16:44:46.404317  Set Vref, RX VrefLevel [Byte0]: 40

 8646 16:44:46.406669                           [Byte1]: 40

 8647 16:44:46.410614  

 8648 16:44:46.411044  Set Vref, RX VrefLevel [Byte0]: 41

 8649 16:44:46.414195                           [Byte1]: 41

 8650 16:44:46.418618  

 8651 16:44:46.419218  Set Vref, RX VrefLevel [Byte0]: 42

 8652 16:44:46.422112                           [Byte1]: 42

 8653 16:44:46.426065  

 8654 16:44:46.426617  Set Vref, RX VrefLevel [Byte0]: 43

 8655 16:44:46.429822                           [Byte1]: 43

 8656 16:44:46.433744  

 8657 16:44:46.434175  Set Vref, RX VrefLevel [Byte0]: 44

 8658 16:44:46.437070                           [Byte1]: 44

 8659 16:44:46.441237  

 8660 16:44:46.441674  Set Vref, RX VrefLevel [Byte0]: 45

 8661 16:44:46.445180                           [Byte1]: 45

 8662 16:44:46.448447  

 8663 16:44:46.448874  Set Vref, RX VrefLevel [Byte0]: 46

 8664 16:44:46.452032                           [Byte1]: 46

 8665 16:44:46.456082  

 8666 16:44:46.456520  Set Vref, RX VrefLevel [Byte0]: 47

 8667 16:44:46.459631                           [Byte1]: 47

 8668 16:44:46.463811  

 8669 16:44:46.464235  Set Vref, RX VrefLevel [Byte0]: 48

 8670 16:44:46.467076                           [Byte1]: 48

 8671 16:44:46.471648  

 8672 16:44:46.472080  Set Vref, RX VrefLevel [Byte0]: 49

 8673 16:44:46.474659                           [Byte1]: 49

 8674 16:44:46.479021  

 8675 16:44:46.479472  Set Vref, RX VrefLevel [Byte0]: 50

 8676 16:44:46.482469                           [Byte1]: 50

 8677 16:44:46.486787  

 8678 16:44:46.487238  Set Vref, RX VrefLevel [Byte0]: 51

 8679 16:44:46.489771                           [Byte1]: 51

 8680 16:44:46.494124  

 8681 16:44:46.494652  Set Vref, RX VrefLevel [Byte0]: 52

 8682 16:44:46.497454                           [Byte1]: 52

 8683 16:44:46.501494  

 8684 16:44:46.501921  Set Vref, RX VrefLevel [Byte0]: 53

 8685 16:44:46.504906                           [Byte1]: 53

 8686 16:44:46.509438  

 8687 16:44:46.509862  Set Vref, RX VrefLevel [Byte0]: 54

 8688 16:44:46.512430                           [Byte1]: 54

 8689 16:44:46.516852  

 8690 16:44:46.517371  Set Vref, RX VrefLevel [Byte0]: 55

 8691 16:44:46.519833                           [Byte1]: 55

 8692 16:44:46.524419  

 8693 16:44:46.524847  Set Vref, RX VrefLevel [Byte0]: 56

 8694 16:44:46.527551                           [Byte1]: 56

 8695 16:44:46.532186  

 8696 16:44:46.532701  Set Vref, RX VrefLevel [Byte0]: 57

 8697 16:44:46.535554                           [Byte1]: 57

 8698 16:44:46.539657  

 8699 16:44:46.540177  Set Vref, RX VrefLevel [Byte0]: 58

 8700 16:44:46.543239                           [Byte1]: 58

 8701 16:44:46.547360  

 8702 16:44:46.547871  Set Vref, RX VrefLevel [Byte0]: 59

 8703 16:44:46.550250                           [Byte1]: 59

 8704 16:44:46.554564  

 8705 16:44:46.555157  Set Vref, RX VrefLevel [Byte0]: 60

 8706 16:44:46.557838                           [Byte1]: 60

 8707 16:44:46.562053  

 8708 16:44:46.562510  Set Vref, RX VrefLevel [Byte0]: 61

 8709 16:44:46.565879                           [Byte1]: 61

 8710 16:44:46.569776  

 8711 16:44:46.570217  Set Vref, RX VrefLevel [Byte0]: 62

 8712 16:44:46.573492                           [Byte1]: 62

 8713 16:44:46.577336  

 8714 16:44:46.577920  Set Vref, RX VrefLevel [Byte0]: 63

 8715 16:44:46.580618                           [Byte1]: 63

 8716 16:44:46.585204  

 8717 16:44:46.585654  Set Vref, RX VrefLevel [Byte0]: 64

 8718 16:44:46.588216                           [Byte1]: 64

 8719 16:44:46.592511  

 8720 16:44:46.593155  Set Vref, RX VrefLevel [Byte0]: 65

 8721 16:44:46.596102                           [Byte1]: 65

 8722 16:44:46.600184  

 8723 16:44:46.600703  Set Vref, RX VrefLevel [Byte0]: 66

 8724 16:44:46.603422                           [Byte1]: 66

 8725 16:44:46.608098  

 8726 16:44:46.608614  Set Vref, RX VrefLevel [Byte0]: 67

 8727 16:44:46.610939                           [Byte1]: 67

 8728 16:44:46.615627  

 8729 16:44:46.616095  Set Vref, RX VrefLevel [Byte0]: 68

 8730 16:44:46.618451                           [Byte1]: 68

 8731 16:44:46.622741  

 8732 16:44:46.623169  Set Vref, RX VrefLevel [Byte0]: 69

 8733 16:44:46.626088                           [Byte1]: 69

 8734 16:44:46.631023  

 8735 16:44:46.631608  Set Vref, RX VrefLevel [Byte0]: 70

 8736 16:44:46.633816                           [Byte1]: 70

 8737 16:44:46.638248  

 8738 16:44:46.638818  Final RX Vref Byte 0 = 58 to rank0

 8739 16:44:46.641847  Final RX Vref Byte 1 = 57 to rank0

 8740 16:44:46.644711  Final RX Vref Byte 0 = 58 to rank1

 8741 16:44:46.647838  Final RX Vref Byte 1 = 57 to rank1==

 8742 16:44:46.651201  Dram Type= 6, Freq= 0, CH_1, rank 0

 8743 16:44:46.657821  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8744 16:44:46.658346  ==

 8745 16:44:46.658684  DQS Delay:

 8746 16:44:46.661081  DQS0 = 0, DQS1 = 0

 8747 16:44:46.661636  DQM Delay:

 8748 16:44:46.664654  DQM0 = 131, DQM1 = 127

 8749 16:44:46.665148  DQ Delay:

 8750 16:44:46.667831  DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =130

 8751 16:44:46.670936  DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126

 8752 16:44:46.674013  DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =122

 8753 16:44:46.677561  DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138

 8754 16:44:46.677987  

 8755 16:44:46.678320  

 8756 16:44:46.678660  

 8757 16:44:46.680629  [DramC_TX_OE_Calibration] TA2

 8758 16:44:46.683881  Original DQ_B0 (3 6) =30, OEN = 27

 8759 16:44:46.687277  Original DQ_B1 (3 6) =30, OEN = 27

 8760 16:44:46.690308  24, 0x0, End_B0=24 End_B1=24

 8761 16:44:46.694239  25, 0x0, End_B0=25 End_B1=25

 8762 16:44:46.694674  26, 0x0, End_B0=26 End_B1=26

 8763 16:44:46.697086  27, 0x0, End_B0=27 End_B1=27

 8764 16:44:46.700441  28, 0x0, End_B0=28 End_B1=28

 8765 16:44:46.703601  29, 0x0, End_B0=29 End_B1=29

 8766 16:44:46.707646  30, 0x0, End_B0=30 End_B1=30

 8767 16:44:46.708078  31, 0x4141, End_B0=30 End_B1=30

 8768 16:44:46.710141  Byte0 end_step=30  best_step=27

 8769 16:44:46.713947  Byte1 end_step=30  best_step=27

 8770 16:44:46.716769  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8771 16:44:46.720139  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8772 16:44:46.720589  

 8773 16:44:46.720938  

 8774 16:44:46.726588  [DQSOSCAuto] RK0, (LSB)MR18= 0xc15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 403 ps

 8775 16:44:46.730236  CH1 RK0: MR19=303, MR18=C15

 8776 16:44:46.737004  CH1_RK0: MR19=0x303, MR18=0xC15, DQSOSC=399, MR23=63, INC=23, DEC=15

 8777 16:44:46.737657  

 8778 16:44:46.740067  ----->DramcWriteLeveling(PI) begin...

 8779 16:44:46.740527  ==

 8780 16:44:46.742925  Dram Type= 6, Freq= 0, CH_1, rank 1

 8781 16:44:46.747108  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8782 16:44:46.747579  ==

 8783 16:44:46.749920  Write leveling (Byte 0): 24 => 24

 8784 16:44:46.753223  Write leveling (Byte 1): 25 => 25

 8785 16:44:46.756035  DramcWriteLeveling(PI) end<-----

 8786 16:44:46.756459  

 8787 16:44:46.756790  ==

 8788 16:44:46.759308  Dram Type= 6, Freq= 0, CH_1, rank 1

 8789 16:44:46.766359  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8790 16:44:46.766799  ==

 8791 16:44:46.767132  [Gating] SW mode calibration

 8792 16:44:46.776216  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8793 16:44:46.779599  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8794 16:44:46.785803   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8795 16:44:46.789249   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8796 16:44:46.792664   1  4  8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)

 8797 16:44:46.799912   1  4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)

 8798 16:44:46.802168   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8799 16:44:46.805370   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8800 16:44:46.811972   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8801 16:44:46.815126   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8802 16:44:46.818874   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8803 16:44:46.825284   1  5  4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 8804 16:44:46.828935   1  5  8 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)

 8805 16:44:46.832708   1  5 12 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)

 8806 16:44:46.839119   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8807 16:44:46.842279   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8808 16:44:46.845080   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8809 16:44:46.852025   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8810 16:44:46.854884   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8811 16:44:46.858436   1  6  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8812 16:44:46.865368   1  6  8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 8813 16:44:46.868001   1  6 12 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)

 8814 16:44:46.871333   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8815 16:44:46.878667   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8816 16:44:46.881581   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8817 16:44:46.884883   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8818 16:44:46.891339   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8819 16:44:46.894478   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8820 16:44:46.897670   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8821 16:44:46.904277   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8822 16:44:46.907665   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8823 16:44:46.910887   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8824 16:44:46.917289   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8825 16:44:46.920859   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8826 16:44:46.924446   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8827 16:44:46.930980   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8828 16:44:46.934012   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8829 16:44:46.937821   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8830 16:44:46.944041   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8831 16:44:46.947211   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8832 16:44:46.950554   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8833 16:44:46.956940   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8834 16:44:46.960136   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8835 16:44:46.963913   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8836 16:44:46.970149   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8837 16:44:46.974003   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8838 16:44:46.976931  Total UI for P1: 0, mck2ui 16

 8839 16:44:46.979817  best dqsien dly found for B0: ( 1,  9,  6)

 8840 16:44:46.983503   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8841 16:44:46.986313  Total UI for P1: 0, mck2ui 16

 8842 16:44:46.990001  best dqsien dly found for B1: ( 1,  9, 10)

 8843 16:44:46.993285  best DQS0 dly(MCK, UI, PI) = (1, 9, 6)

 8844 16:44:46.996319  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8845 16:44:46.996750  

 8846 16:44:47.002757  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8847 16:44:47.006408  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8848 16:44:47.006838  [Gating] SW calibration Done

 8849 16:44:47.010077  ==

 8850 16:44:47.013071  Dram Type= 6, Freq= 0, CH_1, rank 1

 8851 16:44:47.016346  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8852 16:44:47.016874  ==

 8853 16:44:47.017215  RX Vref Scan: 0

 8854 16:44:47.017534  

 8855 16:44:47.019741  RX Vref 0 -> 0, step: 1

 8856 16:44:47.020166  

 8857 16:44:47.022584  RX Delay 0 -> 252, step: 8

 8858 16:44:47.026280  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8859 16:44:47.030052  iDelay=200, Bit 1, Center 131 (72 ~ 191) 120

 8860 16:44:47.033006  iDelay=200, Bit 2, Center 119 (64 ~ 175) 112

 8861 16:44:47.039324  iDelay=200, Bit 3, Center 131 (72 ~ 191) 120

 8862 16:44:47.043491  iDelay=200, Bit 4, Center 131 (72 ~ 191) 120

 8863 16:44:47.046208  iDelay=200, Bit 5, Center 143 (88 ~ 199) 112

 8864 16:44:47.049607  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8865 16:44:47.053282  iDelay=200, Bit 7, Center 135 (80 ~ 191) 112

 8866 16:44:47.059274  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 8867 16:44:47.062636  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8868 16:44:47.065524  iDelay=200, Bit 10, Center 131 (72 ~ 191) 120

 8869 16:44:47.069337  iDelay=200, Bit 11, Center 123 (64 ~ 183) 120

 8870 16:44:47.075670  iDelay=200, Bit 12, Center 139 (80 ~ 199) 120

 8871 16:44:47.079250  iDelay=200, Bit 13, Center 139 (80 ~ 199) 120

 8872 16:44:47.082017  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8873 16:44:47.085278  iDelay=200, Bit 15, Center 139 (80 ~ 199) 120

 8874 16:44:47.085872  ==

 8875 16:44:47.088441  Dram Type= 6, Freq= 0, CH_1, rank 1

 8876 16:44:47.095142  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8877 16:44:47.095597  ==

 8878 16:44:47.095927  DQS Delay:

 8879 16:44:47.098397  DQS0 = 0, DQS1 = 0

 8880 16:44:47.098909  DQM Delay:

 8881 16:44:47.102038  DQM0 = 133, DQM1 = 130

 8882 16:44:47.102599  DQ Delay:

 8883 16:44:47.105056  DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131

 8884 16:44:47.108417  DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =135

 8885 16:44:47.111871  DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123

 8886 16:44:47.114759  DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139

 8887 16:44:47.115210  

 8888 16:44:47.115550  

 8889 16:44:47.115856  ==

 8890 16:44:47.118443  Dram Type= 6, Freq= 0, CH_1, rank 1

 8891 16:44:47.124768  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8892 16:44:47.125300  ==

 8893 16:44:47.125640  

 8894 16:44:47.125952  

 8895 16:44:47.126251  	TX Vref Scan disable

 8896 16:44:47.128305   == TX Byte 0 ==

 8897 16:44:47.131571  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8898 16:44:47.137968  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8899 16:44:47.138497   == TX Byte 1 ==

 8900 16:44:47.142393  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8901 16:44:47.148032  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8902 16:44:47.148567  ==

 8903 16:44:47.151353  Dram Type= 6, Freq= 0, CH_1, rank 1

 8904 16:44:47.154585  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8905 16:44:47.155159  ==

 8906 16:44:47.167965  

 8907 16:44:47.171291  TX Vref early break, caculate TX vref

 8908 16:44:47.174957  TX Vref=16, minBit 9, minWin=22, winSum=379

 8909 16:44:47.177888  TX Vref=18, minBit 9, minWin=22, winSum=388

 8910 16:44:47.181333  TX Vref=20, minBit 9, minWin=22, winSum=394

 8911 16:44:47.184477  TX Vref=22, minBit 9, minWin=23, winSum=399

 8912 16:44:47.187968  TX Vref=24, minBit 9, minWin=23, winSum=408

 8913 16:44:47.194628  TX Vref=26, minBit 9, minWin=24, winSum=413

 8914 16:44:47.197455  TX Vref=28, minBit 9, minWin=24, winSum=419

 8915 16:44:47.200801  TX Vref=30, minBit 0, minWin=25, winSum=417

 8916 16:44:47.204455  TX Vref=32, minBit 0, minWin=25, winSum=412

 8917 16:44:47.207355  TX Vref=34, minBit 0, minWin=24, winSum=402

 8918 16:44:47.214104  TX Vref=36, minBit 9, minWin=23, winSum=392

 8919 16:44:47.217614  [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 30

 8920 16:44:47.218209  

 8921 16:44:47.220461  Final TX Range 0 Vref 30

 8922 16:44:47.221024  

 8923 16:44:47.221397  ==

 8924 16:44:47.223688  Dram Type= 6, Freq= 0, CH_1, rank 1

 8925 16:44:47.226902  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8926 16:44:47.230549  ==

 8927 16:44:47.230978  

 8928 16:44:47.231346  

 8929 16:44:47.231704  	TX Vref Scan disable

 8930 16:44:47.237205  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8931 16:44:47.237725   == TX Byte 0 ==

 8932 16:44:47.240693  u2DelayCellOfst[0]=14 cells (4 PI)

 8933 16:44:47.243757  u2DelayCellOfst[1]=10 cells (3 PI)

 8934 16:44:47.246984  u2DelayCellOfst[2]=0 cells (0 PI)

 8935 16:44:47.250884  u2DelayCellOfst[3]=7 cells (2 PI)

 8936 16:44:47.254058  u2DelayCellOfst[4]=7 cells (2 PI)

 8937 16:44:47.257650  u2DelayCellOfst[5]=17 cells (5 PI)

 8938 16:44:47.260258  u2DelayCellOfst[6]=17 cells (5 PI)

 8939 16:44:47.264052  u2DelayCellOfst[7]=7 cells (2 PI)

 8940 16:44:47.266753  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8941 16:44:47.270375  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8942 16:44:47.273485   == TX Byte 1 ==

 8943 16:44:47.276783  u2DelayCellOfst[8]=0 cells (0 PI)

 8944 16:44:47.279738  u2DelayCellOfst[9]=7 cells (2 PI)

 8945 16:44:47.283060  u2DelayCellOfst[10]=14 cells (4 PI)

 8946 16:44:47.286432  u2DelayCellOfst[11]=7 cells (2 PI)

 8947 16:44:47.289887  u2DelayCellOfst[12]=17 cells (5 PI)

 8948 16:44:47.292871  u2DelayCellOfst[13]=17 cells (5 PI)

 8949 16:44:47.296518  u2DelayCellOfst[14]=21 cells (6 PI)

 8950 16:44:47.299795  u2DelayCellOfst[15]=21 cells (6 PI)

 8951 16:44:47.303078  Update DQ  dly =977 (3 ,6, 17)  DQ  OEN =(3 ,3)

 8952 16:44:47.305893  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8953 16:44:47.309364  DramC Write-DBI on

 8954 16:44:47.309911  ==

 8955 16:44:47.312546  Dram Type= 6, Freq= 0, CH_1, rank 1

 8956 16:44:47.316022  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8957 16:44:47.316452  ==

 8958 16:44:47.316786  

 8959 16:44:47.317093  

 8960 16:44:47.319857  	TX Vref Scan disable

 8961 16:44:47.320280   == TX Byte 0 ==

 8962 16:44:47.326120  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8963 16:44:47.326673   == TX Byte 1 ==

 8964 16:44:47.332830  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8965 16:44:47.333368  DramC Write-DBI off

 8966 16:44:47.333706  

 8967 16:44:47.334018  [DATLAT]

 8968 16:44:47.335988  Freq=1600, CH1 RK1

 8969 16:44:47.336412  

 8970 16:44:47.338922  DATLAT Default: 0xf

 8971 16:44:47.339505  0, 0xFFFF, sum = 0

 8972 16:44:47.342324  1, 0xFFFF, sum = 0

 8973 16:44:47.342760  2, 0xFFFF, sum = 0

 8974 16:44:47.345355  3, 0xFFFF, sum = 0

 8975 16:44:47.345787  4, 0xFFFF, sum = 0

 8976 16:44:47.348738  5, 0xFFFF, sum = 0

 8977 16:44:47.349172  6, 0xFFFF, sum = 0

 8978 16:44:47.352028  7, 0xFFFF, sum = 0

 8979 16:44:47.352462  8, 0xFFFF, sum = 0

 8980 16:44:47.356061  9, 0xFFFF, sum = 0

 8981 16:44:47.356597  10, 0xFFFF, sum = 0

 8982 16:44:47.359079  11, 0xFFFF, sum = 0

 8983 16:44:47.359645  12, 0xFFFF, sum = 0

 8984 16:44:47.361909  13, 0xFFFF, sum = 0

 8985 16:44:47.362341  14, 0x0, sum = 1

 8986 16:44:47.365691  15, 0x0, sum = 2

 8987 16:44:47.366299  16, 0x0, sum = 3

 8988 16:44:47.368935  17, 0x0, sum = 4

 8989 16:44:47.369473  best_step = 15

 8990 16:44:47.369815  

 8991 16:44:47.370128  ==

 8992 16:44:47.372320  Dram Type= 6, Freq= 0, CH_1, rank 1

 8993 16:44:47.378471  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8994 16:44:47.379009  ==

 8995 16:44:47.379395  RX Vref Scan: 0

 8996 16:44:47.379718  

 8997 16:44:47.381566  RX Vref 0 -> 0, step: 1

 8998 16:44:47.382132  

 8999 16:44:47.385621  RX Delay 11 -> 252, step: 4

 9000 16:44:47.388206  iDelay=195, Bit 0, Center 134 (83 ~ 186) 104

 9001 16:44:47.391796  iDelay=195, Bit 1, Center 130 (79 ~ 182) 104

 9002 16:44:47.398618  iDelay=195, Bit 2, Center 120 (67 ~ 174) 108

 9003 16:44:47.401357  iDelay=195, Bit 3, Center 128 (75 ~ 182) 108

 9004 16:44:47.404993  iDelay=195, Bit 4, Center 130 (75 ~ 186) 112

 9005 16:44:47.408285  iDelay=195, Bit 5, Center 142 (91 ~ 194) 104

 9006 16:44:47.411572  iDelay=195, Bit 6, Center 140 (87 ~ 194) 108

 9007 16:44:47.418248  iDelay=195, Bit 7, Center 130 (79 ~ 182) 104

 9008 16:44:47.421936  iDelay=195, Bit 8, Center 114 (59 ~ 170) 112

 9009 16:44:47.425026  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 9010 16:44:47.427946  iDelay=195, Bit 10, Center 128 (75 ~ 182) 108

 9011 16:44:47.432066  iDelay=195, Bit 11, Center 122 (67 ~ 178) 112

 9012 16:44:47.438271  iDelay=195, Bit 12, Center 138 (87 ~ 190) 104

 9013 16:44:47.441173  iDelay=195, Bit 13, Center 134 (83 ~ 186) 104

 9014 16:44:47.444503  iDelay=195, Bit 14, Center 132 (79 ~ 186) 108

 9015 16:44:47.448279  iDelay=195, Bit 15, Center 136 (83 ~ 190) 108

 9016 16:44:47.448704  ==

 9017 16:44:47.451044  Dram Type= 6, Freq= 0, CH_1, rank 1

 9018 16:44:47.457729  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9019 16:44:47.458315  ==

 9020 16:44:47.458662  DQS Delay:

 9021 16:44:47.461571  DQS0 = 0, DQS1 = 0

 9022 16:44:47.462099  DQM Delay:

 9023 16:44:47.464517  DQM0 = 131, DQM1 = 127

 9024 16:44:47.465050  DQ Delay:

 9025 16:44:47.468505  DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128

 9026 16:44:47.471602  DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =130

 9027 16:44:47.474917  DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =122

 9028 16:44:47.477478  DQ12 =138, DQ13 =134, DQ14 =132, DQ15 =136

 9029 16:44:47.478047  

 9030 16:44:47.478414  

 9031 16:44:47.478755  

 9032 16:44:47.480653  [DramC_TX_OE_Calibration] TA2

 9033 16:44:47.483899  Original DQ_B0 (3 6) =30, OEN = 27

 9034 16:44:47.487844  Original DQ_B1 (3 6) =30, OEN = 27

 9035 16:44:47.490332  24, 0x0, End_B0=24 End_B1=24

 9036 16:44:47.494297  25, 0x0, End_B0=25 End_B1=25

 9037 16:44:47.494877  26, 0x0, End_B0=26 End_B1=26

 9038 16:44:47.497281  27, 0x0, End_B0=27 End_B1=27

 9039 16:44:47.501218  28, 0x0, End_B0=28 End_B1=28

 9040 16:44:47.503717  29, 0x0, End_B0=29 End_B1=29

 9041 16:44:47.507103  30, 0x0, End_B0=30 End_B1=30

 9042 16:44:47.507611  31, 0x4141, End_B0=30 End_B1=30

 9043 16:44:47.510414  Byte0 end_step=30  best_step=27

 9044 16:44:47.513356  Byte1 end_step=30  best_step=27

 9045 16:44:47.516699  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9046 16:44:47.520041  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9047 16:44:47.520467  

 9048 16:44:47.520798  

 9049 16:44:47.526750  [DQSOSCAuto] RK1, (LSB)MR18= 0xc1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps

 9050 16:44:47.529886  CH1 RK1: MR19=303, MR18=C1B

 9051 16:44:47.536940  CH1_RK1: MR19=0x303, MR18=0xC1B, DQSOSC=396, MR23=63, INC=23, DEC=15

 9052 16:44:47.539887  [RxdqsGatingPostProcess] freq 1600

 9053 16:44:47.546246  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9054 16:44:47.546692  best DQS0 dly(2T, 0.5T) = (1, 1)

 9055 16:44:47.550099  best DQS1 dly(2T, 0.5T) = (1, 1)

 9056 16:44:47.553285  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9057 16:44:47.556715  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9058 16:44:47.559699  best DQS0 dly(2T, 0.5T) = (1, 1)

 9059 16:44:47.562998  best DQS1 dly(2T, 0.5T) = (1, 1)

 9060 16:44:47.566929  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9061 16:44:47.569705  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9062 16:44:47.572742  Pre-setting of DQS Precalculation

 9063 16:44:47.576109  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9064 16:44:47.586206  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9065 16:44:47.592291  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9066 16:44:47.592846  

 9067 16:44:47.593321  

 9068 16:44:47.596278  [Calibration Summary] 3200 Mbps

 9069 16:44:47.596703  CH 0, Rank 0

 9070 16:44:47.599083  SW Impedance     : PASS

 9071 16:44:47.602691  DUTY Scan        : NO K

 9072 16:44:47.603263  ZQ Calibration   : PASS

 9073 16:44:47.606672  Jitter Meter     : NO K

 9074 16:44:47.607287  CBT Training     : PASS

 9075 16:44:47.609089  Write leveling   : PASS

 9076 16:44:47.611969  RX DQS gating    : PASS

 9077 16:44:47.612394  RX DQ/DQS(RDDQC) : PASS

 9078 16:44:47.615796  TX DQ/DQS        : PASS

 9079 16:44:47.618933  RX DATLAT        : PASS

 9080 16:44:47.619388  RX DQ/DQS(Engine): PASS

 9081 16:44:47.621857  TX OE            : PASS

 9082 16:44:47.622317  All Pass.

 9083 16:44:47.622846  

 9084 16:44:47.625406  CH 0, Rank 1

 9085 16:44:47.625824  SW Impedance     : PASS

 9086 16:44:47.628680  DUTY Scan        : NO K

 9087 16:44:47.632698  ZQ Calibration   : PASS

 9088 16:44:47.633134  Jitter Meter     : NO K

 9089 16:44:47.635219  CBT Training     : PASS

 9090 16:44:47.638821  Write leveling   : PASS

 9091 16:44:47.639272  RX DQS gating    : PASS

 9092 16:44:47.641575  RX DQ/DQS(RDDQC) : PASS

 9093 16:44:47.645314  TX DQ/DQS        : PASS

 9094 16:44:47.645735  RX DATLAT        : PASS

 9095 16:44:47.648698  RX DQ/DQS(Engine): PASS

 9096 16:44:47.651577  TX OE            : PASS

 9097 16:44:47.652149  All Pass.

 9098 16:44:47.652599  

 9099 16:44:47.653133  CH 1, Rank 0

 9100 16:44:47.654876  SW Impedance     : PASS

 9101 16:44:47.658535  DUTY Scan        : NO K

 9102 16:44:47.658954  ZQ Calibration   : PASS

 9103 16:44:47.661248  Jitter Meter     : NO K

 9104 16:44:47.664676  CBT Training     : PASS

 9105 16:44:47.665224  Write leveling   : PASS

 9106 16:44:47.668140  RX DQS gating    : PASS

 9107 16:44:47.671274  RX DQ/DQS(RDDQC) : PASS

 9108 16:44:47.671716  TX DQ/DQS        : PASS

 9109 16:44:47.675011  RX DATLAT        : PASS

 9110 16:44:47.677837  RX DQ/DQS(Engine): PASS

 9111 16:44:47.678261  TX OE            : PASS

 9112 16:44:47.680851  All Pass.

 9113 16:44:47.681268  

 9114 16:44:47.681597  CH 1, Rank 1

 9115 16:44:47.684408  SW Impedance     : PASS

 9116 16:44:47.684826  DUTY Scan        : NO K

 9117 16:44:47.687433  ZQ Calibration   : PASS

 9118 16:44:47.691202  Jitter Meter     : NO K

 9119 16:44:47.691663  CBT Training     : PASS

 9120 16:44:47.694652  Write leveling   : PASS

 9121 16:44:47.697859  RX DQS gating    : PASS

 9122 16:44:47.698386  RX DQ/DQS(RDDQC) : PASS

 9123 16:44:47.701213  TX DQ/DQS        : PASS

 9124 16:44:47.703855  RX DATLAT        : PASS

 9125 16:44:47.704273  RX DQ/DQS(Engine): PASS

 9126 16:44:47.707093  TX OE            : PASS

 9127 16:44:47.707542  All Pass.

 9128 16:44:47.707872  

 9129 16:44:47.710817  DramC Write-DBI on

 9130 16:44:47.713810  	PER_BANK_REFRESH: Hybrid Mode

 9131 16:44:47.714229  TX_TRACKING: ON

 9132 16:44:47.723808  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9133 16:44:47.730523  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9134 16:44:47.737082  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9135 16:44:47.741065  [FAST_K] Save calibration result to emmc

 9136 16:44:47.743758  sync common calibartion params.

 9137 16:44:47.746673  sync cbt_mode0:1, 1:1

 9138 16:44:47.750373  dram_init: ddr_geometry: 2

 9139 16:44:47.750882  dram_init: ddr_geometry: 2

 9140 16:44:47.753692  dram_init: ddr_geometry: 2

 9141 16:44:47.756877  0:dram_rank_size:100000000

 9142 16:44:47.760106  1:dram_rank_size:100000000

 9143 16:44:47.763290  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9144 16:44:47.767004  DFS_SHUFFLE_HW_MODE: ON

 9145 16:44:47.769834  dramc_set_vcore_voltage set vcore to 725000

 9146 16:44:47.773401  Read voltage for 1600, 0

 9147 16:44:47.773944  Vio18 = 0

 9148 16:44:47.774285  Vcore = 725000

 9149 16:44:47.777371  Vdram = 0

 9150 16:44:47.777923  Vddq = 0

 9151 16:44:47.778266  Vmddr = 0

 9152 16:44:47.779746  switch to 3200 Mbps bootup

 9153 16:44:47.783270  [DramcRunTimeConfig]

 9154 16:44:47.783934  PHYPLL

 9155 16:44:47.784330  DPM_CONTROL_AFTERK: ON

 9156 16:44:47.786484  PER_BANK_REFRESH: ON

 9157 16:44:47.790119  REFRESH_OVERHEAD_REDUCTION: ON

 9158 16:44:47.790560  CMD_PICG_NEW_MODE: OFF

 9159 16:44:47.793191  XRTWTW_NEW_MODE: ON

 9160 16:44:47.796835  XRTRTR_NEW_MODE: ON

 9161 16:44:47.797362  TX_TRACKING: ON

 9162 16:44:47.800011  RDSEL_TRACKING: OFF

 9163 16:44:47.800432  DQS Precalculation for DVFS: ON

 9164 16:44:47.803264  RX_TRACKING: OFF

 9165 16:44:47.803678  HW_GATING DBG: ON

 9166 16:44:47.806095  ZQCS_ENABLE_LP4: ON

 9167 16:44:47.809484  RX_PICG_NEW_MODE: ON

 9168 16:44:47.809902  TX_PICG_NEW_MODE: ON

 9169 16:44:47.812499  ENABLE_RX_DCM_DPHY: ON

 9170 16:44:47.815730  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9171 16:44:47.816150  DUMMY_READ_FOR_TRACKING: OFF

 9172 16:44:47.819252  !!! SPM_CONTROL_AFTERK: OFF

 9173 16:44:47.822779  !!! SPM could not control APHY

 9174 16:44:47.826033  IMPEDANCE_TRACKING: ON

 9175 16:44:47.826456  TEMP_SENSOR: ON

 9176 16:44:47.829012  HW_SAVE_FOR_SR: OFF

 9177 16:44:47.832662  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9178 16:44:47.835595  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9179 16:44:47.836115  Read ODT Tracking: ON

 9180 16:44:47.838914  Refresh Rate DeBounce: ON

 9181 16:44:47.842707  DFS_NO_QUEUE_FLUSH: ON

 9182 16:44:47.845563  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9183 16:44:47.845982  ENABLE_DFS_RUNTIME_MRW: OFF

 9184 16:44:47.848743  DDR_RESERVE_NEW_MODE: ON

 9185 16:44:47.851898  MR_CBT_SWITCH_FREQ: ON

 9186 16:44:47.852317  =========================

 9187 16:44:47.872610  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9188 16:44:47.875381  dram_init: ddr_geometry: 2

 9189 16:44:47.894041  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9190 16:44:47.897699  dram_init: dram init end (result: 0)

 9191 16:44:47.903700  DRAM-K: Full calibration passed in 24433 msecs

 9192 16:44:47.907251  MRC: failed to locate region type 0.

 9193 16:44:47.907813  DRAM rank0 size:0x100000000,

 9194 16:44:47.910979  DRAM rank1 size=0x100000000

 9195 16:44:47.920401  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9196 16:44:47.927465  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9197 16:44:47.933331  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9198 16:44:47.943372  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9199 16:44:47.943797  DRAM rank0 size:0x100000000,

 9200 16:44:47.946875  DRAM rank1 size=0x100000000

 9201 16:44:47.947517  CBMEM:

 9202 16:44:47.949658  IMD: root @ 0xfffff000 254 entries.

 9203 16:44:47.953153  IMD: root @ 0xffffec00 62 entries.

 9204 16:44:47.959642  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9205 16:44:47.962987  WARNING: RO_VPD is uninitialized or empty.

 9206 16:44:47.966452  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9207 16:44:47.973917  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9208 16:44:47.986799  read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps

 9209 16:44:47.998261  BS: romstage times (exec / console): total (unknown) / 23960 ms

 9210 16:44:47.998909  

 9211 16:44:47.999341  

 9212 16:44:48.008011  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9213 16:44:48.011630  ARM64: Exception handlers installed.

 9214 16:44:48.014445  ARM64: Testing exception

 9215 16:44:48.017506  ARM64: Done test exception

 9216 16:44:48.017923  Enumerating buses...

 9217 16:44:48.021118  Show all devs... Before device enumeration.

 9218 16:44:48.024146  Root Device: enabled 1

 9219 16:44:48.027536  CPU_CLUSTER: 0: enabled 1

 9220 16:44:48.027955  CPU: 00: enabled 1

 9221 16:44:48.030652  Compare with tree...

 9222 16:44:48.031070  Root Device: enabled 1

 9223 16:44:48.034730   CPU_CLUSTER: 0: enabled 1

 9224 16:44:48.038084    CPU: 00: enabled 1

 9225 16:44:48.038606  Root Device scanning...

 9226 16:44:48.040930  scan_static_bus for Root Device

 9227 16:44:48.044018  CPU_CLUSTER: 0 enabled

 9228 16:44:48.047448  scan_static_bus for Root Device done

 9229 16:44:48.050916  scan_bus: bus Root Device finished in 8 msecs

 9230 16:44:48.051483  done

 9231 16:44:48.057190  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9232 16:44:48.060566  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9233 16:44:48.067604  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9234 16:44:48.073768  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9235 16:44:48.074202  Allocating resources...

 9236 16:44:48.076683  Reading resources...

 9237 16:44:48.080200  Root Device read_resources bus 0 link: 0

 9238 16:44:48.084181  DRAM rank0 size:0x100000000,

 9239 16:44:48.084838  DRAM rank1 size=0x100000000

 9240 16:44:48.089943  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9241 16:44:48.090364  CPU: 00 missing read_resources

 9242 16:44:48.096936  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9243 16:44:48.100359  Root Device read_resources bus 0 link: 0 done

 9244 16:44:48.103008  Done reading resources.

 9245 16:44:48.106872  Show resources in subtree (Root Device)...After reading.

 9246 16:44:48.109734   Root Device child on link 0 CPU_CLUSTER: 0

 9247 16:44:48.113650    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9248 16:44:48.122842    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9249 16:44:48.123554     CPU: 00

 9250 16:44:48.129547  Root Device assign_resources, bus 0 link: 0

 9251 16:44:48.133102  CPU_CLUSTER: 0 missing set_resources

 9252 16:44:48.136090  Root Device assign_resources, bus 0 link: 0 done

 9253 16:44:48.139519  Done setting resources.

 9254 16:44:48.142877  Show resources in subtree (Root Device)...After assigning values.

 9255 16:44:48.146129   Root Device child on link 0 CPU_CLUSTER: 0

 9256 16:44:48.152812    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9257 16:44:48.159352    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9258 16:44:48.162350     CPU: 00

 9259 16:44:48.162768  Done allocating resources.

 9260 16:44:48.169067  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9261 16:44:48.172046  Enabling resources...

 9262 16:44:48.172542  done.

 9263 16:44:48.175641  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9264 16:44:48.179260  Initializing devices...

 9265 16:44:48.179779  Root Device init

 9266 16:44:48.182316  init hardware done!

 9267 16:44:48.185305  0x00000018: ctrlr->caps

 9268 16:44:48.185807  52.000 MHz: ctrlr->f_max

 9269 16:44:48.188632  0.400 MHz: ctrlr->f_min

 9270 16:44:48.192187  0x40ff8080: ctrlr->voltages

 9271 16:44:48.192632  sclk: 390625

 9272 16:44:48.192968  Bus Width = 1

 9273 16:44:48.195808  sclk: 390625

 9274 16:44:48.196228  Bus Width = 1

 9275 16:44:48.198464  Early init status = 3

 9276 16:44:48.201792  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9277 16:44:48.205466  in-header: 03 fc 00 00 01 00 00 00 

 9278 16:44:48.208951  in-data: 00 

 9279 16:44:48.212218  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9280 16:44:48.216750  in-header: 03 fd 00 00 00 00 00 00 

 9281 16:44:48.220373  in-data: 

 9282 16:44:48.223159  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9283 16:44:48.227331  in-header: 03 fc 00 00 01 00 00 00 

 9284 16:44:48.230811  in-data: 00 

 9285 16:44:48.233668  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9286 16:44:48.238388  in-header: 03 fd 00 00 00 00 00 00 

 9287 16:44:48.241953  in-data: 

 9288 16:44:48.245335  [SSUSB] Setting up USB HOST controller...

 9289 16:44:48.248188  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9290 16:44:48.251668  [SSUSB] phy power-on done.

 9291 16:44:48.254567  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9292 16:44:48.261342  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9293 16:44:48.264863  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9294 16:44:48.271667  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9295 16:44:48.277890  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9296 16:44:48.284410  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9297 16:44:48.290867  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9298 16:44:48.297613  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9299 16:44:48.301507  SPM: binary array size = 0x9dc

 9300 16:44:48.304178  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9301 16:44:48.310881  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9302 16:44:48.317757  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9303 16:44:48.323826  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9304 16:44:48.327407  configure_display: Starting display init

 9305 16:44:48.361915  anx7625_power_on_init: Init interface.

 9306 16:44:48.364742  anx7625_disable_pd_protocol: Disabled PD feature.

 9307 16:44:48.368148  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9308 16:44:48.396349  anx7625_start_dp_work: Secure OCM version=00

 9309 16:44:48.399298  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9310 16:44:48.414038  sp_tx_get_edid_block: EDID Block = 1

 9311 16:44:48.516603  Extracted contents:

 9312 16:44:48.519609  header:          00 ff ff ff ff ff ff 00

 9313 16:44:48.522911  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9314 16:44:48.526351  version:         01 04

 9315 16:44:48.529839  basic params:    95 1f 11 78 0a

 9316 16:44:48.533259  chroma info:     76 90 94 55 54 90 27 21 50 54

 9317 16:44:48.536654  established:     00 00 00

 9318 16:44:48.543025  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9319 16:44:48.546617  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9320 16:44:48.553187  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9321 16:44:48.559826  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9322 16:44:48.566488  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9323 16:44:48.569545  extensions:      00

 9324 16:44:48.569969  checksum:        fb

 9325 16:44:48.570295  

 9326 16:44:48.573489  Manufacturer: IVO Model 57d Serial Number 0

 9327 16:44:48.576107  Made week 0 of 2020

 9328 16:44:48.576618  EDID version: 1.4

 9329 16:44:48.580260  Digital display

 9330 16:44:48.582750  6 bits per primary color channel

 9331 16:44:48.583253  DisplayPort interface

 9332 16:44:48.586279  Maximum image size: 31 cm x 17 cm

 9333 16:44:48.589261  Gamma: 220%

 9334 16:44:48.589678  Check DPMS levels

 9335 16:44:48.592774  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9336 16:44:48.598974  First detailed timing is preferred timing

 9337 16:44:48.599441  Established timings supported:

 9338 16:44:48.602525  Standard timings supported:

 9339 16:44:48.605532  Detailed timings

 9340 16:44:48.609062  Hex of detail: 383680a07038204018303c0035ae10000019

 9341 16:44:48.615526  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9342 16:44:48.618996                 0780 0798 07c8 0820 hborder 0

 9343 16:44:48.622179                 0438 043b 0447 0458 vborder 0

 9344 16:44:48.625311                 -hsync -vsync

 9345 16:44:48.625730  Did detailed timing

 9346 16:44:48.632305  Hex of detail: 000000000000000000000000000000000000

 9347 16:44:48.635494  Manufacturer-specified data, tag 0

 9348 16:44:48.638755  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9349 16:44:48.641965  ASCII string: InfoVision

 9350 16:44:48.644970  Hex of detail: 000000fe00523134304e574635205248200a

 9351 16:44:48.648439  ASCII string: R140NWF5 RH 

 9352 16:44:48.648858  Checksum

 9353 16:44:48.651573  Checksum: 0xfb (valid)

 9354 16:44:48.655690  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9355 16:44:48.658284  DSI data_rate: 832800000 bps

 9356 16:44:48.664821  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9357 16:44:48.668426  anx7625_parse_edid: pixelclock(138800).

 9358 16:44:48.671636   hactive(1920), hsync(48), hfp(24), hbp(88)

 9359 16:44:48.674736   vactive(1080), vsync(12), vfp(3), vbp(17)

 9360 16:44:48.678110  anx7625_dsi_config: config dsi.

 9361 16:44:48.684745  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9362 16:44:48.698624  anx7625_dsi_config: success to config DSI

 9363 16:44:48.702044  anx7625_dp_start: MIPI phy setup OK.

 9364 16:44:48.705132  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9365 16:44:48.708478  mtk_ddp_mode_set invalid vrefresh 60

 9366 16:44:48.711450  main_disp_path_setup

 9367 16:44:48.711857  ovl_layer_smi_id_en

 9368 16:44:48.715057  ovl_layer_smi_id_en

 9369 16:44:48.715500  ccorr_config

 9370 16:44:48.715818  aal_config

 9371 16:44:48.718196  gamma_config

 9372 16:44:48.718605  postmask_config

 9373 16:44:48.721124  dither_config

 9374 16:44:48.724542  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9375 16:44:48.731337                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9376 16:44:48.734343  Root Device init finished in 551 msecs

 9377 16:44:48.737977  CPU_CLUSTER: 0 init

 9378 16:44:48.745174  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9379 16:44:48.751034  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9380 16:44:48.751471  APU_MBOX 0x190000b0 = 0x10001

 9381 16:44:48.754477  APU_MBOX 0x190001b0 = 0x10001

 9382 16:44:48.757892  APU_MBOX 0x190005b0 = 0x10001

 9383 16:44:48.760943  APU_MBOX 0x190006b0 = 0x10001

 9384 16:44:48.767449  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9385 16:44:48.778061  read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps

 9386 16:44:48.790083  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9387 16:44:48.796656  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9388 16:44:48.808129  read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps

 9389 16:44:48.817315  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9390 16:44:48.820607  CPU_CLUSTER: 0 init finished in 81 msecs

 9391 16:44:48.824118  Devices initialized

 9392 16:44:48.827079  Show all devs... After init.

 9393 16:44:48.827573  Root Device: enabled 1

 9394 16:44:48.830275  CPU_CLUSTER: 0: enabled 1

 9395 16:44:48.833736  CPU: 00: enabled 1

 9396 16:44:48.837462  BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms

 9397 16:44:48.840689  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9398 16:44:48.844023  ELOG: NV offset 0x57f000 size 0x1000

 9399 16:44:48.850835  read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps

 9400 16:44:48.857002  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9401 16:44:48.860415  ELOG: Event(17) added with size 13 at 2023-06-03 16:44:49 UTC

 9402 16:44:48.867167  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9403 16:44:48.870271  in-header: 03 28 00 00 2c 00 00 00 

 9404 16:44:48.879847  in-data: 37 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9405 16:44:48.886940  ELOG: Event(A1) added with size 10 at 2023-06-03 16:44:49 UTC

 9406 16:44:48.893329  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9407 16:44:48.900087  ELOG: Event(A0) added with size 9 at 2023-06-03 16:44:49 UTC

 9408 16:44:48.903869  elog_add_boot_reason: Logged dev mode boot

 9409 16:44:48.909797  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9410 16:44:48.910335  Finalize devices...

 9411 16:44:48.913134  Devices finalized

 9412 16:44:48.916585  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9413 16:44:48.919723  Writing coreboot table at 0xffe64000

 9414 16:44:48.922938   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9415 16:44:48.929909   1. 0000000040000000-00000000400fffff: RAM

 9416 16:44:48.933130   2. 0000000040100000-000000004032afff: RAMSTAGE

 9417 16:44:48.936422   3. 000000004032b000-00000000545fffff: RAM

 9418 16:44:48.939454   4. 0000000054600000-000000005465ffff: BL31

 9419 16:44:48.942672   5. 0000000054660000-00000000ffe63fff: RAM

 9420 16:44:48.949553   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9421 16:44:48.952521   7. 0000000100000000-000000023fffffff: RAM

 9422 16:44:48.956154  Passing 5 GPIOs to payload:

 9423 16:44:48.959698              NAME |       PORT | POLARITY |     VALUE

 9424 16:44:48.965976          EC in RW | 0x000000aa |      low | undefined

 9425 16:44:48.968924      EC interrupt | 0x00000005 |      low | undefined

 9426 16:44:48.972307     TPM interrupt | 0x000000ab |     high | undefined

 9427 16:44:48.978987    SD card detect | 0x00000011 |     high | undefined

 9428 16:44:48.982235    speaker enable | 0x00000093 |     high | undefined

 9429 16:44:48.985478  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9430 16:44:48.989707  in-header: 03 f9 00 00 02 00 00 00 

 9431 16:44:48.993093  in-data: 02 00 

 9432 16:44:48.996587  ADC[4]: Raw value=902216 ID=7

 9433 16:44:48.999487  ADC[3]: Raw value=213546 ID=1

 9434 16:44:48.999915  RAM Code: 0x71

 9435 16:44:49.003548  ADC[6]: Raw value=75000 ID=0

 9436 16:44:49.007030  ADC[5]: Raw value=213546 ID=1

 9437 16:44:49.007503  SKU Code: 0x1

 9438 16:44:49.013285  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a53a

 9439 16:44:49.013826  coreboot table: 964 bytes.

 9440 16:44:49.016636  IMD ROOT    0. 0xfffff000 0x00001000

 9441 16:44:49.019522  IMD SMALL   1. 0xffffe000 0x00001000

 9442 16:44:49.022962  RO MCACHE   2. 0xffffc000 0x00001104

 9443 16:44:49.026112  CONSOLE     3. 0xfff7c000 0x00080000

 9444 16:44:49.029317  FMAP        4. 0xfff7b000 0x00000452

 9445 16:44:49.032549  TIME STAMP  5. 0xfff7a000 0x00000910

 9446 16:44:49.036311  VBOOT WORK  6. 0xfff66000 0x00014000

 9447 16:44:49.039300  RAMOOPS     7. 0xffe66000 0x00100000

 9448 16:44:49.042298  COREBOOT    8. 0xffe64000 0x00002000

 9449 16:44:49.045706  IMD small region:

 9450 16:44:49.048769    IMD ROOT    0. 0xffffec00 0x00000400

 9451 16:44:49.052261    VPD         1. 0xffffeba0 0x0000004c

 9452 16:44:49.055610    MMC STATUS  2. 0xffffeb80 0x00000004

 9453 16:44:49.062333  BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms

 9454 16:44:49.062857  Probing TPM:  done!

 9455 16:44:49.069673  Connected to device vid:did:rid of 1ae0:0028:00

 9456 16:44:49.075727  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523

 9457 16:44:49.079333  Initialized TPM device CR50 revision 0

 9458 16:44:49.083620  Checking cr50 for pending updates

 9459 16:44:49.088240  Reading cr50 TPM mode

 9460 16:44:49.096473  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9461 16:44:49.103210  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9462 16:44:49.143678  read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps

 9463 16:44:49.146639  Checking segment from ROM address 0x40100000

 9464 16:44:49.149935  Checking segment from ROM address 0x4010001c

 9465 16:44:49.156516  Loading segment from ROM address 0x40100000

 9466 16:44:49.156987    code (compression=0)

 9467 16:44:49.166573    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9468 16:44:49.173343  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9469 16:44:49.173873  it's not compressed!

 9470 16:44:49.179513  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9471 16:44:49.186539  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9472 16:44:49.204117  Loading segment from ROM address 0x4010001c

 9473 16:44:49.204686    Entry Point 0x80000000

 9474 16:44:49.206964  Loaded segments

 9475 16:44:49.210962  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9476 16:44:49.217168  Jumping to boot code at 0x80000000(0xffe64000)

 9477 16:44:49.223316  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9478 16:44:49.230108  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9479 16:44:49.238014  read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps

 9480 16:44:49.241178  Checking segment from ROM address 0x40100000

 9481 16:44:49.244398  Checking segment from ROM address 0x4010001c

 9482 16:44:49.251609  Loading segment from ROM address 0x40100000

 9483 16:44:49.252236    code (compression=1)

 9484 16:44:49.257921    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9485 16:44:49.267602  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9486 16:44:49.268166  using LZMA

 9487 16:44:49.276142  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9488 16:44:49.283127  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9489 16:44:49.286192  Loading segment from ROM address 0x4010001c

 9490 16:44:49.286629    Entry Point 0x54601000

 9491 16:44:49.290316  Loaded segments

 9492 16:44:49.293019  NOTICE:  MT8192 bl31_setup

 9493 16:44:49.300252  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9494 16:44:49.303301  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9495 16:44:49.306643  WARNING: region 0:

 9496 16:44:49.310269  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9497 16:44:49.310794  WARNING: region 1:

 9498 16:44:49.316982  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9499 16:44:49.319785  WARNING: region 2:

 9500 16:44:49.323101  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9501 16:44:49.326767  WARNING: region 3:

 9502 16:44:49.329602  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9503 16:44:49.332985  WARNING: region 4:

 9504 16:44:49.339688  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9505 16:44:49.340115  WARNING: region 5:

 9506 16:44:49.343643  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9507 16:44:49.346169  WARNING: region 6:

 9508 16:44:49.349664  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9509 16:44:49.353130  WARNING: region 7:

 9510 16:44:49.356444  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9511 16:44:49.362872  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9512 16:44:49.366660  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9513 16:44:49.370013  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9514 16:44:49.376590  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9515 16:44:49.379514  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9516 16:44:49.382874  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9517 16:44:49.390171  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9518 16:44:49.392675  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9519 16:44:49.399671  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9520 16:44:49.402837  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9521 16:44:49.406085  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9522 16:44:49.413096  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9523 16:44:49.416049  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9524 16:44:49.419344  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9525 16:44:49.426071  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9526 16:44:49.429182  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9527 16:44:49.435925  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9528 16:44:49.439311  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9529 16:44:49.443221  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9530 16:44:49.449255  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9531 16:44:49.452522  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9532 16:44:49.459063  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9533 16:44:49.462243  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9534 16:44:49.465501  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9535 16:44:49.472714  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9536 16:44:49.475810  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9537 16:44:49.482725  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9538 16:44:49.485688  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9539 16:44:49.489042  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9540 16:44:49.495603  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9541 16:44:49.499261  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9542 16:44:49.505492  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9543 16:44:49.510084  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9544 16:44:49.512308  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9545 16:44:49.515474  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9546 16:44:49.522145  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9547 16:44:49.525814  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9548 16:44:49.528917  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9549 16:44:49.532267  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9550 16:44:49.539100  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9551 16:44:49.542087  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9552 16:44:49.545097  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9553 16:44:49.549102  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9554 16:44:49.555653  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9555 16:44:49.558377  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9556 16:44:49.562227  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9557 16:44:49.565171  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9558 16:44:49.571570  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9559 16:44:49.575153  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9560 16:44:49.581875  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9561 16:44:49.584848  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9562 16:44:49.588155  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9563 16:44:49.594937  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9564 16:44:49.598047  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9565 16:44:49.604994  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9566 16:44:49.608303  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9567 16:44:49.614616  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9568 16:44:49.617804  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9569 16:44:49.624842  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9570 16:44:49.628281  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9571 16:44:49.631577  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9572 16:44:49.638597  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9573 16:44:49.641604  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9574 16:44:49.648080  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9575 16:44:49.651278  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9576 16:44:49.658002  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9577 16:44:49.661382  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9578 16:44:49.664725  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9579 16:44:49.670697  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9580 16:44:49.673958  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9581 16:44:49.680484  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9582 16:44:49.684306  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9583 16:44:49.690800  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9584 16:44:49.693869  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9585 16:44:49.700551  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9586 16:44:49.703783  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9587 16:44:49.710491  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9588 16:44:49.713803  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9589 16:44:49.718059  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9590 16:44:49.723832  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9591 16:44:49.727017  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9592 16:44:49.733455  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9593 16:44:49.736735  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9594 16:44:49.742947  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9595 16:44:49.746412  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9596 16:44:49.753224  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9597 16:44:49.756518  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9598 16:44:49.759497  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9599 16:44:49.766483  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9600 16:44:49.769912  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9601 16:44:49.776430  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9602 16:44:49.779354  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9603 16:44:49.785928  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9604 16:44:49.789857  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9605 16:44:49.796137  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9606 16:44:49.799168  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9607 16:44:49.802685  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9608 16:44:49.808883  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9609 16:44:49.812332  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9610 16:44:49.816178  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9611 16:44:49.819118  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9612 16:44:49.825778  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9613 16:44:49.829290  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9614 16:44:49.836162  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9615 16:44:49.839450  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9616 16:44:49.842371  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9617 16:44:49.849172  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9618 16:44:49.852545  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9619 16:44:49.859561  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9620 16:44:49.862239  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9621 16:44:49.866148  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9622 16:44:49.872307  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9623 16:44:49.875300  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9624 16:44:49.882340  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9625 16:44:49.885959  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9626 16:44:49.889586  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9627 16:44:49.895761  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9628 16:44:49.898724  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9629 16:44:49.902259  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9630 16:44:49.908933  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9631 16:44:49.912006  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9632 16:44:49.915529  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9633 16:44:49.918919  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9634 16:44:49.925598  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9635 16:44:49.928764  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9636 16:44:49.932308  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9637 16:44:49.939058  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9638 16:44:49.942246  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9639 16:44:49.949331  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9640 16:44:49.952027  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9641 16:44:49.955701  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9642 16:44:49.962377  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9643 16:44:49.965751  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9644 16:44:49.972014  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9645 16:44:49.975899  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9646 16:44:49.978490  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9647 16:44:49.985516  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9648 16:44:49.988654  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9649 16:44:49.992325  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9650 16:44:49.998420  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9651 16:44:50.001870  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9652 16:44:50.008946  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9653 16:44:50.011804  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9654 16:44:50.014958  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9655 16:44:50.021951  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9656 16:44:50.025608  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9657 16:44:50.031959  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9658 16:44:50.035081  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9659 16:44:50.038622  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9660 16:44:50.044983  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9661 16:44:50.049326  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9662 16:44:50.055235  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9663 16:44:50.058227  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9664 16:44:50.061779  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9665 16:44:50.067916  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9666 16:44:50.071266  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9667 16:44:50.077796  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9668 16:44:50.081611  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9669 16:44:50.084799  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9670 16:44:50.091661  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9671 16:44:50.094620  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9672 16:44:50.101101  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9673 16:44:50.104083  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9674 16:44:50.107406  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9675 16:44:50.114096  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9676 16:44:50.117778  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9677 16:44:50.124087  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9678 16:44:50.127280  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9679 16:44:50.130475  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9680 16:44:50.137615  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9681 16:44:50.140533  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9682 16:44:50.147389  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9683 16:44:50.150506  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9684 16:44:50.154479  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9685 16:44:50.160193  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9686 16:44:50.163627  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9687 16:44:50.170123  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9688 16:44:50.174173  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9689 16:44:50.176726  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9690 16:44:50.183117  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9691 16:44:50.186883  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9692 16:44:50.193082  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9693 16:44:50.196438  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9694 16:44:50.199823  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9695 16:44:50.206005  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9696 16:44:50.209239  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9697 16:44:50.215806  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9698 16:44:50.219155  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9699 16:44:50.226280  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9700 16:44:50.228982  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9701 16:44:50.232561  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9702 16:44:50.239464  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9703 16:44:50.242469  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9704 16:44:50.249114  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9705 16:44:50.252894  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9706 16:44:50.258857  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9707 16:44:50.262223  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9708 16:44:50.265306  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9709 16:44:50.271904  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9710 16:44:50.275058  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9711 16:44:50.281799  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9712 16:44:50.284793  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9713 16:44:50.291830  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9714 16:44:50.294988  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9715 16:44:50.297984  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9716 16:44:50.304371  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9717 16:44:50.307881  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9718 16:44:50.314823  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9719 16:44:50.318422  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9720 16:44:50.324497  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9721 16:44:50.327582  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9722 16:44:50.334063  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9723 16:44:50.337321  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9724 16:44:50.340615  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9725 16:44:50.347214  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9726 16:44:50.350726  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9727 16:44:50.357272  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9728 16:44:50.361154  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9729 16:44:50.363810  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9730 16:44:50.370756  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9731 16:44:50.374173  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9732 16:44:50.380621  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9733 16:44:50.383903  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9734 16:44:50.390640  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9735 16:44:50.394050  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9736 16:44:50.397091  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9737 16:44:50.403952  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9738 16:44:50.406912  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9739 16:44:50.413151  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9740 16:44:50.417046  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9741 16:44:50.419577  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9742 16:44:50.423113  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9743 16:44:50.429797  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9744 16:44:50.433149  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9745 16:44:50.436568  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9746 16:44:50.442744  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9747 16:44:50.446336  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9748 16:44:50.452553  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9749 16:44:50.456249  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9750 16:44:50.459446  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9751 16:44:50.465802  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9752 16:44:50.469716  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9753 16:44:50.472567  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9754 16:44:50.479076  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9755 16:44:50.482950  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9756 16:44:50.485821  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9757 16:44:50.492429  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9758 16:44:50.495897  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9759 16:44:50.499354  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9760 16:44:50.505832  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9761 16:44:50.508857  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9762 16:44:50.515462  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9763 16:44:50.518687  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9764 16:44:50.522179  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9765 16:44:50.528549  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9766 16:44:50.531815  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9767 16:44:50.538352  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9768 16:44:50.541684  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9769 16:44:50.545271  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9770 16:44:50.551888  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9771 16:44:50.555224  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9772 16:44:50.561202  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9773 16:44:50.564552  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9774 16:44:50.567839  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9775 16:44:50.574168  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9776 16:44:50.578047  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9777 16:44:50.580984  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9778 16:44:50.587308  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9779 16:44:50.590402  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9780 16:44:50.594079  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9781 16:44:50.600747  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9782 16:44:50.603996  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9783 16:44:50.607592  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9784 16:44:50.610485  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9785 16:44:50.617202  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9786 16:44:50.620551  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9787 16:44:50.623539  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9788 16:44:50.627092  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9789 16:44:50.634339  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9790 16:44:50.636978  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9791 16:44:50.641002  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9792 16:44:50.643716  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9793 16:44:50.650175  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9794 16:44:50.653558  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9795 16:44:50.659789  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9796 16:44:50.663234  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9797 16:44:50.669849  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9798 16:44:50.673191  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9799 16:44:50.680393  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9800 16:44:50.682979  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9801 16:44:50.686335  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9802 16:44:50.693128  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9803 16:44:50.696328  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9804 16:44:50.703023  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9805 16:44:50.706174  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9806 16:44:50.709958  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9807 16:44:50.715726  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9808 16:44:50.719110  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9809 16:44:50.725742  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9810 16:44:50.729027  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9811 16:44:50.735741  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9812 16:44:50.739168  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9813 16:44:50.742697  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9814 16:44:50.748983  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9815 16:44:50.752045  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9816 16:44:50.759285  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9817 16:44:50.762450  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9818 16:44:50.765403  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9819 16:44:50.772190  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9820 16:44:50.775297  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9821 16:44:50.782000  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9822 16:44:50.785032  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9823 16:44:50.791965  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9824 16:44:50.795092  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9825 16:44:50.798399  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9826 16:44:50.805170  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9827 16:44:50.807800  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9828 16:44:50.814749  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9829 16:44:50.818172  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9830 16:44:50.824409  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9831 16:44:50.827630  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9832 16:44:50.830984  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9833 16:44:50.838312  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9834 16:44:50.840936  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9835 16:44:50.847733  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9836 16:44:50.850918  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9837 16:44:50.857316  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9838 16:44:50.860601  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9839 16:44:50.864049  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9840 16:44:50.870369  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9841 16:44:50.873608  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9842 16:44:50.880524  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9843 16:44:50.883647  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9844 16:44:50.887295  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9845 16:44:50.893117  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9846 16:44:50.896551  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9847 16:44:50.903283  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9848 16:44:50.906671  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9849 16:44:50.913327  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9850 16:44:50.916136  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9851 16:44:50.919817  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9852 16:44:50.926759  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9853 16:44:50.929819  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9854 16:44:50.936506  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9855 16:44:50.939590  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9856 16:44:50.943003  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9857 16:44:50.949634  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9858 16:44:50.952863  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9859 16:44:50.959265  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9860 16:44:50.962977  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9861 16:44:50.969487  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9862 16:44:50.972872  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9863 16:44:50.979404  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9864 16:44:50.982347  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9865 16:44:50.985656  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9866 16:44:50.992216  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9867 16:44:50.995589  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9868 16:44:51.002204  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9869 16:44:51.005256  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9870 16:44:51.011986  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9871 16:44:51.014953  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9872 16:44:51.018283  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9873 16:44:51.025155  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9874 16:44:51.028584  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9875 16:44:51.034819  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9876 16:44:51.038202  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9877 16:44:51.045122  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9878 16:44:51.047881  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9879 16:44:51.054509  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9880 16:44:51.057908  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9881 16:44:51.061577  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9882 16:44:51.067745  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9883 16:44:51.071141  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9884 16:44:51.077562  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9885 16:44:51.081385  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9886 16:44:51.087411  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9887 16:44:51.090745  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9888 16:44:51.097482  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9889 16:44:51.100459  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9890 16:44:51.103783  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9891 16:44:51.110532  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9892 16:44:51.114105  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9893 16:44:51.120922  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9894 16:44:51.123562  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9895 16:44:51.130029  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9896 16:44:51.133456  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9897 16:44:51.139986  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9898 16:44:51.143354  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9899 16:44:51.150143  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9900 16:44:51.153205  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9901 16:44:51.156752  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9902 16:44:51.163136  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9903 16:44:51.166290  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9904 16:44:51.172864  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9905 16:44:51.176392  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9906 16:44:51.182534  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9907 16:44:51.186071  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9908 16:44:51.193304  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9909 16:44:51.195646  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9910 16:44:51.202935  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9911 16:44:51.206423  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9912 16:44:51.209339  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9913 16:44:51.215662  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9914 16:44:51.219019  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9915 16:44:51.225662  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9916 16:44:51.228965  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9917 16:44:51.235272  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9918 16:44:51.238560  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9919 16:44:51.245533  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9920 16:44:51.248583  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9921 16:44:51.255270  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9922 16:44:51.258793  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9923 16:44:51.264798  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9924 16:44:51.268258  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9925 16:44:51.274960  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9926 16:44:51.278260  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9927 16:44:51.285003  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9928 16:44:51.287944  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9929 16:44:51.294604  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9930 16:44:51.297712  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9931 16:44:51.301353  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9932 16:44:51.307859  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9933 16:44:51.310981  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9934 16:44:51.317660  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9935 16:44:51.324133  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9936 16:44:51.327582  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9937 16:44:51.333809  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9938 16:44:51.337741  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9939 16:44:51.343943  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9940 16:44:51.347119  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9941 16:44:51.353580  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9942 16:44:51.357024  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9943 16:44:51.363734  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9944 16:44:51.366777  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9945 16:44:51.370247  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9946 16:44:51.373247  INFO:    [APUAPC] vio 0

 9947 16:44:51.380102  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9948 16:44:51.383856  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9949 16:44:51.386585  INFO:    [APUAPC] D0_APC_0: 0x400510

 9950 16:44:51.389853  INFO:    [APUAPC] D0_APC_1: 0x0

 9951 16:44:51.393580  INFO:    [APUAPC] D0_APC_2: 0x1540

 9952 16:44:51.396961  INFO:    [APUAPC] D0_APC_3: 0x0

 9953 16:44:51.400044  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9954 16:44:51.403207  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9955 16:44:51.406289  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9956 16:44:51.409778  INFO:    [APUAPC] D1_APC_3: 0x0

 9957 16:44:51.413126  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9958 16:44:51.416346  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9959 16:44:51.419992  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9960 16:44:51.423378  INFO:    [APUAPC] D2_APC_3: 0x0

 9961 16:44:51.426583  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9962 16:44:51.429600  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9963 16:44:51.432990  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9964 16:44:51.436346  INFO:    [APUAPC] D3_APC_3: 0x0

 9965 16:44:51.439721  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9966 16:44:51.442854  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9967 16:44:51.445739  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9968 16:44:51.446184  INFO:    [APUAPC] D4_APC_3: 0x0

 9969 16:44:51.452574  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9970 16:44:51.456500  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9971 16:44:51.459477  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9972 16:44:51.459925  INFO:    [APUAPC] D5_APC_3: 0x0

 9973 16:44:51.462834  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9974 16:44:51.469236  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9975 16:44:51.472486  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9976 16:44:51.472913  INFO:    [APUAPC] D6_APC_3: 0x0

 9977 16:44:51.475855  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9978 16:44:51.479281  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9979 16:44:51.482565  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9980 16:44:51.486161  INFO:    [APUAPC] D7_APC_3: 0x0

 9981 16:44:51.489107  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9982 16:44:51.492428  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9983 16:44:51.495736  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9984 16:44:51.498890  INFO:    [APUAPC] D8_APC_3: 0x0

 9985 16:44:51.502062  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9986 16:44:51.505190  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9987 16:44:51.508775  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9988 16:44:51.511867  INFO:    [APUAPC] D9_APC_3: 0x0

 9989 16:44:51.515086  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9990 16:44:51.518639  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9991 16:44:51.522008  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9992 16:44:51.524991  INFO:    [APUAPC] D10_APC_3: 0x0

 9993 16:44:51.528652  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9994 16:44:51.532272  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9995 16:44:51.535485  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9996 16:44:51.538109  INFO:    [APUAPC] D11_APC_3: 0x0

 9997 16:44:51.541517  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9998 16:44:51.545156  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9999 16:44:51.547881  INFO:    [APUAPC] D12_APC_2: 0x3fffff

10000 16:44:51.551335  INFO:    [APUAPC] D12_APC_3: 0x0

10001 16:44:51.554825  INFO:    [APUAPC] D13_APC_0: 0xffffffff

10002 16:44:51.561272  INFO:    [APUAPC] D13_APC_1: 0xffffffff

10003 16:44:51.564302  INFO:    [APUAPC] D13_APC_2: 0x3fffff

10004 16:44:51.564412  INFO:    [APUAPC] D13_APC_3: 0x0

10005 16:44:51.567558  INFO:    [APUAPC] D14_APC_0: 0xffffffff

10006 16:44:51.574366  INFO:    [APUAPC] D14_APC_1: 0xffffffff

10007 16:44:51.577680  INFO:    [APUAPC] D14_APC_2: 0x3fffff

10008 16:44:51.577789  INFO:    [APUAPC] D14_APC_3: 0x0

10009 16:44:51.584030  INFO:    [APUAPC] D15_APC_0: 0xffffffff

10010 16:44:51.587242  INFO:    [APUAPC] D15_APC_1: 0xffffffff

10011 16:44:51.590705  INFO:    [APUAPC] D15_APC_2: 0x3fffff

10012 16:44:51.593982  INFO:    [APUAPC] D15_APC_3: 0x0

10013 16:44:51.594084  INFO:    [APUAPC] APC_CON: 0x4

10014 16:44:51.597568  INFO:    [NOCDAPC] D0_APC_0: 0x0

10015 16:44:51.600497  INFO:    [NOCDAPC] D0_APC_1: 0x0

10016 16:44:51.604341  INFO:    [NOCDAPC] D1_APC_0: 0x0

10017 16:44:51.607097  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10018 16:44:51.611053  INFO:    [NOCDAPC] D2_APC_0: 0x0

10019 16:44:51.613631  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10020 16:44:51.617216  INFO:    [NOCDAPC] D3_APC_0: 0x0

10021 16:44:51.620028  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10022 16:44:51.623690  INFO:    [NOCDAPC] D4_APC_0: 0x0

10023 16:44:51.623764  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10024 16:44:51.627112  INFO:    [NOCDAPC] D5_APC_0: 0x0

10025 16:44:51.630375  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10026 16:44:51.633868  INFO:    [NOCDAPC] D6_APC_0: 0x0

10027 16:44:51.636906  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10028 16:44:51.639807  INFO:    [NOCDAPC] D7_APC_0: 0x0

10029 16:44:51.642976  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10030 16:44:51.646811  INFO:    [NOCDAPC] D8_APC_0: 0x0

10031 16:44:51.649690  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10032 16:44:51.653160  INFO:    [NOCDAPC] D9_APC_0: 0x0

10033 16:44:51.656399  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10034 16:44:51.659963  INFO:    [NOCDAPC] D10_APC_0: 0x0

10035 16:44:51.662799  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10036 16:44:51.662873  INFO:    [NOCDAPC] D11_APC_0: 0x0

10037 16:44:51.667040  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10038 16:44:51.669467  INFO:    [NOCDAPC] D12_APC_0: 0x0

10039 16:44:51.673268  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10040 16:44:51.675945  INFO:    [NOCDAPC] D13_APC_0: 0x0

10041 16:44:51.679502  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10042 16:44:51.682935  INFO:    [NOCDAPC] D14_APC_0: 0x0

10043 16:44:51.686341  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10044 16:44:51.689590  INFO:    [NOCDAPC] D15_APC_0: 0x0

10045 16:44:51.692547  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10046 16:44:51.695852  INFO:    [NOCDAPC] APC_CON: 0x4

10047 16:44:51.699879  INFO:    [APUAPC] set_apusys_apc done

10048 16:44:51.702753  INFO:    [DEVAPC] devapc_init done

10049 16:44:51.706053  INFO:    GICv3 without legacy support detected.

10050 16:44:51.709507  INFO:    ARM GICv3 driver initialized in EL3

10051 16:44:51.713079  INFO:    Maximum SPI INTID supported: 639

10052 16:44:51.719327  INFO:    BL31: Initializing runtime services

10053 16:44:51.722255  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10054 16:44:51.726027  INFO:    SPM: enable CPC mode

10055 16:44:51.732684  INFO:    mcdi ready for mcusys-off-idle and system suspend

10056 16:44:51.735889  INFO:    BL31: Preparing for EL3 exit to normal world

10057 16:44:51.738629  INFO:    Entry point address = 0x80000000

10058 16:44:51.742441  INFO:    SPSR = 0x8

10059 16:44:51.747852  

10060 16:44:51.748352  

10061 16:44:51.748756  

10062 16:44:51.751401  Starting depthcharge on Spherion...

10063 16:44:51.752005  

10064 16:44:51.752547  Wipe memory regions:

10065 16:44:51.753074  

10066 16:44:51.755793  end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10067 16:44:51.756393  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10068 16:44:51.756871  Setting prompt string to ['asurada:']
10069 16:44:51.757358  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10070 16:44:51.758136  	[0x00000040000000, 0x00000054600000)

10071 16:44:51.876547  

10072 16:44:51.876704  	[0x00000054660000, 0x00000080000000)

10073 16:44:52.137450  

10074 16:44:52.137973  	[0x000000821a7280, 0x000000ffe64000)

10075 16:44:52.882715  

10076 16:44:52.883306  	[0x00000100000000, 0x00000240000000)

10077 16:44:54.772350  

10078 16:44:54.775387  Initializing XHCI USB controller at 0x11200000.

10079 16:44:55.813534  

10080 16:44:55.816777  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10081 16:44:55.817303  

10082 16:44:55.817946  

10083 16:44:55.818385  

10084 16:44:55.819332  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 16:44:55.920703  asurada: tftpboot 192.168.201.1 10576285/tftp-deploy-reorxb3r/kernel/image.itb 10576285/tftp-deploy-reorxb3r/kernel/cmdline 

10087 16:44:55.921274  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 16:44:55.921708  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10089 16:44:55.926074  tftpboot 192.168.201.1 10576285/tftp-deploy-reorxb3r/kernel/image.itp-deploy-reorxb3r/kernel/cmdline 

10090 16:44:55.926571  

10091 16:44:55.926908  Waiting for link

10092 16:44:56.086311  

10093 16:44:56.086803  R8152: Initializing

10094 16:44:56.087222  

10095 16:44:56.089757  Version 6 (ocp_data = 5c30)

10096 16:44:56.090262  

10097 16:44:56.092573  R8152: Done initializing

10098 16:44:56.092996  

10099 16:44:56.093332  Adding net device

10100 16:44:58.070203  

10101 16:44:58.070691  done.

10102 16:44:58.071050  

10103 16:44:58.071480  MAC: 00:24:32:30:7c:7b

10104 16:44:58.071803  

10105 16:44:58.073420  Sending DHCP discover... done.

10106 16:44:58.073846  

10107 16:44:58.076717  Waiting for reply... done.

10108 16:44:58.077186  

10109 16:44:58.079815  Sending DHCP request... done.

10110 16:44:58.080401  

10111 16:44:58.091479  Waiting for reply... done.

10112 16:44:58.091913  

10113 16:44:58.092294  My ip is 192.168.201.14

10114 16:44:58.092615  

10115 16:44:58.094509  The DHCP server ip is 192.168.201.1

10116 16:44:58.094970  

10117 16:44:58.101255  TFTP server IP predefined by user: 192.168.201.1

10118 16:44:58.101711  

10119 16:44:58.107660  Bootfile predefined by user: 10576285/tftp-deploy-reorxb3r/kernel/image.itb

10120 16:44:58.108094  

10121 16:44:58.111280  Sending tftp read request... done.

10122 16:44:58.111746  

10123 16:44:58.116856  Waiting for the transfer... 

10124 16:44:58.117287  

10125 16:44:58.741799  00000000 ################################################################

10126 16:44:58.742442  

10127 16:44:59.378066  00080000 ################################################################

10128 16:44:59.378573  

10129 16:45:00.001440  00100000 ################################################################

10130 16:45:00.001992  

10131 16:45:00.616854  00180000 ################################################################

10132 16:45:00.617361  

10133 16:45:01.280931  00200000 ################################################################

10134 16:45:01.281071  

10135 16:45:01.936484  00280000 ################################################################

10136 16:45:01.937018  

10137 16:45:02.622977  00300000 ################################################################

10138 16:45:02.623626  

10139 16:45:03.325942  00380000 ################################################################

10140 16:45:03.326459  

10141 16:45:04.022442  00400000 ################################################################

10142 16:45:04.022594  

10143 16:45:04.723517  00480000 ################################################################

10144 16:45:04.724130  

10145 16:45:05.417825  00500000 ################################################################

10146 16:45:05.418370  

10147 16:45:06.069022  00580000 ################################################################

10148 16:45:06.069234  

10149 16:45:06.704545  00600000 ################################################################

10150 16:45:06.704699  

10151 16:45:07.287616  00680000 ################################################################

10152 16:45:07.288270  

10153 16:45:07.878492  00700000 ################################################################

10154 16:45:07.878636  

10155 16:45:08.443819  00780000 ################################################################

10156 16:45:08.443961  

10157 16:45:09.003102  00800000 ################################################################

10158 16:45:09.003259  

10159 16:45:09.576726  00880000 ################################################################

10160 16:45:09.576867  

10161 16:45:10.130289  00900000 ################################################################

10162 16:45:10.130427  

10163 16:45:10.691438  00980000 ################################################################

10164 16:45:10.691572  

10165 16:45:11.260798  00a00000 ################################################################

10166 16:45:11.260930  

10167 16:45:11.837380  00a80000 ################################################################

10168 16:45:11.837519  

10169 16:45:12.392175  00b00000 ################################################################

10170 16:45:12.392359  

10171 16:45:12.952416  00b80000 ################################################################

10172 16:45:12.952604  

10173 16:45:13.523445  00c00000 ################################################################

10174 16:45:13.523586  

10175 16:45:14.096956  00c80000 ################################################################

10176 16:45:14.097193  

10177 16:45:14.659319  00d00000 ################################################################

10178 16:45:14.659465  

10179 16:45:15.238202  00d80000 ################################################################

10180 16:45:15.238358  

10181 16:45:15.804956  00e00000 ################################################################

10182 16:45:15.805116  

10183 16:45:16.358212  00e80000 ################################################################

10184 16:45:16.358361  

10185 16:45:16.917657  00f00000 ################################################################

10186 16:45:16.917816  

10187 16:45:17.480076  00f80000 ################################################################

10188 16:45:17.480279  

10189 16:45:18.048100  01000000 ################################################################

10190 16:45:18.048264  

10191 16:45:18.608935  01080000 ################################################################

10192 16:45:18.609137  

10193 16:45:19.171484  01100000 ################################################################

10194 16:45:19.171661  

10195 16:45:19.737945  01180000 ################################################################

10196 16:45:19.738096  

10197 16:45:20.309914  01200000 ################################################################

10198 16:45:20.310071  

10199 16:45:20.887020  01280000 ################################################################

10200 16:45:20.887223  

10201 16:45:21.475825  01300000 ################################################################

10202 16:45:21.475965  

10203 16:45:22.038483  01380000 ################################################################

10204 16:45:22.038640  

10205 16:45:22.614771  01400000 ################################################################

10206 16:45:22.614945  

10207 16:45:23.207146  01480000 ################################################################

10208 16:45:23.207336  

10209 16:45:23.781678  01500000 ################################################################

10210 16:45:23.781847  

10211 16:45:24.363458  01580000 ################################################################

10212 16:45:24.363590  

10213 16:45:25.031463  01600000 ################################################################

10214 16:45:25.031959  

10215 16:45:25.673842  01680000 ################################################################

10216 16:45:25.674436  

10217 16:45:26.329115  01700000 ################################################################

10218 16:45:26.329671  

10219 16:45:26.974100  01780000 ################################################################

10220 16:45:26.974309  

10221 16:45:27.618659  01800000 ################################################################

10222 16:45:27.619152  

10223 16:45:28.236624  01880000 ################################################################

10224 16:45:28.237151  

10225 16:45:28.887414  01900000 ################################################################

10226 16:45:28.887838  

10227 16:45:29.533744  01980000 ################################################################

10228 16:45:29.534449  

10229 16:45:30.058941  01a00000 ############################################################## done.

10230 16:45:30.059074  

10231 16:45:30.061950  The bootfile was 27769954 bytes long.

10232 16:45:30.062083  

10233 16:45:30.065122  Sending tftp read request... done.

10234 16:45:30.065205  

10235 16:45:30.065271  Waiting for the transfer... 

10236 16:45:30.065333  

10237 16:45:30.068316  00000000 # done.

10238 16:45:30.068400  

10239 16:45:30.075316  Command line loaded dynamically from TFTP file: 10576285/tftp-deploy-reorxb3r/kernel/cmdline

10240 16:45:30.075421  

10241 16:45:30.094762  The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576285/extract-nfsrootfs-7_pn6cuh,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10242 16:45:30.094860  

10243 16:45:30.097881  Loading FIT.

10244 16:45:30.097959  

10245 16:45:30.101227  Image ramdisk-1 has 17637521 bytes.

10246 16:45:30.101310  

10247 16:45:30.104304  Image fdt-1 has 46924 bytes.

10248 16:45:30.104381  

10249 16:45:30.104444  Image kernel-1 has 10083474 bytes.

10250 16:45:30.107736  

10251 16:45:30.114237  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10252 16:45:30.114319  

10253 16:45:30.134255  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10254 16:45:30.134353  

10255 16:45:30.137185  Choosing best match conf-1 for compat google,spherion-rev2.

10256 16:45:30.142214  

10257 16:45:30.146380  Connected to device vid:did:rid of 1ae0:0028:00

10258 16:45:30.153732  

10259 16:45:30.156835  tpm_get_response: command 0x17b, return code 0x0

10260 16:45:30.156917  

10261 16:45:30.160316  ec_init: CrosEC protocol v3 supported (256, 248)

10262 16:45:30.165196  

10263 16:45:30.168358  tpm_cleanup: add release locality here.

10264 16:45:30.168442  

10265 16:45:30.168507  Shutting down all USB controllers.

10266 16:45:30.171633  

10267 16:45:30.171716  Removing current net device

10268 16:45:30.171781  

10269 16:45:30.178320  Exiting depthcharge with code 4 at timestamp: 67679472

10270 16:45:30.178404  

10271 16:45:30.181643  LZMA decompressing kernel-1 to 0x821a6718

10272 16:45:30.181726  

10273 16:45:30.185133  LZMA decompressing kernel-1 to 0x40000000

10274 16:45:31.450969  

10275 16:45:31.451110  jumping to kernel

10276 16:45:31.451522  end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10277 16:45:31.451623  start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10278 16:45:31.451700  Setting prompt string to ['Linux version [0-9]']
10279 16:45:31.451769  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10280 16:45:31.451837  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10281 16:45:31.532671  

10282 16:45:31.536420  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10283 16:45:31.540262  start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10284 16:45:31.540719  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10285 16:45:31.541142  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10286 16:45:31.541514  Using line separator: #'\n'#
10287 16:45:31.541830  No login prompt set.
10288 16:45:31.542148  Parsing kernel messages
10289 16:45:31.542440  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10290 16:45:31.542954  [login-action] Waiting for messages, (timeout 00:03:45)
10291 16:45:31.559046  [    0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun  3 16:27:28 UTC 2023

10292 16:45:31.561966  [    0.000000] random: crng init done

10293 16:45:31.568897  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10294 16:45:31.572282  [    0.000000] efi: UEFI not found.

10295 16:45:31.579021  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10296 16:45:31.585051  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10297 16:45:31.595072  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10298 16:45:31.604852  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10299 16:45:31.611800  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10300 16:45:31.618268  [    0.000000] printk: bootconsole [mtk8250] enabled

10301 16:45:31.624811  [    0.000000] NUMA: No NUMA configuration found

10302 16:45:31.631417  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10303 16:45:31.634374  [    0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]

10304 16:45:31.637886  [    0.000000] Zone ranges:

10305 16:45:31.644458  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10306 16:45:31.647792  [    0.000000]   DMA32    empty

10307 16:45:31.654686  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10308 16:45:31.658071  [    0.000000] Movable zone start for each node

10309 16:45:31.661023  [    0.000000] Early memory node ranges

10310 16:45:31.667814  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10311 16:45:31.674137  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10312 16:45:31.680728  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10313 16:45:31.687568  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10314 16:45:31.693779  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10315 16:45:31.700332  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10316 16:45:31.756676  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10317 16:45:31.763737  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10318 16:45:31.769739  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10319 16:45:31.773052  [    0.000000] psci: probing for conduit method from DT.

10320 16:45:31.779834  [    0.000000] psci: PSCIv1.1 detected in firmware.

10321 16:45:31.783237  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10322 16:45:31.789971  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10323 16:45:31.792743  [    0.000000] psci: SMC Calling Convention v1.2

10324 16:45:31.799291  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10325 16:45:31.802806  [    0.000000] Detected VIPT I-cache on CPU0

10326 16:45:31.809262  [    0.000000] CPU features: detected: GIC system register CPU interface

10327 16:45:31.816067  [    0.000000] CPU features: detected: Virtualization Host Extensions

10328 16:45:31.822604  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10329 16:45:31.829026  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10330 16:45:31.838962  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10331 16:45:31.845634  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10332 16:45:31.848823  [    0.000000] alternatives: applying boot alternatives

10333 16:45:31.856033  [    0.000000] Fallback order for Node 0: 0 

10334 16:45:31.862043  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10335 16:45:31.865224  [    0.000000] Policy zone: Normal

10336 16:45:31.885215  [    0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576285/extract-nfsrootfs-7_pn6cuh,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10337 16:45:31.895543  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10338 16:45:31.907904  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10339 16:45:31.917153  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10340 16:45:31.923858  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10341 16:45:31.926896  <6>[    0.000000] software IO TLB: area num 8.

10342 16:45:31.983676  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10343 16:45:32.132698  <6>[    0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)

10344 16:45:32.139562  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10345 16:45:32.146019  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10346 16:45:32.149361  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10347 16:45:32.156023  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10348 16:45:32.162436  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10349 16:45:32.168786  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10350 16:45:32.175680  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10351 16:45:32.182392  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10352 16:45:32.189133  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10353 16:45:32.195919  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10354 16:45:32.198580  <6>[    0.000000] GICv3: 608 SPIs implemented

10355 16:45:32.201804  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10356 16:45:32.209247  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10357 16:45:32.211917  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10358 16:45:32.218636  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10359 16:45:32.231692  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10360 16:45:32.244885  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10361 16:45:32.251210  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10362 16:45:32.259581  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10363 16:45:32.272652  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10364 16:45:32.279428  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10365 16:45:32.286179  <6>[    0.009231] Console: colour dummy device 80x25

10366 16:45:32.295971  <6>[    0.013989] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10367 16:45:32.302902  <6>[    0.024496] pid_max: default: 32768 minimum: 301

10368 16:45:32.305762  <6>[    0.029369] LSM: Security Framework initializing

10369 16:45:32.312380  <6>[    0.034307] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10370 16:45:32.322434  <6>[    0.042169] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10371 16:45:32.332230  <6>[    0.051600] cblist_init_generic: Setting adjustable number of callback queues.

10372 16:45:32.339120  <6>[    0.059100] cblist_init_generic: Setting shift to 3 and lim to 1.

10373 16:45:32.341990  <6>[    0.065478] cblist_init_generic: Setting shift to 3 and lim to 1.

10374 16:45:32.348918  <6>[    0.071884] rcu: Hierarchical SRCU implementation.

10375 16:45:32.355660  <6>[    0.076898] rcu: 	Max phase no-delay instances is 1000.

10376 16:45:32.362039  <6>[    0.083951] EFI services will not be available.

10377 16:45:32.365426  <6>[    0.088901] smp: Bringing up secondary CPUs ...

10378 16:45:32.373310  <6>[    0.093981] Detected VIPT I-cache on CPU1

10379 16:45:32.380036  <6>[    0.094056] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10380 16:45:32.386318  <6>[    0.094085] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10381 16:45:32.390139  <6>[    0.094419] Detected VIPT I-cache on CPU2

10382 16:45:32.399788  <6>[    0.094470] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10383 16:45:32.406065  <6>[    0.094486] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10384 16:45:32.409390  <6>[    0.094749] Detected VIPT I-cache on CPU3

10385 16:45:32.415835  <6>[    0.094795] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10386 16:45:32.422549  <6>[    0.094810] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10387 16:45:32.429082  <6>[    0.095117] CPU features: detected: Spectre-v4

10388 16:45:32.433105  <6>[    0.095123] CPU features: detected: Spectre-BHB

10389 16:45:32.435912  <6>[    0.095130] Detected PIPT I-cache on CPU4

10390 16:45:32.442391  <6>[    0.095186] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10391 16:45:32.451902  <6>[    0.095204] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10392 16:45:32.455740  <6>[    0.095501] Detected PIPT I-cache on CPU5

10393 16:45:32.461889  <6>[    0.095567] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10394 16:45:32.468525  <6>[    0.095584] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10395 16:45:32.472096  <6>[    0.095869] Detected PIPT I-cache on CPU6

10396 16:45:32.481777  <6>[    0.095936] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10397 16:45:32.488202  <6>[    0.095953] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10398 16:45:32.491549  <6>[    0.096252] Detected PIPT I-cache on CPU7

10399 16:45:32.498013  <6>[    0.096317] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10400 16:45:32.505017  <6>[    0.096333] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10401 16:45:32.508177  <6>[    0.096381] smp: Brought up 1 node, 8 CPUs

10402 16:45:32.515131  <6>[    0.237600] SMP: Total of 8 processors activated.

10403 16:45:32.521400  <6>[    0.242552] CPU features: detected: 32-bit EL0 Support

10404 16:45:32.528103  <6>[    0.247914] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10405 16:45:32.534723  <6>[    0.256714] CPU features: detected: Common not Private translations

10406 16:45:32.541241  <6>[    0.263189] CPU features: detected: CRC32 instructions

10407 16:45:32.547809  <6>[    0.268557] CPU features: detected: RCpc load-acquire (LDAPR)

10408 16:45:32.551140  <6>[    0.274516] CPU features: detected: LSE atomic instructions

10409 16:45:32.557631  <6>[    0.280333] CPU features: detected: Privileged Access Never

10410 16:45:32.564156  <6>[    0.286113] CPU features: detected: RAS Extension Support

10411 16:45:32.570937  <6>[    0.291756] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10412 16:45:32.574268  <6>[    0.299020] CPU: All CPU(s) started at EL2

10413 16:45:32.580627  <6>[    0.303336] alternatives: applying system-wide alternatives

10414 16:45:32.590947  <6>[    0.314045] devtmpfs: initialized

10415 16:45:32.606578  <6>[    0.322953] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10416 16:45:32.613243  <6>[    0.332915] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10417 16:45:32.615964  <6>[    0.340521] pinctrl core: initialized pinctrl subsystem

10418 16:45:32.624225  <6>[    0.347335] DMI not present or invalid.

10419 16:45:32.630716  <6>[    0.351758] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10420 16:45:32.637126  <6>[    0.358653] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10421 16:45:32.646969  <6>[    0.366239] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10422 16:45:32.653949  <6>[    0.374472] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10423 16:45:32.660131  <6>[    0.382721] audit: initializing netlink subsys (disabled)

10424 16:45:32.667227  <5>[    0.388421] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1

10425 16:45:32.673704  <6>[    0.389207] thermal_sys: Registered thermal governor 'step_wise'

10426 16:45:32.680755  <6>[    0.396390] thermal_sys: Registered thermal governor 'power_allocator'

10427 16:45:32.686871  <6>[    0.402646] cpuidle: using governor menu

10428 16:45:32.690323  <6>[    0.413614] NET: Registered PF_QIPCRTR protocol family

10429 16:45:32.696588  <6>[    0.419142] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10430 16:45:32.703789  <6>[    0.426243] ASID allocator initialised with 32768 entries

10431 16:45:32.709675  <6>[    0.432909] Serial: AMBA PL011 UART driver

10432 16:45:32.719193  <4>[    0.441926] Trying to register duplicate clock ID: 134

10433 16:45:32.775421  <6>[    0.501873] KASLR enabled

10434 16:45:32.789883  <6>[    0.509557] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10435 16:45:32.796175  <6>[    0.516574] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10436 16:45:32.803419  <6>[    0.523066] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10437 16:45:32.809243  <6>[    0.530073] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10438 16:45:32.816032  <6>[    0.536560] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10439 16:45:32.822784  <6>[    0.543564] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10440 16:45:32.829185  <6>[    0.550054] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10441 16:45:32.836119  <6>[    0.557060] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10442 16:45:32.839149  <6>[    0.564559] ACPI: Interpreter disabled.

10443 16:45:32.847823  <6>[    0.571027] iommu: Default domain type: Translated 

10444 16:45:32.854570  <6>[    0.576191] iommu: DMA domain TLB invalidation policy: strict mode 

10445 16:45:32.858050  <5>[    0.582854] SCSI subsystem initialized

10446 16:45:32.864534  <6>[    0.587091] usbcore: registered new interface driver usbfs

10447 16:45:32.871052  <6>[    0.592824] usbcore: registered new interface driver hub

10448 16:45:32.874115  <6>[    0.598378] usbcore: registered new device driver usb

10449 16:45:32.881377  <6>[    0.604526] pps_core: LinuxPPS API ver. 1 registered

10450 16:45:32.891950  <6>[    0.609721] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10451 16:45:32.895008  <6>[    0.619062] PTP clock support registered

10452 16:45:32.898001  <6>[    0.623306] EDAC MC: Ver: 3.0.0

10453 16:45:32.905556  <6>[    0.628529] FPGA manager framework

10454 16:45:32.912526  <6>[    0.632208] Advanced Linux Sound Architecture Driver Initialized.

10455 16:45:32.915410  <6>[    0.638985] vgaarb: loaded

10456 16:45:32.921671  <6>[    0.642090] clocksource: Switched to clocksource arch_sys_counter

10457 16:45:32.925447  <5>[    0.648535] VFS: Disk quotas dquot_6.6.0

10458 16:45:32.931841  <6>[    0.652724] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10459 16:45:32.935364  <6>[    0.659920] pnp: PnP ACPI: disabled

10460 16:45:32.943654  <6>[    0.666614] NET: Registered PF_INET protocol family

10461 16:45:32.953608  <6>[    0.672199] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10462 16:45:32.964626  <6>[    0.684504] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10463 16:45:32.974691  <6>[    0.693321] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10464 16:45:32.981235  <6>[    0.701294] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10465 16:45:32.991394  <6>[    0.709993] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10466 16:45:32.997523  <6>[    0.719742] TCP: Hash tables configured (established 65536 bind 65536)

10467 16:45:33.003806  <6>[    0.726603] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10468 16:45:33.014368  <6>[    0.733802] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10469 16:45:33.020852  <6>[    0.741505] NET: Registered PF_UNIX/PF_LOCAL protocol family

10470 16:45:33.027480  <6>[    0.747670] RPC: Registered named UNIX socket transport module.

10471 16:45:33.030227  <6>[    0.753823] RPC: Registered udp transport module.

10472 16:45:33.037082  <6>[    0.758754] RPC: Registered tcp transport module.

10473 16:45:33.043438  <6>[    0.763688] RPC: Registered tcp NFSv4.1 backchannel transport module.

10474 16:45:33.047023  <6>[    0.770358] PCI: CLS 0 bytes, default 64

10475 16:45:33.050317  <6>[    0.774749] Unpacking initramfs...

10476 16:45:33.059808  <6>[    0.778561] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10477 16:45:33.066704  <6>[    0.787236] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10478 16:45:33.073533  <6>[    0.796091] kvm [1]: IPA Size Limit: 40 bits

10479 16:45:33.076907  <6>[    0.800616] kvm [1]: GICv3: no GICV resource entry

10480 16:45:33.083560  <6>[    0.805635] kvm [1]: disabling GICv2 emulation

10481 16:45:33.089641  <6>[    0.810320] kvm [1]: GIC system register CPU interface enabled

10482 16:45:33.093262  <6>[    0.816485] kvm [1]: vgic interrupt IRQ18

10483 16:45:33.099640  <6>[    0.820842] kvm [1]: VHE mode initialized successfully

10484 16:45:33.103133  <5>[    0.827207] Initialise system trusted keyrings

10485 16:45:33.109529  <6>[    0.832015] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10486 16:45:33.118960  <6>[    0.842059] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10487 16:45:33.125932  <5>[    0.848422] NFS: Registering the id_resolver key type

10488 16:45:33.129164  <5>[    0.853722] Key type id_resolver registered

10489 16:45:33.135363  <5>[    0.858138] Key type id_legacy registered

10490 16:45:33.142563  <6>[    0.862418] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10491 16:45:33.148501  <6>[    0.869339] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10492 16:45:33.155116  <6>[    0.877072] 9p: Installing v9fs 9p2000 file system support

10493 16:45:33.191908  <5>[    0.914671] Key type asymmetric registered

10494 16:45:33.194679  <5>[    0.919005] Asymmetric key parser 'x509' registered

10495 16:45:33.204659  <6>[    0.924144] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10496 16:45:33.207932  <6>[    0.931758] io scheduler mq-deadline registered

10497 16:45:33.211251  <6>[    0.936521] io scheduler kyber registered

10498 16:45:33.230526  <6>[    0.953764] EINJ: ACPI disabled.

10499 16:45:33.263007  <4>[    0.979690] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10500 16:45:33.272887  <4>[    0.990326] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10501 16:45:33.288475  <6>[    1.011546] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10502 16:45:33.296128  <6>[    1.019556] printk: console [ttyS0] disabled

10503 16:45:33.324254  <6>[    1.044206] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10504 16:45:33.331056  <6>[    1.053683] printk: console [ttyS0] enabled

10505 16:45:33.334216  <6>[    1.053683] printk: console [ttyS0] enabled

10506 16:45:33.340640  <6>[    1.062579] printk: bootconsole [mtk8250] disabled

10507 16:45:33.343988  <6>[    1.062579] printk: bootconsole [mtk8250] disabled

10508 16:45:33.350564  <6>[    1.073870] SuperH (H)SCI(F) driver initialized

10509 16:45:33.353735  <6>[    1.079163] msm_serial: driver initialized

10510 16:45:33.368455  <6>[    1.088226] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10511 16:45:33.378983  <6>[    1.096774] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10512 16:45:33.385092  <6>[    1.105318] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10513 16:45:33.394534  <6>[    1.113948] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10514 16:45:33.404173  <6>[    1.122655] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10515 16:45:33.411141  <6>[    1.131381] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10516 16:45:33.421131  <6>[    1.139925] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10517 16:45:33.428129  <6>[    1.148732] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10518 16:45:33.437521  <6>[    1.157275] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10519 16:45:33.447185  <6>[    1.172955] loop: module loaded

10520 16:45:33.455620  <6>[    1.179028] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10521 16:45:33.479363  <4>[    1.202742] mtk-pmic-keys: Failed to locate of_node [id: -1]

10522 16:45:33.486731  <6>[    1.209724] megasas: 07.719.03.00-rc1

10523 16:45:33.496435  <6>[    1.219697] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10524 16:45:33.503088  <6>[    1.221500] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10525 16:45:33.518971  <6>[    1.241734] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10526 16:45:33.575584  <6>[    1.292041] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9

10527 16:45:33.781331  <6>[    1.504523] Freeing initrd memory: 17220K

10528 16:45:33.791315  <6>[    1.514966] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10529 16:45:33.802731  <6>[    1.526109] tun: Universal TUN/TAP device driver, 1.6

10530 16:45:33.805710  <6>[    1.532198] thunder_xcv, ver 1.0

10531 16:45:33.809022  <6>[    1.535707] thunder_bgx, ver 1.0

10532 16:45:33.812608  <6>[    1.539204] nicpf, ver 1.0

10533 16:45:33.823374  <6>[    1.543251] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10534 16:45:33.826076  <6>[    1.550727] hns3: Copyright (c) 2017 Huawei Corporation.

10535 16:45:33.833219  <6>[    1.556333] hclge is initializing

10536 16:45:33.836147  <6>[    1.559915] e1000: Intel(R) PRO/1000 Network Driver

10537 16:45:33.842998  <6>[    1.565044] e1000: Copyright (c) 1999-2006 Intel Corporation.

10538 16:45:33.846161  <6>[    1.571059] e1000e: Intel(R) PRO/1000 Network Driver

10539 16:45:33.853276  <6>[    1.576274] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10540 16:45:33.859231  <6>[    1.582460] igb: Intel(R) Gigabit Ethernet Network Driver

10541 16:45:33.865780  <6>[    1.588110] igb: Copyright (c) 2007-2014 Intel Corporation.

10542 16:45:33.872454  <6>[    1.593947] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10543 16:45:33.879321  <6>[    1.600465] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10544 16:45:33.882462  <6>[    1.606935] sky2: driver version 1.30

10545 16:45:33.889042  <6>[    1.611970] VFIO - User Level meta-driver version: 0.3

10546 16:45:33.896947  <6>[    1.620197] usbcore: registered new interface driver usb-storage

10547 16:45:33.903279  <6>[    1.626645] usbcore: registered new device driver onboard-usb-hub

10548 16:45:33.912178  <6>[    1.635781] mt6397-rtc mt6359-rtc: registered as rtc0

10549 16:45:33.922402  <6>[    1.641248] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:45:34 UTC (1685810734)

10550 16:45:33.925241  <6>[    1.650857] i2c_dev: i2c /dev entries driver

10551 16:45:33.942459  <6>[    1.662804] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10552 16:45:33.949318  <6>[    1.673102] sdhci: Secure Digital Host Controller Interface driver

10553 16:45:33.955960  <6>[    1.679540] sdhci: Copyright(c) Pierre Ossman

10554 16:45:33.962998  <6>[    1.684987] Synopsys Designware Multimedia Card Interface Driver

10555 16:45:33.966736  <6>[    1.691557] mmc0: CQHCI version 5.10

10556 16:45:33.972450  <6>[    1.692167] sdhci-pltfm: SDHCI platform and OF driver helper

10557 16:45:33.980031  <6>[    1.703787] ledtrig-cpu: registered to indicate activity on CPUs

10558 16:45:33.990714  <6>[    1.711170] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10559 16:45:33.997483  <6>[    1.718608] usbcore: registered new interface driver usbhid

10560 16:45:34.000962  <6>[    1.724436] usbhid: USB HID core driver

10561 16:45:34.007301  <6>[    1.728677] spi_master spi0: will run message pump with realtime priority

10562 16:45:34.053699  <6>[    1.770869] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10563 16:45:34.073138  <6>[    1.786354] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10564 16:45:34.076335  <6>[    1.799924] mmc0: Command Queue Engine enabled

10565 16:45:34.083185  <6>[    1.801472] cros-ec-spi spi0.0: Chrome EC device registered

10566 16:45:34.089864  <6>[    1.804666] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10567 16:45:34.093449  <6>[    1.817886] mmcblk0: mmc0:0001 DA4128 116 GiB 

10568 16:45:34.107898  <6>[    1.828331] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10569 16:45:34.114589  <6>[    1.830351]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10570 16:45:34.121453  <6>[    1.839789] NET: Registered PF_PACKET protocol family

10571 16:45:34.124683  <6>[    1.844976] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10572 16:45:34.131361  <6>[    1.848976] 9pnet: Installing 9P2000 support

10573 16:45:34.134418  <6>[    1.854752] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10574 16:45:34.140953  <5>[    1.858676] Key type dns_resolver registered

10575 16:45:34.147843  <6>[    1.864477] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10576 16:45:34.151388  <6>[    1.868984] registered taskstats version 1

10577 16:45:34.154341  <5>[    1.879277] Loading compiled-in X.509 certificates

10578 16:45:34.189517  <4>[    1.906404] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10579 16:45:34.199652  <4>[    1.917102] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10580 16:45:34.209597  <3>[    1.929860] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10581 16:45:34.221708  <6>[    1.945216] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10582 16:45:34.228352  <6>[    1.951969] xhci-mtk 11200000.usb: xHCI Host Controller

10583 16:45:34.235025  <6>[    1.957473] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10584 16:45:34.245194  <6>[    1.965327] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10585 16:45:34.251652  <6>[    1.974778] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10586 16:45:34.258386  <6>[    1.981006] xhci-mtk 11200000.usb: xHCI Host Controller

10587 16:45:34.265144  <6>[    1.986524] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10588 16:45:34.271597  <6>[    1.994180] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10589 16:45:34.278583  <6>[    2.002119] hub 1-0:1.0: USB hub found

10590 16:45:34.282038  <6>[    2.006154] hub 1-0:1.0: 1 port detected

10591 16:45:34.291886  <6>[    2.010516] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10592 16:45:34.295103  <6>[    2.019325] hub 2-0:1.0: USB hub found

10593 16:45:34.298319  <6>[    2.023361] hub 2-0:1.0: 1 port detected

10594 16:45:34.307123  <6>[    2.030699] mtk-msdc 11f70000.mmc: Got CD GPIO

10595 16:45:34.325137  <6>[    2.045365] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10596 16:45:34.331733  <6>[    2.053414] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10597 16:45:34.341613  <4>[    2.061384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10598 16:45:34.351348  <6>[    2.071047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10599 16:45:34.358503  <6>[    2.079130] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10600 16:45:34.367998  <6>[    2.087157] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10601 16:45:34.374653  <6>[    2.095073] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10602 16:45:34.381516  <6>[    2.102908] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10603 16:45:34.391714  <6>[    2.110730] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10604 16:45:34.401348  <6>[    2.121468] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10605 16:45:34.411097  <6>[    2.129839] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10606 16:45:34.417820  <6>[    2.138196] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10607 16:45:34.428021  <6>[    2.146540] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10608 16:45:34.434180  <6>[    2.154882] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10609 16:45:34.444530  <6>[    2.163225] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10610 16:45:34.451078  <6>[    2.171567] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10611 16:45:34.460697  <6>[    2.179909] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10612 16:45:34.467298  <6>[    2.188252] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10613 16:45:34.477338  <6>[    2.196594] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10614 16:45:34.484270  <6>[    2.204937] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10615 16:45:34.493802  <6>[    2.213279] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10616 16:45:34.500501  <6>[    2.221622] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10617 16:45:34.510381  <6>[    2.229965] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10618 16:45:34.516686  <6>[    2.238310] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10619 16:45:34.523526  <6>[    2.247256] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10620 16:45:34.530937  <6>[    2.254728] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10621 16:45:34.537924  <6>[    2.261759] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10622 16:45:34.548735  <6>[    2.268858] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10623 16:45:34.555409  <6>[    2.276150] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10624 16:45:34.565293  <6>[    2.283064] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10625 16:45:34.571914  <6>[    2.292203] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10626 16:45:34.581714  <6>[    2.301330] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10627 16:45:34.591628  <6>[    2.310631] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10628 16:45:34.601242  <6>[    2.320106] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10629 16:45:34.611162  <6>[    2.329580] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10630 16:45:34.617863  <6>[    2.338706] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10631 16:45:34.627975  <6>[    2.348182] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10632 16:45:34.637729  <6>[    2.357315] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10633 16:45:34.647650  <6>[    2.366617] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10634 16:45:34.657500  <6>[    2.376783] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10635 16:45:34.668419  <6>[    2.388734] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10636 16:45:34.675077  <6>[    2.398734] Trying to probe devices needed for running init ...

10637 16:45:34.690022  <6>[    2.410368] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10638 16:45:34.717282  <6>[    2.440794] hub 2-1:1.0: USB hub found

10639 16:45:34.720449  <6>[    2.445193] hub 2-1:1.0: 3 ports detected

10640 16:45:34.841909  <6>[    2.562365] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10641 16:45:34.996304  <6>[    2.720007] hub 1-1:1.0: USB hub found

10642 16:45:35.000144  <6>[    2.724455] hub 1-1:1.0: 4 ports detected

10643 16:45:35.077923  <6>[    2.798621] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10644 16:45:35.321561  <6>[    3.042341] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10645 16:45:35.453030  <6>[    3.176909] hub 1-1.4:1.0: USB hub found

10646 16:45:35.456584  <6>[    3.181443] hub 1-1.4:1.0: 2 ports detected

10647 16:45:35.754022  <6>[    3.474311] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10648 16:45:35.938114  <6>[    3.658339] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10649 16:45:46.970459  <6>[   14.698924] ALSA device list:

10650 16:45:46.977130  <6>[   14.702181]   No soundcards found.

10651 16:45:46.989353  <6>[   14.714625] Freeing unused kernel memory: 8384K

10652 16:45:46.992657  <6>[   14.719557] Run /init as init process

10653 16:45:47.003796  Loading, please wait...

10654 16:45:47.022999  Starting version 247.3-7+deb11u2

10655 16:45:47.346947  <6>[   15.068585] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10656 16:45:47.357914  <6>[   15.082871] remoteproc remoteproc0: scp is available

10657 16:45:47.367708  <4>[   15.088338] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10658 16:45:47.374325  <6>[   15.098193] remoteproc remoteproc0: powering up scp

10659 16:45:47.384465  <4>[   15.103386] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10660 16:45:47.390683  <3>[   15.113229] remoteproc remoteproc0: request_firmware failed: -2

10661 16:45:47.397377  <3>[   15.120892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10662 16:45:47.407328  <6>[   15.128396] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10663 16:45:47.414032  <3>[   15.129044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10664 16:45:47.423908  <6>[   15.136592] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10665 16:45:47.430363  <3>[   15.144634] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10666 16:45:47.440424  <3>[   15.144767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10667 16:45:47.446824  <4>[   15.145184] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10668 16:45:47.453885  <4>[   15.145288] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10669 16:45:47.463499  <6>[   15.153463] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10670 16:45:47.469981  <6>[   15.154188] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10671 16:45:47.477241  <3>[   15.161428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10672 16:45:47.483957  <6>[   15.163987] mc: Linux media interface: v0.10

10673 16:45:47.490333  <6>[   15.171812] usbcore: registered new interface driver r8152

10674 16:45:47.497121  <3>[   15.176889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10675 16:45:47.504219  <6>[   15.185169] videodev: Linux video capture interface: v2.00

10676 16:45:47.511247  <4>[   15.191676] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10677 16:45:47.518082  <4>[   15.191676] Fallback method does not support PEC.

10678 16:45:47.524781  <3>[   15.193074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10679 16:45:47.534391  <3>[   15.206771] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10680 16:45:47.541365  <3>[   15.209146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10681 16:45:47.551014  <3>[   15.235800] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10682 16:45:47.557640  <3>[   15.246799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10683 16:45:47.567606  <6>[   15.250482] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10684 16:45:47.573939  <6>[   15.274726] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10685 16:45:47.583985  <3>[   15.280475] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10686 16:45:47.590476  <6>[   15.287590] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10687 16:45:47.593907  <6>[   15.287598] pci_bus 0000:00: root bus resource [bus 00-ff]

10688 16:45:47.603625  <6>[   15.287606] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10689 16:45:47.613667  <6>[   15.287611] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10690 16:45:47.620511  <6>[   15.287643] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10691 16:45:47.626706  <6>[   15.287661] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10692 16:45:47.630232  <6>[   15.287744] pci 0000:00:00.0: supports D1 D2

10693 16:45:47.636849  <6>[   15.287748] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10694 16:45:47.646304  <6>[   15.289668] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10695 16:45:47.656686  <6>[   15.295572] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003

10696 16:45:47.666392  <6>[   15.296020] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10697 16:45:47.673273  <3>[   15.297746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10698 16:45:47.679582  <6>[   15.305007] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10699 16:45:47.689450  <4>[   15.309648] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2

10700 16:45:47.696196  <4>[   15.309659] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)

10701 16:45:47.705745  <3>[   15.312961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10702 16:45:47.712961  <6>[   15.319928] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10703 16:45:47.719335  <3>[   15.325786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10704 16:45:47.725570  <6>[   15.326177] usbcore: registered new interface driver cdc_ether

10705 16:45:47.732160  <6>[   15.332753] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10706 16:45:47.739044  <6>[   15.333418] Bluetooth: Core ver 2.22

10707 16:45:47.742159  <6>[   15.333474] NET: Registered PF_BLUETOOTH protocol family

10708 16:45:47.749111  <6>[   15.333476] Bluetooth: HCI device and connection manager initialized

10709 16:45:47.755364  <6>[   15.333494] Bluetooth: HCI socket layer initialized

10710 16:45:47.758937  <6>[   15.333501] Bluetooth: L2CAP socket layer initialized

10711 16:45:47.765261  <6>[   15.333514] Bluetooth: SCO socket layer initialized

10712 16:45:47.772294  <3>[   15.342654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10713 16:45:47.778672  <6>[   15.342898] usbcore: registered new interface driver r8153_ecm

10714 16:45:47.784988  <6>[   15.348931] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10715 16:45:47.795569  <3>[   15.356395] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10716 16:45:47.798469  <6>[   15.356482] r8152 2-1.3:1.0 eth0: v1.12.13

10717 16:45:47.805121  <6>[   15.361041] pci 0000:01:00.0: supports D1 D2

10718 16:45:47.808439  <6>[   15.364920] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0

10719 16:45:47.818120  <3>[   15.367815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10720 16:45:47.825327  <6>[   15.369210] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10721 16:45:47.837794  <6>[   15.370577] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10722 16:45:47.844711  <6>[   15.370729] usbcore: registered new interface driver uvcvideo

10723 16:45:47.850962  <6>[   15.376070] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10724 16:45:47.858101  <3>[   15.386161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10725 16:45:47.864482  <6>[   15.396200] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10726 16:45:47.870983  <6>[   15.396342] usbcore: registered new interface driver btusb

10727 16:45:47.880697  <4>[   15.397144] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10728 16:45:47.887419  <3>[   15.397159] Bluetooth: hci0: Failed to load firmware file (-2)

10729 16:45:47.894160  <3>[   15.397163] Bluetooth: hci0: Failed to set up firmware (-2)

10730 16:45:47.904275  <4>[   15.397168] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10731 16:45:47.910831  <3>[   15.403308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10732 16:45:47.917173  <6>[   15.406290] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10733 16:45:47.927083  <6>[   15.406321] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10734 16:45:47.933504  <6>[   15.406329] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10735 16:45:47.943445  <6>[   15.406341] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10736 16:45:47.950222  <6>[   15.406357] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10737 16:45:47.956817  <6>[   15.406373] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10738 16:45:47.963136  <6>[   15.406388] pci 0000:00:00.0: PCI bridge to [bus 01]

10739 16:45:47.969818  <6>[   15.406395] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10740 16:45:47.976614  <6>[   15.406529] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10741 16:45:47.983142  <6>[   15.407335] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

10742 16:45:47.990076  <6>[   15.407896] pcieport 0000:00:00.0: AER: enabled with IRQ 282

10743 16:45:48.030691  <5>[   15.752074] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10744 16:45:48.049511  <5>[   15.771211] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10745 16:45:48.055993  <4>[   15.778114] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10746 16:45:48.062401  <6>[   15.786990] cfg80211: failed to load regulatory.db

10747 16:45:48.113479  <6>[   15.835656] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10748 16:45:48.120133  <6>[   15.843242] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10749 16:45:48.141166  <6>[   15.866349] mt7921e 0000:01:00.0: ASIC revision: 79610010

10750 16:45:48.247218  <4>[   15.966009] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10751 16:45:48.261005  Begin: Loading essential drivers ... done.

10752 16:45:48.268064  Begin: Running /scripts/init-premount ... done.

10753 16:45:48.274031  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.

10754 16:45:48.280785  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available

10755 16:45:48.284227  Device /sys/class/net/enx002432307c7b found

10756 16:45:48.287816  done.

10757 16:45:48.348119  IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP

10758 16:45:48.366100  <4>[   16.084784] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10759 16:45:48.485150  <4>[   16.204031] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10760 16:45:48.601357  <4>[   16.319986] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10761 16:45:48.717017  <4>[   16.435875] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10762 16:45:48.833337  <4>[   16.551834] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10763 16:45:48.949350  <4>[   16.667768] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10764 16:45:49.064775  <4>[   16.783694] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10765 16:45:49.180982  <4>[   16.899702] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10766 16:45:49.296672  <4>[   17.015683] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10767 16:45:49.303995  <6>[   17.029405] r8152 2-1.3:1.0 enx002432307c7b: carrier on

10768 16:45:49.404281  <3>[   17.129533] mt7921e 0000:01:00.0: hardware init failed

10769 16:45:49.415940  IP-Config: no response after 2 secs - giving up

10770 16:45:49.456315  IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP

10771 16:45:49.459421  IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):

10772 16:45:49.466032   address: 192.168.201.14   broadcast: 192.168.201.255  netmask: 255.255.255.0   

10773 16:45:49.476120   gateway: 192.168.201.1    dns0     : 192.168.201.1    dns1   : 0.0.0.0         

10774 16:45:49.482544   host   : mt8192-asurada-spherion-r0-cbg-2                                

10775 16:45:49.489630   domain : lava-rack                                                       

10776 16:45:49.492454   rootserver: 192.168.201.1 rootpath: 

10777 16:45:49.492559   filename  : 

10778 16:45:49.519762  done.

10779 16:45:49.527435  Begin: Running /scripts/nfs-bottom ... done.

10780 16:45:49.544795  Begin: Running /scripts/init-bottom ... done.

10781 16:45:50.679718  <6>[   18.405026] NET: Registered PF_INET6 protocol family

10782 16:45:50.686891  <6>[   18.412187] Segment Routing with IPv6

10783 16:45:50.690464  <6>[   18.416218] In-situ OAM (IOAM) with IPv6

10784 16:45:50.813884  <30>[   18.519204] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10785 16:45:50.817144  <30>[   18.543010] systemd[1]: Detected architecture arm64.

10786 16:45:50.838975  

10787 16:45:50.842357  Welcome to Debian GNU/Linux 11 (bullseye)!

10788 16:45:50.842884  

10789 16:45:50.860199  <30>[   18.585187] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10790 16:45:51.517582  <30>[   19.239682] systemd[1]: Queued start job for default target Graphical Interface.

10791 16:45:51.546267  <30>[   19.271383] systemd[1]: Created slice system-getty.slice.

10792 16:45:51.552187  [  OK  ] Created slice system-getty.slice.

10793 16:45:51.569606  <30>[   19.294998] systemd[1]: Created slice system-modprobe.slice.

10794 16:45:51.575931  [  OK  ] Created slice system-modprobe.slice.

10795 16:45:51.593650  <30>[   19.318922] systemd[1]: Created slice system-serial\x2dgetty.slice.

10796 16:45:51.603407  [  OK  ] Created slice system-serial\x2dgetty.slice.

10797 16:45:51.618369  <30>[   19.343398] systemd[1]: Created slice User and Session Slice.

10798 16:45:51.624787  [  OK  ] Created slice User and Session Slice.

10799 16:45:51.644971  <30>[   19.366852] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10800 16:45:51.654657  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10801 16:45:51.672527  <30>[   19.394882] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10802 16:45:51.679801  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10803 16:45:51.699773  <30>[   19.418492] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10804 16:45:51.706477  <30>[   19.430527] systemd[1]: Reached target Local Encrypted Volumes.

10805 16:45:51.712828  [  OK  ] Reached target Local Encrypted Volumes.

10806 16:45:51.729127  <30>[   19.454850] systemd[1]: Reached target Paths.

10807 16:45:51.732507  [  OK  ] Reached target Paths.

10808 16:45:51.748664  <30>[   19.474389] systemd[1]: Reached target Remote File Systems.

10809 16:45:51.755459  [  OK  ] Reached target Remote File Systems.

10810 16:45:51.768777  <30>[   19.494351] systemd[1]: Reached target Slices.

10811 16:45:51.772308  [  OK  ] Reached target Slices.

10812 16:45:51.788918  <30>[   19.514414] systemd[1]: Reached target Swap.

10813 16:45:51.792369  [  OK  ] Reached target Swap.

10814 16:45:51.812503  <30>[   19.534732] systemd[1]: Listening on initctl Compatibility Named Pipe.

10815 16:45:51.818918  [  OK  ] Listening on initctl Compatibility Named Pipe.

10816 16:45:51.825442  <30>[   19.550266] systemd[1]: Listening on Journal Audit Socket.

10817 16:45:51.832633  [  OK  ] Listening on Journal Audit Socket.

10818 16:45:51.845909  <30>[   19.571488] systemd[1]: Listening on Journal Socket (/dev/log).

10819 16:45:51.852521  [  OK  ] Listening on Journal Socket (/dev/log).

10820 16:45:51.869727  <30>[   19.595188] systemd[1]: Listening on Journal Socket.

10821 16:45:51.876230  [  OK  ] Listening on Journal Socket.

10822 16:45:51.894368  <30>[   19.615958] systemd[1]: Listening on Network Service Netlink Socket.

10823 16:45:51.900852  [  OK  ] Listening on Network Service Netlink Socket.

10824 16:45:51.916210  <30>[   19.641676] systemd[1]: Listening on udev Control Socket.

10825 16:45:51.923762  [  OK  ] Listening on udev Control Socket.

10826 16:45:51.937692  <30>[   19.662656] systemd[1]: Listening on udev Kernel Socket.

10827 16:45:51.943708  [  OK  ] Listening on udev Kernel Socket.

10828 16:45:51.993513  <30>[   19.718610] systemd[1]: Mounting Huge Pages File System...

10829 16:45:51.999666           Mounting Huge Pages File System...

10830 16:45:52.015696  <30>[   19.741018] systemd[1]: Mounting POSIX Message Queue File System...

10831 16:45:52.022118           Mounting POSIX Message Queue File System...

10832 16:45:52.039009  <30>[   19.764634] systemd[1]: Mounting Kernel Debug File System...

10833 16:45:52.045793           Mounting Kernel Debug File System...

10834 16:45:52.064448  <30>[   19.786670] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10835 16:45:52.076455  <30>[   19.798920] systemd[1]: Starting Create list of static device nodes for the current kernel...

10836 16:45:52.082995           Starting Create list of st…odes for the current kernel...

10837 16:45:52.104251  <30>[   19.829569] systemd[1]: Starting Load Kernel Module configfs...

10838 16:45:52.110739           Starting Load Kernel Module configfs...

10839 16:45:52.127156  <30>[   19.852820] systemd[1]: Starting Load Kernel Module drm...

10840 16:45:52.133471           Starting Load Kernel Module drm...

10841 16:45:52.151402  <30>[   19.876905] systemd[1]: Starting Load Kernel Module fuse...

10842 16:45:52.157717           Starting Load Kernel Module fuse...

10843 16:45:52.189673  <6>[   19.915187] fuse: init (API version 7.37)

10844 16:45:52.199092  <30>[   19.920927] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10845 16:45:52.209079  <30>[   19.934658] systemd[1]: Starting Journal Service...

10846 16:45:52.211948           Starting Journal Service...

10847 16:45:52.237448  <30>[   19.963407] systemd[1]: Starting Load Kernel Modules...

10848 16:45:52.244200           Starting Load Kernel Modules...

10849 16:45:52.262398  <30>[   19.984796] systemd[1]: Starting Remount Root and Kernel File Systems...

10850 16:45:52.268963           Starting Remount Root and Kernel File Systems...

10851 16:45:52.283909  <30>[   20.009691] systemd[1]: Starting Coldplug All udev Devices...

10852 16:45:52.290556           Starting Coldplug All udev Devices...

10853 16:45:52.308620  <30>[   20.033443] systemd[1]: Mounted Huge Pages File System.

10854 16:45:52.314557  [  OK  ] Mounted Huge Pages File System.

10855 16:45:52.333395  <30>[   20.058888] systemd[1]: Mounted POSIX Message Queue File System.

10856 16:45:52.339767  [  OK  ] Mounted POSIX Message Queue File System.

10857 16:45:52.357570  <30>[   20.083295] systemd[1]: Mounted Kernel Debug File System.

10858 16:45:52.364768  [  OK  ] Mounted Kernel Debug File System.

10859 16:45:52.375981  <3>[   20.098517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10860 16:45:52.386069  <30>[   20.108678] systemd[1]: Finished Create list of static device nodes for the current kernel.

10861 16:45:52.396291  [  OK  ] Finished Create list of st… nodes for the current kernel.

10862 16:45:52.407186  <3>[   20.129371] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10863 16:45:52.413675  <30>[   20.139311] systemd[1]: modprobe@configfs.service: Succeeded.

10864 16:45:52.420999  <30>[   20.146049] systemd[1]: Finished Load Kernel Module configfs.

10865 16:45:52.426862  [  OK  ] Finished Load Kernel Module configfs.

10866 16:45:52.441860  <30>[   20.167130] systemd[1]: modprobe@drm.service: Succeeded.

10867 16:45:52.448717  <30>[   20.173407] systemd[1]: Finished Load Kernel Module drm.

10868 16:45:52.458558  <3>[   20.176537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10869 16:45:52.461970  [  OK  ] Finished Load Kernel Module drm.

10870 16:45:52.477812  <30>[   20.203107] systemd[1]: modprobe@fuse.service: Succeeded.

10871 16:45:52.484588  <30>[   20.209703] systemd[1]: Finished Load Kernel Module fuse.

10872 16:45:52.494643  <3>[   20.211186] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10873 16:45:52.501159  [  OK  ] Finished Load Kernel Module fuse.

10874 16:45:52.514764  <30>[   20.239287] systemd[1]: Finished Load Kernel Modules.

10875 16:45:52.524466  [  OK  [<3>[   20.245658] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10876 16:45:52.528202  0m] Finished Load Kernel Modules.

10877 16:45:52.542114  <30>[   20.267510] systemd[1]: Finished Remount Root and Kernel File Systems.

10878 16:45:52.555776  [  OK  [<3>[   20.276157] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10879 16:45:52.559089  0m] Finished Remount Root and Kernel File Systems.

10880 16:45:52.584434  <3>[   20.306573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10881 16:45:52.604780  <30>[   20.329891] systemd[1]: Mounting FUSE Control File System...

10882 16:45:52.617928           Mounting FUSE <3>[   20.337750] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10883 16:45:52.620993  Control File System...

10884 16:45:52.635633  <30>[   20.360839] systemd[1]: Mounting Kernel Configuration File System...

10885 16:45:52.648701           Mountin<3>[   20.368813] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10886 16:45:52.651968  g Kernel Configuration File System...

10887 16:45:52.676592  <3>[   20.398517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10888 16:45:52.686449  <30>[   20.400423] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.

10889 16:45:52.696187  <30>[   20.416322] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.

10890 16:45:52.702674  <30>[   20.428542] systemd[1]: Starting Load/Save Random Seed...

10891 16:45:52.712843  <3>[   20.428641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10892 16:45:52.715967           Starting Load/Save Random Seed...

10893 16:45:52.736624  <30>[   20.461343] systemd[1]: Starting Apply Kernel Variables...

10894 16:45:52.746393           Startin<3>[   20.467767] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10895 16:45:52.756681  g Apply<3>[   20.468499] power_supply sbs-5-000b: driver failed to report `status' property: -6

10896 16:45:52.759821   Kernel Variables...

10897 16:45:52.781503  <30>[   20.507235] systemd[1]: Starting Create System Users...

10898 16:45:52.788303           Starting Create System Users...

10899 16:45:52.806686  <30>[   20.532209] systemd[1]: Mounted FUSE Control File System.

10900 16:45:52.813012  [  OK  ] Mounted FUSE Control File System.

10901 16:45:52.834069  <30>[   20.558716] systemd[1]: Mounted Kernel Configuration File System.

10902 16:45:52.853932  [  OK  [<4>[   20.566138] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent

10903 16:45:52.860077  <3>[   20.582407] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5

10904 16:45:52.863220  0m] Mounted Kernel Configuration File System.

10905 16:45:52.881832  <30>[   20.607008] systemd[1]: Started Journal Service.

10906 16:45:52.885152  [  OK  ] Started Journal Service.

10907 16:45:52.907251  [FAILED] Failed to start Coldplug All udev Devices.

10908 16:45:52.921527  See 'systemctl status systemd-udev-trigger.service' for details.

10909 16:45:52.937977  [  OK  ] Finished Load/Save Random Seed.

10910 16:45:52.953361  [  OK  ] Finished Apply Kernel Variables.

10911 16:45:52.973538  [  OK  ] Finished Create System Users.

10912 16:45:53.017807           Starting Flush Journal to Persistent Storage...

10913 16:45:53.039317           Starting Create Static Device Nodes in /dev...

10914 16:45:53.082560  <46>[   20.804874] systemd-journald[292]: Received client request to flush runtime journal.

10915 16:45:53.831920  [  OK  ] Finished Create Static Device Nodes in /dev.

10916 16:45:53.845639  [  OK  ] Reached target Local File Systems (Pre).

10917 16:45:53.860518  [  OK  ] Reached target Local File Systems.

10918 16:45:53.929467           Starting Rule-based Manage…for Device Events and Files...

10919 16:45:54.468039  [  OK  ] Finished Flush Journal to Persistent Storage.

10920 16:45:54.505071           Starting Create Volatile Files and Directories...

10921 16:45:54.569578  [  OK  ] Started Rule-based Manager for Device Events and Files.

10922 16:45:54.634233           Starting Network Service...

10923 16:45:54.915143  [  OK  ] Found device /dev/ttyS0.

10924 16:45:54.939021  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10925 16:45:54.985011           Starting Load/Save Screen …of leds:white:kbd_backlight...

10926 16:45:55.178592  <6>[   22.903831] remoteproc remoteproc0: powering up scp

10927 16:45:55.220617  <4>[   22.942971] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10928 16:45:55.227104  <3>[   22.952859] remoteproc remoteproc0: request_firmware failed: -2

10929 16:45:55.236922  <3>[   22.959038] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!

10930 16:45:55.364855  [  OK  ] Finished Create Volatile Files and Directories.

10931 16:45:55.385502  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10932 16:45:55.401378  [  OK  ] Started Network Service.

10933 16:45:55.422077  [  OK  ] Reached target Bluetooth.

10934 16:45:55.440490  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10935 16:45:55.481508           Starting Network Name Resolution...

10936 16:45:55.508555           Starting Network Time Synchronization...

10937 16:45:55.527622           Starting Update UTMP about System Boot/Shutdown...

10938 16:45:55.548741           Starting Load/Save RF Kill Switch Status...

10939 16:45:55.583483  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10940 16:45:55.604314  [  OK  ] Started Load/Save RF Kill Switch Status.

10941 16:45:55.784512  [  OK  ] Started Network Time Synchronization.

10942 16:45:55.805152  [  OK  ] Reached target System Initialization.

10943 16:45:55.828310  [  OK  ] Started Daily Cleanup of Temporary Directories.

10944 16:45:55.841169  [  OK  ] Reached target System Time Set.

10945 16:45:55.861195  [  OK  ] Reached target System Time Synchronized.

10946 16:45:55.989126  [  OK  ] Started Daily apt download activities.

10947 16:45:56.042913  [  OK  ] Started Daily apt upgrade and clean activities.

10948 16:45:56.075803  [  OK  ] Started Periodic ext4 Onli…ata Check for All Filesystems.

10949 16:45:56.539129  [  OK  ] Started Discard unused blocks once a week.

10950 16:45:56.552406  [  OK  ] Reached target Timers.

10951 16:45:56.807904  [  OK  ] Listening on D-Bus System Message Bus Socket.

10952 16:45:56.825208  [  OK  ] Reached target Sockets.

10953 16:45:56.845191  [  OK  ] Reached target Basic System.

10954 16:45:56.885172  [  OK  ] Started D-Bus System Message Bus.

10955 16:45:57.201489           Starting Remove Stale Onli…t4 Metadata Check Snapshots...

10956 16:45:57.265032           Starting User Login Management...

10957 16:45:57.281338  [  OK  ] Started Network Name Resolution.

10958 16:45:57.298327  [  OK  ] Reached target Network.

10959 16:45:57.315765  [  OK  ] Reached target Host and Network Name Lookups.

10960 16:45:57.356986           Starting Permit User Sessions...

10961 16:45:57.453470  [  OK  ] Finished Permit User Sessions.

10962 16:45:57.492851  [  OK  ] Started Getty on tty1.

10963 16:45:57.511159  [  OK  ] Started Serial Getty on ttyS0.

10964 16:45:57.528636  [  OK  ] Reached target Login Prompts.

10965 16:45:57.552093  [  OK  ] Finished Remove Stale Onli…ext4 Metadata Check Snapshots.

10966 16:45:57.572401  [  OK  ] Started User Login Management.

10967 16:45:57.590354  [  OK  ] Reached target Multi-User System.

10968 16:45:57.608900  [  OK  ] Reached target Graphical Interface.

10969 16:45:57.652694           Starting Update UTMP about System Runlevel Changes...

10970 16:45:57.700186  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10971 16:45:57.810610  

10972 16:45:57.811340  

10973 16:45:57.814063  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10974 16:45:57.814638  

10975 16:45:57.817117  debian-bullseye-arm64 login: root (automatic login)

10976 16:45:57.817763  

10977 16:45:57.818291  

10978 16:45:58.171591  Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun  3 16:27:28 UTC 2023 aarch64

10979 16:45:58.171748  

10980 16:45:58.178298  The programs included with the Debian GNU/Linux system are free software;

10981 16:45:58.184614  the exact distribution terms for each program are described in the

10982 16:45:58.188149  individual files in /usr/share/doc/*/copyright.

10983 16:45:58.188290  

10984 16:45:58.194578  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

10985 16:45:58.197733  permitted by applicable law.

10986 16:45:59.115865  Matched prompt #10: / #
10988 16:45:59.116154  Setting prompt string to ['/ #']
10989 16:45:59.116249  end: 2.2.5.1 login-action (duration 00:00:28) [common]
10991 16:45:59.116441  end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10992 16:45:59.116530  start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
10993 16:45:59.116604  Setting prompt string to ['/ #']
10994 16:45:59.116664  Forcing a shell prompt, looking for ['/ #']
10996 16:45:59.166951  / # 

10997 16:45:59.167457  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 16:45:59.167834  Waiting using forced prompt support (timeout 00:02:30)
10999 16:45:59.173295  

11000 16:45:59.174036  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11001 16:45:59.174489  start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11003 16:45:59.275912  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576285/extract-nfsrootfs-7_pn6cuh'

11004 16:45:59.283457  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576285/extract-nfsrootfs-7_pn6cuh'

11006 16:45:59.385130  / # export NFS_SERVER_IP='192.168.201.1'

11007 16:45:59.391312  export NFS_SERVER_IP='192.168.201.1'

11008 16:45:59.392285  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11009 16:45:59.392922  end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11010 16:45:59.393495  end: 2 depthcharge-action (duration 00:01:42) [common]
11011 16:45:59.394089  start: 3 lava-test-retry (timeout 00:07:28) [common]
11012 16:45:59.394673  start: 3.1 lava-test-shell (timeout 00:07:28) [common]
11013 16:45:59.395154  Using namespace: common
11015 16:45:59.496571  / # #

11016 16:45:59.497264  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11017 16:45:59.503292  #

11018 16:45:59.504229  Using /lava-10576285
11020 16:45:59.605675  / # export SHELL=/bin/bash

11021 16:45:59.612016  export SHELL=/bin/bash

11023 16:45:59.713693  / # . /lava-10576285/environment

11024 16:45:59.720085  . /lava-10576285/environment

11026 16:45:59.827423  / # /lava-10576285/bin/lava-test-runner /lava-10576285/0

11027 16:45:59.828082  Test shell timeout: 10s (minimum of the action and connection timeout)
11028 16:45:59.833901  /lava-10576285/bin/lava-test-runner /lava-10576285/0

11029 16:46:00.132687  + export TESTRUN_ID=0_timesync-off

11030 16:46:00.135658  + TESTRUN_ID=0_timesync-off

11031 16:46:00.138984  + cd /lava-10576285/0/tests/0_timesync-off

11032 16:46:00.142601  ++ cat uuid

11033 16:46:00.152279  + UUID=10576285_1.6.2.3.1

11034 16:46:00.152720  + set +x

11035 16:46:00.159499  <LAVA_SIGNAL_STARTRUN 0_timesync-off 10576285_1.6.2.3.1>

11036 16:46:00.160197  Received signal: <STARTRUN> 0_timesync-off 10576285_1.6.2.3.1
11037 16:46:00.160601  Starting test lava.0_timesync-off (10576285_1.6.2.3.1)
11038 16:46:00.161121  Skipping test definition patterns.
11039 16:46:00.162577  + systemctl stop systemd-timesyncd

11040 16:46:00.209668  + set +x

11041 16:46:00.212570  <LAVA_SIGNAL_ENDRUN 0_timesync-off 10576285_1.6.2.3.1>

11042 16:46:00.213267  Received signal: <ENDRUN> 0_timesync-off 10576285_1.6.2.3.1
11043 16:46:00.213732  Ending use of test pattern.
11044 16:46:00.214110  Ending test lava.0_timesync-off (10576285_1.6.2.3.1), duration 0.05
11046 16:46:00.303166  + export TESTRUN_ID=1_kselftest-tpm2

11047 16:46:00.306485  + TESTRUN_ID=1_kselftest-tpm2

11048 16:46:00.312414  + cd /lava-10576285/0/tests/1_kselftest-tpm2

11049 16:46:00.312848  ++ cat uuid

11050 16:46:00.325440  + UUID=10576285_1.6.2.3.5

11051 16:46:00.325934  + set +x

11052 16:46:00.332152  <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10576285_1.6.2.3.5>

11053 16:46:00.332836  Received signal: <STARTRUN> 1_kselftest-tpm2 10576285_1.6.2.3.5
11054 16:46:00.333218  Starting test lava.1_kselftest-tpm2 (10576285_1.6.2.3.5)
11055 16:46:00.333617  Skipping test definition patterns.
11056 16:46:00.335142  + cd ./automated/linux/kselftest/

11057 16:46:00.361435  + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1

11058 16:46:00.414556  INFO: install_deps skipped

11059 16:46:00.535208  --2023-06-03 16:46:00--  http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz

11060 16:46:00.553494  Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28

11061 16:46:00.699683  Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.

11062 16:46:00.844609  HTTP request sent, awaiting response... 200 OK

11063 16:46:00.847415  Length: 2713064 (2.6M) [application/octet-stream]

11064 16:46:00.850913  Saving to: 'kselftest.tar.xz'

11065 16:46:00.851400  

11066 16:46:00.851746  

11067 16:46:01.132910  kselftest.tar.xz      0%[                    ]       0  --.-KB/s               

11068 16:46:01.422243  kselftest.tar.xz      1%[                    ]  44.98K   156KB/s               

11069 16:46:01.856507  kselftest.tar.xz      8%[>                   ] 217.50K   377KB/s               

11070 16:46:02.153671  kselftest.tar.xz     33%[=====>              ] 875.03K   866KB/s               

11071 16:46:02.159706  kselftest.tar.xz     76%[==============>     ]   1.99M  1.52MB/s               

11072 16:46:02.166293  kselftest.tar.xz    100%[===================>]   2.59M  1.97MB/s    in 1.3s    

11073 16:46:02.166380  

11074 16:46:02.401504  2023-06-03 16:46:02 (1.97 MB/s) - 'kselftest.tar.xz' saved [2713064/2713064]

11075 16:46:02.401637  

11076 16:46:07.899784  skiplist:

11077 16:46:07.902874  ========================================

11078 16:46:07.906429  ========================================

11079 16:46:07.951965  tpm2:test_smoke.sh

11080 16:46:07.954979  tpm2:test_space.sh

11081 16:46:07.971579  ============== Tests to run ===============

11082 16:46:07.974382  tpm2:test_smoke.sh

11083 16:46:07.974474  tpm2:test_space.sh

11084 16:46:07.977957  ===========End Tests to run ===============

11085 16:46:08.078942  <12>[   35.806170] kselftest: Running tests in tpm2

11086 16:46:08.089544  TAP version 13

11087 16:46:08.104034  1..2

11088 16:46:08.142466  # selftests: tpm2: test_smoke.sh

11089 16:46:09.346822  # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR

11090 16:46:09.350196  # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR

11091 16:46:09.356216  # Exception ignored in: <function Client.__del__ at 0xffffae09ad30>

11092 16:46:09.359592  # Traceback (most recent call last):

11093 16:46:09.369905  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11094 16:46:09.373011  #     if self.tpm:

11095 16:46:09.377208  # AttributeError: 'Client' object has no attribute 'tpm'

11096 16:46:09.382847  # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR

11097 16:46:09.386192  # Exception ignored in: <function Client.__del__ at 0xffffae09ad30>

11098 16:46:09.389330  # Traceback (most recent call last):

11099 16:46:09.399645  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11100 16:46:09.402994  #     if self.tpm:

11101 16:46:09.405825  # AttributeError: 'Client' object has no attribute 'tpm'

11102 16:46:09.412742  # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR

11103 16:46:09.419734  # Exception ignored in: <function Client.__del__ at 0xffffae09ad30>

11104 16:46:09.423098  # Traceback (most recent call last):

11105 16:46:09.432281  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11106 16:46:09.432791  #     if self.tpm:

11107 16:46:09.439220  # AttributeError: 'Client' object has no attribute 'tpm'

11108 16:46:09.442413  # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR

11109 16:46:09.449089  # Exception ignored in: <function Client.__del__ at 0xffffae09ad30>

11110 16:46:09.452851  # Traceback (most recent call last):

11111 16:46:09.462868  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11112 16:46:09.465545  #     if self.tpm:

11113 16:46:09.469401  # AttributeError: 'Client' object has no attribute 'tpm'

11114 16:46:09.475691  # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR

11115 16:46:09.478783  # Exception ignored in: <function Client.__del__ at 0xffffae09ad30>

11116 16:46:09.482240  # Traceback (most recent call last):

11117 16:46:09.492364  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11118 16:46:09.495354  #     if self.tpm:

11119 16:46:09.498519  # AttributeError: 'Client' object has no attribute 'tpm'

11120 16:46:09.505512  # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR

11121 16:46:09.512097  # Exception ignored in: <function Client.__del__ at 0xffffae09ad30>

11122 16:46:09.515421  # Traceback (most recent call last):

11123 16:46:09.525064  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11124 16:46:09.525640  #     if self.tpm:

11125 16:46:09.531698  # AttributeError: 'Client' object has no attribute 'tpm'

11126 16:46:09.535073  # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR

11127 16:46:09.541882  # Exception ignored in: <function Client.__del__ at 0xffffae09ad30>

11128 16:46:09.545157  # Traceback (most recent call last):

11129 16:46:09.554895  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11130 16:46:09.558475  #     if self.tpm:

11131 16:46:09.561562  # AttributeError: 'Client' object has no attribute 'tpm'

11132 16:46:09.568849  # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR

11133 16:46:09.574679  # Exception ignored in: <function Client.__del__ at 0xffffae09ad30>

11134 16:46:09.578277  # Traceback (most recent call last):

11135 16:46:09.587670  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11136 16:46:09.588099  #     if self.tpm:

11137 16:46:09.594152  # AttributeError: 'Client' object has no attribute 'tpm'

11138 16:46:09.594619  # 

11139 16:46:09.601145  # ======================================================================

11140 16:46:09.607601  # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)

11141 16:46:09.610565  # ----------------------------------------------------------------------

11142 16:46:09.614053  # Traceback (most recent call last):

11143 16:46:09.624066  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp

11144 16:46:09.630712  #     self.root_key = self.client.create_root_key()

11145 16:46:09.641240  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11146 16:46:09.647093  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11147 16:46:09.657155  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11148 16:46:09.660998  #     raise ProtocolError(cc, rc)

11149 16:46:09.669911  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11150 16:46:09.670491  # 

11151 16:46:09.673336  # ======================================================================

11152 16:46:09.677230  # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)

11153 16:46:09.684014  # ----------------------------------------------------------------------

11154 16:46:09.686632  # Traceback (most recent call last):

11155 16:46:09.696373  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11156 16:46:09.699504  #     self.client = tpm2.Client()

11157 16:46:09.709714  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11158 16:46:09.712950  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11159 16:46:09.719531  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11160 16:46:09.719613  # 

11161 16:46:09.726173  # ======================================================================

11162 16:46:09.732793  # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)

11163 16:46:09.735955  # ----------------------------------------------------------------------

11164 16:46:09.739504  # Traceback (most recent call last):

11165 16:46:09.752590  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11166 16:46:09.752702  #     self.client = tpm2.Client()

11167 16:46:09.762709  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11168 16:46:09.768913  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11169 16:46:09.772693  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11170 16:46:09.776070  # 

11171 16:46:09.782854  # ======================================================================

11172 16:46:09.785860  # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)

11173 16:46:09.792932  # ----------------------------------------------------------------------

11174 16:46:09.795488  # Traceback (most recent call last):

11175 16:46:09.805750  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11176 16:46:09.809231  #     self.client = tpm2.Client()

11177 16:46:09.818657  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11178 16:46:09.822336  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11179 16:46:09.828691  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11180 16:46:09.829113  # 

11181 16:46:09.835241  # ======================================================================

11182 16:46:09.842160  # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)

11183 16:46:09.848765  # ----------------------------------------------------------------------

11184 16:46:09.851897  # Traceback (most recent call last):

11185 16:46:09.861500  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11186 16:46:09.865063  #     self.client = tpm2.Client()

11187 16:46:09.874942  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11188 16:46:09.878482  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11189 16:46:09.884817  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11190 16:46:09.885334  # 

11191 16:46:09.891999  # ======================================================================

11192 16:46:09.894751  # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)

11193 16:46:09.901481  # ----------------------------------------------------------------------

11194 16:46:09.904764  # Traceback (most recent call last):

11195 16:46:09.914491  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11196 16:46:09.917885  #     self.client = tpm2.Client()

11197 16:46:09.927931  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11198 16:46:09.931011  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11199 16:46:09.937509  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11200 16:46:09.938030  # 

11201 16:46:09.944121  # ======================================================================

11202 16:46:09.947664  # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)

11203 16:46:09.954492  # ----------------------------------------------------------------------

11204 16:46:09.957556  # Traceback (most recent call last):

11205 16:46:09.967511  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11206 16:46:09.970381  #     self.client = tpm2.Client()

11207 16:46:09.981122  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11208 16:46:09.987542  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11209 16:46:09.990635  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11210 16:46:09.990816  # 

11211 16:46:09.997500  # ======================================================================

11212 16:46:10.003640  # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)

11213 16:46:10.010638  # ----------------------------------------------------------------------

11214 16:46:10.014697  # Traceback (most recent call last):

11215 16:46:10.023860  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11216 16:46:10.026717  #     self.client = tpm2.Client()

11217 16:46:10.039728  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11218 16:46:10.040152  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11219 16:46:10.047064  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11220 16:46:10.047512  # 

11221 16:46:10.057241  # ======================================================================

11222 16:46:10.060029  # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)

11223 16:46:10.063314  # ----------------------------------------------------------------------

11224 16:46:10.068054  # Traceback (most recent call last):

11225 16:46:10.079796  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11226 16:46:10.082699  #     self.client = tpm2.Client()

11227 16:46:10.092557  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11228 16:46:10.096488  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11229 16:46:10.102644  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11230 16:46:10.103137  # 

11231 16:46:10.109154  # ----------------------------------------------------------------------

11232 16:46:10.109575  # Ran 9 tests in 0.027s

11233 16:46:10.112214  # 

11234 16:46:10.112635  # FAILED (errors=9)

11235 16:46:10.115800  # test_async (tpm2_tests.AsyncTest) ... ok

11236 16:46:10.122656  # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok

11237 16:46:10.123228  # 

11238 16:46:10.128852  # ----------------------------------------------------------------------

11239 16:46:10.132113  # Ran 2 tests in 0.029s

11240 16:46:10.132533  # 

11241 16:46:10.132864  # OK

11242 16:46:10.135658  ok 1 selftests: tpm2: test_smoke.sh

11243 16:46:10.138715  # selftests: tpm2: test_space.sh

11244 16:46:10.142135  # test_flush_context (tpm2_tests.SpaceTest) ... ERROR

11245 16:46:10.145459  # test_get_handles (tpm2_tests.SpaceTest) ... ERROR

11246 16:46:10.152249  # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR

11247 16:46:10.155370  # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR

11248 16:46:10.155845  # 

11249 16:46:10.162346  # ======================================================================

11250 16:46:10.168941  # ERROR: test_flush_context (tpm2_tests.SpaceTest)

11251 16:46:10.175236  # ----------------------------------------------------------------------

11252 16:46:10.178749  # Traceback (most recent call last):

11253 16:46:10.188554  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context

11254 16:46:10.191993  #     root1 = space1.create_root_key()

11255 16:46:10.201910  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11256 16:46:10.208268  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11257 16:46:10.218579  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11258 16:46:10.222297  #     raise ProtocolError(cc, rc)

11259 16:46:10.228391  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11260 16:46:10.228824  # 

11261 16:46:10.235342  # ======================================================================

11262 16:46:10.238584  # ERROR: test_get_handles (tpm2_tests.SpaceTest)

11263 16:46:10.245089  # ----------------------------------------------------------------------

11264 16:46:10.248594  # Traceback (most recent call last):

11265 16:46:10.258722  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles

11266 16:46:10.262185  #     space1.create_root_key()

11267 16:46:10.271564  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11268 16:46:10.278050  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11269 16:46:10.288479  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11270 16:46:10.291669  #     raise ProtocolError(cc, rc)

11271 16:46:10.298465  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11272 16:46:10.299049  # 

11273 16:46:10.304456  # ======================================================================

11274 16:46:10.307902  # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)

11275 16:46:10.315125  # ----------------------------------------------------------------------

11276 16:46:10.317941  # Traceback (most recent call last):

11277 16:46:10.328140  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc

11278 16:46:10.331304  #     root1 = space1.create_root_key()

11279 16:46:10.341498  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11280 16:46:10.347894  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11281 16:46:10.357996  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11282 16:46:10.361594  #     raise ProtocolError(cc, rc)

11283 16:46:10.367453  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11284 16:46:10.368014  # 

11285 16:46:10.374373  # ======================================================================

11286 16:46:10.378149  # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)

11287 16:46:10.384593  # ----------------------------------------------------------------------

11288 16:46:10.387426  # Traceback (most recent call last):

11289 16:46:10.401234  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces

11290 16:46:10.404377  #     root1 = space1.create_root_key()

11291 16:46:10.414147  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11292 16:46:10.420749  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11293 16:46:10.430394  #   File "/lava-10576285/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11294 16:46:10.430966  #     raise ProtocolError(cc, rc)

11295 16:46:10.437869  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11296 16:46:10.438333  # 

11297 16:46:10.443418  # ----------------------------------------------------------------------

11298 16:46:10.446742  # Ran 4 tests in 0.077s

11299 16:46:10.446822  # 

11300 16:46:10.450180  # FAILED (errors=4)

11301 16:46:10.452967  not ok 2 selftests: tpm2: test_space.sh # exit=1

11302 16:46:10.551712  tpm2_test_smoke_sh pass

11303 16:46:10.554866  tpm2_test_space_sh fail

11304 16:46:10.572190  + ../../utils/send-to-lava.sh ./output/result.txt

11305 16:46:10.672339  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>

11306 16:46:10.673080  Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11308 16:46:10.745318  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>

11309 16:46:10.746031  Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11311 16:46:10.747830  + set +x

11312 16:46:10.752044  <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10576285_1.6.2.3.5>

11313 16:46:10.752741  Received signal: <ENDRUN> 1_kselftest-tpm2 10576285_1.6.2.3.5
11314 16:46:10.753104  Ending use of test pattern.
11315 16:46:10.753417  Ending test lava.1_kselftest-tpm2 (10576285_1.6.2.3.5), duration 10.42
11317 16:46:10.754582  <LAVA_TEST_RUNNER EXIT>

11318 16:46:10.755161  ok: lava_test_shell seems to have completed
11319 16:46:10.755671  tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail

11320 16:46:10.756067  end: 3.1 lava-test-shell (duration 00:00:11) [common]
11321 16:46:10.756486  end: 3 lava-test-retry (duration 00:00:11) [common]
11322 16:46:10.756908  start: 4 finalize (timeout 00:07:16) [common]
11323 16:46:10.757345  start: 4.1 power-off (timeout 00:00:30) [common]
11324 16:46:10.758069  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11325 16:46:10.880838  >> Command sent successfully.

11326 16:46:10.891221  Returned 0 in 0 seconds
11327 16:46:10.992498  end: 4.1 power-off (duration 00:00:00) [common]
11329 16:46:10.994143  start: 4.2 read-feedback (timeout 00:07:16) [common]
11330 16:46:10.995378  Listened to connection for namespace 'common' for up to 1s
11331 16:46:11.995387  Finalising connection for namespace 'common'
11332 16:46:11.995910  Disconnecting from shell: Finalise
11333 16:46:11.996249  / # 
11334 16:46:12.097148  end: 4.2 read-feedback (duration 00:00:01) [common]
11335 16:46:12.097923  end: 4 finalize (duration 00:00:01) [common]
11336 16:46:12.098756  Cleaning after the job
11337 16:46:12.099473  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/ramdisk
11338 16:46:12.109081  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/kernel
11339 16:46:12.127771  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/dtb
11340 16:46:12.128076  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/nfsrootfs
11341 16:46:12.198553  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576285/tftp-deploy-reorxb3r/modules
11342 16:46:12.203951  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576285
11343 16:46:12.712479  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576285
11344 16:46:12.712645  Job finished correctly