Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
1 16:42:58.487297 lava-dispatcher, installed at version: 2023.03
2 16:42:58.487514 start: 0 validate
3 16:42:58.487649 Start time: 2023-06-03 16:42:58.487642+00:00 (UTC)
4 16:42:58.487786 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:42:58.487922 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 16:42:58.771995 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:42:58.772997 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:43:09.579890 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:43:09.580877 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:43:09.879045 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:43:09.879804 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:43:10.458133 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:43:10.459015 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:43:12.966860 validate duration: 14.48
16 16:43:12.967205 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:43:12.967307 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:43:12.967396 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:43:12.967514 Not decompressing ramdisk as can be used compressed.
20 16:43:12.967606 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/initrd.cpio.gz
21 16:43:12.967677 saving as /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/ramdisk/initrd.cpio.gz
22 16:43:12.967762 total size: 4665273 (4MB)
23 16:43:13.290919 progress 0% (0MB)
24 16:43:13.292432 progress 5% (0MB)
25 16:43:13.293698 progress 10% (0MB)
26 16:43:13.295019 progress 15% (0MB)
27 16:43:13.296576 progress 20% (0MB)
28 16:43:13.297926 progress 25% (1MB)
29 16:43:13.299290 progress 30% (1MB)
30 16:43:13.300527 progress 35% (1MB)
31 16:43:13.301821 progress 40% (1MB)
32 16:43:13.303375 progress 45% (2MB)
33 16:43:13.304646 progress 50% (2MB)
34 16:43:13.305970 progress 55% (2MB)
35 16:43:13.307299 progress 60% (2MB)
36 16:43:13.308612 progress 65% (2MB)
37 16:43:13.309937 progress 70% (3MB)
38 16:43:13.311330 progress 75% (3MB)
39 16:43:13.312642 progress 80% (3MB)
40 16:43:13.314257 progress 85% (3MB)
41 16:43:13.315554 progress 90% (4MB)
42 16:43:13.316828 progress 95% (4MB)
43 16:43:13.318129 progress 100% (4MB)
44 16:43:13.318343 4MB downloaded in 0.35s (12.69MB/s)
45 16:43:13.318555 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:43:13.318933 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:43:13.319103 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:43:13.319206 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:43:13.319364 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:43:13.319447 saving as /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/kernel/Image
52 16:43:13.319528 total size: 45746688 (43MB)
53 16:43:13.319605 No compression specified
54 16:43:13.321315 progress 0% (0MB)
55 16:43:13.333754 progress 5% (2MB)
56 16:43:13.345948 progress 10% (4MB)
57 16:43:13.358028 progress 15% (6MB)
58 16:43:13.370071 progress 20% (8MB)
59 16:43:13.382049 progress 25% (10MB)
60 16:43:13.393710 progress 30% (13MB)
61 16:43:13.405741 progress 35% (15MB)
62 16:43:13.418678 progress 40% (17MB)
63 16:43:13.431031 progress 45% (19MB)
64 16:43:13.443558 progress 50% (21MB)
65 16:43:13.455499 progress 55% (24MB)
66 16:43:13.467995 progress 60% (26MB)
67 16:43:13.480207 progress 65% (28MB)
68 16:43:13.492205 progress 70% (30MB)
69 16:43:13.504297 progress 75% (32MB)
70 16:43:13.516101 progress 80% (34MB)
71 16:43:13.528222 progress 85% (37MB)
72 16:43:13.540524 progress 90% (39MB)
73 16:43:13.552405 progress 95% (41MB)
74 16:43:13.564273 progress 100% (43MB)
75 16:43:13.564465 43MB downloaded in 0.24s (178.12MB/s)
76 16:43:13.564704 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:43:13.564954 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:43:13.565051 start: 1.3 download-retry (timeout 00:09:59) [common]
80 16:43:13.565139 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 16:43:13.565280 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:43:13.565351 saving as /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/dtb/mt8192-asurada-spherion-r0.dtb
83 16:43:13.565413 total size: 46924 (0MB)
84 16:43:13.565482 No compression specified
85 16:43:13.566695 progress 69% (0MB)
86 16:43:13.566979 progress 100% (0MB)
87 16:43:13.567153 0MB downloaded in 0.00s (25.77MB/s)
88 16:43:13.567285 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:43:13.567517 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:43:13.567611 start: 1.4 download-retry (timeout 00:09:59) [common]
92 16:43:13.567702 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 16:43:13.567825 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/full.rootfs.tar.xz
94 16:43:13.567896 saving as /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/nfsrootfs/full.rootfs.tar
95 16:43:13.567964 total size: 89386020 (85MB)
96 16:43:13.568025 Using unxz to decompress xz
97 16:43:13.571860 progress 0% (0MB)
98 16:43:13.784685 progress 5% (4MB)
99 16:43:14.002761 progress 10% (8MB)
100 16:43:14.258134 progress 15% (12MB)
101 16:43:14.453306 progress 20% (17MB)
102 16:43:14.548785 progress 25% (21MB)
103 16:43:14.799509 progress 30% (25MB)
104 16:43:15.086259 progress 35% (29MB)
105 16:43:15.354870 progress 40% (34MB)
106 16:43:15.624218 progress 45% (38MB)
107 16:43:15.884992 progress 50% (42MB)
108 16:43:16.163604 progress 55% (46MB)
109 16:43:16.422890 progress 60% (51MB)
110 16:43:16.692072 progress 65% (55MB)
111 16:43:16.992492 progress 70% (59MB)
112 16:43:17.290988 progress 75% (63MB)
113 16:43:17.595631 progress 80% (68MB)
114 16:43:17.862277 progress 85% (72MB)
115 16:43:18.107026 progress 90% (76MB)
116 16:43:18.370451 progress 95% (81MB)
117 16:43:18.642554 progress 100% (85MB)
118 16:43:18.648990 85MB downloaded in 5.08s (16.78MB/s)
119 16:43:18.649402 end: 1.4.1 http-download (duration 00:00:05) [common]
121 16:43:18.649814 end: 1.4 download-retry (duration 00:00:05) [common]
122 16:43:18.649951 start: 1.5 download-retry (timeout 00:09:54) [common]
123 16:43:18.650084 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 16:43:18.650298 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:43:18.650411 saving as /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/modules/modules.tar
126 16:43:18.650515 total size: 8545664 (8MB)
127 16:43:18.650616 Using unxz to decompress xz
128 16:43:18.654748 progress 0% (0MB)
129 16:43:18.677213 progress 5% (0MB)
130 16:43:18.704678 progress 10% (0MB)
131 16:43:18.732407 progress 15% (1MB)
132 16:43:18.758148 progress 20% (1MB)
133 16:43:18.785670 progress 25% (2MB)
134 16:43:18.812653 progress 30% (2MB)
135 16:43:18.840093 progress 35% (2MB)
136 16:43:18.865486 progress 40% (3MB)
137 16:43:18.891262 progress 45% (3MB)
138 16:43:18.916988 progress 50% (4MB)
139 16:43:18.940960 progress 55% (4MB)
140 16:43:18.967004 progress 60% (4MB)
141 16:43:18.993063 progress 65% (5MB)
142 16:43:19.019441 progress 70% (5MB)
143 16:43:19.047919 progress 75% (6MB)
144 16:43:19.079361 progress 80% (6MB)
145 16:43:19.105011 progress 85% (6MB)
146 16:43:19.133780 progress 90% (7MB)
147 16:43:19.159970 progress 95% (7MB)
148 16:43:19.187296 progress 100% (8MB)
149 16:43:19.193734 8MB downloaded in 0.54s (15.00MB/s)
150 16:43:19.194129 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:43:19.194560 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:43:19.194710 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 16:43:19.194853 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 16:43:20.912779 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10576288/extract-nfsrootfs-irjyd3ff
156 16:43:20.912992 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 16:43:20.913107 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 16:43:20.913283 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq
159 16:43:20.913447 makedir: /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin
160 16:43:20.913580 makedir: /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/tests
161 16:43:20.913708 makedir: /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/results
162 16:43:20.913842 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-add-keys
163 16:43:20.914022 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-add-sources
164 16:43:20.914184 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-background-process-start
165 16:43:20.914342 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-background-process-stop
166 16:43:20.914496 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-common-functions
167 16:43:20.914653 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-echo-ipv4
168 16:43:20.914806 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-install-packages
169 16:43:20.914963 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-installed-packages
170 16:43:20.915116 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-os-build
171 16:43:20.915240 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-probe-channel
172 16:43:20.915360 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-probe-ip
173 16:43:20.915480 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-target-ip
174 16:43:20.915599 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-target-mac
175 16:43:20.915719 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-target-storage
176 16:43:20.915856 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-test-case
177 16:43:20.916011 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-test-event
178 16:43:20.916135 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-test-feedback
179 16:43:20.916257 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-test-raise
180 16:43:20.916388 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-test-reference
181 16:43:20.916511 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-test-runner
182 16:43:20.916632 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-test-set
183 16:43:20.916751 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-test-shell
184 16:43:20.916872 Updating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-install-packages (oe)
185 16:43:20.917044 Updating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/bin/lava-installed-packages (oe)
186 16:43:20.917196 Creating /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/environment
187 16:43:20.917326 LAVA metadata
188 16:43:20.917426 - LAVA_JOB_ID=10576288
189 16:43:20.917520 - LAVA_DISPATCHER_IP=192.168.201.1
190 16:43:20.917663 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 16:43:20.917759 skipped lava-vland-overlay
192 16:43:20.917865 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 16:43:20.917977 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 16:43:20.918068 skipped lava-multinode-overlay
195 16:43:20.918165 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 16:43:20.918244 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 16:43:20.918320 Loading test definitions
198 16:43:20.918412 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 16:43:20.918482 Using /lava-10576288 at stage 0
200 16:43:20.918834 uuid=10576288_1.6.2.3.1 testdef=None
201 16:43:20.918953 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 16:43:20.919073 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 16:43:20.919600 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 16:43:20.919824 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 16:43:20.920439 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 16:43:20.920783 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 16:43:20.921648 runner path: /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/0/tests/0_lc-compliance test_uuid 10576288_1.6.2.3.1
210 16:43:20.921837 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 16:43:20.922177 Creating lava-test-runner.conf files
213 16:43:20.922268 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576288/lava-overlay-angv4pxq/lava-10576288/0 for stage 0
214 16:43:20.922387 - 0_lc-compliance
215 16:43:20.922496 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 16:43:20.922585 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 16:43:20.929588 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 16:43:20.929761 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 16:43:20.929885 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 16:43:20.930009 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 16:43:20.930127 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 16:43:21.048665 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 16:43:21.049035 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 16:43:21.049171 extracting modules file /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576288/extract-nfsrootfs-irjyd3ff
225 16:43:21.281286 extracting modules file /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576288/extract-overlay-ramdisk-bvn9k6wq/ramdisk
226 16:43:21.490752 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 16:43:21.490932 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 16:43:21.491034 [common] Applying overlay to NFS
229 16:43:21.491110 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576288/compress-overlay-m21jb9fi/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576288/extract-nfsrootfs-irjyd3ff
230 16:43:21.497605 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 16:43:21.497755 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 16:43:21.497852 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 16:43:21.497949 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 16:43:21.498034 Building ramdisk /var/lib/lava/dispatcher/tmp/10576288/extract-overlay-ramdisk-bvn9k6wq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576288/extract-overlay-ramdisk-bvn9k6wq/ramdisk
235 16:43:21.778814 >> 117799 blocks
236 16:43:23.772103 rename /var/lib/lava/dispatcher/tmp/10576288/extract-overlay-ramdisk-bvn9k6wq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/ramdisk/ramdisk.cpio.gz
237 16:43:23.772550 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 16:43:23.772681 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 16:43:23.772791 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 16:43:23.772902 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/kernel/Image'
241 16:43:36.249008 Returned 0 in 12 seconds
242 16:43:36.349604 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/kernel/image.itb
243 16:43:36.664218 output: FIT description: Kernel Image image with one or more FDT blobs
244 16:43:36.664557 output: Created: Sat Jun 3 17:43:36 2023
245 16:43:36.664632 output: Image 0 (kernel-1)
246 16:43:36.664698 output: Description:
247 16:43:36.664763 output: Created: Sat Jun 3 17:43:36 2023
248 16:43:36.664827 output: Type: Kernel Image
249 16:43:36.664888 output: Compression: lzma compressed
250 16:43:36.664947 output: Data Size: 10083474 Bytes = 9847.14 KiB = 9.62 MiB
251 16:43:36.665006 output: Architecture: AArch64
252 16:43:36.665063 output: OS: Linux
253 16:43:36.665120 output: Load Address: 0x00000000
254 16:43:36.665178 output: Entry Point: 0x00000000
255 16:43:36.665235 output: Hash algo: crc32
256 16:43:36.665288 output: Hash value: b48eba69
257 16:43:36.665341 output: Image 1 (fdt-1)
258 16:43:36.665394 output: Description: mt8192-asurada-spherion-r0
259 16:43:36.665447 output: Created: Sat Jun 3 17:43:36 2023
260 16:43:36.665501 output: Type: Flat Device Tree
261 16:43:36.665554 output: Compression: uncompressed
262 16:43:36.665607 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 16:43:36.665660 output: Architecture: AArch64
264 16:43:36.665713 output: Hash algo: crc32
265 16:43:36.665764 output: Hash value: 1df858fa
266 16:43:36.665817 output: Image 2 (ramdisk-1)
267 16:43:36.665869 output: Description: unavailable
268 16:43:36.665921 output: Created: Sat Jun 3 17:43:36 2023
269 16:43:36.665973 output: Type: RAMDisk Image
270 16:43:36.666025 output: Compression: Unknown Compression
271 16:43:36.666078 output: Data Size: 17644088 Bytes = 17230.55 KiB = 16.83 MiB
272 16:43:36.666130 output: Architecture: AArch64
273 16:43:36.666182 output: OS: Linux
274 16:43:36.666235 output: Load Address: unavailable
275 16:43:36.666287 output: Entry Point: unavailable
276 16:43:36.666338 output: Hash algo: crc32
277 16:43:36.666390 output: Hash value: 7c393f4d
278 16:43:36.666442 output: Default Configuration: 'conf-1'
279 16:43:36.666495 output: Configuration 0 (conf-1)
280 16:43:36.666547 output: Description: mt8192-asurada-spherion-r0
281 16:43:36.666599 output: Kernel: kernel-1
282 16:43:36.666651 output: Init Ramdisk: ramdisk-1
283 16:43:36.666703 output: FDT: fdt-1
284 16:43:36.666755 output: Loadables: kernel-1
285 16:43:36.666807 output:
286 16:43:36.667003 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 16:43:36.667143 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 16:43:36.667246 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
289 16:43:36.667341 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:36) [common]
290 16:43:36.667427 No LXC device requested
291 16:43:36.667506 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 16:43:36.667589 start: 1.8 deploy-device-env (timeout 00:09:36) [common]
293 16:43:36.667665 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 16:43:36.667731 Checking files for TFTP limit of 4294967296 bytes.
295 16:43:36.668215 end: 1 tftp-deploy (duration 00:00:24) [common]
296 16:43:36.668317 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 16:43:36.668406 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 16:43:36.668528 substitutions:
299 16:43:36.668596 - {DTB}: 10576288/tftp-deploy-iypy3_7a/dtb/mt8192-asurada-spherion-r0.dtb
300 16:43:36.668660 - {INITRD}: 10576288/tftp-deploy-iypy3_7a/ramdisk/ramdisk.cpio.gz
301 16:43:36.668721 - {KERNEL}: 10576288/tftp-deploy-iypy3_7a/kernel/Image
302 16:43:36.668779 - {LAVA_MAC}: None
303 16:43:36.668836 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10576288/extract-nfsrootfs-irjyd3ff
304 16:43:36.668893 - {NFS_SERVER_IP}: 192.168.201.1
305 16:43:36.668947 - {PRESEED_CONFIG}: None
306 16:43:36.669002 - {PRESEED_LOCAL}: None
307 16:43:36.669055 - {RAMDISK}: 10576288/tftp-deploy-iypy3_7a/ramdisk/ramdisk.cpio.gz
308 16:43:36.669109 - {ROOT_PART}: None
309 16:43:36.669163 - {ROOT}: None
310 16:43:36.669216 - {SERVER_IP}: 192.168.201.1
311 16:43:36.669269 - {TEE}: None
312 16:43:36.669322 Parsed boot commands:
313 16:43:36.669376 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 16:43:36.669552 Parsed boot commands: tftpboot 192.168.201.1 10576288/tftp-deploy-iypy3_7a/kernel/image.itb 10576288/tftp-deploy-iypy3_7a/kernel/cmdline
315 16:43:36.669642 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 16:43:36.669728 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 16:43:36.669820 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 16:43:36.669907 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 16:43:36.669978 Not connected, no need to disconnect.
320 16:43:36.670051 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 16:43:36.670131 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 16:43:36.670199 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
323 16:43:36.673863 Setting prompt string to ['lava-test: # ']
324 16:43:36.674275 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 16:43:36.674385 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 16:43:36.674487 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 16:43:36.674581 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 16:43:36.674798 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
329 16:43:41.812133 >> Command sent successfully.
330 16:43:41.815130 Returned 0 in 5 seconds
331 16:43:41.915511 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 16:43:41.915876 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 16:43:41.915999 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 16:43:41.916086 Setting prompt string to 'Starting depthcharge on Spherion...'
336 16:43:41.916170 Changing prompt to 'Starting depthcharge on Spherion...'
337 16:43:41.916241 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 16:43:41.916527 [Enter `^Ec?' for help]
339 16:43:42.087351
340 16:43:42.087542
341 16:43:42.087642 F0: 102B 0000
342 16:43:42.087741
343 16:43:42.087832 F3: 1001 0000 [0200]
344 16:43:42.090848
345 16:43:42.090958 F3: 1001 0000
346 16:43:42.091052
347 16:43:42.091171 F7: 102D 0000
348 16:43:42.091234
349 16:43:42.094503 F1: 0000 0000
350 16:43:42.094607
351 16:43:42.094707 V0: 0000 0000 [0001]
352 16:43:42.094804
353 16:43:42.094895 00: 0007 8000
354 16:43:42.094999
355 16:43:42.097532 01: 0000 0000
356 16:43:42.097639
357 16:43:42.097747 BP: 0C00 0209 [0000]
358 16:43:42.097841
359 16:43:42.101751 G0: 1182 0000
360 16:43:42.101870
361 16:43:42.101964 EC: 0000 0021 [4000]
362 16:43:42.102060
363 16:43:42.105222 S7: 0000 0000 [0000]
364 16:43:42.105314
365 16:43:42.105440 CC: 0000 0000 [0001]
366 16:43:42.105563
367 16:43:42.108109 T0: 0000 0040 [010F]
368 16:43:42.108188
369 16:43:42.108252 Jump to BL
370 16:43:42.108311
371 16:43:42.134529
372 16:43:42.134661
373 16:43:42.134778
374 16:43:42.141341 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 16:43:42.145026 ARM64: Exception handlers installed.
376 16:43:42.148339 ARM64: Testing exception
377 16:43:42.152169 ARM64: Done test exception
378 16:43:42.159327 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 16:43:42.167079 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 16:43:42.174203 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 16:43:42.185657 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 16:43:42.192328 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 16:43:42.198899 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 16:43:42.210579 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 16:43:42.216989 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 16:43:42.236988 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 16:43:42.240627 WDT: Last reset was cold boot
388 16:43:42.243546 SPI1(PAD0) initialized at 2873684 Hz
389 16:43:42.247019 SPI5(PAD0) initialized at 992727 Hz
390 16:43:42.250477 VBOOT: Loading verstage.
391 16:43:42.257116 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 16:43:42.260076 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 16:43:42.263574 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 16:43:42.266579 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 16:43:42.274255 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 16:43:42.280782 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 16:43:42.291915 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 16:43:42.292006
399 16:43:42.292071
400 16:43:42.302178 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 16:43:42.305138 ARM64: Exception handlers installed.
402 16:43:42.308815 ARM64: Testing exception
403 16:43:42.308916 ARM64: Done test exception
404 16:43:42.315065 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 16:43:42.318738 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 16:43:42.333014 Probing TPM: . done!
407 16:43:42.333099 TPM ready after 0 ms
408 16:43:42.339639 Connected to device vid:did:rid of 1ae0:0028:00
409 16:43:42.349957 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 16:43:42.387679 Initialized TPM device CR50 revision 0
411 16:43:42.400068 tlcl_send_startup: Startup return code is 0
412 16:43:42.400167 TPM: setup succeeded
413 16:43:42.412242 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 16:43:42.421026 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 16:43:42.431734 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 16:43:42.441199 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 16:43:42.444229 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 16:43:42.447763 in-header: 03 07 00 00 08 00 00 00
419 16:43:42.450785 in-data: aa e4 47 04 13 02 00 00
420 16:43:42.454359 Chrome EC: UHEPI supported
421 16:43:42.460775 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 16:43:42.464399 in-header: 03 ad 00 00 08 00 00 00
423 16:43:42.467937 in-data: 00 20 20 08 00 00 00 00
424 16:43:42.468020 Phase 1
425 16:43:42.471214 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 16:43:42.477753 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 16:43:42.484388 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 16:43:42.487253 Recovery requested (1009000e)
429 16:43:42.491723 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 16:43:42.499804 tlcl_extend: response is 0
431 16:43:42.508086 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 16:43:42.513479 tlcl_extend: response is 0
433 16:43:42.519609 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 16:43:42.540493 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 16:43:42.547611 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 16:43:42.547697
437 16:43:42.547763
438 16:43:42.558007 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 16:43:42.561356 ARM64: Exception handlers installed.
440 16:43:42.561463 ARM64: Testing exception
441 16:43:42.565037 ARM64: Done test exception
442 16:43:42.586419 pmic_efuse_setting: Set efuses in 11 msecs
443 16:43:42.590439 pmwrap_interface_init: Select PMIF_VLD_RDY
444 16:43:42.593183 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 16:43:42.600560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 16:43:42.603280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 16:43:42.609872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 16:43:42.613317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 16:43:42.620163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 16:43:42.623287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 16:43:42.629581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 16:43:42.633288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 16:43:42.636328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 16:43:42.642774 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 16:43:42.646427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 16:43:42.653109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 16:43:42.659237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 16:43:42.662859 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 16:43:42.669421 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 16:43:42.676125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 16:43:42.678976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 16:43:42.685662 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 16:43:42.692416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 16:43:42.695816 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 16:43:42.703151 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 16:43:42.710677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 16:43:42.714071 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 16:43:42.720706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 16:43:42.724313 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 16:43:42.731507 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 16:43:42.734491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 16:43:42.741640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 16:43:42.745263 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 16:43:42.749033 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 16:43:42.755573 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 16:43:42.759163 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 16:43:42.765893 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 16:43:42.768911 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 16:43:42.775532 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 16:43:42.779160 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 16:43:42.785580 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 16:43:42.789130 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 16:43:42.792835 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 16:43:42.799543 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 16:43:42.803525 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 16:43:42.806761 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 16:43:42.810357 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 16:43:42.816738 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 16:43:42.820095 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 16:43:42.823708 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 16:43:42.826616 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 16:43:42.833723 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 16:43:42.836723 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 16:43:42.840300 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 16:43:42.850158 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 16:43:42.856667 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 16:43:42.863305 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 16:43:42.870098 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 16:43:42.879689 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 16:43:42.883195 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 16:43:42.886255 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 16:43:42.892788 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 16:43:42.899796 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
504 16:43:42.902931 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 16:43:42.910269 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
506 16:43:42.913995 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 16:43:42.923294 [RTC]rtc_get_frequency_meter,154: input=15, output=835
508 16:43:42.932417 [RTC]rtc_get_frequency_meter,154: input=7, output=710
509 16:43:42.941829 [RTC]rtc_get_frequency_meter,154: input=11, output=773
510 16:43:42.951321 [RTC]rtc_get_frequency_meter,154: input=13, output=804
511 16:43:42.960836 [RTC]rtc_get_frequency_meter,154: input=12, output=788
512 16:43:42.970393 [RTC]rtc_get_frequency_meter,154: input=12, output=788
513 16:43:42.979947 [RTC]rtc_get_frequency_meter,154: input=13, output=804
514 16:43:42.983628 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
515 16:43:42.990798 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
516 16:43:42.993682 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 16:43:42.997166 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 16:43:43.003797 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 16:43:43.007327 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 16:43:43.010327 ADC[4]: Raw value=903031 ID=7
521 16:43:43.010524 ADC[3]: Raw value=213652 ID=1
522 16:43:43.013681 RAM Code: 0x71
523 16:43:43.017294 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 16:43:43.023838 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 16:43:43.030716 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 16:43:43.036759 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 16:43:43.040676 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 16:43:43.043723 in-header: 03 07 00 00 08 00 00 00
529 16:43:43.046994 in-data: aa e4 47 04 13 02 00 00
530 16:43:43.049976 Chrome EC: UHEPI supported
531 16:43:43.056821 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 16:43:43.060325 in-header: 03 dd 00 00 08 00 00 00
533 16:43:43.063344 in-data: 90 20 60 08 00 00 00 00
534 16:43:43.066884 MRC: failed to locate region type 0.
535 16:43:43.073642 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 16:43:43.076864 DRAM-K: Running full calibration
537 16:43:43.083280 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 16:43:43.083364 header.status = 0x0
539 16:43:43.086309 header.version = 0x6 (expected: 0x6)
540 16:43:43.089920 header.size = 0xd00 (expected: 0xd00)
541 16:43:43.093388 header.flags = 0x0
542 16:43:43.099766 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 16:43:43.116519 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
544 16:43:43.123194 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 16:43:43.126338 dram_init: ddr_geometry: 2
546 16:43:43.129838 [EMI] MDL number = 2
547 16:43:43.129926 [EMI] Get MDL freq = 0
548 16:43:43.133261 dram_init: ddr_type: 0
549 16:43:43.133370 is_discrete_lpddr4: 1
550 16:43:43.136675 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 16:43:43.136801
552 16:43:43.136896
553 16:43:43.139969 [Bian_co] ETT version 0.0.0.1
554 16:43:43.146686 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 16:43:43.146792
556 16:43:43.150009 dramc_set_vcore_voltage set vcore to 650000
557 16:43:43.153429 Read voltage for 800, 4
558 16:43:43.153540 Vio18 = 0
559 16:43:43.153639 Vcore = 650000
560 16:43:43.156326 Vdram = 0
561 16:43:43.156427 Vddq = 0
562 16:43:43.156528 Vmddr = 0
563 16:43:43.159968 dram_init: config_dvfs: 1
564 16:43:43.162952 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 16:43:43.170130 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 16:43:43.173112 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
567 16:43:43.176748 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
568 16:43:43.179738 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
569 16:43:43.183381 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
570 16:43:43.186333 MEM_TYPE=3, freq_sel=18
571 16:43:43.189938 sv_algorithm_assistance_LP4_1600
572 16:43:43.193088 ============ PULL DRAM RESETB DOWN ============
573 16:43:43.199522 ========== PULL DRAM RESETB DOWN end =========
574 16:43:43.202980 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 16:43:43.206117 ===================================
576 16:43:43.209790 LPDDR4 DRAM CONFIGURATION
577 16:43:43.212805 ===================================
578 16:43:43.212888 EX_ROW_EN[0] = 0x0
579 16:43:43.216448 EX_ROW_EN[1] = 0x0
580 16:43:43.216533 LP4Y_EN = 0x0
581 16:43:43.219587 WORK_FSP = 0x0
582 16:43:43.219671 WL = 0x2
583 16:43:43.222642 RL = 0x2
584 16:43:43.222725 BL = 0x2
585 16:43:43.225980 RPST = 0x0
586 16:43:43.226064 RD_PRE = 0x0
587 16:43:43.229359 WR_PRE = 0x1
588 16:43:43.232701 WR_PST = 0x0
589 16:43:43.232826 DBI_WR = 0x0
590 16:43:43.236255 DBI_RD = 0x0
591 16:43:43.236369 OTF = 0x1
592 16:43:43.239194 ===================================
593 16:43:43.242475 ===================================
594 16:43:43.242576 ANA top config
595 16:43:43.245817 ===================================
596 16:43:43.249156 DLL_ASYNC_EN = 0
597 16:43:43.252396 ALL_SLAVE_EN = 1
598 16:43:43.256159 NEW_RANK_MODE = 1
599 16:43:43.259295 DLL_IDLE_MODE = 1
600 16:43:43.259368 LP45_APHY_COMB_EN = 1
601 16:43:43.262565 TX_ODT_DIS = 1
602 16:43:43.266012 NEW_8X_MODE = 1
603 16:43:43.269013 ===================================
604 16:43:43.272757 ===================================
605 16:43:43.275803 data_rate = 1600
606 16:43:43.279398 CKR = 1
607 16:43:43.279501 DQ_P2S_RATIO = 8
608 16:43:43.282419 ===================================
609 16:43:43.286217 CA_P2S_RATIO = 8
610 16:43:43.289135 DQ_CA_OPEN = 0
611 16:43:43.292782 DQ_SEMI_OPEN = 0
612 16:43:43.295811 CA_SEMI_OPEN = 0
613 16:43:43.299341 CA_FULL_RATE = 0
614 16:43:43.299426 DQ_CKDIV4_EN = 1
615 16:43:43.302881 CA_CKDIV4_EN = 1
616 16:43:43.306264 CA_PREDIV_EN = 0
617 16:43:43.309270 PH8_DLY = 0
618 16:43:43.312921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 16:43:43.316002 DQ_AAMCK_DIV = 4
620 16:43:43.316085 CA_AAMCK_DIV = 4
621 16:43:43.319008 CA_ADMCK_DIV = 4
622 16:43:43.322754 DQ_TRACK_CA_EN = 0
623 16:43:43.326226 CA_PICK = 800
624 16:43:43.329290 CA_MCKIO = 800
625 16:43:43.332809 MCKIO_SEMI = 0
626 16:43:43.332892 PLL_FREQ = 3068
627 16:43:43.336068 DQ_UI_PI_RATIO = 32
628 16:43:43.339693 CA_UI_PI_RATIO = 0
629 16:43:43.342517 ===================================
630 16:43:43.345893 ===================================
631 16:43:43.349315 memory_type:LPDDR4
632 16:43:43.352655 GP_NUM : 10
633 16:43:43.352739 SRAM_EN : 1
634 16:43:43.356038 MD32_EN : 0
635 16:43:43.359314 ===================================
636 16:43:43.359399 [ANA_INIT] >>>>>>>>>>>>>>
637 16:43:43.362499 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 16:43:43.365810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 16:43:43.369156 ===================================
640 16:43:43.372327 data_rate = 1600,PCW = 0X7600
641 16:43:43.375783 ===================================
642 16:43:43.378615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 16:43:43.385296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 16:43:43.392050 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 16:43:43.395702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 16:43:43.398751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 16:43:43.401730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 16:43:43.405291 [ANA_INIT] flow start
649 16:43:43.405375 [ANA_INIT] PLL >>>>>>>>
650 16:43:43.408801 [ANA_INIT] PLL <<<<<<<<
651 16:43:43.411793 [ANA_INIT] MIDPI >>>>>>>>
652 16:43:43.411877 [ANA_INIT] MIDPI <<<<<<<<
653 16:43:43.415350 [ANA_INIT] DLL >>>>>>>>
654 16:43:43.418350 [ANA_INIT] flow end
655 16:43:43.421999 ============ LP4 DIFF to SE enter ============
656 16:43:43.425115 ============ LP4 DIFF to SE exit ============
657 16:43:43.428723 [ANA_INIT] <<<<<<<<<<<<<
658 16:43:43.431638 [Flow] Enable top DCM control >>>>>
659 16:43:43.435362 [Flow] Enable top DCM control <<<<<
660 16:43:43.438275 Enable DLL master slave shuffle
661 16:43:43.441593 ==============================================================
662 16:43:43.445275 Gating Mode config
663 16:43:43.451761 ==============================================================
664 16:43:43.451891 Config description:
665 16:43:43.461849 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 16:43:43.468240 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 16:43:43.472141 SELPH_MODE 0: By rank 1: By Phase
668 16:43:43.478320 ==============================================================
669 16:43:43.481645 GAT_TRACK_EN = 1
670 16:43:43.485154 RX_GATING_MODE = 2
671 16:43:43.488791 RX_GATING_TRACK_MODE = 2
672 16:43:43.491869 SELPH_MODE = 1
673 16:43:43.495456 PICG_EARLY_EN = 1
674 16:43:43.498346 VALID_LAT_VALUE = 1
675 16:43:43.501896 ==============================================================
676 16:43:43.504844 Enter into Gating configuration >>>>
677 16:43:43.508436 Exit from Gating configuration <<<<
678 16:43:43.511423 Enter into DVFS_PRE_config >>>>>
679 16:43:43.524700 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 16:43:43.524789 Exit from DVFS_PRE_config <<<<<
681 16:43:43.528303 Enter into PICG configuration >>>>
682 16:43:43.531879 Exit from PICG configuration <<<<
683 16:43:43.534921 [RX_INPUT] configuration >>>>>
684 16:43:43.538484 [RX_INPUT] configuration <<<<<
685 16:43:43.545109 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 16:43:43.548698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 16:43:43.556007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 16:43:43.562983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 16:43:43.566522 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 16:43:43.573798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 16:43:43.577690 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 16:43:43.581590 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 16:43:43.584895 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 16:43:43.588933 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 16:43:43.595671 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 16:43:43.599237 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 16:43:43.602922 ===================================
698 16:43:43.603013 LPDDR4 DRAM CONFIGURATION
699 16:43:43.606382 ===================================
700 16:43:43.610443 EX_ROW_EN[0] = 0x0
701 16:43:43.610560 EX_ROW_EN[1] = 0x0
702 16:43:43.614114 LP4Y_EN = 0x0
703 16:43:43.614222 WORK_FSP = 0x0
704 16:43:43.617710 WL = 0x2
705 16:43:43.617823 RL = 0x2
706 16:43:43.621371 BL = 0x2
707 16:43:43.621445 RPST = 0x0
708 16:43:43.624930 RD_PRE = 0x0
709 16:43:43.625002 WR_PRE = 0x1
710 16:43:43.628490 WR_PST = 0x0
711 16:43:43.628584 DBI_WR = 0x0
712 16:43:43.632729 DBI_RD = 0x0
713 16:43:43.632833 OTF = 0x1
714 16:43:43.636345 ===================================
715 16:43:43.640034 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 16:43:43.643649 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 16:43:43.647157 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 16:43:43.650743 ===================================
719 16:43:43.654342 LPDDR4 DRAM CONFIGURATION
720 16:43:43.657933 ===================================
721 16:43:43.658018 EX_ROW_EN[0] = 0x10
722 16:43:43.661965 EX_ROW_EN[1] = 0x0
723 16:43:43.662052 LP4Y_EN = 0x0
724 16:43:43.665477 WORK_FSP = 0x0
725 16:43:43.665569 WL = 0x2
726 16:43:43.669105 RL = 0x2
727 16:43:43.669206 BL = 0x2
728 16:43:43.672791 RPST = 0x0
729 16:43:43.672892 RD_PRE = 0x0
730 16:43:43.676515 WR_PRE = 0x1
731 16:43:43.676614 WR_PST = 0x0
732 16:43:43.679743 DBI_WR = 0x0
733 16:43:43.679829 DBI_RD = 0x0
734 16:43:43.683648 OTF = 0x1
735 16:43:43.683737 ===================================
736 16:43:43.690687 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 16:43:43.695634 nWR fixed to 40
738 16:43:43.698996 [ModeRegInit_LP4] CH0 RK0
739 16:43:43.699114 [ModeRegInit_LP4] CH0 RK1
740 16:43:43.703092 [ModeRegInit_LP4] CH1 RK0
741 16:43:43.703193 [ModeRegInit_LP4] CH1 RK1
742 16:43:43.705989 match AC timing 13
743 16:43:43.709673 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 16:43:43.712732 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 16:43:43.719267 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 16:43:43.722793 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 16:43:43.729494 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 16:43:43.729592 [EMI DOE] emi_dcm 0
749 16:43:43.733115 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 16:43:43.733203 ==
751 16:43:43.736120 Dram Type= 6, Freq= 0, CH_0, rank 0
752 16:43:43.742671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 16:43:43.742764 ==
754 16:43:43.746266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 16:43:43.752848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 16:43:43.762372 [CA 0] Center 37 (7~68) winsize 62
757 16:43:43.765893 [CA 1] Center 36 (6~67) winsize 62
758 16:43:43.769410 [CA 2] Center 34 (4~65) winsize 62
759 16:43:43.772442 [CA 3] Center 34 (4~65) winsize 62
760 16:43:43.776093 [CA 4] Center 33 (3~64) winsize 62
761 16:43:43.779655 [CA 5] Center 33 (3~64) winsize 62
762 16:43:43.779741
763 16:43:43.782645 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 16:43:43.782753
765 16:43:43.786090 [CATrainingPosCal] consider 1 rank data
766 16:43:43.789600 u2DelayCellTimex100 = 270/100 ps
767 16:43:43.792669 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
768 16:43:43.796466 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
769 16:43:43.799448 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 16:43:43.806248 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
771 16:43:43.809685 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 16:43:43.812573 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 16:43:43.812705
774 16:43:43.816165 CA PerBit enable=1, Macro0, CA PI delay=33
775 16:43:43.816285
776 16:43:43.819190 [CBTSetCACLKResult] CA Dly = 33
777 16:43:43.819279 CS Dly: 6 (0~37)
778 16:43:43.819348 ==
779 16:43:43.822806 Dram Type= 6, Freq= 0, CH_0, rank 1
780 16:43:43.829345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 16:43:43.829444 ==
782 16:43:43.833008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 16:43:43.839683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 16:43:43.848685 [CA 0] Center 37 (6~68) winsize 63
785 16:43:43.852187 [CA 1] Center 37 (6~68) winsize 63
786 16:43:43.855105 [CA 2] Center 34 (4~65) winsize 62
787 16:43:43.858557 [CA 3] Center 34 (4~65) winsize 62
788 16:43:43.862089 [CA 4] Center 33 (3~64) winsize 62
789 16:43:43.865111 [CA 5] Center 33 (3~64) winsize 62
790 16:43:43.865199
791 16:43:43.868644 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 16:43:43.868732
793 16:43:43.872080 [CATrainingPosCal] consider 2 rank data
794 16:43:43.875604 u2DelayCellTimex100 = 270/100 ps
795 16:43:43.878610 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 16:43:43.885338 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
797 16:43:43.888397 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 16:43:43.892665 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 16:43:43.896199 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 16:43:43.899612 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 16:43:43.899705
802 16:43:43.902990 CA PerBit enable=1, Macro0, CA PI delay=33
803 16:43:43.903110
804 16:43:43.906876 [CBTSetCACLKResult] CA Dly = 33
805 16:43:43.907002 CS Dly: 6 (0~38)
806 16:43:43.907104
807 16:43:43.910283 ----->DramcWriteLeveling(PI) begin...
808 16:43:43.910385 ==
809 16:43:43.914237 Dram Type= 6, Freq= 0, CH_0, rank 0
810 16:43:43.917398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 16:43:43.917508 ==
812 16:43:43.921351 Write leveling (Byte 0): 34 => 34
813 16:43:43.924413 Write leveling (Byte 1): 32 => 32
814 16:43:43.927983 DramcWriteLeveling(PI) end<-----
815 16:43:43.928078
816 16:43:43.928164 ==
817 16:43:43.930898 Dram Type= 6, Freq= 0, CH_0, rank 0
818 16:43:43.934457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 16:43:43.934570 ==
820 16:43:43.937436 [Gating] SW mode calibration
821 16:43:43.944069 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 16:43:43.950811 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 16:43:43.954275 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 16:43:43.957281 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 16:43:43.964290 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
826 16:43:43.967238 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
827 16:43:43.970899 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 16:43:43.977237 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 16:43:43.980674 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 16:43:43.983654 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 16:43:43.990894 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 16:43:43.993898 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 16:43:43.997459 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 16:43:44.004055 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 16:43:44.007502 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 16:43:44.010834 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 16:43:44.017142 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 16:43:44.020504 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 16:43:44.023779 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 16:43:44.030475 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 16:43:44.033970 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
842 16:43:44.037577 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 16:43:44.043744 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 16:43:44.047315 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 16:43:44.050922 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 16:43:44.056843 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 16:43:44.060512 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 16:43:44.064000 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 16:43:44.066908 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
850 16:43:44.073478 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
851 16:43:44.077135 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 16:43:44.080478 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 16:43:44.087065 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 16:43:44.090030 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 16:43:44.093637 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 16:43:44.100364 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
857 16:43:44.103237 0 10 8 | B1->B0 | 3333 2424 | 0 1 | (0 1) (1 0)
858 16:43:44.106817 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
859 16:43:44.113334 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:43:44.117776 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:43:44.120760 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:43:44.124615 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:43:44.132112 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:43:44.135558 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
865 16:43:44.139653 0 11 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
866 16:43:44.142735 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
867 16:43:44.146364 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 16:43:44.154097 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 16:43:44.157626 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 16:43:44.161218 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 16:43:44.164879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 16:43:44.168309 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 16:43:44.176105 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 16:43:44.179102 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 16:43:44.182689 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 16:43:44.186190 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 16:43:44.192434 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 16:43:44.195926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 16:43:44.199429 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 16:43:44.206005 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 16:43:44.208940 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 16:43:44.212468 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 16:43:44.219015 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 16:43:44.222087 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 16:43:44.225663 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 16:43:44.232907 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 16:43:44.236697 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 16:43:44.240680 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
889 16:43:44.244452 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
890 16:43:44.247827 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 16:43:44.251378 Total UI for P1: 0, mck2ui 16
892 16:43:44.255039 best dqsien dly found for B0: ( 0, 14, 6)
893 16:43:44.258695 Total UI for P1: 0, mck2ui 16
894 16:43:44.261593 best dqsien dly found for B1: ( 0, 14, 8)
895 16:43:44.265242 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
896 16:43:44.268308 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
897 16:43:44.268414
898 16:43:44.271857 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
899 16:43:44.274828 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 16:43:44.278955 [Gating] SW calibration Done
901 16:43:44.279096 ==
902 16:43:44.281926 Dram Type= 6, Freq= 0, CH_0, rank 0
903 16:43:44.285593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 16:43:44.285747 ==
905 16:43:44.289027 RX Vref Scan: 0
906 16:43:44.289134
907 16:43:44.292405 RX Vref 0 -> 0, step: 1
908 16:43:44.292494
909 16:43:44.292560 RX Delay -130 -> 252, step: 16
910 16:43:44.299039 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 16:43:44.302018 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 16:43:44.305745 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 16:43:44.308734 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 16:43:44.312272 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 16:43:44.318907 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 16:43:44.321882 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 16:43:44.325493 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
918 16:43:44.328537 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
919 16:43:44.332102 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
920 16:43:44.338692 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 16:43:44.342083 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 16:43:44.345027 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
923 16:43:44.348296 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
924 16:43:44.355462 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 16:43:44.358426 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
926 16:43:44.358523 ==
927 16:43:44.362060 Dram Type= 6, Freq= 0, CH_0, rank 0
928 16:43:44.365105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 16:43:44.365199 ==
930 16:43:44.368756 DQS Delay:
931 16:43:44.368848 DQS0 = 0, DQS1 = 0
932 16:43:44.368936 DQM Delay:
933 16:43:44.371759 DQM0 = 86, DQM1 = 73
934 16:43:44.371848 DQ Delay:
935 16:43:44.375296 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 16:43:44.378306 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
937 16:43:44.381892 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
938 16:43:44.384852 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
939 16:43:44.384981
940 16:43:44.385083
941 16:43:44.385163 ==
942 16:43:44.388488 Dram Type= 6, Freq= 0, CH_0, rank 0
943 16:43:44.394991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 16:43:44.395133 ==
945 16:43:44.395227
946 16:43:44.395326
947 16:43:44.395425 TX Vref Scan disable
948 16:43:44.398636 == TX Byte 0 ==
949 16:43:44.401851 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
950 16:43:44.405139 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
951 16:43:44.408788 == TX Byte 1 ==
952 16:43:44.411711 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
953 16:43:44.415341 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
954 16:43:44.418736 ==
955 16:43:44.421887 Dram Type= 6, Freq= 0, CH_0, rank 0
956 16:43:44.424829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 16:43:44.424922 ==
958 16:43:44.437397 TX Vref=22, minBit 5, minWin=27, winSum=441
959 16:43:44.440799 TX Vref=24, minBit 3, minWin=27, winSum=443
960 16:43:44.444256 TX Vref=26, minBit 5, minWin=27, winSum=445
961 16:43:44.447193 TX Vref=28, minBit 10, minWin=27, winSum=451
962 16:43:44.450526 TX Vref=30, minBit 8, minWin=27, winSum=447
963 16:43:44.457493 TX Vref=32, minBit 9, minWin=27, winSum=446
964 16:43:44.460506 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 28
965 16:43:44.460607
966 16:43:44.463843 Final TX Range 1 Vref 28
967 16:43:44.463936
968 16:43:44.464020 ==
969 16:43:44.467291 Dram Type= 6, Freq= 0, CH_0, rank 0
970 16:43:44.470699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 16:43:44.473679 ==
972 16:43:44.473780
973 16:43:44.473873
974 16:43:44.473951 TX Vref Scan disable
975 16:43:44.477463 == TX Byte 0 ==
976 16:43:44.481028 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
977 16:43:44.487347 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
978 16:43:44.487450 == TX Byte 1 ==
979 16:43:44.490838 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 16:43:44.497452 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 16:43:44.497564
982 16:43:44.497661 [DATLAT]
983 16:43:44.497747 Freq=800, CH0 RK0
984 16:43:44.497826
985 16:43:44.500453 DATLAT Default: 0xa
986 16:43:44.500529 0, 0xFFFF, sum = 0
987 16:43:44.504160 1, 0xFFFF, sum = 0
988 16:43:44.507177 2, 0xFFFF, sum = 0
989 16:43:44.507272 3, 0xFFFF, sum = 0
990 16:43:44.510805 4, 0xFFFF, sum = 0
991 16:43:44.510894 5, 0xFFFF, sum = 0
992 16:43:44.513794 6, 0xFFFF, sum = 0
993 16:43:44.513874 7, 0xFFFF, sum = 0
994 16:43:44.517454 8, 0xFFFF, sum = 0
995 16:43:44.517547 9, 0x0, sum = 1
996 16:43:44.520376 10, 0x0, sum = 2
997 16:43:44.520458 11, 0x0, sum = 3
998 16:43:44.520543 12, 0x0, sum = 4
999 16:43:44.524108 best_step = 10
1000 16:43:44.524201
1001 16:43:44.524289 ==
1002 16:43:44.527895 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 16:43:44.531287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 16:43:44.531386 ==
1005 16:43:44.534301 RX Vref Scan: 1
1006 16:43:44.534393
1007 16:43:44.534479 Set Vref Range= 32 -> 127
1008 16:43:44.534571
1009 16:43:44.537841 RX Vref 32 -> 127, step: 1
1010 16:43:44.537937
1011 16:43:44.541402 RX Delay -95 -> 252, step: 8
1012 16:43:44.541494
1013 16:43:44.544900 Set Vref, RX VrefLevel [Byte0]: 32
1014 16:43:44.548480 [Byte1]: 32
1015 16:43:44.548577
1016 16:43:44.551969 Set Vref, RX VrefLevel [Byte0]: 33
1017 16:43:44.555965 [Byte1]: 33
1018 16:43:44.556056
1019 16:43:44.559457 Set Vref, RX VrefLevel [Byte0]: 34
1020 16:43:44.562950 [Byte1]: 34
1021 16:43:44.563123
1022 16:43:44.566561 Set Vref, RX VrefLevel [Byte0]: 35
1023 16:43:44.569770 [Byte1]: 35
1024 16:43:44.573473
1025 16:43:44.573581 Set Vref, RX VrefLevel [Byte0]: 36
1026 16:43:44.576151 [Byte1]: 36
1027 16:43:44.580909
1028 16:43:44.581011 Set Vref, RX VrefLevel [Byte0]: 37
1029 16:43:44.584029 [Byte1]: 37
1030 16:43:44.588648
1031 16:43:44.588746 Set Vref, RX VrefLevel [Byte0]: 38
1032 16:43:44.591587 [Byte1]: 38
1033 16:43:44.595851
1034 16:43:44.595953 Set Vref, RX VrefLevel [Byte0]: 39
1035 16:43:44.599337 [Byte1]: 39
1036 16:43:44.603383
1037 16:43:44.606988 Set Vref, RX VrefLevel [Byte0]: 40
1038 16:43:44.607189 [Byte1]: 40
1039 16:43:44.611273
1040 16:43:44.611393 Set Vref, RX VrefLevel [Byte0]: 41
1041 16:43:44.614253 [Byte1]: 41
1042 16:43:44.619103
1043 16:43:44.619227 Set Vref, RX VrefLevel [Byte0]: 42
1044 16:43:44.622791 [Byte1]: 42
1045 16:43:44.626764
1046 16:43:44.626884 Set Vref, RX VrefLevel [Byte0]: 43
1047 16:43:44.629808 [Byte1]: 43
1048 16:43:44.634446
1049 16:43:44.634543 Set Vref, RX VrefLevel [Byte0]: 44
1050 16:43:44.638014 [Byte1]: 44
1051 16:43:44.641691
1052 16:43:44.641790 Set Vref, RX VrefLevel [Byte0]: 45
1053 16:43:44.645280 [Byte1]: 45
1054 16:43:44.649283
1055 16:43:44.649377 Set Vref, RX VrefLevel [Byte0]: 46
1056 16:43:44.652904 [Byte1]: 46
1057 16:43:44.656688
1058 16:43:44.656787 Set Vref, RX VrefLevel [Byte0]: 47
1059 16:43:44.660219 [Byte1]: 47
1060 16:43:44.664715
1061 16:43:44.664836 Set Vref, RX VrefLevel [Byte0]: 48
1062 16:43:44.668262 [Byte1]: 48
1063 16:43:44.671908
1064 16:43:44.672022 Set Vref, RX VrefLevel [Byte0]: 49
1065 16:43:44.675629 [Byte1]: 49
1066 16:43:44.679850
1067 16:43:44.679960 Set Vref, RX VrefLevel [Byte0]: 50
1068 16:43:44.682387 [Byte1]: 50
1069 16:43:44.687271
1070 16:43:44.687375 Set Vref, RX VrefLevel [Byte0]: 51
1071 16:43:44.690209 [Byte1]: 51
1072 16:43:44.694874
1073 16:43:44.694998 Set Vref, RX VrefLevel [Byte0]: 52
1074 16:43:44.697722 [Byte1]: 52
1075 16:43:44.702464
1076 16:43:44.702565 Set Vref, RX VrefLevel [Byte0]: 53
1077 16:43:44.705412 [Byte1]: 53
1078 16:43:44.710139
1079 16:43:44.710239 Set Vref, RX VrefLevel [Byte0]: 54
1080 16:43:44.713199 [Byte1]: 54
1081 16:43:44.717455
1082 16:43:44.717556 Set Vref, RX VrefLevel [Byte0]: 55
1083 16:43:44.721200 [Byte1]: 55
1084 16:43:44.725434
1085 16:43:44.725558 Set Vref, RX VrefLevel [Byte0]: 56
1086 16:43:44.728309 [Byte1]: 56
1087 16:43:44.732476
1088 16:43:44.732606 Set Vref, RX VrefLevel [Byte0]: 57
1089 16:43:44.736110 [Byte1]: 57
1090 16:43:44.740220
1091 16:43:44.740344 Set Vref, RX VrefLevel [Byte0]: 58
1092 16:43:44.743814 [Byte1]: 58
1093 16:43:44.748155
1094 16:43:44.748285 Set Vref, RX VrefLevel [Byte0]: 59
1095 16:43:44.751534 [Byte1]: 59
1096 16:43:44.755612
1097 16:43:44.755729 Set Vref, RX VrefLevel [Byte0]: 60
1098 16:43:44.759320 [Byte1]: 60
1099 16:43:44.762722
1100 16:43:44.762847 Set Vref, RX VrefLevel [Byte0]: 61
1101 16:43:44.766207 [Byte1]: 61
1102 16:43:44.770866
1103 16:43:44.770994 Set Vref, RX VrefLevel [Byte0]: 62
1104 16:43:44.773627 [Byte1]: 62
1105 16:43:44.778624
1106 16:43:44.778764 Set Vref, RX VrefLevel [Byte0]: 63
1107 16:43:44.781730 [Byte1]: 63
1108 16:43:44.785817
1109 16:43:44.785935 Set Vref, RX VrefLevel [Byte0]: 64
1110 16:43:44.789297 [Byte1]: 64
1111 16:43:44.793535
1112 16:43:44.793669 Set Vref, RX VrefLevel [Byte0]: 65
1113 16:43:44.797114 [Byte1]: 65
1114 16:43:44.801097
1115 16:43:44.801233 Set Vref, RX VrefLevel [Byte0]: 66
1116 16:43:44.804619 [Byte1]: 66
1117 16:43:44.808860
1118 16:43:44.808983 Set Vref, RX VrefLevel [Byte0]: 67
1119 16:43:44.812380 [Byte1]: 67
1120 16:43:44.816491
1121 16:43:44.816592 Set Vref, RX VrefLevel [Byte0]: 68
1122 16:43:44.819816 [Byte1]: 68
1123 16:43:44.823859
1124 16:43:44.823957 Set Vref, RX VrefLevel [Byte0]: 69
1125 16:43:44.827502 [Byte1]: 69
1126 16:43:44.831041
1127 16:43:44.834556 Set Vref, RX VrefLevel [Byte0]: 70
1128 16:43:44.834677 [Byte1]: 70
1129 16:43:44.839507
1130 16:43:44.839629 Set Vref, RX VrefLevel [Byte0]: 71
1131 16:43:44.842470 [Byte1]: 71
1132 16:43:44.846653
1133 16:43:44.846774 Set Vref, RX VrefLevel [Byte0]: 72
1134 16:43:44.849585 [Byte1]: 72
1135 16:43:44.854465
1136 16:43:44.854554 Set Vref, RX VrefLevel [Byte0]: 73
1137 16:43:44.857312 [Byte1]: 73
1138 16:43:44.862000
1139 16:43:44.862112 Set Vref, RX VrefLevel [Byte0]: 74
1140 16:43:44.864992 [Byte1]: 74
1141 16:43:44.869277
1142 16:43:44.869366 Set Vref, RX VrefLevel [Byte0]: 75
1143 16:43:44.872819 [Byte1]: 75
1144 16:43:44.876829
1145 16:43:44.880217 Set Vref, RX VrefLevel [Byte0]: 76
1146 16:43:44.880306 [Byte1]: 76
1147 16:43:44.885138
1148 16:43:44.885256 Set Vref, RX VrefLevel [Byte0]: 77
1149 16:43:44.888248 [Byte1]: 77
1150 16:43:44.892217
1151 16:43:44.892309 Set Vref, RX VrefLevel [Byte0]: 78
1152 16:43:44.895991 [Byte1]: 78
1153 16:43:44.900098
1154 16:43:44.900193 Set Vref, RX VrefLevel [Byte0]: 79
1155 16:43:44.903466 [Byte1]: 79
1156 16:43:44.908122
1157 16:43:44.908248 Set Vref, RX VrefLevel [Byte0]: 80
1158 16:43:44.911106 [Byte1]: 80
1159 16:43:44.915329
1160 16:43:44.915431 Set Vref, RX VrefLevel [Byte0]: 81
1161 16:43:44.918683 [Byte1]: 81
1162 16:43:44.922423
1163 16:43:44.922517 Set Vref, RX VrefLevel [Byte0]: 82
1164 16:43:44.926024 [Byte1]: 82
1165 16:43:44.930279
1166 16:43:44.930402 Final RX Vref Byte 0 = 63 to rank0
1167 16:43:44.933416 Final RX Vref Byte 1 = 58 to rank0
1168 16:43:44.937579 Final RX Vref Byte 0 = 63 to rank1
1169 16:43:44.941163 Final RX Vref Byte 1 = 58 to rank1==
1170 16:43:44.944913 Dram Type= 6, Freq= 0, CH_0, rank 0
1171 16:43:44.948378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 16:43:44.948472 ==
1173 16:43:44.948537 DQS Delay:
1174 16:43:44.951916 DQS0 = 0, DQS1 = 0
1175 16:43:44.952016 DQM Delay:
1176 16:43:44.956121 DQM0 = 87, DQM1 = 75
1177 16:43:44.956214 DQ Delay:
1178 16:43:44.959366 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1179 16:43:44.963354 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1180 16:43:44.966947 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =72
1181 16:43:44.967114 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1182 16:43:44.967184
1183 16:43:44.970752
1184 16:43:44.977238 [DQSOSCAuto] RK0, (LSB)MR18= 0x4627, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1185 16:43:44.981127 CH0 RK0: MR19=606, MR18=4627
1186 16:43:44.984517 CH0_RK0: MR19=0x606, MR18=0x4627, DQSOSC=392, MR23=63, INC=96, DEC=64
1187 16:43:44.984642
1188 16:43:44.988820 ----->DramcWriteLeveling(PI) begin...
1189 16:43:44.988946 ==
1190 16:43:44.991979 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 16:43:44.995542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 16:43:44.995662 ==
1193 16:43:44.999582 Write leveling (Byte 0): 31 => 31
1194 16:43:45.003255 Write leveling (Byte 1): 30 => 30
1195 16:43:45.006609 DramcWriteLeveling(PI) end<-----
1196 16:43:45.006726
1197 16:43:45.006796 ==
1198 16:43:45.009834 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 16:43:45.053923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 16:43:45.054098 ==
1201 16:43:45.054202 [Gating] SW mode calibration
1202 16:43:45.054473 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1203 16:43:45.055090 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1204 16:43:45.055176 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1205 16:43:45.055424 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 16:43:45.055494 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1207 16:43:45.055736 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 16:43:45.055987 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 16:43:45.056054 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 16:43:45.096872 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 16:43:45.097026 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 16:43:45.097108 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 16:43:45.097396 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 16:43:45.097480 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 16:43:45.097567 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 16:43:45.097657 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 16:43:45.097937 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 16:43:45.100654 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 16:43:45.100740 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 16:43:45.104104 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 16:43:45.107507 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1222 16:43:45.110789 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1223 16:43:45.117266 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 16:43:45.120945 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 16:43:45.123943 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 16:43:45.130892 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 16:43:45.134004 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:43:45.137034 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:43:45.143650 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:43:45.147023 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1231 16:43:45.150124 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1232 16:43:45.157235 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 16:43:45.160300 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 16:43:45.163920 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 16:43:45.170373 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 16:43:45.174051 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 16:43:45.177073 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1238 16:43:45.183693 0 10 8 | B1->B0 | 3030 2c2c | 0 0 | (0 1) (0 1)
1239 16:43:45.187170 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1240 16:43:45.190294 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 16:43:45.196821 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 16:43:45.200319 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 16:43:45.203680 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 16:43:45.209866 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 16:43:45.213257 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1246 16:43:45.216970 0 11 8 | B1->B0 | 2f2f 3636 | 0 1 | (0 0) (0 0)
1247 16:43:45.223164 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1248 16:43:45.226692 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 16:43:45.229636 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 16:43:45.236317 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 16:43:45.240027 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 16:43:45.242975 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 16:43:45.250096 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 16:43:45.253139 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1255 16:43:45.256666 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1256 16:43:45.263081 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 16:43:45.266158 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 16:43:45.269781 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 16:43:45.276140 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 16:43:45.279683 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 16:43:45.282741 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 16:43:45.289532 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 16:43:45.293153 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 16:43:45.296260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 16:43:45.302669 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 16:43:45.306071 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 16:43:45.309725 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 16:43:45.316346 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 16:43:45.319596 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 16:43:45.323021 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1271 16:43:45.329196 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1272 16:43:45.329321 Total UI for P1: 0, mck2ui 16
1273 16:43:45.332715 best dqsien dly found for B0: ( 0, 14, 8)
1274 16:43:45.339289 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 16:43:45.342973 Total UI for P1: 0, mck2ui 16
1276 16:43:45.345896 best dqsien dly found for B1: ( 0, 14, 10)
1277 16:43:45.349490 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1278 16:43:45.352490 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1279 16:43:45.352598
1280 16:43:45.356051 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1281 16:43:45.359004 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1282 16:43:45.362720 [Gating] SW calibration Done
1283 16:43:45.362798 ==
1284 16:43:45.366103 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 16:43:45.369151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 16:43:45.369230 ==
1287 16:43:45.372201 RX Vref Scan: 0
1288 16:43:45.372275
1289 16:43:45.375782 RX Vref 0 -> 0, step: 1
1290 16:43:45.375869
1291 16:43:45.375935 RX Delay -130 -> 252, step: 16
1292 16:43:45.382309 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1293 16:43:45.386007 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1294 16:43:45.388881 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1295 16:43:45.392559 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1296 16:43:45.396115 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1297 16:43:45.402315 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1298 16:43:45.405773 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1299 16:43:45.409114 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1300 16:43:45.412091 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1301 16:43:45.415793 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1302 16:43:45.422078 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1303 16:43:45.425246 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1304 16:43:45.428620 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1305 16:43:45.431944 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1306 16:43:45.438801 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1307 16:43:45.442318 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1308 16:43:45.442438 ==
1309 16:43:45.445383 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 16:43:45.449116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 16:43:45.449226 ==
1312 16:43:45.449322 DQS Delay:
1313 16:43:45.452152 DQS0 = 0, DQS1 = 0
1314 16:43:45.452249 DQM Delay:
1315 16:43:45.455107 DQM0 = 82, DQM1 = 74
1316 16:43:45.455207 DQ Delay:
1317 16:43:45.458491 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1318 16:43:45.462069 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1319 16:43:45.465684 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1320 16:43:45.468586 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1321 16:43:45.468697
1322 16:43:45.468817
1323 16:43:45.468943 ==
1324 16:43:45.472110 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 16:43:45.475152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 16:43:45.478827 ==
1327 16:43:45.478915
1328 16:43:45.479008
1329 16:43:45.479094 TX Vref Scan disable
1330 16:43:45.481702 == TX Byte 0 ==
1331 16:43:45.485322 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1332 16:43:45.488428 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1333 16:43:45.491989 == TX Byte 1 ==
1334 16:43:45.494997 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1335 16:43:45.498573 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1336 16:43:45.501584 ==
1337 16:43:45.505274 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 16:43:45.508239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 16:43:45.508354 ==
1340 16:43:45.520561 TX Vref=22, minBit 8, minWin=26, winSum=442
1341 16:43:45.524073 TX Vref=24, minBit 9, minWin=27, winSum=450
1342 16:43:45.527409 TX Vref=26, minBit 9, minWin=27, winSum=448
1343 16:43:45.530670 TX Vref=28, minBit 9, minWin=27, winSum=448
1344 16:43:45.533784 TX Vref=30, minBit 9, minWin=27, winSum=447
1345 16:43:45.540582 TX Vref=32, minBit 8, minWin=27, winSum=445
1346 16:43:45.544017 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 24
1347 16:43:45.544122
1348 16:43:45.547475 Final TX Range 1 Vref 24
1349 16:43:45.547584
1350 16:43:45.547682 ==
1351 16:43:45.550586 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 16:43:45.554208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 16:43:45.554287 ==
1354 16:43:45.557277
1355 16:43:45.557358
1356 16:43:45.557421 TX Vref Scan disable
1357 16:43:45.560881 == TX Byte 0 ==
1358 16:43:45.563737 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1359 16:43:45.570269 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1360 16:43:45.570368 == TX Byte 1 ==
1361 16:43:45.573800 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1362 16:43:45.580353 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1363 16:43:45.580460
1364 16:43:45.580524 [DATLAT]
1365 16:43:45.580582 Freq=800, CH0 RK1
1366 16:43:45.580639
1367 16:43:45.583951 DATLAT Default: 0xa
1368 16:43:45.584033 0, 0xFFFF, sum = 0
1369 16:43:45.587353 1, 0xFFFF, sum = 0
1370 16:43:45.587438 2, 0xFFFF, sum = 0
1371 16:43:45.590388 3, 0xFFFF, sum = 0
1372 16:43:45.590473 4, 0xFFFF, sum = 0
1373 16:43:45.593956 5, 0xFFFF, sum = 0
1374 16:43:45.596948 6, 0xFFFF, sum = 0
1375 16:43:45.597035 7, 0xFFFF, sum = 0
1376 16:43:45.600590 8, 0xFFFF, sum = 0
1377 16:43:45.600675 9, 0x0, sum = 1
1378 16:43:45.600741 10, 0x0, sum = 2
1379 16:43:45.603493 11, 0x0, sum = 3
1380 16:43:45.603576 12, 0x0, sum = 4
1381 16:43:45.607099 best_step = 10
1382 16:43:45.607197
1383 16:43:45.607261 ==
1384 16:43:45.610789 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 16:43:45.613682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 16:43:45.613825 ==
1387 16:43:45.616748 RX Vref Scan: 0
1388 16:43:45.616832
1389 16:43:45.616895 RX Vref 0 -> 0, step: 1
1390 16:43:45.620285
1391 16:43:45.620412 RX Delay -111 -> 252, step: 8
1392 16:43:45.627090 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1393 16:43:45.630548 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1394 16:43:45.634119 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1395 16:43:45.637729 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1396 16:43:45.640503 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1397 16:43:45.647355 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1398 16:43:45.650795 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1399 16:43:45.654137 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1400 16:43:45.657147 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1401 16:43:45.660815 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1402 16:43:45.667216 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1403 16:43:45.670132 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1404 16:43:45.673911 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1405 16:43:45.676740 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1406 16:43:45.683428 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1407 16:43:45.687024 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1408 16:43:45.687164 ==
1409 16:43:45.690042 Dram Type= 6, Freq= 0, CH_0, rank 1
1410 16:43:45.693465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 16:43:45.693555 ==
1412 16:43:45.697180 DQS Delay:
1413 16:43:45.697281 DQS0 = 0, DQS1 = 0
1414 16:43:45.697344 DQM Delay:
1415 16:43:45.700144 DQM0 = 84, DQM1 = 77
1416 16:43:45.700225 DQ Delay:
1417 16:43:45.703718 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =80
1418 16:43:45.706698 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1419 16:43:45.710280 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1420 16:43:45.713238 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1421 16:43:45.713351
1422 16:43:45.713417
1423 16:43:45.723411 [DQSOSCAuto] RK1, (LSB)MR18= 0x440a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
1424 16:43:45.723536 CH0 RK1: MR19=606, MR18=440A
1425 16:43:45.729711 CH0_RK1: MR19=0x606, MR18=0x440A, DQSOSC=392, MR23=63, INC=96, DEC=64
1426 16:43:45.733056 [RxdqsGatingPostProcess] freq 800
1427 16:43:45.740049 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1428 16:43:45.742973 Pre-setting of DQS Precalculation
1429 16:43:45.746261 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1430 16:43:45.746360 ==
1431 16:43:45.749524 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 16:43:45.756424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 16:43:45.756527 ==
1434 16:43:45.759912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1435 16:43:45.766532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1436 16:43:45.775580 [CA 0] Center 36 (6~67) winsize 62
1437 16:43:45.779145 [CA 1] Center 37 (7~67) winsize 61
1438 16:43:45.781960 [CA 2] Center 34 (4~65) winsize 62
1439 16:43:45.785691 [CA 3] Center 34 (3~65) winsize 63
1440 16:43:45.789234 [CA 4] Center 34 (4~65) winsize 62
1441 16:43:45.792304 [CA 5] Center 34 (3~65) winsize 63
1442 16:43:45.792393
1443 16:43:45.795753 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1444 16:43:45.795838
1445 16:43:45.799194 [CATrainingPosCal] consider 1 rank data
1446 16:43:45.802270 u2DelayCellTimex100 = 270/100 ps
1447 16:43:45.805284 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1448 16:43:45.808963 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1449 16:43:45.815604 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1450 16:43:45.818675 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1451 16:43:45.822273 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 16:43:45.825275 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1453 16:43:45.825368
1454 16:43:45.828782 CA PerBit enable=1, Macro0, CA PI delay=34
1455 16:43:45.828868
1456 16:43:45.831837 [CBTSetCACLKResult] CA Dly = 34
1457 16:43:45.831917 CS Dly: 5 (0~36)
1458 16:43:45.835243 ==
1459 16:43:45.838840 Dram Type= 6, Freq= 0, CH_1, rank 1
1460 16:43:45.842042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 16:43:45.842129 ==
1462 16:43:45.845245 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1463 16:43:45.851519 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1464 16:43:45.861558 [CA 0] Center 36 (6~67) winsize 62
1465 16:43:45.865233 [CA 1] Center 36 (6~67) winsize 62
1466 16:43:45.868118 [CA 2] Center 34 (4~65) winsize 62
1467 16:43:45.871736 [CA 3] Center 34 (3~65) winsize 63
1468 16:43:45.875308 [CA 4] Center 34 (4~65) winsize 62
1469 16:43:45.878204 [CA 5] Center 34 (3~65) winsize 63
1470 16:43:45.878321
1471 16:43:45.881815 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1472 16:43:45.881905
1473 16:43:45.884839 [CATrainingPosCal] consider 2 rank data
1474 16:43:45.888282 u2DelayCellTimex100 = 270/100 ps
1475 16:43:45.891940 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1476 16:43:45.895018 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1477 16:43:45.902115 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1478 16:43:45.904901 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1479 16:43:45.908560 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 16:43:45.911593 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1481 16:43:45.911723
1482 16:43:45.915048 CA PerBit enable=1, Macro0, CA PI delay=34
1483 16:43:45.915161
1484 16:43:45.918063 [CBTSetCACLKResult] CA Dly = 34
1485 16:43:45.918149 CS Dly: 6 (0~38)
1486 16:43:45.918215
1487 16:43:45.924742 ----->DramcWriteLeveling(PI) begin...
1488 16:43:45.924852 ==
1489 16:43:45.928401 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 16:43:45.931359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1491 16:43:45.931456 ==
1492 16:43:45.934955 Write leveling (Byte 0): 26 => 26
1493 16:43:45.938004 Write leveling (Byte 1): 30 => 30
1494 16:43:45.941667 DramcWriteLeveling(PI) end<-----
1495 16:43:45.941779
1496 16:43:45.941873 ==
1497 16:43:45.944569 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 16:43:45.948020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 16:43:45.948109 ==
1500 16:43:45.951487 [Gating] SW mode calibration
1501 16:43:45.957655 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1502 16:43:45.965001 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1503 16:43:45.967743 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1504 16:43:45.971078 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1505 16:43:45.977643 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1506 16:43:45.981055 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 16:43:45.984716 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 16:43:45.991236 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 16:43:45.994311 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 16:43:45.997404 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 16:43:46.003960 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 16:43:46.007637 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 16:43:46.011050 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 16:43:46.017673 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 16:43:46.020674 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 16:43:46.023963 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 16:43:46.030546 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 16:43:46.034236 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 16:43:46.037333 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1520 16:43:46.040947 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1521 16:43:46.047546 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 16:43:46.050534 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 16:43:46.053907 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 16:43:46.060325 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 16:43:46.063780 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:43:46.066700 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:43:46.073445 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:43:46.076925 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1529 16:43:46.080265 0 9 8 | B1->B0 | 2a2a 2f2f | 0 1 | (0 0) (1 1)
1530 16:43:46.087008 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 16:43:46.089934 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 16:43:46.093291 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 16:43:46.099927 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 16:43:46.103613 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 16:43:46.106637 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 16:43:46.113691 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1537 16:43:46.116723 0 10 8 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
1538 16:43:46.120439 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 16:43:46.126935 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 16:43:46.129955 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 16:43:46.133424 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 16:43:46.139968 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 16:43:46.143600 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 16:43:46.146498 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 16:43:46.153294 0 11 8 | B1->B0 | 3d3d 3f3f | 0 1 | (0 0) (0 0)
1546 16:43:46.156859 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 16:43:46.159610 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 16:43:46.166742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 16:43:46.169670 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 16:43:46.173159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 16:43:46.179425 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 16:43:46.183256 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1553 16:43:46.186086 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1554 16:43:46.192948 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 16:43:46.196482 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 16:43:46.199338 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 16:43:46.206143 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 16:43:46.209794 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 16:43:46.212790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 16:43:46.219850 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 16:43:46.222943 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 16:43:46.226041 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 16:43:46.232577 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 16:43:46.236154 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 16:43:46.239698 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 16:43:46.245735 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 16:43:46.249384 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 16:43:46.252521 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1569 16:43:46.259007 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 16:43:46.259135 Total UI for P1: 0, mck2ui 16
1571 16:43:46.262514 best dqsien dly found for B0: ( 0, 14, 4)
1572 16:43:46.266159 Total UI for P1: 0, mck2ui 16
1573 16:43:46.269096 best dqsien dly found for B1: ( 0, 14, 4)
1574 16:43:46.272619 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1575 16:43:46.278956 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1576 16:43:46.279100
1577 16:43:46.282358 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1578 16:43:46.285753 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1579 16:43:46.288746 [Gating] SW calibration Done
1580 16:43:46.288837 ==
1581 16:43:46.292148 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 16:43:46.295802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 16:43:46.295906 ==
1584 16:43:46.298927 RX Vref Scan: 0
1585 16:43:46.299013
1586 16:43:46.299099 RX Vref 0 -> 0, step: 1
1587 16:43:46.299176
1588 16:43:46.302188 RX Delay -130 -> 252, step: 16
1589 16:43:46.305707 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1590 16:43:46.311970 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1591 16:43:46.315617 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1592 16:43:46.318993 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1593 16:43:46.321924 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1594 16:43:46.325502 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1595 16:43:46.332123 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1596 16:43:46.335151 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1597 16:43:46.338779 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1598 16:43:46.341679 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1599 16:43:46.345400 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1600 16:43:46.352132 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1601 16:43:46.355098 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1602 16:43:46.358724 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1603 16:43:46.361683 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1604 16:43:46.365253 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1605 16:43:46.368711 ==
1606 16:43:46.371830 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 16:43:46.375363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 16:43:46.375462 ==
1609 16:43:46.375529 DQS Delay:
1610 16:43:46.378606 DQS0 = 0, DQS1 = 0
1611 16:43:46.378692 DQM Delay:
1612 16:43:46.381773 DQM0 = 88, DQM1 = 79
1613 16:43:46.381861 DQ Delay:
1614 16:43:46.385279 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1615 16:43:46.388519 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1616 16:43:46.391934 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1617 16:43:46.394696 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1618 16:43:46.394790
1619 16:43:46.394855
1620 16:43:46.394939 ==
1621 16:43:46.398120 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 16:43:46.401565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 16:43:46.401660 ==
1624 16:43:46.401728
1625 16:43:46.401789
1626 16:43:46.404803 TX Vref Scan disable
1627 16:43:46.408067 == TX Byte 0 ==
1628 16:43:46.411730 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1629 16:43:46.414453 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1630 16:43:46.417972 == TX Byte 1 ==
1631 16:43:46.421127 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1632 16:43:46.424514 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1633 16:43:46.424613 ==
1634 16:43:46.428078 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 16:43:46.434689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 16:43:46.434804 ==
1637 16:43:46.446583 TX Vref=22, minBit 2, minWin=27, winSum=439
1638 16:43:46.449612 TX Vref=24, minBit 8, minWin=27, winSum=446
1639 16:43:46.453205 TX Vref=26, minBit 0, minWin=27, winSum=449
1640 16:43:46.456200 TX Vref=28, minBit 10, minWin=27, winSum=449
1641 16:43:46.459875 TX Vref=30, minBit 13, minWin=27, winSum=451
1642 16:43:46.466647 TX Vref=32, minBit 8, minWin=27, winSum=447
1643 16:43:46.470038 [TxChooseVref] Worse bit 13, Min win 27, Win sum 451, Final Vref 30
1644 16:43:46.470159
1645 16:43:46.472911 Final TX Range 1 Vref 30
1646 16:43:46.473017
1647 16:43:46.473087 ==
1648 16:43:46.476748 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 16:43:46.479736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 16:43:46.483317 ==
1651 16:43:46.483416
1652 16:43:46.483491
1653 16:43:46.483555 TX Vref Scan disable
1654 16:43:46.486776 == TX Byte 0 ==
1655 16:43:46.490540 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1656 16:43:46.496907 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1657 16:43:46.497021 == TX Byte 1 ==
1658 16:43:46.499814 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1659 16:43:46.506689 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1660 16:43:46.506798
1661 16:43:46.506870 [DATLAT]
1662 16:43:46.506932 Freq=800, CH1 RK0
1663 16:43:46.506992
1664 16:43:46.510001 DATLAT Default: 0xa
1665 16:43:46.510082 0, 0xFFFF, sum = 0
1666 16:43:46.513392 1, 0xFFFF, sum = 0
1667 16:43:46.516737 2, 0xFFFF, sum = 0
1668 16:43:46.516828 3, 0xFFFF, sum = 0
1669 16:43:46.519797 4, 0xFFFF, sum = 0
1670 16:43:46.519885 5, 0xFFFF, sum = 0
1671 16:43:46.523083 6, 0xFFFF, sum = 0
1672 16:43:46.523169 7, 0xFFFF, sum = 0
1673 16:43:46.526725 8, 0xFFFF, sum = 0
1674 16:43:46.526815 9, 0x0, sum = 1
1675 16:43:46.529642 10, 0x0, sum = 2
1676 16:43:46.529723 11, 0x0, sum = 3
1677 16:43:46.529793 12, 0x0, sum = 4
1678 16:43:46.533252 best_step = 10
1679 16:43:46.533334
1680 16:43:46.533398 ==
1681 16:43:46.536242 Dram Type= 6, Freq= 0, CH_1, rank 0
1682 16:43:46.539693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1683 16:43:46.539780 ==
1684 16:43:46.543379 RX Vref Scan: 1
1685 16:43:46.543470
1686 16:43:46.546385 Set Vref Range= 32 -> 127
1687 16:43:46.546475
1688 16:43:46.546544 RX Vref 32 -> 127, step: 1
1689 16:43:46.546605
1690 16:43:46.549960 RX Delay -95 -> 252, step: 8
1691 16:43:46.550047
1692 16:43:46.553016 Set Vref, RX VrefLevel [Byte0]: 32
1693 16:43:46.556641 [Byte1]: 32
1694 16:43:46.556773
1695 16:43:46.559687 Set Vref, RX VrefLevel [Byte0]: 33
1696 16:43:46.562702 [Byte1]: 33
1697 16:43:46.566985
1698 16:43:46.567126 Set Vref, RX VrefLevel [Byte0]: 34
1699 16:43:46.570516 [Byte1]: 34
1700 16:43:46.574723
1701 16:43:46.574819 Set Vref, RX VrefLevel [Byte0]: 35
1702 16:43:46.577689 [Byte1]: 35
1703 16:43:46.581994
1704 16:43:46.582093 Set Vref, RX VrefLevel [Byte0]: 36
1705 16:43:46.585625 [Byte1]: 36
1706 16:43:46.589892
1707 16:43:46.589986 Set Vref, RX VrefLevel [Byte0]: 37
1708 16:43:46.593182 [Byte1]: 37
1709 16:43:46.597368
1710 16:43:46.597469 Set Vref, RX VrefLevel [Byte0]: 38
1711 16:43:46.600891 [Byte1]: 38
1712 16:43:46.605249
1713 16:43:46.605346 Set Vref, RX VrefLevel [Byte0]: 39
1714 16:43:46.608588 [Byte1]: 39
1715 16:43:46.612636
1716 16:43:46.612737 Set Vref, RX VrefLevel [Byte0]: 40
1717 16:43:46.616084 [Byte1]: 40
1718 16:43:46.619974
1719 16:43:46.623373 Set Vref, RX VrefLevel [Byte0]: 41
1720 16:43:46.626689 [Byte1]: 41
1721 16:43:46.626788
1722 16:43:46.630411 Set Vref, RX VrefLevel [Byte0]: 42
1723 16:43:46.633672 [Byte1]: 42
1724 16:43:46.633767
1725 16:43:46.636811 Set Vref, RX VrefLevel [Byte0]: 43
1726 16:43:46.639782 [Byte1]: 43
1727 16:43:46.639872
1728 16:43:46.643284 Set Vref, RX VrefLevel [Byte0]: 44
1729 16:43:46.646186 [Byte1]: 44
1730 16:43:46.650378
1731 16:43:46.650473 Set Vref, RX VrefLevel [Byte0]: 45
1732 16:43:46.654061 [Byte1]: 45
1733 16:43:46.658274
1734 16:43:46.658367 Set Vref, RX VrefLevel [Byte0]: 46
1735 16:43:46.661299 [Byte1]: 46
1736 16:43:46.666129
1737 16:43:46.666223 Set Vref, RX VrefLevel [Byte0]: 47
1738 16:43:46.669199 [Byte1]: 47
1739 16:43:46.673391
1740 16:43:46.673516 Set Vref, RX VrefLevel [Byte0]: 48
1741 16:43:46.677086 [Byte1]: 48
1742 16:43:46.681164
1743 16:43:46.681261 Set Vref, RX VrefLevel [Byte0]: 49
1744 16:43:46.684266 [Byte1]: 49
1745 16:43:46.688469
1746 16:43:46.688559 Set Vref, RX VrefLevel [Byte0]: 50
1747 16:43:46.691974 [Byte1]: 50
1748 16:43:46.696190
1749 16:43:46.696286 Set Vref, RX VrefLevel [Byte0]: 51
1750 16:43:46.699653 [Byte1]: 51
1751 16:43:46.703832
1752 16:43:46.703928 Set Vref, RX VrefLevel [Byte0]: 52
1753 16:43:46.707263 [Byte1]: 52
1754 16:43:46.711721
1755 16:43:46.711821 Set Vref, RX VrefLevel [Byte0]: 53
1756 16:43:46.714586 [Byte1]: 53
1757 16:43:46.718615
1758 16:43:46.722025 Set Vref, RX VrefLevel [Byte0]: 54
1759 16:43:46.722129 [Byte1]: 54
1760 16:43:46.726774
1761 16:43:46.726872 Set Vref, RX VrefLevel [Byte0]: 55
1762 16:43:46.730017 [Byte1]: 55
1763 16:43:46.734151
1764 16:43:46.734247 Set Vref, RX VrefLevel [Byte0]: 56
1765 16:43:46.737424 [Byte1]: 56
1766 16:43:46.741667
1767 16:43:46.741758 Set Vref, RX VrefLevel [Byte0]: 57
1768 16:43:46.745228 [Byte1]: 57
1769 16:43:46.749314
1770 16:43:46.749407 Set Vref, RX VrefLevel [Byte0]: 58
1771 16:43:46.753018 [Byte1]: 58
1772 16:43:46.757193
1773 16:43:46.757285 Set Vref, RX VrefLevel [Byte0]: 59
1774 16:43:46.760149 [Byte1]: 59
1775 16:43:46.764318
1776 16:43:46.764408 Set Vref, RX VrefLevel [Byte0]: 60
1777 16:43:46.767920 [Byte1]: 60
1778 16:43:46.772198
1779 16:43:46.772280 Set Vref, RX VrefLevel [Byte0]: 61
1780 16:43:46.775654 [Byte1]: 61
1781 16:43:46.779965
1782 16:43:46.780085 Set Vref, RX VrefLevel [Byte0]: 62
1783 16:43:46.782824 [Byte1]: 62
1784 16:43:46.787011
1785 16:43:46.787148 Set Vref, RX VrefLevel [Byte0]: 63
1786 16:43:46.790698 [Byte1]: 63
1787 16:43:46.794981
1788 16:43:46.795123 Set Vref, RX VrefLevel [Byte0]: 64
1789 16:43:46.798072 [Byte1]: 64
1790 16:43:46.802721
1791 16:43:46.802841 Set Vref, RX VrefLevel [Byte0]: 65
1792 16:43:46.805904 [Byte1]: 65
1793 16:43:46.810254
1794 16:43:46.810352 Set Vref, RX VrefLevel [Byte0]: 66
1795 16:43:46.813583 [Byte1]: 66
1796 16:43:46.817629
1797 16:43:46.817713 Set Vref, RX VrefLevel [Byte0]: 67
1798 16:43:46.821066 [Byte1]: 67
1799 16:43:46.825650
1800 16:43:46.825753 Set Vref, RX VrefLevel [Byte0]: 68
1801 16:43:46.828395 [Byte1]: 68
1802 16:43:46.832904
1803 16:43:46.833000 Set Vref, RX VrefLevel [Byte0]: 69
1804 16:43:46.836263 [Byte1]: 69
1805 16:43:46.840395
1806 16:43:46.840495 Set Vref, RX VrefLevel [Byte0]: 70
1807 16:43:46.843836 [Byte1]: 70
1808 16:43:46.847915
1809 16:43:46.848011 Final RX Vref Byte 0 = 56 to rank0
1810 16:43:46.851489 Final RX Vref Byte 1 = 64 to rank0
1811 16:43:46.854473 Final RX Vref Byte 0 = 56 to rank1
1812 16:43:46.858042 Final RX Vref Byte 1 = 64 to rank1==
1813 16:43:46.861054 Dram Type= 6, Freq= 0, CH_1, rank 0
1814 16:43:46.868272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 16:43:46.868393 ==
1816 16:43:46.868462 DQS Delay:
1817 16:43:46.871236 DQS0 = 0, DQS1 = 0
1818 16:43:46.871322 DQM Delay:
1819 16:43:46.871389 DQM0 = 87, DQM1 = 79
1820 16:43:46.874767 DQ Delay:
1821 16:43:46.877710 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1822 16:43:46.881210 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1823 16:43:46.884404 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1824 16:43:46.887881 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1825 16:43:46.888010
1826 16:43:46.888077
1827 16:43:46.894320 [DQSOSCAuto] RK0, (LSB)MR18= 0x3622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1828 16:43:46.897334 CH1 RK0: MR19=606, MR18=3622
1829 16:43:46.904713 CH1_RK0: MR19=0x606, MR18=0x3622, DQSOSC=396, MR23=63, INC=94, DEC=62
1830 16:43:46.904853
1831 16:43:46.907817 ----->DramcWriteLeveling(PI) begin...
1832 16:43:46.907949 ==
1833 16:43:46.910852 Dram Type= 6, Freq= 0, CH_1, rank 1
1834 16:43:46.914524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 16:43:46.914636 ==
1836 16:43:46.917942 Write leveling (Byte 0): 24 => 24
1837 16:43:46.920749 Write leveling (Byte 1): 28 => 28
1838 16:43:46.924096 DramcWriteLeveling(PI) end<-----
1839 16:43:46.924199
1840 16:43:46.924286 ==
1841 16:43:46.927450 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 16:43:46.930813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 16:43:46.930904 ==
1844 16:43:46.934458 [Gating] SW mode calibration
1845 16:43:46.940410 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1846 16:43:46.947513 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1847 16:43:46.950886 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1848 16:43:46.957519 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1849 16:43:46.960668 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 16:43:46.964127 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 16:43:46.970186 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 16:43:46.973876 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 16:43:46.976814 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 16:43:46.983386 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 16:43:46.987062 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 16:43:46.990239 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 16:43:46.997352 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 16:43:47.000309 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 16:43:47.003946 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 16:43:47.010596 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 16:43:47.013446 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 16:43:47.016942 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 16:43:47.023573 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 16:43:47.026860 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1865 16:43:47.030261 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 16:43:47.036594 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 16:43:47.039940 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 16:43:47.043366 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 16:43:47.046844 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 16:43:47.053593 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 16:43:47.056883 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 16:43:47.060449 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 16:43:47.066527 0 9 8 | B1->B0 | 3232 2525 | 0 1 | (0 0) (1 1)
1874 16:43:47.070112 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 16:43:47.073173 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 16:43:47.080268 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 16:43:47.083278 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 16:43:47.086945 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 16:43:47.093496 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 16:43:47.096896 0 10 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
1881 16:43:47.099988 0 10 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 0)
1882 16:43:47.106584 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:43:47.109632 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:43:47.113286 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 16:43:47.119887 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 16:43:47.123266 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 16:43:47.126507 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 16:43:47.133163 0 11 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1889 16:43:47.136442 0 11 8 | B1->B0 | 4343 3838 | 0 0 | (1 1) (0 0)
1890 16:43:47.139807 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 16:43:47.146093 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 16:43:47.149476 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 16:43:47.153069 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 16:43:47.159243 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 16:43:47.162712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 16:43:47.166161 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 16:43:47.172657 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1898 16:43:47.176294 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 16:43:47.179412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 16:43:47.185861 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 16:43:47.188946 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 16:43:47.192443 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 16:43:47.199001 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 16:43:47.202519 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 16:43:47.205526 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 16:43:47.212219 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 16:43:47.215733 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 16:43:47.219289 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 16:43:47.225840 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 16:43:47.228798 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 16:43:47.232216 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 16:43:47.238739 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 16:43:47.242028 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1914 16:43:47.245344 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 16:43:47.248844 Total UI for P1: 0, mck2ui 16
1916 16:43:47.252114 best dqsien dly found for B0: ( 0, 14, 8)
1917 16:43:47.255114 Total UI for P1: 0, mck2ui 16
1918 16:43:47.258521 best dqsien dly found for B1: ( 0, 14, 8)
1919 16:43:47.262044 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1920 16:43:47.265345 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1921 16:43:47.265431
1922 16:43:47.268802 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1923 16:43:47.275227 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1924 16:43:47.275340 [Gating] SW calibration Done
1925 16:43:47.275411 ==
1926 16:43:47.278910 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 16:43:47.284920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 16:43:47.285029 ==
1929 16:43:47.285116 RX Vref Scan: 0
1930 16:43:47.285177
1931 16:43:47.288615 RX Vref 0 -> 0, step: 1
1932 16:43:47.288701
1933 16:43:47.291527 RX Delay -130 -> 252, step: 16
1934 16:43:47.295007 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1935 16:43:47.298168 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1936 16:43:47.301364 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1937 16:43:47.307986 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1938 16:43:47.311635 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1939 16:43:47.314595 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1940 16:43:47.318341 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1941 16:43:47.321305 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1942 16:43:47.328011 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1943 16:43:47.331183 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1944 16:43:47.334657 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1945 16:43:47.337660 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1946 16:43:47.344618 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1947 16:43:47.348037 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1948 16:43:47.350818 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1949 16:43:47.354129 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1950 16:43:47.354224 ==
1951 16:43:47.357635 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 16:43:47.364453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 16:43:47.364593 ==
1954 16:43:47.364693 DQS Delay:
1955 16:43:47.364787 DQS0 = 0, DQS1 = 0
1956 16:43:47.367773 DQM Delay:
1957 16:43:47.367852 DQM0 = 88, DQM1 = 81
1958 16:43:47.370972 DQ Delay:
1959 16:43:47.374347 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1960 16:43:47.377756 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1961 16:43:47.380531 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1962 16:43:47.384273 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1963 16:43:47.384361
1964 16:43:47.384428
1965 16:43:47.384488 ==
1966 16:43:47.387854 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 16:43:47.390708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 16:43:47.390801 ==
1969 16:43:47.390869
1970 16:43:47.390931
1971 16:43:47.394272 TX Vref Scan disable
1972 16:43:47.394361 == TX Byte 0 ==
1973 16:43:47.400897 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1974 16:43:47.403969 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1975 16:43:47.404073 == TX Byte 1 ==
1976 16:43:47.410465 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1977 16:43:47.413929 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1978 16:43:47.414046 ==
1979 16:43:47.417402 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 16:43:47.420424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 16:43:47.420516 ==
1982 16:43:47.435102 TX Vref=22, minBit 1, minWin=26, winSum=436
1983 16:43:47.438682 TX Vref=24, minBit 3, minWin=27, winSum=446
1984 16:43:47.442161 TX Vref=26, minBit 0, minWin=27, winSum=445
1985 16:43:47.445432 TX Vref=28, minBit 3, minWin=27, winSum=447
1986 16:43:47.448548 TX Vref=30, minBit 8, minWin=27, winSum=445
1987 16:43:47.452108 TX Vref=32, minBit 1, minWin=27, winSum=443
1988 16:43:47.458409 [TxChooseVref] Worse bit 3, Min win 27, Win sum 447, Final Vref 28
1989 16:43:47.458525
1990 16:43:47.461921 Final TX Range 1 Vref 28
1991 16:43:47.462011
1992 16:43:47.462076 ==
1993 16:43:47.464738 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 16:43:47.468136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 16:43:47.468227 ==
1996 16:43:47.468292
1997 16:43:47.471777
1998 16:43:47.471905 TX Vref Scan disable
1999 16:43:47.475074 == TX Byte 0 ==
2000 16:43:47.478067 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2001 16:43:47.481488 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2002 16:43:47.484968 == TX Byte 1 ==
2003 16:43:47.488539 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2004 16:43:47.494742 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2005 16:43:47.494853
2006 16:43:47.494920 [DATLAT]
2007 16:43:47.494981 Freq=800, CH1 RK1
2008 16:43:47.495040
2009 16:43:47.498288 DATLAT Default: 0xa
2010 16:43:47.498373 0, 0xFFFF, sum = 0
2011 16:43:47.501343 1, 0xFFFF, sum = 0
2012 16:43:47.501446 2, 0xFFFF, sum = 0
2013 16:43:47.504963 3, 0xFFFF, sum = 0
2014 16:43:47.508000 4, 0xFFFF, sum = 0
2015 16:43:47.508094 5, 0xFFFF, sum = 0
2016 16:43:47.511446 6, 0xFFFF, sum = 0
2017 16:43:47.511543 7, 0xFFFF, sum = 0
2018 16:43:47.515041 8, 0xFFFF, sum = 0
2019 16:43:47.515185 9, 0x0, sum = 1
2020 16:43:47.518180 10, 0x0, sum = 2
2021 16:43:47.518283 11, 0x0, sum = 3
2022 16:43:47.518374 12, 0x0, sum = 4
2023 16:43:47.521271 best_step = 10
2024 16:43:47.521384
2025 16:43:47.521478 ==
2026 16:43:47.524771 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 16:43:47.528382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 16:43:47.528476 ==
2029 16:43:47.531395 RX Vref Scan: 0
2030 16:43:47.531481
2031 16:43:47.531546 RX Vref 0 -> 0, step: 1
2032 16:43:47.534498
2033 16:43:47.534583 RX Delay -95 -> 252, step: 8
2034 16:43:47.541760 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2035 16:43:47.544787 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2036 16:43:47.548263 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2037 16:43:47.551666 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2038 16:43:47.555365 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2039 16:43:47.561485 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2040 16:43:47.564914 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2041 16:43:47.568381 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2042 16:43:47.571715 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2043 16:43:47.575284 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2044 16:43:47.581494 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2045 16:43:47.584845 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2046 16:43:47.588290 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2047 16:43:47.591508 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2048 16:43:47.595078 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2049 16:43:47.601762 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2050 16:43:47.601876 ==
2051 16:43:47.604790 Dram Type= 6, Freq= 0, CH_1, rank 1
2052 16:43:47.608355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2053 16:43:47.608449 ==
2054 16:43:47.608522 DQS Delay:
2055 16:43:47.611934 DQS0 = 0, DQS1 = 0
2056 16:43:47.612030 DQM Delay:
2057 16:43:47.614979 DQM0 = 87, DQM1 = 79
2058 16:43:47.615114 DQ Delay:
2059 16:43:47.618333 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2060 16:43:47.621262 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2061 16:43:47.624939 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =68
2062 16:43:47.627940 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2063 16:43:47.628048
2064 16:43:47.628142
2065 16:43:47.638370 [DQSOSCAuto] RK1, (LSB)MR18= 0x1710, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
2066 16:43:47.638520 CH1 RK1: MR19=606, MR18=1710
2067 16:43:47.644966 CH1_RK1: MR19=0x606, MR18=0x1710, DQSOSC=404, MR23=63, INC=90, DEC=60
2068 16:43:47.647917 [RxdqsGatingPostProcess] freq 800
2069 16:43:47.654837 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2070 16:43:47.658242 Pre-setting of DQS Precalculation
2071 16:43:47.661215 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2072 16:43:47.668096 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2073 16:43:47.677783 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2074 16:43:47.677910
2075 16:43:47.677982
2076 16:43:47.681196 [Calibration Summary] 1600 Mbps
2077 16:43:47.681285 CH 0, Rank 0
2078 16:43:47.684665 SW Impedance : PASS
2079 16:43:47.684753 DUTY Scan : NO K
2080 16:43:47.687558 ZQ Calibration : PASS
2081 16:43:47.690995 Jitter Meter : NO K
2082 16:43:47.691128 CBT Training : PASS
2083 16:43:47.694397 Write leveling : PASS
2084 16:43:47.694484 RX DQS gating : PASS
2085 16:43:47.697755 RX DQ/DQS(RDDQC) : PASS
2086 16:43:47.701153 TX DQ/DQS : PASS
2087 16:43:47.701251 RX DATLAT : PASS
2088 16:43:47.704760 RX DQ/DQS(Engine): PASS
2089 16:43:47.707770 TX OE : NO K
2090 16:43:47.707860 All Pass.
2091 16:43:47.707927
2092 16:43:47.707987 CH 0, Rank 1
2093 16:43:47.711327 SW Impedance : PASS
2094 16:43:47.714300 DUTY Scan : NO K
2095 16:43:47.714389 ZQ Calibration : PASS
2096 16:43:47.717453 Jitter Meter : NO K
2097 16:43:47.721004 CBT Training : PASS
2098 16:43:47.721100 Write leveling : PASS
2099 16:43:47.724168 RX DQS gating : PASS
2100 16:43:47.727789 RX DQ/DQS(RDDQC) : PASS
2101 16:43:47.727883 TX DQ/DQS : PASS
2102 16:43:47.730821 RX DATLAT : PASS
2103 16:43:47.734512 RX DQ/DQS(Engine): PASS
2104 16:43:47.734602 TX OE : NO K
2105 16:43:47.734670 All Pass.
2106 16:43:47.737506
2107 16:43:47.737593 CH 1, Rank 0
2108 16:43:47.741169 SW Impedance : PASS
2109 16:43:47.741261 DUTY Scan : NO K
2110 16:43:47.744254 ZQ Calibration : PASS
2111 16:43:47.744343 Jitter Meter : NO K
2112 16:43:47.747333 CBT Training : PASS
2113 16:43:47.750862 Write leveling : PASS
2114 16:43:47.750953 RX DQS gating : PASS
2115 16:43:47.753877 RX DQ/DQS(RDDQC) : PASS
2116 16:43:47.757417 TX DQ/DQS : PASS
2117 16:43:47.757508 RX DATLAT : PASS
2118 16:43:47.760873 RX DQ/DQS(Engine): PASS
2119 16:43:47.764832 TX OE : NO K
2120 16:43:47.764929 All Pass.
2121 16:43:47.764995
2122 16:43:47.765056 CH 1, Rank 1
2123 16:43:47.767492 SW Impedance : PASS
2124 16:43:47.770858 DUTY Scan : NO K
2125 16:43:47.770947 ZQ Calibration : PASS
2126 16:43:47.774213 Jitter Meter : NO K
2127 16:43:47.777117 CBT Training : PASS
2128 16:43:47.777205 Write leveling : PASS
2129 16:43:47.781012 RX DQS gating : PASS
2130 16:43:47.784004 RX DQ/DQS(RDDQC) : PASS
2131 16:43:47.784113 TX DQ/DQS : PASS
2132 16:43:47.787235 RX DATLAT : PASS
2133 16:43:47.790504 RX DQ/DQS(Engine): PASS
2134 16:43:47.790593 TX OE : NO K
2135 16:43:47.790678 All Pass.
2136 16:43:47.790741
2137 16:43:47.793830 DramC Write-DBI off
2138 16:43:47.797248 PER_BANK_REFRESH: Hybrid Mode
2139 16:43:47.797339 TX_TRACKING: ON
2140 16:43:47.800681 [GetDramInforAfterCalByMRR] Vendor 6.
2141 16:43:47.804028 [GetDramInforAfterCalByMRR] Revision 606.
2142 16:43:47.810671 [GetDramInforAfterCalByMRR] Revision 2 0.
2143 16:43:47.810786 MR0 0x3b3b
2144 16:43:47.810856 MR8 0x5151
2145 16:43:47.813681 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2146 16:43:47.813769
2147 16:43:47.817331 MR0 0x3b3b
2148 16:43:47.817419 MR8 0x5151
2149 16:43:47.820410 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2150 16:43:47.820500
2151 16:43:47.830405 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2152 16:43:47.834121 [FAST_K] Save calibration result to emmc
2153 16:43:47.837111 [FAST_K] Save calibration result to emmc
2154 16:43:47.840759 dram_init: config_dvfs: 1
2155 16:43:47.843646 dramc_set_vcore_voltage set vcore to 662500
2156 16:43:47.847318 Read voltage for 1200, 2
2157 16:43:47.847417 Vio18 = 0
2158 16:43:47.847483 Vcore = 662500
2159 16:43:47.850259 Vdram = 0
2160 16:43:47.850342 Vddq = 0
2161 16:43:47.850408 Vmddr = 0
2162 16:43:47.856917 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2163 16:43:47.860502 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2164 16:43:47.863485 MEM_TYPE=3, freq_sel=15
2165 16:43:47.866987 sv_algorithm_assistance_LP4_1600
2166 16:43:47.870377 ============ PULL DRAM RESETB DOWN ============
2167 16:43:47.873399 ========== PULL DRAM RESETB DOWN end =========
2168 16:43:47.880246 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2169 16:43:47.883894 ===================================
2170 16:43:47.883999 LPDDR4 DRAM CONFIGURATION
2171 16:43:47.886490 ===================================
2172 16:43:47.889879 EX_ROW_EN[0] = 0x0
2173 16:43:47.893382 EX_ROW_EN[1] = 0x0
2174 16:43:47.893475 LP4Y_EN = 0x0
2175 16:43:47.896811 WORK_FSP = 0x0
2176 16:43:47.896899 WL = 0x4
2177 16:43:47.900141 RL = 0x4
2178 16:43:47.900229 BL = 0x2
2179 16:43:47.903022 RPST = 0x0
2180 16:43:47.903135 RD_PRE = 0x0
2181 16:43:47.906419 WR_PRE = 0x1
2182 16:43:47.906506 WR_PST = 0x0
2183 16:43:47.909936 DBI_WR = 0x0
2184 16:43:47.910043 DBI_RD = 0x0
2185 16:43:47.913377 OTF = 0x1
2186 16:43:47.916362 ===================================
2187 16:43:47.920061 ===================================
2188 16:43:47.920151 ANA top config
2189 16:43:47.922970 ===================================
2190 16:43:47.926615 DLL_ASYNC_EN = 0
2191 16:43:47.929667 ALL_SLAVE_EN = 0
2192 16:43:47.933117 NEW_RANK_MODE = 1
2193 16:43:47.933213 DLL_IDLE_MODE = 1
2194 16:43:47.936216 LP45_APHY_COMB_EN = 1
2195 16:43:47.939772 TX_ODT_DIS = 1
2196 16:43:47.942785 NEW_8X_MODE = 1
2197 16:43:47.946479 ===================================
2198 16:43:47.949524 ===================================
2199 16:43:47.953103 data_rate = 2400
2200 16:43:47.953198 CKR = 1
2201 16:43:47.956154 DQ_P2S_RATIO = 8
2202 16:43:47.959236 ===================================
2203 16:43:47.962776 CA_P2S_RATIO = 8
2204 16:43:47.966417 DQ_CA_OPEN = 0
2205 16:43:47.969436 DQ_SEMI_OPEN = 0
2206 16:43:47.972901 CA_SEMI_OPEN = 0
2207 16:43:47.972994 CA_FULL_RATE = 0
2208 16:43:47.976345 DQ_CKDIV4_EN = 0
2209 16:43:47.979765 CA_CKDIV4_EN = 0
2210 16:43:47.982613 CA_PREDIV_EN = 0
2211 16:43:47.985839 PH8_DLY = 17
2212 16:43:47.989354 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2213 16:43:47.989449 DQ_AAMCK_DIV = 4
2214 16:43:47.992355 CA_AAMCK_DIV = 4
2215 16:43:47.995746 CA_ADMCK_DIV = 4
2216 16:43:47.999096 DQ_TRACK_CA_EN = 0
2217 16:43:48.002531 CA_PICK = 1200
2218 16:43:48.005884 CA_MCKIO = 1200
2219 16:43:48.009353 MCKIO_SEMI = 0
2220 16:43:48.009448 PLL_FREQ = 2366
2221 16:43:48.012224 DQ_UI_PI_RATIO = 32
2222 16:43:48.015735 CA_UI_PI_RATIO = 0
2223 16:43:48.019053 ===================================
2224 16:43:48.022087 ===================================
2225 16:43:48.025738 memory_type:LPDDR4
2226 16:43:48.028685 GP_NUM : 10
2227 16:43:48.028781 SRAM_EN : 1
2228 16:43:48.032244 MD32_EN : 0
2229 16:43:48.035777 ===================================
2230 16:43:48.035871 [ANA_INIT] >>>>>>>>>>>>>>
2231 16:43:48.038774 <<<<<< [CONFIGURE PHASE]: ANA_TX
2232 16:43:48.042486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2233 16:43:48.045459 ===================================
2234 16:43:48.049213 data_rate = 2400,PCW = 0X5b00
2235 16:43:48.052146 ===================================
2236 16:43:48.055852 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2237 16:43:48.062452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2238 16:43:48.069092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2239 16:43:48.072257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2240 16:43:48.075289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2241 16:43:48.078952 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2242 16:43:48.081892 [ANA_INIT] flow start
2243 16:43:48.081987 [ANA_INIT] PLL >>>>>>>>
2244 16:43:48.085654 [ANA_INIT] PLL <<<<<<<<
2245 16:43:48.088804 [ANA_INIT] MIDPI >>>>>>>>
2246 16:43:48.088893 [ANA_INIT] MIDPI <<<<<<<<
2247 16:43:48.092052 [ANA_INIT] DLL >>>>>>>>
2248 16:43:48.095431 [ANA_INIT] DLL <<<<<<<<
2249 16:43:48.095523 [ANA_INIT] flow end
2250 16:43:48.102086 ============ LP4 DIFF to SE enter ============
2251 16:43:48.105350 ============ LP4 DIFF to SE exit ============
2252 16:43:48.108861 [ANA_INIT] <<<<<<<<<<<<<
2253 16:43:48.112146 [Flow] Enable top DCM control >>>>>
2254 16:43:48.115465 [Flow] Enable top DCM control <<<<<
2255 16:43:48.115568 Enable DLL master slave shuffle
2256 16:43:48.121666 ==============================================================
2257 16:43:48.124946 Gating Mode config
2258 16:43:48.128249 ==============================================================
2259 16:43:48.131929 Config description:
2260 16:43:48.142144 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2261 16:43:48.148168 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2262 16:43:48.151884 SELPH_MODE 0: By rank 1: By Phase
2263 16:43:48.158637 ==============================================================
2264 16:43:48.161736 GAT_TRACK_EN = 1
2265 16:43:48.165359 RX_GATING_MODE = 2
2266 16:43:48.168296 RX_GATING_TRACK_MODE = 2
2267 16:43:48.168390 SELPH_MODE = 1
2268 16:43:48.172003 PICG_EARLY_EN = 1
2269 16:43:48.174967 VALID_LAT_VALUE = 1
2270 16:43:48.181518 ==============================================================
2271 16:43:48.185132 Enter into Gating configuration >>>>
2272 16:43:48.188150 Exit from Gating configuration <<<<
2273 16:43:48.191671 Enter into DVFS_PRE_config >>>>>
2274 16:43:48.201846 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2275 16:43:48.204767 Exit from DVFS_PRE_config <<<<<
2276 16:43:48.208294 Enter into PICG configuration >>>>
2277 16:43:48.211447 Exit from PICG configuration <<<<
2278 16:43:48.214895 [RX_INPUT] configuration >>>>>
2279 16:43:48.217865 [RX_INPUT] configuration <<<<<
2280 16:43:48.221219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2281 16:43:48.227674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2282 16:43:48.234454 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2283 16:43:48.241057 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2284 16:43:48.247991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2285 16:43:48.250956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2286 16:43:48.257572 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2287 16:43:48.261260 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2288 16:43:48.264322 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2289 16:43:48.267887 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2290 16:43:48.274442 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2291 16:43:48.278024 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2292 16:43:48.281056 ===================================
2293 16:43:48.284119 LPDDR4 DRAM CONFIGURATION
2294 16:43:48.287754 ===================================
2295 16:43:48.287849 EX_ROW_EN[0] = 0x0
2296 16:43:48.290795 EX_ROW_EN[1] = 0x0
2297 16:43:48.290876 LP4Y_EN = 0x0
2298 16:43:48.294426 WORK_FSP = 0x0
2299 16:43:48.294503 WL = 0x4
2300 16:43:48.297338 RL = 0x4
2301 16:43:48.297416 BL = 0x2
2302 16:43:48.300936 RPST = 0x0
2303 16:43:48.301017 RD_PRE = 0x0
2304 16:43:48.304514 WR_PRE = 0x1
2305 16:43:48.304593 WR_PST = 0x0
2306 16:43:48.307439 DBI_WR = 0x0
2307 16:43:48.311077 DBI_RD = 0x0
2308 16:43:48.311176 OTF = 0x1
2309 16:43:48.314113 ===================================
2310 16:43:48.317357 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2311 16:43:48.320797 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2312 16:43:48.327598 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2313 16:43:48.330882 ===================================
2314 16:43:48.334250 LPDDR4 DRAM CONFIGURATION
2315 16:43:48.337575 ===================================
2316 16:43:48.337666 EX_ROW_EN[0] = 0x10
2317 16:43:48.340374 EX_ROW_EN[1] = 0x0
2318 16:43:48.340459 LP4Y_EN = 0x0
2319 16:43:48.343825 WORK_FSP = 0x0
2320 16:43:48.343913 WL = 0x4
2321 16:43:48.347249 RL = 0x4
2322 16:43:48.347330 BL = 0x2
2323 16:43:48.350705 RPST = 0x0
2324 16:43:48.350783 RD_PRE = 0x0
2325 16:43:48.353733 WR_PRE = 0x1
2326 16:43:48.353806 WR_PST = 0x0
2327 16:43:48.357310 DBI_WR = 0x0
2328 16:43:48.360489 DBI_RD = 0x0
2329 16:43:48.360576 OTF = 0x1
2330 16:43:48.364108 ===================================
2331 16:43:48.370681 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2332 16:43:48.370802 ==
2333 16:43:48.373713 Dram Type= 6, Freq= 0, CH_0, rank 0
2334 16:43:48.377389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2335 16:43:48.377479 ==
2336 16:43:48.380391 [Duty_Offset_Calibration]
2337 16:43:48.380473 B0:1 B1:-1 CA:0
2338 16:43:48.380536
2339 16:43:48.383960 [DutyScan_Calibration_Flow] k_type=0
2340 16:43:48.394420
2341 16:43:48.394544 ==CLK 0==
2342 16:43:48.398054 Final CLK duty delay cell = 0
2343 16:43:48.401565 [0] MAX Duty = 5125%(X100), DQS PI = 24
2344 16:43:48.404618 [0] MIN Duty = 4907%(X100), DQS PI = 8
2345 16:43:48.404706 [0] AVG Duty = 5016%(X100)
2346 16:43:48.408161
2347 16:43:48.411014 CH0 CLK Duty spec in!! Max-Min= 218%
2348 16:43:48.414746 [DutyScan_Calibration_Flow] ====Done====
2349 16:43:48.414835
2350 16:43:48.417680 [DutyScan_Calibration_Flow] k_type=1
2351 16:43:48.432294
2352 16:43:48.432441 ==DQS 0 ==
2353 16:43:48.435761 Final DQS duty delay cell = -4
2354 16:43:48.439124 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2355 16:43:48.442446 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2356 16:43:48.445439 [-4] AVG Duty = 4968%(X100)
2357 16:43:48.445527
2358 16:43:48.445591 ==DQS 1 ==
2359 16:43:48.449252 Final DQS duty delay cell = -4
2360 16:43:48.452656 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2361 16:43:48.455486 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2362 16:43:48.459194 [-4] AVG Duty = 4938%(X100)
2363 16:43:48.459276
2364 16:43:48.462287 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2365 16:43:48.462357
2366 16:43:48.465808 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2367 16:43:48.468729 [DutyScan_Calibration_Flow] ====Done====
2368 16:43:48.468808
2369 16:43:48.472392 [DutyScan_Calibration_Flow] k_type=3
2370 16:43:48.490436
2371 16:43:48.490585 ==DQM 0 ==
2372 16:43:48.493468 Final DQM duty delay cell = 0
2373 16:43:48.497109 [0] MAX Duty = 5062%(X100), DQS PI = 18
2374 16:43:48.500135 [0] MIN Duty = 4875%(X100), DQS PI = 8
2375 16:43:48.503702 [0] AVG Duty = 4968%(X100)
2376 16:43:48.503792
2377 16:43:48.503856 ==DQM 1 ==
2378 16:43:48.506781 Final DQM duty delay cell = 4
2379 16:43:48.510260 [4] MAX Duty = 5187%(X100), DQS PI = 32
2380 16:43:48.513170 [4] MIN Duty = 5000%(X100), DQS PI = 22
2381 16:43:48.516757 [4] AVG Duty = 5093%(X100)
2382 16:43:48.516852
2383 16:43:48.520335 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2384 16:43:48.520422
2385 16:43:48.523288 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2386 16:43:48.526824 [DutyScan_Calibration_Flow] ====Done====
2387 16:43:48.526915
2388 16:43:48.529686 [DutyScan_Calibration_Flow] k_type=2
2389 16:43:48.546135
2390 16:43:48.546296 ==DQ 0 ==
2391 16:43:48.549474 Final DQ duty delay cell = -4
2392 16:43:48.552874 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2393 16:43:48.555707 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2394 16:43:48.559470 [-4] AVG Duty = 4953%(X100)
2395 16:43:48.559567
2396 16:43:48.559633 ==DQ 1 ==
2397 16:43:48.562518 Final DQ duty delay cell = 0
2398 16:43:48.566192 [0] MAX Duty = 5093%(X100), DQS PI = 4
2399 16:43:48.569221 [0] MIN Duty = 4969%(X100), DQS PI = 38
2400 16:43:48.572786 [0] AVG Duty = 5031%(X100)
2401 16:43:48.572874
2402 16:43:48.575638 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2403 16:43:48.575758
2404 16:43:48.579301 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2405 16:43:48.582334 [DutyScan_Calibration_Flow] ====Done====
2406 16:43:48.582422 ==
2407 16:43:48.585958 Dram Type= 6, Freq= 0, CH_1, rank 0
2408 16:43:48.588921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2409 16:43:48.589014 ==
2410 16:43:48.592523 [Duty_Offset_Calibration]
2411 16:43:48.592610 B0:-1 B1:1 CA:2
2412 16:43:48.592675
2413 16:43:48.595486 [DutyScan_Calibration_Flow] k_type=0
2414 16:43:48.606190
2415 16:43:48.606320 ==CLK 0==
2416 16:43:48.609813 Final CLK duty delay cell = 0
2417 16:43:48.612763 [0] MAX Duty = 5156%(X100), DQS PI = 22
2418 16:43:48.616340 [0] MIN Duty = 4969%(X100), DQS PI = 62
2419 16:43:48.616440 [0] AVG Duty = 5062%(X100)
2420 16:43:48.619764
2421 16:43:48.622699 CH1 CLK Duty spec in!! Max-Min= 187%
2422 16:43:48.626160 [DutyScan_Calibration_Flow] ====Done====
2423 16:43:48.626270
2424 16:43:48.629180 [DutyScan_Calibration_Flow] k_type=1
2425 16:43:48.645729
2426 16:43:48.645879 ==DQS 0 ==
2427 16:43:48.648721 Final DQS duty delay cell = 0
2428 16:43:48.652534 [0] MAX Duty = 5156%(X100), DQS PI = 48
2429 16:43:48.655389 [0] MIN Duty = 4938%(X100), DQS PI = 6
2430 16:43:48.655479 [0] AVG Duty = 5047%(X100)
2431 16:43:48.658803
2432 16:43:48.658891 ==DQS 1 ==
2433 16:43:48.662323 Final DQS duty delay cell = 0
2434 16:43:48.665678 [0] MAX Duty = 5062%(X100), DQS PI = 10
2435 16:43:48.668575 [0] MIN Duty = 4969%(X100), DQS PI = 56
2436 16:43:48.672242 [0] AVG Duty = 5015%(X100)
2437 16:43:48.672335
2438 16:43:48.675177 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2439 16:43:48.675254
2440 16:43:48.678811 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2441 16:43:48.681835 [DutyScan_Calibration_Flow] ====Done====
2442 16:43:48.681944
2443 16:43:48.685617 [DutyScan_Calibration_Flow] k_type=3
2444 16:43:48.701433
2445 16:43:48.701606 ==DQM 0 ==
2446 16:43:48.704227 Final DQM duty delay cell = -4
2447 16:43:48.707962 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2448 16:43:48.710873 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2449 16:43:48.714429 [-4] AVG Duty = 4969%(X100)
2450 16:43:48.714544
2451 16:43:48.714638 ==DQM 1 ==
2452 16:43:48.717400 Final DQM duty delay cell = 0
2453 16:43:48.720830 [0] MAX Duty = 5187%(X100), DQS PI = 4
2454 16:43:48.724310 [0] MIN Duty = 5000%(X100), DQS PI = 30
2455 16:43:48.727743 [0] AVG Duty = 5093%(X100)
2456 16:43:48.727841
2457 16:43:48.730786 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2458 16:43:48.730872
2459 16:43:48.733839 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2460 16:43:48.737494 [DutyScan_Calibration_Flow] ====Done====
2461 16:43:48.737584
2462 16:43:48.740333 [DutyScan_Calibration_Flow] k_type=2
2463 16:43:48.757733
2464 16:43:48.757882 ==DQ 0 ==
2465 16:43:48.761076 Final DQ duty delay cell = 0
2466 16:43:48.764664 [0] MAX Duty = 5187%(X100), DQS PI = 30
2467 16:43:48.767974 [0] MIN Duty = 4907%(X100), DQS PI = 6
2468 16:43:48.768069 [0] AVG Duty = 5047%(X100)
2469 16:43:48.768136
2470 16:43:48.771401 ==DQ 1 ==
2471 16:43:48.774323 Final DQ duty delay cell = 0
2472 16:43:48.777916 [0] MAX Duty = 5124%(X100), DQS PI = 10
2473 16:43:48.781002 [0] MIN Duty = 4969%(X100), DQS PI = 0
2474 16:43:48.781095 [0] AVG Duty = 5046%(X100)
2475 16:43:48.781164
2476 16:43:48.784573 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2477 16:43:48.787656
2478 16:43:48.791267 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2479 16:43:48.794242 [DutyScan_Calibration_Flow] ====Done====
2480 16:43:48.797811 nWR fixed to 30
2481 16:43:48.797911 [ModeRegInit_LP4] CH0 RK0
2482 16:43:48.800728 [ModeRegInit_LP4] CH0 RK1
2483 16:43:48.804330 [ModeRegInit_LP4] CH1 RK0
2484 16:43:48.804422 [ModeRegInit_LP4] CH1 RK1
2485 16:43:48.807312 match AC timing 7
2486 16:43:48.810942 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2487 16:43:48.817625 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2488 16:43:48.820654 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2489 16:43:48.827691 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2490 16:43:48.830606 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2491 16:43:48.830705 ==
2492 16:43:48.834239 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 16:43:48.837381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 16:43:48.837473 ==
2495 16:43:48.843992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 16:43:48.850695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2497 16:43:48.857386 [CA 0] Center 39 (9~70) winsize 62
2498 16:43:48.860990 [CA 1] Center 39 (9~70) winsize 62
2499 16:43:48.864206 [CA 2] Center 35 (5~66) winsize 62
2500 16:43:48.867643 [CA 3] Center 35 (5~65) winsize 61
2501 16:43:48.870939 [CA 4] Center 33 (3~64) winsize 62
2502 16:43:48.874375 [CA 5] Center 33 (4~63) winsize 60
2503 16:43:48.874471
2504 16:43:48.877650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2505 16:43:48.877735
2506 16:43:48.880997 [CATrainingPosCal] consider 1 rank data
2507 16:43:48.884009 u2DelayCellTimex100 = 270/100 ps
2508 16:43:48.887775 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2509 16:43:48.890697 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2510 16:43:48.897345 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2511 16:43:48.901079 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2512 16:43:48.904157 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2513 16:43:48.907789 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2514 16:43:48.907886
2515 16:43:48.910811 CA PerBit enable=1, Macro0, CA PI delay=33
2516 16:43:48.910898
2517 16:43:48.914426 [CBTSetCACLKResult] CA Dly = 33
2518 16:43:48.914520 CS Dly: 8 (0~39)
2519 16:43:48.917502 ==
2520 16:43:48.917590 Dram Type= 6, Freq= 0, CH_0, rank 1
2521 16:43:48.924162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 16:43:48.924268 ==
2523 16:43:48.927716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 16:43:48.933926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2525 16:43:48.943514 [CA 0] Center 39 (8~70) winsize 63
2526 16:43:48.946938 [CA 1] Center 39 (9~70) winsize 62
2527 16:43:48.949880 [CA 2] Center 35 (5~66) winsize 62
2528 16:43:48.953424 [CA 3] Center 34 (4~65) winsize 62
2529 16:43:48.956892 [CA 4] Center 33 (3~64) winsize 62
2530 16:43:48.960218 [CA 5] Center 33 (3~63) winsize 61
2531 16:43:48.960318
2532 16:43:48.963658 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2533 16:43:48.963745
2534 16:43:48.966685 [CATrainingPosCal] consider 2 rank data
2535 16:43:48.970068 u2DelayCellTimex100 = 270/100 ps
2536 16:43:48.973494 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2537 16:43:48.979818 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2538 16:43:48.983033 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 16:43:48.986494 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2540 16:43:48.990158 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2541 16:43:48.993134 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2542 16:43:48.993258
2543 16:43:48.996661 CA PerBit enable=1, Macro0, CA PI delay=33
2544 16:43:48.996754
2545 16:43:48.999725 [CBTSetCACLKResult] CA Dly = 33
2546 16:43:48.999815 CS Dly: 8 (0~40)
2547 16:43:49.003294
2548 16:43:49.006242 ----->DramcWriteLeveling(PI) begin...
2549 16:43:49.006336 ==
2550 16:43:49.009867 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 16:43:49.012773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 16:43:49.012869 ==
2553 16:43:49.016417 Write leveling (Byte 0): 33 => 33
2554 16:43:49.019554 Write leveling (Byte 1): 29 => 29
2555 16:43:49.023179 DramcWriteLeveling(PI) end<-----
2556 16:43:49.023288
2557 16:43:49.023376 ==
2558 16:43:49.026084 Dram Type= 6, Freq= 0, CH_0, rank 0
2559 16:43:49.029257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 16:43:49.029357 ==
2561 16:43:49.032739 [Gating] SW mode calibration
2562 16:43:49.039149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2563 16:43:49.045856 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2564 16:43:49.049337 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2565 16:43:49.052391 0 15 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2566 16:43:49.059452 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 16:43:49.062400 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 16:43:49.065761 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 16:43:49.072418 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 16:43:49.075809 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 16:43:49.079305 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
2572 16:43:49.085995 1 0 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
2573 16:43:49.088771 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 16:43:49.092090 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 16:43:49.099327 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 16:43:49.102281 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 16:43:49.105894 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 16:43:49.112518 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 16:43:49.115618 1 0 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
2580 16:43:49.119189 1 1 0 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2581 16:43:49.122231 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2582 16:43:49.128901 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 16:43:49.132412 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 16:43:49.135375 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 16:43:49.142407 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 16:43:49.145486 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2587 16:43:49.149075 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2588 16:43:49.155814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2589 16:43:49.158771 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2590 16:43:49.162392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 16:43:49.168762 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 16:43:49.172196 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 16:43:49.175564 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 16:43:49.181863 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 16:43:49.185347 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 16:43:49.188652 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 16:43:49.195241 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 16:43:49.198578 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 16:43:49.201975 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 16:43:49.208683 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 16:43:49.211685 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 16:43:49.215337 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 16:43:49.221979 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2604 16:43:49.225090 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2605 16:43:49.228104 Total UI for P1: 0, mck2ui 16
2606 16:43:49.231820 best dqsien dly found for B0: ( 1, 3, 28)
2607 16:43:49.235307 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2608 16:43:49.241828 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 16:43:49.241990 Total UI for P1: 0, mck2ui 16
2610 16:43:49.248290 best dqsien dly found for B1: ( 1, 4, 2)
2611 16:43:49.251811 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2612 16:43:49.254821 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2613 16:43:49.254939
2614 16:43:49.258365 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2615 16:43:49.261369 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2616 16:43:49.264955 [Gating] SW calibration Done
2617 16:43:49.265073 ==
2618 16:43:49.267933 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 16:43:49.271582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 16:43:49.271698 ==
2621 16:43:49.274983 RX Vref Scan: 0
2622 16:43:49.275146
2623 16:43:49.275243 RX Vref 0 -> 0, step: 1
2624 16:43:49.275332
2625 16:43:49.277929 RX Delay -40 -> 252, step: 8
2626 16:43:49.281181 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2627 16:43:49.288083 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2628 16:43:49.291006 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2629 16:43:49.294775 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2630 16:43:49.298047 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2631 16:43:49.301405 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2632 16:43:49.308074 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2633 16:43:49.311088 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2634 16:43:49.314762 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2635 16:43:49.317770 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2636 16:43:49.320875 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2637 16:43:49.327627 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2638 16:43:49.331239 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2639 16:43:49.334297 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2640 16:43:49.337746 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2641 16:43:49.340725 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2642 16:43:49.344246 ==
2643 16:43:49.347749 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 16:43:49.350636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 16:43:49.350752 ==
2646 16:43:49.350844 DQS Delay:
2647 16:43:49.354204 DQS0 = 0, DQS1 = 0
2648 16:43:49.354287 DQM Delay:
2649 16:43:49.357752 DQM0 = 119, DQM1 = 107
2650 16:43:49.357854 DQ Delay:
2651 16:43:49.361293 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2652 16:43:49.364285 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2653 16:43:49.367996 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2654 16:43:49.370938 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2655 16:43:49.371080
2656 16:43:49.371188
2657 16:43:49.371277 ==
2658 16:43:49.374577 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 16:43:49.380679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 16:43:49.380800 ==
2661 16:43:49.380893
2662 16:43:49.380985
2663 16:43:49.381081 TX Vref Scan disable
2664 16:43:49.383893 == TX Byte 0 ==
2665 16:43:49.387391 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2666 16:43:49.393886 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2667 16:43:49.394026 == TX Byte 1 ==
2668 16:43:49.397341 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2669 16:43:49.403989 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2670 16:43:49.404137 ==
2671 16:43:49.407328 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 16:43:49.410637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 16:43:49.410727 ==
2674 16:43:49.422447 TX Vref=22, minBit 1, minWin=26, winSum=423
2675 16:43:49.426103 TX Vref=24, minBit 1, minWin=25, winSum=425
2676 16:43:49.429095 TX Vref=26, minBit 4, minWin=26, winSum=432
2677 16:43:49.432588 TX Vref=28, minBit 10, minWin=26, winSum=432
2678 16:43:49.435638 TX Vref=30, minBit 4, minWin=26, winSum=433
2679 16:43:49.439319 TX Vref=32, minBit 4, minWin=26, winSum=427
2680 16:43:49.445734 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 30
2681 16:43:49.445854
2682 16:43:49.448739 Final TX Range 1 Vref 30
2683 16:43:49.448834
2684 16:43:49.448917 ==
2685 16:43:49.452326 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 16:43:49.455815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 16:43:49.455909 ==
2688 16:43:49.455995
2689 16:43:49.459252
2690 16:43:49.459338 TX Vref Scan disable
2691 16:43:49.462270 == TX Byte 0 ==
2692 16:43:49.465848 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2693 16:43:49.468883 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2694 16:43:49.472526 == TX Byte 1 ==
2695 16:43:49.475616 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2696 16:43:49.479208 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2697 16:43:49.479327
2698 16:43:49.482234 [DATLAT]
2699 16:43:49.482323 Freq=1200, CH0 RK0
2700 16:43:49.482405
2701 16:43:49.485602 DATLAT Default: 0xd
2702 16:43:49.485741 0, 0xFFFF, sum = 0
2703 16:43:49.488977 1, 0xFFFF, sum = 0
2704 16:43:49.489093 2, 0xFFFF, sum = 0
2705 16:43:49.492087 3, 0xFFFF, sum = 0
2706 16:43:49.492185 4, 0xFFFF, sum = 0
2707 16:43:49.495788 5, 0xFFFF, sum = 0
2708 16:43:49.495899 6, 0xFFFF, sum = 0
2709 16:43:49.498997 7, 0xFFFF, sum = 0
2710 16:43:49.502416 8, 0xFFFF, sum = 0
2711 16:43:49.502520 9, 0xFFFF, sum = 0
2712 16:43:49.505275 10, 0xFFFF, sum = 0
2713 16:43:49.505415 11, 0xFFFF, sum = 0
2714 16:43:49.509072 12, 0x0, sum = 1
2715 16:43:49.509163 13, 0x0, sum = 2
2716 16:43:49.512546 14, 0x0, sum = 3
2717 16:43:49.512642 15, 0x0, sum = 4
2718 16:43:49.512728 best_step = 13
2719 16:43:49.512804
2720 16:43:49.515571 ==
2721 16:43:49.518788 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 16:43:49.521980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 16:43:49.522112 ==
2724 16:43:49.522211 RX Vref Scan: 1
2725 16:43:49.522315
2726 16:43:49.525634 Set Vref Range= 32 -> 127
2727 16:43:49.525744
2728 16:43:49.528657 RX Vref 32 -> 127, step: 1
2729 16:43:49.528739
2730 16:43:49.532183 RX Delay -21 -> 252, step: 4
2731 16:43:49.532268
2732 16:43:49.535215 Set Vref, RX VrefLevel [Byte0]: 32
2733 16:43:49.538782 [Byte1]: 32
2734 16:43:49.538898
2735 16:43:49.541802 Set Vref, RX VrefLevel [Byte0]: 33
2736 16:43:49.545492 [Byte1]: 33
2737 16:43:49.548944
2738 16:43:49.549033 Set Vref, RX VrefLevel [Byte0]: 34
2739 16:43:49.551999 [Byte1]: 34
2740 16:43:49.556731
2741 16:43:49.556831 Set Vref, RX VrefLevel [Byte0]: 35
2742 16:43:49.559649 [Byte1]: 35
2743 16:43:49.564267
2744 16:43:49.564387 Set Vref, RX VrefLevel [Byte0]: 36
2745 16:43:49.567828 [Byte1]: 36
2746 16:43:49.572566
2747 16:43:49.572650 Set Vref, RX VrefLevel [Byte0]: 37
2748 16:43:49.575662 [Byte1]: 37
2749 16:43:49.579958
2750 16:43:49.580082 Set Vref, RX VrefLevel [Byte0]: 38
2751 16:43:49.583585 [Byte1]: 38
2752 16:43:49.588388
2753 16:43:49.588484 Set Vref, RX VrefLevel [Byte0]: 39
2754 16:43:49.591423 [Byte1]: 39
2755 16:43:49.596088
2756 16:43:49.596199 Set Vref, RX VrefLevel [Byte0]: 40
2757 16:43:49.599519 [Byte1]: 40
2758 16:43:49.604147
2759 16:43:49.604250 Set Vref, RX VrefLevel [Byte0]: 41
2760 16:43:49.607415 [Byte1]: 41
2761 16:43:49.611942
2762 16:43:49.612050 Set Vref, RX VrefLevel [Byte0]: 42
2763 16:43:49.615350 [Byte1]: 42
2764 16:43:49.619679
2765 16:43:49.619820 Set Vref, RX VrefLevel [Byte0]: 43
2766 16:43:49.623081 [Byte1]: 43
2767 16:43:49.628005
2768 16:43:49.628120 Set Vref, RX VrefLevel [Byte0]: 44
2769 16:43:49.630878 [Byte1]: 44
2770 16:43:49.635798
2771 16:43:49.635908 Set Vref, RX VrefLevel [Byte0]: 45
2772 16:43:49.638825 [Byte1]: 45
2773 16:43:49.643589
2774 16:43:49.643744 Set Vref, RX VrefLevel [Byte0]: 46
2775 16:43:49.647201 [Byte1]: 46
2776 16:43:49.651345
2777 16:43:49.651533 Set Vref, RX VrefLevel [Byte0]: 47
2778 16:43:49.655035 [Byte1]: 47
2779 16:43:49.659776
2780 16:43:49.659885 Set Vref, RX VrefLevel [Byte0]: 48
2781 16:43:49.666193 [Byte1]: 48
2782 16:43:49.666304
2783 16:43:49.669113 Set Vref, RX VrefLevel [Byte0]: 49
2784 16:43:49.672689 [Byte1]: 49
2785 16:43:49.672784
2786 16:43:49.675703 Set Vref, RX VrefLevel [Byte0]: 50
2787 16:43:49.679211 [Byte1]: 50
2788 16:43:49.683628
2789 16:43:49.683724 Set Vref, RX VrefLevel [Byte0]: 51
2790 16:43:49.686542 [Byte1]: 51
2791 16:43:49.691305
2792 16:43:49.691419 Set Vref, RX VrefLevel [Byte0]: 52
2793 16:43:49.694220 [Byte1]: 52
2794 16:43:49.699040
2795 16:43:49.699189 Set Vref, RX VrefLevel [Byte0]: 53
2796 16:43:49.702737 [Byte1]: 53
2797 16:43:49.707500
2798 16:43:49.707625 Set Vref, RX VrefLevel [Byte0]: 54
2799 16:43:49.710308 [Byte1]: 54
2800 16:43:49.715204
2801 16:43:49.715314 Set Vref, RX VrefLevel [Byte0]: 55
2802 16:43:49.718116 [Byte1]: 55
2803 16:43:49.722987
2804 16:43:49.723140 Set Vref, RX VrefLevel [Byte0]: 56
2805 16:43:49.726261 [Byte1]: 56
2806 16:43:49.730762
2807 16:43:49.730894 Set Vref, RX VrefLevel [Byte0]: 57
2808 16:43:49.734377 [Byte1]: 57
2809 16:43:49.738802
2810 16:43:49.738930 Set Vref, RX VrefLevel [Byte0]: 58
2811 16:43:49.742441 [Byte1]: 58
2812 16:43:49.746592
2813 16:43:49.746689 Set Vref, RX VrefLevel [Byte0]: 59
2814 16:43:49.750244 [Byte1]: 59
2815 16:43:49.754575
2816 16:43:49.754667 Set Vref, RX VrefLevel [Byte0]: 60
2817 16:43:49.757989 [Byte1]: 60
2818 16:43:49.762825
2819 16:43:49.762933 Set Vref, RX VrefLevel [Byte0]: 61
2820 16:43:49.765696 [Byte1]: 61
2821 16:43:49.770319
2822 16:43:49.770423 Set Vref, RX VrefLevel [Byte0]: 62
2823 16:43:49.773996 [Byte1]: 62
2824 16:43:49.778270
2825 16:43:49.778358 Set Vref, RX VrefLevel [Byte0]: 63
2826 16:43:49.781846 [Byte1]: 63
2827 16:43:49.786180
2828 16:43:49.786270 Set Vref, RX VrefLevel [Byte0]: 64
2829 16:43:49.789851 [Byte1]: 64
2830 16:43:49.794609
2831 16:43:49.794737 Set Vref, RX VrefLevel [Byte0]: 65
2832 16:43:49.797630 [Byte1]: 65
2833 16:43:49.802334
2834 16:43:49.802435 Set Vref, RX VrefLevel [Byte0]: 66
2835 16:43:49.805241 [Byte1]: 66
2836 16:43:49.810022
2837 16:43:49.810112 Set Vref, RX VrefLevel [Byte0]: 67
2838 16:43:49.813603 [Byte1]: 67
2839 16:43:49.818271
2840 16:43:49.818367 Set Vref, RX VrefLevel [Byte0]: 68
2841 16:43:49.821526 [Byte1]: 68
2842 16:43:49.825896
2843 16:43:49.826027 Set Vref, RX VrefLevel [Byte0]: 69
2844 16:43:49.829310 [Byte1]: 69
2845 16:43:49.833801
2846 16:43:49.833925 Set Vref, RX VrefLevel [Byte0]: 70
2847 16:43:49.837005 [Byte1]: 70
2848 16:43:49.841991
2849 16:43:49.842117 Set Vref, RX VrefLevel [Byte0]: 71
2850 16:43:49.845313 [Byte1]: 71
2851 16:43:49.850075
2852 16:43:49.850187 Set Vref, RX VrefLevel [Byte0]: 72
2853 16:43:49.852977 [Byte1]: 72
2854 16:43:49.857804
2855 16:43:49.857923 Set Vref, RX VrefLevel [Byte0]: 73
2856 16:43:49.864271 [Byte1]: 73
2857 16:43:49.864377
2858 16:43:49.867330 Set Vref, RX VrefLevel [Byte0]: 74
2859 16:43:49.870719 [Byte1]: 74
2860 16:43:49.870823
2861 16:43:49.874293 Set Vref, RX VrefLevel [Byte0]: 75
2862 16:43:49.877350 [Byte1]: 75
2863 16:43:49.881637
2864 16:43:49.881726 Set Vref, RX VrefLevel [Byte0]: 76
2865 16:43:49.884687 [Byte1]: 76
2866 16:43:49.889433
2867 16:43:49.889528 Set Vref, RX VrefLevel [Byte0]: 77
2868 16:43:49.892569 [Byte1]: 77
2869 16:43:49.897420
2870 16:43:49.897521 Final RX Vref Byte 0 = 59 to rank0
2871 16:43:49.900496 Final RX Vref Byte 1 = 49 to rank0
2872 16:43:49.904614 Final RX Vref Byte 0 = 59 to rank1
2873 16:43:49.906960 Final RX Vref Byte 1 = 49 to rank1==
2874 16:43:49.910606 Dram Type= 6, Freq= 0, CH_0, rank 0
2875 16:43:49.917330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 16:43:49.917441 ==
2877 16:43:49.917565 DQS Delay:
2878 16:43:49.917684 DQS0 = 0, DQS1 = 0
2879 16:43:49.920526 DQM Delay:
2880 16:43:49.920603 DQM0 = 119, DQM1 = 106
2881 16:43:49.923922 DQ Delay:
2882 16:43:49.927422 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2883 16:43:49.930785 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =126
2884 16:43:49.933693 DQ8 =98, DQ9 =92, DQ10 =110, DQ11 =100
2885 16:43:49.937043 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2886 16:43:49.937154
2887 16:43:49.937240
2888 16:43:49.946909 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2889 16:43:49.947031 CH0 RK0: MR19=403, MR18=11FC
2890 16:43:49.953633 CH0_RK0: MR19=0x403, MR18=0x11FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2891 16:43:49.953767
2892 16:43:49.956881 ----->DramcWriteLeveling(PI) begin...
2893 16:43:49.956992 ==
2894 16:43:49.960353 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 16:43:49.966741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 16:43:49.966885 ==
2897 16:43:49.970297 Write leveling (Byte 0): 35 => 35
2898 16:43:49.970394 Write leveling (Byte 1): 29 => 29
2899 16:43:49.973272 DramcWriteLeveling(PI) end<-----
2900 16:43:49.973356
2901 16:43:49.973445 ==
2902 16:43:49.976719 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 16:43:49.983418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 16:43:49.983532 ==
2905 16:43:49.987021 [Gating] SW mode calibration
2906 16:43:49.993046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2907 16:43:49.996739 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2908 16:43:50.003446 0 15 0 | B1->B0 | 2525 3333 | 1 1 | (0 0) (0 0)
2909 16:43:50.006513 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
2910 16:43:50.010101 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 16:43:50.016572 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 16:43:50.019671 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 16:43:50.023251 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 16:43:50.029874 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2915 16:43:50.033416 0 15 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
2916 16:43:50.036581 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2917 16:43:50.042976 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 16:43:50.046305 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 16:43:50.049741 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 16:43:50.056425 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 16:43:50.059819 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 16:43:50.062938 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 16:43:50.066557 1 0 28 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
2924 16:43:50.073401 1 1 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
2925 16:43:50.076226 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 16:43:50.079779 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 16:43:50.086231 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 16:43:50.089818 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 16:43:50.092847 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 16:43:50.099466 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2931 16:43:50.103037 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2932 16:43:50.106080 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2933 16:43:50.112715 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 16:43:50.116202 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 16:43:50.119248 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 16:43:50.126449 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 16:43:50.129403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 16:43:50.132900 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 16:43:50.139323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 16:43:50.142937 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 16:43:50.145941 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 16:43:50.152685 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 16:43:50.156116 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 16:43:50.159490 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 16:43:50.165985 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 16:43:50.169447 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 16:43:50.172266 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2948 16:43:50.179213 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2949 16:43:50.182422 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 16:43:50.185967 Total UI for P1: 0, mck2ui 16
2951 16:43:50.189020 best dqsien dly found for B0: ( 1, 3, 30)
2952 16:43:50.192727 Total UI for P1: 0, mck2ui 16
2953 16:43:50.195664 best dqsien dly found for B1: ( 1, 3, 30)
2954 16:43:50.199247 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2955 16:43:50.202256 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2956 16:43:50.202353
2957 16:43:50.205810 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2958 16:43:50.209454 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2959 16:43:50.212408 [Gating] SW calibration Done
2960 16:43:50.212502 ==
2961 16:43:50.216010 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 16:43:50.219003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 16:43:50.219138 ==
2964 16:43:50.222456 RX Vref Scan: 0
2965 16:43:50.222549
2966 16:43:50.225431 RX Vref 0 -> 0, step: 1
2967 16:43:50.225520
2968 16:43:50.225587 RX Delay -40 -> 252, step: 8
2969 16:43:50.232630 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2970 16:43:50.235637 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2971 16:43:50.239311 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2972 16:43:50.242192 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2973 16:43:50.245896 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2974 16:43:50.252460 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2975 16:43:50.255347 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2976 16:43:50.258701 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2977 16:43:50.262088 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2978 16:43:50.265721 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2979 16:43:50.272050 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2980 16:43:50.275522 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2981 16:43:50.278762 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2982 16:43:50.282228 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2983 16:43:50.288590 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2984 16:43:50.292303 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2985 16:43:50.292406 ==
2986 16:43:50.295440 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 16:43:50.298369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 16:43:50.298465 ==
2989 16:43:50.298559 DQS Delay:
2990 16:43:50.302037 DQS0 = 0, DQS1 = 0
2991 16:43:50.302122 DQM Delay:
2992 16:43:50.305536 DQM0 = 117, DQM1 = 108
2993 16:43:50.305618 DQ Delay:
2994 16:43:50.308543 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2995 16:43:50.311642 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2996 16:43:50.315227 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2997 16:43:50.318278 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2998 16:43:50.321880
2999 16:43:50.321970
3000 16:43:50.322061 ==
3001 16:43:50.324789 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 16:43:50.328460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 16:43:50.328577 ==
3004 16:43:50.328662
3005 16:43:50.328762
3006 16:43:50.331447 TX Vref Scan disable
3007 16:43:50.331527 == TX Byte 0 ==
3008 16:43:50.338525 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3009 16:43:50.341486 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3010 16:43:50.341585 == TX Byte 1 ==
3011 16:43:50.348351 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3012 16:43:50.351346 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3013 16:43:50.351449 ==
3014 16:43:50.354990 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 16:43:50.357959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 16:43:50.358057 ==
3017 16:43:50.371077 TX Vref=22, minBit 5, minWin=25, winSum=413
3018 16:43:50.374528 TX Vref=24, minBit 10, minWin=25, winSum=420
3019 16:43:50.377801 TX Vref=26, minBit 0, minWin=26, winSum=423
3020 16:43:50.381248 TX Vref=28, minBit 10, minWin=25, winSum=425
3021 16:43:50.384434 TX Vref=30, minBit 13, minWin=25, winSum=427
3022 16:43:50.390982 TX Vref=32, minBit 13, minWin=25, winSum=424
3023 16:43:50.394569 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 26
3024 16:43:50.394676
3025 16:43:50.397828 Final TX Range 1 Vref 26
3026 16:43:50.397949
3027 16:43:50.398056 ==
3028 16:43:50.401484 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 16:43:50.404316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 16:43:50.407938 ==
3031 16:43:50.408032
3032 16:43:50.408117
3033 16:43:50.408194 TX Vref Scan disable
3034 16:43:50.411594 == TX Byte 0 ==
3035 16:43:50.414676 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3036 16:43:50.421249 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3037 16:43:50.421358 == TX Byte 1 ==
3038 16:43:50.424817 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3039 16:43:50.431243 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3040 16:43:50.431364
3041 16:43:50.431461 [DATLAT]
3042 16:43:50.431541 Freq=1200, CH0 RK1
3043 16:43:50.431647
3044 16:43:50.434837 DATLAT Default: 0xd
3045 16:43:50.434948 0, 0xFFFF, sum = 0
3046 16:43:50.437782 1, 0xFFFF, sum = 0
3047 16:43:50.441313 2, 0xFFFF, sum = 0
3048 16:43:50.441400 3, 0xFFFF, sum = 0
3049 16:43:50.444342 4, 0xFFFF, sum = 0
3050 16:43:50.444451 5, 0xFFFF, sum = 0
3051 16:43:50.447719 6, 0xFFFF, sum = 0
3052 16:43:50.447812 7, 0xFFFF, sum = 0
3053 16:43:50.451365 8, 0xFFFF, sum = 0
3054 16:43:50.451459 9, 0xFFFF, sum = 0
3055 16:43:50.454520 10, 0xFFFF, sum = 0
3056 16:43:50.454630 11, 0xFFFF, sum = 0
3057 16:43:50.457625 12, 0x0, sum = 1
3058 16:43:50.457711 13, 0x0, sum = 2
3059 16:43:50.461149 14, 0x0, sum = 3
3060 16:43:50.461228 15, 0x0, sum = 4
3061 16:43:50.464240 best_step = 13
3062 16:43:50.464319
3063 16:43:50.464407 ==
3064 16:43:50.467787 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 16:43:50.470768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 16:43:50.470863 ==
3067 16:43:50.470955 RX Vref Scan: 0
3068 16:43:50.471048
3069 16:43:50.474359 RX Vref 0 -> 0, step: 1
3070 16:43:50.474435
3071 16:43:50.477679 RX Delay -21 -> 252, step: 4
3072 16:43:50.484362 iDelay=199, Bit 0, Center 114 (51 ~ 178) 128
3073 16:43:50.487668 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3074 16:43:50.490915 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3075 16:43:50.494368 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3076 16:43:50.497732 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3077 16:43:50.501257 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3078 16:43:50.507774 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3079 16:43:50.510800 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3080 16:43:50.514291 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3081 16:43:50.517241 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3082 16:43:50.520920 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3083 16:43:50.527679 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3084 16:43:50.530718 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3085 16:43:50.534163 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3086 16:43:50.537699 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3087 16:43:50.544382 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3088 16:43:50.544498 ==
3089 16:43:50.547419 Dram Type= 6, Freq= 0, CH_0, rank 1
3090 16:43:50.550932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 16:43:50.551037 ==
3092 16:43:50.551145 DQS Delay:
3093 16:43:50.553858 DQS0 = 0, DQS1 = 0
3094 16:43:50.553970 DQM Delay:
3095 16:43:50.557535 DQM0 = 116, DQM1 = 107
3096 16:43:50.557616 DQ Delay:
3097 16:43:50.560554 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3098 16:43:50.564246 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3099 16:43:50.567213 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3100 16:43:50.570807 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3101 16:43:50.570890
3102 16:43:50.570987
3103 16:43:50.580470 [DQSOSCAuto] RK1, (LSB)MR18= 0xce6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3104 16:43:50.583771 CH0 RK1: MR19=403, MR18=CE6
3105 16:43:50.587263 CH0_RK1: MR19=0x403, MR18=0xCE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3106 16:43:50.590708 [RxdqsGatingPostProcess] freq 1200
3107 16:43:50.597262 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3108 16:43:50.600476 best DQS0 dly(2T, 0.5T) = (0, 11)
3109 16:43:50.603823 best DQS1 dly(2T, 0.5T) = (0, 12)
3110 16:43:50.607023 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3111 16:43:50.610482 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3112 16:43:50.614170 best DQS0 dly(2T, 0.5T) = (0, 11)
3113 16:43:50.617202 best DQS1 dly(2T, 0.5T) = (0, 11)
3114 16:43:50.620013 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3115 16:43:50.623584 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3116 16:43:50.623682 Pre-setting of DQS Precalculation
3117 16:43:50.630093 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3118 16:43:50.630216 ==
3119 16:43:50.633707 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 16:43:50.636580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 16:43:50.636678 ==
3122 16:43:50.643877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 16:43:50.649807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3124 16:43:50.657915 [CA 0] Center 37 (7~67) winsize 61
3125 16:43:50.660760 [CA 1] Center 37 (7~68) winsize 62
3126 16:43:50.664364 [CA 2] Center 34 (4~64) winsize 61
3127 16:43:50.667348 [CA 3] Center 33 (3~64) winsize 62
3128 16:43:50.670956 [CA 4] Center 34 (4~64) winsize 61
3129 16:43:50.674047 [CA 5] Center 34 (4~64) winsize 61
3130 16:43:50.674141
3131 16:43:50.677153 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3132 16:43:50.677229
3133 16:43:50.680785 [CATrainingPosCal] consider 1 rank data
3134 16:43:50.683735 u2DelayCellTimex100 = 270/100 ps
3135 16:43:50.687266 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3136 16:43:50.693760 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3137 16:43:50.697305 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3138 16:43:50.700243 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3139 16:43:50.704047 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3140 16:43:50.706856 CA5 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 16:43:50.706951
3142 16:43:50.710261 CA PerBit enable=1, Macro0, CA PI delay=33
3143 16:43:50.710344
3144 16:43:50.713568 [CBTSetCACLKResult] CA Dly = 33
3145 16:43:50.717179 CS Dly: 6 (0~37)
3146 16:43:50.717278 ==
3147 16:43:50.720022 Dram Type= 6, Freq= 0, CH_1, rank 1
3148 16:43:50.723405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 16:43:50.723497 ==
3150 16:43:50.730462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3151 16:43:50.733526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3152 16:43:50.743066 [CA 0] Center 37 (7~68) winsize 62
3153 16:43:50.746605 [CA 1] Center 38 (8~68) winsize 61
3154 16:43:50.750143 [CA 2] Center 34 (4~65) winsize 62
3155 16:43:50.753176 [CA 3] Center 33 (3~64) winsize 62
3156 16:43:50.756850 [CA 4] Center 34 (4~65) winsize 62
3157 16:43:50.759821 [CA 5] Center 33 (3~64) winsize 62
3158 16:43:50.759903
3159 16:43:50.762778 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3160 16:43:50.762881
3161 16:43:50.766391 [CATrainingPosCal] consider 2 rank data
3162 16:43:50.769561 u2DelayCellTimex100 = 270/100 ps
3163 16:43:50.773127 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3164 16:43:50.776129 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3165 16:43:50.782853 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3166 16:43:50.786490 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3167 16:43:50.789379 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3168 16:43:50.792856 CA5 delay=34 (4~64),Diff = 1 PI (4 cell)
3169 16:43:50.792951
3170 16:43:50.796362 CA PerBit enable=1, Macro0, CA PI delay=33
3171 16:43:50.796451
3172 16:43:50.799913 [CBTSetCACLKResult] CA Dly = 33
3173 16:43:50.799994 CS Dly: 7 (0~40)
3174 16:43:50.800066
3175 16:43:50.803186 ----->DramcWriteLeveling(PI) begin...
3176 16:43:50.806054 ==
3177 16:43:50.809479 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 16:43:50.812876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 16:43:50.812993 ==
3180 16:43:50.816313 Write leveling (Byte 0): 24 => 24
3181 16:43:50.819657 Write leveling (Byte 1): 27 => 27
3182 16:43:50.823211 DramcWriteLeveling(PI) end<-----
3183 16:43:50.823300
3184 16:43:50.823365 ==
3185 16:43:50.826202 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 16:43:50.829442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 16:43:50.829542 ==
3188 16:43:50.832894 [Gating] SW mode calibration
3189 16:43:50.839593 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3190 16:43:50.845877 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3191 16:43:50.849290 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3192 16:43:50.852924 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 16:43:50.859410 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 16:43:50.862407 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 16:43:50.865882 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 16:43:50.869527 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 16:43:50.876151 0 15 24 | B1->B0 | 3333 2929 | 1 1 | (1 0) (1 0)
3198 16:43:50.879198 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3199 16:43:50.882788 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 16:43:50.889458 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 16:43:50.892544 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 16:43:50.895982 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 16:43:50.902542 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 16:43:50.905870 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 16:43:50.909363 1 0 24 | B1->B0 | 2626 3b3a | 0 1 | (0 0) (0 0)
3206 16:43:50.915588 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 16:43:50.919007 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 16:43:50.922358 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 16:43:50.928676 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 16:43:50.932129 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 16:43:50.935455 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 16:43:50.942432 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 16:43:50.945471 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3214 16:43:50.948936 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3215 16:43:50.955174 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 16:43:50.958758 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 16:43:50.961766 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 16:43:50.968926 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 16:43:50.971907 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 16:43:50.974963 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 16:43:50.981580 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 16:43:50.985214 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 16:43:50.988192 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 16:43:50.994791 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 16:43:50.998260 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 16:43:51.001909 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 16:43:51.008361 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 16:43:51.012010 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 16:43:51.014788 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3230 16:43:51.021666 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3231 16:43:51.025091 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 16:43:51.028801 Total UI for P1: 0, mck2ui 16
3233 16:43:51.031234 best dqsien dly found for B0: ( 1, 3, 26)
3234 16:43:51.034672 Total UI for P1: 0, mck2ui 16
3235 16:43:51.038128 best dqsien dly found for B1: ( 1, 3, 26)
3236 16:43:51.041861 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3237 16:43:51.045133 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3238 16:43:51.045283
3239 16:43:51.048563 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3240 16:43:51.051445 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3241 16:43:51.054887 [Gating] SW calibration Done
3242 16:43:51.055020 ==
3243 16:43:51.058396 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 16:43:51.061410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 16:43:51.061542 ==
3246 16:43:51.065043 RX Vref Scan: 0
3247 16:43:51.065144
3248 16:43:51.068076 RX Vref 0 -> 0, step: 1
3249 16:43:51.068158
3250 16:43:51.068223 RX Delay -40 -> 252, step: 8
3251 16:43:51.074619 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3252 16:43:51.078439 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3253 16:43:51.081484 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3254 16:43:51.084588 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3255 16:43:51.088109 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3256 16:43:51.094675 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3257 16:43:51.098318 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3258 16:43:51.101335 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3259 16:43:51.104903 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3260 16:43:51.107872 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3261 16:43:51.114595 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3262 16:43:51.118140 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3263 16:43:51.121070 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3264 16:43:51.124659 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3265 16:43:51.127580 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3266 16:43:51.134702 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3267 16:43:51.134819 ==
3268 16:43:51.137523 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 16:43:51.141217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 16:43:51.141318 ==
3271 16:43:51.141407 DQS Delay:
3272 16:43:51.144582 DQS0 = 0, DQS1 = 0
3273 16:43:51.144702 DQM Delay:
3274 16:43:51.147960 DQM0 = 117, DQM1 = 108
3275 16:43:51.148057 DQ Delay:
3276 16:43:51.150769 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3277 16:43:51.154307 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3278 16:43:51.157775 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3279 16:43:51.161309 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3280 16:43:51.161418
3281 16:43:51.164307
3282 16:43:51.164417 ==
3283 16:43:51.167872 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 16:43:51.170858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 16:43:51.170970 ==
3286 16:43:51.171073
3287 16:43:51.171142
3288 16:43:51.174500 TX Vref Scan disable
3289 16:43:51.174620 == TX Byte 0 ==
3290 16:43:51.180765 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3291 16:43:51.184405 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3292 16:43:51.184493 == TX Byte 1 ==
3293 16:43:51.191005 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3294 16:43:51.194011 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3295 16:43:51.194126 ==
3296 16:43:51.197544 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 16:43:51.200541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 16:43:51.200652 ==
3299 16:43:51.213175 TX Vref=22, minBit 10, minWin=24, winSum=412
3300 16:43:51.216168 TX Vref=24, minBit 8, minWin=25, winSum=419
3301 16:43:51.219728 TX Vref=26, minBit 9, minWin=25, winSum=428
3302 16:43:51.222731 TX Vref=28, minBit 9, minWin=25, winSum=431
3303 16:43:51.226249 TX Vref=30, minBit 9, minWin=25, winSum=429
3304 16:43:51.233132 TX Vref=32, minBit 9, minWin=25, winSum=425
3305 16:43:51.236420 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 28
3306 16:43:51.236533
3307 16:43:51.239319 Final TX Range 1 Vref 28
3308 16:43:51.239406
3309 16:43:51.239472 ==
3310 16:43:51.242646 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 16:43:51.246208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 16:43:51.246319 ==
3313 16:43:51.249661
3314 16:43:51.249786
3315 16:43:51.249889 TX Vref Scan disable
3316 16:43:51.253283 == TX Byte 0 ==
3317 16:43:51.255970 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3318 16:43:51.259263 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3319 16:43:51.263083 == TX Byte 1 ==
3320 16:43:51.266045 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3321 16:43:51.269701 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3322 16:43:51.272707
3323 16:43:51.272793 [DATLAT]
3324 16:43:51.272859 Freq=1200, CH1 RK0
3325 16:43:51.272922
3326 16:43:51.276269 DATLAT Default: 0xd
3327 16:43:51.276354 0, 0xFFFF, sum = 0
3328 16:43:51.279315 1, 0xFFFF, sum = 0
3329 16:43:51.279399 2, 0xFFFF, sum = 0
3330 16:43:51.282577 3, 0xFFFF, sum = 0
3331 16:43:51.282674 4, 0xFFFF, sum = 0
3332 16:43:51.286125 5, 0xFFFF, sum = 0
3333 16:43:51.289304 6, 0xFFFF, sum = 0
3334 16:43:51.289411 7, 0xFFFF, sum = 0
3335 16:43:51.292958 8, 0xFFFF, sum = 0
3336 16:43:51.293039 9, 0xFFFF, sum = 0
3337 16:43:51.296569 10, 0xFFFF, sum = 0
3338 16:43:51.296645 11, 0xFFFF, sum = 0
3339 16:43:51.299550 12, 0x0, sum = 1
3340 16:43:51.299645 13, 0x0, sum = 2
3341 16:43:51.302689 14, 0x0, sum = 3
3342 16:43:51.302796 15, 0x0, sum = 4
3343 16:43:51.302891 best_step = 13
3344 16:43:51.306278
3345 16:43:51.306360 ==
3346 16:43:51.309195 Dram Type= 6, Freq= 0, CH_1, rank 0
3347 16:43:51.312638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3348 16:43:51.312746 ==
3349 16:43:51.312846 RX Vref Scan: 1
3350 16:43:51.312934
3351 16:43:51.316075 Set Vref Range= 32 -> 127
3352 16:43:51.316180
3353 16:43:51.319209 RX Vref 32 -> 127, step: 1
3354 16:43:51.319289
3355 16:43:51.322831 RX Delay -21 -> 252, step: 4
3356 16:43:51.322939
3357 16:43:51.325838 Set Vref, RX VrefLevel [Byte0]: 32
3358 16:43:51.329425 [Byte1]: 32
3359 16:43:51.329533
3360 16:43:51.332369 Set Vref, RX VrefLevel [Byte0]: 33
3361 16:43:51.335856 [Byte1]: 33
3362 16:43:51.339145
3363 16:43:51.339242 Set Vref, RX VrefLevel [Byte0]: 34
3364 16:43:51.342382 [Byte1]: 34
3365 16:43:51.347406
3366 16:43:51.347515 Set Vref, RX VrefLevel [Byte0]: 35
3367 16:43:51.350937 [Byte1]: 35
3368 16:43:51.355330
3369 16:43:51.355441 Set Vref, RX VrefLevel [Byte0]: 36
3370 16:43:51.358168 [Byte1]: 36
3371 16:43:51.362938
3372 16:43:51.363050 Set Vref, RX VrefLevel [Byte0]: 37
3373 16:43:51.366567 [Byte1]: 37
3374 16:43:51.371005
3375 16:43:51.371135 Set Vref, RX VrefLevel [Byte0]: 38
3376 16:43:51.373994 [Byte1]: 38
3377 16:43:51.378838
3378 16:43:51.378942 Set Vref, RX VrefLevel [Byte0]: 39
3379 16:43:51.381875 [Byte1]: 39
3380 16:43:51.386673
3381 16:43:51.386798 Set Vref, RX VrefLevel [Byte0]: 40
3382 16:43:51.390268 [Byte1]: 40
3383 16:43:51.394400
3384 16:43:51.394507 Set Vref, RX VrefLevel [Byte0]: 41
3385 16:43:51.397990 [Byte1]: 41
3386 16:43:51.402828
3387 16:43:51.402913 Set Vref, RX VrefLevel [Byte0]: 42
3388 16:43:51.405935 [Byte1]: 42
3389 16:43:51.410863
3390 16:43:51.410986 Set Vref, RX VrefLevel [Byte0]: 43
3391 16:43:51.413764 [Byte1]: 43
3392 16:43:51.418313
3393 16:43:51.418409 Set Vref, RX VrefLevel [Byte0]: 44
3394 16:43:51.421810 [Byte1]: 44
3395 16:43:51.426648
3396 16:43:51.426734 Set Vref, RX VrefLevel [Byte0]: 45
3397 16:43:51.429719 [Byte1]: 45
3398 16:43:51.434567
3399 16:43:51.434680 Set Vref, RX VrefLevel [Byte0]: 46
3400 16:43:51.437493 [Byte1]: 46
3401 16:43:51.442135
3402 16:43:51.442252 Set Vref, RX VrefLevel [Byte0]: 47
3403 16:43:51.445538 [Byte1]: 47
3404 16:43:51.449936
3405 16:43:51.450025 Set Vref, RX VrefLevel [Byte0]: 48
3406 16:43:51.453304 [Byte1]: 48
3407 16:43:51.457867
3408 16:43:51.457959 Set Vref, RX VrefLevel [Byte0]: 49
3409 16:43:51.461398 [Byte1]: 49
3410 16:43:51.465984
3411 16:43:51.466069 Set Vref, RX VrefLevel [Byte0]: 50
3412 16:43:51.469455 [Byte1]: 50
3413 16:43:51.474099
3414 16:43:51.474186 Set Vref, RX VrefLevel [Byte0]: 51
3415 16:43:51.476898 [Byte1]: 51
3416 16:43:51.481664
3417 16:43:51.481746 Set Vref, RX VrefLevel [Byte0]: 52
3418 16:43:51.485167 [Byte1]: 52
3419 16:43:51.489811
3420 16:43:51.489893 Set Vref, RX VrefLevel [Byte0]: 53
3421 16:43:51.492797 [Byte1]: 53
3422 16:43:51.497730
3423 16:43:51.497816 Set Vref, RX VrefLevel [Byte0]: 54
3424 16:43:51.500679 [Byte1]: 54
3425 16:43:51.505610
3426 16:43:51.505720 Set Vref, RX VrefLevel [Byte0]: 55
3427 16:43:51.509198 [Byte1]: 55
3428 16:43:51.513422
3429 16:43:51.513531 Set Vref, RX VrefLevel [Byte0]: 56
3430 16:43:51.516900 [Byte1]: 56
3431 16:43:51.521523
3432 16:43:51.521602 Set Vref, RX VrefLevel [Byte0]: 57
3433 16:43:51.524562 [Byte1]: 57
3434 16:43:51.529433
3435 16:43:51.529516 Set Vref, RX VrefLevel [Byte0]: 58
3436 16:43:51.532606 [Byte1]: 58
3437 16:43:51.537356
3438 16:43:51.537447 Set Vref, RX VrefLevel [Byte0]: 59
3439 16:43:51.540370 [Byte1]: 59
3440 16:43:51.545091
3441 16:43:51.545202 Set Vref, RX VrefLevel [Byte0]: 60
3442 16:43:51.548332 [Byte1]: 60
3443 16:43:51.552899
3444 16:43:51.552994 Set Vref, RX VrefLevel [Byte0]: 61
3445 16:43:51.556183 [Byte1]: 61
3446 16:43:51.560780
3447 16:43:51.560899 Set Vref, RX VrefLevel [Byte0]: 62
3448 16:43:51.564101 [Byte1]: 62
3449 16:43:51.568880
3450 16:43:51.568978 Set Vref, RX VrefLevel [Byte0]: 63
3451 16:43:51.572219 [Byte1]: 63
3452 16:43:51.576830
3453 16:43:51.576926 Set Vref, RX VrefLevel [Byte0]: 64
3454 16:43:51.580279 [Byte1]: 64
3455 16:43:51.584810
3456 16:43:51.584897 Set Vref, RX VrefLevel [Byte0]: 65
3457 16:43:51.587869 [Byte1]: 65
3458 16:43:51.592632
3459 16:43:51.592725 Set Vref, RX VrefLevel [Byte0]: 66
3460 16:43:51.596186 [Byte1]: 66
3461 16:43:51.600807
3462 16:43:51.600901 Final RX Vref Byte 0 = 49 to rank0
3463 16:43:51.603804 Final RX Vref Byte 1 = 53 to rank0
3464 16:43:51.607491 Final RX Vref Byte 0 = 49 to rank1
3465 16:43:51.610588 Final RX Vref Byte 1 = 53 to rank1==
3466 16:43:51.614150 Dram Type= 6, Freq= 0, CH_1, rank 0
3467 16:43:51.620670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 16:43:51.620788 ==
3469 16:43:51.620864 DQS Delay:
3470 16:43:51.620930 DQS0 = 0, DQS1 = 0
3471 16:43:51.623605 DQM Delay:
3472 16:43:51.623705 DQM0 = 116, DQM1 = 109
3473 16:43:51.627012 DQ Delay:
3474 16:43:51.630624 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3475 16:43:51.633672 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =112
3476 16:43:51.637295 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =98
3477 16:43:51.640404 DQ12 =116, DQ13 =116, DQ14 =118, DQ15 =118
3478 16:43:51.640490
3479 16:43:51.640580
3480 16:43:51.646992 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 408 ps
3481 16:43:51.650703 CH1 RK0: MR19=403, MR18=5F9
3482 16:43:51.657243 CH1_RK0: MR19=0x403, MR18=0x5F9, DQSOSC=408, MR23=63, INC=39, DEC=26
3483 16:43:51.657336
3484 16:43:51.660172 ----->DramcWriteLeveling(PI) begin...
3485 16:43:51.660257 ==
3486 16:43:51.663888 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 16:43:51.666902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 16:43:51.670091 ==
3489 16:43:51.670179 Write leveling (Byte 0): 26 => 26
3490 16:43:51.673591 Write leveling (Byte 1): 26 => 26
3491 16:43:51.676872 DramcWriteLeveling(PI) end<-----
3492 16:43:51.676947
3493 16:43:51.677011 ==
3494 16:43:51.680566 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 16:43:51.687345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 16:43:51.687434 ==
3497 16:43:51.687506 [Gating] SW mode calibration
3498 16:43:51.697038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3499 16:43:51.700591 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3500 16:43:51.703506 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3501 16:43:51.710276 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 16:43:51.713856 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 16:43:51.716835 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 16:43:51.723372 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 16:43:51.726969 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 16:43:51.730441 0 15 24 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
3507 16:43:51.737121 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3508 16:43:51.740104 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 16:43:51.743140 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 16:43:51.749862 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 16:43:51.753512 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 16:43:51.756560 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 16:43:51.762944 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 16:43:51.766383 1 0 24 | B1->B0 | 3d3d 2a2a | 0 0 | (0 0) (1 1)
3515 16:43:51.769730 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3516 16:43:51.776368 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 16:43:51.779492 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 16:43:51.782765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 16:43:51.789143 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 16:43:51.792453 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 16:43:51.795891 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 16:43:51.802512 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3523 16:43:51.805453 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3524 16:43:51.809133 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 16:43:51.815697 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 16:43:51.818812 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 16:43:51.822304 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 16:43:51.829009 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 16:43:51.831924 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 16:43:51.835407 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 16:43:51.842201 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 16:43:51.845214 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 16:43:51.851839 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 16:43:51.854921 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 16:43:51.858657 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 16:43:51.865190 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 16:43:51.868180 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 16:43:51.871784 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3539 16:43:51.874977 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3540 16:43:51.881430 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 16:43:51.884782 Total UI for P1: 0, mck2ui 16
3542 16:43:51.887964 best dqsien dly found for B0: ( 1, 3, 26)
3543 16:43:51.891463 Total UI for P1: 0, mck2ui 16
3544 16:43:51.894995 best dqsien dly found for B1: ( 1, 3, 26)
3545 16:43:51.897871 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3546 16:43:51.901452 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3547 16:43:51.901586
3548 16:43:51.904784 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3549 16:43:51.908154 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3550 16:43:51.911382 [Gating] SW calibration Done
3551 16:43:51.911485 ==
3552 16:43:51.914794 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 16:43:51.917927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 16:43:51.918088 ==
3555 16:43:51.921514 RX Vref Scan: 0
3556 16:43:51.921617
3557 16:43:51.924608 RX Vref 0 -> 0, step: 1
3558 16:43:51.924712
3559 16:43:51.924813 RX Delay -40 -> 252, step: 8
3560 16:43:51.931214 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3561 16:43:51.934729 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3562 16:43:51.937688 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3563 16:43:51.940810 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3564 16:43:51.944477 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3565 16:43:51.950516 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3566 16:43:51.954151 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3567 16:43:51.957147 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3568 16:43:51.960707 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3569 16:43:51.963793 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3570 16:43:51.970694 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3571 16:43:51.973719 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3572 16:43:51.977243 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3573 16:43:51.980627 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3574 16:43:51.987203 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3575 16:43:51.990469 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3576 16:43:51.990559 ==
3577 16:43:51.993936 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 16:43:51.996808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 16:43:51.996898 ==
3580 16:43:51.996986 DQS Delay:
3581 16:43:52.000727 DQS0 = 0, DQS1 = 0
3582 16:43:52.000814 DQM Delay:
3583 16:43:52.003799 DQM0 = 117, DQM1 = 109
3584 16:43:52.003892 DQ Delay:
3585 16:43:52.006698 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3586 16:43:52.010200 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3587 16:43:52.013548 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3588 16:43:52.019913 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3589 16:43:52.020003
3590 16:43:52.020090
3591 16:43:52.020172 ==
3592 16:43:52.023380 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 16:43:52.026979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 16:43:52.027073 ==
3595 16:43:52.027161
3596 16:43:52.027243
3597 16:43:52.029980 TX Vref Scan disable
3598 16:43:52.030068 == TX Byte 0 ==
3599 16:43:52.036603 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3600 16:43:52.040226 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3601 16:43:52.040315 == TX Byte 1 ==
3602 16:43:52.046751 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3603 16:43:52.049823 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3604 16:43:52.049904 ==
3605 16:43:52.052906 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 16:43:52.056529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 16:43:52.056604 ==
3608 16:43:52.069337 TX Vref=22, minBit 0, minWin=26, winSum=423
3609 16:43:52.072282 TX Vref=24, minBit 9, minWin=26, winSum=427
3610 16:43:52.075725 TX Vref=26, minBit 9, minWin=26, winSum=433
3611 16:43:52.078693 TX Vref=28, minBit 9, minWin=26, winSum=434
3612 16:43:52.082219 TX Vref=30, minBit 9, minWin=26, winSum=433
3613 16:43:52.088737 TX Vref=32, minBit 9, minWin=26, winSum=429
3614 16:43:52.092026 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3615 16:43:52.092108
3616 16:43:52.095484 Final TX Range 1 Vref 28
3617 16:43:52.095560
3618 16:43:52.095622 ==
3619 16:43:52.098772 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 16:43:52.102101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 16:43:52.105769 ==
3622 16:43:52.105844
3623 16:43:52.105906
3624 16:43:52.105968 TX Vref Scan disable
3625 16:43:52.108869 == TX Byte 0 ==
3626 16:43:52.111879 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3627 16:43:52.118666 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3628 16:43:52.118815 == TX Byte 1 ==
3629 16:43:52.121830 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3630 16:43:52.128878 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3631 16:43:52.128966
3632 16:43:52.129032 [DATLAT]
3633 16:43:52.129096 Freq=1200, CH1 RK1
3634 16:43:52.129155
3635 16:43:52.131789 DATLAT Default: 0xd
3636 16:43:52.131953 0, 0xFFFF, sum = 0
3637 16:43:52.135369 1, 0xFFFF, sum = 0
3638 16:43:52.138435 2, 0xFFFF, sum = 0
3639 16:43:52.138527 3, 0xFFFF, sum = 0
3640 16:43:52.141527 4, 0xFFFF, sum = 0
3641 16:43:52.141610 5, 0xFFFF, sum = 0
3642 16:43:52.145056 6, 0xFFFF, sum = 0
3643 16:43:52.145168 7, 0xFFFF, sum = 0
3644 16:43:52.148540 8, 0xFFFF, sum = 0
3645 16:43:52.148624 9, 0xFFFF, sum = 0
3646 16:43:52.151526 10, 0xFFFF, sum = 0
3647 16:43:52.151610 11, 0xFFFF, sum = 0
3648 16:43:52.155176 12, 0x0, sum = 1
3649 16:43:52.155260 13, 0x0, sum = 2
3650 16:43:52.158153 14, 0x0, sum = 3
3651 16:43:52.158245 15, 0x0, sum = 4
3652 16:43:52.161659 best_step = 13
3653 16:43:52.161741
3654 16:43:52.161806 ==
3655 16:43:52.164714 Dram Type= 6, Freq= 0, CH_1, rank 1
3656 16:43:52.168394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3657 16:43:52.168477 ==
3658 16:43:52.171387 RX Vref Scan: 0
3659 16:43:52.171469
3660 16:43:52.171533 RX Vref 0 -> 0, step: 1
3661 16:43:52.171594
3662 16:43:52.174912 RX Delay -21 -> 252, step: 4
3663 16:43:52.181324 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3664 16:43:52.184361 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3665 16:43:52.187956 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3666 16:43:52.190929 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3667 16:43:52.194425 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3668 16:43:52.200748 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3669 16:43:52.204127 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3670 16:43:52.207723 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3671 16:43:52.211046 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3672 16:43:52.214472 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3673 16:43:52.220766 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3674 16:43:52.224155 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3675 16:43:52.227455 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3676 16:43:52.230758 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3677 16:43:52.234257 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3678 16:43:52.240966 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3679 16:43:52.241059 ==
3680 16:43:52.244030 Dram Type= 6, Freq= 0, CH_1, rank 1
3681 16:43:52.247666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3682 16:43:52.247750 ==
3683 16:43:52.247816 DQS Delay:
3684 16:43:52.251077 DQS0 = 0, DQS1 = 0
3685 16:43:52.251222 DQM Delay:
3686 16:43:52.254137 DQM0 = 116, DQM1 = 110
3687 16:43:52.254239 DQ Delay:
3688 16:43:52.257198 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3689 16:43:52.260812 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =114
3690 16:43:52.263904 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3691 16:43:52.267574 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3692 16:43:52.270541
3693 16:43:52.270627
3694 16:43:52.277309 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8f3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3695 16:43:52.280320 CH1 RK1: MR19=303, MR18=F8F3
3696 16:43:52.287356 CH1_RK1: MR19=0x303, MR18=0xF8F3, DQSOSC=413, MR23=63, INC=38, DEC=25
3697 16:43:52.290281 [RxdqsGatingPostProcess] freq 1200
3698 16:43:52.293824 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3699 16:43:52.296822 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 16:43:52.300468 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 16:43:52.303893 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 16:43:52.306763 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 16:43:52.310289 best DQS0 dly(2T, 0.5T) = (0, 11)
3704 16:43:52.313724 best DQS1 dly(2T, 0.5T) = (0, 11)
3705 16:43:52.316571 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3706 16:43:52.320034 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3707 16:43:52.323437 Pre-setting of DQS Precalculation
3708 16:43:52.326923 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3709 16:43:52.336851 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3710 16:43:52.343213 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3711 16:43:52.343322
3712 16:43:52.343389
3713 16:43:52.346797 [Calibration Summary] 2400 Mbps
3714 16:43:52.346881 CH 0, Rank 0
3715 16:43:52.349859 SW Impedance : PASS
3716 16:43:52.349953 DUTY Scan : NO K
3717 16:43:52.353310 ZQ Calibration : PASS
3718 16:43:52.356218 Jitter Meter : NO K
3719 16:43:52.356321 CBT Training : PASS
3720 16:43:52.359849 Write leveling : PASS
3721 16:43:52.362912 RX DQS gating : PASS
3722 16:43:52.363020 RX DQ/DQS(RDDQC) : PASS
3723 16:43:52.366630 TX DQ/DQS : PASS
3724 16:43:52.369742 RX DATLAT : PASS
3725 16:43:52.369826 RX DQ/DQS(Engine): PASS
3726 16:43:52.372827 TX OE : NO K
3727 16:43:52.372940 All Pass.
3728 16:43:52.373037
3729 16:43:52.376450 CH 0, Rank 1
3730 16:43:52.376547 SW Impedance : PASS
3731 16:43:52.379435 DUTY Scan : NO K
3732 16:43:52.382548 ZQ Calibration : PASS
3733 16:43:52.382648 Jitter Meter : NO K
3734 16:43:52.386077 CBT Training : PASS
3735 16:43:52.389415 Write leveling : PASS
3736 16:43:52.389502 RX DQS gating : PASS
3737 16:43:52.392431 RX DQ/DQS(RDDQC) : PASS
3738 16:43:52.396060 TX DQ/DQS : PASS
3739 16:43:52.396175 RX DATLAT : PASS
3740 16:43:52.399041 RX DQ/DQS(Engine): PASS
3741 16:43:52.402755 TX OE : NO K
3742 16:43:52.402837 All Pass.
3743 16:43:52.402917
3744 16:43:52.402979 CH 1, Rank 0
3745 16:43:52.405721 SW Impedance : PASS
3746 16:43:52.409118 DUTY Scan : NO K
3747 16:43:52.409221 ZQ Calibration : PASS
3748 16:43:52.412358 Jitter Meter : NO K
3749 16:43:52.415315 CBT Training : PASS
3750 16:43:52.415412 Write leveling : PASS
3751 16:43:52.418752 RX DQS gating : PASS
3752 16:43:52.418850 RX DQ/DQS(RDDQC) : PASS
3753 16:43:52.422190 TX DQ/DQS : PASS
3754 16:43:52.425745 RX DATLAT : PASS
3755 16:43:52.425845 RX DQ/DQS(Engine): PASS
3756 16:43:52.429116 TX OE : NO K
3757 16:43:52.429201 All Pass.
3758 16:43:52.429267
3759 16:43:52.432423 CH 1, Rank 1
3760 16:43:52.432507 SW Impedance : PASS
3761 16:43:52.435426 DUTY Scan : NO K
3762 16:43:52.438769 ZQ Calibration : PASS
3763 16:43:52.438873 Jitter Meter : NO K
3764 16:43:52.442213 CBT Training : PASS
3765 16:43:52.445654 Write leveling : PASS
3766 16:43:52.445758 RX DQS gating : PASS
3767 16:43:52.448791 RX DQ/DQS(RDDQC) : PASS
3768 16:43:52.452390 TX DQ/DQS : PASS
3769 16:43:52.452467 RX DATLAT : PASS
3770 16:43:52.455346 RX DQ/DQS(Engine): PASS
3771 16:43:52.458830 TX OE : NO K
3772 16:43:52.458928 All Pass.
3773 16:43:52.459023
3774 16:43:52.459136 DramC Write-DBI off
3775 16:43:52.461803 PER_BANK_REFRESH: Hybrid Mode
3776 16:43:52.465447 TX_TRACKING: ON
3777 16:43:52.472110 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3778 16:43:52.475002 [FAST_K] Save calibration result to emmc
3779 16:43:52.481693 dramc_set_vcore_voltage set vcore to 650000
3780 16:43:52.481799 Read voltage for 600, 5
3781 16:43:52.485332 Vio18 = 0
3782 16:43:52.485436 Vcore = 650000
3783 16:43:52.485525 Vdram = 0
3784 16:43:52.488210 Vddq = 0
3785 16:43:52.488308 Vmddr = 0
3786 16:43:52.491548 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3787 16:43:52.498132 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3788 16:43:52.501662 MEM_TYPE=3, freq_sel=19
3789 16:43:52.504736 sv_algorithm_assistance_LP4_1600
3790 16:43:52.508358 ============ PULL DRAM RESETB DOWN ============
3791 16:43:52.511860 ========== PULL DRAM RESETB DOWN end =========
3792 16:43:52.514778 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3793 16:43:52.518087 ===================================
3794 16:43:52.521449 LPDDR4 DRAM CONFIGURATION
3795 16:43:52.524718 ===================================
3796 16:43:52.528170 EX_ROW_EN[0] = 0x0
3797 16:43:52.528255 EX_ROW_EN[1] = 0x0
3798 16:43:52.531552 LP4Y_EN = 0x0
3799 16:43:52.531636 WORK_FSP = 0x0
3800 16:43:52.534320 WL = 0x2
3801 16:43:52.534431 RL = 0x2
3802 16:43:52.537636 BL = 0x2
3803 16:43:52.541116 RPST = 0x0
3804 16:43:52.541204 RD_PRE = 0x0
3805 16:43:52.544493 WR_PRE = 0x1
3806 16:43:52.544587 WR_PST = 0x0
3807 16:43:52.547713 DBI_WR = 0x0
3808 16:43:52.547796 DBI_RD = 0x0
3809 16:43:52.550938 OTF = 0x1
3810 16:43:52.554488 ===================================
3811 16:43:52.558029 ===================================
3812 16:43:52.558143 ANA top config
3813 16:43:52.561026 ===================================
3814 16:43:52.564464 DLL_ASYNC_EN = 0
3815 16:43:52.567440 ALL_SLAVE_EN = 1
3816 16:43:52.567521 NEW_RANK_MODE = 1
3817 16:43:52.570991 DLL_IDLE_MODE = 1
3818 16:43:52.573820 LP45_APHY_COMB_EN = 1
3819 16:43:52.577356 TX_ODT_DIS = 1
3820 16:43:52.581015 NEW_8X_MODE = 1
3821 16:43:52.584058 ===================================
3822 16:43:52.586999 ===================================
3823 16:43:52.587149 data_rate = 1200
3824 16:43:52.590655 CKR = 1
3825 16:43:52.594162 DQ_P2S_RATIO = 8
3826 16:43:52.597202 ===================================
3827 16:43:52.600762 CA_P2S_RATIO = 8
3828 16:43:52.603751 DQ_CA_OPEN = 0
3829 16:43:52.607350 DQ_SEMI_OPEN = 0
3830 16:43:52.607426 CA_SEMI_OPEN = 0
3831 16:43:52.610342 CA_FULL_RATE = 0
3832 16:43:52.613451 DQ_CKDIV4_EN = 1
3833 16:43:52.616995 CA_CKDIV4_EN = 1
3834 16:43:52.620685 CA_PREDIV_EN = 0
3835 16:43:52.623443 PH8_DLY = 0
3836 16:43:52.623529 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3837 16:43:52.626828 DQ_AAMCK_DIV = 4
3838 16:43:52.630145 CA_AAMCK_DIV = 4
3839 16:43:52.633354 CA_ADMCK_DIV = 4
3840 16:43:52.636841 DQ_TRACK_CA_EN = 0
3841 16:43:52.640347 CA_PICK = 600
3842 16:43:52.643823 CA_MCKIO = 600
3843 16:43:52.643955 MCKIO_SEMI = 0
3844 16:43:52.646574 PLL_FREQ = 2288
3845 16:43:52.649987 DQ_UI_PI_RATIO = 32
3846 16:43:52.653440 CA_UI_PI_RATIO = 0
3847 16:43:52.656956 ===================================
3848 16:43:52.660051 ===================================
3849 16:43:52.663555 memory_type:LPDDR4
3850 16:43:52.663670 GP_NUM : 10
3851 16:43:52.666511 SRAM_EN : 1
3852 16:43:52.670036 MD32_EN : 0
3853 16:43:52.673091 ===================================
3854 16:43:52.673172 [ANA_INIT] >>>>>>>>>>>>>>
3855 16:43:52.676021 <<<<<< [CONFIGURE PHASE]: ANA_TX
3856 16:43:52.679739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3857 16:43:52.682811 ===================================
3858 16:43:52.686063 data_rate = 1200,PCW = 0X5800
3859 16:43:52.689654 ===================================
3860 16:43:52.692569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3861 16:43:52.699141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3862 16:43:52.706217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 16:43:52.709167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3864 16:43:52.712797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3865 16:43:52.715788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3866 16:43:52.719437 [ANA_INIT] flow start
3867 16:43:52.719553 [ANA_INIT] PLL >>>>>>>>
3868 16:43:52.722351 [ANA_INIT] PLL <<<<<<<<
3869 16:43:52.725912 [ANA_INIT] MIDPI >>>>>>>>
3870 16:43:52.726026 [ANA_INIT] MIDPI <<<<<<<<
3871 16:43:52.728872 [ANA_INIT] DLL >>>>>>>>
3872 16:43:52.732688 [ANA_INIT] flow end
3873 16:43:52.735591 ============ LP4 DIFF to SE enter ============
3874 16:43:52.738859 ============ LP4 DIFF to SE exit ============
3875 16:43:52.742271 [ANA_INIT] <<<<<<<<<<<<<
3876 16:43:52.745680 [Flow] Enable top DCM control >>>>>
3877 16:43:52.748959 [Flow] Enable top DCM control <<<<<
3878 16:43:52.751938 Enable DLL master slave shuffle
3879 16:43:52.755346 ==============================================================
3880 16:43:52.758641 Gating Mode config
3881 16:43:52.765599 ==============================================================
3882 16:43:52.765708 Config description:
3883 16:43:52.775465 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3884 16:43:52.782086 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3885 16:43:52.788163 SELPH_MODE 0: By rank 1: By Phase
3886 16:43:52.791787 ==============================================================
3887 16:43:52.794795 GAT_TRACK_EN = 1
3888 16:43:52.798299 RX_GATING_MODE = 2
3889 16:43:52.802021 RX_GATING_TRACK_MODE = 2
3890 16:43:52.804886 SELPH_MODE = 1
3891 16:43:52.808446 PICG_EARLY_EN = 1
3892 16:43:52.811308 VALID_LAT_VALUE = 1
3893 16:43:52.814952 ==============================================================
3894 16:43:52.817971 Enter into Gating configuration >>>>
3895 16:43:52.821738 Exit from Gating configuration <<<<
3896 16:43:52.824686 Enter into DVFS_PRE_config >>>>>
3897 16:43:52.837748 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3898 16:43:52.841320 Exit from DVFS_PRE_config <<<<<
3899 16:43:52.844764 Enter into PICG configuration >>>>
3900 16:43:52.847725 Exit from PICG configuration <<<<
3901 16:43:52.847815 [RX_INPUT] configuration >>>>>
3902 16:43:52.851292 [RX_INPUT] configuration <<<<<
3903 16:43:52.858109 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3904 16:43:52.861048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3905 16:43:52.868019 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 16:43:52.874599 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 16:43:52.881124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 16:43:52.887922 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 16:43:52.891039 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3910 16:43:52.894154 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3911 16:43:52.900458 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3912 16:43:52.903509 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3913 16:43:52.907464 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3914 16:43:52.913418 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 16:43:52.916950 ===================================
3916 16:43:52.917044 LPDDR4 DRAM CONFIGURATION
3917 16:43:52.920053 ===================================
3918 16:43:52.923660 EX_ROW_EN[0] = 0x0
3919 16:43:52.926689 EX_ROW_EN[1] = 0x0
3920 16:43:52.926782 LP4Y_EN = 0x0
3921 16:43:52.930261 WORK_FSP = 0x0
3922 16:43:52.930349 WL = 0x2
3923 16:43:52.933388 RL = 0x2
3924 16:43:52.933481 BL = 0x2
3925 16:43:52.936862 RPST = 0x0
3926 16:43:52.936951 RD_PRE = 0x0
3927 16:43:52.939900 WR_PRE = 0x1
3928 16:43:52.939986 WR_PST = 0x0
3929 16:43:52.943349 DBI_WR = 0x0
3930 16:43:52.943433 DBI_RD = 0x0
3931 16:43:52.946757 OTF = 0x1
3932 16:43:52.949819 ===================================
3933 16:43:52.953053 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3934 16:43:52.956401 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3935 16:43:52.963528 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 16:43:52.966226 ===================================
3937 16:43:52.966323 LPDDR4 DRAM CONFIGURATION
3938 16:43:52.969750 ===================================
3939 16:43:52.973077 EX_ROW_EN[0] = 0x10
3940 16:43:52.975958 EX_ROW_EN[1] = 0x0
3941 16:43:52.976049 LP4Y_EN = 0x0
3942 16:43:52.979641 WORK_FSP = 0x0
3943 16:43:52.979755 WL = 0x2
3944 16:43:52.983074 RL = 0x2
3945 16:43:52.983207 BL = 0x2
3946 16:43:52.986169 RPST = 0x0
3947 16:43:52.986255 RD_PRE = 0x0
3948 16:43:52.989741 WR_PRE = 0x1
3949 16:43:52.989843 WR_PST = 0x0
3950 16:43:52.992677 DBI_WR = 0x0
3951 16:43:52.992824 DBI_RD = 0x0
3952 16:43:52.996374 OTF = 0x1
3953 16:43:52.999240 ===================================
3954 16:43:53.005795 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3955 16:43:53.009408 nWR fixed to 30
3956 16:43:53.009505 [ModeRegInit_LP4] CH0 RK0
3957 16:43:53.012420 [ModeRegInit_LP4] CH0 RK1
3958 16:43:53.015998 [ModeRegInit_LP4] CH1 RK0
3959 16:43:53.018990 [ModeRegInit_LP4] CH1 RK1
3960 16:43:53.019109 match AC timing 17
3961 16:43:53.025759 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3962 16:43:53.029459 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3963 16:43:53.032553 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3964 16:43:53.039299 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3965 16:43:53.042304 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3966 16:43:53.042403 ==
3967 16:43:53.045781 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 16:43:53.048773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 16:43:53.048864 ==
3970 16:43:53.055597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 16:43:53.061936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3972 16:43:53.065495 [CA 0] Center 36 (6~66) winsize 61
3973 16:43:53.069048 [CA 1] Center 36 (6~66) winsize 61
3974 16:43:53.072297 [CA 2] Center 33 (3~64) winsize 62
3975 16:43:53.075305 [CA 3] Center 34 (4~65) winsize 62
3976 16:43:53.078705 [CA 4] Center 33 (3~64) winsize 62
3977 16:43:53.082231 [CA 5] Center 33 (3~64) winsize 62
3978 16:43:53.082329
3979 16:43:53.085659 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3980 16:43:53.085751
3981 16:43:53.088502 [CATrainingPosCal] consider 1 rank data
3982 16:43:53.092131 u2DelayCellTimex100 = 270/100 ps
3983 16:43:53.095017 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3984 16:43:53.098711 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 16:43:53.101633 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 16:43:53.105199 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3987 16:43:53.108338 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 16:43:53.112168 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 16:43:53.114997
3990 16:43:53.118557 CA PerBit enable=1, Macro0, CA PI delay=33
3991 16:43:53.118660
3992 16:43:53.122007 [CBTSetCACLKResult] CA Dly = 33
3993 16:43:53.122100 CS Dly: 6 (0~37)
3994 16:43:53.122175 ==
3995 16:43:53.125133 Dram Type= 6, Freq= 0, CH_0, rank 1
3996 16:43:53.128149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 16:43:53.128242 ==
3998 16:43:53.134894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3999 16:43:53.141467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4000 16:43:53.145051 [CA 0] Center 36 (6~66) winsize 61
4001 16:43:53.148053 [CA 1] Center 36 (6~66) winsize 61
4002 16:43:53.151103 [CA 2] Center 34 (4~64) winsize 61
4003 16:43:53.154533 [CA 3] Center 33 (3~64) winsize 62
4004 16:43:53.157991 [CA 4] Center 33 (2~64) winsize 63
4005 16:43:53.161406 [CA 5] Center 33 (2~64) winsize 63
4006 16:43:53.161565
4007 16:43:53.164228 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4008 16:43:53.164379
4009 16:43:53.167640 [CATrainingPosCal] consider 2 rank data
4010 16:43:53.171233 u2DelayCellTimex100 = 270/100 ps
4011 16:43:53.174882 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4012 16:43:53.178075 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4013 16:43:53.180917 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4014 16:43:53.187908 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4015 16:43:53.190924 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4016 16:43:53.194221 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4017 16:43:53.194322
4018 16:43:53.197640 CA PerBit enable=1, Macro0, CA PI delay=33
4019 16:43:53.197724
4020 16:43:53.200636 [CBTSetCACLKResult] CA Dly = 33
4021 16:43:53.200720 CS Dly: 6 (0~37)
4022 16:43:53.200815
4023 16:43:53.204310 ----->DramcWriteLeveling(PI) begin...
4024 16:43:53.204410 ==
4025 16:43:53.207198 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 16:43:53.213800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 16:43:53.213918 ==
4028 16:43:53.217382 Write leveling (Byte 0): 34 => 34
4029 16:43:53.220519 Write leveling (Byte 1): 29 => 29
4030 16:43:53.224118 DramcWriteLeveling(PI) end<-----
4031 16:43:53.224232
4032 16:43:53.224326 ==
4033 16:43:53.227068 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 16:43:53.230865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 16:43:53.230982 ==
4036 16:43:53.233816 [Gating] SW mode calibration
4037 16:43:53.240413 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4038 16:43:53.247020 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4039 16:43:53.250629 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 16:43:53.253748 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 16:43:53.260322 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 16:43:53.263616 0 9 12 | B1->B0 | 3434 3030 | 0 1 | (0 1) (1 1)
4043 16:43:53.266951 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
4044 16:43:53.273578 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 16:43:53.276570 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 16:43:53.279906 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 16:43:53.283395 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 16:43:53.289731 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 16:43:53.293206 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 16:43:53.296582 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4051 16:43:53.302855 0 10 16 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
4052 16:43:53.306408 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 16:43:53.309868 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 16:43:53.316599 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 16:43:53.319469 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 16:43:53.322980 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 16:43:53.329359 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 16:43:53.332959 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 16:43:53.335911 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4060 16:43:53.342988 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 16:43:53.345949 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 16:43:53.349689 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 16:43:53.355671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 16:43:53.359392 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 16:43:53.362393 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 16:43:53.369397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 16:43:53.372177 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 16:43:53.375596 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 16:43:53.382235 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 16:43:53.385622 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 16:43:53.388990 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 16:43:53.395995 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 16:43:53.398715 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 16:43:53.402445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 16:43:53.408627 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4076 16:43:53.412182 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 16:43:53.415208 Total UI for P1: 0, mck2ui 16
4078 16:43:53.418815 best dqsien dly found for B0: ( 0, 13, 16)
4079 16:43:53.421839 Total UI for P1: 0, mck2ui 16
4080 16:43:53.425528 best dqsien dly found for B1: ( 0, 13, 16)
4081 16:43:53.428513 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4082 16:43:53.432113 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4083 16:43:53.432228
4084 16:43:53.435148 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4085 16:43:53.441712 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4086 16:43:53.441832 [Gating] SW calibration Done
4087 16:43:53.441931 ==
4088 16:43:53.445327 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 16:43:53.452089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 16:43:53.452195 ==
4091 16:43:53.452287 RX Vref Scan: 0
4092 16:43:53.452368
4093 16:43:53.455197 RX Vref 0 -> 0, step: 1
4094 16:43:53.455279
4095 16:43:53.458274 RX Delay -230 -> 252, step: 16
4096 16:43:53.461768 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4097 16:43:53.464762 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4098 16:43:53.468360 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4099 16:43:53.474900 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4100 16:43:53.478309 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4101 16:43:53.481760 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4102 16:43:53.485156 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4103 16:43:53.491297 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4104 16:43:53.494773 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4105 16:43:53.498328 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4106 16:43:53.501263 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4107 16:43:53.508123 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4108 16:43:53.511516 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4109 16:43:53.514880 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4110 16:43:53.517723 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4111 16:43:53.524691 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4112 16:43:53.524791 ==
4113 16:43:53.527691 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 16:43:53.531286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 16:43:53.531371 ==
4116 16:43:53.531437 DQS Delay:
4117 16:43:53.534297 DQS0 = 0, DQS1 = 0
4118 16:43:53.534390 DQM Delay:
4119 16:43:53.537888 DQM0 = 45, DQM1 = 33
4120 16:43:53.537977 DQ Delay:
4121 16:43:53.540864 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4122 16:43:53.544453 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =49
4123 16:43:53.547486 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4124 16:43:53.551140 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4125 16:43:53.551255
4126 16:43:53.551330
4127 16:43:53.551393 ==
4128 16:43:53.554172 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 16:43:53.557874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 16:43:53.557961 ==
4131 16:43:53.560868
4132 16:43:53.560950
4133 16:43:53.561017 TX Vref Scan disable
4134 16:43:53.564441 == TX Byte 0 ==
4135 16:43:53.567506 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4136 16:43:53.571014 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4137 16:43:53.574088 == TX Byte 1 ==
4138 16:43:53.577032 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4139 16:43:53.580579 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4140 16:43:53.583965 ==
4141 16:43:53.587338 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 16:43:53.590371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 16:43:53.590483 ==
4144 16:43:53.590588
4145 16:43:53.590689
4146 16:43:53.593558 TX Vref Scan disable
4147 16:43:53.596892 == TX Byte 0 ==
4148 16:43:53.600392 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4149 16:43:53.603290 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4150 16:43:53.606673 == TX Byte 1 ==
4151 16:43:53.610084 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4152 16:43:53.613534 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4153 16:43:53.613640
4154 16:43:53.613738 [DATLAT]
4155 16:43:53.616893 Freq=600, CH0 RK0
4156 16:43:53.617000
4157 16:43:53.620110 DATLAT Default: 0x9
4158 16:43:53.620214 0, 0xFFFF, sum = 0
4159 16:43:53.623777 1, 0xFFFF, sum = 0
4160 16:43:53.623892 2, 0xFFFF, sum = 0
4161 16:43:53.626793 3, 0xFFFF, sum = 0
4162 16:43:53.626872 4, 0xFFFF, sum = 0
4163 16:43:53.629753 5, 0xFFFF, sum = 0
4164 16:43:53.629853 6, 0xFFFF, sum = 0
4165 16:43:53.633310 7, 0xFFFF, sum = 0
4166 16:43:53.633430 8, 0x0, sum = 1
4167 16:43:53.636382 9, 0x0, sum = 2
4168 16:43:53.636499 10, 0x0, sum = 3
4169 16:43:53.639894 11, 0x0, sum = 4
4170 16:43:53.639976 best_step = 9
4171 16:43:53.640054
4172 16:43:53.640148 ==
4173 16:43:53.642781 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 16:43:53.646372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 16:43:53.646473 ==
4176 16:43:53.649502 RX Vref Scan: 1
4177 16:43:53.649586
4178 16:43:53.653184 RX Vref 0 -> 0, step: 1
4179 16:43:53.653290
4180 16:43:53.653383 RX Delay -179 -> 252, step: 8
4181 16:43:53.656217
4182 16:43:53.656317 Set Vref, RX VrefLevel [Byte0]: 59
4183 16:43:53.659277 [Byte1]: 49
4184 16:43:53.664129
4185 16:43:53.664206 Final RX Vref Byte 0 = 59 to rank0
4186 16:43:53.667872 Final RX Vref Byte 1 = 49 to rank0
4187 16:43:53.670804 Final RX Vref Byte 0 = 59 to rank1
4188 16:43:53.674428 Final RX Vref Byte 1 = 49 to rank1==
4189 16:43:53.677501 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 16:43:53.684140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 16:43:53.684226 ==
4192 16:43:53.684299 DQS Delay:
4193 16:43:53.687602 DQS0 = 0, DQS1 = 0
4194 16:43:53.687680 DQM Delay:
4195 16:43:53.687745 DQM0 = 43, DQM1 = 32
4196 16:43:53.690969 DQ Delay:
4197 16:43:53.694227 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4198 16:43:53.697281 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4199 16:43:53.700825 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4200 16:43:53.703712 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4201 16:43:53.703792
4202 16:43:53.703856
4203 16:43:53.710468 [DQSOSCAuto] RK0, (LSB)MR18= 0x633a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4204 16:43:53.713882 CH0 RK0: MR19=808, MR18=633A
4205 16:43:53.720059 CH0_RK0: MR19=0x808, MR18=0x633A, DQSOSC=391, MR23=63, INC=171, DEC=114
4206 16:43:53.720151
4207 16:43:53.723360 ----->DramcWriteLeveling(PI) begin...
4208 16:43:53.723467 ==
4209 16:43:53.726650 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 16:43:53.730305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 16:43:53.730384 ==
4212 16:43:53.733573 Write leveling (Byte 0): 34 => 34
4213 16:43:53.737083 Write leveling (Byte 1): 34 => 34
4214 16:43:53.740207 DramcWriteLeveling(PI) end<-----
4215 16:43:53.740282
4216 16:43:53.740346 ==
4217 16:43:53.743797 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 16:43:53.746707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 16:43:53.750341 ==
4220 16:43:53.750416 [Gating] SW mode calibration
4221 16:43:53.759978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4222 16:43:53.763077 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4223 16:43:53.766752 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 16:43:53.773300 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 16:43:53.776447 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 16:43:53.780061 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4227 16:43:53.786754 0 9 16 | B1->B0 | 2e2e 2929 | 0 0 | (1 1) (1 1)
4228 16:43:53.789682 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 16:43:53.793267 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 16:43:53.799708 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 16:43:53.803070 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 16:43:53.805955 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 16:43:53.812638 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 16:43:53.816165 0 10 12 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 1)
4235 16:43:53.819422 0 10 16 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
4236 16:43:53.826168 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 16:43:53.829511 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 16:43:53.832739 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 16:43:53.839241 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 16:43:53.842658 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 16:43:53.846200 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 16:43:53.852698 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4243 16:43:53.855721 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4244 16:43:53.858728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 16:43:53.865393 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 16:43:53.869002 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 16:43:53.872018 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 16:43:53.879071 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 16:43:53.882156 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 16:43:53.885199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 16:43:53.891903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 16:43:53.894973 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 16:43:53.898565 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 16:43:53.904973 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 16:43:53.908574 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 16:43:53.911886 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 16:43:53.918494 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 16:43:53.921880 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4259 16:43:53.924750 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 16:43:53.928282 Total UI for P1: 0, mck2ui 16
4261 16:43:53.931726 best dqsien dly found for B0: ( 0, 13, 12)
4262 16:43:53.935021 Total UI for P1: 0, mck2ui 16
4263 16:43:53.938332 best dqsien dly found for B1: ( 0, 13, 12)
4264 16:43:53.941852 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4265 16:43:53.945096 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4266 16:43:53.945171
4267 16:43:53.951430 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4268 16:43:53.954891 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4269 16:43:53.954998 [Gating] SW calibration Done
4270 16:43:53.958483 ==
4271 16:43:53.961453 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 16:43:53.965131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 16:43:53.965232 ==
4274 16:43:53.965332 RX Vref Scan: 0
4275 16:43:53.965424
4276 16:43:53.968174 RX Vref 0 -> 0, step: 1
4277 16:43:53.968275
4278 16:43:53.971869 RX Delay -230 -> 252, step: 16
4279 16:43:53.975008 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4280 16:43:53.977998 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4281 16:43:53.984669 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4282 16:43:53.988177 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4283 16:43:53.991179 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4284 16:43:53.994741 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4285 16:43:54.000892 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4286 16:43:54.004404 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4287 16:43:54.007874 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4288 16:43:54.010749 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4289 16:43:54.017475 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4290 16:43:54.020838 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4291 16:43:54.024182 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4292 16:43:54.027585 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4293 16:43:54.034162 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4294 16:43:54.037428 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4295 16:43:54.037514 ==
4296 16:43:54.040839 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 16:43:54.044032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 16:43:54.044118 ==
4299 16:43:54.047494 DQS Delay:
4300 16:43:54.047577 DQS0 = 0, DQS1 = 0
4301 16:43:54.047643 DQM Delay:
4302 16:43:54.050567 DQM0 = 40, DQM1 = 34
4303 16:43:54.050650 DQ Delay:
4304 16:43:54.053906 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4305 16:43:54.057143 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4306 16:43:54.060525 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4307 16:43:54.063920 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4308 16:43:54.064004
4309 16:43:54.064069
4310 16:43:54.064128 ==
4311 16:43:54.066992 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 16:43:54.073771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 16:43:54.073855 ==
4314 16:43:54.073921
4315 16:43:54.073980
4316 16:43:54.074038 TX Vref Scan disable
4317 16:43:54.077384 == TX Byte 0 ==
4318 16:43:54.080355 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4319 16:43:54.087023 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4320 16:43:54.087141 == TX Byte 1 ==
4321 16:43:54.090659 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4322 16:43:54.097294 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4323 16:43:54.097379 ==
4324 16:43:54.100257 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 16:43:54.103841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 16:43:54.103925 ==
4327 16:43:54.103991
4328 16:43:54.104058
4329 16:43:54.106887 TX Vref Scan disable
4330 16:43:54.110477 == TX Byte 0 ==
4331 16:43:54.113341 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4332 16:43:54.116904 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4333 16:43:54.119997 == TX Byte 1 ==
4334 16:43:54.123608 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4335 16:43:54.127008 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4336 16:43:54.127129
4337 16:43:54.127194 [DATLAT]
4338 16:43:54.129810 Freq=600, CH0 RK1
4339 16:43:54.129891
4340 16:43:54.133212 DATLAT Default: 0x9
4341 16:43:54.133390 0, 0xFFFF, sum = 0
4342 16:43:54.136845 1, 0xFFFF, sum = 0
4343 16:43:54.136930 2, 0xFFFF, sum = 0
4344 16:43:54.140172 3, 0xFFFF, sum = 0
4345 16:43:54.140270 4, 0xFFFF, sum = 0
4346 16:43:54.142961 5, 0xFFFF, sum = 0
4347 16:43:54.143044 6, 0xFFFF, sum = 0
4348 16:43:54.146330 7, 0xFFFF, sum = 0
4349 16:43:54.146419 8, 0x0, sum = 1
4350 16:43:54.149905 9, 0x0, sum = 2
4351 16:43:54.149989 10, 0x0, sum = 3
4352 16:43:54.153077 11, 0x0, sum = 4
4353 16:43:54.153159 best_step = 9
4354 16:43:54.153223
4355 16:43:54.153299 ==
4356 16:43:54.156526 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 16:43:54.159862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 16:43:54.159945 ==
4359 16:43:54.163387 RX Vref Scan: 0
4360 16:43:54.163471
4361 16:43:54.166154 RX Vref 0 -> 0, step: 1
4362 16:43:54.166235
4363 16:43:54.166298 RX Delay -179 -> 252, step: 8
4364 16:43:54.174365 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4365 16:43:54.177403 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4366 16:43:54.181026 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4367 16:43:54.183987 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4368 16:43:54.190756 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4369 16:43:54.193767 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4370 16:43:54.197370 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4371 16:43:54.200405 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4372 16:43:54.206942 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4373 16:43:54.210410 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4374 16:43:54.213587 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4375 16:43:54.217181 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4376 16:43:54.223822 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4377 16:43:54.226843 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4378 16:43:54.230297 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4379 16:43:54.233360 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4380 16:43:54.233472 ==
4381 16:43:54.236869 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 16:43:54.243149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 16:43:54.243234 ==
4384 16:43:54.243299 DQS Delay:
4385 16:43:54.246723 DQS0 = 0, DQS1 = 0
4386 16:43:54.246875 DQM Delay:
4387 16:43:54.246969 DQM0 = 41, DQM1 = 36
4388 16:43:54.249754 DQ Delay:
4389 16:43:54.253434 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4390 16:43:54.256610 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4391 16:43:54.259713 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4392 16:43:54.262867 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4393 16:43:54.262948
4394 16:43:54.263011
4395 16:43:54.269587 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e10, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4396 16:43:54.273032 CH0 RK1: MR19=808, MR18=5E10
4397 16:43:54.279433 CH0_RK1: MR19=0x808, MR18=0x5E10, DQSOSC=392, MR23=63, INC=170, DEC=113
4398 16:43:54.282953 [RxdqsGatingPostProcess] freq 600
4399 16:43:54.289590 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4400 16:43:54.289678 Pre-setting of DQS Precalculation
4401 16:43:54.296428 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4402 16:43:54.296512 ==
4403 16:43:54.299308 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 16:43:54.302426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 16:43:54.302502 ==
4406 16:43:54.308977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4407 16:43:54.315702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4408 16:43:54.319208 [CA 0] Center 35 (5~66) winsize 62
4409 16:43:54.322727 [CA 1] Center 35 (5~66) winsize 62
4410 16:43:54.325781 [CA 2] Center 34 (4~65) winsize 62
4411 16:43:54.328841 [CA 3] Center 33 (3~64) winsize 62
4412 16:43:54.332260 [CA 4] Center 34 (4~64) winsize 61
4413 16:43:54.335821 [CA 5] Center 33 (3~64) winsize 62
4414 16:43:54.335907
4415 16:43:54.338793 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4416 16:43:54.338875
4417 16:43:54.342345 [CATrainingPosCal] consider 1 rank data
4418 16:43:54.345294 u2DelayCellTimex100 = 270/100 ps
4419 16:43:54.348691 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4420 16:43:54.352192 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 16:43:54.355642 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 16:43:54.359249 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4423 16:43:54.361886 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4424 16:43:54.365373 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 16:43:54.368753
4426 16:43:54.372170 CA PerBit enable=1, Macro0, CA PI delay=33
4427 16:43:54.372284
4428 16:43:54.375132 [CBTSetCACLKResult] CA Dly = 33
4429 16:43:54.375239 CS Dly: 4 (0~35)
4430 16:43:54.375346 ==
4431 16:43:54.378644 Dram Type= 6, Freq= 0, CH_1, rank 1
4432 16:43:54.382042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 16:43:54.382162 ==
4434 16:43:54.388821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4435 16:43:54.395533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4436 16:43:54.398563 [CA 0] Center 35 (5~66) winsize 62
4437 16:43:54.401627 [CA 1] Center 36 (6~66) winsize 61
4438 16:43:54.405211 [CA 2] Center 34 (4~65) winsize 62
4439 16:43:54.408690 [CA 3] Center 34 (3~65) winsize 63
4440 16:43:54.411712 [CA 4] Center 34 (3~65) winsize 63
4441 16:43:54.415169 [CA 5] Center 34 (3~65) winsize 63
4442 16:43:54.415305
4443 16:43:54.418140 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4444 16:43:54.418253
4445 16:43:54.421789 [CATrainingPosCal] consider 2 rank data
4446 16:43:54.424742 u2DelayCellTimex100 = 270/100 ps
4447 16:43:54.428219 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4448 16:43:54.431243 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4449 16:43:54.434899 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4450 16:43:54.441470 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4451 16:43:54.444465 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4452 16:43:54.447980 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4453 16:43:54.448084
4454 16:43:54.450827 CA PerBit enable=1, Macro0, CA PI delay=33
4455 16:43:54.450929
4456 16:43:54.454634 [CBTSetCACLKResult] CA Dly = 33
4457 16:43:54.454746 CS Dly: 4 (0~36)
4458 16:43:54.454851
4459 16:43:54.457508 ----->DramcWriteLeveling(PI) begin...
4460 16:43:54.461217 ==
4461 16:43:54.461325 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 16:43:54.467771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 16:43:54.467856 ==
4464 16:43:54.471280 Write leveling (Byte 0): 28 => 28
4465 16:43:54.474602 Write leveling (Byte 1): 28 => 28
4466 16:43:54.477563 DramcWriteLeveling(PI) end<-----
4467 16:43:54.477676
4468 16:43:54.477772 ==
4469 16:43:54.480935 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 16:43:54.484317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 16:43:54.484425 ==
4472 16:43:54.487775 [Gating] SW mode calibration
4473 16:43:54.494199 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4474 16:43:54.497811 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4475 16:43:54.503966 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 16:43:54.507601 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 16:43:54.510539 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 16:43:54.517298 0 9 12 | B1->B0 | 3232 3030 | 1 0 | (0 0) (1 0)
4479 16:43:54.520360 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 16:43:54.526950 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 16:43:54.530572 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 16:43:54.533678 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 16:43:54.540288 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 16:43:54.543789 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 16:43:54.546898 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 16:43:54.553415 0 10 12 | B1->B0 | 3333 3838 | 1 0 | (0 0) (0 0)
4487 16:43:54.556925 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 16:43:54.560263 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 16:43:54.564009 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 16:43:54.570044 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 16:43:54.573853 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 16:43:54.576896 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 16:43:54.583121 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 16:43:54.586646 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4495 16:43:54.589893 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 16:43:54.596662 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 16:43:54.599673 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 16:43:54.603330 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 16:43:54.609975 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 16:43:54.613005 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 16:43:54.616074 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 16:43:54.622600 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 16:43:54.626250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 16:43:54.629786 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 16:43:54.636324 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 16:43:54.639356 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 16:43:54.642929 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 16:43:54.649356 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 16:43:54.652434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 16:43:54.656076 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4511 16:43:54.658900 Total UI for P1: 0, mck2ui 16
4512 16:43:54.662577 best dqsien dly found for B1: ( 0, 13, 10)
4513 16:43:54.669344 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 16:43:54.672251 Total UI for P1: 0, mck2ui 16
4515 16:43:54.675976 best dqsien dly found for B0: ( 0, 13, 12)
4516 16:43:54.679150 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4517 16:43:54.682618 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4518 16:43:54.682726
4519 16:43:54.685547 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4520 16:43:54.689006 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4521 16:43:54.692478 [Gating] SW calibration Done
4522 16:43:54.692584 ==
4523 16:43:54.695852 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 16:43:54.698827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 16:43:54.698934 ==
4526 16:43:54.702127 RX Vref Scan: 0
4527 16:43:54.702204
4528 16:43:54.705735 RX Vref 0 -> 0, step: 1
4529 16:43:54.705850
4530 16:43:54.705953 RX Delay -230 -> 252, step: 16
4531 16:43:54.712385 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4532 16:43:54.715253 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4533 16:43:54.718910 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4534 16:43:54.721933 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4535 16:43:54.728633 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4536 16:43:54.731647 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4537 16:43:54.735149 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4538 16:43:54.738242 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4539 16:43:54.744805 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4540 16:43:54.748445 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4541 16:43:54.751934 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4542 16:43:54.754915 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4543 16:43:54.761590 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4544 16:43:54.764662 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4545 16:43:54.768335 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4546 16:43:54.771721 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4547 16:43:54.771797 ==
4548 16:43:54.774648 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 16:43:54.782001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 16:43:54.782095 ==
4551 16:43:54.782164 DQS Delay:
4552 16:43:54.784639 DQS0 = 0, DQS1 = 0
4553 16:43:54.784734 DQM Delay:
4554 16:43:54.784807 DQM0 = 47, DQM1 = 36
4555 16:43:54.788037 DQ Delay:
4556 16:43:54.791413 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4557 16:43:54.794791 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4558 16:43:54.798106 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4559 16:43:54.800919 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4560 16:43:54.801026
4561 16:43:54.801119
4562 16:43:54.801208 ==
4563 16:43:54.804409 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 16:43:54.807775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 16:43:54.807857 ==
4566 16:43:54.807922
4567 16:43:54.807981
4568 16:43:54.810792 TX Vref Scan disable
4569 16:43:54.814376 == TX Byte 0 ==
4570 16:43:54.817935 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 16:43:54.821017 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 16:43:54.824037 == TX Byte 1 ==
4573 16:43:54.827671 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4574 16:43:54.830714 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4575 16:43:54.830800 ==
4576 16:43:54.834280 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 16:43:54.840810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 16:43:54.840926 ==
4579 16:43:54.841022
4580 16:43:54.841113
4581 16:43:54.841202 TX Vref Scan disable
4582 16:43:54.844385 == TX Byte 0 ==
4583 16:43:54.848081 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4584 16:43:54.854606 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4585 16:43:54.854710 == TX Byte 1 ==
4586 16:43:54.858205 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4587 16:43:54.864832 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4588 16:43:54.864917
4589 16:43:54.864984 [DATLAT]
4590 16:43:54.865058 Freq=600, CH1 RK0
4591 16:43:54.865120
4592 16:43:54.867754 DATLAT Default: 0x9
4593 16:43:54.867826 0, 0xFFFF, sum = 0
4594 16:43:54.871320 1, 0xFFFF, sum = 0
4595 16:43:54.874238 2, 0xFFFF, sum = 0
4596 16:43:54.874324 3, 0xFFFF, sum = 0
4597 16:43:54.877779 4, 0xFFFF, sum = 0
4598 16:43:54.877850 5, 0xFFFF, sum = 0
4599 16:43:54.881156 6, 0xFFFF, sum = 0
4600 16:43:54.881239 7, 0xFFFF, sum = 0
4601 16:43:54.884196 8, 0x0, sum = 1
4602 16:43:54.884272 9, 0x0, sum = 2
4603 16:43:54.887631 10, 0x0, sum = 3
4604 16:43:54.887710 11, 0x0, sum = 4
4605 16:43:54.887782 best_step = 9
4606 16:43:54.887844
4607 16:43:54.890564 ==
4608 16:43:54.893960 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 16:43:54.897312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 16:43:54.897390 ==
4611 16:43:54.897459 RX Vref Scan: 1
4612 16:43:54.897519
4613 16:43:54.900784 RX Vref 0 -> 0, step: 1
4614 16:43:54.900858
4615 16:43:54.904178 RX Delay -195 -> 252, step: 8
4616 16:43:54.904253
4617 16:43:54.907103 Set Vref, RX VrefLevel [Byte0]: 49
4618 16:43:54.910583 [Byte1]: 53
4619 16:43:54.910659
4620 16:43:54.913839 Final RX Vref Byte 0 = 49 to rank0
4621 16:43:54.917367 Final RX Vref Byte 1 = 53 to rank0
4622 16:43:54.920348 Final RX Vref Byte 0 = 49 to rank1
4623 16:43:54.923887 Final RX Vref Byte 1 = 53 to rank1==
4624 16:43:54.927029 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 16:43:54.930692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 16:43:54.933687 ==
4627 16:43:54.933773 DQS Delay:
4628 16:43:54.933840 DQS0 = 0, DQS1 = 0
4629 16:43:54.937395 DQM Delay:
4630 16:43:54.937482 DQM0 = 48, DQM1 = 37
4631 16:43:54.940423 DQ Delay:
4632 16:43:54.940508 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4633 16:43:54.944000 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =40
4634 16:43:54.946871 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4635 16:43:54.950644 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =48
4636 16:43:54.950750
4637 16:43:54.953604
4638 16:43:54.959981 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4639 16:43:54.963632 CH1 RK0: MR19=808, MR18=4B31
4640 16:43:54.970128 CH1_RK0: MR19=0x808, MR18=0x4B31, DQSOSC=395, MR23=63, INC=168, DEC=112
4641 16:43:54.970249
4642 16:43:54.973164 ----->DramcWriteLeveling(PI) begin...
4643 16:43:54.973272 ==
4644 16:43:54.976751 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 16:43:54.979808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 16:43:54.979911 ==
4647 16:43:54.983336 Write leveling (Byte 0): 30 => 30
4648 16:43:54.986245 Write leveling (Byte 1): 30 => 30
4649 16:43:54.989975 DramcWriteLeveling(PI) end<-----
4650 16:43:54.990079
4651 16:43:54.990161 ==
4652 16:43:54.992731 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 16:43:54.996200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 16:43:54.996278 ==
4655 16:43:54.999678 [Gating] SW mode calibration
4656 16:43:55.006407 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4657 16:43:55.012877 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4658 16:43:55.016238 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4659 16:43:55.022860 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 16:43:55.025824 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 16:43:55.029566 0 9 12 | B1->B0 | 2f2f 3333 | 1 1 | (1 1) (1 1)
4662 16:43:55.036197 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4663 16:43:55.039079 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 16:43:55.042889 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 16:43:55.049617 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 16:43:55.052557 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 16:43:55.055687 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 16:43:55.062260 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4669 16:43:55.065732 0 10 12 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
4670 16:43:55.068767 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 16:43:55.075861 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 16:43:55.078905 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 16:43:55.082518 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 16:43:55.088988 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 16:43:55.091910 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 16:43:55.095410 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4677 16:43:55.101743 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4678 16:43:55.105181 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 16:43:55.108761 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 16:43:55.114785 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 16:43:55.118319 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 16:43:55.121780 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 16:43:55.128545 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 16:43:55.131472 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 16:43:55.135142 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 16:43:55.141773 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 16:43:55.144829 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 16:43:55.148477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 16:43:55.154856 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 16:43:55.157835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 16:43:55.161498 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 16:43:55.167858 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 16:43:55.171299 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4694 16:43:55.174299 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 16:43:55.178019 Total UI for P1: 0, mck2ui 16
4696 16:43:55.180950 best dqsien dly found for B0: ( 0, 13, 14)
4697 16:43:55.184504 Total UI for P1: 0, mck2ui 16
4698 16:43:55.187478 best dqsien dly found for B1: ( 0, 13, 12)
4699 16:43:55.191163 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4700 16:43:55.194075 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4701 16:43:55.194176
4702 16:43:55.201026 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4703 16:43:55.203873 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4704 16:43:55.203978 [Gating] SW calibration Done
4705 16:43:55.207291 ==
4706 16:43:55.210726 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 16:43:55.214175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 16:43:55.214254 ==
4709 16:43:55.214319 RX Vref Scan: 0
4710 16:43:55.214383
4711 16:43:55.217176 RX Vref 0 -> 0, step: 1
4712 16:43:55.217274
4713 16:43:55.220555 RX Delay -230 -> 252, step: 16
4714 16:43:55.224053 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4715 16:43:55.226906 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4716 16:43:55.233639 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4717 16:43:55.237233 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4718 16:43:55.240240 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4719 16:43:55.243869 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4720 16:43:55.249950 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4721 16:43:55.253518 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4722 16:43:55.257054 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4723 16:43:55.260049 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4724 16:43:55.266788 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4725 16:43:55.270277 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4726 16:43:55.273168 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4727 16:43:55.276591 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4728 16:43:55.283124 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4729 16:43:55.286798 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4730 16:43:55.286937 ==
4731 16:43:55.289875 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 16:43:55.293003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 16:43:55.293152 ==
4734 16:43:55.296666 DQS Delay:
4735 16:43:55.296769 DQS0 = 0, DQS1 = 0
4736 16:43:55.296864 DQM Delay:
4737 16:43:55.299676 DQM0 = 45, DQM1 = 40
4738 16:43:55.299796 DQ Delay:
4739 16:43:55.303171 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4740 16:43:55.306497 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4741 16:43:55.309489 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =33
4742 16:43:55.312943 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4743 16:43:55.313088
4744 16:43:55.313180
4745 16:43:55.313274 ==
4746 16:43:55.316238 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 16:43:55.322631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 16:43:55.322738 ==
4749 16:43:55.322832
4750 16:43:55.322922
4751 16:43:55.323011 TX Vref Scan disable
4752 16:43:55.326631 == TX Byte 0 ==
4753 16:43:55.330049 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4754 16:43:55.336149 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4755 16:43:55.336265 == TX Byte 1 ==
4756 16:43:55.339634 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4757 16:43:55.346209 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4758 16:43:55.346302 ==
4759 16:43:55.349662 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 16:43:55.352721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 16:43:55.352838 ==
4762 16:43:55.352943
4763 16:43:55.353042
4764 16:43:55.356310 TX Vref Scan disable
4765 16:43:55.359343 == TX Byte 0 ==
4766 16:43:55.362788 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4767 16:43:55.366438 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4768 16:43:55.369428 == TX Byte 1 ==
4769 16:43:55.373059 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4770 16:43:55.376532 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4771 16:43:55.376621
4772 16:43:55.376689 [DATLAT]
4773 16:43:55.380007 Freq=600, CH1 RK1
4774 16:43:55.380092
4775 16:43:55.380161 DATLAT Default: 0x9
4776 16:43:55.382769 0, 0xFFFF, sum = 0
4777 16:43:55.386408 1, 0xFFFF, sum = 0
4778 16:43:55.386497 2, 0xFFFF, sum = 0
4779 16:43:55.389505 3, 0xFFFF, sum = 0
4780 16:43:55.389597 4, 0xFFFF, sum = 0
4781 16:43:55.392555 5, 0xFFFF, sum = 0
4782 16:43:55.392643 6, 0xFFFF, sum = 0
4783 16:43:55.396201 7, 0xFFFF, sum = 0
4784 16:43:55.396292 8, 0x0, sum = 1
4785 16:43:55.399227 9, 0x0, sum = 2
4786 16:43:55.399335 10, 0x0, sum = 3
4787 16:43:55.399441 11, 0x0, sum = 4
4788 16:43:55.402932 best_step = 9
4789 16:43:55.403006
4790 16:43:55.403082 ==
4791 16:43:55.405929 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 16:43:55.409008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 16:43:55.409094 ==
4794 16:43:55.412341 RX Vref Scan: 0
4795 16:43:55.412429
4796 16:43:55.416087 RX Vref 0 -> 0, step: 1
4797 16:43:55.416171
4798 16:43:55.416236 RX Delay -195 -> 252, step: 8
4799 16:43:55.423646 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4800 16:43:55.426537 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4801 16:43:55.429909 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4802 16:43:55.433328 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4803 16:43:55.439961 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4804 16:43:55.443267 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4805 16:43:55.446570 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4806 16:43:55.450217 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4807 16:43:55.453241 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4808 16:43:55.460050 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4809 16:43:55.463159 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4810 16:43:55.466637 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4811 16:43:55.469625 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4812 16:43:55.476348 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4813 16:43:55.479760 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4814 16:43:55.483016 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4815 16:43:55.483112 ==
4816 16:43:55.486586 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 16:43:55.489882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 16:43:55.493190 ==
4819 16:43:55.493297 DQS Delay:
4820 16:43:55.493397 DQS0 = 0, DQS1 = 0
4821 16:43:55.496141 DQM Delay:
4822 16:43:55.496244 DQM0 = 45, DQM1 = 36
4823 16:43:55.499873 DQ Delay:
4824 16:43:55.502905 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4825 16:43:55.503004 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4826 16:43:55.506500 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4827 16:43:55.512537 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4828 16:43:55.512643
4829 16:43:55.512740
4830 16:43:55.519050 [DQSOSCAuto] RK1, (LSB)MR18= 0x3227, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4831 16:43:55.522578 CH1 RK1: MR19=808, MR18=3227
4832 16:43:55.529288 CH1_RK1: MR19=0x808, MR18=0x3227, DQSOSC=400, MR23=63, INC=163, DEC=109
4833 16:43:55.532200 [RxdqsGatingPostProcess] freq 600
4834 16:43:55.535515 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4835 16:43:55.538806 Pre-setting of DQS Precalculation
4836 16:43:55.545644 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4837 16:43:55.551890 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4838 16:43:55.558404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4839 16:43:55.558520
4840 16:43:55.558623
4841 16:43:55.562053 [Calibration Summary] 1200 Mbps
4842 16:43:55.565101 CH 0, Rank 0
4843 16:43:55.565202 SW Impedance : PASS
4844 16:43:55.568648 DUTY Scan : NO K
4845 16:43:55.568761 ZQ Calibration : PASS
4846 16:43:55.571525 Jitter Meter : NO K
4847 16:43:55.575195 CBT Training : PASS
4848 16:43:55.575301 Write leveling : PASS
4849 16:43:55.578303 RX DQS gating : PASS
4850 16:43:55.581324 RX DQ/DQS(RDDQC) : PASS
4851 16:43:55.581432 TX DQ/DQS : PASS
4852 16:43:55.584674 RX DATLAT : PASS
4853 16:43:55.588193 RX DQ/DQS(Engine): PASS
4854 16:43:55.588294 TX OE : NO K
4855 16:43:55.591776 All Pass.
4856 16:43:55.591874
4857 16:43:55.591964 CH 0, Rank 1
4858 16:43:55.594626 SW Impedance : PASS
4859 16:43:55.594722 DUTY Scan : NO K
4860 16:43:55.598390 ZQ Calibration : PASS
4861 16:43:55.601414 Jitter Meter : NO K
4862 16:43:55.601515 CBT Training : PASS
4863 16:43:55.604960 Write leveling : PASS
4864 16:43:55.607956 RX DQS gating : PASS
4865 16:43:55.608075 RX DQ/DQS(RDDQC) : PASS
4866 16:43:55.611625 TX DQ/DQS : PASS
4867 16:43:55.614833 RX DATLAT : PASS
4868 16:43:55.614906 RX DQ/DQS(Engine): PASS
4869 16:43:55.618350 TX OE : NO K
4870 16:43:55.618448 All Pass.
4871 16:43:55.618536
4872 16:43:55.621419 CH 1, Rank 0
4873 16:43:55.621515 SW Impedance : PASS
4874 16:43:55.624987 DUTY Scan : NO K
4875 16:43:55.627766 ZQ Calibration : PASS
4876 16:43:55.627858 Jitter Meter : NO K
4877 16:43:55.631532 CBT Training : PASS
4878 16:43:55.631631 Write leveling : PASS
4879 16:43:55.634725 RX DQS gating : PASS
4880 16:43:55.637924 RX DQ/DQS(RDDQC) : PASS
4881 16:43:55.638036 TX DQ/DQS : PASS
4882 16:43:55.641328 RX DATLAT : PASS
4883 16:43:55.644666 RX DQ/DQS(Engine): PASS
4884 16:43:55.644770 TX OE : NO K
4885 16:43:55.647517 All Pass.
4886 16:43:55.647618
4887 16:43:55.647720 CH 1, Rank 1
4888 16:43:55.650904 SW Impedance : PASS
4889 16:43:55.651002 DUTY Scan : NO K
4890 16:43:55.654506 ZQ Calibration : PASS
4891 16:43:55.657962 Jitter Meter : NO K
4892 16:43:55.658068 CBT Training : PASS
4893 16:43:55.660934 Write leveling : PASS
4894 16:43:55.664672 RX DQS gating : PASS
4895 16:43:55.664776 RX DQ/DQS(RDDQC) : PASS
4896 16:43:55.667534 TX DQ/DQS : PASS
4897 16:43:55.671087 RX DATLAT : PASS
4898 16:43:55.671161 RX DQ/DQS(Engine): PASS
4899 16:43:55.673969 TX OE : NO K
4900 16:43:55.674068 All Pass.
4901 16:43:55.674159
4902 16:43:55.677607 DramC Write-DBI off
4903 16:43:55.680603 PER_BANK_REFRESH: Hybrid Mode
4904 16:43:55.680708 TX_TRACKING: ON
4905 16:43:55.690872 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4906 16:43:55.694253 [FAST_K] Save calibration result to emmc
4907 16:43:55.697280 dramc_set_vcore_voltage set vcore to 662500
4908 16:43:55.700934 Read voltage for 933, 3
4909 16:43:55.701011 Vio18 = 0
4910 16:43:55.701073 Vcore = 662500
4911 16:43:55.704009 Vdram = 0
4912 16:43:55.704078 Vddq = 0
4913 16:43:55.704151 Vmddr = 0
4914 16:43:55.710610 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4915 16:43:55.713548 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4916 16:43:55.717163 MEM_TYPE=3, freq_sel=17
4917 16:43:55.720153 sv_algorithm_assistance_LP4_1600
4918 16:43:55.723777 ============ PULL DRAM RESETB DOWN ============
4919 16:43:55.726696 ========== PULL DRAM RESETB DOWN end =========
4920 16:43:55.733620 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4921 16:43:55.736545 ===================================
4922 16:43:55.739949 LPDDR4 DRAM CONFIGURATION
4923 16:43:55.743373 ===================================
4924 16:43:55.743477 EX_ROW_EN[0] = 0x0
4925 16:43:55.746859 EX_ROW_EN[1] = 0x0
4926 16:43:55.746962 LP4Y_EN = 0x0
4927 16:43:55.750115 WORK_FSP = 0x0
4928 16:43:55.750214 WL = 0x3
4929 16:43:55.753146 RL = 0x3
4930 16:43:55.753247 BL = 0x2
4931 16:43:55.756880 RPST = 0x0
4932 16:43:55.757038 RD_PRE = 0x0
4933 16:43:55.760296 WR_PRE = 0x1
4934 16:43:55.760409 WR_PST = 0x0
4935 16:43:55.763044 DBI_WR = 0x0
4936 16:43:55.766573 DBI_RD = 0x0
4937 16:43:55.766656 OTF = 0x1
4938 16:43:55.769635 ===================================
4939 16:43:55.773224 ===================================
4940 16:43:55.773309 ANA top config
4941 16:43:55.776321 ===================================
4942 16:43:55.779844 DLL_ASYNC_EN = 0
4943 16:43:55.782863 ALL_SLAVE_EN = 1
4944 16:43:55.786586 NEW_RANK_MODE = 1
4945 16:43:55.789637 DLL_IDLE_MODE = 1
4946 16:43:55.789751 LP45_APHY_COMB_EN = 1
4947 16:43:55.793037 TX_ODT_DIS = 1
4948 16:43:55.796376 NEW_8X_MODE = 1
4949 16:43:55.799810 ===================================
4950 16:43:55.802823 ===================================
4951 16:43:55.806067 data_rate = 1866
4952 16:43:55.809622 CKR = 1
4953 16:43:55.809733 DQ_P2S_RATIO = 8
4954 16:43:55.812554 ===================================
4955 16:43:55.816297 CA_P2S_RATIO = 8
4956 16:43:55.819243 DQ_CA_OPEN = 0
4957 16:43:55.822844 DQ_SEMI_OPEN = 0
4958 16:43:55.825832 CA_SEMI_OPEN = 0
4959 16:43:55.829449 CA_FULL_RATE = 0
4960 16:43:55.829534 DQ_CKDIV4_EN = 1
4961 16:43:55.832370 CA_CKDIV4_EN = 1
4962 16:43:55.835849 CA_PREDIV_EN = 0
4963 16:43:55.839346 PH8_DLY = 0
4964 16:43:55.842266 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4965 16:43:55.845674 DQ_AAMCK_DIV = 4
4966 16:43:55.845760 CA_AAMCK_DIV = 4
4967 16:43:55.849099 CA_ADMCK_DIV = 4
4968 16:43:55.852535 DQ_TRACK_CA_EN = 0
4969 16:43:55.855944 CA_PICK = 933
4970 16:43:55.858856 CA_MCKIO = 933
4971 16:43:55.862027 MCKIO_SEMI = 0
4972 16:43:55.865517 PLL_FREQ = 3732
4973 16:43:55.868889 DQ_UI_PI_RATIO = 32
4974 16:43:55.868975 CA_UI_PI_RATIO = 0
4975 16:43:55.872254 ===================================
4976 16:43:55.875250 ===================================
4977 16:43:55.878936 memory_type:LPDDR4
4978 16:43:55.881885 GP_NUM : 10
4979 16:43:55.881969 SRAM_EN : 1
4980 16:43:55.885388 MD32_EN : 0
4981 16:43:55.888405 ===================================
4982 16:43:55.891802 [ANA_INIT] >>>>>>>>>>>>>>
4983 16:43:55.895378 <<<<<< [CONFIGURE PHASE]: ANA_TX
4984 16:43:55.898400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4985 16:43:55.901533 ===================================
4986 16:43:55.901618 data_rate = 1866,PCW = 0X8f00
4987 16:43:55.905291 ===================================
4988 16:43:55.908273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4989 16:43:55.915108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4990 16:43:55.921662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 16:43:55.924727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4992 16:43:55.928233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4993 16:43:55.931188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4994 16:43:55.934805 [ANA_INIT] flow start
4995 16:43:55.938344 [ANA_INIT] PLL >>>>>>>>
4996 16:43:55.938435 [ANA_INIT] PLL <<<<<<<<
4997 16:43:55.941262 [ANA_INIT] MIDPI >>>>>>>>
4998 16:43:55.944790 [ANA_INIT] MIDPI <<<<<<<<
4999 16:43:55.944893 [ANA_INIT] DLL >>>>>>>>
5000 16:43:55.947646 [ANA_INIT] flow end
5001 16:43:55.951591 ============ LP4 DIFF to SE enter ============
5002 16:43:55.954405 ============ LP4 DIFF to SE exit ============
5003 16:43:55.957912 [ANA_INIT] <<<<<<<<<<<<<
5004 16:43:55.961397 [Flow] Enable top DCM control >>>>>
5005 16:43:55.964648 [Flow] Enable top DCM control <<<<<
5006 16:43:55.967767 Enable DLL master slave shuffle
5007 16:43:55.974355 ==============================================================
5008 16:43:55.974444 Gating Mode config
5009 16:43:55.980729 ==============================================================
5010 16:43:55.984394 Config description:
5011 16:43:55.990829 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5012 16:43:55.997378 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5013 16:43:56.003886 SELPH_MODE 0: By rank 1: By Phase
5014 16:43:56.010976 ==============================================================
5015 16:43:56.014017 GAT_TRACK_EN = 1
5016 16:43:56.014097 RX_GATING_MODE = 2
5017 16:43:56.017098 RX_GATING_TRACK_MODE = 2
5018 16:43:56.020744 SELPH_MODE = 1
5019 16:43:56.023745 PICG_EARLY_EN = 1
5020 16:43:56.027421 VALID_LAT_VALUE = 1
5021 16:43:56.033756 ==============================================================
5022 16:43:56.036720 Enter into Gating configuration >>>>
5023 16:43:56.040298 Exit from Gating configuration <<<<
5024 16:43:56.043341 Enter into DVFS_PRE_config >>>>>
5025 16:43:56.053377 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5026 16:43:56.056797 Exit from DVFS_PRE_config <<<<<
5027 16:43:56.060000 Enter into PICG configuration >>>>
5028 16:43:56.063542 Exit from PICG configuration <<<<
5029 16:43:56.066643 [RX_INPUT] configuration >>>>>
5030 16:43:56.069942 [RX_INPUT] configuration <<<<<
5031 16:43:56.073482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5032 16:43:56.079672 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5033 16:43:56.086680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 16:43:56.093156 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 16:43:56.096131 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 16:43:56.102793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 16:43:56.106472 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5038 16:43:56.112685 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5039 16:43:56.116262 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5040 16:43:56.119385 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5041 16:43:56.122957 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5042 16:43:56.129632 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5043 16:43:56.132632 ===================================
5044 16:43:56.136243 LPDDR4 DRAM CONFIGURATION
5045 16:43:56.139374 ===================================
5046 16:43:56.139458 EX_ROW_EN[0] = 0x0
5047 16:43:56.142382 EX_ROW_EN[1] = 0x0
5048 16:43:56.142466 LP4Y_EN = 0x0
5049 16:43:56.145993 WORK_FSP = 0x0
5050 16:43:56.146077 WL = 0x3
5051 16:43:56.149036 RL = 0x3
5052 16:43:56.149119 BL = 0x2
5053 16:43:56.152616 RPST = 0x0
5054 16:43:56.152700 RD_PRE = 0x0
5055 16:43:56.156051 WR_PRE = 0x1
5056 16:43:56.156169 WR_PST = 0x0
5057 16:43:56.159011 DBI_WR = 0x0
5058 16:43:56.162360 DBI_RD = 0x0
5059 16:43:56.162443 OTF = 0x1
5060 16:43:56.165916 ===================================
5061 16:43:56.169193 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5062 16:43:56.172310 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5063 16:43:56.179074 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 16:43:56.181969 ===================================
5065 16:43:56.185305 LPDDR4 DRAM CONFIGURATION
5066 16:43:56.188584 ===================================
5067 16:43:56.188670 EX_ROW_EN[0] = 0x10
5068 16:43:56.192116 EX_ROW_EN[1] = 0x0
5069 16:43:56.192201 LP4Y_EN = 0x0
5070 16:43:56.195645 WORK_FSP = 0x0
5071 16:43:56.195730 WL = 0x3
5072 16:43:56.198633 RL = 0x3
5073 16:43:56.198717 BL = 0x2
5074 16:43:56.202067 RPST = 0x0
5075 16:43:56.202152 RD_PRE = 0x0
5076 16:43:56.205710 WR_PRE = 0x1
5077 16:43:56.205794 WR_PST = 0x0
5078 16:43:56.208535 DBI_WR = 0x0
5079 16:43:56.212166 DBI_RD = 0x0
5080 16:43:56.212249 OTF = 0x1
5081 16:43:56.215580 ===================================
5082 16:43:56.221495 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5083 16:43:56.225243 nWR fixed to 30
5084 16:43:56.228377 [ModeRegInit_LP4] CH0 RK0
5085 16:43:56.228465 [ModeRegInit_LP4] CH0 RK1
5086 16:43:56.232025 [ModeRegInit_LP4] CH1 RK0
5087 16:43:56.235507 [ModeRegInit_LP4] CH1 RK1
5088 16:43:56.235591 match AC timing 9
5089 16:43:56.242162 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5090 16:43:56.245101 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5091 16:43:56.248603 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5092 16:43:56.255211 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5093 16:43:56.258106 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5094 16:43:56.258197 ==
5095 16:43:56.261542 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 16:43:56.265114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 16:43:56.265190 ==
5098 16:43:56.271960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 16:43:56.278399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5100 16:43:56.281840 [CA 0] Center 37 (7~68) winsize 62
5101 16:43:56.285095 [CA 1] Center 37 (7~68) winsize 62
5102 16:43:56.288075 [CA 2] Center 34 (4~65) winsize 62
5103 16:43:56.291471 [CA 3] Center 35 (5~65) winsize 61
5104 16:43:56.294916 [CA 4] Center 33 (3~64) winsize 62
5105 16:43:56.297876 [CA 5] Center 33 (4~63) winsize 60
5106 16:43:56.297958
5107 16:43:56.301266 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5108 16:43:56.301347
5109 16:43:56.304599 [CATrainingPosCal] consider 1 rank data
5110 16:43:56.307725 u2DelayCellTimex100 = 270/100 ps
5111 16:43:56.311288 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5112 16:43:56.314331 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5113 16:43:56.317783 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5114 16:43:56.321408 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5115 16:43:56.327425 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5116 16:43:56.331147 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5117 16:43:56.331256
5118 16:43:56.334163 CA PerBit enable=1, Macro0, CA PI delay=33
5119 16:43:56.334244
5120 16:43:56.337738 [CBTSetCACLKResult] CA Dly = 33
5121 16:43:56.337845 CS Dly: 7 (0~38)
5122 16:43:56.337928 ==
5123 16:43:56.340726 Dram Type= 6, Freq= 0, CH_0, rank 1
5124 16:43:56.347426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 16:43:56.347509 ==
5126 16:43:56.350992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5127 16:43:56.357586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5128 16:43:56.360612 [CA 0] Center 37 (7~68) winsize 62
5129 16:43:56.364180 [CA 1] Center 37 (7~68) winsize 62
5130 16:43:56.367093 [CA 2] Center 34 (4~65) winsize 62
5131 16:43:56.370356 [CA 3] Center 34 (4~65) winsize 62
5132 16:43:56.374217 [CA 4] Center 33 (3~64) winsize 62
5133 16:43:56.377274 [CA 5] Center 32 (2~63) winsize 62
5134 16:43:56.377369
5135 16:43:56.380617 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5136 16:43:56.380706
5137 16:43:56.383548 [CATrainingPosCal] consider 2 rank data
5138 16:43:56.386920 u2DelayCellTimex100 = 270/100 ps
5139 16:43:56.390465 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5140 16:43:56.396706 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5141 16:43:56.400097 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5142 16:43:56.403564 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5143 16:43:56.406826 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5144 16:43:56.410159 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5145 16:43:56.410257
5146 16:43:56.413640 CA PerBit enable=1, Macro0, CA PI delay=33
5147 16:43:56.413777
5148 16:43:56.416571 [CBTSetCACLKResult] CA Dly = 33
5149 16:43:56.420125 CS Dly: 7 (0~39)
5150 16:43:56.420207
5151 16:43:56.423582 ----->DramcWriteLeveling(PI) begin...
5152 16:43:56.423665 ==
5153 16:43:56.426663 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 16:43:56.430296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 16:43:56.430378 ==
5156 16:43:56.433308 Write leveling (Byte 0): 33 => 33
5157 16:43:56.436336 Write leveling (Byte 1): 30 => 30
5158 16:43:56.439956 DramcWriteLeveling(PI) end<-----
5159 16:43:56.440042
5160 16:43:56.440107 ==
5161 16:43:56.442983 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 16:43:56.446672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 16:43:56.446755 ==
5164 16:43:56.449680 [Gating] SW mode calibration
5165 16:43:56.456307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5166 16:43:56.462840 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5167 16:43:56.466408 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5168 16:43:56.469341 0 14 4 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
5169 16:43:56.476008 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 16:43:56.479536 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 16:43:56.482658 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 16:43:56.489746 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 16:43:56.492753 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 16:43:56.496050 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
5175 16:43:56.502754 0 15 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
5176 16:43:56.506174 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 16:43:56.508895 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 16:43:56.515988 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 16:43:56.518745 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 16:43:56.522206 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 16:43:56.528700 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 16:43:56.532314 0 15 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5183 16:43:56.535265 1 0 0 | B1->B0 | 3232 4545 | 1 0 | (0 0) (0 0)
5184 16:43:56.541926 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 16:43:56.545519 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 16:43:56.548400 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 16:43:56.555119 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 16:43:56.558730 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 16:43:56.561730 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 16:43:56.568488 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5191 16:43:56.571394 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5192 16:43:56.574971 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5193 16:43:56.581757 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 16:43:56.584665 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 16:43:56.588076 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 16:43:56.595033 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 16:43:56.598243 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 16:43:56.601592 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 16:43:56.607838 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 16:43:56.611190 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 16:43:56.614457 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 16:43:56.621593 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 16:43:56.624834 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 16:43:56.628157 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 16:43:56.634899 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5206 16:43:56.637874 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5207 16:43:56.641604 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5208 16:43:56.644620 Total UI for P1: 0, mck2ui 16
5209 16:43:56.648151 best dqsien dly found for B0: ( 1, 2, 26)
5210 16:43:56.654750 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 16:43:56.654836 Total UI for P1: 0, mck2ui 16
5212 16:43:56.661284 best dqsien dly found for B1: ( 1, 3, 0)
5213 16:43:56.664395 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5214 16:43:56.667443 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5215 16:43:56.667526
5216 16:43:56.670982 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5217 16:43:56.674055 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5218 16:43:56.677634 [Gating] SW calibration Done
5219 16:43:56.677718 ==
5220 16:43:56.680604 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 16:43:56.684276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 16:43:56.684360 ==
5223 16:43:56.687305 RX Vref Scan: 0
5224 16:43:56.687418
5225 16:43:56.687497 RX Vref 0 -> 0, step: 1
5226 16:43:56.687559
5227 16:43:56.690815 RX Delay -80 -> 252, step: 8
5228 16:43:56.693695 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5229 16:43:56.700823 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5230 16:43:56.704066 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5231 16:43:56.707026 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5232 16:43:56.710291 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5233 16:43:56.713634 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5234 16:43:56.717022 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5235 16:43:56.723643 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5236 16:43:56.726919 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5237 16:43:56.730269 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5238 16:43:56.733573 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5239 16:43:56.737034 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5240 16:43:56.743752 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5241 16:43:56.746641 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5242 16:43:56.750204 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5243 16:43:56.753244 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5244 16:43:56.753366 ==
5245 16:43:56.756377 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 16:43:56.762976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 16:43:56.763068 ==
5248 16:43:56.763151 DQS Delay:
5249 16:43:56.763213 DQS0 = 0, DQS1 = 0
5250 16:43:56.766738 DQM Delay:
5251 16:43:56.766823 DQM0 = 97, DQM1 = 87
5252 16:43:56.769673 DQ Delay:
5253 16:43:56.773368 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5254 16:43:56.776298 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5255 16:43:56.779878 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5256 16:43:56.782858 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5257 16:43:56.782941
5258 16:43:56.783006
5259 16:43:56.783092 ==
5260 16:43:56.786628 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 16:43:56.789462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 16:43:56.789585 ==
5263 16:43:56.789687
5264 16:43:56.789777
5265 16:43:56.792765 TX Vref Scan disable
5266 16:43:56.792878 == TX Byte 0 ==
5267 16:43:56.799363 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5268 16:43:56.802880 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5269 16:43:56.803009 == TX Byte 1 ==
5270 16:43:56.809300 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5271 16:43:56.812569 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5272 16:43:56.812680 ==
5273 16:43:56.815953 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 16:43:56.819484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 16:43:56.819597 ==
5276 16:43:56.822247
5277 16:43:56.822433
5278 16:43:56.822572 TX Vref Scan disable
5279 16:43:56.825649 == TX Byte 0 ==
5280 16:43:56.829189 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5281 16:43:56.835498 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5282 16:43:56.835621 == TX Byte 1 ==
5283 16:43:56.838905 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5284 16:43:56.845745 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5285 16:43:56.845834
5286 16:43:56.845903 [DATLAT]
5287 16:43:56.845966 Freq=933, CH0 RK0
5288 16:43:56.846026
5289 16:43:56.849023 DATLAT Default: 0xd
5290 16:43:56.849135 0, 0xFFFF, sum = 0
5291 16:43:56.852542 1, 0xFFFF, sum = 0
5292 16:43:56.855642 2, 0xFFFF, sum = 0
5293 16:43:56.855726 3, 0xFFFF, sum = 0
5294 16:43:56.858713 4, 0xFFFF, sum = 0
5295 16:43:56.858815 5, 0xFFFF, sum = 0
5296 16:43:56.862323 6, 0xFFFF, sum = 0
5297 16:43:56.862396 7, 0xFFFF, sum = 0
5298 16:43:56.865283 8, 0xFFFF, sum = 0
5299 16:43:56.865388 9, 0xFFFF, sum = 0
5300 16:43:56.868974 10, 0x0, sum = 1
5301 16:43:56.869081 11, 0x0, sum = 2
5302 16:43:56.872074 12, 0x0, sum = 3
5303 16:43:56.872150 13, 0x0, sum = 4
5304 16:43:56.872212 best_step = 11
5305 16:43:56.875235
5306 16:43:56.875307 ==
5307 16:43:56.878757 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 16:43:56.881735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 16:43:56.881835 ==
5310 16:43:56.881925 RX Vref Scan: 1
5311 16:43:56.882013
5312 16:43:56.885647 RX Vref 0 -> 0, step: 1
5313 16:43:56.885721
5314 16:43:56.888576 RX Delay -61 -> 252, step: 4
5315 16:43:56.888649
5316 16:43:56.891625 Set Vref, RX VrefLevel [Byte0]: 59
5317 16:43:56.895316 [Byte1]: 49
5318 16:43:56.898267
5319 16:43:56.898351 Final RX Vref Byte 0 = 59 to rank0
5320 16:43:56.902040 Final RX Vref Byte 1 = 49 to rank0
5321 16:43:56.905200 Final RX Vref Byte 0 = 59 to rank1
5322 16:43:56.908320 Final RX Vref Byte 1 = 49 to rank1==
5323 16:43:56.911398 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 16:43:56.918065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 16:43:56.918154 ==
5326 16:43:56.918221 DQS Delay:
5327 16:43:56.921541 DQS0 = 0, DQS1 = 0
5328 16:43:56.921651 DQM Delay:
5329 16:43:56.921750 DQM0 = 96, DQM1 = 86
5330 16:43:56.924480 DQ Delay:
5331 16:43:56.928199 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =90
5332 16:43:56.931412 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =104
5333 16:43:56.934728 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5334 16:43:56.937769 DQ12 =92, DQ13 =88, DQ14 =98, DQ15 =94
5335 16:43:56.937898
5336 16:43:56.937994
5337 16:43:56.944712 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5338 16:43:56.948052 CH0 RK0: MR19=505, MR18=2B11
5339 16:43:56.954825 CH0_RK0: MR19=0x505, MR18=0x2B11, DQSOSC=408, MR23=63, INC=65, DEC=43
5340 16:43:56.954993
5341 16:43:56.957511 ----->DramcWriteLeveling(PI) begin...
5342 16:43:56.957627 ==
5343 16:43:56.960874 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 16:43:56.964583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 16:43:56.964710 ==
5346 16:43:56.967676 Write leveling (Byte 0): 34 => 34
5347 16:43:56.970787 Write leveling (Byte 1): 29 => 29
5348 16:43:56.974494 DramcWriteLeveling(PI) end<-----
5349 16:43:56.974617
5350 16:43:56.974713 ==
5351 16:43:56.977525 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 16:43:56.981114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 16:43:56.984175 ==
5354 16:43:56.984290 [Gating] SW mode calibration
5355 16:43:56.994004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5356 16:43:56.997682 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5357 16:43:57.000526 0 14 0 | B1->B0 | 2b2b 3232 | 1 1 | (1 1) (0 0)
5358 16:43:57.007281 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5359 16:43:57.010331 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 16:43:57.014115 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 16:43:57.020582 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 16:43:57.023542 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 16:43:57.027169 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5364 16:43:57.033577 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
5365 16:43:57.036983 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5366 16:43:57.039947 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 16:43:57.046968 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 16:43:57.050003 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 16:43:57.053403 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 16:43:57.059889 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 16:43:57.063458 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 16:43:57.066962 0 15 28 | B1->B0 | 2323 3332 | 0 1 | (0 0) (1 1)
5373 16:43:57.073275 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5374 16:43:57.076319 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 16:43:57.079973 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 16:43:57.086552 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 16:43:57.089677 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 16:43:57.092743 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 16:43:57.099546 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 16:43:57.102542 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5381 16:43:57.105971 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 16:43:57.112593 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 16:43:57.116274 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 16:43:57.119343 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 16:43:57.126084 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 16:43:57.128979 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 16:43:57.132746 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 16:43:57.139146 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 16:43:57.142733 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 16:43:57.145545 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 16:43:57.152360 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 16:43:57.155869 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 16:43:57.158718 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 16:43:57.165338 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 16:43:57.168816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 16:43:57.172082 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5397 16:43:57.178732 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5398 16:43:57.181763 Total UI for P1: 0, mck2ui 16
5399 16:43:57.185585 best dqsien dly found for B0: ( 1, 2, 28)
5400 16:43:57.188626 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 16:43:57.192165 Total UI for P1: 0, mck2ui 16
5402 16:43:57.195248 best dqsien dly found for B1: ( 1, 3, 0)
5403 16:43:57.198262 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5404 16:43:57.201855 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5405 16:43:57.201958
5406 16:43:57.204955 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5407 16:43:57.208561 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5408 16:43:57.211572 [Gating] SW calibration Done
5409 16:43:57.211659 ==
5410 16:43:57.215316 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 16:43:57.218410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 16:43:57.221595 ==
5413 16:43:57.221704 RX Vref Scan: 0
5414 16:43:57.221807
5415 16:43:57.225356 RX Vref 0 -> 0, step: 1
5416 16:43:57.225459
5417 16:43:57.228433 RX Delay -80 -> 252, step: 8
5418 16:43:57.232324 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5419 16:43:57.234842 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5420 16:43:57.238185 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5421 16:43:57.241431 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5422 16:43:57.244829 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5423 16:43:57.251275 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5424 16:43:57.254756 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5425 16:43:57.258237 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5426 16:43:57.261166 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5427 16:43:57.264597 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5428 16:43:57.271003 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5429 16:43:57.274539 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5430 16:43:57.277850 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5431 16:43:57.280997 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5432 16:43:57.284020 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5433 16:43:57.287611 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5434 16:43:57.290655 ==
5435 16:43:57.294289 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 16:43:57.297365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 16:43:57.297467 ==
5438 16:43:57.297559 DQS Delay:
5439 16:43:57.301088 DQS0 = 0, DQS1 = 0
5440 16:43:57.301159 DQM Delay:
5441 16:43:57.304207 DQM0 = 97, DQM1 = 89
5442 16:43:57.304321 DQ Delay:
5443 16:43:57.307273 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5444 16:43:57.310391 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5445 16:43:57.313896 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5446 16:43:57.317016 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5447 16:43:57.317117
5448 16:43:57.317217
5449 16:43:57.317305 ==
5450 16:43:57.320655 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 16:43:57.323657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 16:43:57.323757 ==
5453 16:43:57.323858
5454 16:43:57.327367
5455 16:43:57.327478 TX Vref Scan disable
5456 16:43:57.330556 == TX Byte 0 ==
5457 16:43:57.333573 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5458 16:43:57.337218 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5459 16:43:57.340179 == TX Byte 1 ==
5460 16:43:57.343682 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5461 16:43:57.346934 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5462 16:43:57.347019 ==
5463 16:43:57.350344 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 16:43:57.356752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 16:43:57.356839 ==
5466 16:43:57.356906
5467 16:43:57.356969
5468 16:43:57.360098 TX Vref Scan disable
5469 16:43:57.360230 == TX Byte 0 ==
5470 16:43:57.366819 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5471 16:43:57.370222 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5472 16:43:57.370332 == TX Byte 1 ==
5473 16:43:57.376383 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5474 16:43:57.379789 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5475 16:43:57.379899
5476 16:43:57.379995 [DATLAT]
5477 16:43:57.383180 Freq=933, CH0 RK1
5478 16:43:57.383268
5479 16:43:57.383346 DATLAT Default: 0xb
5480 16:43:57.386496 0, 0xFFFF, sum = 0
5481 16:43:57.386579 1, 0xFFFF, sum = 0
5482 16:43:57.389455 2, 0xFFFF, sum = 0
5483 16:43:57.389536 3, 0xFFFF, sum = 0
5484 16:43:57.393351 4, 0xFFFF, sum = 0
5485 16:43:57.393469 5, 0xFFFF, sum = 0
5486 16:43:57.396163 6, 0xFFFF, sum = 0
5487 16:43:57.400038 7, 0xFFFF, sum = 0
5488 16:43:57.400113 8, 0xFFFF, sum = 0
5489 16:43:57.402983 9, 0xFFFF, sum = 0
5490 16:43:57.403123 10, 0x0, sum = 1
5491 16:43:57.403192 11, 0x0, sum = 2
5492 16:43:57.406593 12, 0x0, sum = 3
5493 16:43:57.406669 13, 0x0, sum = 4
5494 16:43:57.409673 best_step = 11
5495 16:43:57.409744
5496 16:43:57.409808 ==
5497 16:43:57.412792 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 16:43:57.416335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 16:43:57.416412 ==
5500 16:43:57.419317 RX Vref Scan: 0
5501 16:43:57.419389
5502 16:43:57.419469 RX Vref 0 -> 0, step: 1
5503 16:43:57.423074
5504 16:43:57.423190 RX Delay -61 -> 252, step: 4
5505 16:43:57.430264 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5506 16:43:57.433338 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5507 16:43:57.436923 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5508 16:43:57.439924 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5509 16:43:57.443630 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5510 16:43:57.449808 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5511 16:43:57.453366 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5512 16:43:57.456316 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5513 16:43:57.460051 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5514 16:43:57.463489 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5515 16:43:57.469833 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5516 16:43:57.473241 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5517 16:43:57.476110 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5518 16:43:57.479505 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5519 16:43:57.482953 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5520 16:43:57.489336 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5521 16:43:57.489464 ==
5522 16:43:57.492707 Dram Type= 6, Freq= 0, CH_0, rank 1
5523 16:43:57.495893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 16:43:57.496000 ==
5525 16:43:57.496110 DQS Delay:
5526 16:43:57.498991 DQS0 = 0, DQS1 = 0
5527 16:43:57.499104 DQM Delay:
5528 16:43:57.502689 DQM0 = 95, DQM1 = 86
5529 16:43:57.502798 DQ Delay:
5530 16:43:57.505728 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5531 16:43:57.509437 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5532 16:43:57.512506 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5533 16:43:57.515528 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5534 16:43:57.515661
5535 16:43:57.515767
5536 16:43:57.525811 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cfd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5537 16:43:57.525925 CH0 RK1: MR19=504, MR18=2CFD
5538 16:43:57.532034 CH0_RK1: MR19=0x504, MR18=0x2CFD, DQSOSC=408, MR23=63, INC=65, DEC=43
5539 16:43:57.535626 [RxdqsGatingPostProcess] freq 933
5540 16:43:57.542271 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5541 16:43:57.545185 best DQS0 dly(2T, 0.5T) = (0, 10)
5542 16:43:57.548775 best DQS1 dly(2T, 0.5T) = (0, 11)
5543 16:43:57.551899 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5544 16:43:57.554938 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5545 16:43:57.558634 best DQS0 dly(2T, 0.5T) = (0, 10)
5546 16:43:57.561570 best DQS1 dly(2T, 0.5T) = (0, 11)
5547 16:43:57.565021 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5548 16:43:57.568595 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5549 16:43:57.568685 Pre-setting of DQS Precalculation
5550 16:43:57.574931 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5551 16:43:57.575045 ==
5552 16:43:57.577896 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 16:43:57.581283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 16:43:57.581390 ==
5555 16:43:57.587820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5556 16:43:57.594913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5557 16:43:57.597898 [CA 0] Center 36 (6~67) winsize 62
5558 16:43:57.601229 [CA 1] Center 36 (6~67) winsize 62
5559 16:43:57.604729 [CA 2] Center 34 (4~64) winsize 61
5560 16:43:57.607791 [CA 3] Center 33 (3~64) winsize 62
5561 16:43:57.611445 [CA 4] Center 34 (4~64) winsize 61
5562 16:43:57.614414 [CA 5] Center 33 (3~64) winsize 62
5563 16:43:57.614496
5564 16:43:57.617442 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5565 16:43:57.617524
5566 16:43:57.621117 [CATrainingPosCal] consider 1 rank data
5567 16:43:57.624198 u2DelayCellTimex100 = 270/100 ps
5568 16:43:57.627821 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5569 16:43:57.630783 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 16:43:57.633975 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 16:43:57.637588 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 16:43:57.644269 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 16:43:57.647340 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5574 16:43:57.647414
5575 16:43:57.651025 CA PerBit enable=1, Macro0, CA PI delay=33
5576 16:43:57.651143
5577 16:43:57.654115 [CBTSetCACLKResult] CA Dly = 33
5578 16:43:57.654234 CS Dly: 6 (0~37)
5579 16:43:57.654299 ==
5580 16:43:57.657775 Dram Type= 6, Freq= 0, CH_1, rank 1
5581 16:43:57.663726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5582 16:43:57.663809 ==
5583 16:43:57.667394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5584 16:43:57.673894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5585 16:43:57.677206 [CA 0] Center 36 (6~67) winsize 62
5586 16:43:57.680607 [CA 1] Center 37 (7~67) winsize 61
5587 16:43:57.683508 [CA 2] Center 34 (3~65) winsize 63
5588 16:43:57.687022 [CA 3] Center 33 (3~64) winsize 62
5589 16:43:57.690423 [CA 4] Center 34 (3~65) winsize 63
5590 16:43:57.693298 [CA 5] Center 33 (3~64) winsize 62
5591 16:43:57.693381
5592 16:43:57.696781 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5593 16:43:57.696867
5594 16:43:57.700143 [CATrainingPosCal] consider 2 rank data
5595 16:43:57.703611 u2DelayCellTimex100 = 270/100 ps
5596 16:43:57.706997 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5597 16:43:57.709886 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5598 16:43:57.716628 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5599 16:43:57.719702 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5600 16:43:57.723344 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5601 16:43:57.726365 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5602 16:43:57.726447
5603 16:43:57.729888 CA PerBit enable=1, Macro0, CA PI delay=33
5604 16:43:57.729986
5605 16:43:57.732797 [CBTSetCACLKResult] CA Dly = 33
5606 16:43:57.732881 CS Dly: 7 (0~39)
5607 16:43:57.736548
5608 16:43:57.739580 ----->DramcWriteLeveling(PI) begin...
5609 16:43:57.739689 ==
5610 16:43:57.742748 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 16:43:57.746290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 16:43:57.746376 ==
5613 16:43:57.749374 Write leveling (Byte 0): 26 => 26
5614 16:43:57.752996 Write leveling (Byte 1): 31 => 31
5615 16:43:57.756086 DramcWriteLeveling(PI) end<-----
5616 16:43:57.756171
5617 16:43:57.756266 ==
5618 16:43:57.760005 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 16:43:57.762541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 16:43:57.762663 ==
5621 16:43:57.765986 [Gating] SW mode calibration
5622 16:43:57.772665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5623 16:43:57.779195 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5624 16:43:57.782161 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5625 16:43:57.785621 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 16:43:57.792591 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 16:43:57.795992 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 16:43:57.798882 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 16:43:57.805709 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 16:43:57.808617 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5631 16:43:57.812134 0 14 28 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
5632 16:43:57.819010 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5633 16:43:57.821962 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 16:43:57.825657 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 16:43:57.832307 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 16:43:57.835256 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 16:43:57.838931 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 16:43:57.845603 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5639 16:43:57.848733 0 15 28 | B1->B0 | 3030 3636 | 0 1 | (1 1) (0 0)
5640 16:43:57.851800 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5641 16:43:57.858499 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 16:43:57.862089 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 16:43:57.865603 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 16:43:57.871750 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 16:43:57.875926 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 16:43:57.878492 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5647 16:43:57.885132 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 16:43:57.888073 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5649 16:43:57.891585 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 16:43:57.898412 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 16:43:57.901245 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 16:43:57.904756 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 16:43:57.911042 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 16:43:57.914625 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 16:43:57.917913 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 16:43:57.924395 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 16:43:57.927485 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 16:43:57.931216 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 16:43:57.937703 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 16:43:57.940725 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 16:43:57.944395 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5662 16:43:57.951017 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5663 16:43:57.951155 Total UI for P1: 0, mck2ui 16
5664 16:43:57.957054 best dqsien dly found for B0: ( 1, 2, 20)
5665 16:43:57.960760 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5666 16:43:57.963838 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 16:43:57.967503 Total UI for P1: 0, mck2ui 16
5668 16:43:57.970740 best dqsien dly found for B1: ( 1, 2, 26)
5669 16:43:57.974131 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5670 16:43:57.976987 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5671 16:43:57.977169
5672 16:43:57.983755 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5673 16:43:57.986810 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5674 16:43:57.990220 [Gating] SW calibration Done
5675 16:43:57.990291 ==
5676 16:43:57.993814 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 16:43:57.996667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 16:43:57.996741 ==
5679 16:43:57.996803 RX Vref Scan: 0
5680 16:43:57.996860
5681 16:43:58.000333 RX Vref 0 -> 0, step: 1
5682 16:43:58.000400
5683 16:43:58.003391 RX Delay -80 -> 252, step: 8
5684 16:43:58.006852 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5685 16:43:58.009842 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5686 16:43:58.016759 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5687 16:43:58.019613 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5688 16:43:58.023218 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5689 16:43:58.026497 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5690 16:43:58.030060 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5691 16:43:58.033108 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5692 16:43:58.039872 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5693 16:43:58.042765 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5694 16:43:58.046377 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5695 16:43:58.049467 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5696 16:43:58.052594 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5697 16:43:58.059225 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5698 16:43:58.062381 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5699 16:43:58.066094 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5700 16:43:58.066191 ==
5701 16:43:58.069147 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 16:43:58.072169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 16:43:58.072238 ==
5704 16:43:58.076000 DQS Delay:
5705 16:43:58.076068 DQS0 = 0, DQS1 = 0
5706 16:43:58.078766 DQM Delay:
5707 16:43:58.078833 DQM0 = 101, DQM1 = 90
5708 16:43:58.078889 DQ Delay:
5709 16:43:58.082385 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5710 16:43:58.085524 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5711 16:43:58.089219 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5712 16:43:58.092317 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5713 16:43:58.095973
5714 16:43:58.096056
5715 16:43:58.096121 ==
5716 16:43:58.098819 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 16:43:58.102288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 16:43:58.102371 ==
5719 16:43:58.102438
5720 16:43:58.102498
5721 16:43:58.105782 TX Vref Scan disable
5722 16:43:58.105853 == TX Byte 0 ==
5723 16:43:58.112156 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5724 16:43:58.115650 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5725 16:43:58.115735 == TX Byte 1 ==
5726 16:43:58.122061 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5727 16:43:58.125394 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5728 16:43:58.125473 ==
5729 16:43:58.128338 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 16:43:58.131681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 16:43:58.131762 ==
5732 16:43:58.131832
5733 16:43:58.131892
5734 16:43:58.135210 TX Vref Scan disable
5735 16:43:58.138289 == TX Byte 0 ==
5736 16:43:58.141943 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5737 16:43:58.144965 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5738 16:43:58.148588 == TX Byte 1 ==
5739 16:43:58.151670 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5740 16:43:58.154767 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5741 16:43:58.157822
5742 16:43:58.157928 [DATLAT]
5743 16:43:58.158019 Freq=933, CH1 RK0
5744 16:43:58.158108
5745 16:43:58.161493 DATLAT Default: 0xd
5746 16:43:58.161589 0, 0xFFFF, sum = 0
5747 16:43:58.164540 1, 0xFFFF, sum = 0
5748 16:43:58.164611 2, 0xFFFF, sum = 0
5749 16:43:58.168439 3, 0xFFFF, sum = 0
5750 16:43:58.168542 4, 0xFFFF, sum = 0
5751 16:43:58.171335 5, 0xFFFF, sum = 0
5752 16:43:58.174491 6, 0xFFFF, sum = 0
5753 16:43:58.174597 7, 0xFFFF, sum = 0
5754 16:43:58.178176 8, 0xFFFF, sum = 0
5755 16:43:58.178279 9, 0xFFFF, sum = 0
5756 16:43:58.181155 10, 0x0, sum = 1
5757 16:43:58.181240 11, 0x0, sum = 2
5758 16:43:58.184307 12, 0x0, sum = 3
5759 16:43:58.184391 13, 0x0, sum = 4
5760 16:43:58.184458 best_step = 11
5761 16:43:58.184520
5762 16:43:58.187908 ==
5763 16:43:58.190976 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 16:43:58.194642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 16:43:58.194725 ==
5766 16:43:58.194790 RX Vref Scan: 1
5767 16:43:58.194851
5768 16:43:58.197753 RX Vref 0 -> 0, step: 1
5769 16:43:58.197835
5770 16:43:58.201362 RX Delay -61 -> 252, step: 4
5771 16:43:58.201444
5772 16:43:58.204316 Set Vref, RX VrefLevel [Byte0]: 49
5773 16:43:58.207615 [Byte1]: 53
5774 16:43:58.207700
5775 16:43:58.211192 Final RX Vref Byte 0 = 49 to rank0
5776 16:43:58.214113 Final RX Vref Byte 1 = 53 to rank0
5777 16:43:58.217529 Final RX Vref Byte 0 = 49 to rank1
5778 16:43:58.221004 Final RX Vref Byte 1 = 53 to rank1==
5779 16:43:58.224542 Dram Type= 6, Freq= 0, CH_1, rank 0
5780 16:43:58.227353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 16:43:58.230899 ==
5782 16:43:58.230992 DQS Delay:
5783 16:43:58.231064 DQS0 = 0, DQS1 = 0
5784 16:43:58.234427 DQM Delay:
5785 16:43:58.234529 DQM0 = 100, DQM1 = 93
5786 16:43:58.237722 DQ Delay:
5787 16:43:58.240620 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5788 16:43:58.243726 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =98
5789 16:43:58.247433 DQ8 =80, DQ9 =86, DQ10 =94, DQ11 =84
5790 16:43:58.250314 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =104
5791 16:43:58.250386
5792 16:43:58.250448
5793 16:43:58.257082 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5794 16:43:58.260398 CH1 RK0: MR19=505, MR18=1A09
5795 16:43:58.266911 CH1_RK0: MR19=0x505, MR18=0x1A09, DQSOSC=413, MR23=63, INC=63, DEC=42
5796 16:43:58.266994
5797 16:43:58.270499 ----->DramcWriteLeveling(PI) begin...
5798 16:43:58.270582 ==
5799 16:43:58.273614 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 16:43:58.277247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 16:43:58.277330 ==
5802 16:43:58.280213 Write leveling (Byte 0): 23 => 23
5803 16:43:58.283332 Write leveling (Byte 1): 27 => 27
5804 16:43:58.287241 DramcWriteLeveling(PI) end<-----
5805 16:43:58.287323
5806 16:43:58.287387 ==
5807 16:43:58.290034 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 16:43:58.293696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 16:43:58.296917 ==
5810 16:43:58.296994 [Gating] SW mode calibration
5811 16:43:58.306704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5812 16:43:58.310289 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5813 16:43:58.313246 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 16:43:58.320080 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 16:43:58.323474 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 16:43:58.326274 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 16:43:58.333113 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 16:43:58.336524 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 16:43:58.339899 0 14 24 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
5820 16:43:58.346302 0 14 28 | B1->B0 | 2b2b 2f2f | 0 1 | (1 0) (1 0)
5821 16:43:58.349225 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 16:43:58.352848 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 16:43:58.359510 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 16:43:58.362597 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 16:43:58.366206 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 16:43:58.373018 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 16:43:58.375964 0 15 24 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (0 0)
5828 16:43:58.379607 0 15 28 | B1->B0 | 3737 3131 | 1 1 | (1 1) (0 0)
5829 16:43:58.385739 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 16:43:58.389380 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 16:43:58.392350 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 16:43:58.399154 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 16:43:58.402165 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 16:43:58.405851 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 16:43:58.412037 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 16:43:58.415669 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5837 16:43:58.418620 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 16:43:58.425625 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 16:43:58.428627 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 16:43:58.432017 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 16:43:58.438466 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 16:43:58.441895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 16:43:58.445147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 16:43:58.451944 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 16:43:58.455335 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 16:43:58.458236 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 16:43:58.464866 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 16:43:58.468623 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 16:43:58.471639 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 16:43:58.478352 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 16:43:58.481385 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5852 16:43:58.484914 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5853 16:43:58.491565 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5854 16:43:58.494772 Total UI for P1: 0, mck2ui 16
5855 16:43:58.498217 best dqsien dly found for B1: ( 1, 2, 26)
5856 16:43:58.501322 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 16:43:58.504396 Total UI for P1: 0, mck2ui 16
5858 16:43:58.508010 best dqsien dly found for B0: ( 1, 2, 28)
5859 16:43:58.511045 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5860 16:43:58.514334 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5861 16:43:58.514417
5862 16:43:58.517914 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5863 16:43:58.521078 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5864 16:43:58.524551 [Gating] SW calibration Done
5865 16:43:58.524626 ==
5866 16:43:58.527564 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 16:43:58.534606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 16:43:58.534683 ==
5869 16:43:58.534746 RX Vref Scan: 0
5870 16:43:58.534807
5871 16:43:58.537504 RX Vref 0 -> 0, step: 1
5872 16:43:58.537577
5873 16:43:58.540868 RX Delay -80 -> 252, step: 8
5874 16:43:58.544322 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5875 16:43:58.547258 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5876 16:43:58.550760 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5877 16:43:58.554094 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5878 16:43:58.560791 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5879 16:43:58.564133 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5880 16:43:58.567358 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5881 16:43:58.570285 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5882 16:43:58.573992 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5883 16:43:58.577053 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5884 16:43:58.583867 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5885 16:43:58.586719 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5886 16:43:58.590495 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5887 16:43:58.593558 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5888 16:43:58.596692 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5889 16:43:58.603344 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5890 16:43:58.603425 ==
5891 16:43:58.606915 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 16:43:58.609951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 16:43:58.610035 ==
5894 16:43:58.610102 DQS Delay:
5895 16:43:58.613037 DQS0 = 0, DQS1 = 0
5896 16:43:58.613109 DQM Delay:
5897 16:43:58.616772 DQM0 = 99, DQM1 = 91
5898 16:43:58.616884 DQ Delay:
5899 16:43:58.619851 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5900 16:43:58.622945 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5901 16:43:58.626504 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5902 16:43:58.629954 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5903 16:43:58.630040
5904 16:43:58.630103
5905 16:43:58.630162 ==
5906 16:43:58.633037 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 16:43:58.636108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 16:43:58.639742 ==
5909 16:43:58.639815
5910 16:43:58.639876
5911 16:43:58.639939 TX Vref Scan disable
5912 16:43:58.642806 == TX Byte 0 ==
5913 16:43:58.646075 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5914 16:43:58.649581 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5915 16:43:58.653067 == TX Byte 1 ==
5916 16:43:58.655936 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5917 16:43:58.659390 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5918 16:43:58.662748 ==
5919 16:43:58.666050 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 16:43:58.669438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 16:43:58.669518 ==
5922 16:43:58.669583
5923 16:43:58.669642
5924 16:43:58.672784 TX Vref Scan disable
5925 16:43:58.672855 == TX Byte 0 ==
5926 16:43:58.679502 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5927 16:43:58.682909 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5928 16:43:58.683012 == TX Byte 1 ==
5929 16:43:58.689580 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5930 16:43:58.692611 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5931 16:43:58.692717
5932 16:43:58.692813 [DATLAT]
5933 16:43:58.695664 Freq=933, CH1 RK1
5934 16:43:58.695748
5935 16:43:58.695813 DATLAT Default: 0xb
5936 16:43:58.699300 0, 0xFFFF, sum = 0
5937 16:43:58.699376 1, 0xFFFF, sum = 0
5938 16:43:58.702461 2, 0xFFFF, sum = 0
5939 16:43:58.702548 3, 0xFFFF, sum = 0
5940 16:43:58.706014 4, 0xFFFF, sum = 0
5941 16:43:58.706099 5, 0xFFFF, sum = 0
5942 16:43:58.709049 6, 0xFFFF, sum = 0
5943 16:43:58.712677 7, 0xFFFF, sum = 0
5944 16:43:58.712762 8, 0xFFFF, sum = 0
5945 16:43:58.715856 9, 0xFFFF, sum = 0
5946 16:43:58.715989 10, 0x0, sum = 1
5947 16:43:58.718921 11, 0x0, sum = 2
5948 16:43:58.719038 12, 0x0, sum = 3
5949 16:43:58.719160 13, 0x0, sum = 4
5950 16:43:58.722114 best_step = 11
5951 16:43:58.722195
5952 16:43:58.722262 ==
5953 16:43:58.725717 Dram Type= 6, Freq= 0, CH_1, rank 1
5954 16:43:58.728723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5955 16:43:58.728805 ==
5956 16:43:58.732217 RX Vref Scan: 0
5957 16:43:58.732299
5958 16:43:58.732361 RX Vref 0 -> 0, step: 1
5959 16:43:58.735218
5960 16:43:58.735288 RX Delay -61 -> 252, step: 4
5961 16:43:58.743329 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5962 16:43:58.746506 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5963 16:43:58.749991 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5964 16:43:58.752919 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5965 16:43:58.756308 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5966 16:43:58.763299 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
5967 16:43:58.766153 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5968 16:43:58.769574 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5969 16:43:58.772960 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5970 16:43:58.776313 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5971 16:43:58.779736 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5972 16:43:58.786034 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5973 16:43:58.789358 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5974 16:43:58.792459 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
5975 16:43:58.796171 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
5976 16:43:58.799209 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
5977 16:43:58.802817 ==
5978 16:43:58.805896 Dram Type= 6, Freq= 0, CH_1, rank 1
5979 16:43:58.809084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5980 16:43:58.809161 ==
5981 16:43:58.809226 DQS Delay:
5982 16:43:58.812550 DQS0 = 0, DQS1 = 0
5983 16:43:58.812630 DQM Delay:
5984 16:43:58.815679 DQM0 = 101, DQM1 = 93
5985 16:43:58.815755 DQ Delay:
5986 16:43:58.819324 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
5987 16:43:58.822506 DQ4 =98, DQ5 =112, DQ6 =116, DQ7 =98
5988 16:43:58.825535 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84
5989 16:43:58.829081 DQ12 =104, DQ13 =98, DQ14 =102, DQ15 =104
5990 16:43:58.829153
5991 16:43:58.829215
5992 16:43:58.835752 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5993 16:43:58.839311 CH1 RK1: MR19=505, MR18=701
5994 16:43:58.845489 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
5995 16:43:58.848591 [RxdqsGatingPostProcess] freq 933
5996 16:43:58.855473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5997 16:43:58.859137 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 16:43:58.859211 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 16:43:58.861956 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 16:43:58.865254 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 16:43:58.868596 best DQS0 dly(2T, 0.5T) = (0, 10)
6002 16:43:58.872070 best DQS1 dly(2T, 0.5T) = (0, 10)
6003 16:43:58.875456 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6004 16:43:58.878232 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6005 16:43:58.881738 Pre-setting of DQS Precalculation
6006 16:43:58.888201 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6007 16:43:58.895331 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6008 16:43:58.901709 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6009 16:43:58.901796
6010 16:43:58.901859
6011 16:43:58.904762 [Calibration Summary] 1866 Mbps
6012 16:43:58.904836 CH 0, Rank 0
6013 16:43:58.908738 SW Impedance : PASS
6014 16:43:58.911557 DUTY Scan : NO K
6015 16:43:58.911657 ZQ Calibration : PASS
6016 16:43:58.914458 Jitter Meter : NO K
6017 16:43:58.918134 CBT Training : PASS
6018 16:43:58.918204 Write leveling : PASS
6019 16:43:58.921203 RX DQS gating : PASS
6020 16:43:58.924846 RX DQ/DQS(RDDQC) : PASS
6021 16:43:58.924928 TX DQ/DQS : PASS
6022 16:43:58.927942 RX DATLAT : PASS
6023 16:43:58.931099 RX DQ/DQS(Engine): PASS
6024 16:43:58.931195 TX OE : NO K
6025 16:43:58.934776 All Pass.
6026 16:43:58.934857
6027 16:43:58.934922 CH 0, Rank 1
6028 16:43:58.937839 SW Impedance : PASS
6029 16:43:58.937920 DUTY Scan : NO K
6030 16:43:58.941361 ZQ Calibration : PASS
6031 16:43:58.944501 Jitter Meter : NO K
6032 16:43:58.944583 CBT Training : PASS
6033 16:43:58.948226 Write leveling : PASS
6034 16:43:58.951349 RX DQS gating : PASS
6035 16:43:58.951431 RX DQ/DQS(RDDQC) : PASS
6036 16:43:58.954350 TX DQ/DQS : PASS
6037 16:43:58.954458 RX DATLAT : PASS
6038 16:43:58.958069 RX DQ/DQS(Engine): PASS
6039 16:43:58.961097 TX OE : NO K
6040 16:43:58.961179 All Pass.
6041 16:43:58.961245
6042 16:43:58.961307 CH 1, Rank 0
6043 16:43:58.964661 SW Impedance : PASS
6044 16:43:58.967831 DUTY Scan : NO K
6045 16:43:58.967917 ZQ Calibration : PASS
6046 16:43:58.971165 Jitter Meter : NO K
6047 16:43:58.974634 CBT Training : PASS
6048 16:43:58.974716 Write leveling : PASS
6049 16:43:58.978050 RX DQS gating : PASS
6050 16:43:58.980951 RX DQ/DQS(RDDQC) : PASS
6051 16:43:58.981034 TX DQ/DQS : PASS
6052 16:43:58.984369 RX DATLAT : PASS
6053 16:43:58.987559 RX DQ/DQS(Engine): PASS
6054 16:43:58.987642 TX OE : NO K
6055 16:43:58.990874 All Pass.
6056 16:43:58.990955
6057 16:43:58.991021 CH 1, Rank 1
6058 16:43:58.994227 SW Impedance : PASS
6059 16:43:58.994326 DUTY Scan : NO K
6060 16:43:58.997453 ZQ Calibration : PASS
6061 16:43:59.000894 Jitter Meter : NO K
6062 16:43:59.000976 CBT Training : PASS
6063 16:43:59.004236 Write leveling : PASS
6064 16:43:59.007647 RX DQS gating : PASS
6065 16:43:59.007731 RX DQ/DQS(RDDQC) : PASS
6066 16:43:59.010717 TX DQ/DQS : PASS
6067 16:43:59.013907 RX DATLAT : PASS
6068 16:43:59.013989 RX DQ/DQS(Engine): PASS
6069 16:43:59.017389 TX OE : NO K
6070 16:43:59.017471 All Pass.
6071 16:43:59.017537
6072 16:43:59.020390 DramC Write-DBI off
6073 16:43:59.024114 PER_BANK_REFRESH: Hybrid Mode
6074 16:43:59.024197 TX_TRACKING: ON
6075 16:43:59.034052 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6076 16:43:59.036994 [FAST_K] Save calibration result to emmc
6077 16:43:59.040729 dramc_set_vcore_voltage set vcore to 650000
6078 16:43:59.043737 Read voltage for 400, 6
6079 16:43:59.043836 Vio18 = 0
6080 16:43:59.043926 Vcore = 650000
6081 16:43:59.047145 Vdram = 0
6082 16:43:59.047219 Vddq = 0
6083 16:43:59.047281 Vmddr = 0
6084 16:43:59.053886 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6085 16:43:59.057058 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6086 16:43:59.060184 MEM_TYPE=3, freq_sel=20
6087 16:43:59.063242 sv_algorithm_assistance_LP4_800
6088 16:43:59.066892 ============ PULL DRAM RESETB DOWN ============
6089 16:43:59.070421 ========== PULL DRAM RESETB DOWN end =========
6090 16:43:59.076963 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6091 16:43:59.079987 ===================================
6092 16:43:59.080070 LPDDR4 DRAM CONFIGURATION
6093 16:43:59.083419 ===================================
6094 16:43:59.086324 EX_ROW_EN[0] = 0x0
6095 16:43:59.089778 EX_ROW_EN[1] = 0x0
6096 16:43:59.089860 LP4Y_EN = 0x0
6097 16:43:59.093216 WORK_FSP = 0x0
6098 16:43:59.093298 WL = 0x2
6099 16:43:59.096569 RL = 0x2
6100 16:43:59.096650 BL = 0x2
6101 16:43:59.100008 RPST = 0x0
6102 16:43:59.100093 RD_PRE = 0x0
6103 16:43:59.103287 WR_PRE = 0x1
6104 16:43:59.103368 WR_PST = 0x0
6105 16:43:59.106140 DBI_WR = 0x0
6106 16:43:59.106222 DBI_RD = 0x0
6107 16:43:59.109600 OTF = 0x1
6108 16:43:59.112841 ===================================
6109 16:43:59.116409 ===================================
6110 16:43:59.116491 ANA top config
6111 16:43:59.119496 ===================================
6112 16:43:59.123007 DLL_ASYNC_EN = 0
6113 16:43:59.126121 ALL_SLAVE_EN = 1
6114 16:43:59.129700 NEW_RANK_MODE = 1
6115 16:43:59.129808 DLL_IDLE_MODE = 1
6116 16:43:59.132852 LP45_APHY_COMB_EN = 1
6117 16:43:59.136605 TX_ODT_DIS = 1
6118 16:43:59.139659 NEW_8X_MODE = 1
6119 16:43:59.142669 ===================================
6120 16:43:59.146225 ===================================
6121 16:43:59.149176 data_rate = 800
6122 16:43:59.149274 CKR = 1
6123 16:43:59.152869 DQ_P2S_RATIO = 4
6124 16:43:59.156033 ===================================
6125 16:43:59.159663 CA_P2S_RATIO = 4
6126 16:43:59.162663 DQ_CA_OPEN = 0
6127 16:43:59.165703 DQ_SEMI_OPEN = 1
6128 16:43:59.169306 CA_SEMI_OPEN = 1
6129 16:43:59.169388 CA_FULL_RATE = 0
6130 16:43:59.172407 DQ_CKDIV4_EN = 0
6131 16:43:59.175969 CA_CKDIV4_EN = 1
6132 16:43:59.178999 CA_PREDIV_EN = 0
6133 16:43:59.182692 PH8_DLY = 0
6134 16:43:59.186055 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6135 16:43:59.189033 DQ_AAMCK_DIV = 0
6136 16:43:59.189113 CA_AAMCK_DIV = 0
6137 16:43:59.192624 CA_ADMCK_DIV = 4
6138 16:43:59.195822 DQ_TRACK_CA_EN = 0
6139 16:43:59.198734 CA_PICK = 800
6140 16:43:59.202121 CA_MCKIO = 400
6141 16:43:59.205608 MCKIO_SEMI = 400
6142 16:43:59.208950 PLL_FREQ = 3016
6143 16:43:59.209031 DQ_UI_PI_RATIO = 32
6144 16:43:59.212380 CA_UI_PI_RATIO = 32
6145 16:43:59.215851 ===================================
6146 16:43:59.218751 ===================================
6147 16:43:59.222234 memory_type:LPDDR4
6148 16:43:59.225637 GP_NUM : 10
6149 16:43:59.225721 SRAM_EN : 1
6150 16:43:59.228690 MD32_EN : 0
6151 16:43:59.232342 ===================================
6152 16:43:59.235413 [ANA_INIT] >>>>>>>>>>>>>>
6153 16:43:59.235497 <<<<<< [CONFIGURE PHASE]: ANA_TX
6154 16:43:59.242081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6155 16:43:59.245141 ===================================
6156 16:43:59.245226 data_rate = 800,PCW = 0X7400
6157 16:43:59.248741 ===================================
6158 16:43:59.251839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6159 16:43:59.258387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6160 16:43:59.268205 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 16:43:59.274908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6162 16:43:59.278562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6163 16:43:59.281704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6164 16:43:59.284810 [ANA_INIT] flow start
6165 16:43:59.284894 [ANA_INIT] PLL >>>>>>>>
6166 16:43:59.288465 [ANA_INIT] PLL <<<<<<<<
6167 16:43:59.291524 [ANA_INIT] MIDPI >>>>>>>>
6168 16:43:59.291607 [ANA_INIT] MIDPI <<<<<<<<
6169 16:43:59.294980 [ANA_INIT] DLL >>>>>>>>
6170 16:43:59.298016 [ANA_INIT] flow end
6171 16:43:59.301566 ============ LP4 DIFF to SE enter ============
6172 16:43:59.304713 ============ LP4 DIFF to SE exit ============
6173 16:43:59.307962 [ANA_INIT] <<<<<<<<<<<<<
6174 16:43:59.311377 [Flow] Enable top DCM control >>>>>
6175 16:43:59.314766 [Flow] Enable top DCM control <<<<<
6176 16:43:59.317679 Enable DLL master slave shuffle
6177 16:43:59.321052 ==============================================================
6178 16:43:59.324465 Gating Mode config
6179 16:43:59.330952 ==============================================================
6180 16:43:59.331037 Config description:
6181 16:43:59.340700 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6182 16:43:59.347366 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6183 16:43:59.354176 SELPH_MODE 0: By rank 1: By Phase
6184 16:43:59.357173 ==============================================================
6185 16:43:59.360834 GAT_TRACK_EN = 0
6186 16:43:59.363984 RX_GATING_MODE = 2
6187 16:43:59.367016 RX_GATING_TRACK_MODE = 2
6188 16:43:59.370801 SELPH_MODE = 1
6189 16:43:59.373855 PICG_EARLY_EN = 1
6190 16:43:59.377627 VALID_LAT_VALUE = 1
6191 16:43:59.380473 ==============================================================
6192 16:43:59.384104 Enter into Gating configuration >>>>
6193 16:43:59.387206 Exit from Gating configuration <<<<
6194 16:43:59.390217 Enter into DVFS_PRE_config >>>>>
6195 16:43:59.403289 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6196 16:43:59.406720 Exit from DVFS_PRE_config <<<<<
6197 16:43:59.410193 Enter into PICG configuration >>>>
6198 16:43:59.413788 Exit from PICG configuration <<<<
6199 16:43:59.413871 [RX_INPUT] configuration >>>>>
6200 16:43:59.416449 [RX_INPUT] configuration <<<<<
6201 16:43:59.423319 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6202 16:43:59.429506 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6203 16:43:59.432863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 16:43:59.439737 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 16:43:59.446472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6206 16:43:59.452627 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6207 16:43:59.456295 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6208 16:43:59.459410 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6209 16:43:59.466098 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6210 16:43:59.469080 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6211 16:43:59.472669 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6212 16:43:59.479431 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6213 16:43:59.482503 ===================================
6214 16:43:59.482588 LPDDR4 DRAM CONFIGURATION
6215 16:43:59.485614 ===================================
6216 16:43:59.489085 EX_ROW_EN[0] = 0x0
6217 16:43:59.492751 EX_ROW_EN[1] = 0x0
6218 16:43:59.492837 LP4Y_EN = 0x0
6219 16:43:59.495721 WORK_FSP = 0x0
6220 16:43:59.495813 WL = 0x2
6221 16:43:59.499374 RL = 0x2
6222 16:43:59.499458 BL = 0x2
6223 16:43:59.502406 RPST = 0x0
6224 16:43:59.502490 RD_PRE = 0x0
6225 16:43:59.506002 WR_PRE = 0x1
6226 16:43:59.506085 WR_PST = 0x0
6227 16:43:59.508850 DBI_WR = 0x0
6228 16:43:59.508935 DBI_RD = 0x0
6229 16:43:59.512285 OTF = 0x1
6230 16:43:59.515711 ===================================
6231 16:43:59.519330 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6232 16:43:59.522000 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6233 16:43:59.528893 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6234 16:43:59.532331 ===================================
6235 16:43:59.532425 LPDDR4 DRAM CONFIGURATION
6236 16:43:59.535311 ===================================
6237 16:43:59.538780 EX_ROW_EN[0] = 0x10
6238 16:43:59.541817 EX_ROW_EN[1] = 0x0
6239 16:43:59.541903 LP4Y_EN = 0x0
6240 16:43:59.545233 WORK_FSP = 0x0
6241 16:43:59.545318 WL = 0x2
6242 16:43:59.548811 RL = 0x2
6243 16:43:59.548896 BL = 0x2
6244 16:43:59.551823 RPST = 0x0
6245 16:43:59.551908 RD_PRE = 0x0
6246 16:43:59.555599 WR_PRE = 0x1
6247 16:43:59.555683 WR_PST = 0x0
6248 16:43:59.558662 DBI_WR = 0x0
6249 16:43:59.558747 DBI_RD = 0x0
6250 16:43:59.561765 OTF = 0x1
6251 16:43:59.565393 ===================================
6252 16:43:59.572034 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6253 16:43:59.575022 nWR fixed to 30
6254 16:43:59.575117 [ModeRegInit_LP4] CH0 RK0
6255 16:43:59.578164 [ModeRegInit_LP4] CH0 RK1
6256 16:43:59.581924 [ModeRegInit_LP4] CH1 RK0
6257 16:43:59.584921 [ModeRegInit_LP4] CH1 RK1
6258 16:43:59.585023 match AC timing 19
6259 16:43:59.588589 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6260 16:43:59.595207 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6261 16:43:59.598196 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6262 16:43:59.601799 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6263 16:43:59.608587 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6264 16:43:59.608690 ==
6265 16:43:59.611585 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 16:43:59.614550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 16:43:59.614649 ==
6268 16:43:59.621596 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6269 16:43:59.627929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6270 16:43:59.631377 [CA 0] Center 36 (8~64) winsize 57
6271 16:43:59.631479 [CA 1] Center 36 (8~64) winsize 57
6272 16:43:59.634749 [CA 2] Center 36 (8~64) winsize 57
6273 16:43:59.637982 [CA 3] Center 36 (8~64) winsize 57
6274 16:43:59.641336 [CA 4] Center 36 (8~64) winsize 57
6275 16:43:59.644237 [CA 5] Center 36 (8~64) winsize 57
6276 16:43:59.644340
6277 16:43:59.647835 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6278 16:43:59.647931
6279 16:43:59.654170 [CATrainingPosCal] consider 1 rank data
6280 16:43:59.654269 u2DelayCellTimex100 = 270/100 ps
6281 16:43:59.661018 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 16:43:59.664148 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 16:43:59.667263 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 16:43:59.670880 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 16:43:59.673911 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 16:43:59.677600 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 16:43:59.677696
6288 16:43:59.680683 CA PerBit enable=1, Macro0, CA PI delay=36
6289 16:43:59.680783
6290 16:43:59.683803 [CBTSetCACLKResult] CA Dly = 36
6291 16:43:59.687469 CS Dly: 1 (0~32)
6292 16:43:59.687540 ==
6293 16:43:59.690419 Dram Type= 6, Freq= 0, CH_0, rank 1
6294 16:43:59.694295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 16:43:59.694373 ==
6296 16:43:59.700659 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6297 16:43:59.703609 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6298 16:43:59.707193 [CA 0] Center 36 (8~64) winsize 57
6299 16:43:59.710227 [CA 1] Center 36 (8~64) winsize 57
6300 16:43:59.713856 [CA 2] Center 36 (8~64) winsize 57
6301 16:43:59.716802 [CA 3] Center 36 (8~64) winsize 57
6302 16:43:59.720432 [CA 4] Center 36 (8~64) winsize 57
6303 16:43:59.723472 [CA 5] Center 36 (8~64) winsize 57
6304 16:43:59.723547
6305 16:43:59.726936 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6306 16:43:59.727036
6307 16:43:59.729913 [CATrainingPosCal] consider 2 rank data
6308 16:43:59.733459 u2DelayCellTimex100 = 270/100 ps
6309 16:43:59.736734 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 16:43:59.743299 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 16:43:59.746981 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 16:43:59.750003 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 16:43:59.753606 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 16:43:59.756505 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 16:43:59.756604
6316 16:43:59.759892 CA PerBit enable=1, Macro0, CA PI delay=36
6317 16:43:59.759975
6318 16:43:59.763577 [CBTSetCACLKResult] CA Dly = 36
6319 16:43:59.763685 CS Dly: 1 (0~32)
6320 16:43:59.763786
6321 16:43:59.769689 ----->DramcWriteLeveling(PI) begin...
6322 16:43:59.769797 ==
6323 16:43:59.773397 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 16:43:59.776377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 16:43:59.776475 ==
6326 16:43:59.780020 Write leveling (Byte 0): 40 => 8
6327 16:43:59.782997 Write leveling (Byte 1): 32 => 0
6328 16:43:59.786141 DramcWriteLeveling(PI) end<-----
6329 16:43:59.786220
6330 16:43:59.786280 ==
6331 16:43:59.789753 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 16:43:59.792821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 16:43:59.792927 ==
6334 16:43:59.796505 [Gating] SW mode calibration
6335 16:43:59.803012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6336 16:43:59.809572 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6337 16:43:59.812574 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6338 16:43:59.816342 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 16:43:59.822864 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 16:43:59.825868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 16:43:59.829408 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 16:43:59.835962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 16:43:59.839381 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 16:43:59.842101 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 16:43:59.849042 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 16:43:59.849123 Total UI for P1: 0, mck2ui 16
6347 16:43:59.855421 best dqsien dly found for B0: ( 0, 14, 24)
6348 16:43:59.855502 Total UI for P1: 0, mck2ui 16
6349 16:43:59.862374 best dqsien dly found for B1: ( 0, 14, 24)
6350 16:43:59.865433 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6351 16:43:59.868962 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6352 16:43:59.869040
6353 16:43:59.872023 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6354 16:43:59.875672 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 16:43:59.878579 [Gating] SW calibration Done
6356 16:43:59.878673 ==
6357 16:43:59.882273 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 16:43:59.885295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 16:43:59.885375 ==
6360 16:43:59.888903 RX Vref Scan: 0
6361 16:43:59.888982
6362 16:43:59.889043 RX Vref 0 -> 0, step: 1
6363 16:43:59.889101
6364 16:43:59.892047 RX Delay -410 -> 252, step: 16
6365 16:43:59.898694 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6366 16:43:59.901766 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6367 16:43:59.905227 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6368 16:43:59.908288 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6369 16:43:59.915283 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6370 16:43:59.918272 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6371 16:43:59.921922 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6372 16:43:59.924979 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6373 16:43:59.931868 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6374 16:43:59.934905 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6375 16:43:59.938539 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6376 16:43:59.941558 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6377 16:43:59.948472 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6378 16:43:59.951361 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6379 16:43:59.954674 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6380 16:43:59.961384 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6381 16:43:59.961499 ==
6382 16:43:59.964482 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 16:43:59.967981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 16:43:59.968063 ==
6385 16:43:59.968127 DQS Delay:
6386 16:43:59.971315 DQS0 = 43, DQS1 = 59
6387 16:43:59.971428 DQM Delay:
6388 16:43:59.974343 DQM0 = 9, DQM1 = 12
6389 16:43:59.974424 DQ Delay:
6390 16:43:59.977974 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6391 16:43:59.981062 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6392 16:43:59.984636 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6393 16:43:59.987742 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6394 16:43:59.987856
6395 16:43:59.987962
6396 16:43:59.988084 ==
6397 16:43:59.990747 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 16:43:59.994382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 16:43:59.994465 ==
6400 16:43:59.994527
6401 16:43:59.994585
6402 16:43:59.997489 TX Vref Scan disable
6403 16:43:59.997558 == TX Byte 0 ==
6404 16:44:00.004168 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 16:44:00.007687 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 16:44:00.007778 == TX Byte 1 ==
6407 16:44:00.013844 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6408 16:44:00.017390 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6409 16:44:00.017493 ==
6410 16:44:00.020859 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 16:44:00.024011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 16:44:00.024084 ==
6413 16:44:00.027141
6414 16:44:00.027221
6415 16:44:00.027324 TX Vref Scan disable
6416 16:44:00.030838 == TX Byte 0 ==
6417 16:44:00.033897 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 16:44:00.037006 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 16:44:00.040749 == TX Byte 1 ==
6420 16:44:00.043667 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6421 16:44:00.047276 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6422 16:44:00.047357
6423 16:44:00.050167 [DATLAT]
6424 16:44:00.050246 Freq=400, CH0 RK0
6425 16:44:00.050311
6426 16:44:00.053717 DATLAT Default: 0xf
6427 16:44:00.053799 0, 0xFFFF, sum = 0
6428 16:44:00.057190 1, 0xFFFF, sum = 0
6429 16:44:00.057307 2, 0xFFFF, sum = 0
6430 16:44:00.060146 3, 0xFFFF, sum = 0
6431 16:44:00.060246 4, 0xFFFF, sum = 0
6432 16:44:00.063611 5, 0xFFFF, sum = 0
6433 16:44:00.063683 6, 0xFFFF, sum = 0
6434 16:44:00.066782 7, 0xFFFF, sum = 0
6435 16:44:00.066878 8, 0xFFFF, sum = 0
6436 16:44:00.070234 9, 0xFFFF, sum = 0
6437 16:44:00.070324 10, 0xFFFF, sum = 0
6438 16:44:00.073725 11, 0xFFFF, sum = 0
6439 16:44:00.073829 12, 0xFFFF, sum = 0
6440 16:44:00.076622 13, 0x0, sum = 1
6441 16:44:00.076706 14, 0x0, sum = 2
6442 16:44:00.080214 15, 0x0, sum = 3
6443 16:44:00.080296 16, 0x0, sum = 4
6444 16:44:00.083278 best_step = 14
6445 16:44:00.083360
6446 16:44:00.083453 ==
6447 16:44:00.086848 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 16:44:00.089894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 16:44:00.089978 ==
6450 16:44:00.092912 RX Vref Scan: 1
6451 16:44:00.093008
6452 16:44:00.093073 RX Vref 0 -> 0, step: 1
6453 16:44:00.093150
6454 16:44:00.096672 RX Delay -359 -> 252, step: 8
6455 16:44:00.096754
6456 16:44:00.099816 Set Vref, RX VrefLevel [Byte0]: 59
6457 16:44:00.102898 [Byte1]: 49
6458 16:44:00.108391
6459 16:44:00.108473 Final RX Vref Byte 0 = 59 to rank0
6460 16:44:00.111313 Final RX Vref Byte 1 = 49 to rank0
6461 16:44:00.114929 Final RX Vref Byte 0 = 59 to rank1
6462 16:44:00.117825 Final RX Vref Byte 1 = 49 to rank1==
6463 16:44:00.121379 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 16:44:00.127796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 16:44:00.127881 ==
6466 16:44:00.127947 DQS Delay:
6467 16:44:00.131355 DQS0 = 48, DQS1 = 60
6468 16:44:00.131437 DQM Delay:
6469 16:44:00.131520 DQM0 = 11, DQM1 = 12
6470 16:44:00.134433 DQ Delay:
6471 16:44:00.138063 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6472 16:44:00.141176 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6473 16:44:00.141258 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6474 16:44:00.147772 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6475 16:44:00.147857
6476 16:44:00.147921
6477 16:44:00.154172 [DQSOSCAuto] RK0, (LSB)MR18= 0xbc7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6478 16:44:00.157665 CH0 RK0: MR19=C0C, MR18=BC7F
6479 16:44:00.164030 CH0_RK0: MR19=0xC0C, MR18=0xBC7F, DQSOSC=386, MR23=63, INC=396, DEC=264
6480 16:44:00.164115 ==
6481 16:44:00.167505 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 16:44:00.170798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 16:44:00.170870 ==
6484 16:44:00.174192 [Gating] SW mode calibration
6485 16:44:00.180568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6486 16:44:00.187151 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6487 16:44:00.190699 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6488 16:44:00.193809 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 16:44:00.200553 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 16:44:00.203791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 16:44:00.206800 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 16:44:00.213512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 16:44:00.217042 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 16:44:00.220036 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 16:44:00.226693 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 16:44:00.230209 Total UI for P1: 0, mck2ui 16
6497 16:44:00.233282 best dqsien dly found for B0: ( 0, 14, 24)
6498 16:44:00.233369 Total UI for P1: 0, mck2ui 16
6499 16:44:00.240007 best dqsien dly found for B1: ( 0, 14, 24)
6500 16:44:00.243209 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6501 16:44:00.246696 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6502 16:44:00.246816
6503 16:44:00.249790 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6504 16:44:00.252812 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 16:44:00.256379 [Gating] SW calibration Done
6506 16:44:00.256456 ==
6507 16:44:00.259659 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 16:44:00.263046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 16:44:00.263172 ==
6510 16:44:00.266528 RX Vref Scan: 0
6511 16:44:00.266605
6512 16:44:00.269382 RX Vref 0 -> 0, step: 1
6513 16:44:00.269455
6514 16:44:00.269519 RX Delay -410 -> 252, step: 16
6515 16:44:00.276212 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6516 16:44:00.279533 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6517 16:44:00.282851 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6518 16:44:00.289311 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6519 16:44:00.292952 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6520 16:44:00.295904 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6521 16:44:00.299569 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6522 16:44:00.305740 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6523 16:44:00.309456 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6524 16:44:00.312507 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6525 16:44:00.316231 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6526 16:44:00.322681 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6527 16:44:00.325691 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6528 16:44:00.329306 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6529 16:44:00.332293 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6530 16:44:00.338953 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6531 16:44:00.339033 ==
6532 16:44:00.342621 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 16:44:00.345749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 16:44:00.345875 ==
6535 16:44:00.345974 DQS Delay:
6536 16:44:00.348767 DQS0 = 43, DQS1 = 59
6537 16:44:00.348857 DQM Delay:
6538 16:44:00.352419 DQM0 = 10, DQM1 = 16
6539 16:44:00.352545 DQ Delay:
6540 16:44:00.355535 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6541 16:44:00.358572 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6542 16:44:00.362189 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6543 16:44:00.365669 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6544 16:44:00.365747
6545 16:44:00.365812
6546 16:44:00.365883 ==
6547 16:44:00.368553 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 16:44:00.371779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 16:44:00.371854 ==
6550 16:44:00.375285
6551 16:44:00.375362
6552 16:44:00.375426 TX Vref Scan disable
6553 16:44:00.378718 == TX Byte 0 ==
6554 16:44:00.382032 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6555 16:44:00.385427 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6556 16:44:00.388818 == TX Byte 1 ==
6557 16:44:00.392465 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6558 16:44:00.395000 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6559 16:44:00.395110 ==
6560 16:44:00.398490 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 16:44:00.402038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 16:44:00.404969 ==
6563 16:44:00.405068
6564 16:44:00.405164
6565 16:44:00.405252 TX Vref Scan disable
6566 16:44:00.408581 == TX Byte 0 ==
6567 16:44:00.411758 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6568 16:44:00.414879 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6569 16:44:00.418546 == TX Byte 1 ==
6570 16:44:00.421509 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6571 16:44:00.425016 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6572 16:44:00.425098
6573 16:44:00.427968 [DATLAT]
6574 16:44:00.428049 Freq=400, CH0 RK1
6575 16:44:00.428115
6576 16:44:00.431609 DATLAT Default: 0xe
6577 16:44:00.431690 0, 0xFFFF, sum = 0
6578 16:44:00.434743 1, 0xFFFF, sum = 0
6579 16:44:00.434851 2, 0xFFFF, sum = 0
6580 16:44:00.438446 3, 0xFFFF, sum = 0
6581 16:44:00.438528 4, 0xFFFF, sum = 0
6582 16:44:00.441719 5, 0xFFFF, sum = 0
6583 16:44:00.441804 6, 0xFFFF, sum = 0
6584 16:44:00.444806 7, 0xFFFF, sum = 0
6585 16:44:00.444890 8, 0xFFFF, sum = 0
6586 16:44:00.447973 9, 0xFFFF, sum = 0
6587 16:44:00.448061 10, 0xFFFF, sum = 0
6588 16:44:00.451666 11, 0xFFFF, sum = 0
6589 16:44:00.454829 12, 0xFFFF, sum = 0
6590 16:44:00.454941 13, 0x0, sum = 1
6591 16:44:00.455037 14, 0x0, sum = 2
6592 16:44:00.457820 15, 0x0, sum = 3
6593 16:44:00.457905 16, 0x0, sum = 4
6594 16:44:00.461360 best_step = 14
6595 16:44:00.461443
6596 16:44:00.461507 ==
6597 16:44:00.464371 Dram Type= 6, Freq= 0, CH_0, rank 1
6598 16:44:00.468087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 16:44:00.468177 ==
6600 16:44:00.471142 RX Vref Scan: 0
6601 16:44:00.471225
6602 16:44:00.471290 RX Vref 0 -> 0, step: 1
6603 16:44:00.474538
6604 16:44:00.474619 RX Delay -359 -> 252, step: 8
6605 16:44:00.482629 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6606 16:44:00.486002 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6607 16:44:00.489521 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6608 16:44:00.496147 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6609 16:44:00.499540 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6610 16:44:00.502942 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6611 16:44:00.505745 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6612 16:44:00.512254 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6613 16:44:00.515954 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6614 16:44:00.518940 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6615 16:44:00.522651 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6616 16:44:00.529150 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6617 16:44:00.532096 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6618 16:44:00.535854 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6619 16:44:00.538931 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6620 16:44:00.545249 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6621 16:44:00.545373 ==
6622 16:44:00.548988 Dram Type= 6, Freq= 0, CH_0, rank 1
6623 16:44:00.551999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 16:44:00.552082 ==
6625 16:44:00.552214 DQS Delay:
6626 16:44:00.555152 DQS0 = 44, DQS1 = 60
6627 16:44:00.555262 DQM Delay:
6628 16:44:00.558862 DQM0 = 7, DQM1 = 15
6629 16:44:00.558968 DQ Delay:
6630 16:44:00.561961 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6631 16:44:00.565551 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6632 16:44:00.568593 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6633 16:44:00.571650 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =20
6634 16:44:00.571722
6635 16:44:00.571783
6636 16:44:00.578292 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe4a, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6637 16:44:00.581788 CH0 RK1: MR19=C0C, MR18=BE4A
6638 16:44:00.588352 CH0_RK1: MR19=0xC0C, MR18=0xBE4A, DQSOSC=386, MR23=63, INC=396, DEC=264
6639 16:44:00.591637 [RxdqsGatingPostProcess] freq 400
6640 16:44:00.598245 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6641 16:44:00.601686 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 16:44:00.604964 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 16:44:00.608412 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 16:44:00.611640 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 16:44:00.611735 best DQS0 dly(2T, 0.5T) = (0, 10)
6646 16:44:00.615205 best DQS1 dly(2T, 0.5T) = (0, 10)
6647 16:44:00.618231 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6648 16:44:00.621344 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6649 16:44:00.624352 Pre-setting of DQS Precalculation
6650 16:44:00.631004 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6651 16:44:00.631125 ==
6652 16:44:00.634521 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 16:44:00.638006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 16:44:00.638096 ==
6655 16:44:00.644161 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6656 16:44:00.651129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6657 16:44:00.654248 [CA 0] Center 36 (8~64) winsize 57
6658 16:44:00.657369 [CA 1] Center 36 (8~64) winsize 57
6659 16:44:00.657522 [CA 2] Center 36 (8~64) winsize 57
6660 16:44:00.661067 [CA 3] Center 36 (8~64) winsize 57
6661 16:44:00.664104 [CA 4] Center 36 (8~64) winsize 57
6662 16:44:00.667200 [CA 5] Center 36 (8~64) winsize 57
6663 16:44:00.667278
6664 16:44:00.673818 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6665 16:44:00.673921
6666 16:44:00.677622 [CATrainingPosCal] consider 1 rank data
6667 16:44:00.680635 u2DelayCellTimex100 = 270/100 ps
6668 16:44:00.683655 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 16:44:00.687246 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 16:44:00.690364 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 16:44:00.693851 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 16:44:00.696911 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 16:44:00.700318 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 16:44:00.700424
6675 16:44:00.703611 CA PerBit enable=1, Macro0, CA PI delay=36
6676 16:44:00.703710
6677 16:44:00.707016 [CBTSetCACLKResult] CA Dly = 36
6678 16:44:00.710623 CS Dly: 1 (0~32)
6679 16:44:00.710724 ==
6680 16:44:00.713303 Dram Type= 6, Freq= 0, CH_1, rank 1
6681 16:44:00.716708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 16:44:00.716819 ==
6683 16:44:00.723320 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6684 16:44:00.726898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6685 16:44:00.730502 [CA 0] Center 36 (8~64) winsize 57
6686 16:44:00.733503 [CA 1] Center 36 (8~64) winsize 57
6687 16:44:00.737065 [CA 2] Center 36 (8~64) winsize 57
6688 16:44:00.740143 [CA 3] Center 36 (8~64) winsize 57
6689 16:44:00.743829 [CA 4] Center 36 (8~64) winsize 57
6690 16:44:00.746742 [CA 5] Center 36 (8~64) winsize 57
6691 16:44:00.746850
6692 16:44:00.750281 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6693 16:44:00.750385
6694 16:44:00.753566 [CATrainingPosCal] consider 2 rank data
6695 16:44:00.756908 u2DelayCellTimex100 = 270/100 ps
6696 16:44:00.759970 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 16:44:00.766770 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 16:44:00.769762 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 16:44:00.773408 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 16:44:00.776507 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 16:44:00.780140 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 16:44:00.780254
6703 16:44:00.783215 CA PerBit enable=1, Macro0, CA PI delay=36
6704 16:44:00.783319
6705 16:44:00.786779 [CBTSetCACLKResult] CA Dly = 36
6706 16:44:00.786881 CS Dly: 1 (0~32)
6707 16:44:00.786973
6708 16:44:00.789664 ----->DramcWriteLeveling(PI) begin...
6709 16:44:00.793317 ==
6710 16:44:00.796314 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 16:44:00.800057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 16:44:00.800139 ==
6713 16:44:00.802994 Write leveling (Byte 0): 40 => 8
6714 16:44:00.806361 Write leveling (Byte 1): 32 => 0
6715 16:44:00.809794 DramcWriteLeveling(PI) end<-----
6716 16:44:00.809892
6717 16:44:00.809985 ==
6718 16:44:00.812680 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 16:44:00.815999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 16:44:00.816098 ==
6721 16:44:00.819822 [Gating] SW mode calibration
6722 16:44:00.826081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6723 16:44:00.832603 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6724 16:44:00.835986 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6725 16:44:00.839650 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 16:44:00.846076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 16:44:00.849141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 16:44:00.852229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 16:44:00.858930 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 16:44:00.862264 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 16:44:00.865824 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 16:44:00.871891 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 16:44:00.871970 Total UI for P1: 0, mck2ui 16
6734 16:44:00.878653 best dqsien dly found for B0: ( 0, 14, 24)
6735 16:44:00.878731 Total UI for P1: 0, mck2ui 16
6736 16:44:00.885226 best dqsien dly found for B1: ( 0, 14, 24)
6737 16:44:00.888289 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6738 16:44:00.891879 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6739 16:44:00.891985
6740 16:44:00.894820 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6741 16:44:00.898358 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 16:44:00.901458 [Gating] SW calibration Done
6743 16:44:00.901562 ==
6744 16:44:00.905127 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 16:44:00.908169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 16:44:00.908274 ==
6747 16:44:00.911756 RX Vref Scan: 0
6748 16:44:00.911858
6749 16:44:00.911951 RX Vref 0 -> 0, step: 1
6750 16:44:00.914600
6751 16:44:00.914697 RX Delay -410 -> 252, step: 16
6752 16:44:00.921603 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6753 16:44:00.925006 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6754 16:44:00.927843 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6755 16:44:00.931362 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6756 16:44:00.937846 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6757 16:44:00.941416 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6758 16:44:00.944471 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6759 16:44:00.950912 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6760 16:44:00.954577 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6761 16:44:00.957637 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6762 16:44:00.961175 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6763 16:44:00.967956 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6764 16:44:00.971032 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6765 16:44:00.974145 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6766 16:44:00.977754 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6767 16:44:00.984477 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6768 16:44:00.984587 ==
6769 16:44:00.987384 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 16:44:00.991152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 16:44:00.991254 ==
6772 16:44:00.991346 DQS Delay:
6773 16:44:00.994129 DQS0 = 43, DQS1 = 51
6774 16:44:00.994264 DQM Delay:
6775 16:44:00.997614 DQM0 = 12, DQM1 = 14
6776 16:44:00.997715 DQ Delay:
6777 16:44:01.000610 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6778 16:44:01.004156 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6779 16:44:01.007171 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6780 16:44:01.010825 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6781 16:44:01.010934
6782 16:44:01.011026
6783 16:44:01.011154 ==
6784 16:44:01.013935 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 16:44:01.017031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 16:44:01.017134 ==
6787 16:44:01.017224
6788 16:44:01.017310
6789 16:44:01.020483 TX Vref Scan disable
6790 16:44:01.023857 == TX Byte 0 ==
6791 16:44:01.026986 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 16:44:01.030340 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 16:44:01.033559 == TX Byte 1 ==
6794 16:44:01.037065 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6795 16:44:01.040387 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6796 16:44:01.040491 ==
6797 16:44:01.043676 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 16:44:01.046706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 16:44:01.050132 ==
6800 16:44:01.050243
6801 16:44:01.050320
6802 16:44:01.050395 TX Vref Scan disable
6803 16:44:01.053637 == TX Byte 0 ==
6804 16:44:01.056535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 16:44:01.060187 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 16:44:01.063657 == TX Byte 1 ==
6807 16:44:01.066780 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6808 16:44:01.069809 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6809 16:44:01.069911
6810 16:44:01.073462 [DATLAT]
6811 16:44:01.073573 Freq=400, CH1 RK0
6812 16:44:01.073669
6813 16:44:01.076537 DATLAT Default: 0xf
6814 16:44:01.076622 0, 0xFFFF, sum = 0
6815 16:44:01.079737 1, 0xFFFF, sum = 0
6816 16:44:01.079847 2, 0xFFFF, sum = 0
6817 16:44:01.083350 3, 0xFFFF, sum = 0
6818 16:44:01.083429 4, 0xFFFF, sum = 0
6819 16:44:01.086347 5, 0xFFFF, sum = 0
6820 16:44:01.086424 6, 0xFFFF, sum = 0
6821 16:44:01.090069 7, 0xFFFF, sum = 0
6822 16:44:01.090154 8, 0xFFFF, sum = 0
6823 16:44:01.093156 9, 0xFFFF, sum = 0
6824 16:44:01.093266 10, 0xFFFF, sum = 0
6825 16:44:01.096843 11, 0xFFFF, sum = 0
6826 16:44:01.099823 12, 0xFFFF, sum = 0
6827 16:44:01.099931 13, 0x0, sum = 1
6828 16:44:01.100028 14, 0x0, sum = 2
6829 16:44:01.103280 15, 0x0, sum = 3
6830 16:44:01.103398 16, 0x0, sum = 4
6831 16:44:01.106386 best_step = 14
6832 16:44:01.106485
6833 16:44:01.106580 ==
6834 16:44:01.110021 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 16:44:01.113118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 16:44:01.113225 ==
6837 16:44:01.116122 RX Vref Scan: 1
6838 16:44:01.116226
6839 16:44:01.116321 RX Vref 0 -> 0, step: 1
6840 16:44:01.119829
6841 16:44:01.119933 RX Delay -343 -> 252, step: 8
6842 16:44:01.120030
6843 16:44:01.122812 Set Vref, RX VrefLevel [Byte0]: 49
6844 16:44:01.126402 [Byte1]: 53
6845 16:44:01.131659
6846 16:44:01.131778 Final RX Vref Byte 0 = 49 to rank0
6847 16:44:01.134521 Final RX Vref Byte 1 = 53 to rank0
6848 16:44:01.137891 Final RX Vref Byte 0 = 49 to rank1
6849 16:44:01.141401 Final RX Vref Byte 1 = 53 to rank1==
6850 16:44:01.144223 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 16:44:01.151050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 16:44:01.151205 ==
6853 16:44:01.151303 DQS Delay:
6854 16:44:01.154401 DQS0 = 44, DQS1 = 56
6855 16:44:01.154506 DQM Delay:
6856 16:44:01.154599 DQM0 = 8, DQM1 = 13
6857 16:44:01.157964 DQ Delay:
6858 16:44:01.160778 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6859 16:44:01.164282 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6860 16:44:01.164368 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6861 16:44:01.167260 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6862 16:44:01.170700
6863 16:44:01.170812
6864 16:44:01.177595 [DQSOSCAuto] RK0, (LSB)MR18= 0xa176, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 389 ps
6865 16:44:01.180668 CH1 RK0: MR19=C0C, MR18=A176
6866 16:44:01.187296 CH1_RK0: MR19=0xC0C, MR18=0xA176, DQSOSC=389, MR23=63, INC=390, DEC=260
6867 16:44:01.187408 ==
6868 16:44:01.190410 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 16:44:01.194075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 16:44:01.194180 ==
6871 16:44:01.197173 [Gating] SW mode calibration
6872 16:44:01.203322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6873 16:44:01.209819 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6874 16:44:01.213367 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6875 16:44:01.216999 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 16:44:01.223240 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 16:44:01.226754 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 16:44:01.229844 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 16:44:01.236973 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 16:44:01.239972 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 16:44:01.243230 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 16:44:01.250008 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 16:44:01.252849 Total UI for P1: 0, mck2ui 16
6884 16:44:01.256147 best dqsien dly found for B0: ( 0, 14, 24)
6885 16:44:01.259257 Total UI for P1: 0, mck2ui 16
6886 16:44:01.262879 best dqsien dly found for B1: ( 0, 14, 24)
6887 16:44:01.266170 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6888 16:44:01.269699 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6889 16:44:01.269813
6890 16:44:01.272654 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6891 16:44:01.276330 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 16:44:01.279551 [Gating] SW calibration Done
6893 16:44:01.279659 ==
6894 16:44:01.282482 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 16:44:01.285554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 16:44:01.285696 ==
6897 16:44:01.289153 RX Vref Scan: 0
6898 16:44:01.289248
6899 16:44:01.292259 RX Vref 0 -> 0, step: 1
6900 16:44:01.292340
6901 16:44:01.295959 RX Delay -410 -> 252, step: 16
6902 16:44:01.299044 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6903 16:44:01.302289 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6904 16:44:01.305764 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6905 16:44:01.312280 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6906 16:44:01.315380 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6907 16:44:01.318448 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6908 16:44:01.322037 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6909 16:44:01.328742 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6910 16:44:01.331747 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6911 16:44:01.335480 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6912 16:44:01.338376 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6913 16:44:01.345520 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6914 16:44:01.348233 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6915 16:44:01.351579 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6916 16:44:01.358250 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6917 16:44:01.361672 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6918 16:44:01.361747 ==
6919 16:44:01.365068 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 16:44:01.368217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 16:44:01.368289 ==
6922 16:44:01.371904 DQS Delay:
6923 16:44:01.371982 DQS0 = 51, DQS1 = 51
6924 16:44:01.372046 DQM Delay:
6925 16:44:01.374693 DQM0 = 19, DQM1 = 14
6926 16:44:01.374765 DQ Delay:
6927 16:44:01.378048 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6928 16:44:01.381525 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6929 16:44:01.384545 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6930 16:44:01.388182 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6931 16:44:01.388255
6932 16:44:01.388322
6933 16:44:01.388382 ==
6934 16:44:01.391200 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 16:44:01.394841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 16:44:01.397998 ==
6937 16:44:01.398078
6938 16:44:01.398148
6939 16:44:01.398208 TX Vref Scan disable
6940 16:44:01.400991 == TX Byte 0 ==
6941 16:44:01.404724 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6942 16:44:01.407720 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6943 16:44:01.411317 == TX Byte 1 ==
6944 16:44:01.414302 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6945 16:44:01.417798 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6946 16:44:01.417874 ==
6947 16:44:01.420870 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 16:44:01.427835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 16:44:01.427924 ==
6950 16:44:01.427994
6951 16:44:01.428057
6952 16:44:01.428115 TX Vref Scan disable
6953 16:44:01.430822 == TX Byte 0 ==
6954 16:44:01.434469 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6955 16:44:01.440627 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6956 16:44:01.440710 == TX Byte 1 ==
6957 16:44:01.444279 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6958 16:44:01.447351 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6959 16:44:01.450734
6960 16:44:01.450821 [DATLAT]
6961 16:44:01.450917 Freq=400, CH1 RK1
6962 16:44:01.451007
6963 16:44:01.454138 DATLAT Default: 0xe
6964 16:44:01.454214 0, 0xFFFF, sum = 0
6965 16:44:01.457062 1, 0xFFFF, sum = 0
6966 16:44:01.457142 2, 0xFFFF, sum = 0
6967 16:44:01.460475 3, 0xFFFF, sum = 0
6968 16:44:01.460560 4, 0xFFFF, sum = 0
6969 16:44:01.463885 5, 0xFFFF, sum = 0
6970 16:44:01.467275 6, 0xFFFF, sum = 0
6971 16:44:01.467385 7, 0xFFFF, sum = 0
6972 16:44:01.470721 8, 0xFFFF, sum = 0
6973 16:44:01.470795 9, 0xFFFF, sum = 0
6974 16:44:01.474292 10, 0xFFFF, sum = 0
6975 16:44:01.474370 11, 0xFFFF, sum = 0
6976 16:44:01.477208 12, 0xFFFF, sum = 0
6977 16:44:01.477285 13, 0x0, sum = 1
6978 16:44:01.480722 14, 0x0, sum = 2
6979 16:44:01.480797 15, 0x0, sum = 3
6980 16:44:01.483620 16, 0x0, sum = 4
6981 16:44:01.483693 best_step = 14
6982 16:44:01.483754
6983 16:44:01.483816 ==
6984 16:44:01.486993 Dram Type= 6, Freq= 0, CH_1, rank 1
6985 16:44:01.490669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6986 16:44:01.493674 ==
6987 16:44:01.493750 RX Vref Scan: 0
6988 16:44:01.493814
6989 16:44:01.497278 RX Vref 0 -> 0, step: 1
6990 16:44:01.497360
6991 16:44:01.500223 RX Delay -343 -> 252, step: 8
6992 16:44:01.503963 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6993 16:44:01.510185 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6994 16:44:01.513771 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6995 16:44:01.516697 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
6996 16:44:01.523258 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6997 16:44:01.526878 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6998 16:44:01.529905 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6999 16:44:01.533584 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7000 16:44:01.540225 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7001 16:44:01.543313 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7002 16:44:01.546417 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7003 16:44:01.550070 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7004 16:44:01.556513 iDelay=225, Bit 12, Center -32 (-279 ~ 216) 496
7005 16:44:01.559537 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
7006 16:44:01.562913 iDelay=225, Bit 14, Center -36 (-279 ~ 208) 488
7007 16:44:01.566330 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7008 16:44:01.569964 ==
7009 16:44:01.572720 Dram Type= 6, Freq= 0, CH_1, rank 1
7010 16:44:01.576249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7011 16:44:01.576331 ==
7012 16:44:01.576396 DQS Delay:
7013 16:44:01.579758 DQS0 = 44, DQS1 = 56
7014 16:44:01.579839 DQM Delay:
7015 16:44:01.582586 DQM0 = 10, DQM1 = 13
7016 16:44:01.582666 DQ Delay:
7017 16:44:01.586207 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
7018 16:44:01.589064 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7019 16:44:01.592485 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7020 16:44:01.595914 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7021 16:44:01.595997
7022 16:44:01.596066
7023 16:44:01.602533 [DQSOSCAuto] RK1, (LSB)MR18= 0x6858, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7024 16:44:01.605559 CH1 RK1: MR19=C0C, MR18=6858
7025 16:44:01.612226 CH1_RK1: MR19=0xC0C, MR18=0x6858, DQSOSC=396, MR23=63, INC=376, DEC=251
7026 16:44:01.615908 [RxdqsGatingPostProcess] freq 400
7027 16:44:01.622335 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7028 16:44:01.622419 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 16:44:01.625338 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 16:44:01.628977 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 16:44:01.632088 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 16:44:01.635160 best DQS0 dly(2T, 0.5T) = (0, 10)
7033 16:44:01.638922 best DQS1 dly(2T, 0.5T) = (0, 10)
7034 16:44:01.641903 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7035 16:44:01.645437 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7036 16:44:01.648503 Pre-setting of DQS Precalculation
7037 16:44:01.655341 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7038 16:44:01.661938 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7039 16:44:01.668534 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7040 16:44:01.668624
7041 16:44:01.668689
7042 16:44:01.671941 [Calibration Summary] 800 Mbps
7043 16:44:01.672022 CH 0, Rank 0
7044 16:44:01.675197 SW Impedance : PASS
7045 16:44:01.678153 DUTY Scan : NO K
7046 16:44:01.678228 ZQ Calibration : PASS
7047 16:44:01.681748 Jitter Meter : NO K
7048 16:44:01.685270 CBT Training : PASS
7049 16:44:01.685343 Write leveling : PASS
7050 16:44:01.688237 RX DQS gating : PASS
7051 16:44:01.691848 RX DQ/DQS(RDDQC) : PASS
7052 16:44:01.691923 TX DQ/DQS : PASS
7053 16:44:01.694684 RX DATLAT : PASS
7054 16:44:01.694773 RX DQ/DQS(Engine): PASS
7055 16:44:01.698143 TX OE : NO K
7056 16:44:01.698255 All Pass.
7057 16:44:01.698328
7058 16:44:01.701636 CH 0, Rank 1
7059 16:44:01.701817 SW Impedance : PASS
7060 16:44:01.704745 DUTY Scan : NO K
7061 16:44:01.707764 ZQ Calibration : PASS
7062 16:44:01.707863 Jitter Meter : NO K
7063 16:44:01.711520 CBT Training : PASS
7064 16:44:01.714483 Write leveling : NO K
7065 16:44:01.714556 RX DQS gating : PASS
7066 16:44:01.718214 RX DQ/DQS(RDDQC) : PASS
7067 16:44:01.721213 TX DQ/DQS : PASS
7068 16:44:01.721312 RX DATLAT : PASS
7069 16:44:01.724857 RX DQ/DQS(Engine): PASS
7070 16:44:01.727794 TX OE : NO K
7071 16:44:01.727895 All Pass.
7072 16:44:01.727985
7073 16:44:01.728087 CH 1, Rank 0
7074 16:44:01.731389 SW Impedance : PASS
7075 16:44:01.734552 DUTY Scan : NO K
7076 16:44:01.734648 ZQ Calibration : PASS
7077 16:44:01.737519 Jitter Meter : NO K
7078 16:44:01.741236 CBT Training : PASS
7079 16:44:01.741377 Write leveling : PASS
7080 16:44:01.744229 RX DQS gating : PASS
7081 16:44:01.747745 RX DQ/DQS(RDDQC) : PASS
7082 16:44:01.747849 TX DQ/DQS : PASS
7083 16:44:01.750755 RX DATLAT : PASS
7084 16:44:01.754330 RX DQ/DQS(Engine): PASS
7085 16:44:01.754421 TX OE : NO K
7086 16:44:01.754485 All Pass.
7087 16:44:01.757524
7088 16:44:01.757636 CH 1, Rank 1
7089 16:44:01.761099 SW Impedance : PASS
7090 16:44:01.761222 DUTY Scan : NO K
7091 16:44:01.764228 ZQ Calibration : PASS
7092 16:44:01.764304 Jitter Meter : NO K
7093 16:44:01.767270 CBT Training : PASS
7094 16:44:01.770666 Write leveling : NO K
7095 16:44:01.770771 RX DQS gating : PASS
7096 16:44:01.773933 RX DQ/DQS(RDDQC) : PASS
7097 16:44:01.777326 TX DQ/DQS : PASS
7098 16:44:01.777428 RX DATLAT : PASS
7099 16:44:01.780816 RX DQ/DQS(Engine): PASS
7100 16:44:01.784050 TX OE : NO K
7101 16:44:01.784171 All Pass.
7102 16:44:01.784264
7103 16:44:01.787578 DramC Write-DBI off
7104 16:44:01.787679 PER_BANK_REFRESH: Hybrid Mode
7105 16:44:01.790407 TX_TRACKING: ON
7106 16:44:01.800290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7107 16:44:01.803781 [FAST_K] Save calibration result to emmc
7108 16:44:01.807172 dramc_set_vcore_voltage set vcore to 725000
7109 16:44:01.807281 Read voltage for 1600, 0
7110 16:44:01.810152 Vio18 = 0
7111 16:44:01.810226 Vcore = 725000
7112 16:44:01.810296 Vdram = 0
7113 16:44:01.813769 Vddq = 0
7114 16:44:01.813839 Vmddr = 0
7115 16:44:01.820365 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7116 16:44:01.823962 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7117 16:44:01.827041 MEM_TYPE=3, freq_sel=13
7118 16:44:01.830580 sv_algorithm_assistance_LP4_3733
7119 16:44:01.833531 ============ PULL DRAM RESETB DOWN ============
7120 16:44:01.837248 ========== PULL DRAM RESETB DOWN end =========
7121 16:44:01.843918 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7122 16:44:01.847069 ===================================
7123 16:44:01.847174 LPDDR4 DRAM CONFIGURATION
7124 16:44:01.850145 ===================================
7125 16:44:01.853781 EX_ROW_EN[0] = 0x0
7126 16:44:01.856772 EX_ROW_EN[1] = 0x0
7127 16:44:01.856866 LP4Y_EN = 0x0
7128 16:44:01.859894 WORK_FSP = 0x1
7129 16:44:01.859982 WL = 0x5
7130 16:44:01.863597 RL = 0x5
7131 16:44:01.863685 BL = 0x2
7132 16:44:01.866845 RPST = 0x0
7133 16:44:01.866985 RD_PRE = 0x0
7134 16:44:01.869971 WR_PRE = 0x1
7135 16:44:01.870098 WR_PST = 0x1
7136 16:44:01.873061 DBI_WR = 0x0
7137 16:44:01.873178 DBI_RD = 0x0
7138 16:44:01.876723 OTF = 0x1
7139 16:44:01.880122 ===================================
7140 16:44:01.882990 ===================================
7141 16:44:01.883108 ANA top config
7142 16:44:01.886576 ===================================
7143 16:44:01.889998 DLL_ASYNC_EN = 0
7144 16:44:01.892848 ALL_SLAVE_EN = 0
7145 16:44:01.896503 NEW_RANK_MODE = 1
7146 16:44:01.896585 DLL_IDLE_MODE = 1
7147 16:44:01.899517 LP45_APHY_COMB_EN = 1
7148 16:44:01.902777 TX_ODT_DIS = 0
7149 16:44:01.906241 NEW_8X_MODE = 1
7150 16:44:01.909758 ===================================
7151 16:44:01.912817 ===================================
7152 16:44:01.916289 data_rate = 3200
7153 16:44:01.916374 CKR = 1
7154 16:44:01.919402 DQ_P2S_RATIO = 8
7155 16:44:01.922581 ===================================
7156 16:44:01.926503 CA_P2S_RATIO = 8
7157 16:44:01.929377 DQ_CA_OPEN = 0
7158 16:44:01.933173 DQ_SEMI_OPEN = 0
7159 16:44:01.933277 CA_SEMI_OPEN = 0
7160 16:44:01.936038 CA_FULL_RATE = 0
7161 16:44:01.939697 DQ_CKDIV4_EN = 0
7162 16:44:01.942823 CA_CKDIV4_EN = 0
7163 16:44:01.945859 CA_PREDIV_EN = 0
7164 16:44:01.949531 PH8_DLY = 12
7165 16:44:01.952586 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7166 16:44:01.952672 DQ_AAMCK_DIV = 4
7167 16:44:01.956104 CA_AAMCK_DIV = 4
7168 16:44:01.959126 CA_ADMCK_DIV = 4
7169 16:44:01.962891 DQ_TRACK_CA_EN = 0
7170 16:44:01.965996 CA_PICK = 1600
7171 16:44:01.968993 CA_MCKIO = 1600
7172 16:44:01.972729 MCKIO_SEMI = 0
7173 16:44:01.972814 PLL_FREQ = 3068
7174 16:44:01.975799 DQ_UI_PI_RATIO = 32
7175 16:44:01.979479 CA_UI_PI_RATIO = 0
7176 16:44:01.982484 ===================================
7177 16:44:01.986007 ===================================
7178 16:44:01.989329 memory_type:LPDDR4
7179 16:44:01.992719 GP_NUM : 10
7180 16:44:01.992830 SRAM_EN : 1
7181 16:44:01.995430 MD32_EN : 0
7182 16:44:01.998956 ===================================
7183 16:44:01.999041 [ANA_INIT] >>>>>>>>>>>>>>
7184 16:44:02.001903 <<<<<< [CONFIGURE PHASE]: ANA_TX
7185 16:44:02.005369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7186 16:44:02.009081 ===================================
7187 16:44:02.011993 data_rate = 3200,PCW = 0X7600
7188 16:44:02.015489 ===================================
7189 16:44:02.018529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7190 16:44:02.025502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7191 16:44:02.031535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 16:44:02.035227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7193 16:44:02.038336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7194 16:44:02.041945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7195 16:44:02.045126 [ANA_INIT] flow start
7196 16:44:02.045210 [ANA_INIT] PLL >>>>>>>>
7197 16:44:02.048158 [ANA_INIT] PLL <<<<<<<<
7198 16:44:02.051926 [ANA_INIT] MIDPI >>>>>>>>
7199 16:44:02.055024 [ANA_INIT] MIDPI <<<<<<<<
7200 16:44:02.055117 [ANA_INIT] DLL >>>>>>>>
7201 16:44:02.058614 [ANA_INIT] DLL <<<<<<<<
7202 16:44:02.058714 [ANA_INIT] flow end
7203 16:44:02.064682 ============ LP4 DIFF to SE enter ============
7204 16:44:02.068358 ============ LP4 DIFF to SE exit ============
7205 16:44:02.071458 [ANA_INIT] <<<<<<<<<<<<<
7206 16:44:02.074973 [Flow] Enable top DCM control >>>>>
7207 16:44:02.078058 [Flow] Enable top DCM control <<<<<
7208 16:44:02.081702 Enable DLL master slave shuffle
7209 16:44:02.084824 ==============================================================
7210 16:44:02.087847 Gating Mode config
7211 16:44:02.091332 ==============================================================
7212 16:44:02.094729 Config description:
7213 16:44:02.104436 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7214 16:44:02.111253 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7215 16:44:02.114296 SELPH_MODE 0: By rank 1: By Phase
7216 16:44:02.121289 ==============================================================
7217 16:44:02.124292 GAT_TRACK_EN = 1
7218 16:44:02.127849 RX_GATING_MODE = 2
7219 16:44:02.130690 RX_GATING_TRACK_MODE = 2
7220 16:44:02.133821 SELPH_MODE = 1
7221 16:44:02.137524 PICG_EARLY_EN = 1
7222 16:44:02.140610 VALID_LAT_VALUE = 1
7223 16:44:02.144242 ==============================================================
7224 16:44:02.147158 Enter into Gating configuration >>>>
7225 16:44:02.150833 Exit from Gating configuration <<<<
7226 16:44:02.153742 Enter into DVFS_PRE_config >>>>>
7227 16:44:02.164189 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7228 16:44:02.167125 Exit from DVFS_PRE_config <<<<<
7229 16:44:02.170201 Enter into PICG configuration >>>>
7230 16:44:02.173852 Exit from PICG configuration <<<<
7231 16:44:02.176882 [RX_INPUT] configuration >>>>>
7232 16:44:02.180472 [RX_INPUT] configuration <<<<<
7233 16:44:02.186744 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7234 16:44:02.190472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7235 16:44:02.196779 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 16:44:02.203213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 16:44:02.210254 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7238 16:44:02.216462 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7239 16:44:02.219975 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7240 16:44:02.223434 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7241 16:44:02.226344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7242 16:44:02.233547 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7243 16:44:02.236303 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7244 16:44:02.239859 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7245 16:44:02.242930 ===================================
7246 16:44:02.246511 LPDDR4 DRAM CONFIGURATION
7247 16:44:02.249610 ===================================
7248 16:44:02.253267 EX_ROW_EN[0] = 0x0
7249 16:44:02.253367 EX_ROW_EN[1] = 0x0
7250 16:44:02.256387 LP4Y_EN = 0x0
7251 16:44:02.256484 WORK_FSP = 0x1
7252 16:44:02.259484 WL = 0x5
7253 16:44:02.259556 RL = 0x5
7254 16:44:02.263076 BL = 0x2
7255 16:44:02.263166 RPST = 0x0
7256 16:44:02.266111 RD_PRE = 0x0
7257 16:44:02.266234 WR_PRE = 0x1
7258 16:44:02.269662 WR_PST = 0x1
7259 16:44:02.269736 DBI_WR = 0x0
7260 16:44:02.272788 DBI_RD = 0x0
7261 16:44:02.272871 OTF = 0x1
7262 16:44:02.276473 ===================================
7263 16:44:02.282532 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7264 16:44:02.286102 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7265 16:44:02.289282 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7266 16:44:02.293002 ===================================
7267 16:44:02.296078 LPDDR4 DRAM CONFIGURATION
7268 16:44:02.299671 ===================================
7269 16:44:02.302583 EX_ROW_EN[0] = 0x10
7270 16:44:02.302655 EX_ROW_EN[1] = 0x0
7271 16:44:02.305990 LP4Y_EN = 0x0
7272 16:44:02.306144 WORK_FSP = 0x1
7273 16:44:02.309367 WL = 0x5
7274 16:44:02.309464 RL = 0x5
7275 16:44:02.312553 BL = 0x2
7276 16:44:02.312627 RPST = 0x0
7277 16:44:02.315617 RD_PRE = 0x0
7278 16:44:02.315705 WR_PRE = 0x1
7279 16:44:02.319226 WR_PST = 0x1
7280 16:44:02.319302 DBI_WR = 0x0
7281 16:44:02.322419 DBI_RD = 0x0
7282 16:44:02.322532 OTF = 0x1
7283 16:44:02.325908 ===================================
7284 16:44:02.332340 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7285 16:44:02.332463 ==
7286 16:44:02.335816 Dram Type= 6, Freq= 0, CH_0, rank 0
7287 16:44:02.342115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7288 16:44:02.342198 ==
7289 16:44:02.342264 [Duty_Offset_Calibration]
7290 16:44:02.345695 B0:1 B1:-1 CA:0
7291 16:44:02.345775
7292 16:44:02.348790 [DutyScan_Calibration_Flow] k_type=0
7293 16:44:02.358389
7294 16:44:02.358469 ==CLK 0==
7295 16:44:02.361432 Final CLK duty delay cell = 0
7296 16:44:02.365212 [0] MAX Duty = 5125%(X100), DQS PI = 24
7297 16:44:02.368201 [0] MIN Duty = 4907%(X100), DQS PI = 4
7298 16:44:02.368282 [0] AVG Duty = 5016%(X100)
7299 16:44:02.371714
7300 16:44:02.374677 CH0 CLK Duty spec in!! Max-Min= 218%
7301 16:44:02.378273 [DutyScan_Calibration_Flow] ====Done====
7302 16:44:02.378353
7303 16:44:02.381373 [DutyScan_Calibration_Flow] k_type=1
7304 16:44:02.397626
7305 16:44:02.397710 ==DQS 0 ==
7306 16:44:02.400756 Final DQS duty delay cell = -4
7307 16:44:02.404332 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7308 16:44:02.407235 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7309 16:44:02.410631 [-4] AVG Duty = 4906%(X100)
7310 16:44:02.410712
7311 16:44:02.410776 ==DQS 1 ==
7312 16:44:02.414296 Final DQS duty delay cell = 0
7313 16:44:02.417329 [0] MAX Duty = 5156%(X100), DQS PI = 0
7314 16:44:02.420609 [0] MIN Duty = 5031%(X100), DQS PI = 20
7315 16:44:02.424103 [0] AVG Duty = 5093%(X100)
7316 16:44:02.424185
7317 16:44:02.427552 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7318 16:44:02.427677
7319 16:44:02.430907 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7320 16:44:02.433975 [DutyScan_Calibration_Flow] ====Done====
7321 16:44:02.434103
7322 16:44:02.437460 [DutyScan_Calibration_Flow] k_type=3
7323 16:44:02.454982
7324 16:44:02.455131 ==DQM 0 ==
7325 16:44:02.458549 Final DQM duty delay cell = 0
7326 16:44:02.461548 [0] MAX Duty = 5124%(X100), DQS PI = 20
7327 16:44:02.465129 [0] MIN Duty = 4875%(X100), DQS PI = 10
7328 16:44:02.465210 [0] AVG Duty = 4999%(X100)
7329 16:44:02.468188
7330 16:44:02.468266 ==DQM 1 ==
7331 16:44:02.471314 Final DQM duty delay cell = 0
7332 16:44:02.474971 [0] MAX Duty = 5031%(X100), DQS PI = 30
7333 16:44:02.477929 [0] MIN Duty = 4782%(X100), DQS PI = 22
7334 16:44:02.481564 [0] AVG Duty = 4906%(X100)
7335 16:44:02.481643
7336 16:44:02.484541 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7337 16:44:02.484623
7338 16:44:02.488181 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7339 16:44:02.491198 [DutyScan_Calibration_Flow] ====Done====
7340 16:44:02.491310
7341 16:44:02.494809 [DutyScan_Calibration_Flow] k_type=2
7342 16:44:02.511379
7343 16:44:02.511459 ==DQ 0 ==
7344 16:44:02.514842 Final DQ duty delay cell = -4
7345 16:44:02.517888 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7346 16:44:02.521498 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7347 16:44:02.524594 [-4] AVG Duty = 4953%(X100)
7348 16:44:02.524690
7349 16:44:02.524779 ==DQ 1 ==
7350 16:44:02.527702 Final DQ duty delay cell = 0
7351 16:44:02.531204 [0] MAX Duty = 5125%(X100), DQS PI = 4
7352 16:44:02.534123 [0] MIN Duty = 5000%(X100), DQS PI = 36
7353 16:44:02.538101 [0] AVG Duty = 5062%(X100)
7354 16:44:02.538198
7355 16:44:02.540671 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7356 16:44:02.540747
7357 16:44:02.544242 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7358 16:44:02.547845 [DutyScan_Calibration_Flow] ====Done====
7359 16:44:02.547929 ==
7360 16:44:02.550792 Dram Type= 6, Freq= 0, CH_1, rank 0
7361 16:44:02.554247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7362 16:44:02.554328 ==
7363 16:44:02.557367 [Duty_Offset_Calibration]
7364 16:44:02.557446 B0:-1 B1:1 CA:2
7365 16:44:02.560996
7366 16:44:02.561081 [DutyScan_Calibration_Flow] k_type=0
7367 16:44:02.571695
7368 16:44:02.571782 ==CLK 0==
7369 16:44:02.575230 Final CLK duty delay cell = 0
7370 16:44:02.578298 [0] MAX Duty = 5187%(X100), DQS PI = 22
7371 16:44:02.581804 [0] MIN Duty = 4969%(X100), DQS PI = 62
7372 16:44:02.584795 [0] AVG Duty = 5078%(X100)
7373 16:44:02.584877
7374 16:44:02.588219 CH1 CLK Duty spec in!! Max-Min= 218%
7375 16:44:02.591947 [DutyScan_Calibration_Flow] ====Done====
7376 16:44:02.592057
7377 16:44:02.594904 [DutyScan_Calibration_Flow] k_type=1
7378 16:44:02.612142
7379 16:44:02.612223 ==DQS 0 ==
7380 16:44:02.614864 Final DQS duty delay cell = 0
7381 16:44:02.618428 [0] MAX Duty = 5156%(X100), DQS PI = 18
7382 16:44:02.621331 [0] MIN Duty = 4907%(X100), DQS PI = 10
7383 16:44:02.624602 [0] AVG Duty = 5031%(X100)
7384 16:44:02.624681
7385 16:44:02.624745 ==DQS 1 ==
7386 16:44:02.628245 Final DQS duty delay cell = 0
7387 16:44:02.631344 [0] MAX Duty = 5093%(X100), DQS PI = 26
7388 16:44:02.634870 [0] MIN Duty = 4969%(X100), DQS PI = 54
7389 16:44:02.637718 [0] AVG Duty = 5031%(X100)
7390 16:44:02.637798
7391 16:44:02.641343 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7392 16:44:02.641424
7393 16:44:02.644339 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7394 16:44:02.647805 [DutyScan_Calibration_Flow] ====Done====
7395 16:44:02.647886
7396 16:44:02.651416 [DutyScan_Calibration_Flow] k_type=3
7397 16:44:02.667568
7398 16:44:02.667650 ==DQM 0 ==
7399 16:44:02.671247 Final DQM duty delay cell = -4
7400 16:44:02.674258 [-4] MAX Duty = 5031%(X100), DQS PI = 18
7401 16:44:02.678069 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7402 16:44:02.681140 [-4] AVG Duty = 4906%(X100)
7403 16:44:02.681221
7404 16:44:02.681284 ==DQM 1 ==
7405 16:44:02.684130 Final DQM duty delay cell = 0
7406 16:44:02.687723 [0] MAX Duty = 5156%(X100), DQS PI = 0
7407 16:44:02.691177 [0] MIN Duty = 5000%(X100), DQS PI = 28
7408 16:44:02.694267 [0] AVG Duty = 5078%(X100)
7409 16:44:02.694347
7410 16:44:02.697329 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7411 16:44:02.697410
7412 16:44:02.701005 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7413 16:44:02.704179 [DutyScan_Calibration_Flow] ====Done====
7414 16:44:02.704259
7415 16:44:02.707204 [DutyScan_Calibration_Flow] k_type=2
7416 16:44:02.725146
7417 16:44:02.725228 ==DQ 0 ==
7418 16:44:02.728091 Final DQ duty delay cell = 0
7419 16:44:02.731714 [0] MAX Duty = 5187%(X100), DQS PI = 32
7420 16:44:02.734719 [0] MIN Duty = 4906%(X100), DQS PI = 10
7421 16:44:02.734800 [0] AVG Duty = 5046%(X100)
7422 16:44:02.738260
7423 16:44:02.738340 ==DQ 1 ==
7424 16:44:02.741649 Final DQ duty delay cell = 0
7425 16:44:02.744576 [0] MAX Duty = 5156%(X100), DQS PI = 8
7426 16:44:02.748700 [0] MIN Duty = 4938%(X100), DQS PI = 60
7427 16:44:02.748790 [0] AVG Duty = 5047%(X100)
7428 16:44:02.751550
7429 16:44:02.754558 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7430 16:44:02.754697
7431 16:44:02.757537 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7432 16:44:02.761143 [DutyScan_Calibration_Flow] ====Done====
7433 16:44:02.764712 nWR fixed to 30
7434 16:44:02.767791 [ModeRegInit_LP4] CH0 RK0
7435 16:44:02.767935 [ModeRegInit_LP4] CH0 RK1
7436 16:44:02.770825 [ModeRegInit_LP4] CH1 RK0
7437 16:44:02.774554 [ModeRegInit_LP4] CH1 RK1
7438 16:44:02.774686 match AC timing 5
7439 16:44:02.780715 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7440 16:44:02.784324 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7441 16:44:02.787427 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7442 16:44:02.793873 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7443 16:44:02.797608 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7444 16:44:02.797720 [MiockJmeterHQA]
7445 16:44:02.797818
7446 16:44:02.800752 [DramcMiockJmeter] u1RxGatingPI = 0
7447 16:44:02.803891 0 : 4252, 4027
7448 16:44:02.803999 4 : 4252, 4026
7449 16:44:02.807595 8 : 4253, 4026
7450 16:44:02.807679 12 : 4253, 4026
7451 16:44:02.810620 16 : 4252, 4027
7452 16:44:02.810704 20 : 4363, 4137
7453 16:44:02.810775 24 : 4253, 4026
7454 16:44:02.813665 28 : 4363, 4137
7455 16:44:02.813775 32 : 4253, 4026
7456 16:44:02.817733 36 : 4252, 4026
7457 16:44:02.817849 40 : 4252, 4027
7458 16:44:02.820477 44 : 4255, 4029
7459 16:44:02.820562 48 : 4252, 4027
7460 16:44:02.823702 52 : 4252, 4027
7461 16:44:02.823804 56 : 4365, 4140
7462 16:44:02.823900 60 : 4250, 4027
7463 16:44:02.827160 64 : 4253, 4029
7464 16:44:02.827261 68 : 4249, 4027
7465 16:44:02.830594 72 : 4360, 4137
7466 16:44:02.830693 76 : 4250, 4027
7467 16:44:02.833524 80 : 4360, 4137
7468 16:44:02.833643 84 : 4250, 4026
7469 16:44:02.837152 88 : 4250, 4027
7470 16:44:02.837269 92 : 4250, 454
7471 16:44:02.837363 96 : 4361, 0
7472 16:44:02.840101 100 : 4252, 0
7473 16:44:02.840201 104 : 4360, 0
7474 16:44:02.843548 108 : 4250, 0
7475 16:44:02.843652 112 : 4250, 0
7476 16:44:02.843745 116 : 4361, 0
7477 16:44:02.847054 120 : 4360, 0
7478 16:44:02.847163 124 : 4250, 0
7479 16:44:02.847257 128 : 4253, 0
7480 16:44:02.849910 132 : 4360, 0
7481 16:44:02.850013 136 : 4250, 0
7482 16:44:02.853481 140 : 4252, 0
7483 16:44:02.853586 144 : 4250, 0
7484 16:44:02.853681 148 : 4250, 0
7485 16:44:02.856513 152 : 4253, 0
7486 16:44:02.856613 156 : 4253, 0
7487 16:44:02.860195 160 : 4250, 0
7488 16:44:02.860297 164 : 4253, 0
7489 16:44:02.860393 168 : 4250, 0
7490 16:44:02.863240 172 : 4360, 0
7491 16:44:02.863357 176 : 4361, 0
7492 16:44:02.866567 180 : 4252, 0
7493 16:44:02.866679 184 : 4360, 0
7494 16:44:02.866777 188 : 4249, 0
7495 16:44:02.869681 192 : 4252, 0
7496 16:44:02.869766 196 : 4252, 0
7497 16:44:02.873113 200 : 4250, 0
7498 16:44:02.873197 204 : 4253, 0
7499 16:44:02.873286 208 : 4252, 0
7500 16:44:02.876137 212 : 4250, 0
7501 16:44:02.876251 216 : 4253, 0
7502 16:44:02.879912 220 : 4361, 0
7503 16:44:02.879999 224 : 4360, 322
7504 16:44:02.880067 228 : 4250, 3523
7505 16:44:02.882943 232 : 4250, 4027
7506 16:44:02.883030 236 : 4250, 4027
7507 16:44:02.886573 240 : 4250, 4027
7508 16:44:02.886647 244 : 4250, 4026
7509 16:44:02.889636 248 : 4253, 4029
7510 16:44:02.889708 252 : 4250, 4026
7511 16:44:02.892587 256 : 4361, 4138
7512 16:44:02.892686 260 : 4360, 4137
7513 16:44:02.896055 264 : 4250, 4027
7514 16:44:02.896158 268 : 4363, 4140
7515 16:44:02.899762 272 : 4360, 4137
7516 16:44:02.899860 276 : 4249, 4027
7517 16:44:02.902733 280 : 4250, 4027
7518 16:44:02.902815 284 : 4253, 4029
7519 16:44:02.902878 288 : 4249, 4027
7520 16:44:02.906326 292 : 4250, 4027
7521 16:44:02.906438 296 : 4250, 4026
7522 16:44:02.909501 300 : 4252, 4030
7523 16:44:02.909577 304 : 4249, 4027
7524 16:44:02.912490 308 : 4360, 4137
7525 16:44:02.912560 312 : 4360, 4137
7526 16:44:02.916142 316 : 4250, 4027
7527 16:44:02.916239 320 : 4363, 4140
7528 16:44:02.919415 324 : 4360, 4137
7529 16:44:02.919486 328 : 4250, 4027
7530 16:44:02.922758 332 : 4250, 4026
7531 16:44:02.922825 336 : 4252, 3584
7532 16:44:02.925748 340 : 4249, 1774
7533 16:44:02.925822
7534 16:44:02.925886 MIOCK jitter meter ch=0
7535 16:44:02.925974
7536 16:44:02.929306 1T = (340-92) = 248 dly cells
7537 16:44:02.935783 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7538 16:44:02.935864 ==
7539 16:44:02.939237 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 16:44:02.942306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 16:44:02.942403 ==
7542 16:44:02.948990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 16:44:02.952515 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 16:44:02.955646 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 16:44:02.962277 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 16:44:02.972013 [CA 0] Center 43 (12~74) winsize 63
7547 16:44:02.975147 [CA 1] Center 42 (12~73) winsize 62
7548 16:44:02.978823 [CA 2] Center 38 (9~68) winsize 60
7549 16:44:02.982117 [CA 3] Center 38 (8~68) winsize 61
7550 16:44:02.985368 [CA 4] Center 36 (7~66) winsize 60
7551 16:44:02.988705 [CA 5] Center 35 (6~65) winsize 60
7552 16:44:02.988812
7553 16:44:02.991870 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 16:44:02.991972
7555 16:44:02.998029 [CATrainingPosCal] consider 1 rank data
7556 16:44:02.998152 u2DelayCellTimex100 = 262/100 ps
7557 16:44:03.004816 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7558 16:44:03.008130 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7559 16:44:03.011377 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7560 16:44:03.014649 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7561 16:44:03.018386 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7562 16:44:03.021732 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7563 16:44:03.021849
7564 16:44:03.024713 CA PerBit enable=1, Macro0, CA PI delay=35
7565 16:44:03.024828
7566 16:44:03.027988 [CBTSetCACLKResult] CA Dly = 35
7567 16:44:03.031495 CS Dly: 12 (0~43)
7568 16:44:03.034460 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 16:44:03.038217 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 16:44:03.038324 ==
7571 16:44:03.041326 Dram Type= 6, Freq= 0, CH_0, rank 1
7572 16:44:03.048030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 16:44:03.048149 ==
7574 16:44:03.051120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7575 16:44:03.057639 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7576 16:44:03.061262 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7577 16:44:03.067251 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7578 16:44:03.075651 [CA 0] Center 43 (13~74) winsize 62
7579 16:44:03.078726 [CA 1] Center 44 (14~74) winsize 61
7580 16:44:03.082344 [CA 2] Center 38 (9~68) winsize 60
7581 16:44:03.085552 [CA 3] Center 38 (9~68) winsize 60
7582 16:44:03.088720 [CA 4] Center 36 (7~66) winsize 60
7583 16:44:03.091885 [CA 5] Center 36 (7~66) winsize 60
7584 16:44:03.091990
7585 16:44:03.095158 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7586 16:44:03.095235
7587 16:44:03.101482 [CATrainingPosCal] consider 2 rank data
7588 16:44:03.101565 u2DelayCellTimex100 = 262/100 ps
7589 16:44:03.108013 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7590 16:44:03.111665 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7591 16:44:03.114628 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7592 16:44:03.118344 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7593 16:44:03.121352 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7594 16:44:03.124996 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7595 16:44:03.125072
7596 16:44:03.128178 CA PerBit enable=1, Macro0, CA PI delay=36
7597 16:44:03.128252
7598 16:44:03.131167 [CBTSetCACLKResult] CA Dly = 36
7599 16:44:03.134787 CS Dly: 12 (0~43)
7600 16:44:03.137892 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7601 16:44:03.141320 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7602 16:44:03.141430
7603 16:44:03.144258 ----->DramcWriteLeveling(PI) begin...
7604 16:44:03.147772 ==
7605 16:44:03.147857 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 16:44:03.154361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 16:44:03.154472 ==
7608 16:44:03.157776 Write leveling (Byte 0): 35 => 35
7609 16:44:03.160775 Write leveling (Byte 1): 27 => 27
7610 16:44:03.164355 DramcWriteLeveling(PI) end<-----
7611 16:44:03.164441
7612 16:44:03.164508 ==
7613 16:44:03.167357 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 16:44:03.170896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 16:44:03.171004 ==
7616 16:44:03.173952 [Gating] SW mode calibration
7617 16:44:03.180485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7618 16:44:03.187467 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7619 16:44:03.190504 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 16:44:03.194209 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 16:44:03.200324 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 16:44:03.203353 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7623 16:44:03.206880 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7624 16:44:03.213582 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7625 16:44:03.216765 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7626 16:44:03.220327 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 16:44:03.226914 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 16:44:03.229994 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 16:44:03.233107 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7630 16:44:03.239696 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7631 16:44:03.243224 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7632 16:44:03.246583 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7633 16:44:03.253175 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7634 16:44:03.256293 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 16:44:03.259778 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 16:44:03.266360 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 16:44:03.269981 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7638 16:44:03.272827 1 6 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7639 16:44:03.279812 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7640 16:44:03.282678 1 6 20 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
7641 16:44:03.286321 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7642 16:44:03.292902 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 16:44:03.295993 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 16:44:03.299685 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 16:44:03.306038 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 16:44:03.309768 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7647 16:44:03.312628 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7648 16:44:03.319685 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7649 16:44:03.322628 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7650 16:44:03.326282 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 16:44:03.329358 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 16:44:03.335723 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 16:44:03.338936 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 16:44:03.342583 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 16:44:03.349136 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 16:44:03.352630 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 16:44:03.355594 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 16:44:03.362333 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 16:44:03.365914 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 16:44:03.369087 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 16:44:03.376068 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 16:44:03.378953 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 16:44:03.382012 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7664 16:44:03.385712 Total UI for P1: 0, mck2ui 16
7665 16:44:03.388694 best dqsien dly found for B0: ( 1, 9, 12)
7666 16:44:03.395314 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7667 16:44:03.398519 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 16:44:03.402118 Total UI for P1: 0, mck2ui 16
7669 16:44:03.405222 best dqsien dly found for B1: ( 1, 9, 20)
7670 16:44:03.408267 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7671 16:44:03.412125 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7672 16:44:03.412217
7673 16:44:03.415147 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7674 16:44:03.421834 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7675 16:44:03.421912 [Gating] SW calibration Done
7676 16:44:03.421976 ==
7677 16:44:03.425009 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 16:44:03.431853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 16:44:03.431958 ==
7680 16:44:03.432058 RX Vref Scan: 0
7681 16:44:03.432147
7682 16:44:03.435047 RX Vref 0 -> 0, step: 1
7683 16:44:03.435165
7684 16:44:03.438298 RX Delay 0 -> 252, step: 8
7685 16:44:03.441883 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7686 16:44:03.445039 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7687 16:44:03.448507 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7688 16:44:03.455030 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7689 16:44:03.458088 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7690 16:44:03.461186 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7691 16:44:03.464749 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7692 16:44:03.467956 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7693 16:44:03.474467 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7694 16:44:03.477547 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7695 16:44:03.481447 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7696 16:44:03.484322 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7697 16:44:03.487964 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7698 16:44:03.494210 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7699 16:44:03.497749 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7700 16:44:03.500842 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7701 16:44:03.500926 ==
7702 16:44:03.503951 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 16:44:03.507524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 16:44:03.511172 ==
7705 16:44:03.511255 DQS Delay:
7706 16:44:03.511322 DQS0 = 0, DQS1 = 0
7707 16:44:03.514238 DQM Delay:
7708 16:44:03.514320 DQM0 = 136, DQM1 = 126
7709 16:44:03.517228 DQ Delay:
7710 16:44:03.520878 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7711 16:44:03.523915 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7712 16:44:03.526909 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7713 16:44:03.530618 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7714 16:44:03.530703
7715 16:44:03.530771
7716 16:44:03.530843 ==
7717 16:44:03.533685 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 16:44:03.537247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 16:44:03.540294 ==
7720 16:44:03.540401
7721 16:44:03.540495
7722 16:44:03.540585 TX Vref Scan disable
7723 16:44:03.543496 == TX Byte 0 ==
7724 16:44:03.547048 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7725 16:44:03.550226 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7726 16:44:03.553688 == TX Byte 1 ==
7727 16:44:03.556727 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7728 16:44:03.560317 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7729 16:44:03.563325 ==
7730 16:44:03.566955 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 16:44:03.570067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 16:44:03.570173 ==
7733 16:44:03.582983
7734 16:44:03.585995 TX Vref early break, caculate TX vref
7735 16:44:03.589519 TX Vref=16, minBit 7, minWin=22, winSum=371
7736 16:44:03.593026 TX Vref=18, minBit 1, minWin=23, winSum=381
7737 16:44:03.595768 TX Vref=20, minBit 14, minWin=22, winSum=389
7738 16:44:03.599481 TX Vref=22, minBit 1, minWin=23, winSum=399
7739 16:44:03.602400 TX Vref=24, minBit 3, minWin=24, winSum=407
7740 16:44:03.609094 TX Vref=26, minBit 2, minWin=25, winSum=414
7741 16:44:03.612212 TX Vref=28, minBit 0, minWin=24, winSum=417
7742 16:44:03.615903 TX Vref=30, minBit 4, minWin=24, winSum=409
7743 16:44:03.618973 TX Vref=32, minBit 0, minWin=24, winSum=398
7744 16:44:03.622019 TX Vref=34, minBit 4, minWin=22, winSum=391
7745 16:44:03.628624 [TxChooseVref] Worse bit 2, Min win 25, Win sum 414, Final Vref 26
7746 16:44:03.628704
7747 16:44:03.632289 Final TX Range 0 Vref 26
7748 16:44:03.632371
7749 16:44:03.632435 ==
7750 16:44:03.635376 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 16:44:03.638563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 16:44:03.638666 ==
7753 16:44:03.638772
7754 16:44:03.638920
7755 16:44:03.642349 TX Vref Scan disable
7756 16:44:03.648646 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7757 16:44:03.648768 == TX Byte 0 ==
7758 16:44:03.652284 u2DelayCellOfst[0]=14 cells (4 PI)
7759 16:44:03.655351 u2DelayCellOfst[1]=18 cells (5 PI)
7760 16:44:03.658581 u2DelayCellOfst[2]=14 cells (4 PI)
7761 16:44:03.662189 u2DelayCellOfst[3]=14 cells (4 PI)
7762 16:44:03.665786 u2DelayCellOfst[4]=11 cells (3 PI)
7763 16:44:03.668739 u2DelayCellOfst[5]=0 cells (0 PI)
7764 16:44:03.672349 u2DelayCellOfst[6]=18 cells (5 PI)
7765 16:44:03.675410 u2DelayCellOfst[7]=22 cells (6 PI)
7766 16:44:03.678454 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7767 16:44:03.682132 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7768 16:44:03.684989 == TX Byte 1 ==
7769 16:44:03.688616 u2DelayCellOfst[8]=0 cells (0 PI)
7770 16:44:03.691671 u2DelayCellOfst[9]=0 cells (0 PI)
7771 16:44:03.691754 u2DelayCellOfst[10]=3 cells (1 PI)
7772 16:44:03.695282 u2DelayCellOfst[11]=0 cells (0 PI)
7773 16:44:03.698166 u2DelayCellOfst[12]=7 cells (2 PI)
7774 16:44:03.701655 u2DelayCellOfst[13]=7 cells (2 PI)
7775 16:44:03.705212 u2DelayCellOfst[14]=11 cells (3 PI)
7776 16:44:03.708402 u2DelayCellOfst[15]=11 cells (3 PI)
7777 16:44:03.715003 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7778 16:44:03.718172 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7779 16:44:03.718319 DramC Write-DBI on
7780 16:44:03.718405 ==
7781 16:44:03.721232 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 16:44:03.727874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 16:44:03.727965 ==
7784 16:44:03.728051
7785 16:44:03.728142
7786 16:44:03.731064 TX Vref Scan disable
7787 16:44:03.731161 == TX Byte 0 ==
7788 16:44:03.737671 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7789 16:44:03.737808 == TX Byte 1 ==
7790 16:44:03.741337 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7791 16:44:03.744557 DramC Write-DBI off
7792 16:44:03.744651
7793 16:44:03.744734 [DATLAT]
7794 16:44:03.747505 Freq=1600, CH0 RK0
7795 16:44:03.747590
7796 16:44:03.747656 DATLAT Default: 0xf
7797 16:44:03.751149 0, 0xFFFF, sum = 0
7798 16:44:03.751233 1, 0xFFFF, sum = 0
7799 16:44:03.754180 2, 0xFFFF, sum = 0
7800 16:44:03.754264 3, 0xFFFF, sum = 0
7801 16:44:03.757785 4, 0xFFFF, sum = 0
7802 16:44:03.757861 5, 0xFFFF, sum = 0
7803 16:44:03.760898 6, 0xFFFF, sum = 0
7804 16:44:03.760982 7, 0xFFFF, sum = 0
7805 16:44:03.764387 8, 0xFFFF, sum = 0
7806 16:44:03.764471 9, 0xFFFF, sum = 0
7807 16:44:03.767821 10, 0xFFFF, sum = 0
7808 16:44:03.770657 11, 0xFFFF, sum = 0
7809 16:44:03.770776 12, 0xFFFF, sum = 0
7810 16:44:03.774173 13, 0xFFFF, sum = 0
7811 16:44:03.774257 14, 0x0, sum = 1
7812 16:44:03.777814 15, 0x0, sum = 2
7813 16:44:03.777898 16, 0x0, sum = 3
7814 16:44:03.780766 17, 0x0, sum = 4
7815 16:44:03.780850 best_step = 15
7816 16:44:03.780915
7817 16:44:03.780976 ==
7818 16:44:03.784350 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 16:44:03.787340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 16:44:03.787456 ==
7821 16:44:03.790937 RX Vref Scan: 1
7822 16:44:03.791049
7823 16:44:03.793924 Set Vref Range= 24 -> 127
7824 16:44:03.794032
7825 16:44:03.794112 RX Vref 24 -> 127, step: 1
7826 16:44:03.794183
7827 16:44:03.797501 RX Delay 11 -> 252, step: 4
7828 16:44:03.797583
7829 16:44:03.800984 Set Vref, RX VrefLevel [Byte0]: 24
7830 16:44:03.804042 [Byte1]: 24
7831 16:44:03.807719
7832 16:44:03.807801 Set Vref, RX VrefLevel [Byte0]: 25
7833 16:44:03.810644 [Byte1]: 25
7834 16:44:03.814856
7835 16:44:03.814964 Set Vref, RX VrefLevel [Byte0]: 26
7836 16:44:03.818541 [Byte1]: 26
7837 16:44:03.822803
7838 16:44:03.822885 Set Vref, RX VrefLevel [Byte0]: 27
7839 16:44:03.825922 [Byte1]: 27
7840 16:44:03.830228
7841 16:44:03.830311 Set Vref, RX VrefLevel [Byte0]: 28
7842 16:44:03.833765 [Byte1]: 28
7843 16:44:03.838052
7844 16:44:03.838136 Set Vref, RX VrefLevel [Byte0]: 29
7845 16:44:03.840969 [Byte1]: 29
7846 16:44:03.845293
7847 16:44:03.845376 Set Vref, RX VrefLevel [Byte0]: 30
7848 16:44:03.848918 [Byte1]: 30
7849 16:44:03.853147
7850 16:44:03.853229 Set Vref, RX VrefLevel [Byte0]: 31
7851 16:44:03.856324 [Byte1]: 31
7852 16:44:03.860648
7853 16:44:03.860732 Set Vref, RX VrefLevel [Byte0]: 32
7854 16:44:03.864254 [Byte1]: 32
7855 16:44:03.868515
7856 16:44:03.868598 Set Vref, RX VrefLevel [Byte0]: 33
7857 16:44:03.871547 [Byte1]: 33
7858 16:44:03.876071
7859 16:44:03.876154 Set Vref, RX VrefLevel [Byte0]: 34
7860 16:44:03.878929 [Byte1]: 34
7861 16:44:03.883869
7862 16:44:03.883951 Set Vref, RX VrefLevel [Byte0]: 35
7863 16:44:03.886730 [Byte1]: 35
7864 16:44:03.890915
7865 16:44:03.890999 Set Vref, RX VrefLevel [Byte0]: 36
7866 16:44:03.894584 [Byte1]: 36
7867 16:44:03.898809
7868 16:44:03.898892 Set Vref, RX VrefLevel [Byte0]: 37
7869 16:44:03.901847 [Byte1]: 37
7870 16:44:03.906596
7871 16:44:03.906681 Set Vref, RX VrefLevel [Byte0]: 38
7872 16:44:03.909569 [Byte1]: 38
7873 16:44:03.913840
7874 16:44:03.913913 Set Vref, RX VrefLevel [Byte0]: 39
7875 16:44:03.917393 [Byte1]: 39
7876 16:44:03.921635
7877 16:44:03.921707 Set Vref, RX VrefLevel [Byte0]: 40
7878 16:44:03.924785 [Byte1]: 40
7879 16:44:03.929199
7880 16:44:03.929285 Set Vref, RX VrefLevel [Byte0]: 41
7881 16:44:03.932281 [Byte1]: 41
7882 16:44:03.937191
7883 16:44:03.937301 Set Vref, RX VrefLevel [Byte0]: 42
7884 16:44:03.940120 [Byte1]: 42
7885 16:44:03.944360
7886 16:44:03.944462 Set Vref, RX VrefLevel [Byte0]: 43
7887 16:44:03.947649 [Byte1]: 43
7888 16:44:03.951836
7889 16:44:03.951929 Set Vref, RX VrefLevel [Byte0]: 44
7890 16:44:03.955036 [Byte1]: 44
7891 16:44:03.959545
7892 16:44:03.959631 Set Vref, RX VrefLevel [Byte0]: 45
7893 16:44:03.962802 [Byte1]: 45
7894 16:44:03.967198
7895 16:44:03.967285 Set Vref, RX VrefLevel [Byte0]: 46
7896 16:44:03.970845 [Byte1]: 46
7897 16:44:03.974843
7898 16:44:03.974958 Set Vref, RX VrefLevel [Byte0]: 47
7899 16:44:03.977925 [Byte1]: 47
7900 16:44:03.982705
7901 16:44:03.982818 Set Vref, RX VrefLevel [Byte0]: 48
7902 16:44:03.985787 [Byte1]: 48
7903 16:44:03.990209
7904 16:44:03.990318 Set Vref, RX VrefLevel [Byte0]: 49
7905 16:44:03.993186 [Byte1]: 49
7906 16:44:03.997983
7907 16:44:03.998088 Set Vref, RX VrefLevel [Byte0]: 50
7908 16:44:04.000914 [Byte1]: 50
7909 16:44:04.005225
7910 16:44:04.005309 Set Vref, RX VrefLevel [Byte0]: 51
7911 16:44:04.008339 [Byte1]: 51
7912 16:44:04.013044
7913 16:44:04.013129 Set Vref, RX VrefLevel [Byte0]: 52
7914 16:44:04.016065 [Byte1]: 52
7915 16:44:04.020891
7916 16:44:04.020975 Set Vref, RX VrefLevel [Byte0]: 53
7917 16:44:04.023996 [Byte1]: 53
7918 16:44:04.028377
7919 16:44:04.028461 Set Vref, RX VrefLevel [Byte0]: 54
7920 16:44:04.031562 [Byte1]: 54
7921 16:44:04.035999
7922 16:44:04.036088 Set Vref, RX VrefLevel [Byte0]: 55
7923 16:44:04.039067 [Byte1]: 55
7924 16:44:04.043277
7925 16:44:04.043363 Set Vref, RX VrefLevel [Byte0]: 56
7926 16:44:04.046866 [Byte1]: 56
7927 16:44:04.051181
7928 16:44:04.051266 Set Vref, RX VrefLevel [Byte0]: 57
7929 16:44:04.054392 [Byte1]: 57
7930 16:44:04.058793
7931 16:44:04.058878 Set Vref, RX VrefLevel [Byte0]: 58
7932 16:44:04.061845 [Byte1]: 58
7933 16:44:04.066253
7934 16:44:04.066337 Set Vref, RX VrefLevel [Byte0]: 59
7935 16:44:04.069932 [Byte1]: 59
7936 16:44:04.074132
7937 16:44:04.074216 Set Vref, RX VrefLevel [Byte0]: 60
7938 16:44:04.077095 [Byte1]: 60
7939 16:44:04.081718
7940 16:44:04.081806 Set Vref, RX VrefLevel [Byte0]: 61
7941 16:44:04.084550 [Byte1]: 61
7942 16:44:04.088951
7943 16:44:04.089033 Set Vref, RX VrefLevel [Byte0]: 62
7944 16:44:04.092685 [Byte1]: 62
7945 16:44:04.097012
7946 16:44:04.097122 Set Vref, RX VrefLevel [Byte0]: 63
7947 16:44:04.099834 [Byte1]: 63
7948 16:44:04.104208
7949 16:44:04.104321 Set Vref, RX VrefLevel [Byte0]: 64
7950 16:44:04.107785 [Byte1]: 64
7951 16:44:04.111892
7952 16:44:04.111969 Set Vref, RX VrefLevel [Byte0]: 65
7953 16:44:04.115787 [Byte1]: 65
7954 16:44:04.119359
7955 16:44:04.119466 Set Vref, RX VrefLevel [Byte0]: 66
7956 16:44:04.122833 [Byte1]: 66
7957 16:44:04.127141
7958 16:44:04.127252 Set Vref, RX VrefLevel [Byte0]: 67
7959 16:44:04.130251 [Byte1]: 67
7960 16:44:04.134644
7961 16:44:04.134754 Set Vref, RX VrefLevel [Byte0]: 68
7962 16:44:04.138333 [Byte1]: 68
7963 16:44:04.142549
7964 16:44:04.142660 Set Vref, RX VrefLevel [Byte0]: 69
7965 16:44:04.145509 [Byte1]: 69
7966 16:44:04.149647
7967 16:44:04.149761 Set Vref, RX VrefLevel [Byte0]: 70
7968 16:44:04.153463 [Byte1]: 70
7969 16:44:04.157680
7970 16:44:04.157788 Set Vref, RX VrefLevel [Byte0]: 71
7971 16:44:04.160831 [Byte1]: 71
7972 16:44:04.165201
7973 16:44:04.165310 Set Vref, RX VrefLevel [Byte0]: 72
7974 16:44:04.168391 [Byte1]: 72
7975 16:44:04.172807
7976 16:44:04.172909 Set Vref, RX VrefLevel [Byte0]: 73
7977 16:44:04.175957 [Byte1]: 73
7978 16:44:04.180225
7979 16:44:04.180343 Set Vref, RX VrefLevel [Byte0]: 74
7980 16:44:04.183919 [Byte1]: 74
7981 16:44:04.188056
7982 16:44:04.188165 Set Vref, RX VrefLevel [Byte0]: 75
7983 16:44:04.194380 [Byte1]: 75
7984 16:44:04.194489
7985 16:44:04.198156 Set Vref, RX VrefLevel [Byte0]: 76
7986 16:44:04.201086 [Byte1]: 76
7987 16:44:04.201191
7988 16:44:04.204060 Set Vref, RX VrefLevel [Byte0]: 77
7989 16:44:04.207882 [Byte1]: 77
7990 16:44:04.210795
7991 16:44:04.210904 Set Vref, RX VrefLevel [Byte0]: 78
7992 16:44:04.214620 [Byte1]: 78
7993 16:44:04.218615
7994 16:44:04.218722 Set Vref, RX VrefLevel [Byte0]: 79
7995 16:44:04.221652 [Byte1]: 79
7996 16:44:04.225865
7997 16:44:04.225981 Final RX Vref Byte 0 = 69 to rank0
7998 16:44:04.229547 Final RX Vref Byte 1 = 58 to rank0
7999 16:44:04.232893 Final RX Vref Byte 0 = 69 to rank1
8000 16:44:04.235836 Final RX Vref Byte 1 = 58 to rank1==
8001 16:44:04.239481 Dram Type= 6, Freq= 0, CH_0, rank 0
8002 16:44:04.245898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 16:44:04.246024 ==
8004 16:44:04.246121 DQS Delay:
8005 16:44:04.246195 DQS0 = 0, DQS1 = 0
8006 16:44:04.249578 DQM Delay:
8007 16:44:04.249686 DQM0 = 134, DQM1 = 122
8008 16:44:04.252813 DQ Delay:
8009 16:44:04.255774 DQ0 =132, DQ1 =138, DQ2 =132, DQ3 =134
8010 16:44:04.259117 DQ4 =134, DQ5 =122, DQ6 =142, DQ7 =144
8011 16:44:04.262640 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =118
8012 16:44:04.265688 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8013 16:44:04.265794
8014 16:44:04.265898
8015 16:44:04.266001
8016 16:44:04.269470 [DramC_TX_OE_Calibration] TA2
8017 16:44:04.272698 Original DQ_B0 (3 6) =30, OEN = 27
8018 16:44:04.275919 Original DQ_B1 (3 6) =30, OEN = 27
8019 16:44:04.278858 24, 0x0, End_B0=24 End_B1=24
8020 16:44:04.278967 25, 0x0, End_B0=25 End_B1=25
8021 16:44:04.282476 26, 0x0, End_B0=26 End_B1=26
8022 16:44:04.285575 27, 0x0, End_B0=27 End_B1=27
8023 16:44:04.288940 28, 0x0, End_B0=28 End_B1=28
8024 16:44:04.292307 29, 0x0, End_B0=29 End_B1=29
8025 16:44:04.292385 30, 0x0, End_B0=30 End_B1=30
8026 16:44:04.295296 31, 0x4141, End_B0=30 End_B1=30
8027 16:44:04.299136 Byte0 end_step=30 best_step=27
8028 16:44:04.302292 Byte1 end_step=30 best_step=27
8029 16:44:04.305658 Byte0 TX OE(2T, 0.5T) = (3, 3)
8030 16:44:04.308663 Byte1 TX OE(2T, 0.5T) = (3, 3)
8031 16:44:04.308766
8032 16:44:04.308862
8033 16:44:04.315351 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8034 16:44:04.318367 CH0 RK0: MR19=303, MR18=2112
8035 16:44:04.325580 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8036 16:44:04.325690
8037 16:44:04.328575 ----->DramcWriteLeveling(PI) begin...
8038 16:44:04.328683 ==
8039 16:44:04.331581 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 16:44:04.335182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 16:44:04.335268 ==
8042 16:44:04.338243 Write leveling (Byte 0): 37 => 37
8043 16:44:04.341992 Write leveling (Byte 1): 27 => 27
8044 16:44:04.345103 DramcWriteLeveling(PI) end<-----
8045 16:44:04.345187
8046 16:44:04.345253 ==
8047 16:44:04.348661 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 16:44:04.351926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 16:44:04.354698 ==
8050 16:44:04.354785 [Gating] SW mode calibration
8051 16:44:04.365212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8052 16:44:04.368216 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8053 16:44:04.371267 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 16:44:04.377922 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 16:44:04.381632 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 16:44:04.384662 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 16:44:04.391352 1 4 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8058 16:44:04.394218 1 4 20 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
8059 16:44:04.397771 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 16:44:04.404485 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 16:44:04.407776 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 16:44:04.410985 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 16:44:04.417687 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 16:44:04.421260 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
8065 16:44:04.424397 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
8066 16:44:04.430683 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8067 16:44:04.434429 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 16:44:04.437225 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 16:44:04.444409 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 16:44:04.447387 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 16:44:04.450916 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 16:44:04.457658 1 6 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8073 16:44:04.460703 1 6 16 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
8074 16:44:04.464248 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 16:44:04.470420 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 16:44:04.474168 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 16:44:04.477125 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 16:44:04.483923 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 16:44:04.487117 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 16:44:04.490534 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8081 16:44:04.497101 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8082 16:44:04.500639 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 16:44:04.503584 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 16:44:04.510190 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 16:44:04.513725 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 16:44:04.516619 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 16:44:04.523415 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 16:44:04.526917 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 16:44:04.529869 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 16:44:04.536409 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 16:44:04.539993 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 16:44:04.543504 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 16:44:04.549694 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 16:44:04.553436 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8095 16:44:04.556750 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8096 16:44:04.563033 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8097 16:44:04.566006 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8098 16:44:04.569651 Total UI for P1: 0, mck2ui 16
8099 16:44:04.572847 best dqsien dly found for B0: ( 1, 9, 8)
8100 16:44:04.576377 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 16:44:04.579725 Total UI for P1: 0, mck2ui 16
8102 16:44:04.582865 best dqsien dly found for B1: ( 1, 9, 16)
8103 16:44:04.585893 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8104 16:44:04.589433 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8105 16:44:04.590063
8106 16:44:04.595628 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8107 16:44:04.599384 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8108 16:44:04.602249 [Gating] SW calibration Done
8109 16:44:04.602880 ==
8110 16:44:04.605595 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 16:44:04.609184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 16:44:04.609792 ==
8113 16:44:04.610322 RX Vref Scan: 0
8114 16:44:04.610824
8115 16:44:04.612296 RX Vref 0 -> 0, step: 1
8116 16:44:04.612829
8117 16:44:04.615917 RX Delay 0 -> 252, step: 8
8118 16:44:04.619217 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8119 16:44:04.622147 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8120 16:44:04.628785 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8121 16:44:04.632402 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8122 16:44:04.635788 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8123 16:44:04.638759 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8124 16:44:04.642295 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8125 16:44:04.648853 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8126 16:44:04.651869 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8127 16:44:04.655054 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8128 16:44:04.658149 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8129 16:44:04.662028 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8130 16:44:04.668218 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8131 16:44:04.671831 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8132 16:44:04.674814 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8133 16:44:04.677894 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8134 16:44:04.677999 ==
8135 16:44:04.681647 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 16:44:04.687925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 16:44:04.688031 ==
8138 16:44:04.688128 DQS Delay:
8139 16:44:04.691575 DQS0 = 0, DQS1 = 0
8140 16:44:04.691684 DQM Delay:
8141 16:44:04.694714 DQM0 = 133, DQM1 = 129
8142 16:44:04.694817 DQ Delay:
8143 16:44:04.697692 DQ0 =131, DQ1 =139, DQ2 =127, DQ3 =127
8144 16:44:04.700830 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8145 16:44:04.704633 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8146 16:44:04.707450 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8147 16:44:04.707528
8148 16:44:04.707592
8149 16:44:04.707652 ==
8150 16:44:04.711009 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 16:44:04.717755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 16:44:04.717861 ==
8153 16:44:04.717956
8154 16:44:04.718064
8155 16:44:04.718155 TX Vref Scan disable
8156 16:44:04.721146 == TX Byte 0 ==
8157 16:44:04.724634 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8158 16:44:04.730743 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8159 16:44:04.730849 == TX Byte 1 ==
8160 16:44:04.734318 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8161 16:44:04.740812 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8162 16:44:04.740946 ==
8163 16:44:04.744431 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 16:44:04.747375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 16:44:04.747529 ==
8166 16:44:04.760028
8167 16:44:04.762934 TX Vref early break, caculate TX vref
8168 16:44:04.766374 TX Vref=16, minBit 3, minWin=22, winSum=375
8169 16:44:04.770013 TX Vref=18, minBit 0, minWin=23, winSum=385
8170 16:44:04.773120 TX Vref=20, minBit 1, minWin=23, winSum=394
8171 16:44:04.776253 TX Vref=22, minBit 0, minWin=24, winSum=400
8172 16:44:04.780038 TX Vref=24, minBit 3, minWin=24, winSum=410
8173 16:44:04.786514 TX Vref=26, minBit 1, minWin=24, winSum=416
8174 16:44:04.789699 TX Vref=28, minBit 1, minWin=24, winSum=412
8175 16:44:04.792829 TX Vref=30, minBit 0, minWin=24, winSum=400
8176 16:44:04.796607 TX Vref=32, minBit 0, minWin=24, winSum=393
8177 16:44:04.802782 [TxChooseVref] Worse bit 1, Min win 24, Win sum 416, Final Vref 26
8178 16:44:04.803535
8179 16:44:04.806500 Final TX Range 0 Vref 26
8180 16:44:04.806931
8181 16:44:04.807506 ==
8182 16:44:04.809366 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 16:44:04.812982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 16:44:04.813420 ==
8185 16:44:04.813756
8186 16:44:04.814064
8187 16:44:04.815814 TX Vref Scan disable
8188 16:44:04.822676 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8189 16:44:04.822996 == TX Byte 0 ==
8190 16:44:04.825582 u2DelayCellOfst[0]=11 cells (3 PI)
8191 16:44:04.829159 u2DelayCellOfst[1]=18 cells (5 PI)
8192 16:44:04.832145 u2DelayCellOfst[2]=11 cells (3 PI)
8193 16:44:04.835175 u2DelayCellOfst[3]=14 cells (4 PI)
8194 16:44:04.838703 u2DelayCellOfst[4]=7 cells (2 PI)
8195 16:44:04.842191 u2DelayCellOfst[5]=0 cells (0 PI)
8196 16:44:04.845347 u2DelayCellOfst[6]=14 cells (4 PI)
8197 16:44:04.848813 u2DelayCellOfst[7]=14 cells (4 PI)
8198 16:44:04.851826 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8199 16:44:04.855329 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8200 16:44:04.858307 == TX Byte 1 ==
8201 16:44:04.861951 u2DelayCellOfst[8]=0 cells (0 PI)
8202 16:44:04.862063 u2DelayCellOfst[9]=3 cells (1 PI)
8203 16:44:04.865025 u2DelayCellOfst[10]=7 cells (2 PI)
8204 16:44:04.868811 u2DelayCellOfst[11]=3 cells (1 PI)
8205 16:44:04.871794 u2DelayCellOfst[12]=11 cells (3 PI)
8206 16:44:04.874959 u2DelayCellOfst[13]=11 cells (3 PI)
8207 16:44:04.878639 u2DelayCellOfst[14]=14 cells (4 PI)
8208 16:44:04.881640 u2DelayCellOfst[15]=11 cells (3 PI)
8209 16:44:04.884773 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8210 16:44:04.891719 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8211 16:44:04.891832 DramC Write-DBI on
8212 16:44:04.891929 ==
8213 16:44:04.894811 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 16:44:04.901592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 16:44:04.901677 ==
8216 16:44:04.901743
8217 16:44:04.901805
8218 16:44:04.901863 TX Vref Scan disable
8219 16:44:04.905344 == TX Byte 0 ==
8220 16:44:04.908964 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8221 16:44:04.911889 == TX Byte 1 ==
8222 16:44:04.915559 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8223 16:44:04.918466 DramC Write-DBI off
8224 16:44:04.918576
8225 16:44:04.918675 [DATLAT]
8226 16:44:04.918769 Freq=1600, CH0 RK1
8227 16:44:04.918859
8228 16:44:04.922058 DATLAT Default: 0xf
8229 16:44:04.925097 0, 0xFFFF, sum = 0
8230 16:44:04.925210 1, 0xFFFF, sum = 0
8231 16:44:04.928509 2, 0xFFFF, sum = 0
8232 16:44:04.928622 3, 0xFFFF, sum = 0
8233 16:44:04.931816 4, 0xFFFF, sum = 0
8234 16:44:04.931929 5, 0xFFFF, sum = 0
8235 16:44:04.934833 6, 0xFFFF, sum = 0
8236 16:44:04.934936 7, 0xFFFF, sum = 0
8237 16:44:04.938413 8, 0xFFFF, sum = 0
8238 16:44:04.938518 9, 0xFFFF, sum = 0
8239 16:44:04.941491 10, 0xFFFF, sum = 0
8240 16:44:04.941597 11, 0xFFFF, sum = 0
8241 16:44:04.945089 12, 0xFFFF, sum = 0
8242 16:44:04.945205 13, 0xFFFF, sum = 0
8243 16:44:04.948122 14, 0x0, sum = 1
8244 16:44:04.948235 15, 0x0, sum = 2
8245 16:44:04.951338 16, 0x0, sum = 3
8246 16:44:04.951473 17, 0x0, sum = 4
8247 16:44:04.954778 best_step = 15
8248 16:44:04.954922
8249 16:44:04.955029 ==
8250 16:44:04.958190 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 16:44:04.961214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 16:44:04.961339 ==
8253 16:44:04.964914 RX Vref Scan: 0
8254 16:44:04.965065
8255 16:44:04.965183 RX Vref 0 -> 0, step: 1
8256 16:44:04.965285
8257 16:44:04.967979 RX Delay 11 -> 252, step: 4
8258 16:44:04.974650 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8259 16:44:04.977882 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8260 16:44:04.981328 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8261 16:44:04.984841 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8262 16:44:04.987889 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8263 16:44:04.994602 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8264 16:44:04.997722 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8265 16:44:05.001336 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8266 16:44:05.004451 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8267 16:44:05.007629 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8268 16:44:05.014280 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8269 16:44:05.017951 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8270 16:44:05.020849 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8271 16:44:05.024622 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8272 16:44:05.030910 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8273 16:44:05.034451 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8274 16:44:05.034769 ==
8275 16:44:05.037343 Dram Type= 6, Freq= 0, CH_0, rank 1
8276 16:44:05.041237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 16:44:05.041577 ==
8278 16:44:05.041869 DQS Delay:
8279 16:44:05.044050 DQS0 = 0, DQS1 = 0
8280 16:44:05.044279 DQM Delay:
8281 16:44:05.047615 DQM0 = 130, DQM1 = 126
8282 16:44:05.047973 DQ Delay:
8283 16:44:05.050625 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =128
8284 16:44:05.053944 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8285 16:44:05.057150 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8286 16:44:05.064295 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =134
8287 16:44:05.064588
8288 16:44:05.064832
8289 16:44:05.065064
8290 16:44:05.067045 [DramC_TX_OE_Calibration] TA2
8291 16:44:05.067289 Original DQ_B0 (3 6) =30, OEN = 27
8292 16:44:05.070653 Original DQ_B1 (3 6) =30, OEN = 27
8293 16:44:05.073639 24, 0x0, End_B0=24 End_B1=24
8294 16:44:05.077417 25, 0x0, End_B0=25 End_B1=25
8295 16:44:05.080692 26, 0x0, End_B0=26 End_B1=26
8296 16:44:05.083792 27, 0x0, End_B0=27 End_B1=27
8297 16:44:05.084067 28, 0x0, End_B0=28 End_B1=28
8298 16:44:05.087135 29, 0x0, End_B0=29 End_B1=29
8299 16:44:05.090147 30, 0x0, End_B0=30 End_B1=30
8300 16:44:05.093895 31, 0x4141, End_B0=30 End_B1=30
8301 16:44:05.097056 Byte0 end_step=30 best_step=27
8302 16:44:05.097142 Byte1 end_step=30 best_step=27
8303 16:44:05.100131 Byte0 TX OE(2T, 0.5T) = (3, 3)
8304 16:44:05.103815 Byte1 TX OE(2T, 0.5T) = (3, 3)
8305 16:44:05.103928
8306 16:44:05.104023
8307 16:44:05.113914 [DQSOSCAuto] RK1, (LSB)MR18= 0x2205, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
8308 16:44:05.114025 CH0 RK1: MR19=303, MR18=2205
8309 16:44:05.120121 CH0_RK1: MR19=0x303, MR18=0x2205, DQSOSC=392, MR23=63, INC=24, DEC=16
8310 16:44:05.123668 [RxdqsGatingPostProcess] freq 1600
8311 16:44:05.130246 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8312 16:44:05.133347 best DQS0 dly(2T, 0.5T) = (1, 1)
8313 16:44:05.136380 best DQS1 dly(2T, 0.5T) = (1, 1)
8314 16:44:05.140064 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8315 16:44:05.143040 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8316 16:44:05.146863 best DQS0 dly(2T, 0.5T) = (1, 1)
8317 16:44:05.147009 best DQS1 dly(2T, 0.5T) = (1, 1)
8318 16:44:05.149956 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8319 16:44:05.153345 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8320 16:44:05.156432 Pre-setting of DQS Precalculation
8321 16:44:05.163082 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8322 16:44:05.163247 ==
8323 16:44:05.166680 Dram Type= 6, Freq= 0, CH_1, rank 0
8324 16:44:05.169642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 16:44:05.169948 ==
8326 16:44:05.176512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8327 16:44:05.179572 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8328 16:44:05.182897 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8329 16:44:05.189440 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8330 16:44:05.198814 [CA 0] Center 41 (12~71) winsize 60
8331 16:44:05.201896 [CA 1] Center 42 (13~72) winsize 60
8332 16:44:05.205484 [CA 2] Center 36 (7~66) winsize 60
8333 16:44:05.208619 [CA 3] Center 36 (7~65) winsize 59
8334 16:44:05.211657 [CA 4] Center 36 (7~66) winsize 60
8335 16:44:05.215339 [CA 5] Center 36 (7~66) winsize 60
8336 16:44:05.215419
8337 16:44:05.218347 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8338 16:44:05.218454
8339 16:44:05.224934 [CATrainingPosCal] consider 1 rank data
8340 16:44:05.225015 u2DelayCellTimex100 = 262/100 ps
8341 16:44:05.231668 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8342 16:44:05.234763 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8343 16:44:05.238515 CA2 delay=36 (7~66),Diff = 0 PI (0 cell)
8344 16:44:05.241371 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8345 16:44:05.244865 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8346 16:44:05.247860 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8347 16:44:05.247941
8348 16:44:05.251372 CA PerBit enable=1, Macro0, CA PI delay=36
8349 16:44:05.251453
8350 16:44:05.254364 [CBTSetCACLKResult] CA Dly = 36
8351 16:44:05.257900 CS Dly: 10 (0~41)
8352 16:44:05.261384 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8353 16:44:05.264383 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8354 16:44:05.264464 ==
8355 16:44:05.268061 Dram Type= 6, Freq= 0, CH_1, rank 1
8356 16:44:05.274454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 16:44:05.274549 ==
8358 16:44:05.277912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8359 16:44:05.284296 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8360 16:44:05.287833 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8361 16:44:05.293925 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8362 16:44:05.301760 [CA 0] Center 43 (14~72) winsize 59
8363 16:44:05.305470 [CA 1] Center 42 (13~72) winsize 60
8364 16:44:05.308431 [CA 2] Center 37 (8~67) winsize 60
8365 16:44:05.311600 [CA 3] Center 37 (8~67) winsize 60
8366 16:44:05.315278 [CA 4] Center 37 (8~67) winsize 60
8367 16:44:05.318246 [CA 5] Center 37 (8~67) winsize 60
8368 16:44:05.318327
8369 16:44:05.321901 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8370 16:44:05.321988
8371 16:44:05.325082 [CATrainingPosCal] consider 2 rank data
8372 16:44:05.328584 u2DelayCellTimex100 = 262/100 ps
8373 16:44:05.335229 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8374 16:44:05.338263 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8375 16:44:05.341993 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8376 16:44:05.345044 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8377 16:44:05.348362 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8378 16:44:05.351790 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8379 16:44:05.351870
8380 16:44:05.354647 CA PerBit enable=1, Macro0, CA PI delay=36
8381 16:44:05.354727
8382 16:44:05.358298 [CBTSetCACLKResult] CA Dly = 36
8383 16:44:05.361365 CS Dly: 11 (0~43)
8384 16:44:05.364901 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8385 16:44:05.368178 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8386 16:44:05.368257
8387 16:44:05.371683 ----->DramcWriteLeveling(PI) begin...
8388 16:44:05.371771 ==
8389 16:44:05.374880 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 16:44:05.381532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 16:44:05.381628 ==
8392 16:44:05.384630 Write leveling (Byte 0): 23 => 23
8393 16:44:05.387683 Write leveling (Byte 1): 28 => 28
8394 16:44:05.387756 DramcWriteLeveling(PI) end<-----
8395 16:44:05.387827
8396 16:44:05.390837 ==
8397 16:44:05.394575 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 16:44:05.397731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 16:44:05.397803 ==
8400 16:44:05.401256 [Gating] SW mode calibration
8401 16:44:05.407941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8402 16:44:05.411209 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8403 16:44:05.417998 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 16:44:05.421390 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 16:44:05.424521 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 16:44:05.431083 1 4 12 | B1->B0 | 3231 3434 | 1 0 | (1 1) (0 0)
8407 16:44:05.434518 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 16:44:05.437926 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 16:44:05.444444 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 16:44:05.447604 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 16:44:05.451127 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 16:44:05.457426 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 16:44:05.461056 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8414 16:44:05.463894 1 5 12 | B1->B0 | 2c2c 2525 | 0 0 | (1 0) (0 1)
8415 16:44:05.470912 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 16:44:05.473786 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 16:44:05.477307 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 16:44:05.483775 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 16:44:05.487334 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 16:44:05.490516 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 16:44:05.497111 1 6 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8422 16:44:05.499896 1 6 12 | B1->B0 | 3f3e 4646 | 1 0 | (0 0) (0 0)
8423 16:44:05.503122 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 16:44:05.509713 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 16:44:05.513471 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 16:44:05.516592 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 16:44:05.523297 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 16:44:05.526854 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 16:44:05.530063 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8430 16:44:05.536683 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8431 16:44:05.539725 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8432 16:44:05.543311 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 16:44:05.549506 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 16:44:05.553220 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 16:44:05.556716 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 16:44:05.563679 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 16:44:05.566868 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 16:44:05.569975 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 16:44:05.576405 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 16:44:05.579705 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 16:44:05.583324 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 16:44:05.589708 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 16:44:05.593431 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 16:44:05.596555 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 16:44:05.603289 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 16:44:05.606208 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8447 16:44:05.609770 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8448 16:44:05.612786 Total UI for P1: 0, mck2ui 16
8449 16:44:05.616473 best dqsien dly found for B0: ( 1, 9, 12)
8450 16:44:05.619520 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 16:44:05.623173 Total UI for P1: 0, mck2ui 16
8452 16:44:05.626324 best dqsien dly found for B1: ( 1, 9, 14)
8453 16:44:05.633121 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8454 16:44:05.636218 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8455 16:44:05.636645
8456 16:44:05.639787 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8457 16:44:05.642860 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8458 16:44:05.646077 [Gating] SW calibration Done
8459 16:44:05.646524 ==
8460 16:44:05.649498 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 16:44:05.652545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 16:44:05.653146 ==
8463 16:44:05.656316 RX Vref Scan: 0
8464 16:44:05.656785
8465 16:44:05.657318 RX Vref 0 -> 0, step: 1
8466 16:44:05.657817
8467 16:44:05.659140 RX Delay 0 -> 252, step: 8
8468 16:44:05.662631 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8469 16:44:05.669171 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8470 16:44:05.672272 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8471 16:44:05.675766 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8472 16:44:05.679447 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8473 16:44:05.682367 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8474 16:44:05.688683 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8475 16:44:05.692259 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8476 16:44:05.695779 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8477 16:44:05.698805 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8478 16:44:05.701797 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8479 16:44:05.708456 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8480 16:44:05.712187 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8481 16:44:05.715138 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8482 16:44:05.718406 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8483 16:44:05.725304 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8484 16:44:05.725764 ==
8485 16:44:05.728677 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 16:44:05.732226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 16:44:05.732750 ==
8488 16:44:05.733085 DQS Delay:
8489 16:44:05.735221 DQS0 = 0, DQS1 = 0
8490 16:44:05.735633 DQM Delay:
8491 16:44:05.738438 DQM0 = 137, DQM1 = 129
8492 16:44:05.738968 DQ Delay:
8493 16:44:05.741960 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8494 16:44:05.744981 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8495 16:44:05.748848 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8496 16:44:05.752005 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8497 16:44:05.752476
8498 16:44:05.752844
8499 16:44:05.754828 ==
8500 16:44:05.758337 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 16:44:05.761350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 16:44:05.761772 ==
8503 16:44:05.762108
8504 16:44:05.762593
8505 16:44:05.765008 TX Vref Scan disable
8506 16:44:05.765426 == TX Byte 0 ==
8507 16:44:05.771221 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8508 16:44:05.775006 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8509 16:44:05.775475 == TX Byte 1 ==
8510 16:44:05.781359 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8511 16:44:05.784160 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8512 16:44:05.784579 ==
8513 16:44:05.788023 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 16:44:05.791223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 16:44:05.791646 ==
8516 16:44:05.804673
8517 16:44:05.807771 TX Vref early break, caculate TX vref
8518 16:44:05.811342 TX Vref=16, minBit 0, minWin=21, winSum=370
8519 16:44:05.814449 TX Vref=18, minBit 0, minWin=22, winSum=382
8520 16:44:05.817944 TX Vref=20, minBit 0, minWin=23, winSum=390
8521 16:44:05.820985 TX Vref=22, minBit 0, minWin=23, winSum=398
8522 16:44:05.824496 TX Vref=24, minBit 5, minWin=23, winSum=408
8523 16:44:05.831176 TX Vref=26, minBit 5, minWin=24, winSum=416
8524 16:44:05.834187 TX Vref=28, minBit 0, minWin=24, winSum=411
8525 16:44:05.837496 TX Vref=30, minBit 5, minWin=24, winSum=411
8526 16:44:05.840961 TX Vref=32, minBit 0, minWin=23, winSum=396
8527 16:44:05.844114 TX Vref=34, minBit 5, minWin=22, winSum=387
8528 16:44:05.850845 [TxChooseVref] Worse bit 5, Min win 24, Win sum 416, Final Vref 26
8529 16:44:05.851304
8530 16:44:05.854221 Final TX Range 0 Vref 26
8531 16:44:05.854736
8532 16:44:05.855118 ==
8533 16:44:05.857216 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 16:44:05.860557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 16:44:05.861033 ==
8536 16:44:05.861433
8537 16:44:05.861751
8538 16:44:05.864114 TX Vref Scan disable
8539 16:44:05.870392 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8540 16:44:05.870837 == TX Byte 0 ==
8541 16:44:05.873699 u2DelayCellOfst[0]=18 cells (5 PI)
8542 16:44:05.877407 u2DelayCellOfst[1]=14 cells (4 PI)
8543 16:44:05.880412 u2DelayCellOfst[2]=0 cells (0 PI)
8544 16:44:05.883546 u2DelayCellOfst[3]=7 cells (2 PI)
8545 16:44:05.886988 u2DelayCellOfst[4]=11 cells (3 PI)
8546 16:44:05.890238 u2DelayCellOfst[5]=22 cells (6 PI)
8547 16:44:05.893482 u2DelayCellOfst[6]=22 cells (6 PI)
8548 16:44:05.896948 u2DelayCellOfst[7]=7 cells (2 PI)
8549 16:44:05.899865 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8550 16:44:05.903418 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8551 16:44:05.906927 == TX Byte 1 ==
8552 16:44:05.909901 u2DelayCellOfst[8]=0 cells (0 PI)
8553 16:44:05.913520 u2DelayCellOfst[9]=3 cells (1 PI)
8554 16:44:05.916564 u2DelayCellOfst[10]=11 cells (3 PI)
8555 16:44:05.916991 u2DelayCellOfst[11]=3 cells (1 PI)
8556 16:44:05.920226 u2DelayCellOfst[12]=14 cells (4 PI)
8557 16:44:05.923172 u2DelayCellOfst[13]=14 cells (4 PI)
8558 16:44:05.926232 u2DelayCellOfst[14]=18 cells (5 PI)
8559 16:44:05.929904 u2DelayCellOfst[15]=18 cells (5 PI)
8560 16:44:05.936073 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8561 16:44:05.939673 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8562 16:44:05.940111 DramC Write-DBI on
8563 16:44:05.942649 ==
8564 16:44:05.946384 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 16:44:05.949439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 16:44:05.949877 ==
8567 16:44:05.950336
8568 16:44:05.950743
8569 16:44:05.952627 TX Vref Scan disable
8570 16:44:05.953082 == TX Byte 0 ==
8571 16:44:05.959669 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8572 16:44:05.960246 == TX Byte 1 ==
8573 16:44:05.962468 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8574 16:44:05.966003 DramC Write-DBI off
8575 16:44:05.966468
8576 16:44:05.967026 [DATLAT]
8577 16:44:05.969541 Freq=1600, CH1 RK0
8578 16:44:05.969981
8579 16:44:05.970314 DATLAT Default: 0xf
8580 16:44:05.972642 0, 0xFFFF, sum = 0
8581 16:44:05.973067 1, 0xFFFF, sum = 0
8582 16:44:05.976126 2, 0xFFFF, sum = 0
8583 16:44:05.976549 3, 0xFFFF, sum = 0
8584 16:44:05.979186 4, 0xFFFF, sum = 0
8585 16:44:05.979608 5, 0xFFFF, sum = 0
8586 16:44:05.982730 6, 0xFFFF, sum = 0
8587 16:44:05.985859 7, 0xFFFF, sum = 0
8588 16:44:05.986280 8, 0xFFFF, sum = 0
8589 16:44:05.988904 9, 0xFFFF, sum = 0
8590 16:44:05.989395 10, 0xFFFF, sum = 0
8591 16:44:05.992499 11, 0xFFFF, sum = 0
8592 16:44:05.992950 12, 0xFFFF, sum = 0
8593 16:44:05.996045 13, 0xFFFF, sum = 0
8594 16:44:05.996500 14, 0x0, sum = 1
8595 16:44:05.998899 15, 0x0, sum = 2
8596 16:44:05.999406 16, 0x0, sum = 3
8597 16:44:06.002362 17, 0x0, sum = 4
8598 16:44:06.002809 best_step = 15
8599 16:44:06.003193
8600 16:44:06.003536 ==
8601 16:44:06.006081 Dram Type= 6, Freq= 0, CH_1, rank 0
8602 16:44:06.009042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8603 16:44:06.011981 ==
8604 16:44:06.012426 RX Vref Scan: 1
8605 16:44:06.012789
8606 16:44:06.015544 Set Vref Range= 24 -> 127
8607 16:44:06.016062
8608 16:44:06.018605 RX Vref 24 -> 127, step: 1
8609 16:44:06.019024
8610 16:44:06.019451 RX Delay 11 -> 252, step: 4
8611 16:44:06.019776
8612 16:44:06.022336 Set Vref, RX VrefLevel [Byte0]: 24
8613 16:44:06.025257 [Byte1]: 24
8614 16:44:06.029496
8615 16:44:06.030047 Set Vref, RX VrefLevel [Byte0]: 25
8616 16:44:06.032346 [Byte1]: 25
8617 16:44:06.036721
8618 16:44:06.037136 Set Vref, RX VrefLevel [Byte0]: 26
8619 16:44:06.040361 [Byte1]: 26
8620 16:44:06.044661
8621 16:44:06.045111 Set Vref, RX VrefLevel [Byte0]: 27
8622 16:44:06.047830 [Byte1]: 27
8623 16:44:06.052125
8624 16:44:06.052578 Set Vref, RX VrefLevel [Byte0]: 28
8625 16:44:06.055213 [Byte1]: 28
8626 16:44:06.059592
8627 16:44:06.060008 Set Vref, RX VrefLevel [Byte0]: 29
8628 16:44:06.063177 [Byte1]: 29
8629 16:44:06.067162
8630 16:44:06.067584 Set Vref, RX VrefLevel [Byte0]: 30
8631 16:44:06.070620 [Byte1]: 30
8632 16:44:06.074683
8633 16:44:06.075146 Set Vref, RX VrefLevel [Byte0]: 31
8634 16:44:06.078432 [Byte1]: 31
8635 16:44:06.082550
8636 16:44:06.082973 Set Vref, RX VrefLevel [Byte0]: 32
8637 16:44:06.086035 [Byte1]: 32
8638 16:44:06.090156
8639 16:44:06.090584 Set Vref, RX VrefLevel [Byte0]: 33
8640 16:44:06.093374 [Byte1]: 33
8641 16:44:06.097902
8642 16:44:06.098318 Set Vref, RX VrefLevel [Byte0]: 34
8643 16:44:06.100683 [Byte1]: 34
8644 16:44:06.105398
8645 16:44:06.105820 Set Vref, RX VrefLevel [Byte0]: 35
8646 16:44:06.108839 [Byte1]: 35
8647 16:44:06.113056
8648 16:44:06.113559 Set Vref, RX VrefLevel [Byte0]: 36
8649 16:44:06.116534 [Byte1]: 36
8650 16:44:06.120389
8651 16:44:06.120474 Set Vref, RX VrefLevel [Byte0]: 37
8652 16:44:06.123349 [Byte1]: 37
8653 16:44:06.127610
8654 16:44:06.127697 Set Vref, RX VrefLevel [Byte0]: 38
8655 16:44:06.131250 [Byte1]: 38
8656 16:44:06.135375
8657 16:44:06.135466 Set Vref, RX VrefLevel [Byte0]: 39
8658 16:44:06.138455 [Byte1]: 39
8659 16:44:06.143319
8660 16:44:06.143439 Set Vref, RX VrefLevel [Byte0]: 40
8661 16:44:06.146430 [Byte1]: 40
8662 16:44:06.150735
8663 16:44:06.150844 Set Vref, RX VrefLevel [Byte0]: 41
8664 16:44:06.154060 [Byte1]: 41
8665 16:44:06.158107
8666 16:44:06.158191 Set Vref, RX VrefLevel [Byte0]: 42
8667 16:44:06.161814 [Byte1]: 42
8668 16:44:06.166005
8669 16:44:06.166088 Set Vref, RX VrefLevel [Byte0]: 43
8670 16:44:06.168949 [Byte1]: 43
8671 16:44:06.173732
8672 16:44:06.173816 Set Vref, RX VrefLevel [Byte0]: 44
8673 16:44:06.176832 [Byte1]: 44
8674 16:44:06.181178
8675 16:44:06.181260 Set Vref, RX VrefLevel [Byte0]: 45
8676 16:44:06.184708 [Byte1]: 45
8677 16:44:06.189210
8678 16:44:06.189633 Set Vref, RX VrefLevel [Byte0]: 46
8679 16:44:06.192271 [Byte1]: 46
8680 16:44:06.196921
8681 16:44:06.197352 Set Vref, RX VrefLevel [Byte0]: 47
8682 16:44:06.199998 [Byte1]: 47
8683 16:44:06.204147
8684 16:44:06.204590 Set Vref, RX VrefLevel [Byte0]: 48
8685 16:44:06.207672 [Byte1]: 48
8686 16:44:06.211705
8687 16:44:06.212125 Set Vref, RX VrefLevel [Byte0]: 49
8688 16:44:06.215345 [Byte1]: 49
8689 16:44:06.219602
8690 16:44:06.220022 Set Vref, RX VrefLevel [Byte0]: 50
8691 16:44:06.222589 [Byte1]: 50
8692 16:44:06.226898
8693 16:44:06.227364 Set Vref, RX VrefLevel [Byte0]: 51
8694 16:44:06.230393 [Byte1]: 51
8695 16:44:06.234748
8696 16:44:06.235205 Set Vref, RX VrefLevel [Byte0]: 52
8697 16:44:06.237770 [Byte1]: 52
8698 16:44:06.242127
8699 16:44:06.242672 Set Vref, RX VrefLevel [Byte0]: 53
8700 16:44:06.245780 [Byte1]: 53
8701 16:44:06.250025
8702 16:44:06.250448 Set Vref, RX VrefLevel [Byte0]: 54
8703 16:44:06.253013 [Byte1]: 54
8704 16:44:06.257420
8705 16:44:06.257841 Set Vref, RX VrefLevel [Byte0]: 55
8706 16:44:06.260664 [Byte1]: 55
8707 16:44:06.265311
8708 16:44:06.265725 Set Vref, RX VrefLevel [Byte0]: 56
8709 16:44:06.268158 [Byte1]: 56
8710 16:44:06.272931
8711 16:44:06.273367 Set Vref, RX VrefLevel [Byte0]: 57
8712 16:44:06.275977 [Byte1]: 57
8713 16:44:06.280700
8714 16:44:06.281120 Set Vref, RX VrefLevel [Byte0]: 58
8715 16:44:06.283734 [Byte1]: 58
8716 16:44:06.287984
8717 16:44:06.288411 Set Vref, RX VrefLevel [Byte0]: 59
8718 16:44:06.291594 [Byte1]: 59
8719 16:44:06.295592
8720 16:44:06.296014 Set Vref, RX VrefLevel [Byte0]: 60
8721 16:44:06.299118 [Byte1]: 60
8722 16:44:06.303648
8723 16:44:06.304158 Set Vref, RX VrefLevel [Byte0]: 61
8724 16:44:06.306471 [Byte1]: 61
8725 16:44:06.311184
8726 16:44:06.311615 Set Vref, RX VrefLevel [Byte0]: 62
8727 16:44:06.314083 [Byte1]: 62
8728 16:44:06.318744
8729 16:44:06.319209 Set Vref, RX VrefLevel [Byte0]: 63
8730 16:44:06.321653 [Byte1]: 63
8731 16:44:06.325961
8732 16:44:06.326422 Set Vref, RX VrefLevel [Byte0]: 64
8733 16:44:06.329585 [Byte1]: 64
8734 16:44:06.333965
8735 16:44:06.334379 Set Vref, RX VrefLevel [Byte0]: 65
8736 16:44:06.337015 [Byte1]: 65
8737 16:44:06.341224
8738 16:44:06.341691 Set Vref, RX VrefLevel [Byte0]: 66
8739 16:44:06.344766 [Byte1]: 66
8740 16:44:06.349116
8741 16:44:06.349541 Set Vref, RX VrefLevel [Byte0]: 67
8742 16:44:06.352140 [Byte1]: 67
8743 16:44:06.356564
8744 16:44:06.357009 Set Vref, RX VrefLevel [Byte0]: 68
8745 16:44:06.359537 [Byte1]: 68
8746 16:44:06.363986
8747 16:44:06.364423 Set Vref, RX VrefLevel [Byte0]: 69
8748 16:44:06.367732 [Byte1]: 69
8749 16:44:06.371958
8750 16:44:06.372403 Set Vref, RX VrefLevel [Byte0]: 70
8751 16:44:06.375014 [Byte1]: 70
8752 16:44:06.379518
8753 16:44:06.379940 Set Vref, RX VrefLevel [Byte0]: 71
8754 16:44:06.382443 [Byte1]: 71
8755 16:44:06.387164
8756 16:44:06.387823 Set Vref, RX VrefLevel [Byte0]: 72
8757 16:44:06.389994 [Byte1]: 72
8758 16:44:06.394734
8759 16:44:06.395266 Final RX Vref Byte 0 = 53 to rank0
8760 16:44:06.397629 Final RX Vref Byte 1 = 60 to rank0
8761 16:44:06.401192 Final RX Vref Byte 0 = 53 to rank1
8762 16:44:06.404764 Final RX Vref Byte 1 = 60 to rank1==
8763 16:44:06.407958 Dram Type= 6, Freq= 0, CH_1, rank 0
8764 16:44:06.414221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 16:44:06.414730 ==
8766 16:44:06.415270 DQS Delay:
8767 16:44:06.415635 DQS0 = 0, DQS1 = 0
8768 16:44:06.417732 DQM Delay:
8769 16:44:06.418222 DQM0 = 133, DQM1 = 127
8770 16:44:06.421401 DQ Delay:
8771 16:44:06.424226 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8772 16:44:06.427715 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8773 16:44:06.430613 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8774 16:44:06.434313 DQ12 =136, DQ13 =134, DQ14 =136, DQ15 =138
8775 16:44:06.434883
8776 16:44:06.435324
8777 16:44:06.435655
8778 16:44:06.437410 [DramC_TX_OE_Calibration] TA2
8779 16:44:06.440974 Original DQ_B0 (3 6) =30, OEN = 27
8780 16:44:06.444058 Original DQ_B1 (3 6) =30, OEN = 27
8781 16:44:06.447654 24, 0x0, End_B0=24 End_B1=24
8782 16:44:06.448121 25, 0x0, End_B0=25 End_B1=25
8783 16:44:06.450572 26, 0x0, End_B0=26 End_B1=26
8784 16:44:06.454154 27, 0x0, End_B0=27 End_B1=27
8785 16:44:06.457228 28, 0x0, End_B0=28 End_B1=28
8786 16:44:06.460919 29, 0x0, End_B0=29 End_B1=29
8787 16:44:06.461380 30, 0x0, End_B0=30 End_B1=30
8788 16:44:06.463970 31, 0x4141, End_B0=30 End_B1=30
8789 16:44:06.467088 Byte0 end_step=30 best_step=27
8790 16:44:06.470840 Byte1 end_step=30 best_step=27
8791 16:44:06.473902 Byte0 TX OE(2T, 0.5T) = (3, 3)
8792 16:44:06.477398 Byte1 TX OE(2T, 0.5T) = (3, 3)
8793 16:44:06.477856
8794 16:44:06.478364
8795 16:44:06.483790 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8796 16:44:06.487309 CH1 RK0: MR19=303, MR18=1B10
8797 16:44:06.493534 CH1_RK0: MR19=0x303, MR18=0x1B10, DQSOSC=396, MR23=63, INC=23, DEC=15
8798 16:44:06.493952
8799 16:44:06.497155 ----->DramcWriteLeveling(PI) begin...
8800 16:44:06.497573 ==
8801 16:44:06.500561 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 16:44:06.503533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 16:44:06.503959 ==
8804 16:44:06.506878 Write leveling (Byte 0): 23 => 23
8805 16:44:06.510509 Write leveling (Byte 1): 28 => 28
8806 16:44:06.513554 DramcWriteLeveling(PI) end<-----
8807 16:44:06.513970
8808 16:44:06.514297 ==
8809 16:44:06.517194 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 16:44:06.520108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 16:44:06.520544 ==
8812 16:44:06.523856 [Gating] SW mode calibration
8813 16:44:06.530211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8814 16:44:06.536632 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8815 16:44:06.539804 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 16:44:06.546031 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 16:44:06.549674 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8818 16:44:06.552629 1 4 12 | B1->B0 | 3434 2524 | 1 1 | (1 1) (0 0)
8819 16:44:06.559837 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 16:44:06.562803 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 16:44:06.565881 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 16:44:06.572573 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 16:44:06.575674 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 16:44:06.579596 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 16:44:06.585988 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8826 16:44:06.589054 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8827 16:44:06.592490 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8828 16:44:06.598663 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 16:44:06.602284 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 16:44:06.605843 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 16:44:06.612127 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 16:44:06.615261 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 16:44:06.618914 1 6 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8834 16:44:06.625483 1 6 12 | B1->B0 | 4646 2727 | 0 0 | (0 0) (0 0)
8835 16:44:06.628397 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 16:44:06.632031 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 16:44:06.638582 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 16:44:06.641612 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 16:44:06.644708 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 16:44:06.651539 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 16:44:06.654566 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8842 16:44:06.658158 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8843 16:44:06.664913 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 16:44:06.668040 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 16:44:06.670957 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 16:44:06.678099 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 16:44:06.681232 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 16:44:06.684745 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 16:44:06.691311 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 16:44:06.694310 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 16:44:06.697822 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 16:44:06.704098 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 16:44:06.707575 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 16:44:06.710637 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 16:44:06.717033 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 16:44:06.720696 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 16:44:06.723742 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8858 16:44:06.730275 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8859 16:44:06.734027 Total UI for P1: 0, mck2ui 16
8860 16:44:06.736771 best dqsien dly found for B1: ( 1, 9, 8)
8861 16:44:06.740382 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 16:44:06.743737 Total UI for P1: 0, mck2ui 16
8863 16:44:06.746913 best dqsien dly found for B0: ( 1, 9, 12)
8864 16:44:06.750436 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8865 16:44:06.753530 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8866 16:44:06.754096
8867 16:44:06.757221 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8868 16:44:06.763683 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8869 16:44:06.764125 [Gating] SW calibration Done
8870 16:44:06.764592 ==
8871 16:44:06.766617 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 16:44:06.773546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 16:44:06.774134 ==
8874 16:44:06.774546 RX Vref Scan: 0
8875 16:44:06.774869
8876 16:44:06.776622 RX Vref 0 -> 0, step: 1
8877 16:44:06.777054
8878 16:44:06.779954 RX Delay 0 -> 252, step: 8
8879 16:44:06.782988 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8880 16:44:06.786122 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8881 16:44:06.789692 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8882 16:44:06.796215 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8883 16:44:06.799281 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8884 16:44:06.802689 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8885 16:44:06.805796 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8886 16:44:06.809446 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8887 16:44:06.815668 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8888 16:44:06.819231 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8889 16:44:06.822295 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8890 16:44:06.825893 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8891 16:44:06.828885 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8892 16:44:06.835950 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8893 16:44:06.838791 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8894 16:44:06.842429 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8895 16:44:06.842512 ==
8896 16:44:06.845251 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 16:44:06.852127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 16:44:06.852210 ==
8899 16:44:06.852276 DQS Delay:
8900 16:44:06.852335 DQS0 = 0, DQS1 = 0
8901 16:44:06.855766 DQM Delay:
8902 16:44:06.855850 DQM0 = 137, DQM1 = 130
8903 16:44:06.858785 DQ Delay:
8904 16:44:06.862338 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8905 16:44:06.865353 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8906 16:44:06.868547 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8907 16:44:06.872039 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8908 16:44:06.872146
8909 16:44:06.872221
8910 16:44:06.872290 ==
8911 16:44:06.875256 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 16:44:06.878826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 16:44:06.881924 ==
8914 16:44:06.882039
8915 16:44:06.882128
8916 16:44:06.882208 TX Vref Scan disable
8917 16:44:06.885506 == TX Byte 0 ==
8918 16:44:06.888641 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8919 16:44:06.891685 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8920 16:44:06.895375 == TX Byte 1 ==
8921 16:44:06.898283 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8922 16:44:06.901724 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8923 16:44:06.904771 ==
8924 16:44:06.908344 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 16:44:06.911415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 16:44:06.911667 ==
8927 16:44:06.924099
8928 16:44:06.927816 TX Vref early break, caculate TX vref
8929 16:44:06.930844 TX Vref=16, minBit 0, minWin=22, winSum=378
8930 16:44:06.933832 TX Vref=18, minBit 1, minWin=23, winSum=391
8931 16:44:06.937186 TX Vref=20, minBit 1, minWin=23, winSum=397
8932 16:44:06.940903 TX Vref=22, minBit 1, minWin=24, winSum=403
8933 16:44:06.944340 TX Vref=24, minBit 6, minWin=24, winSum=411
8934 16:44:06.950914 TX Vref=26, minBit 5, minWin=24, winSum=417
8935 16:44:06.954011 TX Vref=28, minBit 0, minWin=24, winSum=417
8936 16:44:06.958008 TX Vref=30, minBit 0, minWin=24, winSum=410
8937 16:44:06.960705 TX Vref=32, minBit 0, minWin=23, winSum=402
8938 16:44:06.963934 TX Vref=34, minBit 0, minWin=22, winSum=389
8939 16:44:06.970652 [TxChooseVref] Worse bit 5, Min win 24, Win sum 417, Final Vref 26
8940 16:44:06.971162
8941 16:44:06.973842 Final TX Range 0 Vref 26
8942 16:44:06.974267
8943 16:44:06.974619 ==
8944 16:44:06.977359 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 16:44:06.980575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 16:44:06.981007 ==
8947 16:44:06.981364
8948 16:44:06.981668
8949 16:44:06.983668 TX Vref Scan disable
8950 16:44:06.990208 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8951 16:44:06.990646 == TX Byte 0 ==
8952 16:44:06.993901 u2DelayCellOfst[0]=18 cells (5 PI)
8953 16:44:06.997012 u2DelayCellOfst[1]=11 cells (3 PI)
8954 16:44:07.000132 u2DelayCellOfst[2]=0 cells (0 PI)
8955 16:44:07.003736 u2DelayCellOfst[3]=7 cells (2 PI)
8956 16:44:07.007029 u2DelayCellOfst[4]=7 cells (2 PI)
8957 16:44:07.009986 u2DelayCellOfst[5]=22 cells (6 PI)
8958 16:44:07.013634 u2DelayCellOfst[6]=18 cells (5 PI)
8959 16:44:07.016630 u2DelayCellOfst[7]=3 cells (1 PI)
8960 16:44:07.020236 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8961 16:44:07.023148 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8962 16:44:07.026696 == TX Byte 1 ==
8963 16:44:07.029639 u2DelayCellOfst[8]=0 cells (0 PI)
8964 16:44:07.030052 u2DelayCellOfst[9]=7 cells (2 PI)
8965 16:44:07.033339 u2DelayCellOfst[10]=11 cells (3 PI)
8966 16:44:07.036248 u2DelayCellOfst[11]=7 cells (2 PI)
8967 16:44:07.039859 u2DelayCellOfst[12]=14 cells (4 PI)
8968 16:44:07.042731 u2DelayCellOfst[13]=18 cells (5 PI)
8969 16:44:07.046211 u2DelayCellOfst[14]=18 cells (5 PI)
8970 16:44:07.049714 u2DelayCellOfst[15]=18 cells (5 PI)
8971 16:44:07.056428 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8972 16:44:07.059436 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8973 16:44:07.059867 DramC Write-DBI on
8974 16:44:07.062573 ==
8975 16:44:07.063013 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 16:44:07.069195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 16:44:07.069613 ==
8978 16:44:07.069981
8979 16:44:07.070292
8980 16:44:07.072262 TX Vref Scan disable
8981 16:44:07.072691 == TX Byte 0 ==
8982 16:44:07.079167 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8983 16:44:07.079618 == TX Byte 1 ==
8984 16:44:07.082371 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8985 16:44:07.085920 DramC Write-DBI off
8986 16:44:07.086337
8987 16:44:07.086669 [DATLAT]
8988 16:44:07.089012 Freq=1600, CH1 RK1
8989 16:44:07.089434
8990 16:44:07.089768 DATLAT Default: 0xf
8991 16:44:07.092670 0, 0xFFFF, sum = 0
8992 16:44:07.093108 1, 0xFFFF, sum = 0
8993 16:44:07.095593 2, 0xFFFF, sum = 0
8994 16:44:07.096014 3, 0xFFFF, sum = 0
8995 16:44:07.099201 4, 0xFFFF, sum = 0
8996 16:44:07.099643 5, 0xFFFF, sum = 0
8997 16:44:07.102283 6, 0xFFFF, sum = 0
8998 16:44:07.102731 7, 0xFFFF, sum = 0
8999 16:44:07.105189 8, 0xFFFF, sum = 0
9000 16:44:07.108676 9, 0xFFFF, sum = 0
9001 16:44:07.109293 10, 0xFFFF, sum = 0
9002 16:44:07.112350 11, 0xFFFF, sum = 0
9003 16:44:07.112899 12, 0xFFFF, sum = 0
9004 16:44:07.115317 13, 0xFFFF, sum = 0
9005 16:44:07.115778 14, 0x0, sum = 1
9006 16:44:07.118781 15, 0x0, sum = 2
9007 16:44:07.119383 16, 0x0, sum = 3
9008 16:44:07.122204 17, 0x0, sum = 4
9009 16:44:07.122728 best_step = 15
9010 16:44:07.123252
9011 16:44:07.123709 ==
9012 16:44:07.125285 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 16:44:07.128837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 16:44:07.131927 ==
9015 16:44:07.132518 RX Vref Scan: 0
9016 16:44:07.133031
9017 16:44:07.134809 RX Vref 0 -> 0, step: 1
9018 16:44:07.135406
9019 16:44:07.135928 RX Delay 11 -> 252, step: 4
9020 16:44:07.142438 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9021 16:44:07.145381 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9022 16:44:07.148987 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9023 16:44:07.152426 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9024 16:44:07.159004 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9025 16:44:07.162598 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9026 16:44:07.165623 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9027 16:44:07.168554 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9028 16:44:07.172118 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9029 16:44:07.178849 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9030 16:44:07.181891 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9031 16:44:07.185441 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9032 16:44:07.188553 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9033 16:44:07.191680 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9034 16:44:07.198371 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9035 16:44:07.202025 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9036 16:44:07.202473 ==
9037 16:44:07.205043 Dram Type= 6, Freq= 0, CH_1, rank 1
9038 16:44:07.208655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9039 16:44:07.209106 ==
9040 16:44:07.211675 DQS Delay:
9041 16:44:07.212207 DQS0 = 0, DQS1 = 0
9042 16:44:07.212627 DQM Delay:
9043 16:44:07.215172 DQM0 = 134, DQM1 = 126
9044 16:44:07.215744 DQ Delay:
9045 16:44:07.218790 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9046 16:44:07.221571 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9047 16:44:07.228297 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9048 16:44:07.231863 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9049 16:44:07.232480
9050 16:44:07.232981
9051 16:44:07.233308
9052 16:44:07.234776 [DramC_TX_OE_Calibration] TA2
9053 16:44:07.238379 Original DQ_B0 (3 6) =30, OEN = 27
9054 16:44:07.241417 Original DQ_B1 (3 6) =30, OEN = 27
9055 16:44:07.241991 24, 0x0, End_B0=24 End_B1=24
9056 16:44:07.245025 25, 0x0, End_B0=25 End_B1=25
9057 16:44:07.248265 26, 0x0, End_B0=26 End_B1=26
9058 16:44:07.251774 27, 0x0, End_B0=27 End_B1=27
9059 16:44:07.252210 28, 0x0, End_B0=28 End_B1=28
9060 16:44:07.254672 29, 0x0, End_B0=29 End_B1=29
9061 16:44:07.258016 30, 0x0, End_B0=30 End_B1=30
9062 16:44:07.261632 31, 0x4141, End_B0=30 End_B1=30
9063 16:44:07.264429 Byte0 end_step=30 best_step=27
9064 16:44:07.268107 Byte1 end_step=30 best_step=27
9065 16:44:07.268644 Byte0 TX OE(2T, 0.5T) = (3, 3)
9066 16:44:07.271199 Byte1 TX OE(2T, 0.5T) = (3, 3)
9067 16:44:07.271658
9068 16:44:07.272127
9069 16:44:07.280847 [DQSOSCAuto] RK1, (LSB)MR18= 0xb07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9070 16:44:07.284498 CH1 RK1: MR19=303, MR18=B07
9071 16:44:07.287576 CH1_RK1: MR19=0x303, MR18=0xB07, DQSOSC=404, MR23=63, INC=22, DEC=15
9072 16:44:07.291168 [RxdqsGatingPostProcess] freq 1600
9073 16:44:07.297320 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9074 16:44:07.300942 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 16:44:07.303957 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 16:44:07.307575 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 16:44:07.310521 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 16:44:07.320931 best DQS0 dly(2T, 0.5T) = (1, 1)
9079 16:44:07.321437 best DQS1 dly(2T, 0.5T) = (1, 1)
9080 16:44:07.321969 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9081 16:44:07.322440 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9082 16:44:07.324167 Pre-setting of DQS Precalculation
9083 16:44:07.330206 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9084 16:44:07.337201 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9085 16:44:07.343431 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 16:44:07.343990
9087 16:44:07.344370
9088 16:44:07.346964 [Calibration Summary] 3200 Mbps
9089 16:44:07.350644 CH 0, Rank 0
9090 16:44:07.351249 SW Impedance : PASS
9091 16:44:07.353497 DUTY Scan : NO K
9092 16:44:07.356731 ZQ Calibration : PASS
9093 16:44:07.357168 Jitter Meter : NO K
9094 16:44:07.360181 CBT Training : PASS
9095 16:44:07.363570 Write leveling : PASS
9096 16:44:07.364048 RX DQS gating : PASS
9097 16:44:07.366850 RX DQ/DQS(RDDQC) : PASS
9098 16:44:07.367310 TX DQ/DQS : PASS
9099 16:44:07.370314 RX DATLAT : PASS
9100 16:44:07.373356 RX DQ/DQS(Engine): PASS
9101 16:44:07.373792 TX OE : PASS
9102 16:44:07.376803 All Pass.
9103 16:44:07.377388
9104 16:44:07.377898 CH 0, Rank 1
9105 16:44:07.379842 SW Impedance : PASS
9106 16:44:07.380410 DUTY Scan : NO K
9107 16:44:07.383382 ZQ Calibration : PASS
9108 16:44:07.386508 Jitter Meter : NO K
9109 16:44:07.387122 CBT Training : PASS
9110 16:44:07.389827 Write leveling : PASS
9111 16:44:07.393315 RX DQS gating : PASS
9112 16:44:07.393877 RX DQ/DQS(RDDQC) : PASS
9113 16:44:07.396303 TX DQ/DQS : PASS
9114 16:44:07.399890 RX DATLAT : PASS
9115 16:44:07.400475 RX DQ/DQS(Engine): PASS
9116 16:44:07.403289 TX OE : PASS
9117 16:44:07.403945 All Pass.
9118 16:44:07.404428
9119 16:44:07.406225 CH 1, Rank 0
9120 16:44:07.406656 SW Impedance : PASS
9121 16:44:07.409814 DUTY Scan : NO K
9122 16:44:07.412791 ZQ Calibration : PASS
9123 16:44:07.413334 Jitter Meter : NO K
9124 16:44:07.416419 CBT Training : PASS
9125 16:44:07.419342 Write leveling : PASS
9126 16:44:07.419955 RX DQS gating : PASS
9127 16:44:07.422830 RX DQ/DQS(RDDQC) : PASS
9128 16:44:07.425815 TX DQ/DQS : PASS
9129 16:44:07.426411 RX DATLAT : PASS
9130 16:44:07.429055 RX DQ/DQS(Engine): PASS
9131 16:44:07.432594 TX OE : PASS
9132 16:44:07.432680 All Pass.
9133 16:44:07.432748
9134 16:44:07.432810 CH 1, Rank 1
9135 16:44:07.435565 SW Impedance : PASS
9136 16:44:07.438779 DUTY Scan : NO K
9137 16:44:07.438899 ZQ Calibration : PASS
9138 16:44:07.442209 Jitter Meter : NO K
9139 16:44:07.445689 CBT Training : PASS
9140 16:44:07.445775 Write leveling : PASS
9141 16:44:07.448589 RX DQS gating : PASS
9142 16:44:07.448675 RX DQ/DQS(RDDQC) : PASS
9143 16:44:07.452125 TX DQ/DQS : PASS
9144 16:44:07.455419 RX DATLAT : PASS
9145 16:44:07.455506 RX DQ/DQS(Engine): PASS
9146 16:44:07.458518 TX OE : PASS
9147 16:44:07.458604 All Pass.
9148 16:44:07.458672
9149 16:44:07.461923 DramC Write-DBI on
9150 16:44:07.465302 PER_BANK_REFRESH: Hybrid Mode
9151 16:44:07.465422 TX_TRACKING: ON
9152 16:44:07.475104 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9153 16:44:07.481847 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9154 16:44:07.492111 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9155 16:44:07.495071 [FAST_K] Save calibration result to emmc
9156 16:44:07.495161 sync common calibartion params.
9157 16:44:07.498608 sync cbt_mode0:1, 1:1
9158 16:44:07.501757 dram_init: ddr_geometry: 2
9159 16:44:07.505159 dram_init: ddr_geometry: 2
9160 16:44:07.505244 dram_init: ddr_geometry: 2
9161 16:44:07.508083 0:dram_rank_size:100000000
9162 16:44:07.511741 1:dram_rank_size:100000000
9163 16:44:07.514800 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9164 16:44:07.518462 DFS_SHUFFLE_HW_MODE: ON
9165 16:44:07.521390 dramc_set_vcore_voltage set vcore to 725000
9166 16:44:07.525041 Read voltage for 1600, 0
9167 16:44:07.525128 Vio18 = 0
9168 16:44:07.527989 Vcore = 725000
9169 16:44:07.528074 Vdram = 0
9170 16:44:07.528142 Vddq = 0
9171 16:44:07.528204 Vmddr = 0
9172 16:44:07.531344 switch to 3200 Mbps bootup
9173 16:44:07.534708 [DramcRunTimeConfig]
9174 16:44:07.534793 PHYPLL
9175 16:44:07.538164 DPM_CONTROL_AFTERK: ON
9176 16:44:07.538251 PER_BANK_REFRESH: ON
9177 16:44:07.541011 REFRESH_OVERHEAD_REDUCTION: ON
9178 16:44:07.544554 CMD_PICG_NEW_MODE: OFF
9179 16:44:07.544640 XRTWTW_NEW_MODE: ON
9180 16:44:07.547507 XRTRTR_NEW_MODE: ON
9181 16:44:07.547593 TX_TRACKING: ON
9182 16:44:07.550956 RDSEL_TRACKING: OFF
9183 16:44:07.554171 DQS Precalculation for DVFS: ON
9184 16:44:07.554258 RX_TRACKING: OFF
9185 16:44:07.557753 HW_GATING DBG: ON
9186 16:44:07.557840 ZQCS_ENABLE_LP4: ON
9187 16:44:07.561317 RX_PICG_NEW_MODE: ON
9188 16:44:07.561403 TX_PICG_NEW_MODE: ON
9189 16:44:07.564104 ENABLE_RX_DCM_DPHY: ON
9190 16:44:07.567629 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9191 16:44:07.570923 DUMMY_READ_FOR_TRACKING: OFF
9192 16:44:07.571035 !!! SPM_CONTROL_AFTERK: OFF
9193 16:44:07.574482 !!! SPM could not control APHY
9194 16:44:07.577377 IMPEDANCE_TRACKING: ON
9195 16:44:07.577463 TEMP_SENSOR: ON
9196 16:44:07.581024 HW_SAVE_FOR_SR: OFF
9197 16:44:07.584005 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9198 16:44:07.587590 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9199 16:44:07.587678 Read ODT Tracking: ON
9200 16:44:07.590592 Refresh Rate DeBounce: ON
9201 16:44:07.594138 DFS_NO_QUEUE_FLUSH: ON
9202 16:44:07.597251 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9203 16:44:07.600686 ENABLE_DFS_RUNTIME_MRW: OFF
9204 16:44:07.600772 DDR_RESERVE_NEW_MODE: ON
9205 16:44:07.603754 MR_CBT_SWITCH_FREQ: ON
9206 16:44:07.607180 =========================
9207 16:44:07.625006 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9208 16:44:07.628000 dram_init: ddr_geometry: 2
9209 16:44:07.646130 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9210 16:44:07.649608 dram_init: dram init end (result: 0)
9211 16:44:07.655995 DRAM-K: Full calibration passed in 24567 msecs
9212 16:44:07.659121 MRC: failed to locate region type 0.
9213 16:44:07.659235 DRAM rank0 size:0x100000000,
9214 16:44:07.662210 DRAM rank1 size=0x100000000
9215 16:44:07.672401 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9216 16:44:07.678724 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9217 16:44:07.688553 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9218 16:44:07.695031 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9219 16:44:07.695132 DRAM rank0 size:0x100000000,
9220 16:44:07.698621 DRAM rank1 size=0x100000000
9221 16:44:07.698695 CBMEM:
9222 16:44:07.701680 IMD: root @ 0xfffff000 254 entries.
9223 16:44:07.705109 IMD: root @ 0xffffec00 62 entries.
9224 16:44:07.708582 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9225 16:44:07.715046 WARNING: RO_VPD is uninitialized or empty.
9226 16:44:07.718084 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9227 16:44:07.726347 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9228 16:44:07.738829 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9229 16:44:07.750107 BS: romstage times (exec / console): total (unknown) / 24071 ms
9230 16:44:07.750235
9231 16:44:07.750331
9232 16:44:07.760260 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9233 16:44:07.763674 ARM64: Exception handlers installed.
9234 16:44:07.766723 ARM64: Testing exception
9235 16:44:07.770231 ARM64: Done test exception
9236 16:44:07.770319 Enumerating buses...
9237 16:44:07.773569 Show all devs... Before device enumeration.
9238 16:44:07.776401 Root Device: enabled 1
9239 16:44:07.779861 CPU_CLUSTER: 0: enabled 1
9240 16:44:07.779962 CPU: 00: enabled 1
9241 16:44:07.783255 Compare with tree...
9242 16:44:07.783337 Root Device: enabled 1
9243 16:44:07.786640 CPU_CLUSTER: 0: enabled 1
9244 16:44:07.789687 CPU: 00: enabled 1
9245 16:44:07.789764 Root Device scanning...
9246 16:44:07.793192 scan_static_bus for Root Device
9247 16:44:07.796219 CPU_CLUSTER: 0 enabled
9248 16:44:07.799738 scan_static_bus for Root Device done
9249 16:44:07.803224 scan_bus: bus Root Device finished in 8 msecs
9250 16:44:07.803306 done
9251 16:44:07.809691 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9252 16:44:07.813236 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9253 16:44:07.819334 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9254 16:44:07.822969 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9255 16:44:07.826630 Allocating resources...
9256 16:44:07.829609 Reading resources...
9257 16:44:07.833167 Root Device read_resources bus 0 link: 0
9258 16:44:07.836536 DRAM rank0 size:0x100000000,
9259 16:44:07.836620 DRAM rank1 size=0x100000000
9260 16:44:07.839337 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9261 16:44:07.842881 CPU: 00 missing read_resources
9262 16:44:07.849300 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9263 16:44:07.852629 Root Device read_resources bus 0 link: 0 done
9264 16:44:07.852717 Done reading resources.
9265 16:44:07.859354 Show resources in subtree (Root Device)...After reading.
9266 16:44:07.862770 Root Device child on link 0 CPU_CLUSTER: 0
9267 16:44:07.865707 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 16:44:07.875916 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 16:44:07.876042 CPU: 00
9270 16:44:07.878782 Root Device assign_resources, bus 0 link: 0
9271 16:44:07.882115 CPU_CLUSTER: 0 missing set_resources
9272 16:44:07.889078 Root Device assign_resources, bus 0 link: 0 done
9273 16:44:07.889165 Done setting resources.
9274 16:44:07.895688 Show resources in subtree (Root Device)...After assigning values.
9275 16:44:07.898655 Root Device child on link 0 CPU_CLUSTER: 0
9276 16:44:07.902229 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 16:44:07.912438 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 16:44:07.912529 CPU: 00
9279 16:44:07.915213 Done allocating resources.
9280 16:44:07.922547 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9281 16:44:07.922632 Enabling resources...
9282 16:44:07.922698 done.
9283 16:44:07.928641 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9284 16:44:07.932218 Initializing devices...
9285 16:44:07.932338 Root Device init
9286 16:44:07.935195 init hardware done!
9287 16:44:07.935280 0x00000018: ctrlr->caps
9288 16:44:07.938850 52.000 MHz: ctrlr->f_max
9289 16:44:07.941756 0.400 MHz: ctrlr->f_min
9290 16:44:07.941844 0x40ff8080: ctrlr->voltages
9291 16:44:07.945247 sclk: 390625
9292 16:44:07.945329 Bus Width = 1
9293 16:44:07.945414 sclk: 390625
9294 16:44:07.948256 Bus Width = 1
9295 16:44:07.951787 Early init status = 3
9296 16:44:07.955218 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9297 16:44:07.958724 in-header: 03 fc 00 00 01 00 00 00
9298 16:44:07.961653 in-data: 00
9299 16:44:07.965044 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9300 16:44:07.969304 in-header: 03 fd 00 00 00 00 00 00
9301 16:44:07.972862 in-data:
9302 16:44:07.975805 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9303 16:44:07.980668 in-header: 03 fc 00 00 01 00 00 00
9304 16:44:07.983352 in-data: 00
9305 16:44:07.986719 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9306 16:44:07.991918 in-header: 03 fd 00 00 00 00 00 00
9307 16:44:07.995409 in-data:
9308 16:44:07.998945 [SSUSB] Setting up USB HOST controller...
9309 16:44:08.001880 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9310 16:44:08.005486 [SSUSB] phy power-on done.
9311 16:44:08.008553 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9312 16:44:08.015048 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9313 16:44:08.018490 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9314 16:44:08.025159 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9315 16:44:08.031810 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9316 16:44:08.038182 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9317 16:44:08.045515 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9318 16:44:08.051801 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9319 16:44:08.054787 SPM: binary array size = 0x9dc
9320 16:44:08.058225 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9321 16:44:08.065138 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9322 16:44:08.071407 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9323 16:44:08.078462 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9324 16:44:08.081500 configure_display: Starting display init
9325 16:44:08.115492 anx7625_power_on_init: Init interface.
9326 16:44:08.118673 anx7625_disable_pd_protocol: Disabled PD feature.
9327 16:44:08.122014 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9328 16:44:08.150004 anx7625_start_dp_work: Secure OCM version=00
9329 16:44:08.153251 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9330 16:44:08.167651 sp_tx_get_edid_block: EDID Block = 1
9331 16:44:08.270801 Extracted contents:
9332 16:44:08.273721 header: 00 ff ff ff ff ff ff 00
9333 16:44:08.277261 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9334 16:44:08.280638 version: 01 04
9335 16:44:08.283537 basic params: 95 1f 11 78 0a
9336 16:44:08.287019 chroma info: 76 90 94 55 54 90 27 21 50 54
9337 16:44:08.290095 established: 00 00 00
9338 16:44:08.297058 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9339 16:44:08.303274 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9340 16:44:08.306827 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 16:44:08.313413 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9342 16:44:08.319834 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9343 16:44:08.323353 extensions: 00
9344 16:44:08.323432 checksum: fb
9345 16:44:08.323497
9346 16:44:08.326346 Manufacturer: IVO Model 57d Serial Number 0
9347 16:44:08.329871 Made week 0 of 2020
9348 16:44:08.333364 EDID version: 1.4
9349 16:44:08.333458 Digital display
9350 16:44:08.336314 6 bits per primary color channel
9351 16:44:08.336411 DisplayPort interface
9352 16:44:08.340000 Maximum image size: 31 cm x 17 cm
9353 16:44:08.342860 Gamma: 220%
9354 16:44:08.342967 Check DPMS levels
9355 16:44:08.349511 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9356 16:44:08.352612 First detailed timing is preferred timing
9357 16:44:08.352721 Established timings supported:
9358 16:44:08.356217 Standard timings supported:
9359 16:44:08.359992 Detailed timings
9360 16:44:08.362711 Hex of detail: 383680a07038204018303c0035ae10000019
9361 16:44:08.369558 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9362 16:44:08.372444 0780 0798 07c8 0820 hborder 0
9363 16:44:08.375851 0438 043b 0447 0458 vborder 0
9364 16:44:08.379444 -hsync -vsync
9365 16:44:08.379575 Did detailed timing
9366 16:44:08.385748 Hex of detail: 000000000000000000000000000000000000
9367 16:44:08.389195 Manufacturer-specified data, tag 0
9368 16:44:08.392659 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9369 16:44:08.395647 ASCII string: InfoVision
9370 16:44:08.399014 Hex of detail: 000000fe00523134304e574635205248200a
9371 16:44:08.402465 ASCII string: R140NWF5 RH
9372 16:44:08.402551 Checksum
9373 16:44:08.405843 Checksum: 0xfb (valid)
9374 16:44:08.409377 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9375 16:44:08.412241 DSI data_rate: 832800000 bps
9376 16:44:08.419054 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9377 16:44:08.422606 anx7625_parse_edid: pixelclock(138800).
9378 16:44:08.426052 hactive(1920), hsync(48), hfp(24), hbp(88)
9379 16:44:08.429000 vactive(1080), vsync(12), vfp(3), vbp(17)
9380 16:44:08.432543 anx7625_dsi_config: config dsi.
9381 16:44:08.438861 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9382 16:44:08.453035 anx7625_dsi_config: success to config DSI
9383 16:44:08.455844 anx7625_dp_start: MIPI phy setup OK.
9384 16:44:08.459499 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9385 16:44:08.462391 mtk_ddp_mode_set invalid vrefresh 60
9386 16:44:08.466202 main_disp_path_setup
9387 16:44:08.466756 ovl_layer_smi_id_en
9388 16:44:08.469162 ovl_layer_smi_id_en
9389 16:44:08.469579 ccorr_config
9390 16:44:08.469908 aal_config
9391 16:44:08.472654 gamma_config
9392 16:44:08.473066 postmask_config
9393 16:44:08.476093 dither_config
9394 16:44:08.479485 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9395 16:44:08.485985 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9396 16:44:08.489421 Root Device init finished in 553 msecs
9397 16:44:08.492382 CPU_CLUSTER: 0 init
9398 16:44:08.499492 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9399 16:44:08.505605 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9400 16:44:08.506169 APU_MBOX 0x190000b0 = 0x10001
9401 16:44:08.509139 APU_MBOX 0x190001b0 = 0x10001
9402 16:44:08.512436 APU_MBOX 0x190005b0 = 0x10001
9403 16:44:08.515879 APU_MBOX 0x190006b0 = 0x10001
9404 16:44:08.522371 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9405 16:44:08.531543 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9406 16:44:08.543789 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9407 16:44:08.550251 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9408 16:44:08.561919 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9409 16:44:08.571603 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9410 16:44:08.574553 CPU_CLUSTER: 0 init finished in 81 msecs
9411 16:44:08.577947 Devices initialized
9412 16:44:08.581277 Show all devs... After init.
9413 16:44:08.581368 Root Device: enabled 1
9414 16:44:08.584289 CPU_CLUSTER: 0: enabled 1
9415 16:44:08.587650 CPU: 00: enabled 1
9416 16:44:08.591043 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9417 16:44:08.594092 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9418 16:44:08.597436 ELOG: NV offset 0x57f000 size 0x1000
9419 16:44:08.604701 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9420 16:44:08.610737 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9421 16:44:08.614263 ELOG: Event(17) added with size 13 at 2023-06-03 16:44:08 UTC
9422 16:44:08.621070 out: cmd=0x121: 03 db 21 01 00 00 00 00
9423 16:44:08.624137 in-header: 03 fa 00 00 2c 00 00 00
9424 16:44:08.633744 in-data: 65 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9425 16:44:08.640562 ELOG: Event(A1) added with size 10 at 2023-06-03 16:44:08 UTC
9426 16:44:08.647493 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9427 16:44:08.653581 ELOG: Event(A0) added with size 9 at 2023-06-03 16:44:08 UTC
9428 16:44:08.657198 elog_add_boot_reason: Logged dev mode boot
9429 16:44:08.663846 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9430 16:44:08.663930 Finalize devices...
9431 16:44:08.666887 Devices finalized
9432 16:44:08.670487 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9433 16:44:08.673953 Writing coreboot table at 0xffe64000
9434 16:44:08.676835 0. 000000000010a000-0000000000113fff: RAMSTAGE
9435 16:44:08.683232 1. 0000000040000000-00000000400fffff: RAM
9436 16:44:08.686610 2. 0000000040100000-000000004032afff: RAMSTAGE
9437 16:44:08.690038 3. 000000004032b000-00000000545fffff: RAM
9438 16:44:08.693077 4. 0000000054600000-000000005465ffff: BL31
9439 16:44:08.696428 5. 0000000054660000-00000000ffe63fff: RAM
9440 16:44:08.702869 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9441 16:44:08.706636 7. 0000000100000000-000000023fffffff: RAM
9442 16:44:08.709741 Passing 5 GPIOs to payload:
9443 16:44:08.712833 NAME | PORT | POLARITY | VALUE
9444 16:44:08.719582 EC in RW | 0x000000aa | low | undefined
9445 16:44:08.723053 EC interrupt | 0x00000005 | low | undefined
9446 16:44:08.726080 TPM interrupt | 0x000000ab | high | undefined
9447 16:44:08.733207 SD card detect | 0x00000011 | high | undefined
9448 16:44:08.736255 speaker enable | 0x00000093 | high | undefined
9449 16:44:08.739770 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9450 16:44:08.742718 in-header: 03 f9 00 00 02 00 00 00
9451 16:44:08.746491 in-data: 02 00
9452 16:44:08.749692 ADC[4]: Raw value=900813 ID=7
9453 16:44:08.752671 ADC[3]: Raw value=213282 ID=1
9454 16:44:08.752764 RAM Code: 0x71
9455 16:44:08.756196 ADC[6]: Raw value=75036 ID=0
9456 16:44:08.759174 ADC[5]: Raw value=213282 ID=1
9457 16:44:08.759251 SKU Code: 0x1
9458 16:44:08.765613 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a12d
9459 16:44:08.765695 coreboot table: 964 bytes.
9460 16:44:08.769178 IMD ROOT 0. 0xfffff000 0x00001000
9461 16:44:08.772198 IMD SMALL 1. 0xffffe000 0x00001000
9462 16:44:08.775856 RO MCACHE 2. 0xffffc000 0x00001104
9463 16:44:08.779260 CONSOLE 3. 0xfff7c000 0x00080000
9464 16:44:08.782241 FMAP 4. 0xfff7b000 0x00000452
9465 16:44:08.785772 TIME STAMP 5. 0xfff7a000 0x00000910
9466 16:44:08.788625 VBOOT WORK 6. 0xfff66000 0x00014000
9467 16:44:08.792081 RAMOOPS 7. 0xffe66000 0x00100000
9468 16:44:08.795613 COREBOOT 8. 0xffe64000 0x00002000
9469 16:44:08.799043 IMD small region:
9470 16:44:08.801847 IMD ROOT 0. 0xffffec00 0x00000400
9471 16:44:08.805427 VPD 1. 0xffffeba0 0x0000004c
9472 16:44:08.808857 MMC STATUS 2. 0xffffeb80 0x00000004
9473 16:44:08.815164 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9474 16:44:08.815260 Probing TPM: done!
9475 16:44:08.818642 Connected to device vid:did:rid of 1ae0:0028:00
9476 16:44:08.830150 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9477 16:44:08.833754 Initialized TPM device CR50 revision 0
9478 16:44:08.837322 Checking cr50 for pending updates
9479 16:44:08.840823 Reading cr50 TPM mode
9480 16:44:08.849365 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9481 16:44:08.855816 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9482 16:44:08.896077 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9483 16:44:08.899647 Checking segment from ROM address 0x40100000
9484 16:44:08.902969 Checking segment from ROM address 0x4010001c
9485 16:44:08.909755 Loading segment from ROM address 0x40100000
9486 16:44:08.909846 code (compression=0)
9487 16:44:08.919632 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9488 16:44:08.926387 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9489 16:44:08.926478 it's not compressed!
9490 16:44:08.932824 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9491 16:44:08.936277 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9492 16:44:08.956707 Loading segment from ROM address 0x4010001c
9493 16:44:08.956825 Entry Point 0x80000000
9494 16:44:08.959697 Loaded segments
9495 16:44:08.963235 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9496 16:44:08.969652 Jumping to boot code at 0x80000000(0xffe64000)
9497 16:44:08.976321 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9498 16:44:08.982853 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9499 16:44:08.991337 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9500 16:44:08.994319 Checking segment from ROM address 0x40100000
9501 16:44:08.997793 Checking segment from ROM address 0x4010001c
9502 16:44:09.004738 Loading segment from ROM address 0x40100000
9503 16:44:09.004821 code (compression=1)
9504 16:44:09.011085 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9505 16:44:09.021011 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9506 16:44:09.021094 using LZMA
9507 16:44:09.029677 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9508 16:44:09.036099 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9509 16:44:09.039484 Loading segment from ROM address 0x4010001c
9510 16:44:09.039566 Entry Point 0x54601000
9511 16:44:09.042628 Loaded segments
9512 16:44:09.046006 NOTICE: MT8192 bl31_setup
9513 16:44:09.053328 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9514 16:44:09.056273 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9515 16:44:09.059966 WARNING: region 0:
9516 16:44:09.063290 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 16:44:09.063373 WARNING: region 1:
9518 16:44:09.070035 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9519 16:44:09.072981 WARNING: region 2:
9520 16:44:09.076674 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9521 16:44:09.079593 WARNING: region 3:
9522 16:44:09.083172 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9523 16:44:09.086212 WARNING: region 4:
9524 16:44:09.093264 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9525 16:44:09.093348 WARNING: region 5:
9526 16:44:09.096287 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 16:44:09.099810 WARNING: region 6:
9528 16:44:09.103283 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 16:44:09.106210 WARNING: region 7:
9530 16:44:09.109620 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 16:44:09.116610 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9532 16:44:09.120074 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9533 16:44:09.122956 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9534 16:44:09.129515 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9535 16:44:09.132828 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9536 16:44:09.136408 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9537 16:44:09.142835 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9538 16:44:09.146210 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9539 16:44:09.152820 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9540 16:44:09.156377 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9541 16:44:09.159438 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9542 16:44:09.166404 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9543 16:44:09.169359 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9544 16:44:09.172866 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9545 16:44:09.179653 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9546 16:44:09.182525 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9547 16:44:09.189715 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9548 16:44:09.192691 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9549 16:44:09.196121 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9550 16:44:09.202546 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9551 16:44:09.205968 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9552 16:44:09.209364 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9553 16:44:09.216192 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9554 16:44:09.219199 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9555 16:44:09.226337 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9556 16:44:09.229254 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9557 16:44:09.236165 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9558 16:44:09.239564 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9559 16:44:09.243170 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9560 16:44:09.249462 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9561 16:44:09.253137 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9562 16:44:09.256190 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9563 16:44:09.262826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9564 16:44:09.266334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9565 16:44:09.269294 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9566 16:44:09.272510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9567 16:44:09.279576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9568 16:44:09.282577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9569 16:44:09.285740 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9570 16:44:09.289204 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9571 16:44:09.295953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9572 16:44:09.299420 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9573 16:44:09.302757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9574 16:44:09.309228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9575 16:44:09.312550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9576 16:44:09.315586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9577 16:44:09.319031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9578 16:44:09.325929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9579 16:44:09.329204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9580 16:44:09.332617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9581 16:44:09.339264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9582 16:44:09.342653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9583 16:44:09.348956 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9584 16:44:09.352410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9585 16:44:09.358525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9586 16:44:09.362108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9587 16:44:09.365115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9588 16:44:09.371763 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9589 16:44:09.375195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9590 16:44:09.381547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9591 16:44:09.385041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9592 16:44:09.391619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9593 16:44:09.395349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9594 16:44:09.402426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9595 16:44:09.405161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9596 16:44:09.408722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9597 16:44:09.415116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9598 16:44:09.418421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9599 16:44:09.425432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9600 16:44:09.428708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9601 16:44:09.434923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9602 16:44:09.438181 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9603 16:44:09.445360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9604 16:44:09.448229 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9605 16:44:09.451611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9606 16:44:09.458477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9607 16:44:09.461918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9608 16:44:09.468633 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9609 16:44:09.471940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9610 16:44:09.478655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9611 16:44:09.482006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9612 16:44:09.484847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9613 16:44:09.491256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9614 16:44:09.494714 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9615 16:44:09.501253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9616 16:44:09.504817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9617 16:44:09.511445 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9618 16:44:09.514341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9619 16:44:09.521407 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9620 16:44:09.524833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9621 16:44:09.527798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9622 16:44:09.534475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9623 16:44:09.537982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9624 16:44:09.544285 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9625 16:44:09.547927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9626 16:44:09.554178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9627 16:44:09.557629 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9628 16:44:09.561147 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9629 16:44:09.565002 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9630 16:44:09.571356 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9631 16:44:09.574350 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9632 16:44:09.577909 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9633 16:44:09.584348 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9634 16:44:09.587313 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9635 16:44:09.594602 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9636 16:44:09.597503 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9637 16:44:09.601126 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9638 16:44:09.607451 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9639 16:44:09.611055 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9640 16:44:09.617459 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9641 16:44:09.621097 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9642 16:44:09.623826 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9643 16:44:09.630702 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9644 16:44:09.633683 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9645 16:44:09.640369 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9646 16:44:09.644097 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9647 16:44:09.646766 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9648 16:44:09.653789 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9649 16:44:09.656778 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9650 16:44:09.660323 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9651 16:44:09.663513 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9652 16:44:09.669951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9653 16:44:09.673574 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9654 16:44:09.676547 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9655 16:44:09.683110 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9656 16:44:09.686598 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9657 16:44:09.689993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9658 16:44:09.696672 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9659 16:44:09.699634 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9660 16:44:09.706327 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9661 16:44:09.709889 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9662 16:44:09.712909 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9663 16:44:09.719538 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9664 16:44:09.722914 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9665 16:44:09.729894 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9666 16:44:09.733252 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9667 16:44:09.736749 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9668 16:44:09.742994 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9669 16:44:09.746339 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9670 16:44:09.749729 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9671 16:44:09.756362 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9672 16:44:09.759815 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9673 16:44:09.766847 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9674 16:44:09.769645 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9675 16:44:09.773083 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9676 16:44:09.780171 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9677 16:44:09.783152 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9678 16:44:09.789759 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9679 16:44:09.793458 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9680 16:44:09.796820 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9681 16:44:09.803514 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9682 16:44:09.806392 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9683 16:44:09.812916 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9684 16:44:09.816604 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9685 16:44:09.820176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9686 16:44:09.826627 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9687 16:44:09.830010 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9688 16:44:09.832877 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9689 16:44:09.839795 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9690 16:44:09.843088 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9691 16:44:09.849822 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9692 16:44:09.852591 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9693 16:44:09.856025 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9694 16:44:09.862669 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9695 16:44:09.865851 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9696 16:44:09.872701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9697 16:44:09.876093 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9698 16:44:09.879218 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9699 16:44:09.885851 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9700 16:44:09.889400 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9701 16:44:09.895849 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9702 16:44:09.899489 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9703 16:44:09.902251 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9704 16:44:09.908885 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9705 16:44:09.912497 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9706 16:44:09.918887 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9707 16:44:09.922516 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9708 16:44:09.925542 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9709 16:44:09.932162 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9710 16:44:09.935628 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9711 16:44:09.942551 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9712 16:44:09.945182 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9713 16:44:09.948544 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9714 16:44:09.955546 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9715 16:44:09.958426 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9716 16:44:09.965581 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9717 16:44:09.968407 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9718 16:44:09.971821 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9719 16:44:09.978738 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9720 16:44:09.981548 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9721 16:44:09.988171 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9722 16:44:09.991788 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9723 16:44:09.998290 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9724 16:44:10.001840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9725 16:44:10.004612 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9726 16:44:10.011717 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9727 16:44:10.014814 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9728 16:44:10.021356 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9729 16:44:10.024598 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9730 16:44:10.031538 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9731 16:44:10.034451 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9732 16:44:10.037869 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9733 16:44:10.044183 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9734 16:44:10.047536 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9735 16:44:10.054188 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9736 16:44:10.056967 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9737 16:44:10.064128 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9738 16:44:10.066827 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9739 16:44:10.070405 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9740 16:44:10.076742 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9741 16:44:10.080338 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9742 16:44:10.086766 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9743 16:44:10.090134 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9744 16:44:10.097185 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9745 16:44:10.100077 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9746 16:44:10.103506 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9747 16:44:10.109921 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9748 16:44:10.113451 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9749 16:44:10.119964 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9750 16:44:10.123179 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9751 16:44:10.129609 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9752 16:44:10.133280 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9753 16:44:10.136333 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9754 16:44:10.143428 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9755 16:44:10.146341 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9756 16:44:10.152995 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9757 16:44:10.156265 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9758 16:44:10.159980 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9759 16:44:10.166049 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9760 16:44:10.169519 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9761 16:44:10.173106 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9762 16:44:10.179451 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9763 16:44:10.182825 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9764 16:44:10.186305 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9765 16:44:10.189654 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9766 16:44:10.196136 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9767 16:44:10.199806 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9768 16:44:10.206436 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9769 16:44:10.209329 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9770 16:44:10.212835 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9771 16:44:10.219163 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9772 16:44:10.222783 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9773 16:44:10.226412 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9774 16:44:10.232509 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9775 16:44:10.236040 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9776 16:44:10.239503 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9777 16:44:10.246010 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9778 16:44:10.249127 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9779 16:44:10.255494 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9780 16:44:10.258904 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9781 16:44:10.262303 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9782 16:44:10.269045 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9783 16:44:10.272510 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9784 16:44:10.275797 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9785 16:44:10.282280 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9786 16:44:10.285687 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9787 16:44:10.292110 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9788 16:44:10.295609 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9789 16:44:10.298434 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9790 16:44:10.305117 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9791 16:44:10.308799 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9792 16:44:10.311438 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9793 16:44:10.317915 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9794 16:44:10.321324 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9795 16:44:10.327956 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9796 16:44:10.331565 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9797 16:44:10.334567 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9798 16:44:10.341068 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9799 16:44:10.344235 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9800 16:44:10.347891 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9801 16:44:10.350885 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9802 16:44:10.358033 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9803 16:44:10.360848 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9804 16:44:10.364355 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9805 16:44:10.367750 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9806 16:44:10.374618 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9807 16:44:10.377668 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9808 16:44:10.381124 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9809 16:44:10.384596 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9810 16:44:10.391106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9811 16:44:10.394614 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9812 16:44:10.397986 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9813 16:44:10.404221 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9814 16:44:10.407775 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9815 16:44:10.414444 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9816 16:44:10.417284 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9817 16:44:10.420804 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9818 16:44:10.427650 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9819 16:44:10.430631 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9820 16:44:10.437654 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9821 16:44:10.440377 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9822 16:44:10.443990 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9823 16:44:10.450593 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9824 16:44:10.453461 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9825 16:44:10.460591 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9826 16:44:10.463920 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9827 16:44:10.470065 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9828 16:44:10.473468 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9829 16:44:10.476954 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9830 16:44:10.483383 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9831 16:44:10.486769 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9832 16:44:10.493311 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9833 16:44:10.496353 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9834 16:44:10.503111 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9835 16:44:10.506448 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9836 16:44:10.509921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9837 16:44:10.515993 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9838 16:44:10.519489 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9839 16:44:10.526219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9840 16:44:10.529548 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9841 16:44:10.536072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9842 16:44:10.539031 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9843 16:44:10.542339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9844 16:44:10.548800 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9845 16:44:10.552390 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9846 16:44:10.558907 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9847 16:44:10.562301 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9848 16:44:10.565190 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9849 16:44:10.572059 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9850 16:44:10.575489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9851 16:44:10.582065 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9852 16:44:10.585062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9853 16:44:10.588533 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9854 16:44:10.595182 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9855 16:44:10.597918 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9856 16:44:10.604821 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9857 16:44:10.608202 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9858 16:44:10.614701 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9859 16:44:10.618236 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9860 16:44:10.621163 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9861 16:44:10.628368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9862 16:44:10.631281 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9863 16:44:10.637772 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9864 16:44:10.641468 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9865 16:44:10.644923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9866 16:44:10.651391 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9867 16:44:10.654833 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9868 16:44:10.661303 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9869 16:44:10.664757 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9870 16:44:10.668381 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9871 16:44:10.674687 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9872 16:44:10.678195 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9873 16:44:10.684920 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9874 16:44:10.688349 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9875 16:44:10.694462 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9876 16:44:10.697877 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9877 16:44:10.701437 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9878 16:44:10.708010 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9879 16:44:10.710811 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9880 16:44:10.717716 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9881 16:44:10.720895 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9882 16:44:10.727583 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9883 16:44:10.731118 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9884 16:44:10.734093 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9885 16:44:10.740544 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9886 16:44:10.744263 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9887 16:44:10.750709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9888 16:44:10.753800 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9889 16:44:10.760513 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9890 16:44:10.763524 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9891 16:44:10.770420 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9892 16:44:10.773513 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9893 16:44:10.776999 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9894 16:44:10.783469 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9895 16:44:10.786897 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9896 16:44:10.793408 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9897 16:44:10.796704 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9898 16:44:10.803025 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9899 16:44:10.806792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9900 16:44:10.810127 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9901 16:44:10.816495 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9902 16:44:10.819942 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9903 16:44:10.826331 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9904 16:44:10.829410 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9905 16:44:10.836516 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9906 16:44:10.839399 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9907 16:44:10.846425 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9908 16:44:10.849699 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9909 16:44:10.852585 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9910 16:44:10.859718 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9911 16:44:10.862646 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9912 16:44:10.869818 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9913 16:44:10.872624 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9914 16:44:10.879152 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9915 16:44:10.882440 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9916 16:44:10.889247 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9917 16:44:10.892155 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9918 16:44:10.895466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9919 16:44:10.902464 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9920 16:44:10.905859 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9921 16:44:10.912197 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9922 16:44:10.915693 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9923 16:44:10.922054 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9924 16:44:10.925561 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9925 16:44:10.929095 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9926 16:44:10.935162 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9927 16:44:10.938667 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9928 16:44:10.945306 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9929 16:44:10.948778 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9930 16:44:10.955231 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9931 16:44:10.958338 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9932 16:44:10.964974 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9933 16:44:10.968581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9934 16:44:10.971513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9935 16:44:10.978530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9936 16:44:10.981552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9937 16:44:10.987957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9938 16:44:10.991451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9939 16:44:10.998099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9940 16:44:11.001568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9941 16:44:11.008020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9942 16:44:11.011384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9943 16:44:11.018071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9944 16:44:11.021226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9945 16:44:11.027759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9946 16:44:11.031133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9947 16:44:11.037692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9948 16:44:11.040699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9949 16:44:11.046972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9950 16:44:11.050726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9951 16:44:11.057144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9952 16:44:11.060245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9953 16:44:11.066769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9954 16:44:11.070224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9955 16:44:11.076977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9956 16:44:11.080406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9957 16:44:11.086731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9958 16:44:11.090301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9959 16:44:11.096726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9960 16:44:11.100223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9961 16:44:11.107101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9962 16:44:11.110059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9963 16:44:11.116266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9964 16:44:11.119908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9965 16:44:11.126155 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9966 16:44:11.126237 INFO: [APUAPC] vio 0
9967 16:44:11.133011 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9968 16:44:11.136509 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9969 16:44:11.139499 INFO: [APUAPC] D0_APC_0: 0x400510
9970 16:44:11.143020 INFO: [APUAPC] D0_APC_1: 0x0
9971 16:44:11.146174 INFO: [APUAPC] D0_APC_2: 0x1540
9972 16:44:11.149630 INFO: [APUAPC] D0_APC_3: 0x0
9973 16:44:11.153260 INFO: [APUAPC] D1_APC_0: 0xffffffff
9974 16:44:11.156188 INFO: [APUAPC] D1_APC_1: 0xffffffff
9975 16:44:11.159547 INFO: [APUAPC] D1_APC_2: 0x3fffff
9976 16:44:11.162491 INFO: [APUAPC] D1_APC_3: 0x0
9977 16:44:11.166298 INFO: [APUAPC] D2_APC_0: 0xffffffff
9978 16:44:11.169121 INFO: [APUAPC] D2_APC_1: 0xffffffff
9979 16:44:11.172739 INFO: [APUAPC] D2_APC_2: 0x3fffff
9980 16:44:11.175753 INFO: [APUAPC] D2_APC_3: 0x0
9981 16:44:11.179271 INFO: [APUAPC] D3_APC_0: 0xffffffff
9982 16:44:11.182262 INFO: [APUAPC] D3_APC_1: 0xffffffff
9983 16:44:11.185953 INFO: [APUAPC] D3_APC_2: 0x3fffff
9984 16:44:11.189013 INFO: [APUAPC] D3_APC_3: 0x0
9985 16:44:11.192469 INFO: [APUAPC] D4_APC_0: 0xffffffff
9986 16:44:11.195718 INFO: [APUAPC] D4_APC_1: 0xffffffff
9987 16:44:11.198880 INFO: [APUAPC] D4_APC_2: 0x3fffff
9988 16:44:11.198978 INFO: [APUAPC] D4_APC_3: 0x0
9989 16:44:11.205914 INFO: [APUAPC] D5_APC_0: 0xffffffff
9990 16:44:11.209181 INFO: [APUAPC] D5_APC_1: 0xffffffff
9991 16:44:11.212187 INFO: [APUAPC] D5_APC_2: 0x3fffff
9992 16:44:11.212266 INFO: [APUAPC] D5_APC_3: 0x0
9993 16:44:11.215799 INFO: [APUAPC] D6_APC_0: 0xffffffff
9994 16:44:11.219316 INFO: [APUAPC] D6_APC_1: 0xffffffff
9995 16:44:11.222123 INFO: [APUAPC] D6_APC_2: 0x3fffff
9996 16:44:11.225964 INFO: [APUAPC] D6_APC_3: 0x0
9997 16:44:11.229106 INFO: [APUAPC] D7_APC_0: 0xffffffff
9998 16:44:11.232133 INFO: [APUAPC] D7_APC_1: 0xffffffff
9999 16:44:11.235475 INFO: [APUAPC] D7_APC_2: 0x3fffff
10000 16:44:11.238727 INFO: [APUAPC] D7_APC_3: 0x0
10001 16:44:11.242251 INFO: [APUAPC] D8_APC_0: 0xffffffff
10002 16:44:11.245265 INFO: [APUAPC] D8_APC_1: 0xffffffff
10003 16:44:11.248924 INFO: [APUAPC] D8_APC_2: 0x3fffff
10004 16:44:11.251994 INFO: [APUAPC] D8_APC_3: 0x0
10005 16:44:11.255263 INFO: [APUAPC] D9_APC_0: 0xffffffff
10006 16:44:11.258812 INFO: [APUAPC] D9_APC_1: 0xffffffff
10007 16:44:11.262171 INFO: [APUAPC] D9_APC_2: 0x3fffff
10008 16:44:11.265254 INFO: [APUAPC] D9_APC_3: 0x0
10009 16:44:11.268347 INFO: [APUAPC] D10_APC_0: 0xffffffff
10010 16:44:11.271958 INFO: [APUAPC] D10_APC_1: 0xffffffff
10011 16:44:11.275482 INFO: [APUAPC] D10_APC_2: 0x3fffff
10012 16:44:11.278587 INFO: [APUAPC] D10_APC_3: 0x0
10013 16:44:11.282019 INFO: [APUAPC] D11_APC_0: 0xffffffff
10014 16:44:11.285068 INFO: [APUAPC] D11_APC_1: 0xffffffff
10015 16:44:11.288742 INFO: [APUAPC] D11_APC_2: 0x3fffff
10016 16:44:11.291691 INFO: [APUAPC] D11_APC_3: 0x0
10017 16:44:11.295243 INFO: [APUAPC] D12_APC_0: 0xffffffff
10018 16:44:11.298101 INFO: [APUAPC] D12_APC_1: 0xffffffff
10019 16:44:11.301574 INFO: [APUAPC] D12_APC_2: 0x3fffff
10020 16:44:11.305059 INFO: [APUAPC] D12_APC_3: 0x0
10021 16:44:11.308728 INFO: [APUAPC] D13_APC_0: 0xffffffff
10022 16:44:11.311632 INFO: [APUAPC] D13_APC_1: 0xffffffff
10023 16:44:11.314473 INFO: [APUAPC] D13_APC_2: 0x3fffff
10024 16:44:11.318066 INFO: [APUAPC] D13_APC_3: 0x0
10025 16:44:11.321555 INFO: [APUAPC] D14_APC_0: 0xffffffff
10026 16:44:11.324851 INFO: [APUAPC] D14_APC_1: 0xffffffff
10027 16:44:11.331396 INFO: [APUAPC] D14_APC_2: 0x3fffff
10028 16:44:11.331481 INFO: [APUAPC] D14_APC_3: 0x0
10029 16:44:11.334197 INFO: [APUAPC] D15_APC_0: 0xffffffff
10030 16:44:11.341093 INFO: [APUAPC] D15_APC_1: 0xffffffff
10031 16:44:11.344424 INFO: [APUAPC] D15_APC_2: 0x3fffff
10032 16:44:11.344534 INFO: [APUAPC] D15_APC_3: 0x0
10033 16:44:11.347769 INFO: [APUAPC] APC_CON: 0x4
10034 16:44:11.350767 INFO: [NOCDAPC] D0_APC_0: 0x0
10035 16:44:11.354304 INFO: [NOCDAPC] D0_APC_1: 0x0
10036 16:44:11.357376 INFO: [NOCDAPC] D1_APC_0: 0x0
10037 16:44:11.360924 INFO: [NOCDAPC] D1_APC_1: 0xfff
10038 16:44:11.363832 INFO: [NOCDAPC] D2_APC_0: 0x0
10039 16:44:11.367279 INFO: [NOCDAPC] D2_APC_1: 0xfff
10040 16:44:11.370925 INFO: [NOCDAPC] D3_APC_0: 0x0
10041 16:44:11.373924 INFO: [NOCDAPC] D3_APC_1: 0xfff
10042 16:44:11.374026 INFO: [NOCDAPC] D4_APC_0: 0x0
10043 16:44:11.377446 INFO: [NOCDAPC] D4_APC_1: 0xfff
10044 16:44:11.380510 INFO: [NOCDAPC] D5_APC_0: 0x0
10045 16:44:11.384020 INFO: [NOCDAPC] D5_APC_1: 0xfff
10046 16:44:11.387023 INFO: [NOCDAPC] D6_APC_0: 0x0
10047 16:44:11.390609 INFO: [NOCDAPC] D6_APC_1: 0xfff
10048 16:44:11.393656 INFO: [NOCDAPC] D7_APC_0: 0x0
10049 16:44:11.397115 INFO: [NOCDAPC] D7_APC_1: 0xfff
10050 16:44:11.400063 INFO: [NOCDAPC] D8_APC_0: 0x0
10051 16:44:11.403543 INFO: [NOCDAPC] D8_APC_1: 0xfff
10052 16:44:11.406900 INFO: [NOCDAPC] D9_APC_0: 0x0
10053 16:44:11.410414 INFO: [NOCDAPC] D9_APC_1: 0xfff
10054 16:44:11.410516 INFO: [NOCDAPC] D10_APC_0: 0x0
10055 16:44:11.413183 INFO: [NOCDAPC] D10_APC_1: 0xfff
10056 16:44:11.416632 INFO: [NOCDAPC] D11_APC_0: 0x0
10057 16:44:11.420139 INFO: [NOCDAPC] D11_APC_1: 0xfff
10058 16:44:11.423679 INFO: [NOCDAPC] D12_APC_0: 0x0
10059 16:44:11.426655 INFO: [NOCDAPC] D12_APC_1: 0xfff
10060 16:44:11.430035 INFO: [NOCDAPC] D13_APC_0: 0x0
10061 16:44:11.433637 INFO: [NOCDAPC] D13_APC_1: 0xfff
10062 16:44:11.436689 INFO: [NOCDAPC] D14_APC_0: 0x0
10063 16:44:11.440095 INFO: [NOCDAPC] D14_APC_1: 0xfff
10064 16:44:11.442954 INFO: [NOCDAPC] D15_APC_0: 0x0
10065 16:44:11.446447 INFO: [NOCDAPC] D15_APC_1: 0xfff
10066 16:44:11.449773 INFO: [NOCDAPC] APC_CON: 0x4
10067 16:44:11.453279 INFO: [APUAPC] set_apusys_apc done
10068 16:44:11.456277 INFO: [DEVAPC] devapc_init done
10069 16:44:11.459900 INFO: GICv3 without legacy support detected.
10070 16:44:11.462891 INFO: ARM GICv3 driver initialized in EL3
10071 16:44:11.465967 INFO: Maximum SPI INTID supported: 639
10072 16:44:11.472622 INFO: BL31: Initializing runtime services
10073 16:44:11.476330 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10074 16:44:11.479276 INFO: SPM: enable CPC mode
10075 16:44:11.485810 INFO: mcdi ready for mcusys-off-idle and system suspend
10076 16:44:11.489346 INFO: BL31: Preparing for EL3 exit to normal world
10077 16:44:11.492883 INFO: Entry point address = 0x80000000
10078 16:44:11.495798 INFO: SPSR = 0x8
10079 16:44:11.500959
10080 16:44:11.501070
10081 16:44:11.501166
10082 16:44:11.504485 Starting depthcharge on Spherion...
10083 16:44:11.504556
10084 16:44:11.504630 Wipe memory regions:
10085 16:44:11.504698
10086 16:44:11.505340 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10087 16:44:11.505455 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10088 16:44:11.505543 Setting prompt string to ['asurada:']
10089 16:44:11.505635 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10090 16:44:11.507441 [0x00000040000000, 0x00000054600000)
10091 16:44:11.629565
10092 16:44:11.633044 [0x00000054660000, 0x00000080000000)
10093 16:44:11.890814
10094 16:44:11.890994 [0x000000821a7280, 0x000000ffe64000)
10095 16:44:12.635407
10096 16:44:12.635586 [0x00000100000000, 0x00000240000000)
10097 16:44:14.526043
10098 16:44:14.528866 Initializing XHCI USB controller at 0x11200000.
10099 16:44:15.510755
10100 16:44:15.510905 R8152: Initializing
10101 16:44:15.510974
10102 16:44:15.513522 Version 9 (ocp_data = 6010)
10103 16:44:15.513609
10104 16:44:15.517273 R8152: Done initializing
10105 16:44:15.517355
10106 16:44:15.517421 Adding net device
10107 16:44:16.038644
10108 16:44:16.041962 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10109 16:44:16.042058
10110 16:44:16.042123
10111 16:44:16.042184
10112 16:44:16.042489 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10114 16:44:16.142838 asurada: tftpboot 192.168.201.1 10576288/tftp-deploy-iypy3_7a/kernel/image.itb 10576288/tftp-deploy-iypy3_7a/kernel/cmdline
10115 16:44:16.142990 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10116 16:44:16.143140 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10117 16:44:16.147668 tftpboot 192.168.201.1 10576288/tftp-deploy-iypy3_7a/kernel/image.ittp-deploy-iypy3_7a/kernel/cmdline
10118 16:44:16.147752
10119 16:44:16.147817 Waiting for link
10120 16:44:16.350369
10121 16:44:16.350552 done.
10122 16:44:16.350624
10123 16:44:16.350721 MAC: f4:f5:e8:50:de:0a
10124 16:44:16.350794
10125 16:44:16.352714 Sending DHCP discover... done.
10126 16:44:16.352826
10127 16:44:16.356172 Waiting for reply... done.
10128 16:44:16.356256
10129 16:44:16.359545 Sending DHCP request... done.
10130 16:44:16.359627
10131 16:44:16.359692 Waiting for reply... done.
10132 16:44:16.359752
10133 16:44:16.362936 My ip is 192.168.201.14
10134 16:44:16.363041
10135 16:44:16.365950 The DHCP server ip is 192.168.201.1
10136 16:44:16.366031
10137 16:44:16.369541 TFTP server IP predefined by user: 192.168.201.1
10138 16:44:16.369625
10139 16:44:16.376215 Bootfile predefined by user: 10576288/tftp-deploy-iypy3_7a/kernel/image.itb
10140 16:44:16.376296
10141 16:44:16.379109 Sending tftp read request... done.
10142 16:44:16.379221
10143 16:44:16.382521 Waiting for the transfer...
10144 16:44:16.382604
10145 16:44:16.609706 00000000 ################################################################
10146 16:44:16.609869
10147 16:44:16.826408 00080000 ################################################################
10148 16:44:16.826562
10149 16:44:17.044191 00100000 ################################################################
10150 16:44:17.044342
10151 16:44:17.265514 00180000 ################################################################
10152 16:44:17.265707
10153 16:44:17.484140 00200000 ################################################################
10154 16:44:17.484324
10155 16:44:17.701381 00280000 ################################################################
10156 16:44:17.701553
10157 16:44:17.923165 00300000 ################################################################
10158 16:44:17.923329
10159 16:44:18.148253 00380000 ################################################################
10160 16:44:18.148430
10161 16:44:18.364484 00400000 ################################################################
10162 16:44:18.364630
10163 16:44:18.581767 00480000 ################################################################
10164 16:44:18.581920
10165 16:44:18.798679 00500000 ################################################################
10166 16:44:18.798838
10167 16:44:19.020892 00580000 ################################################################
10168 16:44:19.021045
10169 16:44:19.241549 00600000 ################################################################
10170 16:44:19.241711
10171 16:44:19.458990 00680000 ################################################################
10172 16:44:19.459160
10173 16:44:19.676837 00700000 ################################################################
10174 16:44:19.677000
10175 16:44:19.897370 00780000 ################################################################
10176 16:44:19.897532
10177 16:44:20.120424 00800000 ################################################################
10178 16:44:20.120572
10179 16:44:20.349952 00880000 ################################################################
10180 16:44:20.350128
10181 16:44:20.568107 00900000 ################################################################
10182 16:44:20.568280
10183 16:44:20.783709 00980000 ################################################################
10184 16:44:20.783874
10185 16:44:20.997875 00a00000 ################################################################
10186 16:44:20.998048
10187 16:44:21.214945 00a80000 ################################################################
10188 16:44:21.215121
10189 16:44:21.433155 00b00000 ################################################################
10190 16:44:21.433298
10191 16:44:21.650612 00b80000 ################################################################
10192 16:44:21.650781
10193 16:44:21.868424 00c00000 ################################################################
10194 16:44:21.868557
10195 16:44:22.086987 00c80000 ################################################################
10196 16:44:22.087142
10197 16:44:22.307958 00d00000 ################################################################
10198 16:44:22.308173
10199 16:44:22.523749 00d80000 ################################################################
10200 16:44:22.523915
10201 16:44:22.738615 00e00000 ################################################################
10202 16:44:22.738776
10203 16:44:22.954721 00e80000 ################################################################
10204 16:44:22.954861
10205 16:44:23.169525 00f00000 ################################################################
10206 16:44:23.169659
10207 16:44:23.386187 00f80000 ################################################################
10208 16:44:23.386324
10209 16:44:23.601803 01000000 ################################################################
10210 16:44:23.601965
10211 16:44:23.817500 01080000 ################################################################
10212 16:44:23.817678
10213 16:44:24.033734 01100000 ################################################################
10214 16:44:24.033899
10215 16:44:24.250035 01180000 ################################################################
10216 16:44:24.250212
10217 16:44:24.468607 01200000 ################################################################
10218 16:44:24.468752
10219 16:44:24.682500 01280000 ################################################################
10220 16:44:24.682638
10221 16:44:24.899420 01300000 ################################################################
10222 16:44:24.899610
10223 16:44:25.115707 01380000 ################################################################
10224 16:44:25.115854
10225 16:44:25.334180 01400000 ################################################################
10226 16:44:25.334353
10227 16:44:25.553081 01480000 ################################################################
10228 16:44:25.553211
10229 16:44:25.774856 01500000 ################################################################
10230 16:44:25.775032
10231 16:44:25.997080 01580000 ################################################################
10232 16:44:25.997246
10233 16:44:26.216085 01600000 ################################################################
10234 16:44:26.216260
10235 16:44:26.433222 01680000 ################################################################
10236 16:44:26.433370
10237 16:44:26.654279 01700000 ################################################################
10238 16:44:26.654437
10239 16:44:26.878961 01780000 ################################################################
10240 16:44:26.879144
10241 16:44:27.097918 01800000 ################################################################
10242 16:44:27.098077
10243 16:44:27.312564 01880000 ################################################################
10244 16:44:27.312708
10245 16:44:27.533210 01900000 ################################################################
10246 16:44:27.533373
10247 16:44:27.756042 01980000 ################################################################
10248 16:44:27.756174
10249 16:44:27.973567 01a00000 ############################################################### done.
10250 16:44:27.973731
10251 16:44:27.976947 The bootfile was 27776518 bytes long.
10252 16:44:27.977057
10253 16:44:27.980031 Sending tftp read request... done.
10254 16:44:27.980141
10255 16:44:27.983355 Waiting for the transfer...
10256 16:44:27.983474
10257 16:44:27.986777 00000000 # done.
10258 16:44:27.986886
10259 16:44:27.993133 Command line loaded dynamically from TFTP file: 10576288/tftp-deploy-iypy3_7a/kernel/cmdline
10260 16:44:27.993231
10261 16:44:28.009765 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576288/extract-nfsrootfs-irjyd3ff,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10262 16:44:28.009865
10263 16:44:28.012708 Loading FIT.
10264 16:44:28.012792
10265 16:44:28.012858 Image ramdisk-1 has 17644088 bytes.
10266 16:44:28.016236
10267 16:44:28.016319 Image fdt-1 has 46924 bytes.
10268 16:44:28.016386
10269 16:44:28.019606 Image kernel-1 has 10083474 bytes.
10270 16:44:28.019689
10271 16:44:28.029611 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10272 16:44:28.029698
10273 16:44:28.046066 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10274 16:44:28.046222
10275 16:44:28.052557 Choosing best match conf-1 for compat google,spherion-rev2.
10276 16:44:28.056498
10277 16:44:28.060376 Connected to device vid:did:rid of 1ae0:0028:00
10278 16:44:28.067966
10279 16:44:28.070902 tpm_get_response: command 0x17b, return code 0x0
10280 16:44:28.070981
10281 16:44:28.074292 ec_init: CrosEC protocol v3 supported (256, 248)
10282 16:44:28.078209
10283 16:44:28.081834 tpm_cleanup: add release locality here.
10284 16:44:28.081941
10285 16:44:28.082037 Shutting down all USB controllers.
10286 16:44:28.082128
10287 16:44:28.085040 Removing current net device
10288 16:44:28.085124
10289 16:44:28.091565 Exiting depthcharge with code 4 at timestamp: 45953772
10290 16:44:28.091650
10291 16:44:28.094827 LZMA decompressing kernel-1 to 0x821a6718
10292 16:44:28.094938
10293 16:44:28.098589 LZMA decompressing kernel-1 to 0x40000000
10294 16:44:29.364932
10295 16:44:29.365679 jumping to kernel
10296 16:44:29.368538 end: 2.2.4 bootloader-commands (duration 00:00:18) [common]
10297 16:44:29.369239 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
10298 16:44:29.369803 Setting prompt string to ['Linux version [0-9]']
10299 16:44:29.370338 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10300 16:44:29.370705 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10301 16:44:29.918017
10302 16:44:29.920622 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10303 16:44:29.924758 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
10304 16:44:29.925262 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10305 16:44:29.925703 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10306 16:44:29.926097 Using line separator: #'\n'#
10307 16:44:29.926605 No login prompt set.
10308 16:44:29.926955 Parsing kernel messages
10309 16:44:29.927329 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10310 16:44:29.928142 [login-action] Waiting for messages, (timeout 00:04:07)
10311 16:44:29.943639 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
10312 16:44:29.947026 [ 0.000000] random: crng init done
10313 16:44:29.953607 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10314 16:44:29.956958 [ 0.000000] efi: UEFI not found.
10315 16:44:29.963359 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10316 16:44:29.970248 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10317 16:44:29.980197 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10318 16:44:29.989825 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10319 16:44:29.993466 [ 0.000000] NUMA: No NUMA configuration found
10320 16:44:30.003316 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10321 16:44:30.006163 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10322 16:44:30.009585 [ 0.000000] Zone ranges:
10323 16:44:30.016611 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10324 16:44:30.019810 [ 0.000000] DMA32 empty
10325 16:44:30.026183 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10326 16:44:30.029614 [ 0.000000] Movable zone start for each node
10327 16:44:30.033019 [ 0.000000] Early memory node ranges
10328 16:44:30.039750 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10329 16:44:30.046099 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10330 16:44:30.052636 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10331 16:44:30.059035 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10332 16:44:30.062488 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10333 16:44:30.072175 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10334 16:44:30.075740 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10335 16:44:30.082815 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10336 16:44:30.088974 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10337 16:44:30.092163 [ 0.000000] psci: probing for conduit method from DT.
10338 16:44:30.098473 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10339 16:44:30.102075 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10340 16:44:30.108427 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10341 16:44:30.111750 [ 0.000000] psci: SMC Calling Convention v1.2
10342 16:44:30.118610 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10343 16:44:30.121883 [ 0.000000] Detected VIPT I-cache on CPU0
10344 16:44:30.128077 [ 0.000000] CPU features: detected: GIC system register CPU interface
10345 16:44:30.134764 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10346 16:44:30.141266 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10347 16:44:30.147735 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10348 16:44:30.157997 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10349 16:44:30.164265 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10350 16:44:30.167804 [ 0.000000] alternatives: applying boot alternatives
10351 16:44:30.171193 [ 0.000000] Fallback order for Node 0: 0
10352 16:44:30.180961 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10353 16:44:30.181040 [ 0.000000] Policy zone: Normal
10354 16:44:30.200808 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576288/extract-nfsrootfs-irjyd3ff,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10355 16:44:30.210894 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10356 16:44:30.217026 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10357 16:44:30.226967 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10358 16:44:30.233580 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10359 16:44:30.237091 [ 0.000000] software IO TLB: area num 8.
10360 16:44:30.243956 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10361 16:44:30.259854 [ 0.000000] Memory: 7955708K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397060K reserved, 32768K cma-reserved)
10362 16:44:30.263335 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10363 16:44:30.269826 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10364 16:44:30.276584 [ 0.000000] rcu: RCU event tracing is enabled.
10365 16:44:30.283099 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10366 16:44:30.286527 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10367 16:44:30.293181 [ 0.000000] Tracing variant of Tasks RCU enabled.
10368 16:44:30.299956 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10369 16:44:30.306216 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10370 16:44:30.313182 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10371 16:44:30.316201 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10372 16:44:30.319603 [ 0.000000] GICv3: 608 SPIs implemented
10373 16:44:30.326298 [ 0.000000] GICv3: 0 Extended SPIs implemented
10374 16:44:30.329546 [ 0.000000] Root IRQ handler: gic_handle_irq
10375 16:44:30.332891 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10376 16:44:30.339763 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10377 16:44:30.352884 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10378 16:44:30.365677 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10379 16:44:30.372797 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10380 16:44:30.376071 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10381 16:44:30.389090 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10382 16:44:30.395560 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10383 16:44:30.398939 [ 0.000952] Console: colour dummy device 80x25
10384 16:44:30.412190 [ 0.001021] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10385 16:44:30.415668 [ 0.001028] pid_max: default: 32768 minimum: 301
10386 16:44:30.419092 [ 0.001069] LSM: Security Framework initializing
10387 16:44:30.428692 [ 0.001174] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 16:44:30.435503 [ 0.001226] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 16:44:30.442121 [ 0.002317] cblist_init_generic: Setting adjustable number of callback queues.
10390 16:44:30.449102 [ 0.002327] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 16:44:30.455504 [ 0.002371] cblist_init_generic: Setting shift to 3 and lim to 1.
10392 16:44:30.458774 [ 0.002477] rcu: Hierarchical SRCU implementation.
10393 16:44:30.465567 [ 0.002479] rcu: Max phase no-delay instances is 1000.
10394 16:44:30.468301 [ 0.004103] EFI services will not be available.
10395 16:44:30.474858 [ 0.004322] smp: Bringing up secondary CPUs ...
10396 16:44:30.478356 [ 0.004619] Detected VIPT I-cache on CPU1
10397 16:44:30.485121 [ 0.004690] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10398 16:44:30.491513 [ 0.004721] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10399 16:44:30.495181 [ 0.005060] Detected VIPT I-cache on CPU2
10400 16:44:30.501207 [ 0.005112] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10401 16:44:30.508076 [ 0.005129] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10402 16:44:30.514895 [ 0.005395] Detected VIPT I-cache on CPU3
10403 16:44:30.520953 [ 0.005446] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10404 16:44:30.527954 [ 0.005460] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10405 16:44:30.531258 [ 0.005767] CPU features: detected: Spectre-v4
10406 16:44:30.534275 [ 0.005773] CPU features: detected: Spectre-BHB
10407 16:44:30.541101 [ 0.005779] Detected PIPT I-cache on CPU4
10408 16:44:30.547866 [ 0.005837] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10409 16:44:30.554340 [ 0.005854] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10410 16:44:30.557687 [ 0.006151] Detected PIPT I-cache on CPU5
10411 16:44:30.563933 [ 0.006214] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10412 16:44:30.571040 [ 0.006230] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10413 16:44:30.574265 [ 0.006515] Detected PIPT I-cache on CPU6
10414 16:44:30.580686 [ 0.006582] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10415 16:44:30.587427 [ 0.006598] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10416 16:44:30.593927 [ 0.006898] Detected PIPT I-cache on CPU7
10417 16:44:30.600897 [ 0.006964] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10418 16:44:30.606973 [ 0.006980] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10419 16:44:30.610253 [ 0.007027] smp: Brought up 1 node, 8 CPUs
10420 16:44:30.613593 [ 0.007032] SMP: Total of 8 processors activated.
10421 16:44:30.620567 [ 0.007035] CPU features: detected: 32-bit EL0 Support
10422 16:44:30.626867 [ 0.007038] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10423 16:44:30.633774 [ 0.007040] CPU features: detected: Common not Private translations
10424 16:44:30.639879 [ 0.007042] CPU features: detected: CRC32 instructions
10425 16:44:30.646747 [ 0.007045] CPU features: detected: RCpc load-acquire (LDAPR)
10426 16:44:30.650155 [ 0.007047] CPU features: detected: LSE atomic instructions
10427 16:44:30.656668 [ 0.007049] CPU features: detected: Privileged Access Never
10428 16:44:30.662932 [ 0.007050] CPU features: detected: RAS Extension Support
10429 16:44:30.669844 [ 0.007053] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10430 16:44:30.673297 [ 0.007119] CPU: All CPU(s) started at EL2
10431 16:44:30.679661 [ 0.007121] alternatives: applying system-wide alternatives
10432 16:44:30.683209 [ 0.012092] devtmpfs: initialized
10433 16:44:30.692904 [ 0.017293] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10434 16:44:30.699561 [ 0.017307] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10435 16:44:30.703030 [ 0.018143] pinctrl core: initialized pinctrl subsystem
10436 16:44:30.706045 [ 0.019299] DMI not present or invalid.
10437 16:44:30.712741 [ 0.019636] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10438 16:44:30.719908 [ 0.020343] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10439 16:44:30.729223 [ 0.020570] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10440 16:44:30.735956 [ 0.020740] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10441 16:44:30.742190 [ 0.020766] audit: initializing netlink subsys (disabled)
10442 16:44:30.748904 [ 0.020837] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10443 16:44:30.756067 [ 0.021525] thermal_sys: Registered thermal governor 'step_wise'
10444 16:44:30.762479 [ 0.021529] thermal_sys: Registered thermal governor 'power_allocator'
10445 16:44:30.765729 [ 0.021557] cpuidle: using governor menu
10446 16:44:30.772066 [ 0.021620] NET: Registered PF_QIPCRTR protocol family
10447 16:44:30.778486 [ 0.021731] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10448 16:44:30.781860 [ 0.021823] ASID allocator initialised with 32768 entries
10449 16:44:30.788809 [ 0.022749] Serial: AMBA PL011 UART driver
10450 16:44:30.791698 [ 0.027019] Trying to register duplicate clock ID: 134
10451 16:44:30.795114 [ 0.078936] KASLR enabled
10452 16:44:30.801878 [ 0.083740] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10453 16:44:30.808719 [ 0.083744] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10454 16:44:30.814881 [ 0.083749] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10455 16:44:30.821899 [ 0.083751] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10456 16:44:30.828261 [ 0.083754] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10457 16:44:30.835141 [ 0.083756] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10458 16:44:30.841487 [ 0.083759] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10459 16:44:30.848286 [ 0.083761] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10460 16:44:30.851464 [ 0.084725] ACPI: Interpreter disabled.
10461 16:44:30.854902 [ 0.087033] iommu: Default domain type: Translated
10462 16:44:30.861246 [ 0.087036] iommu: DMA domain TLB invalidation policy: strict mode
10463 16:44:30.864621 [ 0.087213] SCSI subsystem initialized
10464 16:44:30.871150 [ 0.087400] usbcore: registered new interface driver usbfs
10465 16:44:30.877829 [ 0.087417] usbcore: registered new interface driver hub
10466 16:44:30.881154 [ 0.087430] usbcore: registered new device driver usb
10467 16:44:30.887961 [ 0.088236] pps_core: LinuxPPS API ver. 1 registered
10468 16:44:30.894321 [ 0.088239] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10469 16:44:30.901164 [ 0.088245] PTP clock support registered
10470 16:44:30.904536 [ 0.088327] EDAC MC: Ver: 3.0.0
10471 16:44:30.907701 [ 0.090081] FPGA manager framework
10472 16:44:30.911078 [ 0.090121] Advanced Linux Sound Architecture Driver Initialized.
10473 16:44:30.913627 [ 0.090575] vgaarb: loaded
10474 16:44:30.920492 [ 0.090789] clocksource: Switched to clocksource arch_sys_counter
10475 16:44:30.923866 [ 0.090905] VFS: Disk quotas dquot_6.6.0
10476 16:44:30.931026 [ 0.090933] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10477 16:44:30.933856 [ 0.091039] pnp: PnP ACPI: disabled
10478 16:44:30.940709 [ 0.093740] NET: Registered PF_INET protocol family
10479 16:44:30.946655 [ 0.094225] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10480 16:44:30.957019 [ 0.098804] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10481 16:44:30.963667 [ 0.098879] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10482 16:44:30.970188 [ 0.098893] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10483 16:44:30.979789 [ 0.099466] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10484 16:44:30.986786 [ 0.101607] TCP: Hash tables configured (established 65536 bind 65536)
10485 16:44:30.992893 [ 0.101717] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10486 16:44:30.999834 [ 0.101908] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 16:44:31.006219 [ 0.102148] NET: Registered PF_UNIX/PF_LOCAL protocol family
10488 16:44:31.009477 [ 0.102360] RPC: Registered named UNIX socket transport module.
10489 16:44:31.016141 [ 0.102364] RPC: Registered udp transport module.
10490 16:44:31.019571 [ 0.102366] RPC: Registered tcp transport module.
10491 16:44:31.026328 [ 0.102367] RPC: Registered tcp NFSv4.1 backchannel transport module.
10492 16:44:31.030399 [ 0.102376] PCI: CLS 0 bytes, default 64
10493 16:44:31.033060 [ 0.102615] Unpacking initramfs...
10494 16:44:31.042869 [ 0.119321] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10495 16:44:31.049143 [ 0.119563] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10496 16:44:31.055956 [ 0.120041] kvm [1]: IPA Size Limit: 40 bits
10497 16:44:31.059374 [ 0.120064] kvm [1]: GICv3: no GICV resource entry
10498 16:44:31.062763 [ 0.120069] kvm [1]: disabling GICv2 emulation
10499 16:44:31.069077 [ 0.120081] kvm [1]: GIC system register CPU interface enabled
10500 16:44:31.072634 [ 0.120168] kvm [1]: vgic interrupt IRQ18
10501 16:44:31.079465 [ 0.120265] kvm [1]: VHE mode initialized successfully
10502 16:44:31.082864 [ 0.121137] Initialise system trusted keyrings
10503 16:44:31.089493 [ 0.121224] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10504 16:44:31.095595 [ 0.124536] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10505 16:44:31.099039 [ 0.124829] NFS: Registering the id_resolver key type
10506 16:44:31.106020 [ 0.124845] Key type id_resolver registered
10507 16:44:31.108820 [ 0.124847] Key type id_legacy registered
10508 16:44:31.115872 [ 0.124882] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10509 16:44:31.122265 [ 0.124886] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10510 16:44:31.128959 [ 0.124969] 9p: Installing v9fs 9p2000 file system support
10511 16:44:31.132364 [ 0.156056] Key type asymmetric registered
10512 16:44:31.138369 [ 0.156061] Asymmetric key parser 'x509' registered
10513 16:44:31.145310 [ 0.156103] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10514 16:44:31.148340 [ 0.156108] io scheduler mq-deadline registered
10515 16:44:31.151763 [ 0.156113] io scheduler kyber registered
10516 16:44:31.155142 [ 0.168748] EINJ: ACPI disabled.
10517 16:44:31.165253 [ 0.190687] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10518 16:44:31.178173 [ 0.190856] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 16:44:31.181552 [ 0.200990] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10520 16:44:31.188299 [ 0.202468] printk: console [ttyS0] disabled
10521 16:44:31.198085 [ 0.222608] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10522 16:44:31.201445 [ 0.857244] Freeing initrd memory: 17228K
10523 16:44:31.204929 [ 0.860120] printk: console [ttyS0] enabled
10524 16:44:31.211341 [ 1.513109] SuperH (H)SCI(F) driver initialized
10525 16:44:31.214822 [ 1.518117] msm_serial: driver initialized
10526 16:44:31.227965 [ 1.526711] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10527 16:44:31.234654 [ 1.534998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10528 16:44:31.244348 [ 1.543278] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10529 16:44:31.254765 [ 1.551647] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10530 16:44:31.260994 [ 1.560093] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10531 16:44:31.271174 [ 1.568544] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10532 16:44:31.277448 [ 1.576824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10533 16:44:31.287314 [ 1.585362] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10534 16:44:31.293705 [ 1.593644] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10535 16:44:31.303016 [ 1.608581] loop: module loaded
10536 16:44:31.311800 [ 1.614150] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10537 16:44:31.334924 [ 1.636792] mtk-pmic-keys: Failed to locate of_node [id: -1]
10538 16:44:31.341068 [ 1.643135] megasas: 07.719.03.00-rc1
10539 16:44:31.350104 [ 1.652358] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10540 16:44:31.357666 [ 1.658157] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10541 16:44:31.363822 [ 1.663192] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10542 16:44:31.373494 [ 1.675092] tun: Universal TUN/TAP device driver, 1.6
10543 16:44:31.380952 [ 1.675971] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10544 16:44:31.384307 [ 1.680883] thunder_xcv, ver 1.0
10545 16:44:31.384727 [ 1.689551] thunder_bgx, ver 1.0
10546 16:44:31.389183 [ 1.692796] nicpf, ver 1.0
10547 16:44:31.397273 [ 1.696531] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10548 16:44:31.413881 [ 1.703745] hns3: Copyright (c) 2017 Huawei Corporation.
10549 16:44:31.414882 [ 1.709070] hclge is initializing
10550 16:44:31.415299 [ 1.712389] e1000: Intel(R) PRO/1000 Network Driver
10551 16:44:31.418386 [ 1.717258] e1000: Copyright (c) 1999-2006 Intel Corporation.
10552 16:44:31.423288 [ 1.723013] e1000e: Intel(R) PRO/1000 Network Driver
10553 16:44:31.430048 [ 1.727968] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10554 16:44:31.433302 [ 1.733893] igb: Intel(R) Gigabit Ethernet Network Driver
10555 16:44:31.438451 [ 1.739283] igb: Copyright (c) 2007-2014 Intel Corporation.
10556 16:44:31.444770 [ 1.744859] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10557 16:44:31.454931 [ 1.746475] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10558 16:44:31.461368 [ 1.751118] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10559 16:44:31.464855 [ 1.751411] sky2: driver version 1.30
10560 16:44:31.471137 [ 1.772554] VFIO - User Level meta-driver version: 0.3
10561 16:44:31.478159 [ 1.780424] usbcore: registered new interface driver usb-storage
10562 16:44:31.484885 [ 1.786608] usbcore: registered new device driver onboard-usb-hub
10563 16:44:31.493273 [ 1.795346] mt6397-rtc mt6359-rtc: registered as rtc0
10564 16:44:31.503495 [ 1.800573] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:44:31 UTC (1685810671)
10565 16:44:31.506533 [ 1.809907] i2c_dev: i2c /dev entries driver
10566 16:44:31.522210 [ 1.821232] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10567 16:44:31.528964 [ 1.831157] sdhci: Secure Digital Host Controller Interface driver
10568 16:44:31.535854 [ 1.837333] sdhci: Copyright(c) Pierre Ossman
10569 16:44:31.542678 [ 1.842489] Synopsys Designware Multimedia Card Interface Driver
10570 16:44:31.545590 [ 1.848945] mmc0: CQHCI version 5.10
10571 16:44:31.552193 [ 1.849380] sdhci-pltfm: SDHCI platform and OF driver helper
10572 16:44:31.558867 [ 1.860584] ledtrig-cpu: registered to indicate activity on CPUs
10573 16:44:31.565466 [ 1.867662] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10574 16:44:31.573035 [ 1.874812] usbcore: registered new interface driver usbhid
10575 16:44:31.576458 [ 1.880378] usbhid: USB HID core driver
10576 16:44:31.582625 [ 1.884393] spi_master spi0: will run message pump with realtime priority
10577 16:44:31.628783 [ 1.924686] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10578 16:44:31.643889 [ 1.939591] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10579 16:44:31.651193 [ 1.952982] mmc0: Command Queue Engine enabled
10580 16:44:31.654522 [ 1.954149] cros-ec-spi spi0.0: Chrome EC device registered
10581 16:44:31.661149 [ 1.957455] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10582 16:44:31.668009 [ 1.970218] mmcblk0: mmc0:0001 DA4128 116 GiB
10583 16:44:31.680658 [ 1.979574] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10584 16:44:31.687082 [ 1.980807] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10585 16:44:31.690547 [ 1.990713] NET: Registered PF_PACKET protocol family
10586 16:44:31.697314 [ 1.995984] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10587 16:44:31.700185 [ 1.999455] 9pnet: Installing 9P2000 support
10588 16:44:31.707045 [ 2.005217] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10589 16:44:31.710525 [ 2.008613] Key type dns_resolver registered
10590 16:44:31.717520 [ 2.014342] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10591 16:44:31.720406 [ 2.018272] registered taskstats version 1
10592 16:44:31.726634 [ 2.028178] Loading compiled-in X.509 certificates
10593 16:44:31.759544 [ 2.055173] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 16:44:31.769211 [ 2.065587] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 16:44:31.779029 [ 2.077731] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10596 16:44:31.789803 [ 2.092381] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10597 16:44:31.796644 [ 2.098884] xhci-mtk 11200000.usb: xHCI Host Controller
10598 16:44:31.803395 [ 2.104123] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10599 16:44:31.813276 [ 2.111710] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10600 16:44:31.819722 [ 2.120888] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10601 16:44:31.823082 [ 2.126720] xhci-mtk 11200000.usb: xHCI Host Controller
10602 16:44:31.833402 [ 2.131949] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10603 16:44:31.840015 [ 2.139341] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10604 16:44:31.843480 [ 2.146868] hub 1-0:1.0: USB hub found
10605 16:44:31.846107 [ 2.150622] hub 1-0:1.0: 1 port detected
10606 16:44:31.856432 [ 2.154717] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10607 16:44:31.859285 [ 2.163234] hub 2-0:1.0: USB hub found
10608 16:44:31.862638 [ 2.167001] hub 2-0:1.0: 1 port detected
10609 16:44:31.871587 [ 2.173984] mtk-msdc 11f70000.mmc: Got CD GPIO
10610 16:44:31.892270 [ 2.191244] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10611 16:44:31.898915 [ 2.199020] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10612 16:44:31.908559 [ 2.206726] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10613 16:44:31.915166 [ 2.216120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10614 16:44:31.925005 [ 2.223943] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10615 16:44:31.932006 [ 2.231706] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10616 16:44:31.938784 [ 2.239365] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10617 16:44:31.948375 [ 2.246930] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10618 16:44:31.955269 [ 2.254492] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10619 16:44:31.965416 [ 2.264794] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10620 16:44:31.972568 [ 2.272906] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10621 16:44:31.982418 [ 2.280999] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10622 16:44:31.989459 [ 2.289081] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10623 16:44:31.999478 [ 2.297163] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10624 16:44:32.006175 [ 2.305245] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10625 16:44:32.015624 [ 2.313326] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10626 16:44:32.022306 [ 2.321409] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10627 16:44:32.028704 [ 2.329491] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10628 16:44:32.038809 [ 2.337572] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10629 16:44:32.045302 [ 2.345654] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10630 16:44:32.055102 [ 2.353740] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10631 16:44:32.061778 [ 2.361822] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10632 16:44:32.071703 [ 2.369904] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10633 16:44:32.078341 [ 2.377988] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10634 16:44:32.084990 [ 2.386611] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10635 16:44:32.092106 [ 2.393767] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10636 16:44:32.098477 [ 2.400539] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10637 16:44:32.105358 [ 2.407379] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10638 16:44:32.112597 [ 2.414404] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10639 16:44:32.122317 [ 2.421037] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10640 16:44:32.132578 [ 2.429924] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10641 16:44:32.142238 [ 2.438792] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10642 16:44:32.148695 [ 2.447833] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10643 16:44:32.159169 [ 2.457054] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10644 16:44:32.169373 [ 2.466268] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10645 16:44:32.178930 [ 2.475135] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10646 16:44:32.185465 [ 2.484350] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10647 16:44:32.195143 [ 2.493216] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10648 16:44:32.205304 [ 2.502258] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10649 16:44:32.214750 [ 2.512162] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10650 16:44:32.224888 [ 2.523450] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10651 16:44:32.231838 [ 2.533023] Trying to probe devices needed for running init ...
10652 16:44:32.268660 [ 2.571061] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10653 16:44:32.426608 [ 2.728515] hub 1-1:1.0: USB hub found
10654 16:44:32.429322 [ 2.732689] hub 1-1:1.0: 4 ports detected
10655 16:44:32.548922 [ 2.851052] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10656 16:44:32.576335 [ 2.878688] hub 2-1:1.0: USB hub found
10657 16:44:32.579709 [ 2.882724] hub 2-1:1.0: 3 ports detected
10658 16:44:32.751973 [ 3.051063] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10659 16:44:32.882947 [ 3.184928] hub 1-1.1:1.0: USB hub found
10660 16:44:32.885938 [ 3.188950] hub 1-1.1:1.0: 4 ports detected
10661 16:44:33.000054 [ 3.298839] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10662 16:44:33.133029 [ 3.435098] hub 1-1.4:1.0: USB hub found
10663 16:44:33.135985 [ 3.439489] hub 1-1.4:1.0: 2 ports detected
10664 16:44:33.211964 [ 3.511065] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10665 16:44:33.396266 [ 3.695064] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10666 16:44:33.481058 [ 3.783300] usb 1-1.1.4: device descriptor read/64, error -32
10667 16:44:33.673018 [ 3.975265] usb 1-1.1.4: device descriptor read/64, error -32
10668 16:44:33.868163 [ 4.167062] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10669 16:44:34.055944 [ 4.355069] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10670 16:44:34.141058 [ 4.443237] usb 1-1.1.4: device descriptor read/64, error -32
10671 16:44:34.332869 [ 4.635274] usb 1-1.1.4: device descriptor read/64, error -32
10672 16:44:34.444906 [ 4.747631] usb 1-1.1-port4: attempt power cycle
10673 16:44:34.532150 [ 4.831063] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10674 16:44:35.055767 [ 5.355027] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10675 16:44:35.059144 [ 5.362147] usb 1-1.1.4: Device not responding to setup address.
10676 16:44:35.272619 [ 5.575331] usb 1-1.1.4: Device not responding to setup address.
10677 16:44:35.485172 [ 5.787083] usb 1-1.1.4: device not accepting address 10, error -71
10678 16:44:35.571740 [ 5.871063] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10679 16:44:35.574487 [ 5.878256] usb 1-1.1.4: Device not responding to setup address.
10680 16:44:35.788832 [ 6.091328] usb 1-1.1.4: Device not responding to setup address.
10681 16:44:36.000170 [ 6.302952] usb 1-1.1.4: device not accepting address 11, error -71
10682 16:44:36.007318 [ 6.309764] usb 1-1.1-port4: unable to enumerate USB device
10683 16:44:44.508957 [ 14.815630] ALSA device list:
10684 16:44:44.511759 [ 14.818604] No soundcards found.
10685 16:44:44.527305 [ 14.830785] Freeing unused kernel memory: 8384K
10686 16:44:44.530432 [ 14.835455] Run /init as init process
10687 16:44:44.540592 Loading, please wait...
10688 16:44:44.560426 Starting version 247.3-7+deb11u2
10689 16:44:44.887208 [ 15.187589] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10690 16:44:44.897464 [ 15.201077] remoteproc remoteproc0: scp is available
10691 16:44:44.907569 [ 15.206248] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10692 16:44:44.910481 [ 15.216031] remoteproc remoteproc0: powering up scp
10693 16:44:44.921117 [ 15.221547] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10694 16:44:44.928001 [ 15.231134] remoteproc remoteproc0: request_firmware failed: -2
10695 16:44:44.942046 [ 15.242083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 16:44:44.948587 [ 15.248448] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10697 16:44:44.955110 [ 15.249968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 16:44:44.964745 [ 15.257298] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10699 16:44:44.971575 [ 15.265042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 16:44:44.982015 [ 15.273473] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10701 16:44:44.994173 [ 15.294261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 16:44:44.997762 [ 15.294324] mc: Linux media interface: v0.10
10703 16:44:45.004000 [ 15.295049] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10704 16:44:45.010561 [ 15.301814] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10705 16:44:45.020598 [ 15.302145] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 16:44:45.026826 [ 15.302155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 16:44:45.033896 [ 15.315177] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10708 16:44:45.043590 [ 15.320585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 16:44:45.050437 [ 15.320593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 16:44:45.056923 [ 15.321594] usbcore: registered new interface driver r8152
10711 16:44:45.063853 [ 15.343889] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10712 16:44:45.070648 [ 15.343889] Fallback method does not support PEC.
10713 16:44:45.077519 [ 15.351794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 16:44:45.086848 [ 15.379124] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10715 16:44:45.094165 [ 15.385834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 16:44:45.100609 [ 15.399141] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10717 16:44:45.106802 [ 15.402107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 16:44:45.113676 [ 15.408113] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10719 16:44:45.120680 [ 15.408121] pci_bus 0000:00: root bus resource [bus 00-ff]
10720 16:44:45.127450 [ 15.408129] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10721 16:44:45.137051 [ 15.408135] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10722 16:44:45.143983 [ 15.408167] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10723 16:44:45.150351 [ 15.408185] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10724 16:44:45.153800 [ 15.408260] pci 0000:00:00.0: supports D1 D2
10725 16:44:45.159971 [ 15.408264] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10726 16:44:45.170141 [ 15.410010] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10727 16:44:45.176541 [ 15.411175] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10728 16:44:45.186337 [ 15.416968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 16:44:45.193240 [ 15.423676] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10730 16:44:45.199571 [ 15.428505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10731 16:44:45.209804 [ 15.429100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 16:44:45.215989 [ 15.435934] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10733 16:44:45.225731 [ 15.439201] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10734 16:44:45.235908 [ 15.439624] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10735 16:44:45.242265 [ 15.445559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 16:44:45.249032 [ 15.451573] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10737 16:44:45.256022 [ 15.452575] videodev: Linux video capture interface: v2.00
10738 16:44:45.262243 [ 15.458785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 16:44:45.269247 [ 15.459108] usbcore: registered new interface driver cdc_ether
10740 16:44:45.275673 [ 15.463070] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10741 16:44:45.281944 [ 15.463572] usbcore: registered new interface driver r8153_ecm
10742 16:44:45.288576 [ 15.469689] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 16:44:45.291949 [ 15.477812] pci 0000:01:00.0: supports D1 D2
10744 16:44:45.298571 [ 15.478646] Bluetooth: Core ver 2.22
10745 16:44:45.302082 [ 15.478748] NET: Registered PF_BLUETOOTH protocol family
10746 16:44:45.308401 [ 15.478751] Bluetooth: HCI device and connection manager initialized
10747 16:44:45.315427 [ 15.478794] Bluetooth: HCI socket layer initialized
10748 16:44:45.318262 [ 15.478804] Bluetooth: L2CAP socket layer initialized
10749 16:44:45.325063 [ 15.478818] Bluetooth: SCO socket layer initialized
10750 16:44:45.331342 [ 15.486734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 16:44:45.338372 [ 15.486796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 16:44:45.344589 [ 15.494620] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10753 16:44:45.351643 [ 15.502182] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10754 16:44:45.357789 [ 15.518876] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10755 16:44:45.371689 [ 15.526304] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10756 16:44:45.381175 [ 15.526364] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10757 16:44:45.387504 [ 15.526373] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10758 16:44:45.397325 [ 15.534077] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10759 16:44:45.404279 [ 15.534087] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10760 16:44:45.410642 [ 15.534954] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10761 16:44:45.414081 [ 15.535152] usbcore: registered new interface driver btusb
10762 16:44:45.427365 [ 15.535747] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10763 16:44:45.430890 [ 15.535761] Bluetooth: hci0: Failed to load firmware file (-2)
10764 16:44:45.437107 [ 15.535767] Bluetooth: hci0: Failed to set up firmware (-2)
10765 16:44:45.447128 [ 15.535779] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10766 16:44:45.454097 [ 15.543229] usbcore: registered new interface driver uvcvideo
10767 16:44:45.460239 [ 15.550692] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10768 16:44:45.463668 [ 15.579026] r8152 1-1.1.1:1.0 eth0: v1.12.13
10769 16:44:45.473882 [ 15.584242] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10770 16:44:45.480103 [ 15.598475] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10771 16:44:45.486410 [ 15.602146] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10772 16:44:45.489930 [ 15.795092] pci 0000:00:00.0: PCI bridge to [bus 01]
10773 16:44:45.500089 [ 15.800055] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10774 16:44:45.505996 [ 15.808015] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10775 16:44:45.512377 [ 15.815086] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10776 16:44:45.519246 [ 15.821755] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10777 16:44:45.536990 [ 15.837691] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10778 16:44:45.553951 [ 15.857980] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10779 16:44:45.564203 [ 15.864649] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10780 16:44:45.570544 [ 15.873318] cfg80211: failed to load regulatory.db
10781 16:44:45.615377 [ 15.916099] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10782 16:44:45.618799 [ 15.923356] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10783 16:44:45.645943 [ 15.949861] mt7921e 0000:01:00.0: ASIC revision: 79610010
10784 16:44:45.754373 [ 16.051254] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 16:44:45.770998 Begin: Loading essential drivers ... done.
10786 16:44:45.774392 Begin: Running /scripts/init-premount ... done.
10787 16:44:45.780778 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10788 16:44:45.790739 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10789 16:44:45.794124 Device /sys/class/net/enxf4f5e850de0a found
10790 16:44:45.794710 done.
10791 16:44:45.822730 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10792 16:44:45.875940 [ 16.173045] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 16:44:45.995202 [ 16.292581] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 16:44:46.111178 [ 16.408489] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 16:44:46.226801 [ 16.524384] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 16:44:46.342571 [ 16.640355] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 16:44:46.458654 [ 16.756237] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 16:44:46.575110 [ 16.872338] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 16:44:46.690897 [ 16.988453] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 16:44:46.806448 [ 17.104267] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 16:44:46.903290 [ 17.207487] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10802 16:44:46.913872 [ 17.218312] mt7921e 0000:01:00.0: hardware init failed
10803 16:44:46.996300 IP-Config: no response after 2 secs - giving up
10804 16:44:47.030503 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10805 16:44:47.033195 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10806 16:44:47.040032 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10807 16:44:47.049747 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10808 16:44:47.056639 host : mt8192-asurada-spherion-r0-cbg-9
10809 16:44:47.062984 domain : lava-rack
10810 16:44:47.066429 rootserver: 192.168.201.1 rootpath:
10811 16:44:47.066513 filename :
10812 16:44:47.073713 done.
10813 16:44:47.080057 Begin: Running /scripts/nfs-bottom ... done.
10814 16:44:47.098273 Begin: Running /scripts/init-bottom ... done.
10815 16:44:48.188280 [ 18.492767] NET: Registered PF_INET6 protocol family
10816 16:44:48.194878 [ 18.499445] Segment Routing with IPv6
10817 16:44:48.198411 [ 18.503164] In-situ OAM (IOAM) with IPv6
10818 16:44:48.297998 [ 18.585659] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10819 16:44:48.304761 [ 18.609074] systemd[1]: Detected architecture arm64.
10820 16:44:48.322476
10821 16:44:48.325246 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10822 16:44:48.325353
10823 16:44:48.340490 [ 18.644884] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10824 16:44:48.818957 [ 19.120319] systemd[1]: Queued start job for default target Graphical Interface.
10825 16:44:48.840010 [ 19.144123] systemd[1]: Created slice system-getty.slice.
10826 16:44:48.846454 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10827 16:44:48.863728 [ 19.167771] systemd[1]: Created slice system-modprobe.slice.
10828 16:44:48.870052 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10829 16:44:48.887635 [ 19.191592] systemd[1]: Created slice system-serial\x2dgetty.slice.
10830 16:44:48.894009 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10831 16:44:48.911553 [ 19.216106] systemd[1]: Created slice User and Session Slice.
10832 16:44:48.918376 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10833 16:44:48.938796 [ 19.239605] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10834 16:44:48.945245 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10835 16:44:48.962000 [ 19.263224] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10836 16:44:48.968552 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10837 16:44:48.989334 [ 19.287136] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10838 16:44:48.996475 [ 19.298826] systemd[1]: Reached target Local Encrypted Volumes.
10839 16:44:49.002771 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10840 16:44:49.014902 [ 19.319329] systemd[1]: Reached target Paths.
10841 16:44:49.018164 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10842 16:44:49.034733 [ 19.339106] systemd[1]: Reached target Remote File Systems.
10843 16:44:49.041171 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10844 16:44:49.054489 [ 19.359087] systemd[1]: Reached target Slices.
10845 16:44:49.058146 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10846 16:44:49.074567 [ 19.379110] systemd[1]: Reached target Swap.
10847 16:44:49.077960 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10848 16:44:49.095074 [ 19.399405] systemd[1]: Listening on initctl Compatibility Named Pipe.
10849 16:44:49.104853 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10850 16:44:49.120599 [ 19.425008] systemd[1]: Listening on Journal Audit Socket.
10851 16:44:49.127624 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10852 16:44:49.144128 [ 19.448116] systemd[1]: Listening on Journal Socket (/dev/log).
10853 16:44:49.150392 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10854 16:44:49.167480 [ 19.471871] systemd[1]: Listening on Journal Socket.
10855 16:44:49.173790 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10856 16:44:49.187697 [ 19.492370] systemd[1]: Listening on Network Service Netlink Socket.
10857 16:44:49.197825 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10858 16:44:49.213786 [ 19.517828] systemd[1]: Listening on udev Control Socket.
10859 16:44:49.220431 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10860 16:44:49.235512 [ 19.539359] systemd[1]: Listening on udev Kernel Socket.
10861 16:44:49.242217 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10862 16:44:49.291817 [ 19.595350] systemd[1]: Mounting Huge Pages File System...
10863 16:44:49.297947 Mounting [0;1;39mHuge Pages File System[0m...
10864 16:44:49.313413 [ 19.617576] systemd[1]: Mounting POSIX Message Queue File System...
10865 16:44:49.319871 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10866 16:44:49.337588 [ 19.641528] systemd[1]: Mounting Kernel Debug File System...
10867 16:44:49.343627 Mounting [0;1;39mKernel Debug File System[0m...
10868 16:44:49.362566 [ 19.663253] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10869 16:44:49.375771 [ 19.677032] systemd[1]: Starting Create list of static device nodes for the current kernel...
10870 16:44:49.382732 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10871 16:44:49.435322 [ 19.739461] systemd[1]: Starting Load Kernel Module configfs...
10872 16:44:49.441362 Starting [0;1;39mLoad Kernel Module configfs[0m...
10873 16:44:49.457252 [ 19.761440] systemd[1]: Starting Load Kernel Module drm...
10874 16:44:49.463602 Starting [0;1;39mLoad Kernel Module drm[0m...
10875 16:44:49.481145 [ 19.785507] systemd[1]: Starting Load Kernel Module fuse...
10876 16:44:49.487526 Starting [0;1;39mLoad Kernel Module fuse[0m...
10877 16:44:49.517669 [ 19.818921] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10878 16:44:49.521215 [ 19.819033] fuse: init (API version 7.37)
10879 16:44:49.530441 [ 19.834381] systemd[1]: Starting Journal Service...
10880 16:44:49.533670 Starting [0;1;39mJournal Service[0m...
10881 16:44:49.558175 [ 19.862402] systemd[1]: Starting Load Kernel Modules...
10882 16:44:49.564636 Starting [0;1;39mLoad Kernel Modules[0m...
10883 16:44:49.585008 [ 19.886023] systemd[1]: Starting Remount Root and Kernel File Systems...
10884 16:44:49.591455 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10885 16:44:49.605827 [ 19.909931] systemd[1]: Starting Coldplug All udev Devices...
10886 16:44:49.612034 Starting [0;1;39mColdplug All udev Devices[0m...
10887 16:44:49.629869 [ 19.933933] systemd[1]: Mounted Huge Pages File System.
10888 16:44:49.636193 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10889 16:44:49.651324 [ 19.955433] systemd[1]: Mounted POSIX Message Queue File System.
10890 16:44:49.657976 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10891 16:44:49.675891 [ 19.979477] systemd[1]: Mounted Kernel Debug File System.
10892 16:44:49.689012 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu[ 19.988307] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 16:44:49.689532 g File System[0m.
10894 16:44:49.715881 [ 20.016022] systemd[1]: Finished Create list of static device nodes for the current kernel.
10895 16:44:49.725804 [[0;32m OK [[ 20.025209] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 16:44:49.732023 0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10897 16:44:49.747576 [ 20.052170] systemd[1]: modprobe@configfs.service: Succeeded.
10898 16:44:49.754442 [ 20.058490] systemd[1]: Finished Load Kernel Module configfs.
10899 16:44:49.761043 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10900 16:44:49.772424 [ 20.073226] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 16:44:49.778962 [ 20.082970] systemd[1]: modprobe@drm.service: Succeeded.
10902 16:44:49.785832 [ 20.088868] systemd[1]: Finished Load Kernel Module drm.
10903 16:44:49.792182 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10904 16:44:49.806503 [ 20.107539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 16:44:49.813548 [ 20.117144] systemd[1]: modprobe@fuse.service: Succeeded.
10906 16:44:49.820084 [ 20.123227] systemd[1]: Finished Load Kernel Module fuse.
10907 16:44:49.826644 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10908 16:44:49.839551 [ 20.140497] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 16:44:49.846835 [ 20.150765] systemd[1]: Finished Load Kernel Modules.
10910 16:44:49.853106 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10911 16:44:49.867977 [ 20.172063] systemd[1]: Finished Remount Root and Kernel File Systems.
10912 16:44:49.877569 [ 20.174017] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 16:44:49.884823 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10914 16:44:49.909553 [ 20.210735] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 16:44:49.934979 [ 20.239646] systemd[1]: Mounting FUSE Control File System...
10916 16:44:49.944939 Mountin[ 20.246363] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 16:44:49.948345 g [0;1;39mFUSE Control File System[0m...
10918 16:44:49.965156 [ 20.269922] systemd[1]: Mounting Kernel Configuration File System...
10919 16:44:49.972530 Mounting [0;1;39mKernel Configuration File System[0m...
10920 16:44:49.992283 [ 20.293727] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10921 16:44:50.002127 [ 20.302498] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10922 16:44:50.031157 [ 20.335729] systemd[1]: Starting Load/Save Random Seed...
10923 16:44:50.037931 Starting [0;1;39mLoad/Save Random Seed[0m...
10924 16:44:50.053339 [ 20.357860] systemd[1]: Starting Apply Kernel Variables...
10925 16:44:50.059765 Starting [0;1;39mApply Kernel Variables[0m...
10926 16:44:50.078821 [ 20.383004] systemd[1]: Starting Create System Users...
10927 16:44:50.085682 [ 20.388326] power_supply_show_property: 2 callbacks suppressed
10928 16:44:50.092076 [ 20.388339] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 16:44:50.098960 Starting [0;1;39mCreate System Users[0m...
10930 16:44:50.116029 [ 20.417414] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 16:44:50.123736 [ 20.427960] systemd[1]: Started Journal Service.
10932 16:44:50.126643 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10933 16:44:50.144365 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10934 16:44:50.166197 [[0;32m OK [0m] Mounted [0;1;39mKernel Conf[ 20.466567] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 16:44:50.176047 [ 20.468706] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10936 16:44:50.193207 iguration File S[ 20.485056] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10937 16:44:50.199841 [ 20.496998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 16:44:50.209487 [ 20.501814] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10939 16:44:50.209567 ystem[0m.
10940 16:44:50.231137 [[0;32m OK [0m] Finished [0;1;39mLoad/Save [ 20.531618] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 16:44:50.234583 Random Seed[0m.
10942 16:44:50.251810 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10943 16:44:50.265136 [ 20.565998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 16:44:50.271525 See 'systemctl status systemd-udev-trigger.service' for details.
10945 16:44:50.298571 [[0;32m OK [0m] Finished [0;1;39mApply Kern[ 20.599428] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 16:44:50.301981 el Variables[0m.
10947 16:44:50.319649 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10948 16:44:50.331827 [ 20.632836] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 16:44:50.365681 [ 20.666900] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 16:44:50.375624 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10951 16:44:50.393518 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10952 16:44:50.445435 [ 20.746285] systemd-journald[292]: Received client request to flush runtime journal.
10953 16:44:50.464199 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10954 16:44:50.483421 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10955 16:44:50.503036 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10956 16:44:50.550741 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10957 16:44:51.814106 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10958 16:44:51.868387 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10959 16:44:51.891012 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10960 16:44:51.916756 Starting [0;1;39mNetwork Service[0m...
10961 16:44:52.238572 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10962 16:44:52.261317 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10963 16:44:52.326557 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10964 16:44:52.480832 [ 22.785730] remoteproc remoteproc0: powering up scp
10965 16:44:52.497186 [ 22.798401] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10966 16:44:52.503627 [ 22.808189] remoteproc remoteproc0: request_firmware failed: -2
10967 16:44:52.509945 [ 22.814162] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10968 16:44:52.628408 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10969 16:44:52.642928 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10970 16:44:52.664369 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10971 16:44:52.681649 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10972 16:44:52.698614 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10973 16:44:52.751382 Starting [0;1;39mNetwork Name Resolution[0m...
10974 16:44:52.769601 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10975 16:44:52.795128 Starting [0;1;39mNetwork Time Synchronization[0m...
10976 16:44:52.813287 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10977 16:44:52.835353 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10978 16:44:52.871575 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10979 16:44:53.029879 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10980 16:44:53.046883 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10981 16:44:53.069488 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10982 16:44:53.082421 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10983 16:44:53.102043 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10984 16:44:53.193001 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10985 16:44:53.235022 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10986 16:44:53.267291 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10987 16:44:53.294902 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10988 16:44:53.310580 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10989 16:44:53.330618 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10990 16:44:53.342104 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10991 16:44:53.358402 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10992 16:44:53.402991 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10993 16:44:53.432982 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10994 16:44:53.468354 Starting [0;1;39mUser Login Management[0m...
10995 16:44:53.483226 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10996 16:44:53.499317 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10997 16:44:53.521186 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10998 16:44:53.578844 Starting [0;1;39mPermit User Sessions[0m...
10999 16:44:53.719560 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11000 16:44:53.754908 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11001 16:44:53.810727 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11002 16:44:53.826558 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11003 16:44:53.847183 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11004 16:44:53.864443 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11005 16:44:53.883146 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11006 16:44:53.898548 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11007 16:44:53.934806 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11008 16:44:53.966429 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11009 16:44:54.014610
11010 16:44:54.014784
11011 16:44:54.018008 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11012 16:44:54.018116
11013 16:44:54.021501 debian-bullseye-arm64 login: root (automatic login)
11014 16:44:54.021603
11015 16:44:54.021701
11016 16:44:54.248946 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023 aarch64
11017 16:44:54.249117
11018 16:44:54.255560 The programs included with the Debian GNU/Linux system are free software;
11019 16:44:54.262260 the exact distribution terms for each program are described in the
11020 16:44:54.265111 individual files in /usr/share/doc/*/copyright.
11021 16:44:54.265232
11022 16:44:54.272183 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11023 16:44:54.272283 permitted by applicable law.
11024 16:44:54.336305 Matched prompt #10: / #
11026 16:44:54.336586 Setting prompt string to ['/ #']
11027 16:44:54.336682 end: 2.2.5.1 login-action (duration 00:00:24) [common]
11029 16:44:54.336883 end: 2.2.5 auto-login-action (duration 00:00:25) [common]
11030 16:44:54.336975 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
11031 16:44:54.337061 Setting prompt string to ['/ #']
11032 16:44:54.337130 Forcing a shell prompt, looking for ['/ #']
11034 16:44:54.387331 / #
11035 16:44:54.387471 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11036 16:44:54.387555 Waiting using forced prompt support (timeout 00:02:30)
11037 16:44:54.392145
11038 16:44:54.392415 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11039 16:44:54.392513 start: 2.2.7 export-device-env (timeout 00:03:42) [common]
11041 16:44:54.492828 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576288/extract-nfsrootfs-irjyd3ff'
11042 16:44:54.497774 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576288/extract-nfsrootfs-irjyd3ff'
11044 16:44:54.598314 / # export NFS_SERVER_IP='192.168.201.1'
11045 16:44:54.603027 export NFS_SERVER_IP='192.168.201.1'
11046 16:44:54.603366 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11047 16:44:54.603468 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
11048 16:44:54.603560 end: 2 depthcharge-action (duration 00:01:18) [common]
11049 16:44:54.603657 start: 3 lava-test-retry (timeout 00:30:00) [common]
11050 16:44:54.603747 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11051 16:44:54.603824 Using namespace: common
11053 16:44:54.704139 / # #
11054 16:44:54.704291 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11055 16:44:54.709069 #
11056 16:44:54.709333 Using /lava-10576288
11058 16:44:54.809659 / # export SHELL=/bin/sh
11059 16:44:54.815052 export SHELL=/bin/sh
11061 16:44:54.916425 / # . /lava-10576288/environment
11062 16:44:54.922407 . /lava-10576288/environment
11064 16:44:55.028099 / # /lava-10576288/bin/lava-test-runner /lava-10576288/0
11065 16:44:55.028743 Test shell timeout: 10s (minimum of the action and connection timeout)
11066 16:44:55.033735 /lava-10576288/bin/lava-test-runner /lava-10576288/0
11067 16:44:55.220420 + export TESTRUN_ID=0_lc-compliance
11068 16:44:55.227412 + cd /lava-10576288/0/tests/0_lc-compliance
11069 16:44:55.227527 + cat uuid
11070 16:44:55.230382 + UUID=10576288_1.6.2.3.1
11071 16:44:55.230458 + set +x
11072 16:44:55.233867 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10576288_1.6.2.3.1>
11073 16:44:55.234112 Received signal: <STARTRUN> 0_lc-compliance 10576288_1.6.2.3.1
11074 16:44:55.234182 Starting test lava.0_lc-compliance (10576288_1.6.2.3.1)
11075 16:44:55.234267 Skipping test definition patterns.
11076 16:44:55.236981 + /usr/bin/lc-compliance-parser.sh
11077 16:44:56.348815 [0:00:26.642794479] [403] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-76e1cb9f
11078 16:44:56.352139 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11079 16:44:56.362481 [0:00:26.657973312] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11080 16:44:56.418618 [0:00:26.712292270] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11081 16:44:56.422123 [==========] Running 120 tests from 1 test suite.
11082 16:44:56.470101 [0:00:26.764064961] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11083 16:44:56.473641 [----------] Global test environment set-up.
11084 16:44:56.521498 [0:00:26.815137499] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11085 16:44:56.525271 [----------] 120 tests from CaptureTests/SingleStream
11086 16:44:56.573088 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11087 16:44:56.614925 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11088 16:44:56.615223 Received signal: <TESTSET> START CaptureTests/SingleStream
11089 16:44:56.615314 Starting test_set CaptureTests/SingleStream
11090 16:44:56.618344 Camera needs 4 requests, can't test only 1
11091 16:44:56.665889 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11092 16:44:56.717729
11093 16:44:56.770710 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (55 ms)
11094 16:44:56.834675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11095 16:44:56.835012 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11097 16:44:56.844809 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11098 16:44:56.883006 [0:00:27.176488688] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11099 16:44:56.886195 Camera needs 4 requests, can't test only 2
11100 16:44:56.942503 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11101 16:44:56.998777
11102 16:44:57.063095 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (51 ms)
11103 16:44:57.123889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11104 16:44:57.124195 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11106 16:44:57.133562 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11107 16:44:57.168790 Camera needs 4 requests, can't test only 3
11108 16:44:57.224702 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11109 16:44:57.269730
11110 16:44:57.323217 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (51 ms)
11111 16:44:57.344956 [0:00:27.637966885] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11112 16:44:57.382790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11113 16:44:57.383110 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11115 16:44:57.393528 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11116 16:44:57.435801 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (361 ms)
11117 16:44:57.494508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11118 16:44:57.494980 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11120 16:44:57.505530 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11121 16:44:57.543122 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (461 ms)
11122 16:44:57.601962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11123 16:44:57.602287 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11125 16:44:57.612635 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11126 16:44:58.029286 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (692 ms)
11127 16:44:58.039359 [0:00:28.330165205] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11128 16:44:58.112378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11129 16:44:58.113350 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11131 16:44:58.125059 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11132 16:44:59.022554 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (992 ms)
11133 16:44:59.031775 [0:00:29.322173685] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11134 16:44:59.081130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11135 16:44:59.081702 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11137 16:44:59.092863 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11138 16:45:00.350722 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1328 ms)
11139 16:45:00.360391 [0:00:30.650331557] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11140 16:45:00.414935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11141 16:45:00.415296 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11143 16:45:00.425445 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11144 16:45:02.476069 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2124 ms)
11145 16:45:02.485578 [0:00:32.774977286] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11146 16:45:02.555852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11147 16:45:02.556700 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11149 16:45:02.570140 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11150 16:45:05.701586 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3224 ms)
11151 16:45:05.711493 [0:00:35.998412278] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11152 16:45:05.761115 [0:00:36.049995417] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11153 16:45:05.784379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11154 16:45:05.784936 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11156 16:45:05.797312 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11157 16:45:05.812298 [0:00:36.101895112] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11158 16:45:05.836920 Camera needs 4 requests, can't test only 1
11159 16:45:05.864514 [0:00:36.153778814] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11160 16:45:05.897077 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11161 16:45:05.949342
11162 16:45:06.006923 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (51 ms)
11163 16:45:06.070651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11164 16:45:06.070977 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11166 16:45:06.080907 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11167 16:45:06.114010 Camera needs 4 requests, can't test only 2
11168 16:45:06.162299 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11169 16:45:06.209102
11170 16:45:06.226663 [0:00:36.516176280] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11171 16:45:06.261391 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (52 ms)
11172 16:45:06.318744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11173 16:45:06.319078 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11175 16:45:06.328428 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11176 16:45:06.363320 Camera needs 4 requests, can't test only 3
11177 16:45:06.413130 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11178 16:45:06.457920
11179 16:45:06.507085 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (52 ms)
11180 16:45:06.560121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11181 16:45:06.560422 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11183 16:45:06.570091 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11184 16:45:06.605889 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (362 ms)
11185 16:45:06.660383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11186 16:45:06.660719 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11188 16:45:06.669165 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11189 16:45:06.689966 [0:00:36.978905203] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11190 16:45:06.707269 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (463 ms)
11191 16:45:06.761644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11192 16:45:06.761965 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11194 16:45:06.771923 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11195 16:45:07.374267 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (692 ms)
11196 16:45:07.386976 [0:00:37.671344180] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11197 16:45:07.431106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11198 16:45:07.431396 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11200 16:45:07.444026 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11201 16:45:08.304530 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (930 ms)
11202 16:45:08.317298 [0:00:38.600571067] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11203 16:45:08.379986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11204 16:45:08.380780 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11206 16:45:08.392087 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11207 16:45:09.696162 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1391 ms)
11208 16:45:09.709082 [0:00:39.992278284] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11209 16:45:09.751620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11210 16:45:09.751958 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11212 16:45:09.762764 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11213 16:45:11.788550 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2091 ms)
11214 16:45:11.801287 [0:00:42.083933844] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11215 16:45:11.848109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11216 16:45:11.848430 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11218 16:45:11.859724 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11219 16:45:14.983948 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3195 ms)
11220 16:45:14.996735 [0:00:45.279236113] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11221 16:45:15.043275 [0:00:45.330750535] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11222 16:45:15.049847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11223 16:45:15.050113 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11225 16:45:15.061587 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11226 16:45:15.095476 [0:00:45.382626266] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11227 16:45:15.098384 Camera needs 4 requests, can't test only 1
11228 16:45:15.146820 [0:00:45.434237595] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 16:45:15.159542 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11230 16:45:15.210436
11231 16:45:15.272936 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (52 ms)
11232 16:45:15.337833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11233 16:45:15.338151 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11235 16:45:15.348468 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11236 16:45:15.383811 Camera needs 4 requests, can't test only 2
11237 16:45:15.432126 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11238 16:45:15.480418
11239 16:45:15.508308 [0:00:45.795478369] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11240 16:45:15.539033 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (51 ms)
11241 16:45:15.595053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11242 16:45:15.595412 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11244 16:45:15.605062 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11245 16:45:15.639874 Camera needs 4 requests, can't test only 3
11246 16:45:15.692292 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11247 16:45:15.743243
11248 16:45:15.746630 [ 46.057510] vpu: disabling
11249 16:45:15.750315 [ 46.060324] vproc2: disabling
11250 16:45:15.753440 [ 46.063339] vproc1: disabling
11251 16:45:15.756696 [ 46.066348] vaud18: disabling
11252 16:45:15.760350 [ 46.069495] vsram_others: disabling
11253 16:45:15.763347 [ 46.073102] va09: disabling
11254 16:45:15.766794 [ 46.076023] vsram_md: disabling
11255 16:45:15.770581 [ 46.079264] Vgpu: disabling
11256 16:45:15.798975 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (52 ms)
11257 16:45:15.853177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11258 16:45:15.853523 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11260 16:45:15.863265 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11261 16:45:15.894702 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (361 ms)
11262 16:45:15.945585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11263 16:45:15.945887 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11265 16:45:15.954359 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11266 16:45:15.970222 [0:00:46.257493970] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11267 16:45:15.992275 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (463 ms)
11268 16:45:16.058575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11269 16:45:16.058904 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11271 16:45:16.068444 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11272 16:45:16.655373 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (693 ms)
11273 16:45:16.668744 [0:00:46.951015193] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11274 16:45:16.717683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11275 16:45:16.718001 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11277 16:45:16.729131 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11278 16:45:17.648843 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (993 ms)
11279 16:45:17.661356 [0:00:47.943752716] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11280 16:45:17.713843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11281 16:45:17.714132 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11283 16:45:17.723814 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11284 16:45:19.041630 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1392 ms)
11285 16:45:19.054763 [0:00:49.336654095] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 16:45:19.113885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11287 16:45:19.114194 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11289 16:45:19.125822 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11290 16:45:21.143574 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2098 ms)
11291 16:45:21.153465 [0:00:51.435542783] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 16:45:21.211316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11293 16:45:21.211647 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11295 16:45:21.222814 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11296 16:45:24.342382 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3201 ms)
11297 16:45:24.355592 [0:00:54.637173743] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11298 16:45:24.408941 [0:00:54.695852705] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11299 16:45:24.424360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11300 16:45:24.424690 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11302 16:45:24.436647 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11303 16:45:24.468841 [0:00:54.755502468] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11304 16:45:24.474975 Camera needs 4 requests, can't test only 1
11305 16:45:24.520465 [0:00:54.807523888] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11306 16:45:24.528321 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11307 16:45:24.577424
11308 16:45:24.633204 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (59 ms)
11309 16:45:24.689381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11310 16:45:24.689711 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11312 16:45:24.698943 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11313 16:45:24.732875 Camera needs 4 requests, can't test only 2
11314 16:45:24.785925 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11315 16:45:24.837736
11316 16:45:24.882888 [0:00:55.169802755] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11317 16:45:24.896522 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (59 ms)
11318 16:45:24.958028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11319 16:45:24.958347 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11321 16:45:24.968624 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11322 16:45:25.008543 Camera needs 4 requests, can't test only 3
11323 16:45:25.065336 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11324 16:45:25.112352
11325 16:45:25.164286 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (53 ms)
11326 16:45:25.217357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11327 16:45:25.217684 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11329 16:45:25.228153 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11330 16:45:25.264975 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (362 ms)
11331 16:45:25.318791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11332 16:45:25.319120 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11334 16:45:25.328904 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11335 16:45:25.344543 [0:00:55.631745608] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11336 16:45:25.368400 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (462 ms)
11337 16:45:25.425378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11338 16:45:25.425705 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11340 16:45:25.435817 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11341 16:45:26.030263 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (693 ms)
11342 16:45:26.043676 [0:00:56.325596106] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11343 16:45:26.095208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11344 16:45:26.095538 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11346 16:45:26.105337 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11347 16:45:26.960372 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (930 ms)
11348 16:45:26.973591 [0:00:57.255504112] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11349 16:45:27.022698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11350 16:45:27.023020 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11352 16:45:27.033634 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11353 16:45:28.352967 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1393 ms)
11354 16:45:28.365714 [0:00:58.647699454] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11355 16:45:28.410331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11356 16:45:28.410652 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11358 16:45:28.420554 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11359 16:45:30.445400 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2092 ms)
11360 16:45:30.458348 [0:01:00.741489111] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11361 16:45:30.513546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11362 16:45:30.513867 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11364 16:45:30.524846 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11365 16:45:33.641912 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3197 ms)
11366 16:45:33.655155 [0:01:03.937327540] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11367 16:45:33.701661 [0:01:03.988448384] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11368 16:45:33.722104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11369 16:45:33.722816 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11371 16:45:33.736093 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11372 16:45:33.752897 [0:01:04.039554999] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11373 16:45:33.781269 Camera needs 4 requests, can't test only 1
11374 16:45:33.805259 [0:01:04.092307728] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 16:45:33.845783 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11376 16:45:33.902392
11377 16:45:33.964274 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (52 ms)
11378 16:45:34.030197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11379 16:45:34.030497 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11381 16:45:34.041168 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11382 16:45:34.077745 Camera needs 4 requests, can't test only 2
11383 16:45:34.130498 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11384 16:45:34.188738
11385 16:45:34.246822 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (51 ms)
11386 16:45:34.312066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11387 16:45:34.312777 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11389 16:45:34.324256 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11390 16:45:34.365682 Camera needs 4 requests, can't test only 3
11391 16:45:34.421732 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11392 16:45:34.469893
11393 16:45:34.519709 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (52 ms)
11394 16:45:34.579592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11395 16:45:34.579900 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11397 16:45:34.590167 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11398 16:45:34.877360 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1080 ms)
11399 16:45:34.890470 [0:01:05.172091164] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11400 16:45:34.955891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11401 16:45:34.956836 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11403 16:45:34.966960 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11404 16:45:36.258089 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1381 ms)
11405 16:45:36.271177 [0:01:06.552551360] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11406 16:45:36.335533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11407 16:45:36.336276 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11409 16:45:36.346581 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11410 16:45:38.297806 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2040 ms)
11411 16:45:38.310752 [0:01:08.592683491] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 16:45:38.359082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11413 16:45:38.359411 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11415 16:45:38.370033 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11416 16:45:40.973415 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2676 ms)
11417 16:45:40.986240 [0:01:11.268580185] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11418 16:45:41.038464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11419 16:45:41.038769 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11421 16:45:41.049559 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11422 16:45:45.079739 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4107 ms)
11423 16:45:45.093259 [0:01:15.375791411] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11424 16:45:45.149750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11425 16:45:45.150042 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11427 16:45:45.161342 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11428 16:45:51.317746 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6238 ms)
11429 16:45:51.330715 [0:01:21.614403811] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 16:45:51.377586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11431 16:45:51.377889 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11433 16:45:51.387216 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11434 16:46:00.924144 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9607 ms)
11435 16:46:00.937646 [0:01:31.222121089] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 16:46:00.984750 [0:01:31.273857176] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11437 16:46:00.991313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11438 16:46:00.991599 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11440 16:46:00.998321 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11441 16:46:01.036386 [0:01:31.324946556] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11442 16:46:01.039201 Camera needs 4 requests, can't test only 1
11443 16:46:01.087389 [0:01:31.376327468] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 16:46:01.091030 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11445 16:46:01.129763
11446 16:46:01.180072 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (53 ms)
11447 16:46:01.231139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11448 16:46:01.231461 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11450 16:46:01.238621 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11451 16:46:01.271066 Camera needs 4 requests, can't test only 2
11452 16:46:01.317969 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11453 16:46:01.363171
11454 16:46:01.417493 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (51 ms)
11455 16:46:01.477023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11456 16:46:01.477367 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11458 16:46:01.483791 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11459 16:46:01.518105 Camera needs 4 requests, can't test only 3
11460 16:46:01.564641 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11461 16:46:01.608444
11462 16:46:01.664278 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (51 ms)
11463 16:46:01.720262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11464 16:46:01.720588 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11466 16:46:01.726523 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11467 16:46:02.161685 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1078 ms)
11468 16:46:02.171356 [0:01:32.455882366] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11469 16:46:02.236225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11470 16:46:02.236580 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11472 16:46:02.243318 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11473 16:46:03.539676 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1378 ms)
11474 16:46:03.550034 [0:01:33.833418109] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11475 16:46:03.598264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11476 16:46:03.598672 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11478 16:46:03.605045 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11479 16:46:05.579643 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2040 ms)
11480 16:46:05.590072 [0:01:35.873394003] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 16:46:05.641406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11482 16:46:05.641726 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11484 16:46:05.647894 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11485 16:46:08.353919 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2774 ms)
11486 16:46:08.363686 [0:01:38.647689100] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11487 16:46:08.410520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11488 16:46:08.410846 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11490 16:46:08.417440 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11491 16:46:12.461595 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4108 ms)
11492 16:46:12.471212 [0:01:42.755460776] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11493 16:46:12.518963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11494 16:46:12.519267 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11496 16:46:12.525894 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11497 16:46:18.700261 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6239 ms)
11498 16:46:18.710227 [0:01:48.995117611] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11499 16:46:18.758927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11500 16:46:18.759333 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11502 16:46:18.767419 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11503 16:46:28.434043 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9734 ms)
11504 16:46:28.444047 [0:01:58.728112187] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 16:46:28.490610 [0:01:58.779645719] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11506 16:46:28.497439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11507 16:46:28.497760 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11509 16:46:28.503862 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11510 16:46:28.534110 Camera needs 4 requests, can't test only 1
11511 16:46:28.543570 [0:01:58.831892196] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11512 16:46:28.580501 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11513 16:46:28.594506 [0:01:58.883525336] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11514 16:46:28.625837
11515 16:46:28.677281 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (51 ms)
11516 16:46:28.729411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11517 16:46:28.729751 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11519 16:46:28.736412 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11520 16:46:28.768910 Camera needs 4 requests, can't test only 2
11521 16:46:28.812151 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11522 16:46:28.854721
11523 16:46:28.910924 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (52 ms)
11524 16:46:28.972998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11525 16:46:28.973340 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11527 16:46:28.979377 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11528 16:46:29.012485 Camera needs 4 requests, can't test only 3
11529 16:46:29.056125 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11530 16:46:29.098504
11531 16:46:29.149507 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (52 ms)
11532 16:46:29.200541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11533 16:46:29.200860 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11535 16:46:29.208171 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11536 16:46:29.669837 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1080 ms)
11537 16:46:29.679288 [0:01:59.964734879] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11538 16:46:29.741609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11539 16:46:29.741946 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11541 16:46:29.748137 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11542 16:46:31.054431 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1385 ms)
11543 16:46:31.063922 [0:02:01.348414396] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11544 16:46:31.119981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11545 16:46:31.120306 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11547 16:46:31.126761 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11548 16:46:33.096635 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2042 ms)
11549 16:46:33.106822 [0:02:03.391722483] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 16:46:33.171206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11551 16:46:33.171526 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11553 16:46:33.178218 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11554 16:46:35.809352 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2713 ms)
11555 16:46:35.819435 [0:02:06.103862743] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11556 16:46:35.873347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11557 16:46:35.873668 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11559 16:46:35.882044 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11560 16:46:39.917492 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4108 ms)
11561 16:46:39.927330 [0:02:10.211952346] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11562 16:46:39.981463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11563 16:46:39.981783 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11565 16:46:39.990347 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11566 16:46:46.253528 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6337 ms)
11567 16:46:46.263602 [0:02:16.548359484] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 16:46:46.310935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11569 16:46:46.311243 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11571 16:46:46.317835 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11572 16:46:55.922298 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9668 ms)
11573 16:46:55.931720 [0:02:26.216377418] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11574 16:46:55.982471 [0:02:26.272561950] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11575 16:46:56.008189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11576 16:46:56.009003 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11578 16:46:56.017904 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11579 16:46:56.040298 [0:02:26.330487736] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11580 16:46:56.067943 Camera needs 4 requests, can't test only 1
11581 16:46:56.097720 [0:02:26.387849875] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 16:46:56.140499 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11583 16:46:56.197296
11584 16:46:56.268259 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (56 ms)
11585 16:46:56.334930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11586 16:46:56.335703 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11588 16:46:56.344649 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11589 16:46:56.388711 Camera needs 4 requests, can't test only 2
11590 16:46:56.455544 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11591 16:46:56.526656
11592 16:46:56.586276 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (57 ms)
11593 16:46:56.642114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11594 16:46:56.642410 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11596 16:46:56.648075 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11597 16:46:56.685845 Camera needs 4 requests, can't test only 3
11598 16:46:56.735240 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11599 16:46:56.779964
11600 16:46:56.834839 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (57 ms)
11601 16:46:56.889354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11602 16:46:56.889639 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11604 16:46:56.896121 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11605 16:46:57.355932 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1263 ms)
11606 16:46:57.366065 [0:02:27.651789435] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11607 16:46:57.417028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11608 16:46:57.417350 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11610 16:46:57.423359 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11611 16:46:58.879141 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1523 ms)
11612 16:46:58.889037 [0:02:29.175446922] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11613 16:46:58.955388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11614 16:46:58.956109 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11616 16:46:58.963568 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11617 16:47:01.001804 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2123 ms)
11618 16:47:01.011512 [0:02:31.297302821] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11619 16:47:01.065143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11620 16:47:01.065464 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11622 16:47:01.072073 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11623 16:47:03.692477 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2691 ms)
11624 16:47:03.702600 [0:02:33.990316185] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11625 16:47:03.777108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11626 16:47:03.777421 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11628 16:47:03.783430 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11629 16:47:07.806897 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4115 ms)
11630 16:47:07.817026 [0:02:38.103209316] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11631 16:47:07.876828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11632 16:47:07.877127 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11634 16:47:07.885827 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11635 16:47:14.125124 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6318 ms)
11636 16:47:14.135244 [0:02:44.422647548] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11637 16:47:14.191054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11638 16:47:14.191383 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11640 16:47:14.197769 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11641 16:47:23.876275 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9751 ms)
11642 16:47:23.885981 [0:02:54.172971548] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11643 16:47:23.955041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11644 16:47:23.955797 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11646 16:47:23.963939 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11647 16:47:24.170849 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (298 ms)
11648 16:47:24.183786 [0:02:54.471261487] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11649 16:47:24.240151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11650 16:47:24.240429 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11652 16:47:24.249928 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11653 16:47:24.470561 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (300 ms)
11654 16:47:24.483601 [0:02:54.770884661] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11655 16:47:24.555420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11656 16:47:24.555736 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11658 16:47:24.567587 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11659 16:47:24.770077 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (300 ms)
11660 16:47:24.782940 [0:02:55.070632523] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11661 16:47:24.848119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11662 16:47:24.848578 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11664 16:47:24.859867 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11665 16:47:25.136064 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (365 ms)
11666 16:47:25.148450 [0:02:55.436260057] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11667 16:47:25.207768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11668 16:47:25.208091 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11670 16:47:25.216648 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11671 16:47:25.602990 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (467 ms)
11672 16:47:25.615924 [0:02:55.903784900] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11673 16:47:25.680110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11674 16:47:25.680891 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11676 16:47:25.691284 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11677 16:47:26.301839 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (698 ms)
11678 16:47:26.315437 [0:02:56.603415571] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11679 16:47:26.372329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11680 16:47:26.372610 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11682 16:47:26.383125 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11683 16:47:27.202169 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (900 ms)
11684 16:47:27.214581 [0:02:57.503305130] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11685 16:47:27.274288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11686 16:47:27.274554 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11688 16:47:27.285000 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11689 16:47:28.600142 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1399 ms)
11690 16:47:28.612647 [0:02:58.900244969] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11691 16:47:28.669796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11692 16:47:28.670065 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11694 16:47:28.680852 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11695 16:47:30.697557 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2097 ms)
11696 16:47:30.710658 [0:03:00.999514490] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11697 16:47:30.784096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11698 16:47:30.785247 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11700 16:47:30.795027 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11701 16:47:33.899040 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3202 ms)
11702 16:47:33.912049 [0:03:04.199840098] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11703 16:47:33.978964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11704 16:47:33.979313 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11706 16:47:33.988759 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11707 16:47:34.200875 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (298 ms)
11708 16:47:34.210115 [0:03:04.499511054] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11709 16:47:34.265138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11710 16:47:34.265444 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11712 16:47:34.272140 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11713 16:47:34.501635 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (300 ms)
11714 16:47:34.511294 [0:03:04.800645151] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11715 16:47:34.578741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11716 16:47:34.579532 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11718 16:47:34.587767 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11719 16:47:34.804102 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (303 ms)
11720 16:47:34.813937 [0:03:05.103001292] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11721 16:47:34.878363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11722 16:47:34.878657 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11724 16:47:34.885699 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11725 16:47:35.269142 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (465 ms)
11726 16:47:35.279001 [0:03:05.568946430] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11727 16:47:35.347061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11728 16:47:35.347378 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11730 16:47:35.353646 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11731 16:47:35.838428 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (569 ms)
11732 16:47:35.848009 [0:03:06.136246899] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11733 16:47:35.909311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11734 16:47:35.909579 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11736 16:47:35.915849 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11737 16:47:36.536425 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (698 ms)
11738 16:47:36.545773 [0:03:06.835752506] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11739 16:47:36.627327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11740 16:47:36.628176 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11742 16:47:36.636148 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11743 16:47:37.439306 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (903 ms)
11744 16:47:37.448833 [0:03:07.737957396] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11745 16:47:37.529840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11746 16:47:37.530145 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11748 16:47:37.536465 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11749 16:47:38.838477 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1400 ms)
11750 16:47:38.847745 [0:03:09.136406780] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11751 16:47:38.898275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11752 16:47:38.898597 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11754 16:47:38.904937 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11755 16:47:40.968303 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2130 ms)
11756 16:47:40.978277 [0:03:11.267865095] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11757 16:47:41.031727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11758 16:47:41.032052 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11760 16:47:41.038300 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11761 16:47:44.199621 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3231 ms)
11762 16:47:44.209197 [0:03:14.499389178] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11763 16:47:44.260973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11764 16:47:44.261275 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11766 16:47:44.267551 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11767 16:47:44.499242 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (300 ms)
11768 16:47:44.508952 [0:03:14.799669810] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11769 16:47:44.565703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11770 16:47:44.566031 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11772 16:47:44.571839 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11773 16:47:44.802292 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (303 ms)
11774 16:47:44.811978 [0:03:15.101382715] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11775 16:47:44.860429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11776 16:47:44.860725 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11778 16:47:44.867150 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11779 16:47:45.102567 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (301 ms)
11780 16:47:45.112209 [0:03:15.403295631] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11781 16:47:45.170942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11782 16:47:45.171284 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11784 16:47:45.177654 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11785 16:47:45.569415 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (466 ms)
11786 16:47:45.579550 [0:03:15.868274417] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11787 16:47:45.637298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11788 16:47:45.637589 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11790 16:47:45.643464 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11791 16:47:46.035706 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (466 ms)
11792 16:47:46.045965 [0:03:16.335504077] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11793 16:47:46.098197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11794 16:47:46.098512 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11796 16:47:46.104826 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11797 16:47:46.734350 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (698 ms)
11798 16:47:46.744403 [0:03:17.033653889] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11799 16:47:46.814809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11800 16:47:46.815101 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11802 16:47:46.822277 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11803 16:47:47.669302 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (936 ms)
11804 16:47:47.679879 [0:03:17.968470672] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11805 16:47:47.733406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11806 16:47:47.733715 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11808 16:47:47.740771 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11809 16:47:48.999261 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1330 ms)
11810 16:47:49.008954 [0:03:19.298683695] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11811 16:47:49.059578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11812 16:47:49.059904 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11814 16:47:49.068408 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11815 16:47:51.124548 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2125 ms)
11816 16:47:51.134527 [0:03:21.424317432] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11817 16:47:51.191069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11818 16:47:51.191455 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11820 16:47:51.202046 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11821 16:47:54.285183 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3161 ms)
11822 16:47:54.295022 [0:03:24.584978111] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11823 16:47:54.347809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11824 16:47:54.348178 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11826 16:47:54.356828 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11827 16:47:54.578450 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (293 ms)
11828 16:47:54.588608 [0:03:24.878641632] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11829 16:47:54.640841 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11831 16:47:54.643597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11832 16:47:54.652559 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11833 16:47:54.840466 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (262 ms)
11834 16:47:54.850361 [0:03:25.140528186] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11835 16:47:54.915158 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11837 16:47:54.918256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11838 16:47:54.927873 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11839 16:47:55.135734 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (295 ms)
11840 16:47:55.145518 [0:03:25.435662919] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11841 16:47:55.197064 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11843 16:47:55.200107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11844 16:47:55.206661 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11845 16:47:55.497272 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (361 ms)
11846 16:47:55.506980 [0:03:25.797509847] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11847 16:47:55.555884 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11849 16:47:55.558733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11850 16:47:55.565595 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11851 16:47:55.959140 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (462 ms)
11852 16:47:55.969344 [0:03:26.259430347] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11853 16:47:56.020224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11854 16:47:56.020552 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11856 16:47:56.029627 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11857 16:47:56.652553 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (693 ms)
11858 16:47:56.662275 [0:03:26.953954327] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11859 16:47:56.714211 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11861 16:47:56.717533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11862 16:47:56.724101 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11863 16:47:57.583957 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (931 ms)
11864 16:47:57.593403 [0:03:27.883860900] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11865 16:47:57.650277 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11867 16:47:57.653240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11868 16:47:57.659913 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11869 16:47:58.975981 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1392 ms)
11870 16:47:58.986140 [0:03:29.276421899] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11871 16:47:59.042174 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11873 16:47:59.044913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11874 16:47:59.055339 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11875 16:48:01.068919 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2093 ms)
11876 16:48:01.078772 [0:03:31.371132860] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11877 16:48:01.137611 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11879 16:48:01.140847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11880 16:48:01.148118 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11881 16:48:04.266561 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3198 ms)
11882 16:48:04.332515 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11884 16:48:04.335475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11885 16:48:04.342670 [----------] 120 tests from CaptureTests/SingleStream (187910 ms total)
11886 16:48:04.393154
11887 16:48:04.448983 [----------] Global test environment tear-down
11888 16:48:04.502013 [==========] 120 tests from 1 test suite ran. (187910 ms total)
11889 16:48:04.552062 <LAVA_SIGNAL_TESTSET STOP>
11890 16:48:04.552501 Received signal: <TESTSET> STOP
11891 16:48:04.552617 Closing test_set CaptureTests/SingleStream
11892 16:48:04.558610 + set +x
11893 16:48:04.562039 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10576288_1.6.2.3.1>
11894 16:48:04.562289 Received signal: <ENDRUN> 0_lc-compliance 10576288_1.6.2.3.1
11895 16:48:04.562370 Ending use of test pattern.
11896 16:48:04.562432 Ending test lava.0_lc-compliance (10576288_1.6.2.3.1), duration 189.33
11898 16:48:04.564745 <LAVA_TEST_RUNNER EXIT>
11899 16:48:04.565028 ok: lava_test_shell seems to have completed
11900 16:48:04.566873 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11901 16:48:04.567049 end: 3.1 lava-test-shell (duration 00:03:10) [common]
11902 16:48:04.567162 end: 3 lava-test-retry (duration 00:03:10) [common]
11903 16:48:04.567277 start: 4 finalize (timeout 00:10:00) [common]
11904 16:48:04.567381 start: 4.1 power-off (timeout 00:00:30) [common]
11905 16:48:04.567536 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11906 16:48:04.644271 >> Command sent successfully.
11907 16:48:04.646580 Returned 0 in 0 seconds
11908 16:48:04.746954 end: 4.1 power-off (duration 00:00:00) [common]
11910 16:48:04.747466 start: 4.2 read-feedback (timeout 00:10:00) [common]
11911 16:48:04.747840 Listened to connection for namespace 'common' for up to 1s
11912 16:48:05.748766 Finalising connection for namespace 'common'
11913 16:48:05.748944 Disconnecting from shell: Finalise
11914 16:48:05.749032 / #
11915 16:48:05.849346 end: 4.2 read-feedback (duration 00:00:01) [common]
11916 16:48:05.849530 end: 4 finalize (duration 00:00:01) [common]
11917 16:48:05.849689 Cleaning after the job
11918 16:48:05.849789 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/ramdisk
11919 16:48:05.851855 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/kernel
11920 16:48:05.860723 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/dtb
11921 16:48:05.860949 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/nfsrootfs
11922 16:48:05.903442 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576288/tftp-deploy-iypy3_7a/modules
11923 16:48:05.908795 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576288
11924 16:48:06.172578 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576288
11925 16:48:06.172775 Job finished correctly