Boot log: mt8192-asurada-spherion-r0

    1 16:50:08.817083  lava-dispatcher, installed at version: 2023.03
    2 16:50:08.817297  start: 0 validate
    3 16:50:08.817431  Start time: 2023-06-03 16:50:08.817424+00:00 (UTC)
    4 16:50:08.817570  Using caching service: 'http://localhost/cache/?uri=%s'
    5 16:50:08.817703  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
    6 16:50:09.111663  Using caching service: 'http://localhost/cache/?uri=%s'
    7 16:50:09.111863  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 16:50:09.397115  Using caching service: 'http://localhost/cache/?uri=%s'
    9 16:50:09.397306  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 16:50:09.682633  Using caching service: 'http://localhost/cache/?uri=%s'
   11 16:50:09.682813  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 16:50:09.972078  validate duration: 1.15
   14 16:50:09.972339  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 16:50:09.972438  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 16:50:09.972526  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 16:50:09.972654  Not decompressing ramdisk as can be used compressed.
   18 16:50:09.972742  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/rootfs.cpio.gz
   19 16:50:09.972806  saving as /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/ramdisk/rootfs.cpio.gz
   20 16:50:09.972868  total size: 84903995 (80MB)
   21 16:50:09.974444  progress   0% (0MB)
   22 16:50:09.995288  progress   5% (4MB)
   23 16:50:10.016746  progress  10% (8MB)
   24 16:50:10.037926  progress  15% (12MB)
   25 16:50:10.059212  progress  20% (16MB)
   26 16:50:10.080192  progress  25% (20MB)
   27 16:50:10.101233  progress  30% (24MB)
   28 16:50:10.122224  progress  35% (28MB)
   29 16:50:10.143346  progress  40% (32MB)
   30 16:50:10.165330  progress  45% (36MB)
   31 16:50:10.187130  progress  50% (40MB)
   32 16:50:10.208112  progress  55% (44MB)
   33 16:50:10.229318  progress  60% (48MB)
   34 16:50:10.250682  progress  65% (52MB)
   35 16:50:10.271901  progress  70% (56MB)
   36 16:50:10.293597  progress  75% (60MB)
   37 16:50:10.315409  progress  80% (64MB)
   38 16:50:10.337147  progress  85% (68MB)
   39 16:50:10.358377  progress  90% (72MB)
   40 16:50:10.379967  progress  95% (76MB)
   41 16:50:10.400933  progress 100% (80MB)
   42 16:50:10.401101  80MB downloaded in 0.43s (189.08MB/s)
   43 16:50:10.401270  end: 1.1.1 http-download (duration 00:00:00) [common]
   45 16:50:10.401584  end: 1.1 download-retry (duration 00:00:00) [common]
   46 16:50:10.401670  start: 1.2 download-retry (timeout 00:10:00) [common]
   47 16:50:10.401754  start: 1.2.1 http-download (timeout 00:10:00) [common]
   48 16:50:10.401871  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 16:50:10.401957  saving as /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/kernel/Image
   50 16:50:10.402020  total size: 45746688 (43MB)
   51 16:50:10.402082  No compression specified
   52 16:50:10.403231  progress   0% (0MB)
   53 16:50:10.414737  progress   5% (2MB)
   54 16:50:10.426304  progress  10% (4MB)
   55 16:50:10.437930  progress  15% (6MB)
   56 16:50:10.449539  progress  20% (8MB)
   57 16:50:10.461254  progress  25% (10MB)
   58 16:50:10.472678  progress  30% (13MB)
   59 16:50:10.484356  progress  35% (15MB)
   60 16:50:10.496014  progress  40% (17MB)
   61 16:50:10.508669  progress  45% (19MB)
   62 16:50:10.520591  progress  50% (21MB)
   63 16:50:10.532079  progress  55% (24MB)
   64 16:50:10.543619  progress  60% (26MB)
   65 16:50:10.555180  progress  65% (28MB)
   66 16:50:10.566657  progress  70% (30MB)
   67 16:50:10.578170  progress  75% (32MB)
   68 16:50:10.589651  progress  80% (34MB)
   69 16:50:10.601223  progress  85% (37MB)
   70 16:50:10.612953  progress  90% (39MB)
   71 16:50:10.624453  progress  95% (41MB)
   72 16:50:10.635899  progress 100% (43MB)
   73 16:50:10.636075  43MB downloaded in 0.23s (186.40MB/s)
   74 16:50:10.636239  end: 1.2.1 http-download (duration 00:00:00) [common]
   76 16:50:10.636468  end: 1.2 download-retry (duration 00:00:00) [common]
   77 16:50:10.636554  start: 1.3 download-retry (timeout 00:09:59) [common]
   78 16:50:10.636640  start: 1.3.1 http-download (timeout 00:09:59) [common]
   79 16:50:10.636764  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 16:50:10.636838  saving as /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/dtb/mt8192-asurada-spherion-r0.dtb
   81 16:50:10.636900  total size: 46924 (0MB)
   82 16:50:10.636960  No compression specified
   83 16:50:10.638067  progress  69% (0MB)
   84 16:50:10.638346  progress 100% (0MB)
   85 16:50:10.638541  0MB downloaded in 0.00s (27.32MB/s)
   86 16:50:10.638666  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 16:50:10.638918  end: 1.3 download-retry (duration 00:00:00) [common]
   89 16:50:10.639005  start: 1.4 download-retry (timeout 00:09:59) [common]
   90 16:50:10.639089  start: 1.4.1 http-download (timeout 00:09:59) [common]
   91 16:50:10.639200  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 16:50:10.639269  saving as /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/modules/modules.tar
   93 16:50:10.639331  total size: 8545664 (8MB)
   94 16:50:10.639391  Using unxz to decompress xz
   95 16:50:10.643277  progress   0% (0MB)
   96 16:50:10.664769  progress   5% (0MB)
   97 16:50:10.689547  progress  10% (0MB)
   98 16:50:10.716057  progress  15% (1MB)
   99 16:50:10.741309  progress  20% (1MB)
  100 16:50:10.767719  progress  25% (2MB)
  101 16:50:10.792844  progress  30% (2MB)
  102 16:50:10.818667  progress  35% (2MB)
  103 16:50:10.843713  progress  40% (3MB)
  104 16:50:10.869167  progress  45% (3MB)
  105 16:50:10.893278  progress  50% (4MB)
  106 16:50:10.917066  progress  55% (4MB)
  107 16:50:10.942110  progress  60% (4MB)
  108 16:50:10.967271  progress  65% (5MB)
  109 16:50:10.992292  progress  70% (5MB)
  110 16:50:11.019697  progress  75% (6MB)
  111 16:50:11.049413  progress  80% (6MB)
  112 16:50:11.071683  progress  85% (6MB)
  113 16:50:11.096521  progress  90% (7MB)
  114 16:50:11.120920  progress  95% (7MB)
  115 16:50:11.145230  progress 100% (8MB)
  116 16:50:11.151224  8MB downloaded in 0.51s (15.92MB/s)
  117 16:50:11.151522  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 16:50:11.151783  end: 1.4 download-retry (duration 00:00:01) [common]
  120 16:50:11.151876  start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
  121 16:50:11.151973  start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
  122 16:50:11.152059  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 16:50:11.152148  start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
  124 16:50:11.152356  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt
  125 16:50:11.152485  makedir: /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin
  126 16:50:11.152608  makedir: /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/tests
  127 16:50:11.152705  makedir: /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/results
  128 16:50:11.152816  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-add-keys
  129 16:50:11.152961  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-add-sources
  130 16:50:11.153087  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-background-process-start
  131 16:50:11.153213  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-background-process-stop
  132 16:50:11.153337  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-common-functions
  133 16:50:11.153458  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-echo-ipv4
  134 16:50:11.153581  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-install-packages
  135 16:50:11.153702  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-installed-packages
  136 16:50:11.153822  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-os-build
  137 16:50:11.153943  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-probe-channel
  138 16:50:11.154062  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-probe-ip
  139 16:50:11.154182  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-target-ip
  140 16:50:11.154303  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-target-mac
  141 16:50:11.154471  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-target-storage
  142 16:50:11.154614  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-test-case
  143 16:50:11.154738  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-test-event
  144 16:50:11.154857  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-test-feedback
  145 16:50:11.154978  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-test-raise
  146 16:50:11.155099  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-test-reference
  147 16:50:11.155222  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-test-runner
  148 16:50:11.155342  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-test-set
  149 16:50:11.155462  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-test-shell
  150 16:50:11.155585  Updating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-install-packages (oe)
  151 16:50:11.155736  Updating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/bin/lava-installed-packages (oe)
  152 16:50:11.155854  Creating /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/environment
  153 16:50:11.155951  LAVA metadata
  154 16:50:11.156025  - LAVA_JOB_ID=10576309
  155 16:50:11.156093  - LAVA_DISPATCHER_IP=192.168.201.1
  156 16:50:11.156197  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
  157 16:50:11.156266  skipped lava-vland-overlay
  158 16:50:11.156343  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 16:50:11.156422  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
  160 16:50:11.156485  skipped lava-multinode-overlay
  161 16:50:11.156584  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 16:50:11.156713  start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
  163 16:50:11.156790  Loading test definitions
  164 16:50:11.156886  start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
  165 16:50:11.156961  Using /lava-10576309 at stage 0
  166 16:50:11.157057  Fetching tests from https://github.com/kernelci/kernelci-core
  167 16:50:11.157141  Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/0/tests/0_sleep'
  168 16:50:11.841836  Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/0/tests/0_sleep
  169 16:50:11.843118  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/0/tests/0_sleep/config/lava/sleep/sleep.yaml
  170 16:50:11.843510  uuid=10576309_1.5.2.3.1 testdef=None
  171 16:50:11.843658  end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
  173 16:50:11.843906  start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
  174 16:50:11.844470  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  176 16:50:11.844705  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
  177 16:50:11.845397  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  179 16:50:11.845634  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
  180 16:50:11.846511  runner path: /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/0/tests/0_sleep test_uuid 10576309_1.5.2.3.1
  181 16:50:11.846598  sleep_params='mem freeze'
  182 16:50:11.846736  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  184 16:50:11.846950  Creating lava-test-runner.conf files
  185 16:50:11.847016  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576309/lava-overlay-7gnrmhgt/lava-10576309/0 for stage 0
  186 16:50:11.847110  - 0_sleep
  187 16:50:11.847212  end: 1.5.2.3 test-definition (duration 00:00:01) [common]
  188 16:50:11.847299  start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
  189 16:50:11.966003  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  190 16:50:11.966161  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
  191 16:50:11.966253  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  192 16:50:11.966355  end: 1.5.2 lava-overlay (duration 00:00:01) [common]
  193 16:50:11.966444  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
  194 16:50:14.265765  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
  195 16:50:14.266115  start: 1.5.4 extract-modules (timeout 00:09:56) [common]
  196 16:50:14.266228  extracting modules file /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576309/extract-overlay-ramdisk-hr_tyykq/ramdisk
  197 16:50:14.469048  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  198 16:50:14.469208  start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
  199 16:50:14.469310  [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576309/compress-overlay-rmbublba/overlay-1.5.2.4.tar.gz to ramdisk
  200 16:50:14.469420  [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576309/compress-overlay-rmbublba/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576309/extract-overlay-ramdisk-hr_tyykq/ramdisk
  201 16:50:14.556087  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  202 16:50:14.556238  start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
  203 16:50:14.556334  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  204 16:50:14.556425  start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
  205 16:50:14.556512  Building ramdisk /var/lib/lava/dispatcher/tmp/10576309/extract-overlay-ramdisk-hr_tyykq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576309/extract-overlay-ramdisk-hr_tyykq/ramdisk
  206 16:50:15.901090  >> 561588 blocks

  207 16:50:25.529912  rename /var/lib/lava/dispatcher/tmp/10576309/extract-overlay-ramdisk-hr_tyykq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/ramdisk/ramdisk.cpio.gz
  208 16:50:25.530334  end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
  209 16:50:25.530510  start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
  210 16:50:25.530613  start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
  211 16:50:25.530729  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/kernel/Image'
  212 16:50:37.574330  Returned 0 in 12 seconds
  213 16:50:37.674953  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/kernel/image.itb
  214 16:50:38.977076  output: FIT description: Kernel Image image with one or more FDT blobs
  215 16:50:38.977453  output: Created:         Sat Jun  3 17:50:38 2023
  216 16:50:38.977573  output:  Image 0 (kernel-1)
  217 16:50:38.977677  output:   Description:  
  218 16:50:38.977773  output:   Created:      Sat Jun  3 17:50:38 2023
  219 16:50:38.977880  output:   Type:         Kernel Image
  220 16:50:38.977971  output:   Compression:  lzma compressed
  221 16:50:38.978077  output:   Data Size:    10083474 Bytes = 9847.14 KiB = 9.62 MiB
  222 16:50:38.978167  output:   Architecture: AArch64
  223 16:50:38.978270  output:   OS:           Linux
  224 16:50:38.978383  output:   Load Address: 0x00000000
  225 16:50:38.978465  output:   Entry Point:  0x00000000
  226 16:50:38.978528  output:   Hash algo:    crc32
  227 16:50:38.978584  output:   Hash value:   b48eba69
  228 16:50:38.978639  output:  Image 1 (fdt-1)
  229 16:50:38.978700  output:   Description:  mt8192-asurada-spherion-r0
  230 16:50:38.978759  output:   Created:      Sat Jun  3 17:50:38 2023
  231 16:50:38.978812  output:   Type:         Flat Device Tree
  232 16:50:38.978866  output:   Compression:  uncompressed
  233 16:50:38.978928  output:   Data Size:    46924 Bytes = 45.82 KiB = 0.04 MiB
  234 16:50:38.978985  output:   Architecture: AArch64
  235 16:50:38.979039  output:   Hash algo:    crc32
  236 16:50:38.979092  output:   Hash value:   1df858fa
  237 16:50:38.979152  output:  Image 2 (ramdisk-1)
  238 16:50:38.979208  output:   Description:  unavailable
  239 16:50:38.979261  output:   Created:      Sat Jun  3 17:50:38 2023
  240 16:50:38.979315  output:   Type:         RAMDisk Image
  241 16:50:38.979373  output:   Compression:  Unknown Compression
  242 16:50:38.979430  output:   Data Size:    98158195 Bytes = 95857.61 KiB = 93.61 MiB
  243 16:50:38.979484  output:   Architecture: AArch64
  244 16:50:38.979537  output:   OS:           Linux
  245 16:50:38.979590  output:   Load Address: unavailable
  246 16:50:38.979649  output:   Entry Point:  unavailable
  247 16:50:38.979706  output:   Hash algo:    crc32
  248 16:50:38.979759  output:   Hash value:   40b818b9
  249 16:50:38.979812  output:  Default Configuration: 'conf-1'
  250 16:50:38.979870  output:  Configuration 0 (conf-1)
  251 16:50:38.979927  output:   Description:  mt8192-asurada-spherion-r0
  252 16:50:38.979981  output:   Kernel:       kernel-1
  253 16:50:38.980034  output:   Init Ramdisk: ramdisk-1
  254 16:50:38.980087  output:   FDT:          fdt-1
  255 16:50:38.980151  output:   Loadables:    kernel-1
  256 16:50:38.980207  output: 
  257 16:50:38.980402  end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
  258 16:50:38.980499  end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
  259 16:50:38.980605  end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
  260 16:50:38.980702  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
  261 16:50:38.980783  No LXC device requested
  262 16:50:38.980871  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  263 16:50:38.980958  start: 1.7 deploy-device-env (timeout 00:09:31) [common]
  264 16:50:38.981038  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  265 16:50:38.981114  Checking files for TFTP limit of 4294967296 bytes.
  266 16:50:38.981750  end: 1 tftp-deploy (duration 00:00:29) [common]
  267 16:50:38.981877  start: 2 depthcharge-action (timeout 00:05:00) [common]
  268 16:50:38.981981  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  269 16:50:38.982106  substitutions:
  270 16:50:38.982187  - {DTB}: 10576309/tftp-deploy-3kot0kcr/dtb/mt8192-asurada-spherion-r0.dtb
  271 16:50:38.982254  - {INITRD}: 10576309/tftp-deploy-3kot0kcr/ramdisk/ramdisk.cpio.gz
  272 16:50:38.982317  - {KERNEL}: 10576309/tftp-deploy-3kot0kcr/kernel/Image
  273 16:50:38.982426  - {LAVA_MAC}: None
  274 16:50:38.982486  - {PRESEED_CONFIG}: None
  275 16:50:38.982542  - {PRESEED_LOCAL}: None
  276 16:50:38.982598  - {RAMDISK}: 10576309/tftp-deploy-3kot0kcr/ramdisk/ramdisk.cpio.gz
  277 16:50:38.982657  - {ROOT_PART}: None
  278 16:50:38.982718  - {ROOT}: None
  279 16:50:38.982773  - {SERVER_IP}: 192.168.201.1
  280 16:50:38.982827  - {TEE}: None
  281 16:50:38.982880  Parsed boot commands:
  282 16:50:38.982936  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  283 16:50:38.983116  Parsed boot commands: tftpboot 192.168.201.1 10576309/tftp-deploy-3kot0kcr/kernel/image.itb 10576309/tftp-deploy-3kot0kcr/kernel/cmdline 
  284 16:50:38.983219  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  285 16:50:38.983311  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  286 16:50:38.983401  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  287 16:50:38.983501  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  288 16:50:38.983577  Not connected, no need to disconnect.
  289 16:50:38.983651  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  290 16:50:38.983735  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  291 16:50:38.983811  [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
  292 16:50:38.987207  Setting prompt string to ['lava-test: # ']
  293 16:50:38.987549  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  294 16:50:38.987655  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  295 16:50:38.987763  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  296 16:50:38.987854  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  297 16:50:38.988064  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
  298 16:50:44.121807  >> Command sent successfully.

  299 16:50:44.124227  Returned 0 in 5 seconds
  300 16:50:44.224618  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  302 16:50:44.224943  end: 2.2.2 reset-device (duration 00:00:05) [common]
  303 16:50:44.225043  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  304 16:50:44.225136  Setting prompt string to 'Starting depthcharge on Spherion...'
  305 16:50:44.225206  Changing prompt to 'Starting depthcharge on Spherion...'
  306 16:50:44.225275  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  307 16:50:44.225541  [Enter `^Ec?' for help]

  308 16:50:44.399455  

  309 16:50:44.399595  

  310 16:50:44.399694  F0: 102B 0000

  311 16:50:44.399777  

  312 16:50:44.399860  F3: 1001 0000 [0200]

  313 16:50:44.402809  

  314 16:50:44.402900  F3: 1001 0000

  315 16:50:44.402980  

  316 16:50:44.403066  F7: 102D 0000

  317 16:50:44.403136  

  318 16:50:44.406119  F1: 0000 0000

  319 16:50:44.406202  

  320 16:50:44.406268  V0: 0000 0000 [0001]

  321 16:50:44.406331  

  322 16:50:44.409258  00: 0007 8000

  323 16:50:44.409346  

  324 16:50:44.409412  01: 0000 0000

  325 16:50:44.409474  

  326 16:50:44.412722  BP: 0C00 0209 [0000]

  327 16:50:44.412806  

  328 16:50:44.412874  G0: 1182 0000

  329 16:50:44.412935  

  330 16:50:44.416521  EC: 0000 0021 [4000]

  331 16:50:44.416611  

  332 16:50:44.416678  S7: 0000 0000 [0000]

  333 16:50:44.416740  

  334 16:50:44.419780  CC: 0000 0000 [0001]

  335 16:50:44.419876  

  336 16:50:44.419944  T0: 0000 0040 [010F]

  337 16:50:44.420007  

  338 16:50:44.420067  Jump to BL

  339 16:50:44.420125  

  340 16:50:44.446639  

  341 16:50:44.446731  

  342 16:50:44.446798  

  343 16:50:44.453568  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  344 16:50:44.456824  ARM64: Exception handlers installed.

  345 16:50:44.459569  ARM64: Testing exception

  346 16:50:44.463118  ARM64: Done test exception

  347 16:50:44.469963  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  348 16:50:44.479590  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  349 16:50:44.486658  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  350 16:50:44.497044  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  351 16:50:44.503638  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  352 16:50:44.514510  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  353 16:50:44.524646  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  354 16:50:44.531325  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  355 16:50:44.549026  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  356 16:50:44.552504  WDT: Last reset was cold boot

  357 16:50:44.555837  SPI1(PAD0) initialized at 2873684 Hz

  358 16:50:44.559333  SPI5(PAD0) initialized at 992727 Hz

  359 16:50:44.562555  VBOOT: Loading verstage.

  360 16:50:44.569197  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  361 16:50:44.572245  FMAP: Found "FLASH" version 1.1 at 0x20000.

  362 16:50:44.575859  FMAP: base = 0x0 size = 0x800000 #areas = 25

  363 16:50:44.578986  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  364 16:50:44.586776  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  365 16:50:44.593219  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  366 16:50:44.604420  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  367 16:50:44.604533  

  368 16:50:44.604630  

  369 16:50:44.614073  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  370 16:50:44.617523  ARM64: Exception handlers installed.

  371 16:50:44.620737  ARM64: Testing exception

  372 16:50:44.620845  ARM64: Done test exception

  373 16:50:44.627051  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  374 16:50:44.630243  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  375 16:50:44.645249  Probing TPM: . done!

  376 16:50:44.645368  TPM ready after 0 ms

  377 16:50:44.651772  Connected to device vid:did:rid of 1ae0:0028:00

  378 16:50:44.659111  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

  379 16:50:44.662275  Initialized TPM device CR50 revision 0

  380 16:50:44.728148  tlcl_send_startup: Startup return code is 0

  381 16:50:44.728255  TPM: setup succeeded

  382 16:50:44.739300  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  383 16:50:44.748245  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  384 16:50:44.758290  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  385 16:50:44.767497  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  386 16:50:44.771216  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  387 16:50:44.778262  in-header: 03 07 00 00 08 00 00 00 

  388 16:50:44.782101  in-data: aa e4 47 04 13 02 00 00 

  389 16:50:44.785714  Chrome EC: UHEPI supported

  390 16:50:44.792919  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  391 16:50:44.796602  in-header: 03 ad 00 00 08 00 00 00 

  392 16:50:44.800391  in-data: 00 20 20 08 00 00 00 00 

  393 16:50:44.800476  Phase 1

  394 16:50:44.803904  FMAP: area GBB found @ 3f5000 (12032 bytes)

  395 16:50:44.811720  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  396 16:50:44.815450  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  397 16:50:44.818763  Recovery requested (1009000e)

  398 16:50:44.828604  TPM: Extending digest for VBOOT: boot mode into PCR 0

  399 16:50:44.834679  tlcl_extend: response is 0

  400 16:50:44.844956  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  401 16:50:44.850602  tlcl_extend: response is 0

  402 16:50:44.857865  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  403 16:50:44.878059  read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps

  404 16:50:44.884556  BS: bootblock times (exec / console): total (unknown) / 148 ms

  405 16:50:44.884672  

  406 16:50:44.884768  

  407 16:50:44.894645  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  408 16:50:44.898074  ARM64: Exception handlers installed.

  409 16:50:44.901591  ARM64: Testing exception

  410 16:50:44.901682  ARM64: Done test exception

  411 16:50:44.923593  pmic_efuse_setting: Set efuses in 11 msecs

  412 16:50:44.926688  pmwrap_interface_init: Select PMIF_VLD_RDY

  413 16:50:44.933883  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  414 16:50:44.936721  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  415 16:50:44.943780  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  416 16:50:44.946830  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  417 16:50:44.950500  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  418 16:50:44.958123  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  419 16:50:44.960770  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  420 16:50:44.967896  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  421 16:50:44.971583  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  422 16:50:44.975752  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  423 16:50:44.979338  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  424 16:50:44.985977  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  425 16:50:44.988850  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  426 16:50:44.995725  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  427 16:50:45.002674  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  428 16:50:45.006258  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  429 16:50:45.013504  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  430 16:50:45.016914  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  431 16:50:45.024275  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  432 16:50:45.030668  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  433 16:50:45.034576  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  434 16:50:45.041359  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  435 16:50:45.044612  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  436 16:50:45.051339  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  437 16:50:45.057926  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  438 16:50:45.064476  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  439 16:50:45.067562  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  440 16:50:45.071023  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  441 16:50:45.077779  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  442 16:50:45.080610  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  443 16:50:45.087367  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  444 16:50:45.090541  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  445 16:50:45.097508  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  446 16:50:45.100771  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  447 16:50:45.107126  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  448 16:50:45.110665  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  449 16:50:45.117075  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  450 16:50:45.120402  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  451 16:50:45.127347  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  452 16:50:45.131389  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  453 16:50:45.134714  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  454 16:50:45.138399  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  455 16:50:45.144653  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  456 16:50:45.148397  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  457 16:50:45.151700  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  458 16:50:45.157978  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  459 16:50:45.161493  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  460 16:50:45.164989  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  461 16:50:45.171518  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  462 16:50:45.174924  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  463 16:50:45.178343  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  464 16:50:45.184838  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  465 16:50:45.194723  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  466 16:50:45.198076  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  467 16:50:45.207947  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  468 16:50:45.214649  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  469 16:50:45.221202  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  470 16:50:45.224414  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  471 16:50:45.228055  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  472 16:50:45.235517  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xa

  473 16:50:45.242531  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  474 16:50:45.245754  [RTC]rtc_osc_init,62: osc32con val = 0xde70

  475 16:50:45.249133  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  476 16:50:45.260751  [RTC]rtc_get_frequency_meter,154: input=15, output=772

  477 16:50:45.269737  [RTC]rtc_get_frequency_meter,154: input=23, output=957

  478 16:50:45.279427  [RTC]rtc_get_frequency_meter,154: input=19, output=865

  479 16:50:45.288959  [RTC]rtc_get_frequency_meter,154: input=17, output=817

  480 16:50:45.298478  [RTC]rtc_get_frequency_meter,154: input=16, output=795

  481 16:50:45.302082  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70

  482 16:50:45.308475  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  483 16:50:45.311760  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  484 16:50:45.314917  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  485 16:50:45.318293  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  486 16:50:45.321495  ADC[4]: Raw value=902139 ID=7

  487 16:50:45.325218  ADC[3]: Raw value=213179 ID=1

  488 16:50:45.328406  RAM Code: 0x71

  489 16:50:45.331742  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  490 16:50:45.334970  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  491 16:50:45.345023  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  492 16:50:45.351582  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  493 16:50:45.354885  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  494 16:50:45.358032  in-header: 03 07 00 00 08 00 00 00 

  495 16:50:45.361330  in-data: aa e4 47 04 13 02 00 00 

  496 16:50:45.364536  Chrome EC: UHEPI supported

  497 16:50:45.371507  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  498 16:50:45.374713  in-header: 03 ed 00 00 08 00 00 00 

  499 16:50:45.378095  in-data: 80 20 60 08 00 00 00 00 

  500 16:50:45.381558  MRC: failed to locate region type 0.

  501 16:50:45.387960  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  502 16:50:45.391232  DRAM-K: Running full calibration

  503 16:50:45.394869  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  504 16:50:45.398157  header.status = 0x0

  505 16:50:45.401193  header.version = 0x6 (expected: 0x6)

  506 16:50:45.404673  header.size = 0xd00 (expected: 0xd00)

  507 16:50:45.408171  header.flags = 0x0

  508 16:50:45.411409  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  509 16:50:45.430082  read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps

  510 16:50:45.436854  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  511 16:50:45.440064  dram_init: ddr_geometry: 2

  512 16:50:45.443388  [EMI] MDL number = 2

  513 16:50:45.443474  [EMI] Get MDL freq = 0

  514 16:50:45.446716  dram_init: ddr_type: 0

  515 16:50:45.446802  is_discrete_lpddr4: 1

  516 16:50:45.450304  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  517 16:50:45.450400  

  518 16:50:45.450487  

  519 16:50:45.453402  [Bian_co] ETT version 0.0.0.1

  520 16:50:45.459950   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  521 16:50:45.460038  

  522 16:50:45.463571  dramc_set_vcore_voltage set vcore to 650000

  523 16:50:45.463657  Read voltage for 800, 4

  524 16:50:45.466868  Vio18 = 0

  525 16:50:45.466955  Vcore = 650000

  526 16:50:45.467046  Vdram = 0

  527 16:50:45.470090  Vddq = 0

  528 16:50:45.470176  Vmddr = 0

  529 16:50:45.473673  dram_init: config_dvfs: 1

  530 16:50:45.476907  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  531 16:50:45.483677  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  532 16:50:45.486816  [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9

  533 16:50:45.489973  freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9

  534 16:50:45.493450  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  535 16:50:45.496766  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  536 16:50:45.500812  MEM_TYPE=3, freq_sel=18

  537 16:50:45.503921  sv_algorithm_assistance_LP4_1600 

  538 16:50:45.507836  ============ PULL DRAM RESETB DOWN ============

  539 16:50:45.511462  ========== PULL DRAM RESETB DOWN end =========

  540 16:50:45.515131  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  541 16:50:45.518869  =================================== 

  542 16:50:45.522641  LPDDR4 DRAM CONFIGURATION

  543 16:50:45.526034  =================================== 

  544 16:50:45.526128  EX_ROW_EN[0]    = 0x0

  545 16:50:45.529679  EX_ROW_EN[1]    = 0x0

  546 16:50:45.529768  LP4Y_EN      = 0x0

  547 16:50:45.533863  WORK_FSP     = 0x0

  548 16:50:45.533966  WL           = 0x2

  549 16:50:45.537355  RL           = 0x2

  550 16:50:45.537440  BL           = 0x2

  551 16:50:45.540990  RPST         = 0x0

  552 16:50:45.541092  RD_PRE       = 0x0

  553 16:50:45.544725  WR_PRE       = 0x1

  554 16:50:45.544826  WR_PST       = 0x0

  555 16:50:45.548036  DBI_WR       = 0x0

  556 16:50:45.548135  DBI_RD       = 0x0

  557 16:50:45.551811  OTF          = 0x1

  558 16:50:45.551884  =================================== 

  559 16:50:45.555647  =================================== 

  560 16:50:45.559280  ANA top config

  561 16:50:45.562561  =================================== 

  562 16:50:45.562671  DLL_ASYNC_EN            =  0

  563 16:50:45.566184  ALL_SLAVE_EN            =  1

  564 16:50:45.569345  NEW_RANK_MODE           =  1

  565 16:50:45.572608  DLL_IDLE_MODE           =  1

  566 16:50:45.572724  LP45_APHY_COMB_EN       =  1

  567 16:50:45.575958  TX_ODT_DIS              =  1

  568 16:50:45.579451  NEW_8X_MODE             =  1

  569 16:50:45.582630  =================================== 

  570 16:50:45.585830  =================================== 

  571 16:50:45.589022  data_rate                  = 1600

  572 16:50:45.592558  CKR                        = 1

  573 16:50:45.596003  DQ_P2S_RATIO               = 8

  574 16:50:45.599593  =================================== 

  575 16:50:45.599679  CA_P2S_RATIO               = 8

  576 16:50:45.602474  DQ_CA_OPEN                 = 0

  577 16:50:45.606218  DQ_SEMI_OPEN               = 0

  578 16:50:45.609242  CA_SEMI_OPEN               = 0

  579 16:50:45.612659  CA_FULL_RATE               = 0

  580 16:50:45.612744  DQ_CKDIV4_EN               = 1

  581 16:50:45.616358  CA_CKDIV4_EN               = 1

  582 16:50:45.619890  CA_PREDIV_EN               = 0

  583 16:50:45.623202  PH8_DLY                    = 0

  584 16:50:45.626877  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  585 16:50:45.626958  DQ_AAMCK_DIV               = 4

  586 16:50:45.630330  CA_AAMCK_DIV               = 4

  587 16:50:45.634074  CA_ADMCK_DIV               = 4

  588 16:50:45.637549  DQ_TRACK_CA_EN             = 0

  589 16:50:45.637631  CA_PICK                    = 800

  590 16:50:45.641472  CA_MCKIO                   = 800

  591 16:50:45.644515  MCKIO_SEMI                 = 0

  592 16:50:45.648589  PLL_FREQ                   = 3068

  593 16:50:45.651612  DQ_UI_PI_RATIO             = 32

  594 16:50:45.654887  CA_UI_PI_RATIO             = 0

  595 16:50:45.658020  =================================== 

  596 16:50:45.661598  =================================== 

  597 16:50:45.661682  memory_type:LPDDR4         

  598 16:50:45.664702  GP_NUM     : 10       

  599 16:50:45.668024  SRAM_EN    : 1       

  600 16:50:45.668109  MD32_EN    : 0       

  601 16:50:45.671813  =================================== 

  602 16:50:45.675483  [ANA_INIT] >>>>>>>>>>>>>> 

  603 16:50:45.675569  <<<<<< [CONFIGURE PHASE]: ANA_TX

  604 16:50:45.679093  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  605 16:50:45.682905  =================================== 

  606 16:50:45.686214  data_rate = 1600,PCW = 0X7600

  607 16:50:45.689811  =================================== 

  608 16:50:45.693567  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  609 16:50:45.700703  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  610 16:50:45.704654  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  611 16:50:45.708076  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  612 16:50:45.711404  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  613 16:50:45.714563  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  614 16:50:45.717802  [ANA_INIT] flow start 

  615 16:50:45.721582  [ANA_INIT] PLL >>>>>>>> 

  616 16:50:45.721666  [ANA_INIT] PLL <<<<<<<< 

  617 16:50:45.724603  [ANA_INIT] MIDPI >>>>>>>> 

  618 16:50:45.727714  [ANA_INIT] MIDPI <<<<<<<< 

  619 16:50:45.727799  [ANA_INIT] DLL >>>>>>>> 

  620 16:50:45.730999  [ANA_INIT] flow end 

  621 16:50:45.734420  ============ LP4 DIFF to SE enter ============

  622 16:50:45.738109  ============ LP4 DIFF to SE exit  ============

  623 16:50:45.741351  [ANA_INIT] <<<<<<<<<<<<< 

  624 16:50:45.744383  [Flow] Enable top DCM control >>>>> 

  625 16:50:45.747757  [Flow] Enable top DCM control <<<<< 

  626 16:50:45.751362  Enable DLL master slave shuffle 

  627 16:50:45.758148  ============================================================== 

  628 16:50:45.758234  Gating Mode config

  629 16:50:45.764728  ============================================================== 

  630 16:50:45.764813  Config description: 

  631 16:50:45.774769  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  632 16:50:45.781181  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  633 16:50:45.787964  SELPH_MODE            0: By rank         1: By Phase 

  634 16:50:45.791095  ============================================================== 

  635 16:50:45.794329  GAT_TRACK_EN                 =  1

  636 16:50:45.797964  RX_GATING_MODE               =  2

  637 16:50:45.801189  RX_GATING_TRACK_MODE         =  2

  638 16:50:45.804407  SELPH_MODE                   =  1

  639 16:50:45.807905  PICG_EARLY_EN                =  1

  640 16:50:45.811383  VALID_LAT_VALUE              =  1

  641 16:50:45.817423  ============================================================== 

  642 16:50:45.820653  Enter into Gating configuration >>>> 

  643 16:50:45.824758  Exit from Gating configuration <<<< 

  644 16:50:45.827346  Enter into  DVFS_PRE_config >>>>> 

  645 16:50:45.837296  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  646 16:50:45.840794  Exit from  DVFS_PRE_config <<<<< 

  647 16:50:45.844165  Enter into PICG configuration >>>> 

  648 16:50:45.847664  Exit from PICG configuration <<<< 

  649 16:50:45.850704  [RX_INPUT] configuration >>>>> 

  650 16:50:45.850788  [RX_INPUT] configuration <<<<< 

  651 16:50:45.857705  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  652 16:50:45.864251  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  653 16:50:45.867435  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  654 16:50:45.874085  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  655 16:50:45.880963  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  656 16:50:45.887490  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  657 16:50:45.890940  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  658 16:50:45.894232  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  659 16:50:45.901231  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  660 16:50:45.905113  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  661 16:50:45.908357  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  662 16:50:45.911669  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  663 16:50:45.914772  =================================== 

  664 16:50:45.918086  LPDDR4 DRAM CONFIGURATION

  665 16:50:45.921755  =================================== 

  666 16:50:45.924704  EX_ROW_EN[0]    = 0x0

  667 16:50:45.924792  EX_ROW_EN[1]    = 0x0

  668 16:50:45.928427  LP4Y_EN      = 0x0

  669 16:50:45.928517  WORK_FSP     = 0x0

  670 16:50:45.931339  WL           = 0x2

  671 16:50:45.931453  RL           = 0x2

  672 16:50:45.934675  BL           = 0x2

  673 16:50:45.934753  RPST         = 0x0

  674 16:50:45.938161  RD_PRE       = 0x0

  675 16:50:45.938242  WR_PRE       = 0x1

  676 16:50:45.941302  WR_PST       = 0x0

  677 16:50:45.941382  DBI_WR       = 0x0

  678 16:50:45.944599  DBI_RD       = 0x0

  679 16:50:45.944675  OTF          = 0x1

  680 16:50:45.948305  =================================== 

  681 16:50:45.951454  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  682 16:50:45.957739  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  683 16:50:45.961529  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  684 16:50:45.964679  =================================== 

  685 16:50:45.967981  LPDDR4 DRAM CONFIGURATION

  686 16:50:45.971541  =================================== 

  687 16:50:45.971620  EX_ROW_EN[0]    = 0x10

  688 16:50:45.974696  EX_ROW_EN[1]    = 0x0

  689 16:50:45.977911  LP4Y_EN      = 0x0

  690 16:50:45.977995  WORK_FSP     = 0x0

  691 16:50:45.981215  WL           = 0x2

  692 16:50:45.981299  RL           = 0x2

  693 16:50:45.984858  BL           = 0x2

  694 16:50:45.984934  RPST         = 0x0

  695 16:50:45.988066  RD_PRE       = 0x0

  696 16:50:45.988145  WR_PRE       = 0x1

  697 16:50:45.991304  WR_PST       = 0x0

  698 16:50:45.991378  DBI_WR       = 0x0

  699 16:50:45.994599  DBI_RD       = 0x0

  700 16:50:45.994676  OTF          = 0x1

  701 16:50:45.998310  =================================== 

  702 16:50:46.004756  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  703 16:50:46.008873  nWR fixed to 40

  704 16:50:46.012145  [ModeRegInit_LP4] CH0 RK0

  705 16:50:46.012225  [ModeRegInit_LP4] CH0 RK1

  706 16:50:46.015374  [ModeRegInit_LP4] CH1 RK0

  707 16:50:46.018450  [ModeRegInit_LP4] CH1 RK1

  708 16:50:46.018524  match AC timing 13

  709 16:50:46.025089  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  710 16:50:46.028381  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  711 16:50:46.031707  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  712 16:50:46.038244  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  713 16:50:46.041669  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  714 16:50:46.044981  [EMI DOE] emi_dcm 0

  715 16:50:46.048357  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  716 16:50:46.048436  ==

  717 16:50:46.051960  Dram Type= 6, Freq= 0, CH_0, rank 0

  718 16:50:46.054934  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  719 16:50:46.055013  ==

  720 16:50:46.061733  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  721 16:50:46.068331  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  722 16:50:46.076392  [CA 0] Center 38 (7~69) winsize 63

  723 16:50:46.080101  [CA 1] Center 38 (7~69) winsize 63

  724 16:50:46.083228  [CA 2] Center 35 (5~66) winsize 62

  725 16:50:46.086777  [CA 3] Center 35 (5~66) winsize 62

  726 16:50:46.090059  [CA 4] Center 34 (4~65) winsize 62

  727 16:50:46.093703  [CA 5] Center 33 (3~64) winsize 62

  728 16:50:46.093807  

  729 16:50:46.097250  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  730 16:50:46.097336  

  731 16:50:46.100889  [CATrainingPosCal] consider 1 rank data

  732 16:50:46.104820  u2DelayCellTimex100 = 270/100 ps

  733 16:50:46.108407  CA0 delay=38 (7~69),Diff = 5 PI (36 cell)

  734 16:50:46.112159  CA1 delay=38 (7~69),Diff = 5 PI (36 cell)

  735 16:50:46.115377  CA2 delay=35 (5~66),Diff = 2 PI (14 cell)

  736 16:50:46.119080  CA3 delay=35 (5~66),Diff = 2 PI (14 cell)

  737 16:50:46.122608  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

  738 16:50:46.126319  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  739 16:50:46.126447  

  740 16:50:46.129878  CA PerBit enable=1, Macro0, CA PI delay=33

  741 16:50:46.129955  

  742 16:50:46.133396  [CBTSetCACLKResult] CA Dly = 33

  743 16:50:46.133481  CS Dly: 6 (0~37)

  744 16:50:46.133549  ==

  745 16:50:46.136992  Dram Type= 6, Freq= 0, CH_0, rank 1

  746 16:50:46.140552  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  747 16:50:46.140639  ==

  748 16:50:46.147741  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  749 16:50:46.154831  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  750 16:50:46.163047  [CA 0] Center 38 (7~69) winsize 63

  751 16:50:46.166804  [CA 1] Center 38 (8~69) winsize 62

  752 16:50:46.170560  [CA 2] Center 36 (6~67) winsize 62

  753 16:50:46.173917  [CA 3] Center 36 (5~67) winsize 63

  754 16:50:46.177399  [CA 4] Center 35 (4~66) winsize 63

  755 16:50:46.180947  [CA 5] Center 34 (4~65) winsize 62

  756 16:50:46.181033  

  757 16:50:46.184504  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  758 16:50:46.184650  

  759 16:50:46.188259  [CATrainingPosCal] consider 2 rank data

  760 16:50:46.191986  u2DelayCellTimex100 = 270/100 ps

  761 16:50:46.195798  CA0 delay=38 (7~69),Diff = 4 PI (28 cell)

  762 16:50:46.199582  CA1 delay=38 (8~69),Diff = 4 PI (28 cell)

  763 16:50:46.203167  CA2 delay=36 (6~66),Diff = 2 PI (14 cell)

  764 16:50:46.206903  CA3 delay=35 (5~66),Diff = 1 PI (7 cell)

  765 16:50:46.210647  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

  766 16:50:46.210732  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

  767 16:50:46.213886  

  768 16:50:46.217448  CA PerBit enable=1, Macro0, CA PI delay=34

  769 16:50:46.217534  

  770 16:50:46.217601  [CBTSetCACLKResult] CA Dly = 34

  771 16:50:46.221184  CS Dly: 6 (0~38)

  772 16:50:46.221268  

  773 16:50:46.225279  ----->DramcWriteLeveling(PI) begin...

  774 16:50:46.225366  ==

  775 16:50:46.229201  Dram Type= 6, Freq= 0, CH_0, rank 0

  776 16:50:46.232960  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  777 16:50:46.233047  ==

  778 16:50:46.236368  Write leveling (Byte 0): 32 => 32

  779 16:50:46.240032  Write leveling (Byte 1): 31 => 31

  780 16:50:46.240117  DramcWriteLeveling(PI) end<-----

  781 16:50:46.240185  

  782 16:50:46.243847  ==

  783 16:50:46.243932  Dram Type= 6, Freq= 0, CH_0, rank 0

  784 16:50:46.250640  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  785 16:50:46.250726  ==

  786 16:50:46.250795  [Gating] SW mode calibration

  787 16:50:46.257937  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  788 16:50:46.265291  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  789 16:50:46.269003   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  790 16:50:46.272689   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  791 16:50:46.276484   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  792 16:50:46.283721   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  793 16:50:46.287270   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  794 16:50:46.291065   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  795 16:50:46.294297   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  796 16:50:46.298408   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  797 16:50:46.305841   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  798 16:50:46.309865   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  799 16:50:46.313431   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 16:50:46.317088   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 16:50:46.320815   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 16:50:46.324441   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 16:50:46.332010   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  804 16:50:46.335859   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  805 16:50:46.339706   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  806 16:50:46.343392   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

  807 16:50:46.347202   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  808 16:50:46.354406   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  809 16:50:46.358373   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  810 16:50:46.361910   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  811 16:50:46.365943   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  812 16:50:46.369414   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  813 16:50:46.372756   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  814 16:50:46.380124   0  9  4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 1)

  815 16:50:46.384117   0  9  8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)

  816 16:50:46.387349   0  9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)

  817 16:50:46.390467   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  818 16:50:46.397470   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  819 16:50:46.400990   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  820 16:50:46.404014   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  821 16:50:46.410724   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

  822 16:50:46.414054   0 10  4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)

  823 16:50:46.417394   0 10  8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)

  824 16:50:46.424541   0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

  825 16:50:46.427529   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  826 16:50:46.430837   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  827 16:50:46.436974   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  828 16:50:46.440654   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  829 16:50:46.443923   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  830 16:50:46.450322   0 11  4 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)

  831 16:50:46.453608   0 11  8 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)

  832 16:50:46.456980   0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

  833 16:50:46.463945   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  834 16:50:46.467079   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  835 16:50:46.470793   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  836 16:50:46.473932   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  837 16:50:46.480389   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  838 16:50:46.483697   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  839 16:50:46.486857   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  840 16:50:46.493770   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  841 16:50:46.497185   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  842 16:50:46.500651   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  843 16:50:46.507679   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  844 16:50:46.511030   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  845 16:50:46.513967   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  846 16:50:46.520544   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  847 16:50:46.523974   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  848 16:50:46.527054   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  849 16:50:46.533488   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  850 16:50:46.536870   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  851 16:50:46.540480   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  852 16:50:46.546912   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  853 16:50:46.550160   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  854 16:50:46.553710   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  855 16:50:46.560061   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  856 16:50:46.560543  Total UI for P1: 0, mck2ui 16

  857 16:50:46.567215  best dqsien dly found for B0: ( 0, 14,  2)

  858 16:50:46.570427   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  859 16:50:46.573870  Total UI for P1: 0, mck2ui 16

  860 16:50:46.576643  best dqsien dly found for B1: ( 0, 14,  8)

  861 16:50:46.580099  best DQS0 dly(MCK, UI, PI) = (0, 14, 2)

  862 16:50:46.583452  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

  863 16:50:46.583928  

  864 16:50:46.586444  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)

  865 16:50:46.589762  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

  866 16:50:46.593558  [Gating] SW calibration Done

  867 16:50:46.594055  ==

  868 16:50:46.596607  Dram Type= 6, Freq= 0, CH_0, rank 0

  869 16:50:46.600121  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  870 16:50:46.600706  ==

  871 16:50:46.603183  RX Vref Scan: 0

  872 16:50:46.603658  

  873 16:50:46.606403  RX Vref 0 -> 0, step: 1

  874 16:50:46.606881  

  875 16:50:46.610521  RX Delay -130 -> 252, step: 16

  876 16:50:46.613843  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

  877 16:50:46.616467  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

  878 16:50:46.620129  iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224

  879 16:50:46.623083  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

  880 16:50:46.626838  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

  881 16:50:46.633462  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  882 16:50:46.636719  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

  883 16:50:46.640137  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

  884 16:50:46.643367  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

  885 16:50:46.649885  iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224

  886 16:50:46.653115  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

  887 16:50:46.656190  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

  888 16:50:46.659899  iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208

  889 16:50:46.663418  iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208

  890 16:50:46.670013  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

  891 16:50:46.673127  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

  892 16:50:46.673797  ==

  893 16:50:46.676151  Dram Type= 6, Freq= 0, CH_0, rank 0

  894 16:50:46.679347  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  895 16:50:46.679993  ==

  896 16:50:46.682852  DQS Delay:

  897 16:50:46.683471  DQS0 = 0, DQS1 = 0

  898 16:50:46.684067  DQM Delay:

  899 16:50:46.686188  DQM0 = 93, DQM1 = 81

  900 16:50:46.686711  DQ Delay:

  901 16:50:46.689452  DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93

  902 16:50:46.692788  DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101

  903 16:50:46.696608  DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77

  904 16:50:46.699537  DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93

  905 16:50:46.700040  

  906 16:50:46.700420  

  907 16:50:46.700769  ==

  908 16:50:46.703125  Dram Type= 6, Freq= 0, CH_0, rank 0

  909 16:50:46.709993  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  910 16:50:46.710617  ==

  911 16:50:46.711006  

  912 16:50:46.711359  

  913 16:50:46.711693  	TX Vref Scan disable

  914 16:50:46.713356   == TX Byte 0 ==

  915 16:50:46.716447  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

  916 16:50:46.723031  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

  917 16:50:46.723632   == TX Byte 1 ==

  918 16:50:46.726578  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  919 16:50:46.730036  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  920 16:50:46.733415  ==

  921 16:50:46.736777  Dram Type= 6, Freq= 0, CH_0, rank 0

  922 16:50:46.739868  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  923 16:50:46.740353  ==

  924 16:50:46.752102  TX Vref=22, minBit 11, minWin=26, winSum=437

  925 16:50:46.755370  TX Vref=24, minBit 6, minWin=27, winSum=443

  926 16:50:46.759159  TX Vref=26, minBit 8, minWin=27, winSum=453

  927 16:50:46.762299  TX Vref=28, minBit 8, minWin=27, winSum=453

  928 16:50:46.765502  TX Vref=30, minBit 5, minWin=28, winSum=457

  929 16:50:46.772793  TX Vref=32, minBit 3, minWin=28, winSum=457

  930 16:50:46.775703  [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30

  931 16:50:46.776224  

  932 16:50:46.778696  Final TX Range 1 Vref 30

  933 16:50:46.779178  

  934 16:50:46.779559  ==

  935 16:50:46.782296  Dram Type= 6, Freq= 0, CH_0, rank 0

  936 16:50:46.785484  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  937 16:50:46.785967  ==

  938 16:50:46.788532  

  939 16:50:46.789003  

  940 16:50:46.789572  	TX Vref Scan disable

  941 16:50:46.792096   == TX Byte 0 ==

  942 16:50:46.795293  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

  943 16:50:46.802428  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

  944 16:50:46.802905   == TX Byte 1 ==

  945 16:50:46.805647  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  946 16:50:46.812464  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  947 16:50:46.813104  

  948 16:50:46.813486  [DATLAT]

  949 16:50:46.813839  Freq=800, CH0 RK0

  950 16:50:46.814177  

  951 16:50:46.815082  DATLAT Default: 0xa

  952 16:50:46.815753  0, 0xFFFF, sum = 0

  953 16:50:46.818644  1, 0xFFFF, sum = 0

  954 16:50:46.819309  2, 0xFFFF, sum = 0

  955 16:50:46.822188  3, 0xFFFF, sum = 0

  956 16:50:46.825689  4, 0xFFFF, sum = 0

  957 16:50:46.826497  5, 0xFFFF, sum = 0

  958 16:50:46.828560  6, 0xFFFF, sum = 0

  959 16:50:46.829184  7, 0xFFFF, sum = 0

  960 16:50:46.831734  8, 0xFFFF, sum = 0

  961 16:50:46.832215  9, 0x0, sum = 1

  962 16:50:46.832599  10, 0x0, sum = 2

  963 16:50:46.835644  11, 0x0, sum = 3

  964 16:50:46.836232  12, 0x0, sum = 4

  965 16:50:46.838675  best_step = 10

  966 16:50:46.839150  

  967 16:50:46.839523  ==

  968 16:50:46.841886  Dram Type= 6, Freq= 0, CH_0, rank 0

  969 16:50:46.845107  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  970 16:50:46.845586  ==

  971 16:50:46.848309  RX Vref Scan: 1

  972 16:50:46.848780  

  973 16:50:46.851885  Set Vref Range= 32 -> 127

  974 16:50:46.852461  

  975 16:50:46.852843  RX Vref 32 -> 127, step: 1

  976 16:50:46.853196  

  977 16:50:46.855231  RX Delay -95 -> 252, step: 8

  978 16:50:46.855805  

  979 16:50:46.858759  Set Vref, RX VrefLevel [Byte0]: 32

  980 16:50:46.861944                           [Byte1]: 32

  981 16:50:46.862444  

  982 16:50:46.865338  Set Vref, RX VrefLevel [Byte0]: 33

  983 16:50:46.868362                           [Byte1]: 33

  984 16:50:46.872477  

  985 16:50:46.872951  Set Vref, RX VrefLevel [Byte0]: 34

  986 16:50:46.875543                           [Byte1]: 34

  987 16:50:46.880233  

  988 16:50:46.880974  Set Vref, RX VrefLevel [Byte0]: 35

  989 16:50:46.883441                           [Byte1]: 35

  990 16:50:46.887444  

  991 16:50:46.887874  Set Vref, RX VrefLevel [Byte0]: 36

  992 16:50:46.890713                           [Byte1]: 36

  993 16:50:46.895238  

  994 16:50:46.895707  Set Vref, RX VrefLevel [Byte0]: 37

  995 16:50:46.898680                           [Byte1]: 37

  996 16:50:46.903232  

  997 16:50:46.903918  Set Vref, RX VrefLevel [Byte0]: 38

  998 16:50:46.906456                           [Byte1]: 38

  999 16:50:46.910276  

 1000 16:50:46.910772  Set Vref, RX VrefLevel [Byte0]: 39

 1001 16:50:46.914045                           [Byte1]: 39

 1002 16:50:46.918524  

 1003 16:50:46.919000  Set Vref, RX VrefLevel [Byte0]: 40

 1004 16:50:46.921663                           [Byte1]: 40

 1005 16:50:46.925945  

 1006 16:50:46.926563  Set Vref, RX VrefLevel [Byte0]: 41

 1007 16:50:46.929010                           [Byte1]: 41

 1008 16:50:46.933256  

 1009 16:50:46.936444  Set Vref, RX VrefLevel [Byte0]: 42

 1010 16:50:46.937015                           [Byte1]: 42

 1011 16:50:46.941030  

 1012 16:50:46.941586  Set Vref, RX VrefLevel [Byte0]: 43

 1013 16:50:46.944299                           [Byte1]: 43

 1014 16:50:46.948681  

 1015 16:50:46.949107  Set Vref, RX VrefLevel [Byte0]: 44

 1016 16:50:46.951976                           [Byte1]: 44

 1017 16:50:46.956194  

 1018 16:50:46.956752  Set Vref, RX VrefLevel [Byte0]: 45

 1019 16:50:46.959299                           [Byte1]: 45

 1020 16:50:46.963620  

 1021 16:50:46.964150  Set Vref, RX VrefLevel [Byte0]: 46

 1022 16:50:46.967110                           [Byte1]: 46

 1023 16:50:46.971592  

 1024 16:50:46.972160  Set Vref, RX VrefLevel [Byte0]: 47

 1025 16:50:46.974936                           [Byte1]: 47

 1026 16:50:46.978842  

 1027 16:50:46.979304  Set Vref, RX VrefLevel [Byte0]: 48

 1028 16:50:46.982298                           [Byte1]: 48

 1029 16:50:46.986977  

 1030 16:50:46.987683  Set Vref, RX VrefLevel [Byte0]: 49

 1031 16:50:46.989576                           [Byte1]: 49

 1032 16:50:46.994155  

 1033 16:50:46.994768  Set Vref, RX VrefLevel [Byte0]: 50

 1034 16:50:46.997604                           [Byte1]: 50

 1035 16:50:47.002088  

 1036 16:50:47.002718  Set Vref, RX VrefLevel [Byte0]: 51

 1037 16:50:47.005581                           [Byte1]: 51

 1038 16:50:47.009259  

 1039 16:50:47.009784  Set Vref, RX VrefLevel [Byte0]: 52

 1040 16:50:47.012707                           [Byte1]: 52

 1041 16:50:47.016806  

 1042 16:50:47.017270  Set Vref, RX VrefLevel [Byte0]: 53

 1043 16:50:47.020068                           [Byte1]: 53

 1044 16:50:47.025136  

 1045 16:50:47.025810  Set Vref, RX VrefLevel [Byte0]: 54

 1046 16:50:47.028085                           [Byte1]: 54

 1047 16:50:47.032424  

 1048 16:50:47.032991  Set Vref, RX VrefLevel [Byte0]: 55

 1049 16:50:47.035300                           [Byte1]: 55

 1050 16:50:47.039954  

 1051 16:50:47.040537  Set Vref, RX VrefLevel [Byte0]: 56

 1052 16:50:47.043196                           [Byte1]: 56

 1053 16:50:47.047211  

 1054 16:50:47.047681  Set Vref, RX VrefLevel [Byte0]: 57

 1055 16:50:47.050763                           [Byte1]: 57

 1056 16:50:47.054869  

 1057 16:50:47.055440  Set Vref, RX VrefLevel [Byte0]: 58

 1058 16:50:47.058634                           [Byte1]: 58

 1059 16:50:47.062580  

 1060 16:50:47.063051  Set Vref, RX VrefLevel [Byte0]: 59

 1061 16:50:47.065760                           [Byte1]: 59

 1062 16:50:47.070445  

 1063 16:50:47.071015  Set Vref, RX VrefLevel [Byte0]: 60

 1064 16:50:47.073783                           [Byte1]: 60

 1065 16:50:47.077744  

 1066 16:50:47.078270  Set Vref, RX VrefLevel [Byte0]: 61

 1067 16:50:47.081117                           [Byte1]: 61

 1068 16:50:47.085184  

 1069 16:50:47.085750  Set Vref, RX VrefLevel [Byte0]: 62

 1070 16:50:47.088122                           [Byte1]: 62

 1071 16:50:47.092589  

 1072 16:50:47.093053  Set Vref, RX VrefLevel [Byte0]: 63

 1073 16:50:47.096442                           [Byte1]: 63

 1074 16:50:47.100640  

 1075 16:50:47.101200  Set Vref, RX VrefLevel [Byte0]: 64

 1076 16:50:47.103776                           [Byte1]: 64

 1077 16:50:47.108335  

 1078 16:50:47.108902  Set Vref, RX VrefLevel [Byte0]: 65

 1079 16:50:47.111526                           [Byte1]: 65

 1080 16:50:47.115897  

 1081 16:50:47.116494  Set Vref, RX VrefLevel [Byte0]: 66

 1082 16:50:47.118902                           [Byte1]: 66

 1083 16:50:47.123289  

 1084 16:50:47.123752  Set Vref, RX VrefLevel [Byte0]: 67

 1085 16:50:47.126503                           [Byte1]: 67

 1086 16:50:47.130878  

 1087 16:50:47.131459  Set Vref, RX VrefLevel [Byte0]: 68

 1088 16:50:47.134294                           [Byte1]: 68

 1089 16:50:47.138539  

 1090 16:50:47.139106  Set Vref, RX VrefLevel [Byte0]: 69

 1091 16:50:47.141788                           [Byte1]: 69

 1092 16:50:47.145873  

 1093 16:50:47.146375  Set Vref, RX VrefLevel [Byte0]: 70

 1094 16:50:47.149355                           [Byte1]: 70

 1095 16:50:47.153640  

 1096 16:50:47.154116  Set Vref, RX VrefLevel [Byte0]: 71

 1097 16:50:47.156997                           [Byte1]: 71

 1098 16:50:47.161346  

 1099 16:50:47.161819  Set Vref, RX VrefLevel [Byte0]: 72

 1100 16:50:47.164714                           [Byte1]: 72

 1101 16:50:47.168548  

 1102 16:50:47.169037  Set Vref, RX VrefLevel [Byte0]: 73

 1103 16:50:47.172549                           [Byte1]: 73

 1104 16:50:47.176467  

 1105 16:50:47.179901  Set Vref, RX VrefLevel [Byte0]: 74

 1106 16:50:47.182971                           [Byte1]: 74

 1107 16:50:47.183435  

 1108 16:50:47.186221  Set Vref, RX VrefLevel [Byte0]: 75

 1109 16:50:47.189266                           [Byte1]: 75

 1110 16:50:47.189730  

 1111 16:50:47.192456  Set Vref, RX VrefLevel [Byte0]: 76

 1112 16:50:47.196216                           [Byte1]: 76

 1113 16:50:47.196678  

 1114 16:50:47.199463  Set Vref, RX VrefLevel [Byte0]: 77

 1115 16:50:47.203010                           [Byte1]: 77

 1116 16:50:47.207116  

 1117 16:50:47.207684  Set Vref, RX VrefLevel [Byte0]: 78

 1118 16:50:47.210297                           [Byte1]: 78

 1119 16:50:47.214534  

 1120 16:50:47.215110  Final RX Vref Byte 0 = 62 to rank0

 1121 16:50:47.217925  Final RX Vref Byte 1 = 63 to rank0

 1122 16:50:47.221270  Final RX Vref Byte 0 = 62 to rank1

 1123 16:50:47.224152  Final RX Vref Byte 1 = 63 to rank1==

 1124 16:50:47.228038  Dram Type= 6, Freq= 0, CH_0, rank 0

 1125 16:50:47.234345  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1126 16:50:47.234952  ==

 1127 16:50:47.235325  DQS Delay:

 1128 16:50:47.237756  DQS0 = 0, DQS1 = 0

 1129 16:50:47.238321  DQM Delay:

 1130 16:50:47.238748  DQM0 = 93, DQM1 = 83

 1131 16:50:47.241312  DQ Delay:

 1132 16:50:47.244240  DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88

 1133 16:50:47.247570  DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104

 1134 16:50:47.251031  DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80

 1135 16:50:47.254028  DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92

 1136 16:50:47.254532  

 1137 16:50:47.254905  

 1138 16:50:47.261151  [DQSOSCAuto] RK0, (LSB)MR18= 0x3733, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps

 1139 16:50:47.263991  CH0 RK0: MR19=606, MR18=3733

 1140 16:50:47.270858  CH0_RK0: MR19=0x606, MR18=0x3733, DQSOSC=395, MR23=63, INC=94, DEC=63

 1141 16:50:47.271402  

 1142 16:50:47.274421  ----->DramcWriteLeveling(PI) begin...

 1143 16:50:47.275109  ==

 1144 16:50:47.277449  Dram Type= 6, Freq= 0, CH_0, rank 1

 1145 16:50:47.281143  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1146 16:50:47.281720  ==

 1147 16:50:47.284019  Write leveling (Byte 0): 32 => 32

 1148 16:50:47.287330  Write leveling (Byte 1): 27 => 27

 1149 16:50:47.290318  DramcWriteLeveling(PI) end<-----

 1150 16:50:47.290828  

 1151 16:50:47.291204  ==

 1152 16:50:47.293974  Dram Type= 6, Freq= 0, CH_0, rank 1

 1153 16:50:47.297590  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1154 16:50:47.298169  ==

 1155 16:50:47.300403  [Gating] SW mode calibration

 1156 16:50:47.307364  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1157 16:50:47.313756  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1158 16:50:47.316997   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1159 16:50:47.323629   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1160 16:50:47.367807   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1161 16:50:47.368445   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1162 16:50:47.368835   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1163 16:50:47.369531   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1164 16:50:47.369924   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1165 16:50:47.370270   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1166 16:50:47.370719   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1167 16:50:47.371079   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1168 16:50:47.371405   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1169 16:50:47.371723   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1170 16:50:47.372103   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1171 16:50:47.375519   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1172 16:50:47.378682   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1173 16:50:47.385601   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1174 16:50:47.388853   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1175 16:50:47.392093   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1176 16:50:47.398781   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1177 16:50:47.402450   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1178 16:50:47.405357   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1179 16:50:47.408681   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1180 16:50:47.415086   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1181 16:50:47.418428   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1182 16:50:47.422309   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1183 16:50:47.428751   0  9  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)

 1184 16:50:47.432001   0  9  8 | B1->B0 | 2b2b 3333 | 1 1 | (1 1) (1 1)

 1185 16:50:47.435054   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1186 16:50:47.441595   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1187 16:50:47.444740   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1188 16:50:47.448012   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1189 16:50:47.455210   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1190 16:50:47.458267   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1191 16:50:47.461747   0 10  4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)

 1192 16:50:47.467981   0 10  8 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)

 1193 16:50:47.471258   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1194 16:50:47.474924   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1195 16:50:47.481214   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1196 16:50:47.484774   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1197 16:50:47.488121   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1198 16:50:47.494424   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1199 16:50:47.498065   0 11  4 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)

 1200 16:50:47.501769   0 11  8 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)

 1201 16:50:47.505602   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1202 16:50:47.512948   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1203 16:50:47.516385   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1204 16:50:47.520066   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1205 16:50:47.523069   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1206 16:50:47.530053   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1207 16:50:47.533619   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1208 16:50:47.537122   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1209 16:50:47.543828   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1210 16:50:47.546934   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1211 16:50:47.550476   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1212 16:50:47.557107   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1213 16:50:47.559818   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1214 16:50:47.563378   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1215 16:50:47.566752   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1216 16:50:47.573341   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1217 16:50:47.576708   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1218 16:50:47.579835   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1219 16:50:47.586404   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1220 16:50:47.589873   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1221 16:50:47.593128   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1222 16:50:47.600355   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1223 16:50:47.603257   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1224 16:50:47.606928   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1225 16:50:47.610497  Total UI for P1: 0, mck2ui 16

 1226 16:50:47.613411  best dqsien dly found for B1: ( 0, 14,  6)

 1227 16:50:47.619891   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1228 16:50:47.620468  Total UI for P1: 0, mck2ui 16

 1229 16:50:47.626909  best dqsien dly found for B0: ( 0, 14,  6)

 1230 16:50:47.630114  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1231 16:50:47.633308  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1232 16:50:47.633880  

 1233 16:50:47.636719  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1234 16:50:47.639912  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1235 16:50:47.643237  [Gating] SW calibration Done

 1236 16:50:47.643708  ==

 1237 16:50:47.646513  Dram Type= 6, Freq= 0, CH_0, rank 1

 1238 16:50:47.649524  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1239 16:50:47.650081  ==

 1240 16:50:47.652868  RX Vref Scan: 0

 1241 16:50:47.653612  

 1242 16:50:47.653995  RX Vref 0 -> 0, step: 1

 1243 16:50:47.654344  

 1244 16:50:47.656481  RX Delay -130 -> 252, step: 16

 1245 16:50:47.662762  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

 1246 16:50:47.666454  iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224

 1247 16:50:47.669355  iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240

 1248 16:50:47.672719  iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224

 1249 16:50:47.676390  iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224

 1250 16:50:47.679253  iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224

 1251 16:50:47.686206  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1252 16:50:47.689611  iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224

 1253 16:50:47.692522  iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208

 1254 16:50:47.696225  iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208

 1255 16:50:47.699491  iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208

 1256 16:50:47.706148  iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224

 1257 16:50:47.709547  iDelay=206, Bit 12, Center 85 (-18 ~ 189) 208

 1258 16:50:47.713240  iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224

 1259 16:50:47.716134  iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224

 1260 16:50:47.723078  iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208

 1261 16:50:47.723613  ==

 1262 16:50:47.726287  Dram Type= 6, Freq= 0, CH_0, rank 1

 1263 16:50:47.763552  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1264 16:50:47.763818  ==

 1265 16:50:47.763979  DQS Delay:

 1266 16:50:47.764119  DQS0 = 0, DQS1 = 0

 1267 16:50:47.764254  DQM Delay:

 1268 16:50:47.764384  DQM0 = 87, DQM1 = 82

 1269 16:50:47.764511  DQ Delay:

 1270 16:50:47.764637  DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77

 1271 16:50:47.764761  DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93

 1272 16:50:47.764885  DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77

 1273 16:50:47.765008  DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85

 1274 16:50:47.765130  

 1275 16:50:47.765250  

 1276 16:50:47.765369  ==

 1277 16:50:47.765492  Dram Type= 6, Freq= 0, CH_0, rank 1

 1278 16:50:47.765614  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1279 16:50:47.765736  ==

 1280 16:50:47.765856  

 1281 16:50:47.765975  

 1282 16:50:47.766096  	TX Vref Scan disable

 1283 16:50:47.766216   == TX Byte 0 ==

 1284 16:50:47.766570  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

 1285 16:50:47.769069  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

 1286 16:50:47.772411   == TX Byte 1 ==

 1287 16:50:47.775509  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1288 16:50:47.778747  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1289 16:50:47.778865  ==

 1290 16:50:47.782273  Dram Type= 6, Freq= 0, CH_0, rank 1

 1291 16:50:47.789142  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1292 16:50:47.789368  ==

 1293 16:50:47.801415  TX Vref=22, minBit 10, minWin=27, winSum=447

 1294 16:50:47.804457  TX Vref=24, minBit 10, minWin=27, winSum=451

 1295 16:50:47.807937  TX Vref=26, minBit 8, minWin=27, winSum=453

 1296 16:50:47.811178  TX Vref=28, minBit 8, minWin=27, winSum=455

 1297 16:50:47.814311  TX Vref=30, minBit 4, minWin=28, winSum=457

 1298 16:50:47.820639  TX Vref=32, minBit 8, minWin=28, winSum=459

 1299 16:50:47.824685  [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32

 1300 16:50:47.824873  

 1301 16:50:47.827367  Final TX Range 1 Vref 32

 1302 16:50:47.827552  

 1303 16:50:47.827650  ==

 1304 16:50:47.831240  Dram Type= 6, Freq= 0, CH_0, rank 1

 1305 16:50:47.834511  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1306 16:50:47.837799  ==

 1307 16:50:47.838017  

 1308 16:50:47.838130  

 1309 16:50:47.838231  	TX Vref Scan disable

 1310 16:50:47.841403   == TX Byte 0 ==

 1311 16:50:47.844744  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

 1312 16:50:47.848280  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

 1313 16:50:47.851741   == TX Byte 1 ==

 1314 16:50:47.854880  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1315 16:50:47.858435  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1316 16:50:47.861595  

 1317 16:50:47.861903  [DATLAT]

 1318 16:50:47.862137  Freq=800, CH0 RK1

 1319 16:50:47.862378  

 1320 16:50:47.864852  DATLAT Default: 0xa

 1321 16:50:47.865151  0, 0xFFFF, sum = 0

 1322 16:50:47.868094  1, 0xFFFF, sum = 0

 1323 16:50:47.868483  2, 0xFFFF, sum = 0

 1324 16:50:47.871499  3, 0xFFFF, sum = 0

 1325 16:50:47.871923  4, 0xFFFF, sum = 0

 1326 16:50:47.875253  5, 0xFFFF, sum = 0

 1327 16:50:47.878481  6, 0xFFFF, sum = 0

 1328 16:50:47.879004  7, 0xFFFF, sum = 0

 1329 16:50:47.881405  8, 0xFFFF, sum = 0

 1330 16:50:47.881832  9, 0x0, sum = 1

 1331 16:50:47.882454  10, 0x0, sum = 2

 1332 16:50:47.885034  11, 0x0, sum = 3

 1333 16:50:47.885458  12, 0x0, sum = 4

 1334 16:50:47.888194  best_step = 10

 1335 16:50:47.888718  

 1336 16:50:47.889051  ==

 1337 16:50:47.891287  Dram Type= 6, Freq= 0, CH_0, rank 1

 1338 16:50:47.894721  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1339 16:50:47.895140  ==

 1340 16:50:47.897873  RX Vref Scan: 0

 1341 16:50:47.898285  

 1342 16:50:47.898672  RX Vref 0 -> 0, step: 1

 1343 16:50:47.901396  

 1344 16:50:47.901936  RX Delay -79 -> 252, step: 8

 1345 16:50:47.908656  iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224

 1346 16:50:47.911798  iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224

 1347 16:50:47.914726  iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224

 1348 16:50:47.918430  iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216

 1349 16:50:47.921648  iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216

 1350 16:50:47.928749  iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224

 1351 16:50:47.931949  iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216

 1352 16:50:47.934955  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1353 16:50:47.938147  iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208

 1354 16:50:47.942074  iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208

 1355 16:50:47.948139  iDelay=209, Bit 10, Center 84 (-15 ~ 184) 200

 1356 16:50:47.951599  iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200

 1357 16:50:47.954727  iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216

 1358 16:50:47.958276  iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216

 1359 16:50:47.964851  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1360 16:50:47.967898  iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208

 1361 16:50:47.968320  ==

 1362 16:50:47.971116  Dram Type= 6, Freq= 0, CH_0, rank 1

 1363 16:50:47.975219  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1364 16:50:47.975745  ==

 1365 16:50:47.976080  DQS Delay:

 1366 16:50:47.978324  DQS0 = 0, DQS1 = 0

 1367 16:50:47.978870  DQM Delay:

 1368 16:50:47.981487  DQM0 = 91, DQM1 = 81

 1369 16:50:47.981903  DQ Delay:

 1370 16:50:47.984835  DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84

 1371 16:50:47.988194  DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100

 1372 16:50:47.991849  DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76

 1373 16:50:47.994844  DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88

 1374 16:50:47.995261  

 1375 16:50:47.995590  

 1376 16:50:48.004785  [DQSOSCAuto] RK1, (LSB)MR18= 0x451f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps

 1377 16:50:48.005321  CH0 RK1: MR19=606, MR18=451F

 1378 16:50:48.011211  CH0_RK1: MR19=0x606, MR18=0x451F, DQSOSC=392, MR23=63, INC=96, DEC=64

 1379 16:50:48.014755  [RxdqsGatingPostProcess] freq 800

 1380 16:50:48.021615  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1381 16:50:48.024826  Pre-setting of DQS Precalculation

 1382 16:50:48.028246  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1383 16:50:48.028767  ==

 1384 16:50:48.031321  Dram Type= 6, Freq= 0, CH_1, rank 0

 1385 16:50:48.034572  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1386 16:50:48.037870  ==

 1387 16:50:48.041568  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1388 16:50:48.047942  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1389 16:50:48.057037  [CA 0] Center 36 (6~67) winsize 62

 1390 16:50:48.060149  [CA 1] Center 37 (6~68) winsize 63

 1391 16:50:48.063848  [CA 2] Center 35 (5~65) winsize 61

 1392 16:50:48.066706  [CA 3] Center 34 (4~65) winsize 62

 1393 16:50:48.070300  [CA 4] Center 34 (4~65) winsize 62

 1394 16:50:48.073570  [CA 5] Center 34 (3~65) winsize 63

 1395 16:50:48.074090  

 1396 16:50:48.076526  [CmdBusTrainingLP45] Vref(ca) range 1: 30

 1397 16:50:48.077042  

 1398 16:50:48.079702  [CATrainingPosCal] consider 1 rank data

 1399 16:50:48.083329  u2DelayCellTimex100 = 270/100 ps

 1400 16:50:48.086829  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1401 16:50:48.093223  CA1 delay=37 (6~68),Diff = 3 PI (21 cell)

 1402 16:50:48.097112  CA2 delay=35 (5~65),Diff = 1 PI (7 cell)

 1403 16:50:48.099962  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1404 16:50:48.103179  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1405 16:50:48.106587  CA5 delay=34 (3~65),Diff = 0 PI (0 cell)

 1406 16:50:48.107057  

 1407 16:50:48.109846  CA PerBit enable=1, Macro0, CA PI delay=34

 1408 16:50:48.110316  

 1409 16:50:48.113333  [CBTSetCACLKResult] CA Dly = 34

 1410 16:50:48.113763  CS Dly: 5 (0~36)

 1411 16:50:48.114105  ==

 1412 16:50:48.116512  Dram Type= 6, Freq= 0, CH_1, rank 1

 1413 16:50:48.123460  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1414 16:50:48.123973  ==

 1415 16:50:48.126724  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1416 16:50:48.133454  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1417 16:50:48.143203  [CA 0] Center 37 (6~68) winsize 63

 1418 16:50:48.146541  [CA 1] Center 37 (6~68) winsize 63

 1419 16:50:48.149708  [CA 2] Center 35 (5~66) winsize 62

 1420 16:50:48.152570  [CA 3] Center 34 (4~65) winsize 62

 1421 16:50:48.156552  [CA 4] Center 34 (4~65) winsize 62

 1422 16:50:48.159526  [CA 5] Center 34 (4~65) winsize 62

 1423 16:50:48.160101  

 1424 16:50:48.162816  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1425 16:50:48.163403  

 1426 16:50:48.166080  [CATrainingPosCal] consider 2 rank data

 1427 16:50:48.169795  u2DelayCellTimex100 = 270/100 ps

 1428 16:50:48.173716  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1429 16:50:48.177193  CA1 delay=37 (6~68),Diff = 3 PI (21 cell)

 1430 16:50:48.180764  CA2 delay=35 (5~65),Diff = 1 PI (7 cell)

 1431 16:50:48.184383  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1432 16:50:48.188076  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1433 16:50:48.191706  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 1434 16:50:48.192139  

 1435 16:50:48.195627  CA PerBit enable=1, Macro0, CA PI delay=34

 1436 16:50:48.196056  

 1437 16:50:48.199846  [CBTSetCACLKResult] CA Dly = 34

 1438 16:50:48.200278  CS Dly: 6 (0~38)

 1439 16:50:48.200614  

 1440 16:50:48.203002  ----->DramcWriteLeveling(PI) begin...

 1441 16:50:48.206546  ==

 1442 16:50:48.206974  Dram Type= 6, Freq= 0, CH_1, rank 0

 1443 16:50:48.213046  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1444 16:50:48.213560  ==

 1445 16:50:48.216744  Write leveling (Byte 0): 28 => 28

 1446 16:50:48.220112  Write leveling (Byte 1): 29 => 29

 1447 16:50:48.220654  DramcWriteLeveling(PI) end<-----

 1448 16:50:48.223092  

 1449 16:50:48.223519  ==

 1450 16:50:48.226921  Dram Type= 6, Freq= 0, CH_1, rank 0

 1451 16:50:48.230035  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1452 16:50:48.230592  ==

 1453 16:50:48.233238  [Gating] SW mode calibration

 1454 16:50:48.240170  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1455 16:50:48.243229  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1456 16:50:48.249931   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1457 16:50:48.253137   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1458 16:50:48.256558   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1459 16:50:48.263297   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1460 16:50:48.266521   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1461 16:50:48.269836   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1462 16:50:48.276650   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1463 16:50:48.279901   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1464 16:50:48.283203   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1465 16:50:48.290081   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1466 16:50:48.293263   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1467 16:50:48.296477   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1468 16:50:48.303150   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1469 16:50:48.306627   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1470 16:50:48.309434   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1471 16:50:48.316048   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1472 16:50:48.319302   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1473 16:50:48.323214   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1474 16:50:48.326147   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1475 16:50:48.332801   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1476 16:50:48.336276   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1477 16:50:48.339383   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1478 16:50:48.345956   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1479 16:50:48.349606   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1480 16:50:48.352705   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1481 16:50:48.359699   0  9  4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)

 1482 16:50:48.363019   0  9  8 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)

 1483 16:50:48.366455   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1484 16:50:48.372715   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1485 16:50:48.376035   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1486 16:50:48.379428   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1487 16:50:48.385894   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1488 16:50:48.389440   0 10  0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)

 1489 16:50:48.392547   0 10  4 | B1->B0 | 2f2f 2929 | 1 1 | (1 0) (1 0)

 1490 16:50:48.398990   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1491 16:50:48.402839   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1492 16:50:48.405581   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1493 16:50:48.412674   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1494 16:50:48.415837   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1495 16:50:48.419264   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1496 16:50:48.425817   0 11  0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 1497 16:50:48.428623   0 11  4 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)

 1498 16:50:48.432401   0 11  8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 1499 16:50:48.439282   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1500 16:50:48.442196   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1501 16:50:48.445693   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1502 16:50:48.452656   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1503 16:50:48.455764   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1504 16:50:48.459326   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1505 16:50:48.465627   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1506 16:50:48.469089   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1507 16:50:48.472387   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1508 16:50:48.478550   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1509 16:50:48.481909   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1510 16:50:48.485230   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1511 16:50:48.491532   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1512 16:50:48.495298   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1513 16:50:48.498430   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1514 16:50:48.505167   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1515 16:50:48.508817   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1516 16:50:48.511879   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1517 16:50:48.515249   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1518 16:50:48.521608   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1519 16:50:48.525340   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1520 16:50:48.528408   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1521 16:50:48.534899   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1522 16:50:48.537933  Total UI for P1: 0, mck2ui 16

 1523 16:50:48.541426  best dqsien dly found for B0: ( 0, 14,  0)

 1524 16:50:48.544768   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1525 16:50:48.547846  Total UI for P1: 0, mck2ui 16

 1526 16:50:48.551136  best dqsien dly found for B1: ( 0, 14,  4)

 1527 16:50:48.554951  best DQS0 dly(MCK, UI, PI) = (0, 14, 0)

 1528 16:50:48.558272  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1529 16:50:48.558841  

 1530 16:50:48.561721  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)

 1531 16:50:48.564585  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1532 16:50:48.568023  [Gating] SW calibration Done

 1533 16:50:48.568556  ==

 1534 16:50:48.571070  Dram Type= 6, Freq= 0, CH_1, rank 0

 1535 16:50:48.577795  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1536 16:50:48.578330  ==

 1537 16:50:48.578695  RX Vref Scan: 0

 1538 16:50:48.579014  

 1539 16:50:48.581094  RX Vref 0 -> 0, step: 1

 1540 16:50:48.581626  

 1541 16:50:48.584362  RX Delay -130 -> 252, step: 16

 1542 16:50:48.587569  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1543 16:50:48.591042  iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224

 1544 16:50:48.594494  iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224

 1545 16:50:48.601005  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1546 16:50:48.604244  iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224

 1547 16:50:48.608007  iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208

 1548 16:50:48.611077  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1549 16:50:48.614391  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

 1550 16:50:48.621232  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1551 16:50:48.624847  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1552 16:50:48.628170  iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240

 1553 16:50:48.631182  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1554 16:50:48.634450  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1555 16:50:48.641178  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1556 16:50:48.644093  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1557 16:50:48.647264  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1558 16:50:48.647702  ==

 1559 16:50:48.650517  Dram Type= 6, Freq= 0, CH_1, rank 0

 1560 16:50:48.654264  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1561 16:50:48.654832  ==

 1562 16:50:48.657545  DQS Delay:

 1563 16:50:48.658076  DQS0 = 0, DQS1 = 0

 1564 16:50:48.660596  DQM Delay:

 1565 16:50:48.661037  DQM0 = 87, DQM1 = 80

 1566 16:50:48.661474  DQ Delay:

 1567 16:50:48.664419  DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85

 1568 16:50:48.667203  DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85

 1569 16:50:48.670428  DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77

 1570 16:50:48.673669  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1571 16:50:48.674113  

 1572 16:50:48.677300  

 1573 16:50:48.677737  ==

 1574 16:50:48.680638  Dram Type= 6, Freq= 0, CH_1, rank 0

 1575 16:50:48.683669  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1576 16:50:48.684112  ==

 1577 16:50:48.684553  

 1578 16:50:48.684970  

 1579 16:50:48.687040  	TX Vref Scan disable

 1580 16:50:48.687510   == TX Byte 0 ==

 1581 16:50:48.693857  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1582 16:50:48.697350  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1583 16:50:48.697778   == TX Byte 1 ==

 1584 16:50:48.704257  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1585 16:50:48.707148  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1586 16:50:48.707748  ==

 1587 16:50:48.710945  Dram Type= 6, Freq= 0, CH_1, rank 0

 1588 16:50:48.713619  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1589 16:50:48.714167  ==

 1590 16:50:48.726840  TX Vref=22, minBit 8, minWin=27, winSum=447

 1591 16:50:48.730051  TX Vref=24, minBit 13, minWin=27, winSum=450

 1592 16:50:48.733691  TX Vref=26, minBit 15, minWin=27, winSum=458

 1593 16:50:48.737096  TX Vref=28, minBit 15, minWin=27, winSum=457

 1594 16:50:48.740320  TX Vref=30, minBit 15, minWin=27, winSum=458

 1595 16:50:48.746809  TX Vref=32, minBit 8, minWin=28, winSum=458

 1596 16:50:48.750026  [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32

 1597 16:50:48.750593  

 1598 16:50:48.753415  Final TX Range 1 Vref 32

 1599 16:50:48.753961  

 1600 16:50:48.754303  ==

 1601 16:50:48.757111  Dram Type= 6, Freq= 0, CH_1, rank 0

 1602 16:50:48.760466  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1603 16:50:48.760888  ==

 1604 16:50:48.761218  

 1605 16:50:48.763800  

 1606 16:50:48.764233  	TX Vref Scan disable

 1607 16:50:48.767501   == TX Byte 0 ==

 1608 16:50:48.770506  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1609 16:50:48.774206  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1610 16:50:48.777492   == TX Byte 1 ==

 1611 16:50:48.780758  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1612 16:50:48.786864  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1613 16:50:48.786947  

 1614 16:50:48.787011  [DATLAT]

 1615 16:50:48.787071  Freq=800, CH1 RK0

 1616 16:50:48.787130  

 1617 16:50:48.790411  DATLAT Default: 0xa

 1618 16:50:48.790524  0, 0xFFFF, sum = 0

 1619 16:50:48.793401  1, 0xFFFF, sum = 0

 1620 16:50:48.793483  2, 0xFFFF, sum = 0

 1621 16:50:48.796540  3, 0xFFFF, sum = 0

 1622 16:50:48.799919  4, 0xFFFF, sum = 0

 1623 16:50:48.800003  5, 0xFFFF, sum = 0

 1624 16:50:48.803666  6, 0xFFFF, sum = 0

 1625 16:50:48.803750  7, 0xFFFF, sum = 0

 1626 16:50:48.806819  8, 0xFFFF, sum = 0

 1627 16:50:48.806902  9, 0x0, sum = 1

 1628 16:50:48.810018  10, 0x0, sum = 2

 1629 16:50:48.810101  11, 0x0, sum = 3

 1630 16:50:48.810167  12, 0x0, sum = 4

 1631 16:50:48.813273  best_step = 10

 1632 16:50:48.813354  

 1633 16:50:48.813418  ==

 1634 16:50:48.816853  Dram Type= 6, Freq= 0, CH_1, rank 0

 1635 16:50:48.820130  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1636 16:50:48.820240  ==

 1637 16:50:48.823496  RX Vref Scan: 1

 1638 16:50:48.823577  

 1639 16:50:48.826287  Set Vref Range= 32 -> 127

 1640 16:50:48.826374  

 1641 16:50:48.826438  RX Vref 32 -> 127, step: 1

 1642 16:50:48.826499  

 1643 16:50:48.829927  RX Delay -95 -> 252, step: 8

 1644 16:50:48.830008  

 1645 16:50:48.833244  Set Vref, RX VrefLevel [Byte0]: 32

 1646 16:50:48.836607                           [Byte1]: 32

 1647 16:50:48.836688  

 1648 16:50:48.840061  Set Vref, RX VrefLevel [Byte0]: 33

 1649 16:50:48.843340                           [Byte1]: 33

 1650 16:50:48.847095  

 1651 16:50:48.847176  Set Vref, RX VrefLevel [Byte0]: 34

 1652 16:50:48.850289                           [Byte1]: 34

 1653 16:50:48.854716  

 1654 16:50:48.854799  Set Vref, RX VrefLevel [Byte0]: 35

 1655 16:50:48.857938                           [Byte1]: 35

 1656 16:50:48.862498  

 1657 16:50:48.862579  Set Vref, RX VrefLevel [Byte0]: 36

 1658 16:50:48.865731                           [Byte1]: 36

 1659 16:50:48.869973  

 1660 16:50:48.870054  Set Vref, RX VrefLevel [Byte0]: 37

 1661 16:50:48.873198                           [Byte1]: 37

 1662 16:50:48.877728  

 1663 16:50:48.877810  Set Vref, RX VrefLevel [Byte0]: 38

 1664 16:50:48.881037                           [Byte1]: 38

 1665 16:50:48.885194  

 1666 16:50:48.885279  Set Vref, RX VrefLevel [Byte0]: 39

 1667 16:50:48.888406                           [Byte1]: 39

 1668 16:50:48.893003  

 1669 16:50:48.893085  Set Vref, RX VrefLevel [Byte0]: 40

 1670 16:50:48.896040                           [Byte1]: 40

 1671 16:50:48.900741  

 1672 16:50:48.900822  Set Vref, RX VrefLevel [Byte0]: 41

 1673 16:50:48.903542                           [Byte1]: 41

 1674 16:50:48.907820  

 1675 16:50:48.907903  Set Vref, RX VrefLevel [Byte0]: 42

 1676 16:50:48.911131                           [Byte1]: 42

 1677 16:50:48.915713  

 1678 16:50:48.915796  Set Vref, RX VrefLevel [Byte0]: 43

 1679 16:50:48.918866                           [Byte1]: 43

 1680 16:50:48.923032  

 1681 16:50:48.923114  Set Vref, RX VrefLevel [Byte0]: 44

 1682 16:50:48.926411                           [Byte1]: 44

 1683 16:50:48.930880  

 1684 16:50:48.930962  Set Vref, RX VrefLevel [Byte0]: 45

 1685 16:50:48.934079                           [Byte1]: 45

 1686 16:50:48.938171  

 1687 16:50:48.938280  Set Vref, RX VrefLevel [Byte0]: 46

 1688 16:50:48.941427                           [Byte1]: 46

 1689 16:50:48.945977  

 1690 16:50:48.946059  Set Vref, RX VrefLevel [Byte0]: 47

 1691 16:50:48.949254                           [Byte1]: 47

 1692 16:50:48.953390  

 1693 16:50:48.953473  Set Vref, RX VrefLevel [Byte0]: 48

 1694 16:50:48.956986                           [Byte1]: 48

 1695 16:50:48.961202  

 1696 16:50:48.961284  Set Vref, RX VrefLevel [Byte0]: 49

 1697 16:50:48.964611                           [Byte1]: 49

 1698 16:50:48.968648  

 1699 16:50:48.968756  Set Vref, RX VrefLevel [Byte0]: 50

 1700 16:50:48.972036                           [Byte1]: 50

 1701 16:50:48.976151  

 1702 16:50:48.976234  Set Vref, RX VrefLevel [Byte0]: 51

 1703 16:50:48.979782                           [Byte1]: 51

 1704 16:50:48.983935  

 1705 16:50:48.984018  Set Vref, RX VrefLevel [Byte0]: 52

 1706 16:50:48.987246                           [Byte1]: 52

 1707 16:50:48.991610  

 1708 16:50:48.991692  Set Vref, RX VrefLevel [Byte0]: 53

 1709 16:50:48.994860                           [Byte1]: 53

 1710 16:50:48.998980  

 1711 16:50:48.999090  Set Vref, RX VrefLevel [Byte0]: 54

 1712 16:50:49.002614                           [Byte1]: 54

 1713 16:50:49.006620  

 1714 16:50:49.006702  Set Vref, RX VrefLevel [Byte0]: 55

 1715 16:50:49.010376                           [Byte1]: 55

 1716 16:50:49.014361  

 1717 16:50:49.014447  Set Vref, RX VrefLevel [Byte0]: 56

 1718 16:50:49.017859                           [Byte1]: 56

 1719 16:50:49.021676  

 1720 16:50:49.021758  Set Vref, RX VrefLevel [Byte0]: 57

 1721 16:50:49.025002                           [Byte1]: 57

 1722 16:50:49.029256  

 1723 16:50:49.029339  Set Vref, RX VrefLevel [Byte0]: 58

 1724 16:50:49.032903                           [Byte1]: 58

 1725 16:50:49.037042  

 1726 16:50:49.037124  Set Vref, RX VrefLevel [Byte0]: 59

 1727 16:50:49.040297                           [Byte1]: 59

 1728 16:50:49.044769  

 1729 16:50:49.044878  Set Vref, RX VrefLevel [Byte0]: 60

 1730 16:50:49.047975                           [Byte1]: 60

 1731 16:50:49.052038  

 1732 16:50:49.052121  Set Vref, RX VrefLevel [Byte0]: 61

 1733 16:50:49.055728                           [Byte1]: 61

 1734 16:50:49.059894  

 1735 16:50:49.059977  Set Vref, RX VrefLevel [Byte0]: 62

 1736 16:50:49.063157                           [Byte1]: 62

 1737 16:50:49.067393  

 1738 16:50:49.067502  Set Vref, RX VrefLevel [Byte0]: 63

 1739 16:50:49.070515                           [Byte1]: 63

 1740 16:50:49.075005  

 1741 16:50:49.075087  Set Vref, RX VrefLevel [Byte0]: 64

 1742 16:50:49.078239                           [Byte1]: 64

 1743 16:50:49.082662  

 1744 16:50:49.082744  Set Vref, RX VrefLevel [Byte0]: 65

 1745 16:50:49.086303                           [Byte1]: 65

 1746 16:50:49.090558  

 1747 16:50:49.090638  Set Vref, RX VrefLevel [Byte0]: 66

 1748 16:50:49.093879                           [Byte1]: 66

 1749 16:50:49.098091  

 1750 16:50:49.098165  Set Vref, RX VrefLevel [Byte0]: 67

 1751 16:50:49.101232                           [Byte1]: 67

 1752 16:50:49.105582  

 1753 16:50:49.105659  Set Vref, RX VrefLevel [Byte0]: 68

 1754 16:50:49.108807                           [Byte1]: 68

 1755 16:50:49.113073  

 1756 16:50:49.113152  Set Vref, RX VrefLevel [Byte0]: 69

 1757 16:50:49.116326                           [Byte1]: 69

 1758 16:50:49.120823  

 1759 16:50:49.120907  Set Vref, RX VrefLevel [Byte0]: 70

 1760 16:50:49.123982                           [Byte1]: 70

 1761 16:50:49.128628  

 1762 16:50:49.128711  Set Vref, RX VrefLevel [Byte0]: 71

 1763 16:50:49.131369                           [Byte1]: 71

 1764 16:50:49.135870  

 1765 16:50:49.135953  Set Vref, RX VrefLevel [Byte0]: 72

 1766 16:50:49.139140                           [Byte1]: 72

 1767 16:50:49.143427  

 1768 16:50:49.143509  Set Vref, RX VrefLevel [Byte0]: 73

 1769 16:50:49.146690                           [Byte1]: 73

 1770 16:50:49.151265  

 1771 16:50:49.151348  Set Vref, RX VrefLevel [Byte0]: 74

 1772 16:50:49.154404                           [Byte1]: 74

 1773 16:50:49.158590  

 1774 16:50:49.158673  Set Vref, RX VrefLevel [Byte0]: 75

 1775 16:50:49.161955                           [Byte1]: 75

 1776 16:50:49.166313  

 1777 16:50:49.166430  Set Vref, RX VrefLevel [Byte0]: 76

 1778 16:50:49.169601                           [Byte1]: 76

 1779 16:50:49.173734  

 1780 16:50:49.173819  Set Vref, RX VrefLevel [Byte0]: 77

 1781 16:50:49.177165                           [Byte1]: 77

 1782 16:50:49.181327  

 1783 16:50:49.181410  Final RX Vref Byte 0 = 48 to rank0

 1784 16:50:49.184639  Final RX Vref Byte 1 = 63 to rank0

 1785 16:50:49.188230  Final RX Vref Byte 0 = 48 to rank1

 1786 16:50:49.191845  Final RX Vref Byte 1 = 63 to rank1==

 1787 16:50:49.194525  Dram Type= 6, Freq= 0, CH_1, rank 0

 1788 16:50:49.201197  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1789 16:50:49.201282  ==

 1790 16:50:49.201348  DQS Delay:

 1791 16:50:49.201409  DQS0 = 0, DQS1 = 0

 1792 16:50:49.204792  DQM Delay:

 1793 16:50:49.204875  DQM0 = 91, DQM1 = 83

 1794 16:50:49.207880  DQ Delay:

 1795 16:50:49.211061  DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88

 1796 16:50:49.214598  DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88

 1797 16:50:49.217989  DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80

 1798 16:50:49.221447  DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88

 1799 16:50:49.221530  

 1800 16:50:49.221596  

 1801 16:50:49.227848  [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps

 1802 16:50:49.231584  CH1 RK0: MR19=606, MR18=2B48

 1803 16:50:49.238148  CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64

 1804 16:50:49.238232  

 1805 16:50:49.241271  ----->DramcWriteLeveling(PI) begin...

 1806 16:50:49.241354  ==

 1807 16:50:49.244511  Dram Type= 6, Freq= 0, CH_1, rank 1

 1808 16:50:49.248161  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1809 16:50:49.248244  ==

 1810 16:50:49.251196  Write leveling (Byte 0): 29 => 29

 1811 16:50:49.254513  Write leveling (Byte 1): 29 => 29

 1812 16:50:49.258166  DramcWriteLeveling(PI) end<-----

 1813 16:50:49.258249  

 1814 16:50:49.258314  ==

 1815 16:50:49.261415  Dram Type= 6, Freq= 0, CH_1, rank 1

 1816 16:50:49.264610  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1817 16:50:49.264694  ==

 1818 16:50:49.267866  [Gating] SW mode calibration

 1819 16:50:49.274285  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1820 16:50:49.281323  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1821 16:50:49.284335   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1822 16:50:49.287660   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1823 16:50:49.294411   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1824 16:50:49.297839   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1825 16:50:49.300682   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1826 16:50:49.307715   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1827 16:50:49.310756   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1828 16:50:49.314334   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1829 16:50:49.320995   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1830 16:50:49.323923   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1831 16:50:49.327558   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1832 16:50:49.334052   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1833 16:50:49.337340   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1834 16:50:49.340625   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1835 16:50:49.347444   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1836 16:50:49.350644   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1837 16:50:49.353900   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1838 16:50:49.360745   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1839 16:50:49.364038   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1840 16:50:49.367500   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1841 16:50:49.373991   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1842 16:50:49.377264   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1843 16:50:49.380511   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1844 16:50:49.387225   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1845 16:50:49.390566   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1846 16:50:49.394077   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1847 16:50:49.400486   0  9  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 1848 16:50:49.403949   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1849 16:50:49.407034   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1850 16:50:49.413633   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1851 16:50:49.416966   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1852 16:50:49.420319   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1853 16:50:49.427201   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1854 16:50:49.430680   0 10  4 | B1->B0 | 2e2e 2f2f | 1 0 | (1 0) (0 0)

 1855 16:50:49.433991   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1856 16:50:49.440473   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1857 16:50:49.443610   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1858 16:50:49.446849   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1859 16:50:49.450103   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1860 16:50:49.456840   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1861 16:50:49.460135   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1862 16:50:49.463381   0 11  4 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 1)

 1863 16:50:49.470312   0 11  8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 1864 16:50:49.473606   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1865 16:50:49.476823   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1866 16:50:49.483706   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1867 16:50:49.487193   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1868 16:50:49.490261   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1869 16:50:49.496767   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1870 16:50:49.500004   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 1871 16:50:49.503385   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1872 16:50:49.510069   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1873 16:50:49.513736   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1874 16:50:49.516804   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1875 16:50:49.523361   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1876 16:50:49.526537   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1877 16:50:49.530309   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1878 16:50:49.536635   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1879 16:50:49.539946   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1880 16:50:49.543571   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1881 16:50:49.550221   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1882 16:50:49.553638   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1883 16:50:49.556730   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1884 16:50:49.563187   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1885 16:50:49.566810   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1886 16:50:49.570046   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1887 16:50:49.573198   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1888 16:50:49.576810  Total UI for P1: 0, mck2ui 16

 1889 16:50:49.580233  best dqsien dly found for B0: ( 0, 14,  6)

 1890 16:50:49.583253  Total UI for P1: 0, mck2ui 16

 1891 16:50:49.586508  best dqsien dly found for B1: ( 0, 14,  6)

 1892 16:50:49.589796  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1893 16:50:49.596702  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1894 16:50:49.596806  

 1895 16:50:49.599864  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1896 16:50:49.603498  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1897 16:50:49.606529  [Gating] SW calibration Done

 1898 16:50:49.606612  ==

 1899 16:50:49.609656  Dram Type= 6, Freq= 0, CH_1, rank 1

 1900 16:50:49.613275  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1901 16:50:49.613383  ==

 1902 16:50:49.613474  RX Vref Scan: 0

 1903 16:50:49.613562  

 1904 16:50:49.616643  RX Vref 0 -> 0, step: 1

 1905 16:50:49.616740  

 1906 16:50:49.619857  RX Delay -130 -> 252, step: 16

 1907 16:50:49.623057  iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224

 1908 16:50:49.626669  iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224

 1909 16:50:49.632866  iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224

 1910 16:50:49.636867  iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208

 1911 16:50:49.639698  iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208

 1912 16:50:49.642942  iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224

 1913 16:50:49.646172  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1914 16:50:49.652760  iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208

 1915 16:50:49.656044  iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240

 1916 16:50:49.659724  iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240

 1917 16:50:49.662957  iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240

 1918 16:50:49.666238  iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240

 1919 16:50:49.672904  iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240

 1920 16:50:49.676288  iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240

 1921 16:50:49.679468  iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240

 1922 16:50:49.682738  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

 1923 16:50:49.682822  ==

 1924 16:50:49.686231  Dram Type= 6, Freq= 0, CH_1, rank 1

 1925 16:50:49.693157  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1926 16:50:49.693243  ==

 1927 16:50:49.693310  DQS Delay:

 1928 16:50:49.696339  DQS0 = 0, DQS1 = 0

 1929 16:50:49.696423  DQM Delay:

 1930 16:50:49.696490  DQM0 = 86, DQM1 = 79

 1931 16:50:49.699591  DQ Delay:

 1932 16:50:49.702809  DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85

 1933 16:50:49.706069  DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85

 1934 16:50:49.709635  DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69

 1935 16:50:49.712824  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1936 16:50:49.712907  

 1937 16:50:49.712973  

 1938 16:50:49.713033  ==

 1939 16:50:49.716245  Dram Type= 6, Freq= 0, CH_1, rank 1

 1940 16:50:49.719356  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1941 16:50:49.719441  ==

 1942 16:50:49.719507  

 1943 16:50:49.719568  

 1944 16:50:49.722759  	TX Vref Scan disable

 1945 16:50:49.722843   == TX Byte 0 ==

 1946 16:50:49.729254  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1947 16:50:49.733122  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1948 16:50:49.733207   == TX Byte 1 ==

 1949 16:50:49.739289  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1950 16:50:49.742744  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1951 16:50:49.742829  ==

 1952 16:50:49.745922  Dram Type= 6, Freq= 0, CH_1, rank 1

 1953 16:50:49.749007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1954 16:50:49.749110  ==

 1955 16:50:49.763309  TX Vref=22, minBit 13, minWin=27, winSum=451

 1956 16:50:49.766375  TX Vref=24, minBit 13, minWin=27, winSum=451

 1957 16:50:49.770113  TX Vref=26, minBit 13, minWin=27, winSum=457

 1958 16:50:49.773286  TX Vref=28, minBit 8, minWin=28, winSum=461

 1959 16:50:49.776553  TX Vref=30, minBit 8, minWin=28, winSum=461

 1960 16:50:49.783428  TX Vref=32, minBit 0, minWin=28, winSum=458

 1961 16:50:49.786549  [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28

 1962 16:50:49.786657  

 1963 16:50:49.789724  Final TX Range 1 Vref 28

 1964 16:50:49.789827  

 1965 16:50:49.789925  ==

 1966 16:50:49.792894  Dram Type= 6, Freq= 0, CH_1, rank 1

 1967 16:50:49.796693  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1968 16:50:49.799566  ==

 1969 16:50:49.799641  

 1970 16:50:49.799716  

 1971 16:50:49.799776  	TX Vref Scan disable

 1972 16:50:49.803259   == TX Byte 0 ==

 1973 16:50:49.806707  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1974 16:50:49.813304  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1975 16:50:49.813413   == TX Byte 1 ==

 1976 16:50:49.816500  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1977 16:50:49.823258  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1978 16:50:49.823360  

 1979 16:50:49.823450  [DATLAT]

 1980 16:50:49.823546  Freq=800, CH1 RK1

 1981 16:50:49.823635  

 1982 16:50:49.826535  DATLAT Default: 0xa

 1983 16:50:49.826608  0, 0xFFFF, sum = 0

 1984 16:50:49.829761  1, 0xFFFF, sum = 0

 1985 16:50:49.829867  2, 0xFFFF, sum = 0

 1986 16:50:49.833230  3, 0xFFFF, sum = 0

 1987 16:50:49.836529  4, 0xFFFF, sum = 0

 1988 16:50:49.836630  5, 0xFFFF, sum = 0

 1989 16:50:49.839762  6, 0xFFFF, sum = 0

 1990 16:50:49.839836  7, 0xFFFF, sum = 0

 1991 16:50:49.843105  8, 0xFFFF, sum = 0

 1992 16:50:49.843180  9, 0x0, sum = 1

 1993 16:50:49.843243  10, 0x0, sum = 2

 1994 16:50:49.847124  11, 0x0, sum = 3

 1995 16:50:49.847198  12, 0x0, sum = 4

 1996 16:50:49.849996  best_step = 10

 1997 16:50:49.850067  

 1998 16:50:49.850128  ==

 1999 16:50:49.853322  Dram Type= 6, Freq= 0, CH_1, rank 1

 2000 16:50:49.856321  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2001 16:50:49.856396  ==

 2002 16:50:49.860096  RX Vref Scan: 0

 2003 16:50:49.860179  

 2004 16:50:49.860244  RX Vref 0 -> 0, step: 1

 2005 16:50:49.862826  

 2006 16:50:49.862898  RX Delay -95 -> 252, step: 8

 2007 16:50:49.870240  iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200

 2008 16:50:49.873576  iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200

 2009 16:50:49.876795  iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208

 2010 16:50:49.880100  iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208

 2011 16:50:49.883373  iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208

 2012 16:50:49.889762  iDelay=209, Bit 5, Center 104 (1 ~ 208) 208

 2013 16:50:49.893202  iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208

 2014 16:50:49.896882  iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208

 2015 16:50:49.900075  iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216

 2016 16:50:49.903267  iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224

 2017 16:50:49.909837  iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224

 2018 16:50:50.113070  iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224

 2019 16:50:50.113259  iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216

 2020 16:50:50.113360  iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216

 2021 16:50:50.113423  iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224

 2022 16:50:50.113481  iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232

 2023 16:50:50.113540  ==

 2024 16:50:50.113599  Dram Type= 6, Freq= 0, CH_1, rank 1

 2025 16:50:50.113654  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2026 16:50:50.113710  ==

 2027 16:50:50.113765  DQS Delay:

 2028 16:50:50.113818  DQS0 = 0, DQS1 = 0

 2029 16:50:50.113873  DQM Delay:

 2030 16:50:50.113927  DQM0 = 91, DQM1 = 84

 2031 16:50:50.113981  DQ Delay:

 2032 16:50:50.114064  DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88

 2033 16:50:50.114117  DQ4 =96, DQ5 =104, DQ6 =96, DQ7 =88

 2034 16:50:50.114170  DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80

 2035 16:50:50.114224  DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =92

 2036 16:50:50.114277  

 2037 16:50:50.114346  

 2038 16:50:50.114420  [DQSOSCAuto] RK1, (LSB)MR18= 0x370b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 395 ps

 2039 16:50:50.114477  CH1 RK1: MR19=606, MR18=370B

 2040 16:50:50.114532  CH1_RK1: MR19=0x606, MR18=0x370B, DQSOSC=395, MR23=63, INC=94, DEC=63

 2041 16:50:50.114601  [RxdqsGatingPostProcess] freq 800

 2042 16:50:50.114669  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2043 16:50:50.114723  Pre-setting of DQS Precalculation

 2044 16:50:50.114777  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2045 16:50:50.114831  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2046 16:50:50.114913  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2047 16:50:50.114967  

 2048 16:50:50.115020  

 2049 16:50:50.115073  [Calibration Summary] 1600 Mbps

 2050 16:50:50.115127  CH 0, Rank 0

 2051 16:50:50.115180  SW Impedance     : PASS

 2052 16:50:50.115261  DUTY Scan        : NO K

 2053 16:50:50.115314  ZQ Calibration   : PASS

 2054 16:50:50.115368  Jitter Meter     : NO K

 2055 16:50:50.115421  CBT Training     : PASS

 2056 16:50:50.115474  Write leveling   : PASS

 2057 16:50:50.115557  RX DQS gating    : PASS

 2058 16:50:50.115610  RX DQ/DQS(RDDQC) : PASS

 2059 16:50:50.115662  TX DQ/DQS        : PASS

 2060 16:50:50.115715  RX DATLAT        : PASS

 2061 16:50:50.115768  RX DQ/DQS(Engine): PASS

 2062 16:50:50.115821  TX OE            : NO K

 2063 16:50:50.115874  All Pass.

 2064 16:50:50.115927  

 2065 16:50:50.115979  CH 0, Rank 1

 2066 16:50:50.116032  SW Impedance     : PASS

 2067 16:50:50.116085  DUTY Scan        : NO K

 2068 16:50:50.116138  ZQ Calibration   : PASS

 2069 16:50:50.116191  Jitter Meter     : NO K

 2070 16:50:50.116244  CBT Training     : PASS

 2071 16:50:50.116297  Write leveling   : PASS

 2072 16:50:50.116349  RX DQS gating    : PASS

 2073 16:50:50.116402  RX DQ/DQS(RDDQC) : PASS

 2074 16:50:50.116455  TX DQ/DQS        : PASS

 2075 16:50:50.116509  RX DATLAT        : PASS

 2076 16:50:50.116561  RX DQ/DQS(Engine): PASS

 2077 16:50:50.116629  TX OE            : NO K

 2078 16:50:50.116686  All Pass.

 2079 16:50:50.116743  

 2080 16:50:50.116799  CH 1, Rank 0

 2081 16:50:50.116855  SW Impedance     : PASS

 2082 16:50:50.116912  DUTY Scan        : NO K

 2083 16:50:50.116969  ZQ Calibration   : PASS

 2084 16:50:50.117026  Jitter Meter     : NO K

 2085 16:50:50.117082  CBT Training     : PASS

 2086 16:50:50.117139  Write leveling   : PASS

 2087 16:50:50.117195  RX DQS gating    : PASS

 2088 16:50:50.117252  RX DQ/DQS(RDDQC) : PASS

 2089 16:50:50.117308  TX DQ/DQS        : PASS

 2090 16:50:50.117365  RX DATLAT        : PASS

 2091 16:50:50.117421  RX DQ/DQS(Engine): PASS

 2092 16:50:50.117477  TX OE            : NO K

 2093 16:50:50.117534  All Pass.

 2094 16:50:50.117589  

 2095 16:50:50.117646  CH 1, Rank 1

 2096 16:50:50.117702  SW Impedance     : PASS

 2097 16:50:50.117758  DUTY Scan        : NO K

 2098 16:50:50.117815  ZQ Calibration   : PASS

 2099 16:50:50.117872  Jitter Meter     : NO K

 2100 16:50:50.117928  CBT Training     : PASS

 2101 16:50:50.117985  Write leveling   : PASS

 2102 16:50:50.118042  RX DQS gating    : PASS

 2103 16:50:50.118098  RX DQ/DQS(RDDQC) : PASS

 2104 16:50:50.118154  TX DQ/DQS        : PASS

 2105 16:50:50.158543  RX DATLAT        : PASS

 2106 16:50:50.158747  RX DQ/DQS(Engine): PASS

 2107 16:50:50.158908  TX OE            : NO K

 2108 16:50:50.159058  All Pass.

 2109 16:50:50.159203  

 2110 16:50:50.159343  DramC Write-DBI off

 2111 16:50:50.159481  	PER_BANK_REFRESH: Hybrid Mode

 2112 16:50:50.159630  TX_TRACKING: ON

 2113 16:50:50.159769  [GetDramInforAfterCalByMRR] Vendor 6.

 2114 16:50:50.159904  [GetDramInforAfterCalByMRR] Revision 606.

 2115 16:50:50.160037  [GetDramInforAfterCalByMRR] Revision 2 0.

 2116 16:50:50.160171  MR0 0x3b3b

 2117 16:50:50.160303  MR8 0x5151

 2118 16:50:50.160434  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2119 16:50:50.160567  

 2120 16:50:50.160699  MR0 0x3b3b

 2121 16:50:50.160830  MR8 0x5151

 2122 16:50:50.161220  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2123 16:50:50.161421  

 2124 16:50:50.161629  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2125 16:50:50.162800  [FAST_K] Save calibration result to emmc

 2126 16:50:50.165558  [FAST_K] Save calibration result to emmc

 2127 16:50:50.165787  dram_init: config_dvfs: 1

 2128 16:50:50.172394  dramc_set_vcore_voltage set vcore to 662500

 2129 16:50:50.172794  Read voltage for 1200, 2

 2130 16:50:50.175879  Vio18 = 0

 2131 16:50:50.176277  Vcore = 662500

 2132 16:50:50.176706  Vdram = 0

 2133 16:50:50.179277  Vddq = 0

 2134 16:50:50.179702  Vmddr = 0

 2135 16:50:50.182464  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2136 16:50:50.189207  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2137 16:50:50.192444  MEM_TYPE=3, freq_sel=15

 2138 16:50:50.195778  sv_algorithm_assistance_LP4_1600 

 2139 16:50:50.199101  ============ PULL DRAM RESETB DOWN ============

 2140 16:50:50.202686  ========== PULL DRAM RESETB DOWN end =========

 2141 16:50:50.205909  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2142 16:50:50.209172  =================================== 

 2143 16:50:50.212586  LPDDR4 DRAM CONFIGURATION

 2144 16:50:50.215654  =================================== 

 2145 16:50:50.218996  EX_ROW_EN[0]    = 0x0

 2146 16:50:50.219417  EX_ROW_EN[1]    = 0x0

 2147 16:50:50.222749  LP4Y_EN      = 0x0

 2148 16:50:50.223170  WORK_FSP     = 0x0

 2149 16:50:50.226012  WL           = 0x4

 2150 16:50:50.226456  RL           = 0x4

 2151 16:50:50.229150  BL           = 0x2

 2152 16:50:50.229522  RPST         = 0x0

 2153 16:50:50.232389  RD_PRE       = 0x0

 2154 16:50:50.232789  WR_PRE       = 0x1

 2155 16:50:50.235625  WR_PST       = 0x0

 2156 16:50:50.238893  DBI_WR       = 0x0

 2157 16:50:50.239295  DBI_RD       = 0x0

 2158 16:50:50.241954  OTF          = 0x1

 2159 16:50:50.245381  =================================== 

 2160 16:50:50.248974  =================================== 

 2161 16:50:50.249407  ANA top config

 2162 16:50:50.252461  =================================== 

 2163 16:50:50.255549  DLL_ASYNC_EN            =  0

 2164 16:50:50.259346  ALL_SLAVE_EN            =  0

 2165 16:50:50.259804  NEW_RANK_MODE           =  1

 2166 16:50:50.262127  DLL_IDLE_MODE           =  1

 2167 16:50:50.265523  LP45_APHY_COMB_EN       =  1

 2168 16:50:50.268660  TX_ODT_DIS              =  1

 2169 16:50:50.269248  NEW_8X_MODE             =  1

 2170 16:50:50.272134  =================================== 

 2171 16:50:50.275898  =================================== 

 2172 16:50:50.278625  data_rate                  = 2400

 2173 16:50:50.282051  CKR                        = 1

 2174 16:50:50.285546  DQ_P2S_RATIO               = 8

 2175 16:50:50.288788  =================================== 

 2176 16:50:50.291960  CA_P2S_RATIO               = 8

 2177 16:50:50.295221  DQ_CA_OPEN                 = 0

 2178 16:50:50.295637  DQ_SEMI_OPEN               = 0

 2179 16:50:50.298869  CA_SEMI_OPEN               = 0

 2180 16:50:50.302042  CA_FULL_RATE               = 0

 2181 16:50:50.305306  DQ_CKDIV4_EN               = 0

 2182 16:50:50.309003  CA_CKDIV4_EN               = 0

 2183 16:50:50.312220  CA_PREDIV_EN               = 0

 2184 16:50:50.312643  PH8_DLY                    = 17

 2185 16:50:50.315440  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2186 16:50:50.318718  DQ_AAMCK_DIV               = 4

 2187 16:50:50.322279  CA_AAMCK_DIV               = 4

 2188 16:50:50.325629  CA_ADMCK_DIV               = 4

 2189 16:50:50.328970  DQ_TRACK_CA_EN             = 0

 2190 16:50:50.329393  CA_PICK                    = 1200

 2191 16:50:50.332166  CA_MCKIO                   = 1200

 2192 16:50:50.335461  MCKIO_SEMI                 = 0

 2193 16:50:50.338819  PLL_FREQ                   = 2366

 2194 16:50:50.341826  DQ_UI_PI_RATIO             = 32

 2195 16:50:50.345158  CA_UI_PI_RATIO             = 0

 2196 16:50:50.348760  =================================== 

 2197 16:50:50.351835  =================================== 

 2198 16:50:50.355194  memory_type:LPDDR4         

 2199 16:50:50.355617  GP_NUM     : 10       

 2200 16:50:50.358698  SRAM_EN    : 1       

 2201 16:50:50.359118  MD32_EN    : 0       

 2202 16:50:50.361969  =================================== 

 2203 16:50:50.365242  [ANA_INIT] >>>>>>>>>>>>>> 

 2204 16:50:50.368859  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2205 16:50:50.371990  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2206 16:50:50.375232  =================================== 

 2207 16:50:50.378587  data_rate = 2400,PCW = 0X5b00

 2208 16:50:50.381659  =================================== 

 2209 16:50:50.385393  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2210 16:50:50.388610  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2211 16:50:50.395219  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2212 16:50:50.398444  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2213 16:50:50.405011  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2214 16:50:50.408121  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2215 16:50:50.408548  [ANA_INIT] flow start 

 2216 16:50:50.411990  [ANA_INIT] PLL >>>>>>>> 

 2217 16:50:50.415060  [ANA_INIT] PLL <<<<<<<< 

 2218 16:50:50.415500  [ANA_INIT] MIDPI >>>>>>>> 

 2219 16:50:50.418334  [ANA_INIT] MIDPI <<<<<<<< 

 2220 16:50:50.421535  [ANA_INIT] DLL >>>>>>>> 

 2221 16:50:50.421960  [ANA_INIT] DLL <<<<<<<< 

 2222 16:50:50.424821  [ANA_INIT] flow end 

 2223 16:50:50.428399  ============ LP4 DIFF to SE enter ============

 2224 16:50:50.431640  ============ LP4 DIFF to SE exit  ============

 2225 16:50:50.434899  [ANA_INIT] <<<<<<<<<<<<< 

 2226 16:50:50.438181  [Flow] Enable top DCM control >>>>> 

 2227 16:50:50.441372  [Flow] Enable top DCM control <<<<< 

 2228 16:50:50.444952  Enable DLL master slave shuffle 

 2229 16:50:50.451583  ============================================================== 

 2230 16:50:50.452009  Gating Mode config

 2231 16:50:50.457970  ============================================================== 

 2232 16:50:50.458442  Config description: 

 2233 16:50:50.468174  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2234 16:50:50.474639  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2235 16:50:50.481402  SELPH_MODE            0: By rank         1: By Phase 

 2236 16:50:50.484487  ============================================================== 

 2237 16:50:50.487629  GAT_TRACK_EN                 =  1

 2238 16:50:50.491319  RX_GATING_MODE               =  2

 2239 16:50:50.494768  RX_GATING_TRACK_MODE         =  2

 2240 16:50:50.497903  SELPH_MODE                   =  1

 2241 16:50:50.501032  PICG_EARLY_EN                =  1

 2242 16:50:50.504485  VALID_LAT_VALUE              =  1

 2243 16:50:50.511179  ============================================================== 

 2244 16:50:50.514469  Enter into Gating configuration >>>> 

 2245 16:50:50.517647  Exit from Gating configuration <<<< 

 2246 16:50:50.521317  Enter into  DVFS_PRE_config >>>>> 

 2247 16:50:50.530790  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2248 16:50:50.534290  Exit from  DVFS_PRE_config <<<<< 

 2249 16:50:50.537585  Enter into PICG configuration >>>> 

 2250 16:50:50.540819  Exit from PICG configuration <<<< 

 2251 16:50:50.543936  [RX_INPUT] configuration >>>>> 

 2252 16:50:50.544360  [RX_INPUT] configuration <<<<< 

 2253 16:50:50.550861  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2254 16:50:50.557335  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2255 16:50:50.560923  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2256 16:50:50.567468  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2257 16:50:50.573967  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2258 16:50:50.580703  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2259 16:50:50.583872  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2260 16:50:50.587349  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2261 16:50:50.593847  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2262 16:50:50.597541  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2263 16:50:50.600399  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2264 16:50:50.607212  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2265 16:50:50.610549  =================================== 

 2266 16:50:50.610984  LPDDR4 DRAM CONFIGURATION

 2267 16:50:50.613622  =================================== 

 2268 16:50:50.616941  EX_ROW_EN[0]    = 0x0

 2269 16:50:50.617362  EX_ROW_EN[1]    = 0x0

 2270 16:50:50.620501  LP4Y_EN      = 0x0

 2271 16:50:50.620919  WORK_FSP     = 0x0

 2272 16:50:50.623818  WL           = 0x4

 2273 16:50:50.626797  RL           = 0x4

 2274 16:50:50.627218  BL           = 0x2

 2275 16:50:50.630509  RPST         = 0x0

 2276 16:50:50.631010  RD_PRE       = 0x0

 2277 16:50:50.633762  WR_PRE       = 0x1

 2278 16:50:50.634259  WR_PST       = 0x0

 2279 16:50:50.637083  DBI_WR       = 0x0

 2280 16:50:50.637552  DBI_RD       = 0x0

 2281 16:50:50.640311  OTF          = 0x1

 2282 16:50:50.643453  =================================== 

 2283 16:50:50.646776  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2284 16:50:50.650151  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2285 16:50:50.656672  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2286 16:50:50.657099  =================================== 

 2287 16:50:50.660018  LPDDR4 DRAM CONFIGURATION

 2288 16:50:50.663646  =================================== 

 2289 16:50:50.666858  EX_ROW_EN[0]    = 0x10

 2290 16:50:50.667322  EX_ROW_EN[1]    = 0x0

 2291 16:50:50.670243  LP4Y_EN      = 0x0

 2292 16:50:50.670789  WORK_FSP     = 0x0

 2293 16:50:50.673315  WL           = 0x4

 2294 16:50:50.673909  RL           = 0x4

 2295 16:50:50.677044  BL           = 0x2

 2296 16:50:50.680296  RPST         = 0x0

 2297 16:50:50.680770  RD_PRE       = 0x0

 2298 16:50:50.683543  WR_PRE       = 0x1

 2299 16:50:50.684029  WR_PST       = 0x0

 2300 16:50:50.686793  DBI_WR       = 0x0

 2301 16:50:50.687401  DBI_RD       = 0x0

 2302 16:50:50.690017  OTF          = 0x1

 2303 16:50:50.693359  =================================== 

 2304 16:50:50.699661  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2305 16:50:50.700179  ==

 2306 16:50:50.703202  Dram Type= 6, Freq= 0, CH_0, rank 0

 2307 16:50:50.706825  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2308 16:50:50.707439  ==

 2309 16:50:50.709943  [Duty_Offset_Calibration]

 2310 16:50:50.710586  	B0:2	B1:0	CA:1

 2311 16:50:50.711109  

 2312 16:50:50.713031  [DutyScan_Calibration_Flow] k_type=0

 2313 16:50:50.722114  

 2314 16:50:50.722704  ==CLK 0==

 2315 16:50:50.725360  Final CLK duty delay cell = -4

 2316 16:50:50.728986  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 2317 16:50:50.732141  [-4] MIN Duty = 4875%(X100), DQS PI = 0

 2318 16:50:50.735389  [-4] AVG Duty = 4953%(X100)

 2319 16:50:50.735936  

 2320 16:50:50.738664  CH0 CLK Duty spec in!! Max-Min= 156%

 2321 16:50:50.741889  [DutyScan_Calibration_Flow] ====Done====

 2322 16:50:50.742399  

 2323 16:50:50.745039  [DutyScan_Calibration_Flow] k_type=1

 2324 16:50:50.760732  

 2325 16:50:50.761289  ==DQS 0 ==

 2326 16:50:50.764255  Final DQS duty delay cell = 0

 2327 16:50:50.767690  [0] MAX Duty = 5187%(X100), DQS PI = 28

 2328 16:50:50.770854  [0] MIN Duty = 4938%(X100), DQS PI = 0

 2329 16:50:50.773732  [0] AVG Duty = 5062%(X100)

 2330 16:50:50.774336  

 2331 16:50:50.774785  ==DQS 1 ==

 2332 16:50:50.777342  Final DQS duty delay cell = -4

 2333 16:50:50.780744  [-4] MAX Duty = 5124%(X100), DQS PI = 32

 2334 16:50:50.783960  [-4] MIN Duty = 4938%(X100), DQS PI = 8

 2335 16:50:50.787245  [-4] AVG Duty = 5031%(X100)

 2336 16:50:50.787746  

 2337 16:50:50.790469  CH0 DQS 0 Duty spec in!! Max-Min= 249%

 2338 16:50:50.791017  

 2339 16:50:50.793690  CH0 DQS 1 Duty spec in!! Max-Min= 186%

 2340 16:50:50.796938  [DutyScan_Calibration_Flow] ====Done====

 2341 16:50:50.797502  

 2342 16:50:50.800400  [DutyScan_Calibration_Flow] k_type=3

 2343 16:50:50.816745  

 2344 16:50:50.817151  ==DQM 0 ==

 2345 16:50:50.819948  Final DQM duty delay cell = 0

 2346 16:50:50.823707  [0] MAX Duty = 5062%(X100), DQS PI = 24

 2347 16:50:50.826780  [0] MIN Duty = 4844%(X100), DQS PI = 0

 2348 16:50:50.827191  [0] AVG Duty = 4953%(X100)

 2349 16:50:50.829902  

 2350 16:50:50.830305  ==DQM 1 ==

 2351 16:50:50.833648  Final DQM duty delay cell = -4

 2352 16:50:50.837122  [-4] MAX Duty = 5000%(X100), DQS PI = 32

 2353 16:50:50.840272  [-4] MIN Duty = 4813%(X100), DQS PI = 12

 2354 16:50:50.843472  [-4] AVG Duty = 4906%(X100)

 2355 16:50:50.843875  

 2356 16:50:50.846884  CH0 DQM 0 Duty spec in!! Max-Min= 218%

 2357 16:50:50.847292  

 2358 16:50:50.849790  CH0 DQM 1 Duty spec in!! Max-Min= 187%

 2359 16:50:50.853398  [DutyScan_Calibration_Flow] ====Done====

 2360 16:50:50.853938  

 2361 16:50:50.856607  [DutyScan_Calibration_Flow] k_type=2

 2362 16:50:50.872626  

 2363 16:50:50.873067  ==DQ 0 ==

 2364 16:50:50.876282  Final DQ duty delay cell = -4

 2365 16:50:50.879340  [-4] MAX Duty = 5062%(X100), DQS PI = 34

 2366 16:50:50.882635  [-4] MIN Duty = 4875%(X100), DQS PI = 14

 2367 16:50:50.886067  [-4] AVG Duty = 4968%(X100)

 2368 16:50:50.886537  

 2369 16:50:50.886963  ==DQ 1 ==

 2370 16:50:50.889293  Final DQ duty delay cell = 0

 2371 16:50:50.892555  [0] MAX Duty = 4938%(X100), DQS PI = 6

 2372 16:50:50.896362  [0] MIN Duty = 4907%(X100), DQS PI = 0

 2373 16:50:50.896821  [0] AVG Duty = 4922%(X100)

 2374 16:50:50.899481  

 2375 16:50:50.902467  CH0 DQ 0 Duty spec in!! Max-Min= 187%

 2376 16:50:50.902947  

 2377 16:50:50.906006  CH0 DQ 1 Duty spec in!! Max-Min= 31%

 2378 16:50:50.909321  [DutyScan_Calibration_Flow] ====Done====

 2379 16:50:50.909811  ==

 2380 16:50:50.912943  Dram Type= 6, Freq= 0, CH_1, rank 0

 2381 16:50:50.916347  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2382 16:50:50.916920  ==

 2383 16:50:50.919671  [Duty_Offset_Calibration]

 2384 16:50:50.920132  	B0:0	B1:-1	CA:2

 2385 16:50:50.920502  

 2386 16:50:50.922686  [DutyScan_Calibration_Flow] k_type=0

 2387 16:50:50.933288  

 2388 16:50:50.933837  ==CLK 0==

 2389 16:50:50.936583  Final CLK duty delay cell = 0

 2390 16:50:50.939678  [0] MAX Duty = 5156%(X100), DQS PI = 14

 2391 16:50:50.943265  [0] MIN Duty = 4938%(X100), DQS PI = 44

 2392 16:50:50.943717  [0] AVG Duty = 5047%(X100)

 2393 16:50:50.946434  

 2394 16:50:50.949660  CH1 CLK Duty spec in!! Max-Min= 218%

 2395 16:50:50.952913  [DutyScan_Calibration_Flow] ====Done====

 2396 16:50:50.953363  

 2397 16:50:50.956143  [DutyScan_Calibration_Flow] k_type=1

 2398 16:50:50.972630  

 2399 16:50:50.973051  ==DQS 0 ==

 2400 16:50:50.976047  Final DQS duty delay cell = 0

 2401 16:50:50.979057  [0] MAX Duty = 5093%(X100), DQS PI = 26

 2402 16:50:50.982228  [0] MIN Duty = 4969%(X100), DQS PI = 0

 2403 16:50:50.985660  [0] AVG Duty = 5031%(X100)

 2404 16:50:50.986105  

 2405 16:50:50.986505  ==DQS 1 ==

 2406 16:50:50.988764  Final DQS duty delay cell = 0

 2407 16:50:50.992329  [0] MAX Duty = 5156%(X100), DQS PI = 0

 2408 16:50:50.995474  [0] MIN Duty = 4844%(X100), DQS PI = 36

 2409 16:50:50.998716  [0] AVG Duty = 5000%(X100)

 2410 16:50:50.999169  

 2411 16:50:51.002262  CH1 DQS 0 Duty spec in!! Max-Min= 124%

 2412 16:50:51.002756  

 2413 16:50:51.005351  CH1 DQS 1 Duty spec in!! Max-Min= 312%

 2414 16:50:51.008987  [DutyScan_Calibration_Flow] ====Done====

 2415 16:50:51.009562  

 2416 16:50:51.011900  [DutyScan_Calibration_Flow] k_type=3

 2417 16:50:51.029555  

 2418 16:50:51.029997  ==DQM 0 ==

 2419 16:50:51.032882  Final DQM duty delay cell = 4

 2420 16:50:51.036439  [4] MAX Duty = 5093%(X100), DQS PI = 22

 2421 16:50:51.039806  [4] MIN Duty = 4938%(X100), DQS PI = 30

 2422 16:50:51.042613  [4] AVG Duty = 5015%(X100)

 2423 16:50:51.042722  

 2424 16:50:51.042817  ==DQM 1 ==

 2425 16:50:51.045991  Final DQM duty delay cell = 0

 2426 16:50:51.049241  [0] MAX Duty = 5249%(X100), DQS PI = 0

 2427 16:50:51.052559  [0] MIN Duty = 4907%(X100), DQS PI = 36

 2428 16:50:51.055850  [0] AVG Duty = 5078%(X100)

 2429 16:50:51.055926  

 2430 16:50:51.059157  CH1 DQM 0 Duty spec in!! Max-Min= 155%

 2431 16:50:51.059258  

 2432 16:50:51.062278  CH1 DQM 1 Duty spec in!! Max-Min= 342%

 2433 16:50:51.066001  [DutyScan_Calibration_Flow] ====Done====

 2434 16:50:51.066101  

 2435 16:50:51.069213  [DutyScan_Calibration_Flow] k_type=2

 2436 16:50:51.086006  

 2437 16:50:51.086084  ==DQ 0 ==

 2438 16:50:51.089136  Final DQ duty delay cell = 0

 2439 16:50:51.092604  [0] MAX Duty = 5062%(X100), DQS PI = 20

 2440 16:50:51.095802  [0] MIN Duty = 4938%(X100), DQS PI = 44

 2441 16:50:51.095905  [0] AVG Duty = 5000%(X100)

 2442 16:50:51.099034  

 2443 16:50:51.099139  ==DQ 1 ==

 2444 16:50:51.102449  Final DQ duty delay cell = 0

 2445 16:50:51.105816  [0] MAX Duty = 5031%(X100), DQS PI = 2

 2446 16:50:51.109009  [0] MIN Duty = 4813%(X100), DQS PI = 36

 2447 16:50:51.109109  [0] AVG Duty = 4922%(X100)

 2448 16:50:51.109198  

 2449 16:50:51.112718  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 2450 16:50:51.115732  

 2451 16:50:51.118924  CH1 DQ 1 Duty spec in!! Max-Min= 218%

 2452 16:50:51.122139  [DutyScan_Calibration_Flow] ====Done====

 2453 16:50:51.125715  nWR fixed to 30

 2454 16:50:51.125815  [ModeRegInit_LP4] CH0 RK0

 2455 16:50:51.128819  [ModeRegInit_LP4] CH0 RK1

 2456 16:50:51.132185  [ModeRegInit_LP4] CH1 RK0

 2457 16:50:51.135477  [ModeRegInit_LP4] CH1 RK1

 2458 16:50:51.135580  match AC timing 7

 2459 16:50:51.139048  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2460 16:50:51.145596  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2461 16:50:51.148765  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2462 16:50:51.152451  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2463 16:50:51.158768  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2464 16:50:51.158848  ==

 2465 16:50:51.162103  Dram Type= 6, Freq= 0, CH_0, rank 0

 2466 16:50:51.165697  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2467 16:50:51.165774  ==

 2468 16:50:51.172191  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2469 16:50:51.178600  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2470 16:50:51.185791  [CA 0] Center 38 (7~69) winsize 63

 2471 16:50:51.188967  [CA 1] Center 38 (8~69) winsize 62

 2472 16:50:51.192152  [CA 2] Center 35 (4~66) winsize 63

 2473 16:50:51.195641  [CA 3] Center 35 (4~66) winsize 63

 2474 16:50:51.198838  [CA 4] Center 34 (4~65) winsize 62

 2475 16:50:51.202128  [CA 5] Center 33 (3~63) winsize 61

 2476 16:50:51.202247  

 2477 16:50:51.205368  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2478 16:50:51.205443  

 2479 16:50:51.209082  [CATrainingPosCal] consider 1 rank data

 2480 16:50:51.212307  u2DelayCellTimex100 = 270/100 ps

 2481 16:50:51.215311  CA0 delay=38 (7~69),Diff = 5 PI (24 cell)

 2482 16:50:51.218875  CA1 delay=38 (8~69),Diff = 5 PI (24 cell)

 2483 16:50:51.225419  CA2 delay=35 (4~66),Diff = 2 PI (9 cell)

 2484 16:50:51.229148  CA3 delay=35 (4~66),Diff = 2 PI (9 cell)

 2485 16:50:51.232330  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2486 16:50:51.235646  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 2487 16:50:51.235758  

 2488 16:50:51.239009  CA PerBit enable=1, Macro0, CA PI delay=33

 2489 16:50:51.239086  

 2490 16:50:51.242145  [CBTSetCACLKResult] CA Dly = 33

 2491 16:50:51.242220  CS Dly: 6 (0~37)

 2492 16:50:51.245102  ==

 2493 16:50:51.248544  Dram Type= 6, Freq= 0, CH_0, rank 1

 2494 16:50:51.251841  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2495 16:50:51.251915  ==

 2496 16:50:51.255095  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2497 16:50:51.261667  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2498 16:50:51.271426  [CA 0] Center 39 (8~70) winsize 63

 2499 16:50:51.274638  [CA 1] Center 38 (8~69) winsize 62

 2500 16:50:51.277853  [CA 2] Center 35 (5~66) winsize 62

 2501 16:50:51.281462  [CA 3] Center 35 (5~66) winsize 62

 2502 16:50:51.284619  [CA 4] Center 34 (4~65) winsize 62

 2503 16:50:51.287792  [CA 5] Center 34 (4~64) winsize 61

 2504 16:50:51.287866  

 2505 16:50:51.291393  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 2506 16:50:51.291468  

 2507 16:50:51.294597  [CATrainingPosCal] consider 2 rank data

 2508 16:50:51.297801  u2DelayCellTimex100 = 270/100 ps

 2509 16:50:51.300862  CA0 delay=38 (8~69),Diff = 5 PI (24 cell)

 2510 16:50:51.307819  CA1 delay=38 (8~69),Diff = 5 PI (24 cell)

 2511 16:50:51.311118  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2512 16:50:51.314347  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2513 16:50:51.317841  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2514 16:50:51.320899  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 2515 16:50:51.320999  

 2516 16:50:51.324162  CA PerBit enable=1, Macro0, CA PI delay=33

 2517 16:50:51.324234  

 2518 16:50:51.327545  [CBTSetCACLKResult] CA Dly = 33

 2519 16:50:51.327622  CS Dly: 7 (0~39)

 2520 16:50:51.330946  

 2521 16:50:51.334214  ----->DramcWriteLeveling(PI) begin...

 2522 16:50:51.334316  ==

 2523 16:50:51.338371  Dram Type= 6, Freq= 0, CH_0, rank 0

 2524 16:50:51.341065  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2525 16:50:51.341138  ==

 2526 16:50:51.344318  Write leveling (Byte 0): 35 => 35

 2527 16:50:51.347671  Write leveling (Byte 1): 32 => 32

 2528 16:50:51.350951  DramcWriteLeveling(PI) end<-----

 2529 16:50:51.351027  

 2530 16:50:51.351098  ==

 2531 16:50:51.354596  Dram Type= 6, Freq= 0, CH_0, rank 0

 2532 16:50:51.357624  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2533 16:50:51.357699  ==

 2534 16:50:51.360916  [Gating] SW mode calibration

 2535 16:50:51.367600  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2536 16:50:51.374317  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2537 16:50:51.377481   0 15  0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 2538 16:50:51.380742   0 15  4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)

 2539 16:50:51.387316   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2540 16:50:51.390846   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2541 16:50:51.394194   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2542 16:50:51.401014   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2543 16:50:51.404022   0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 2544 16:50:51.407266   0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)

 2545 16:50:51.410820   1  0  0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)

 2546 16:50:51.417691   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2547 16:50:51.420824   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2548 16:50:51.423914   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2549 16:50:51.430837   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2550 16:50:51.433999   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2551 16:50:51.437671   1  0 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)

 2552 16:50:51.443655   1  0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)

 2553 16:50:51.447075   1  1  0 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)

 2554 16:50:51.450422   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2555 16:50:51.456901   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2556 16:50:51.460284   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2557 16:50:51.463646   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2558 16:50:51.470462   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2559 16:50:51.473719   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2560 16:50:51.476834   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2561 16:50:51.483769   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2562 16:50:51.487063   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2563 16:50:51.490101   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2564 16:50:51.496846   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2565 16:50:51.500116   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2566 16:50:51.503404   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2567 16:50:51.509722   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2568 16:50:51.513359   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2569 16:50:51.516659   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2570 16:50:51.523136   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2571 16:50:51.526573   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2572 16:50:51.530013   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2573 16:50:51.536415   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2574 16:50:51.539706   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2575 16:50:51.543047   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2576 16:50:51.549625   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2577 16:50:51.552884   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2578 16:50:51.556676  Total UI for P1: 0, mck2ui 16

 2579 16:50:51.559616  best dqsien dly found for B0: ( 1,  3, 26)

 2580 16:50:51.563113   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2581 16:50:51.566160  Total UI for P1: 0, mck2ui 16

 2582 16:50:51.569668  best dqsien dly found for B1: ( 1,  4,  0)

 2583 16:50:51.573015  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2584 16:50:51.576465  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2585 16:50:51.576543  

 2586 16:50:51.579690  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2587 16:50:51.586184  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2588 16:50:51.586291  [Gating] SW calibration Done

 2589 16:50:51.586418  ==

 2590 16:50:51.589408  Dram Type= 6, Freq= 0, CH_0, rank 0

 2591 16:50:51.596133  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2592 16:50:51.596246  ==

 2593 16:50:51.596342  RX Vref Scan: 0

 2594 16:50:51.596432  

 2595 16:50:51.599406  RX Vref 0 -> 0, step: 1

 2596 16:50:51.599486  

 2597 16:50:51.602692  RX Delay -40 -> 252, step: 8

 2598 16:50:51.606331  iDelay=208, Bit 0, Center 123 (56 ~ 191) 136

 2599 16:50:51.609660  iDelay=208, Bit 1, Center 123 (48 ~ 199) 152

 2600 16:50:51.613049  iDelay=208, Bit 2, Center 119 (48 ~ 191) 144

 2601 16:50:51.619598  iDelay=208, Bit 3, Center 119 (48 ~ 191) 144

 2602 16:50:51.622795  iDelay=208, Bit 4, Center 127 (56 ~ 199) 144

 2603 16:50:51.626083  iDelay=208, Bit 5, Center 115 (48 ~ 183) 136

 2604 16:50:51.629309  iDelay=208, Bit 6, Center 131 (56 ~ 207) 152

 2605 16:50:51.632665  iDelay=208, Bit 7, Center 127 (56 ~ 199) 144

 2606 16:50:51.639592  iDelay=208, Bit 8, Center 99 (32 ~ 167) 136

 2607 16:50:51.642858  iDelay=208, Bit 9, Center 99 (32 ~ 167) 136

 2608 16:50:51.646231  iDelay=208, Bit 10, Center 107 (40 ~ 175) 136

 2609 16:50:51.649523  iDelay=208, Bit 11, Center 107 (40 ~ 175) 136

 2610 16:50:51.652690  iDelay=208, Bit 12, Center 115 (48 ~ 183) 136

 2611 16:50:51.659667  iDelay=208, Bit 13, Center 115 (48 ~ 183) 136

 2612 16:50:51.662943  iDelay=208, Bit 14, Center 123 (56 ~ 191) 136

 2613 16:50:51.665890  iDelay=208, Bit 15, Center 115 (48 ~ 183) 136

 2614 16:50:51.665993  ==

 2615 16:50:51.669179  Dram Type= 6, Freq= 0, CH_0, rank 0

 2616 16:50:51.672729  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2617 16:50:51.672832  ==

 2618 16:50:51.675888  DQS Delay:

 2619 16:50:51.675973  DQS0 = 0, DQS1 = 0

 2620 16:50:51.679213  DQM Delay:

 2621 16:50:51.679291  DQM0 = 123, DQM1 = 110

 2622 16:50:51.682556  DQ Delay:

 2623 16:50:51.686129  DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119

 2624 16:50:51.689362  DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127

 2625 16:50:51.692551  DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107

 2626 16:50:51.695626  DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115

 2627 16:50:51.695705  

 2628 16:50:51.695769  

 2629 16:50:51.695848  ==

 2630 16:50:51.699068  Dram Type= 6, Freq= 0, CH_0, rank 0

 2631 16:50:51.702335  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2632 16:50:51.702465  ==

 2633 16:50:51.702559  

 2634 16:50:51.702649  

 2635 16:50:51.705689  	TX Vref Scan disable

 2636 16:50:51.709035   == TX Byte 0 ==

 2637 16:50:51.712291  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2638 16:50:51.715787  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2639 16:50:51.718680   == TX Byte 1 ==

 2640 16:50:51.722010  Update DQ  dly =849 (3 ,2, 17)  DQ  OEN =(2 ,7)

 2641 16:50:51.725552  Update DQM dly =849 (3 ,2, 17)  DQM OEN =(2 ,7)

 2642 16:50:51.725665  ==

 2643 16:50:51.728781  Dram Type= 6, Freq= 0, CH_0, rank 0

 2644 16:50:51.732045  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2645 16:50:51.735506  ==

 2646 16:50:51.745522  TX Vref=22, minBit 0, minWin=24, winSum=406

 2647 16:50:51.748778  TX Vref=24, minBit 0, minWin=24, winSum=403

 2648 16:50:51.752495  TX Vref=26, minBit 0, minWin=25, winSum=412

 2649 16:50:51.755738  TX Vref=28, minBit 7, minWin=24, winSum=415

 2650 16:50:51.758647  TX Vref=30, minBit 3, minWin=25, winSum=414

 2651 16:50:51.765562  TX Vref=32, minBit 3, minWin=25, winSum=412

 2652 16:50:51.768746  [TxChooseVref] Worse bit 3, Min win 25, Win sum 414, Final Vref 30

 2653 16:50:51.768830  

 2654 16:50:51.772176  Final TX Range 1 Vref 30

 2655 16:50:51.772260  

 2656 16:50:51.772327  ==

 2657 16:50:51.775436  Dram Type= 6, Freq= 0, CH_0, rank 0

 2658 16:50:51.778842  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2659 16:50:51.782320  ==

 2660 16:50:51.782410  

 2661 16:50:51.782477  

 2662 16:50:51.782536  	TX Vref Scan disable

 2663 16:50:51.785593   == TX Byte 0 ==

 2664 16:50:51.788972  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2665 16:50:51.792025  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2666 16:50:51.795551   == TX Byte 1 ==

 2667 16:50:51.798889  Update DQ  dly =849 (3 ,2, 17)  DQ  OEN =(2 ,7)

 2668 16:50:51.802029  Update DQM dly =849 (3 ,2, 17)  DQM OEN =(2 ,7)

 2669 16:50:51.805339  

 2670 16:50:51.805422  [DATLAT]

 2671 16:50:51.805508  Freq=1200, CH0 RK0

 2672 16:50:51.805589  

 2673 16:50:51.808522  DATLAT Default: 0xd

 2674 16:50:51.808607  0, 0xFFFF, sum = 0

 2675 16:50:51.811793  1, 0xFFFF, sum = 0

 2676 16:50:51.815685  2, 0xFFFF, sum = 0

 2677 16:50:51.815771  3, 0xFFFF, sum = 0

 2678 16:50:51.818637  4, 0xFFFF, sum = 0

 2679 16:50:51.818723  5, 0xFFFF, sum = 0

 2680 16:50:51.822037  6, 0xFFFF, sum = 0

 2681 16:50:51.822123  7, 0xFFFF, sum = 0

 2682 16:50:51.825252  8, 0xFFFF, sum = 0

 2683 16:50:51.825338  9, 0xFFFF, sum = 0

 2684 16:50:51.828407  10, 0xFFFF, sum = 0

 2685 16:50:51.828494  11, 0xFFFF, sum = 0

 2686 16:50:51.832159  12, 0x0, sum = 1

 2687 16:50:51.832246  13, 0x0, sum = 2

 2688 16:50:51.835414  14, 0x0, sum = 3

 2689 16:50:51.835500  15, 0x0, sum = 4

 2690 16:50:51.835587  best_step = 13

 2691 16:50:51.838575  

 2692 16:50:51.838659  ==

 2693 16:50:51.841718  Dram Type= 6, Freq= 0, CH_0, rank 0

 2694 16:50:51.845359  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2695 16:50:51.845445  ==

 2696 16:50:51.845530  RX Vref Scan: 1

 2697 16:50:51.845611  

 2698 16:50:51.848664  Set Vref Range= 32 -> 127

 2699 16:50:51.848749  

 2700 16:50:51.851898  RX Vref 32 -> 127, step: 1

 2701 16:50:51.851983  

 2702 16:50:51.855194  RX Delay -13 -> 252, step: 4

 2703 16:50:51.855279  

 2704 16:50:51.858400  Set Vref, RX VrefLevel [Byte0]: 32

 2705 16:50:51.861673                           [Byte1]: 32

 2706 16:50:51.861758  

 2707 16:50:51.864874  Set Vref, RX VrefLevel [Byte0]: 33

 2708 16:50:51.868133                           [Byte1]: 33

 2709 16:50:51.871618  

 2710 16:50:51.875268  Set Vref, RX VrefLevel [Byte0]: 34

 2711 16:50:51.875353                           [Byte1]: 34

 2712 16:50:51.879638  

 2713 16:50:51.879723  Set Vref, RX VrefLevel [Byte0]: 35

 2714 16:50:51.883258                           [Byte1]: 35

 2715 16:50:51.887651  

 2716 16:50:51.887735  Set Vref, RX VrefLevel [Byte0]: 36

 2717 16:50:51.891470                           [Byte1]: 36

 2718 16:50:51.895405  

 2719 16:50:51.895491  Set Vref, RX VrefLevel [Byte0]: 37

 2720 16:50:51.898932                           [Byte1]: 37

 2721 16:50:51.903506  

 2722 16:50:51.903594  Set Vref, RX VrefLevel [Byte0]: 38

 2723 16:50:51.906704                           [Byte1]: 38

 2724 16:50:51.911348  

 2725 16:50:51.911433  Set Vref, RX VrefLevel [Byte0]: 39

 2726 16:50:51.914606                           [Byte1]: 39

 2727 16:50:51.919465  

 2728 16:50:51.919550  Set Vref, RX VrefLevel [Byte0]: 40

 2729 16:50:51.922673                           [Byte1]: 40

 2730 16:50:51.926943  

 2731 16:50:51.927028  Set Vref, RX VrefLevel [Byte0]: 41

 2732 16:50:51.930604                           [Byte1]: 41

 2733 16:50:51.935252  

 2734 16:50:51.935337  Set Vref, RX VrefLevel [Byte0]: 42

 2735 16:50:51.938385                           [Byte1]: 42

 2736 16:50:51.943079  

 2737 16:50:51.943164  Set Vref, RX VrefLevel [Byte0]: 43

 2738 16:50:51.946107                           [Byte1]: 43

 2739 16:50:51.950613  

 2740 16:50:51.950698  Set Vref, RX VrefLevel [Byte0]: 44

 2741 16:50:51.953896                           [Byte1]: 44

 2742 16:50:51.958647  

 2743 16:50:51.958732  Set Vref, RX VrefLevel [Byte0]: 45

 2744 16:50:51.962126                           [Byte1]: 45

 2745 16:50:51.966888  

 2746 16:50:51.966973  Set Vref, RX VrefLevel [Byte0]: 46

 2747 16:50:51.969972                           [Byte1]: 46

 2748 16:50:51.974336  

 2749 16:50:51.974458  Set Vref, RX VrefLevel [Byte0]: 47

 2750 16:50:51.977801                           [Byte1]: 47

 2751 16:50:51.982184  

 2752 16:50:51.982268  Set Vref, RX VrefLevel [Byte0]: 48

 2753 16:50:51.985459                           [Byte1]: 48

 2754 16:50:51.989983  

 2755 16:50:51.990068  Set Vref, RX VrefLevel [Byte0]: 49

 2756 16:50:51.993540                           [Byte1]: 49

 2757 16:50:51.998306  

 2758 16:50:51.998422  Set Vref, RX VrefLevel [Byte0]: 50

 2759 16:50:52.001320                           [Byte1]: 50

 2760 16:50:52.005986  

 2761 16:50:52.006060  Set Vref, RX VrefLevel [Byte0]: 51

 2762 16:50:52.009137                           [Byte1]: 51

 2763 16:50:52.013706  

 2764 16:50:52.013780  Set Vref, RX VrefLevel [Byte0]: 52

 2765 16:50:52.017293                           [Byte1]: 52

 2766 16:50:52.021750  

 2767 16:50:52.021823  Set Vref, RX VrefLevel [Byte0]: 53

 2768 16:50:52.024965                           [Byte1]: 53

 2769 16:50:52.029479  

 2770 16:50:52.029552  Set Vref, RX VrefLevel [Byte0]: 54

 2771 16:50:52.033090                           [Byte1]: 54

 2772 16:50:52.037263  

 2773 16:50:52.037338  Set Vref, RX VrefLevel [Byte0]: 55

 2774 16:50:52.041007                           [Byte1]: 55

 2775 16:50:52.045502  

 2776 16:50:52.045594  Set Vref, RX VrefLevel [Byte0]: 56

 2777 16:50:52.086791                           [Byte1]: 56

 2778 16:50:52.086962  

 2779 16:50:52.087060  Set Vref, RX VrefLevel [Byte0]: 57

 2780 16:50:52.087183                           [Byte1]: 57

 2781 16:50:52.087271  

 2782 16:50:52.087389  Set Vref, RX VrefLevel [Byte0]: 58

 2783 16:50:52.087477                           [Byte1]: 58

 2784 16:50:52.087562  

 2785 16:50:52.087679  Set Vref, RX VrefLevel [Byte0]: 59

 2786 16:50:52.087763                           [Byte1]: 59

 2787 16:50:52.087846  

 2788 16:50:52.087934  Set Vref, RX VrefLevel [Byte0]: 60

 2789 16:50:52.088002                           [Byte1]: 60

 2790 16:50:52.088057  

 2791 16:50:52.088138  Set Vref, RX VrefLevel [Byte0]: 61

 2792 16:50:52.088377                           [Byte1]: 61

 2793 16:50:52.092769  

 2794 16:50:52.092872  Set Vref, RX VrefLevel [Byte0]: 62

 2795 16:50:52.096148                           [Byte1]: 62

 2796 16:50:52.100897  

 2797 16:50:52.100981  Set Vref, RX VrefLevel [Byte0]: 63

 2798 16:50:52.104412                           [Byte1]: 63

 2799 16:50:52.108278  

 2800 16:50:52.108395  Set Vref, RX VrefLevel [Byte0]: 64

 2801 16:50:52.111651                           [Byte1]: 64

 2802 16:50:52.116274  

 2803 16:50:52.116395  Set Vref, RX VrefLevel [Byte0]: 65

 2804 16:50:52.119505                           [Byte1]: 65

 2805 16:50:52.124116  

 2806 16:50:52.124199  Set Vref, RX VrefLevel [Byte0]: 66

 2807 16:50:52.127443                           [Byte1]: 66

 2808 16:50:52.132016  

 2809 16:50:52.132121  Set Vref, RX VrefLevel [Byte0]: 67

 2810 16:50:52.135583                           [Byte1]: 67

 2811 16:50:52.140214  

 2812 16:50:52.140297  Set Vref, RX VrefLevel [Byte0]: 68

 2813 16:50:52.143531                           [Byte1]: 68

 2814 16:50:52.148010  

 2815 16:50:52.148092  Set Vref, RX VrefLevel [Byte0]: 69

 2816 16:50:52.151193                           [Byte1]: 69

 2817 16:50:52.156121  

 2818 16:50:52.156204  Set Vref, RX VrefLevel [Byte0]: 70

 2819 16:50:52.159332                           [Byte1]: 70

 2820 16:50:52.163921  

 2821 16:50:52.164004  Final RX Vref Byte 0 = 60 to rank0

 2822 16:50:52.167198  Final RX Vref Byte 1 = 49 to rank0

 2823 16:50:52.170443  Final RX Vref Byte 0 = 60 to rank1

 2824 16:50:52.173487  Final RX Vref Byte 1 = 49 to rank1==

 2825 16:50:52.177247  Dram Type= 6, Freq= 0, CH_0, rank 0

 2826 16:50:52.183732  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2827 16:50:52.183821  ==

 2828 16:50:52.183888  DQS Delay:

 2829 16:50:52.183949  DQS0 = 0, DQS1 = 0

 2830 16:50:52.186764  DQM Delay:

 2831 16:50:52.186847  DQM0 = 123, DQM1 = 109

 2832 16:50:52.190417  DQ Delay:

 2833 16:50:52.193792  DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120

 2834 16:50:52.196727  DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128

 2835 16:50:52.200367  DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106

 2836 16:50:52.203704  DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116

 2837 16:50:52.203787  

 2838 16:50:52.203852  

 2839 16:50:52.213656  [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps

 2840 16:50:52.213747  CH0 RK0: MR19=404, MR18=804

 2841 16:50:52.220146  CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26

 2842 16:50:52.220232  

 2843 16:50:52.223595  ----->DramcWriteLeveling(PI) begin...

 2844 16:50:52.223680  ==

 2845 16:50:52.226948  Dram Type= 6, Freq= 0, CH_0, rank 1

 2846 16:50:52.230042  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2847 16:50:52.233319  ==

 2848 16:50:52.233402  Write leveling (Byte 0): 35 => 35

 2849 16:50:52.236994  Write leveling (Byte 1): 30 => 30

 2850 16:50:52.240027  DramcWriteLeveling(PI) end<-----

 2851 16:50:52.240110  

 2852 16:50:52.240175  ==

 2853 16:50:52.243253  Dram Type= 6, Freq= 0, CH_0, rank 1

 2854 16:50:52.249968  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2855 16:50:52.250051  ==

 2856 16:50:52.250117  [Gating] SW mode calibration

 2857 16:50:52.259920  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2858 16:50:52.263580  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2859 16:50:52.270095   0 15  0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)

 2860 16:50:52.273379   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2861 16:50:52.276704   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2862 16:50:52.280015   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2863 16:50:52.286584   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2864 16:50:52.289780   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2865 16:50:52.293081   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2866 16:50:52.300132   0 15 28 | B1->B0 | 3232 2d2d | 0 1 | (0 0) (1 0)

 2867 16:50:52.303279   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2868 16:50:52.306431   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2869 16:50:52.313227   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2870 16:50:52.316555   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2871 16:50:52.319913   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2872 16:50:52.326308   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2873 16:50:52.329871   1  0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 2874 16:50:52.333084   1  0 28 | B1->B0 | 3838 4343 | 0 1 | (0 0) (0 0)

 2875 16:50:52.339880   1  1  0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 2876 16:50:52.343084   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2877 16:50:52.346453   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2878 16:50:52.353317   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2879 16:50:52.356625   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2880 16:50:52.359797   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2881 16:50:52.366631   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2882 16:50:52.369778   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2883 16:50:52.373031   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 2884 16:50:52.379898   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2885 16:50:52.382921   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2886 16:50:52.386035   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2887 16:50:52.392919   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2888 16:50:52.396163   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2889 16:50:52.399725   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2890 16:50:52.406424   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2891 16:50:52.409445   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2892 16:50:52.412925   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2893 16:50:52.419682   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2894 16:50:52.422821   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2895 16:50:52.426162   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2896 16:50:52.429458   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2897 16:50:52.435974   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2898 16:50:52.439124   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2899 16:50:52.442782   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2900 16:50:52.445937  Total UI for P1: 0, mck2ui 16

 2901 16:50:52.449530  best dqsien dly found for B0: ( 1,  3, 26)

 2902 16:50:52.452732  Total UI for P1: 0, mck2ui 16

 2903 16:50:52.455993  best dqsien dly found for B1: ( 1,  3, 28)

 2904 16:50:52.459252  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2905 16:50:52.462385  best DQS1 dly(MCK, UI, PI) = (1, 3, 28)

 2906 16:50:52.465573  

 2907 16:50:52.469233  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2908 16:50:52.472441  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2909 16:50:52.475769  [Gating] SW calibration Done

 2910 16:50:52.475855  ==

 2911 16:50:52.478876  Dram Type= 6, Freq= 0, CH_0, rank 1

 2912 16:50:52.482233  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2913 16:50:52.482324  ==

 2914 16:50:52.485412  RX Vref Scan: 0

 2915 16:50:52.485512  

 2916 16:50:52.485610  RX Vref 0 -> 0, step: 1

 2917 16:50:52.485688  

 2918 16:50:52.489218  RX Delay -40 -> 252, step: 8

 2919 16:50:52.492439  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2920 16:50:52.495640  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2921 16:50:52.502125  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2922 16:50:52.505895  iDelay=200, Bit 3, Center 115 (48 ~ 183) 136

 2923 16:50:52.508687  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2924 16:50:52.512121  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2925 16:50:52.515722  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2926 16:50:52.523014  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2927 16:50:52.525353  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2928 16:50:52.529182  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2929 16:50:52.532304  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 2930 16:50:52.535345  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2931 16:50:52.542241  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2932 16:50:52.545365  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2933 16:50:52.548740  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2934 16:50:52.552026  iDelay=200, Bit 15, Center 111 (48 ~ 175) 128

 2935 16:50:52.552127  ==

 2936 16:50:52.555402  Dram Type= 6, Freq= 0, CH_0, rank 1

 2937 16:50:52.562022  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2938 16:50:52.562132  ==

 2939 16:50:52.562198  DQS Delay:

 2940 16:50:52.562258  DQS0 = 0, DQS1 = 0

 2941 16:50:52.565554  DQM Delay:

 2942 16:50:52.565655  DQM0 = 120, DQM1 = 108

 2943 16:50:52.568690  DQ Delay:

 2944 16:50:52.571816  DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115

 2945 16:50:52.575570  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 2946 16:50:52.578620  DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107

 2947 16:50:52.582294  DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111

 2948 16:50:52.582425  

 2949 16:50:52.582494  

 2950 16:50:52.582554  ==

 2951 16:50:52.585526  Dram Type= 6, Freq= 0, CH_0, rank 1

 2952 16:50:52.588731  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2953 16:50:52.588833  ==

 2954 16:50:52.588930  

 2955 16:50:52.591973  

 2956 16:50:52.592055  	TX Vref Scan disable

 2957 16:50:52.595582   == TX Byte 0 ==

 2958 16:50:52.598827  Update DQ  dly =854 (3 ,2, 22)  DQ  OEN =(2 ,7)

 2959 16:50:52.602036  Update DQM dly =854 (3 ,2, 22)  DQM OEN =(2 ,7)

 2960 16:50:52.605243   == TX Byte 1 ==

 2961 16:50:52.608490  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2962 16:50:52.612164  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2963 16:50:52.612249  ==

 2964 16:50:52.615390  Dram Type= 6, Freq= 0, CH_0, rank 1

 2965 16:50:52.621688  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2966 16:50:52.621774  ==

 2967 16:50:52.633143  TX Vref=22, minBit 0, minWin=24, winSum=406

 2968 16:50:52.636429  TX Vref=24, minBit 0, minWin=24, winSum=410

 2969 16:50:52.639629  TX Vref=26, minBit 1, minWin=25, winSum=418

 2970 16:50:52.643008  TX Vref=28, minBit 1, minWin=25, winSum=417

 2971 16:50:52.646414  TX Vref=30, minBit 1, minWin=25, winSum=419

 2972 16:50:52.649626  TX Vref=32, minBit 5, minWin=25, winSum=420

 2973 16:50:52.656454  [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 32

 2974 16:50:52.656546  

 2975 16:50:52.659600  Final TX Range 1 Vref 32

 2976 16:50:52.659678  

 2977 16:50:52.659749  ==

 2978 16:50:52.663225  Dram Type= 6, Freq= 0, CH_0, rank 1

 2979 16:50:52.666061  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2980 16:50:52.666171  ==

 2981 16:50:52.666257  

 2982 16:50:52.669766  

 2983 16:50:52.669851  	TX Vref Scan disable

 2984 16:50:52.673008   == TX Byte 0 ==

 2985 16:50:52.676107  Update DQ  dly =854 (3 ,2, 22)  DQ  OEN =(2 ,7)

 2986 16:50:52.679759  Update DQM dly =854 (3 ,2, 22)  DQM OEN =(2 ,7)

 2987 16:50:52.682881   == TX Byte 1 ==

 2988 16:50:52.686146  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2989 16:50:52.689870  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2990 16:50:52.689956  

 2991 16:50:52.693203  [DATLAT]

 2992 16:50:52.693282  Freq=1200, CH0 RK1

 2993 16:50:52.693347  

 2994 16:50:52.696390  DATLAT Default: 0xd

 2995 16:50:52.696536  0, 0xFFFF, sum = 0

 2996 16:50:52.699711  1, 0xFFFF, sum = 0

 2997 16:50:52.699809  2, 0xFFFF, sum = 0

 2998 16:50:52.702969  3, 0xFFFF, sum = 0

 2999 16:50:52.703055  4, 0xFFFF, sum = 0

 3000 16:50:52.706718  5, 0xFFFF, sum = 0

 3001 16:50:52.706799  6, 0xFFFF, sum = 0

 3002 16:50:52.709773  7, 0xFFFF, sum = 0

 3003 16:50:52.713085  8, 0xFFFF, sum = 0

 3004 16:50:52.713171  9, 0xFFFF, sum = 0

 3005 16:50:52.716297  10, 0xFFFF, sum = 0

 3006 16:50:52.716380  11, 0xFFFF, sum = 0

 3007 16:50:52.719759  12, 0x0, sum = 1

 3008 16:50:52.719843  13, 0x0, sum = 2

 3009 16:50:52.722804  14, 0x0, sum = 3

 3010 16:50:52.722876  15, 0x0, sum = 4

 3011 16:50:52.722946  best_step = 13

 3012 16:50:52.723006  

 3013 16:50:52.726176  ==

 3014 16:50:52.729733  Dram Type= 6, Freq= 0, CH_0, rank 1

 3015 16:50:52.732962  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3016 16:50:52.733038  ==

 3017 16:50:52.733103  RX Vref Scan: 0

 3018 16:50:52.733164  

 3019 16:50:52.736065  RX Vref 0 -> 0, step: 1

 3020 16:50:52.736142  

 3021 16:50:52.739340  RX Delay -21 -> 252, step: 4

 3022 16:50:52.743097  iDelay=199, Bit 0, Center 118 (51 ~ 186) 136

 3023 16:50:52.749228  iDelay=199, Bit 1, Center 122 (55 ~ 190) 136

 3024 16:50:52.752673  iDelay=199, Bit 2, Center 118 (51 ~ 186) 136

 3025 16:50:52.755857  iDelay=199, Bit 3, Center 114 (51 ~ 178) 128

 3026 16:50:52.759279  iDelay=199, Bit 4, Center 120 (55 ~ 186) 132

 3027 16:50:52.762559  iDelay=199, Bit 5, Center 114 (51 ~ 178) 128

 3028 16:50:52.769201  iDelay=199, Bit 6, Center 128 (59 ~ 198) 140

 3029 16:50:52.772474  iDelay=199, Bit 7, Center 126 (59 ~ 194) 136

 3030 16:50:52.776268  iDelay=199, Bit 8, Center 98 (35 ~ 162) 128

 3031 16:50:52.779374  iDelay=199, Bit 9, Center 94 (31 ~ 158) 128

 3032 16:50:52.782575  iDelay=199, Bit 10, Center 110 (47 ~ 174) 128

 3033 16:50:52.789102  iDelay=199, Bit 11, Center 106 (43 ~ 170) 128

 3034 16:50:52.792358  iDelay=199, Bit 12, Center 114 (51 ~ 178) 128

 3035 16:50:52.795921  iDelay=199, Bit 13, Center 110 (47 ~ 174) 128

 3036 16:50:52.799110  iDelay=199, Bit 14, Center 118 (55 ~ 182) 128

 3037 16:50:52.802317  iDelay=199, Bit 15, Center 114 (51 ~ 178) 128

 3038 16:50:52.805946  ==

 3039 16:50:52.806028  Dram Type= 6, Freq= 0, CH_0, rank 1

 3040 16:50:52.812440  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3041 16:50:52.812518  ==

 3042 16:50:52.812591  DQS Delay:

 3043 16:50:52.815738  DQS0 = 0, DQS1 = 0

 3044 16:50:52.815810  DQM Delay:

 3045 16:50:52.819086  DQM0 = 120, DQM1 = 108

 3046 16:50:52.819165  DQ Delay:

 3047 16:50:52.822203  DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114

 3048 16:50:52.825383  DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =126

 3049 16:50:52.828969  DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106

 3050 16:50:52.832379  DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114

 3051 16:50:52.832461  

 3052 16:50:52.832532  

 3053 16:50:52.842467  [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps

 3054 16:50:52.842562  CH0 RK1: MR19=403, MR18=10F7

 3055 16:50:52.849048  CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26

 3056 16:50:52.852340  [RxdqsGatingPostProcess] freq 1200

 3057 16:50:52.858800  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3058 16:50:52.862016  best DQS0 dly(2T, 0.5T) = (0, 11)

 3059 16:50:52.865682  best DQS1 dly(2T, 0.5T) = (0, 12)

 3060 16:50:52.868703  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3061 16:50:52.872050  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3062 16:50:52.875702  best DQS0 dly(2T, 0.5T) = (0, 11)

 3063 16:50:52.878942  best DQS1 dly(2T, 0.5T) = (0, 11)

 3064 16:50:52.882108  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3065 16:50:52.882219  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3066 16:50:52.885625  Pre-setting of DQS Precalculation

 3067 16:50:52.892082  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3068 16:50:52.892167  ==

 3069 16:50:52.895348  Dram Type= 6, Freq= 0, CH_1, rank 0

 3070 16:50:52.898636  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3071 16:50:52.898729  ==

 3072 16:50:52.905153  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3073 16:50:52.911800  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35

 3074 16:50:52.919238  [CA 0] Center 37 (7~68) winsize 62

 3075 16:50:52.922573  [CA 1] Center 37 (7~68) winsize 62

 3076 16:50:52.925647  [CA 2] Center 35 (5~65) winsize 61

 3077 16:50:52.929336  [CA 3] Center 34 (4~65) winsize 62

 3078 16:50:52.932558  [CA 4] Center 34 (4~64) winsize 61

 3079 16:50:52.935608  [CA 5] Center 33 (3~64) winsize 62

 3080 16:50:52.935693  

 3081 16:50:52.939026  [CmdBusTrainingLP45] Vref(ca) range 1: 31

 3082 16:50:52.939111  

 3083 16:50:52.942265  [CATrainingPosCal] consider 1 rank data

 3084 16:50:52.945499  u2DelayCellTimex100 = 270/100 ps

 3085 16:50:52.948972  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3086 16:50:52.955432  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3087 16:50:52.958779  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3088 16:50:52.961976  CA3 delay=34 (4~65),Diff = 1 PI (4 cell)

 3089 16:50:52.965600  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3090 16:50:52.968925  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3091 16:50:52.969032  

 3092 16:50:52.972127  CA PerBit enable=1, Macro0, CA PI delay=33

 3093 16:50:52.972211  

 3094 16:50:52.975631  [CBTSetCACLKResult] CA Dly = 33

 3095 16:50:52.975716  CS Dly: 5 (0~36)

 3096 16:50:52.978896  ==

 3097 16:50:52.982110  Dram Type= 6, Freq= 0, CH_1, rank 1

 3098 16:50:52.985281  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3099 16:50:52.985367  ==

 3100 16:50:52.992034  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3101 16:50:52.995253  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3102 16:50:53.005047  [CA 0] Center 38 (8~68) winsize 61

 3103 16:50:53.008228  [CA 1] Center 38 (7~69) winsize 63

 3104 16:50:53.011464  [CA 2] Center 35 (5~66) winsize 62

 3105 16:50:53.014700  [CA 3] Center 34 (4~65) winsize 62

 3106 16:50:53.018470  [CA 4] Center 35 (5~65) winsize 61

 3107 16:50:53.021640  [CA 5] Center 34 (4~64) winsize 61

 3108 16:50:53.021724  

 3109 16:50:53.024801  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3110 16:50:53.024886  

 3111 16:50:53.028092  [CATrainingPosCal] consider 2 rank data

 3112 16:50:53.031274  u2DelayCellTimex100 = 270/100 ps

 3113 16:50:53.034578  CA0 delay=38 (8~68),Diff = 4 PI (19 cell)

 3114 16:50:53.041525  CA1 delay=37 (7~68),Diff = 3 PI (14 cell)

 3115 16:50:53.044879  CA2 delay=35 (5~65),Diff = 1 PI (4 cell)

 3116 16:50:53.048132  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 3117 16:50:53.051469  CA4 delay=34 (5~64),Diff = 0 PI (0 cell)

 3118 16:50:53.054424  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3119 16:50:53.054507  

 3120 16:50:53.058023  CA PerBit enable=1, Macro0, CA PI delay=34

 3121 16:50:53.058107  

 3122 16:50:53.061404  [CBTSetCACLKResult] CA Dly = 34

 3123 16:50:53.061488  CS Dly: 6 (0~39)

 3124 16:50:53.064541  

 3125 16:50:53.067937  ----->DramcWriteLeveling(PI) begin...

 3126 16:50:53.068023  ==

 3127 16:50:53.071110  Dram Type= 6, Freq= 0, CH_1, rank 0

 3128 16:50:53.074255  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3129 16:50:53.074339  ==

 3130 16:50:53.078023  Write leveling (Byte 0): 25 => 25

 3131 16:50:53.081374  Write leveling (Byte 1): 27 => 27

 3132 16:50:53.084720  DramcWriteLeveling(PI) end<-----

 3133 16:50:53.084803  

 3134 16:50:53.084870  ==

 3135 16:50:53.087905  Dram Type= 6, Freq= 0, CH_1, rank 0

 3136 16:50:53.091563  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3137 16:50:53.091648  ==

 3138 16:50:53.094231  [Gating] SW mode calibration

 3139 16:50:53.101121  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3140 16:50:53.107925  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3141 16:50:53.111224   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3142 16:50:53.114314   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3143 16:50:53.121225   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3144 16:50:53.124400   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3145 16:50:53.128039   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3146 16:50:53.134443   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 3147 16:50:53.137674   0 15 24 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (1 0)

 3148 16:50:53.140806   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 3149 16:50:53.144339   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3150 16:50:53.150850   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3151 16:50:53.154169   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3152 16:50:53.157763   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3153 16:50:53.163999   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3154 16:50:53.167489   1  0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 3155 16:50:53.170719   1  0 24 | B1->B0 | 4040 4343 | 0 0 | (0 0) (0 0)

 3156 16:50:53.177470   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3157 16:50:53.180641   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3158 16:50:53.183945   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3159 16:50:53.190913   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3160 16:50:53.193882   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3161 16:50:53.197359   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3162 16:50:53.204093   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3163 16:50:53.207361   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3164 16:50:53.210637   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3165 16:50:53.217253   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3166 16:50:53.220435   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3167 16:50:53.223720   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3168 16:50:53.230577   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3169 16:50:53.233783   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3170 16:50:53.237114   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3171 16:50:53.243579   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3172 16:50:53.247297   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3173 16:50:53.250464   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3174 16:50:53.257357   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3175 16:50:53.260375   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3176 16:50:53.263513   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3177 16:50:53.270360   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3178 16:50:53.273633   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3179 16:50:53.276843   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3180 16:50:53.283748   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3181 16:50:53.283834  Total UI for P1: 0, mck2ui 16

 3182 16:50:53.290251  best dqsien dly found for B0: ( 1,  3, 22)

 3183 16:50:53.290420  Total UI for P1: 0, mck2ui 16

 3184 16:50:53.293191  best dqsien dly found for B1: ( 1,  3, 24)

 3185 16:50:53.300224  best DQS0 dly(MCK, UI, PI) = (1, 3, 22)

 3186 16:50:53.303617  best DQS1 dly(MCK, UI, PI) = (1, 3, 24)

 3187 16:50:53.303781  

 3188 16:50:53.306695  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3189 16:50:53.310102  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3190 16:50:53.313384  [Gating] SW calibration Done

 3191 16:50:53.313467  ==

 3192 16:50:53.316665  Dram Type= 6, Freq= 0, CH_1, rank 0

 3193 16:50:53.319918  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3194 16:50:53.320031  ==

 3195 16:50:53.323706  RX Vref Scan: 0

 3196 16:50:53.323789  

 3197 16:50:53.323854  RX Vref 0 -> 0, step: 1

 3198 16:50:53.323914  

 3199 16:50:53.326814  RX Delay -40 -> 252, step: 8

 3200 16:50:53.330086  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3201 16:50:53.336487  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3202 16:50:53.339754  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3203 16:50:53.343054  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3204 16:50:53.346761  iDelay=200, Bit 4, Center 115 (48 ~ 183) 136

 3205 16:50:53.349876  iDelay=200, Bit 5, Center 127 (64 ~ 191) 128

 3206 16:50:53.353361  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3207 16:50:53.359864  iDelay=200, Bit 7, Center 119 (56 ~ 183) 128

 3208 16:50:53.363455  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3209 16:50:53.366720  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 3210 16:50:53.369768  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3211 16:50:53.373412  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3212 16:50:53.379778  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3213 16:50:53.383262  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3214 16:50:53.386612  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3215 16:50:53.389696  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 3216 16:50:53.389771  ==

 3217 16:50:53.393010  Dram Type= 6, Freq= 0, CH_1, rank 0

 3218 16:50:53.399827  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3219 16:50:53.399914  ==

 3220 16:50:53.399981  DQS Delay:

 3221 16:50:53.403406  DQS0 = 0, DQS1 = 0

 3222 16:50:53.403488  DQM Delay:

 3223 16:50:53.403553  DQM0 = 119, DQM1 = 112

 3224 16:50:53.406455  DQ Delay:

 3225 16:50:53.409672  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3226 16:50:53.413275  DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119

 3227 16:50:53.416637  DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107

 3228 16:50:53.419732  DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119

 3229 16:50:53.419814  

 3230 16:50:53.419880  

 3231 16:50:53.419940  ==

 3232 16:50:53.423061  Dram Type= 6, Freq= 0, CH_1, rank 0

 3233 16:50:53.426278  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3234 16:50:53.429559  ==

 3235 16:50:53.429642  

 3236 16:50:53.429708  

 3237 16:50:53.429769  	TX Vref Scan disable

 3238 16:50:53.433192   == TX Byte 0 ==

 3239 16:50:53.436357  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3240 16:50:53.439619  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3241 16:50:53.442922   == TX Byte 1 ==

 3242 16:50:53.446153  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3243 16:50:53.449559  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3244 16:50:53.452633  ==

 3245 16:50:53.456112  Dram Type= 6, Freq= 0, CH_1, rank 0

 3246 16:50:53.459310  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3247 16:50:53.459395  ==

 3248 16:50:53.470458  TX Vref=22, minBit 10, minWin=23, winSum=402

 3249 16:50:53.473712  TX Vref=24, minBit 11, minWin=24, winSum=408

 3250 16:50:53.476902  TX Vref=26, minBit 9, minWin=25, winSum=415

 3251 16:50:53.480168  TX Vref=28, minBit 10, minWin=25, winSum=423

 3252 16:50:53.483759  TX Vref=30, minBit 10, minWin=25, winSum=423

 3253 16:50:53.490221  TX Vref=32, minBit 3, minWin=26, winSum=426

 3254 16:50:53.493578  [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 32

 3255 16:50:53.493664  

 3256 16:50:53.496922  Final TX Range 1 Vref 32

 3257 16:50:53.497011  

 3258 16:50:53.497076  ==

 3259 16:50:53.500302  Dram Type= 6, Freq= 0, CH_1, rank 0

 3260 16:50:53.503422  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3261 16:50:53.506706  ==

 3262 16:50:53.506797  

 3263 16:50:53.506866  

 3264 16:50:53.506929  	TX Vref Scan disable

 3265 16:50:53.510175   == TX Byte 0 ==

 3266 16:50:53.513573  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3267 16:50:53.520269  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3268 16:50:53.520357   == TX Byte 1 ==

 3269 16:50:53.523416  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3270 16:50:53.530239  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3271 16:50:53.530318  

 3272 16:50:53.530407  [DATLAT]

 3273 16:50:53.530475  Freq=1200, CH1 RK0

 3274 16:50:53.530536  

 3275 16:50:53.533489  DATLAT Default: 0xd

 3276 16:50:53.536638  0, 0xFFFF, sum = 0

 3277 16:50:53.536728  1, 0xFFFF, sum = 0

 3278 16:50:53.540342  2, 0xFFFF, sum = 0

 3279 16:50:53.540416  3, 0xFFFF, sum = 0

 3280 16:50:53.543246  4, 0xFFFF, sum = 0

 3281 16:50:53.543319  5, 0xFFFF, sum = 0

 3282 16:50:53.546864  6, 0xFFFF, sum = 0

 3283 16:50:53.546935  7, 0xFFFF, sum = 0

 3284 16:50:53.550102  8, 0xFFFF, sum = 0

 3285 16:50:53.550175  9, 0xFFFF, sum = 0

 3286 16:50:53.553428  10, 0xFFFF, sum = 0

 3287 16:50:53.553501  11, 0xFFFF, sum = 0

 3288 16:50:53.556701  12, 0x0, sum = 1

 3289 16:50:53.556772  13, 0x0, sum = 2

 3290 16:50:53.560295  14, 0x0, sum = 3

 3291 16:50:53.560367  15, 0x0, sum = 4

 3292 16:50:53.563523  best_step = 13

 3293 16:50:53.563624  

 3294 16:50:53.563714  ==

 3295 16:50:53.566886  Dram Type= 6, Freq= 0, CH_1, rank 0

 3296 16:50:53.570000  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3297 16:50:53.570072  ==

 3298 16:50:53.570136  RX Vref Scan: 1

 3299 16:50:53.570195  

 3300 16:50:53.573412  Set Vref Range= 32 -> 127

 3301 16:50:53.573484  

 3302 16:50:53.576900  RX Vref 32 -> 127, step: 1

 3303 16:50:53.576968  

 3304 16:50:53.580056  RX Delay -13 -> 252, step: 4

 3305 16:50:53.580123  

 3306 16:50:53.583213  Set Vref, RX VrefLevel [Byte0]: 32

 3307 16:50:53.586501                           [Byte1]: 32

 3308 16:50:53.586570  

 3309 16:50:53.589883  Set Vref, RX VrefLevel [Byte0]: 33

 3310 16:50:53.593476                           [Byte1]: 33

 3311 16:50:53.596606  

 3312 16:50:53.596696  Set Vref, RX VrefLevel [Byte0]: 34

 3313 16:50:53.600183                           [Byte1]: 34

 3314 16:50:53.604698  

 3315 16:50:53.604795  Set Vref, RX VrefLevel [Byte0]: 35

 3316 16:50:53.608160                           [Byte1]: 35

 3317 16:50:53.612815  

 3318 16:50:53.612886  Set Vref, RX VrefLevel [Byte0]: 36

 3319 16:50:53.615869                           [Byte1]: 36

 3320 16:50:53.620511  

 3321 16:50:53.620614  Set Vref, RX VrefLevel [Byte0]: 37

 3322 16:50:53.623824                           [Byte1]: 37

 3323 16:50:53.628347  

 3324 16:50:53.628422  Set Vref, RX VrefLevel [Byte0]: 38

 3325 16:50:53.631815                           [Byte1]: 38

 3326 16:50:53.636028  

 3327 16:50:53.636098  Set Vref, RX VrefLevel [Byte0]: 39

 3328 16:50:53.639580                           [Byte1]: 39

 3329 16:50:53.644304  

 3330 16:50:53.644375  Set Vref, RX VrefLevel [Byte0]: 40

 3331 16:50:53.647472                           [Byte1]: 40

 3332 16:50:53.651779  

 3333 16:50:53.651848  Set Vref, RX VrefLevel [Byte0]: 41

 3334 16:50:53.655378                           [Byte1]: 41

 3335 16:50:53.660088  

 3336 16:50:53.660156  Set Vref, RX VrefLevel [Byte0]: 42

 3337 16:50:53.663342                           [Byte1]: 42

 3338 16:50:53.667589  

 3339 16:50:53.667663  Set Vref, RX VrefLevel [Byte0]: 43

 3340 16:50:53.671068                           [Byte1]: 43

 3341 16:50:53.675555  

 3342 16:50:53.675630  Set Vref, RX VrefLevel [Byte0]: 44

 3343 16:50:53.678837                           [Byte1]: 44

 3344 16:50:53.683485  

 3345 16:50:53.683567  Set Vref, RX VrefLevel [Byte0]: 45

 3346 16:50:53.686649                           [Byte1]: 45

 3347 16:50:53.691272  

 3348 16:50:53.694423  Set Vref, RX VrefLevel [Byte0]: 46

 3349 16:50:53.697672                           [Byte1]: 46

 3350 16:50:53.697754  

 3351 16:50:53.701378  Set Vref, RX VrefLevel [Byte0]: 47

 3352 16:50:53.704533                           [Byte1]: 47

 3353 16:50:53.704605  

 3354 16:50:53.707657  Set Vref, RX VrefLevel [Byte0]: 48

 3355 16:50:53.711421                           [Byte1]: 48

 3356 16:50:53.715113  

 3357 16:50:53.715183  Set Vref, RX VrefLevel [Byte0]: 49

 3358 16:50:53.718287                           [Byte1]: 49

 3359 16:50:53.722856  

 3360 16:50:53.722991  Set Vref, RX VrefLevel [Byte0]: 50

 3361 16:50:53.726296                           [Byte1]: 50

 3362 16:50:53.730757  

 3363 16:50:53.730833  Set Vref, RX VrefLevel [Byte0]: 51

 3364 16:50:53.734126                           [Byte1]: 51

 3365 16:50:53.738777  

 3366 16:50:53.738861  Set Vref, RX VrefLevel [Byte0]: 52

 3367 16:50:53.741925                           [Byte1]: 52

 3368 16:50:53.746618  

 3369 16:50:53.746691  Set Vref, RX VrefLevel [Byte0]: 53

 3370 16:50:53.749819                           [Byte1]: 53

 3371 16:50:53.754536  

 3372 16:50:53.754608  Set Vref, RX VrefLevel [Byte0]: 54

 3373 16:50:53.757870                           [Byte1]: 54

 3374 16:50:53.762323  

 3375 16:50:53.762446  Set Vref, RX VrefLevel [Byte0]: 55

 3376 16:50:53.766072                           [Byte1]: 55

 3377 16:50:53.770124  

 3378 16:50:53.770198  Set Vref, RX VrefLevel [Byte0]: 56

 3379 16:50:53.773515                           [Byte1]: 56

 3380 16:50:53.778138  

 3381 16:50:53.778212  Set Vref, RX VrefLevel [Byte0]: 57

 3382 16:50:53.781422                           [Byte1]: 57

 3383 16:50:53.786029  

 3384 16:50:53.786128  Set Vref, RX VrefLevel [Byte0]: 58

 3385 16:50:53.789241                           [Byte1]: 58

 3386 16:50:53.793845  

 3387 16:50:53.793917  Set Vref, RX VrefLevel [Byte0]: 59

 3388 16:50:53.797341                           [Byte1]: 59

 3389 16:50:53.802219  

 3390 16:50:53.802322  Set Vref, RX VrefLevel [Byte0]: 60

 3391 16:50:53.805267                           [Byte1]: 60

 3392 16:50:53.809818  

 3393 16:50:53.809891  Set Vref, RX VrefLevel [Byte0]: 61

 3394 16:50:53.813029                           [Byte1]: 61

 3395 16:50:53.817597  

 3396 16:50:53.817669  Set Vref, RX VrefLevel [Byte0]: 62

 3397 16:50:53.820758                           [Byte1]: 62

 3398 16:50:53.825319  

 3399 16:50:53.825392  Set Vref, RX VrefLevel [Byte0]: 63

 3400 16:50:53.828714                           [Byte1]: 63

 3401 16:50:53.833431  

 3402 16:50:53.833531  Set Vref, RX VrefLevel [Byte0]: 64

 3403 16:50:53.836551                           [Byte1]: 64

 3404 16:50:53.841155  

 3405 16:50:53.841228  Set Vref, RX VrefLevel [Byte0]: 65

 3406 16:50:53.844363                           [Byte1]: 65

 3407 16:50:53.849082  

 3408 16:50:53.849156  Set Vref, RX VrefLevel [Byte0]: 66

 3409 16:50:53.852678                           [Byte1]: 66

 3410 16:50:53.856841  

 3411 16:50:53.856912  Set Vref, RX VrefLevel [Byte0]: 67

 3412 16:50:53.860584                           [Byte1]: 67

 3413 16:50:53.864711  

 3414 16:50:53.864780  Set Vref, RX VrefLevel [Byte0]: 68

 3415 16:50:53.868389                           [Byte1]: 68

 3416 16:50:53.872833  

 3417 16:50:53.872934  Final RX Vref Byte 0 = 51 to rank0

 3418 16:50:53.876261  Final RX Vref Byte 1 = 52 to rank0

 3419 16:50:53.879607  Final RX Vref Byte 0 = 51 to rank1

 3420 16:50:53.882804  Final RX Vref Byte 1 = 52 to rank1==

 3421 16:50:53.886090  Dram Type= 6, Freq= 0, CH_1, rank 0

 3422 16:50:53.892529  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3423 16:50:53.892603  ==

 3424 16:50:53.892666  DQS Delay:

 3425 16:50:53.896119  DQS0 = 0, DQS1 = 0

 3426 16:50:53.896230  DQM Delay:

 3427 16:50:53.896322  DQM0 = 119, DQM1 = 112

 3428 16:50:53.899236  DQ Delay:

 3429 16:50:53.902802  DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118

 3430 16:50:53.906065  DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118

 3431 16:50:53.909338  DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106

 3432 16:50:53.912513  DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =118

 3433 16:50:53.912584  

 3434 16:50:53.912649  

 3435 16:50:53.922505  [DQSOSCAuto] RK0, (LSB)MR18= 0x115, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps

 3436 16:50:53.922616  CH1 RK0: MR19=404, MR18=115

 3437 16:50:53.929055  CH1_RK0: MR19=0x404, MR18=0x115, DQSOSC=401, MR23=63, INC=40, DEC=27

 3438 16:50:53.929151  

 3439 16:50:53.932587  ----->DramcWriteLeveling(PI) begin...

 3440 16:50:53.932662  ==

 3441 16:50:53.935791  Dram Type= 6, Freq= 0, CH_1, rank 1

 3442 16:50:53.939250  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3443 16:50:53.942691  ==

 3444 16:50:53.942766  Write leveling (Byte 0): 25 => 25

 3445 16:50:53.946063  Write leveling (Byte 1): 29 => 29

 3446 16:50:53.949116  DramcWriteLeveling(PI) end<-----

 3447 16:50:53.949206  

 3448 16:50:53.949273  ==

 3449 16:50:53.952773  Dram Type= 6, Freq= 0, CH_1, rank 1

 3450 16:50:53.959097  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3451 16:50:53.959181  ==

 3452 16:50:53.962400  [Gating] SW mode calibration

 3453 16:50:53.969362  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3454 16:50:53.972239  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3455 16:50:53.979088   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3456 16:50:53.982263   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3457 16:50:53.985464   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3458 16:50:53.992348   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3459 16:50:53.995703   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3460 16:50:53.999097   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 3461 16:50:54.005320   0 15 24 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 1)

 3462 16:50:54.008631   0 15 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (1 0)

 3463 16:50:54.012378   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3464 16:50:54.015466   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3465 16:50:54.022099   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3466 16:50:54.025257   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3467 16:50:54.031760   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3468 16:50:54.035246   1  0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 3469 16:50:54.038476   1  0 24 | B1->B0 | 3c3c 2b2b | 1 0 | (0 0) (1 1)

 3470 16:50:54.044975   1  0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)

 3471 16:50:54.048326   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3472 16:50:54.051594   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3473 16:50:54.055223   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3474 16:50:54.061735   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3475 16:50:54.064754   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3476 16:50:54.068363   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3477 16:50:54.074780   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3478 16:50:54.078239   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3479 16:50:54.081824   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3480 16:50:54.088242   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3481 16:50:54.091474   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3482 16:50:54.094641   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3483 16:50:54.101979   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3484 16:50:54.104713   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3485 16:50:54.107913   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3486 16:50:54.114474   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3487 16:50:54.117650   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3488 16:50:54.120922   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3489 16:50:54.127499   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3490 16:50:54.131174   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3491 16:50:54.134365   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3492 16:50:54.141017   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3493 16:50:54.144080   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3494 16:50:54.147639   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3495 16:50:54.150861  Total UI for P1: 0, mck2ui 16

 3496 16:50:54.153995  best dqsien dly found for B0: ( 1,  3, 24)

 3497 16:50:54.157277  Total UI for P1: 0, mck2ui 16

 3498 16:50:54.160998  best dqsien dly found for B1: ( 1,  3, 24)

 3499 16:50:54.164060  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 3500 16:50:54.170299  best DQS1 dly(MCK, UI, PI) = (1, 3, 24)

 3501 16:50:54.170419  

 3502 16:50:54.173915  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3503 16:50:54.177018  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3504 16:50:54.180569  [Gating] SW calibration Done

 3505 16:50:54.180654  ==

 3506 16:50:54.183850  Dram Type= 6, Freq= 0, CH_1, rank 1

 3507 16:50:54.186990  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3508 16:50:54.187075  ==

 3509 16:50:54.190358  RX Vref Scan: 0

 3510 16:50:54.190471  

 3511 16:50:54.190538  RX Vref 0 -> 0, step: 1

 3512 16:50:54.190600  

 3513 16:50:54.193669  RX Delay -40 -> 252, step: 8

 3514 16:50:54.196822  iDelay=200, Bit 0, Center 123 (64 ~ 183) 120

 3515 16:50:54.203473  iDelay=200, Bit 1, Center 111 (48 ~ 175) 128

 3516 16:50:54.206680  iDelay=200, Bit 2, Center 111 (48 ~ 175) 128

 3517 16:50:54.209969  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3518 16:50:54.213648  iDelay=200, Bit 4, Center 123 (56 ~ 191) 136

 3519 16:50:54.216925  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3520 16:50:54.223590  iDelay=200, Bit 6, Center 127 (64 ~ 191) 128

 3521 16:50:54.226856  iDelay=200, Bit 7, Center 115 (48 ~ 183) 136

 3522 16:50:54.229924  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3523 16:50:54.233458  iDelay=200, Bit 9, Center 103 (40 ~ 167) 128

 3524 16:50:54.236711  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3525 16:50:54.243091  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3526 16:50:54.246228  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3527 16:50:54.249859  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3528 16:50:54.252812  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3529 16:50:54.256442  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 3530 16:50:54.259668  ==

 3531 16:50:54.262879  Dram Type= 6, Freq= 0, CH_1, rank 1

 3532 16:50:54.266572  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3533 16:50:54.266656  ==

 3534 16:50:54.266723  DQS Delay:

 3535 16:50:54.269850  DQS0 = 0, DQS1 = 0

 3536 16:50:54.269933  DQM Delay:

 3537 16:50:54.272819  DQM0 = 120, DQM1 = 112

 3538 16:50:54.272902  DQ Delay:

 3539 16:50:54.276129  DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119

 3540 16:50:54.279569  DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115

 3541 16:50:54.282650  DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107

 3542 16:50:54.286304  DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119

 3543 16:50:54.286436  

 3544 16:50:54.286502  

 3545 16:50:54.286563  ==

 3546 16:50:54.289585  Dram Type= 6, Freq= 0, CH_1, rank 1

 3547 16:50:54.296286  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3548 16:50:54.296370  ==

 3549 16:50:54.296435  

 3550 16:50:54.296496  

 3551 16:50:54.296554  	TX Vref Scan disable

 3552 16:50:54.299846   == TX Byte 0 ==

 3553 16:50:54.303049  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3554 16:50:54.309548  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3555 16:50:54.309631   == TX Byte 1 ==

 3556 16:50:54.312765  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3557 16:50:54.319465  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3558 16:50:54.319548  ==

 3559 16:50:54.322603  Dram Type= 6, Freq= 0, CH_1, rank 1

 3560 16:50:54.325868  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3561 16:50:54.325952  ==

 3562 16:50:54.337537  TX Vref=22, minBit 1, minWin=25, winSum=417

 3563 16:50:54.340844  TX Vref=24, minBit 0, minWin=26, winSum=423

 3564 16:50:54.344078  TX Vref=26, minBit 2, minWin=26, winSum=425

 3565 16:50:54.347496  TX Vref=28, minBit 9, minWin=25, winSum=426

 3566 16:50:54.351105  TX Vref=30, minBit 9, minWin=25, winSum=428

 3567 16:50:54.357705  TX Vref=32, minBit 1, minWin=26, winSum=426

 3568 16:50:54.360832  [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 32

 3569 16:50:54.360916  

 3570 16:50:54.364093  Final TX Range 1 Vref 32

 3571 16:50:54.364177  

 3572 16:50:54.364243  ==

 3573 16:50:54.367734  Dram Type= 6, Freq= 0, CH_1, rank 1

 3574 16:50:54.370841  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3575 16:50:54.370928  ==

 3576 16:50:54.374152  

 3577 16:50:54.374235  

 3578 16:50:54.374300  	TX Vref Scan disable

 3579 16:50:54.377219   == TX Byte 0 ==

 3580 16:50:54.380575  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3581 16:50:54.387301  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3582 16:50:54.387383   == TX Byte 1 ==

 3583 16:50:54.390500  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3584 16:50:54.397256  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3585 16:50:54.397340  

 3586 16:50:54.397405  [DATLAT]

 3587 16:50:54.397467  Freq=1200, CH1 RK1

 3588 16:50:54.397526  

 3589 16:50:54.400592  DATLAT Default: 0xd

 3590 16:50:54.400679  0, 0xFFFF, sum = 0

 3591 16:50:54.403712  1, 0xFFFF, sum = 0

 3592 16:50:54.406958  2, 0xFFFF, sum = 0

 3593 16:50:54.407042  3, 0xFFFF, sum = 0

 3594 16:50:54.410562  4, 0xFFFF, sum = 0

 3595 16:50:54.410647  5, 0xFFFF, sum = 0

 3596 16:50:54.413712  6, 0xFFFF, sum = 0

 3597 16:50:54.413796  7, 0xFFFF, sum = 0

 3598 16:50:54.416982  8, 0xFFFF, sum = 0

 3599 16:50:54.417066  9, 0xFFFF, sum = 0

 3600 16:50:54.420235  10, 0xFFFF, sum = 0

 3601 16:50:54.420319  11, 0xFFFF, sum = 0

 3602 16:50:54.423702  12, 0x0, sum = 1

 3603 16:50:54.423786  13, 0x0, sum = 2

 3604 16:50:54.427270  14, 0x0, sum = 3

 3605 16:50:54.427355  15, 0x0, sum = 4

 3606 16:50:54.430068  best_step = 13

 3607 16:50:54.430151  

 3608 16:50:54.430216  ==

 3609 16:50:54.433720  Dram Type= 6, Freq= 0, CH_1, rank 1

 3610 16:50:54.437007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3611 16:50:54.437090  ==

 3612 16:50:54.437156  RX Vref Scan: 0

 3613 16:50:54.440030  

 3614 16:50:54.440112  RX Vref 0 -> 0, step: 1

 3615 16:50:54.440178  

 3616 16:50:54.443702  RX Delay -13 -> 252, step: 4

 3617 16:50:54.450029  iDelay=195, Bit 0, Center 124 (67 ~ 182) 116

 3618 16:50:54.453462  iDelay=195, Bit 1, Center 114 (55 ~ 174) 120

 3619 16:50:54.456769  iDelay=195, Bit 2, Center 108 (51 ~ 166) 116

 3620 16:50:54.459873  iDelay=195, Bit 3, Center 118 (59 ~ 178) 120

 3621 16:50:54.463241  iDelay=195, Bit 4, Center 122 (63 ~ 182) 120

 3622 16:50:54.469731  iDelay=195, Bit 5, Center 130 (67 ~ 194) 128

 3623 16:50:54.473448  iDelay=195, Bit 6, Center 126 (67 ~ 186) 120

 3624 16:50:54.476435  iDelay=195, Bit 7, Center 116 (55 ~ 178) 124

 3625 16:50:54.479843  iDelay=195, Bit 8, Center 100 (39 ~ 162) 124

 3626 16:50:54.483391  iDelay=195, Bit 9, Center 102 (39 ~ 166) 128

 3627 16:50:54.489824  iDelay=195, Bit 10, Center 112 (47 ~ 178) 132

 3628 16:50:54.493421  iDelay=195, Bit 11, Center 108 (43 ~ 174) 132

 3629 16:50:54.496463  iDelay=195, Bit 12, Center 122 (59 ~ 186) 128

 3630 16:50:54.499733  iDelay=195, Bit 13, Center 120 (59 ~ 182) 124

 3631 16:50:54.502809  iDelay=195, Bit 14, Center 122 (59 ~ 186) 128

 3632 16:50:54.509594  iDelay=195, Bit 15, Center 124 (59 ~ 190) 132

 3633 16:50:54.509678  ==

 3634 16:50:54.512710  Dram Type= 6, Freq= 0, CH_1, rank 1

 3635 16:50:54.516480  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3636 16:50:54.516567  ==

 3637 16:50:54.516633  DQS Delay:

 3638 16:50:54.519714  DQS0 = 0, DQS1 = 0

 3639 16:50:54.519797  DQM Delay:

 3640 16:50:54.522952  DQM0 = 119, DQM1 = 113

 3641 16:50:54.523035  DQ Delay:

 3642 16:50:54.526189  DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =118

 3643 16:50:54.529381  DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116

 3644 16:50:54.532679  DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108

 3645 16:50:54.539107  DQ12 =122, DQ13 =120, DQ14 =122, DQ15 =124

 3646 16:50:54.539191  

 3647 16:50:54.539256  

 3648 16:50:54.546089  [DQSOSCAuto] RK1, (LSB)MR18= 0x5e9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps

 3649 16:50:54.549242  CH1 RK1: MR19=403, MR18=5E9

 3650 16:50:54.555885  CH1_RK1: MR19=0x403, MR18=0x5E9, DQSOSC=408, MR23=63, INC=39, DEC=26

 3651 16:50:54.559047  [RxdqsGatingPostProcess] freq 1200

 3652 16:50:54.562219  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3653 16:50:54.565837  best DQS0 dly(2T, 0.5T) = (0, 11)

 3654 16:50:54.569198  best DQS1 dly(2T, 0.5T) = (0, 11)

 3655 16:50:54.572319  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3656 16:50:54.575638  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3657 16:50:54.578857  best DQS0 dly(2T, 0.5T) = (0, 11)

 3658 16:50:54.582125  best DQS1 dly(2T, 0.5T) = (0, 11)

 3659 16:50:54.585286  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3660 16:50:54.588704  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3661 16:50:54.591953  Pre-setting of DQS Precalculation

 3662 16:50:54.595298  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3663 16:50:54.605199  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3664 16:50:54.612045  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3665 16:50:54.612130  

 3666 16:50:54.612196  

 3667 16:50:54.615160  [Calibration Summary] 2400 Mbps

 3668 16:50:54.615243  CH 0, Rank 0

 3669 16:50:54.618419  SW Impedance     : PASS

 3670 16:50:54.618502  DUTY Scan        : NO K

 3671 16:50:54.621664  ZQ Calibration   : PASS

 3672 16:50:54.624926  Jitter Meter     : NO K

 3673 16:50:54.625009  CBT Training     : PASS

 3674 16:50:54.628200  Write leveling   : PASS

 3675 16:50:54.631458  RX DQS gating    : PASS

 3676 16:50:54.631541  RX DQ/DQS(RDDQC) : PASS

 3677 16:50:54.634713  TX DQ/DQS        : PASS

 3678 16:50:54.638026  RX DATLAT        : PASS

 3679 16:50:54.638129  RX DQ/DQS(Engine): PASS

 3680 16:50:54.641013  TX OE            : NO K

 3681 16:50:54.641096  All Pass.

 3682 16:50:54.641162  

 3683 16:50:54.644694  CH 0, Rank 1

 3684 16:50:54.644778  SW Impedance     : PASS

 3685 16:50:54.647739  DUTY Scan        : NO K

 3686 16:50:54.650956  ZQ Calibration   : PASS

 3687 16:50:54.651039  Jitter Meter     : NO K

 3688 16:50:54.654160  CBT Training     : PASS

 3689 16:50:54.657573  Write leveling   : PASS

 3690 16:50:54.657656  RX DQS gating    : PASS

 3691 16:50:54.660878  RX DQ/DQS(RDDQC) : PASS

 3692 16:50:54.664055  TX DQ/DQS        : PASS

 3693 16:50:54.664138  RX DATLAT        : PASS

 3694 16:50:54.667597  RX DQ/DQS(Engine): PASS

 3695 16:50:54.670630  TX OE            : NO K

 3696 16:50:54.670713  All Pass.

 3697 16:50:54.670779  

 3698 16:50:54.670840  CH 1, Rank 0

 3699 16:50:54.674165  SW Impedance     : PASS

 3700 16:50:54.677446  DUTY Scan        : NO K

 3701 16:50:54.677528  ZQ Calibration   : PASS

 3702 16:50:54.680721  Jitter Meter     : NO K

 3703 16:50:54.683931  CBT Training     : PASS

 3704 16:50:54.684015  Write leveling   : PASS

 3705 16:50:54.687252  RX DQS gating    : PASS

 3706 16:50:54.687335  RX DQ/DQS(RDDQC) : PASS

 3707 16:50:54.690479  TX DQ/DQS        : PASS

 3708 16:50:54.693623  RX DATLAT        : PASS

 3709 16:50:54.693705  RX DQ/DQS(Engine): PASS

 3710 16:50:54.697383  TX OE            : NO K

 3711 16:50:54.697467  All Pass.

 3712 16:50:54.697532  

 3713 16:50:54.700639  CH 1, Rank 1

 3714 16:50:54.700722  SW Impedance     : PASS

 3715 16:50:54.703709  DUTY Scan        : NO K

 3716 16:50:54.706915  ZQ Calibration   : PASS

 3717 16:50:54.706997  Jitter Meter     : NO K

 3718 16:50:54.710325  CBT Training     : PASS

 3719 16:50:54.713695  Write leveling   : PASS

 3720 16:50:54.713778  RX DQS gating    : PASS

 3721 16:50:54.716833  RX DQ/DQS(RDDQC) : PASS

 3722 16:50:54.720373  TX DQ/DQS        : PASS

 3723 16:50:54.720456  RX DATLAT        : PASS

 3724 16:50:54.723642  RX DQ/DQS(Engine): PASS

 3725 16:50:54.726901  TX OE            : NO K

 3726 16:50:54.726984  All Pass.

 3727 16:50:54.727050  

 3728 16:50:54.730119  DramC Write-DBI off

 3729 16:50:54.730201  	PER_BANK_REFRESH: Hybrid Mode

 3730 16:50:54.733346  TX_TRACKING: ON

 3731 16:50:54.740421  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3732 16:50:54.746595  [FAST_K] Save calibration result to emmc

 3733 16:50:54.750291  dramc_set_vcore_voltage set vcore to 650000

 3734 16:50:54.750382  Read voltage for 600, 5

 3735 16:50:54.753173  Vio18 = 0

 3736 16:50:54.753255  Vcore = 650000

 3737 16:50:54.753321  Vdram = 0

 3738 16:50:54.756366  Vddq = 0

 3739 16:50:54.756449  Vmddr = 0

 3740 16:50:54.759670  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3741 16:50:54.766449  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3742 16:50:54.770020  MEM_TYPE=3, freq_sel=19

 3743 16:50:54.773104  sv_algorithm_assistance_LP4_1600 

 3744 16:50:54.776258  ============ PULL DRAM RESETB DOWN ============

 3745 16:50:54.779761  ========== PULL DRAM RESETB DOWN end =========

 3746 16:50:54.786279  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3747 16:50:54.789506  =================================== 

 3748 16:50:54.789590  LPDDR4 DRAM CONFIGURATION

 3749 16:50:54.792738  =================================== 

 3750 16:50:54.796384  EX_ROW_EN[0]    = 0x0

 3751 16:50:54.796467  EX_ROW_EN[1]    = 0x0

 3752 16:50:54.799643  LP4Y_EN      = 0x0

 3753 16:50:54.799727  WORK_FSP     = 0x0

 3754 16:50:54.802902  WL           = 0x2

 3755 16:50:54.806601  RL           = 0x2

 3756 16:50:54.806715  BL           = 0x2

 3757 16:50:54.809757  RPST         = 0x0

 3758 16:50:54.809835  RD_PRE       = 0x0

 3759 16:50:54.813086  WR_PRE       = 0x1

 3760 16:50:54.813159  WR_PST       = 0x0

 3761 16:50:54.816059  DBI_WR       = 0x0

 3762 16:50:54.816151  DBI_RD       = 0x0

 3763 16:50:54.819631  OTF          = 0x1

 3764 16:50:54.822690  =================================== 

 3765 16:50:54.826176  =================================== 

 3766 16:50:54.826260  ANA top config

 3767 16:50:54.829487  =================================== 

 3768 16:50:54.832667  DLL_ASYNC_EN            =  0

 3769 16:50:54.835833  ALL_SLAVE_EN            =  1

 3770 16:50:54.835916  NEW_RANK_MODE           =  1

 3771 16:50:54.839078  DLL_IDLE_MODE           =  1

 3772 16:50:54.842468  LP45_APHY_COMB_EN       =  1

 3773 16:50:54.845963  TX_ODT_DIS              =  1

 3774 16:50:54.849229  NEW_8X_MODE             =  1

 3775 16:50:54.852503  =================================== 

 3776 16:50:54.855614  =================================== 

 3777 16:50:54.855698  data_rate                  = 1200

 3778 16:50:54.859200  CKR                        = 1

 3779 16:50:54.862454  DQ_P2S_RATIO               = 8

 3780 16:50:54.865690  =================================== 

 3781 16:50:54.869026  CA_P2S_RATIO               = 8

 3782 16:50:54.872119  DQ_CA_OPEN                 = 0

 3783 16:50:54.875800  DQ_SEMI_OPEN               = 0

 3784 16:50:54.875883  CA_SEMI_OPEN               = 0

 3785 16:50:54.879269  CA_FULL_RATE               = 0

 3786 16:50:54.882380  DQ_CKDIV4_EN               = 1

 3787 16:50:54.885566  CA_CKDIV4_EN               = 1

 3788 16:50:54.889138  CA_PREDIV_EN               = 0

 3789 16:50:54.892428  PH8_DLY                    = 0

 3790 16:50:54.892511  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3791 16:50:54.895648  DQ_AAMCK_DIV               = 4

 3792 16:50:54.898907  CA_AAMCK_DIV               = 4

 3793 16:50:54.902366  CA_ADMCK_DIV               = 4

 3794 16:50:54.905306  DQ_TRACK_CA_EN             = 0

 3795 16:50:54.908864  CA_PICK                    = 600

 3796 16:50:54.911896  CA_MCKIO                   = 600

 3797 16:50:54.911979  MCKIO_SEMI                 = 0

 3798 16:50:54.915542  PLL_FREQ                   = 2288

 3799 16:50:54.918721  DQ_UI_PI_RATIO             = 32

 3800 16:50:54.921876  CA_UI_PI_RATIO             = 0

 3801 16:50:54.925206  =================================== 

 3802 16:50:54.928525  =================================== 

 3803 16:50:54.932130  memory_type:LPDDR4         

 3804 16:50:54.932213  GP_NUM     : 10       

 3805 16:50:54.935429  SRAM_EN    : 1       

 3806 16:50:54.938585  MD32_EN    : 0       

 3807 16:50:54.941798  =================================== 

 3808 16:50:54.941881  [ANA_INIT] >>>>>>>>>>>>>> 

 3809 16:50:54.945092  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3810 16:50:54.948299  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3811 16:50:54.951576  =================================== 

 3812 16:50:54.955302  data_rate = 1200,PCW = 0X5800

 3813 16:50:54.958467  =================================== 

 3814 16:50:54.961528  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3815 16:50:54.968460  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3816 16:50:54.971628  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3817 16:50:54.978197  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3818 16:50:54.981399  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3819 16:50:54.984852  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3820 16:50:54.984934  [ANA_INIT] flow start 

 3821 16:50:54.988128  [ANA_INIT] PLL >>>>>>>> 

 3822 16:50:54.991275  [ANA_INIT] PLL <<<<<<<< 

 3823 16:50:54.994565  [ANA_INIT] MIDPI >>>>>>>> 

 3824 16:50:54.994647  [ANA_INIT] MIDPI <<<<<<<< 

 3825 16:50:54.998209  [ANA_INIT] DLL >>>>>>>> 

 3826 16:50:55.001426  [ANA_INIT] flow end 

 3827 16:50:55.004635  ============ LP4 DIFF to SE enter ============

 3828 16:50:55.008075  ============ LP4 DIFF to SE exit  ============

 3829 16:50:55.011148  [ANA_INIT] <<<<<<<<<<<<< 

 3830 16:50:55.014474  [Flow] Enable top DCM control >>>>> 

 3831 16:50:55.017516  [Flow] Enable top DCM control <<<<< 

 3832 16:50:55.021253  Enable DLL master slave shuffle 

 3833 16:50:55.024456  ============================================================== 

 3834 16:50:55.027655  Gating Mode config

 3835 16:50:55.034268  ============================================================== 

 3836 16:50:55.034409  Config description: 

 3837 16:50:55.044468  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3838 16:50:55.051151  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3839 16:50:55.054254  SELPH_MODE            0: By rank         1: By Phase 

 3840 16:50:55.060806  ============================================================== 

 3841 16:50:55.063840  GAT_TRACK_EN                 =  1

 3842 16:50:55.067472  RX_GATING_MODE               =  2

 3843 16:50:55.070752  RX_GATING_TRACK_MODE         =  2

 3844 16:50:55.073943  SELPH_MODE                   =  1

 3845 16:50:55.077225  PICG_EARLY_EN                =  1

 3846 16:50:55.080659  VALID_LAT_VALUE              =  1

 3847 16:50:55.083846  ============================================================== 

 3848 16:50:55.087063  Enter into Gating configuration >>>> 

 3849 16:50:55.090712  Exit from Gating configuration <<<< 

 3850 16:50:55.094016  Enter into  DVFS_PRE_config >>>>> 

 3851 16:50:55.107404  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3852 16:50:55.107488  Exit from  DVFS_PRE_config <<<<< 

 3853 16:50:55.110318  Enter into PICG configuration >>>> 

 3854 16:50:55.113695  Exit from PICG configuration <<<< 

 3855 16:50:55.116941  [RX_INPUT] configuration >>>>> 

 3856 16:50:55.120456  [RX_INPUT] configuration <<<<< 

 3857 16:50:55.126850  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3858 16:50:55.130296  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3859 16:50:55.137292  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3860 16:50:55.143436  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3861 16:50:55.150121  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3862 16:50:55.156690  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3863 16:50:55.159823  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3864 16:50:55.163080  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3865 16:50:55.166483  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3866 16:50:55.173001  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3867 16:50:55.176749  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3868 16:50:55.179612  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3869 16:50:55.183038  =================================== 

 3870 16:50:55.186156  LPDDR4 DRAM CONFIGURATION

 3871 16:50:55.189798  =================================== 

 3872 16:50:55.192897  EX_ROW_EN[0]    = 0x0

 3873 16:50:55.192979  EX_ROW_EN[1]    = 0x0

 3874 16:50:55.196162  LP4Y_EN      = 0x0

 3875 16:50:55.196244  WORK_FSP     = 0x0

 3876 16:50:55.199806  WL           = 0x2

 3877 16:50:55.199889  RL           = 0x2

 3878 16:50:55.202632  BL           = 0x2

 3879 16:50:55.202713  RPST         = 0x0

 3880 16:50:55.206273  RD_PRE       = 0x0

 3881 16:50:55.206413  WR_PRE       = 0x1

 3882 16:50:55.209584  WR_PST       = 0x0

 3883 16:50:55.209665  DBI_WR       = 0x0

 3884 16:50:55.212677  DBI_RD       = 0x0

 3885 16:50:55.212759  OTF          = 0x1

 3886 16:50:55.215972  =================================== 

 3887 16:50:55.223022  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3888 16:50:55.226499  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3889 16:50:55.229419  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3890 16:50:55.232575  =================================== 

 3891 16:50:55.236195  LPDDR4 DRAM CONFIGURATION

 3892 16:50:55.239754  =================================== 

 3893 16:50:55.242679  EX_ROW_EN[0]    = 0x10

 3894 16:50:55.242761  EX_ROW_EN[1]    = 0x0

 3895 16:50:55.245968  LP4Y_EN      = 0x0

 3896 16:50:55.246050  WORK_FSP     = 0x0

 3897 16:50:55.249299  WL           = 0x2

 3898 16:50:55.249380  RL           = 0x2

 3899 16:50:55.252561  BL           = 0x2

 3900 16:50:55.252642  RPST         = 0x0

 3901 16:50:55.255646  RD_PRE       = 0x0

 3902 16:50:55.255728  WR_PRE       = 0x1

 3903 16:50:55.259377  WR_PST       = 0x0

 3904 16:50:55.259459  DBI_WR       = 0x0

 3905 16:50:55.262619  DBI_RD       = 0x0

 3906 16:50:55.262701  OTF          = 0x1

 3907 16:50:55.265886  =================================== 

 3908 16:50:55.272235  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3909 16:50:55.277504  nWR fixed to 30

 3910 16:50:55.280407  [ModeRegInit_LP4] CH0 RK0

 3911 16:50:55.280489  [ModeRegInit_LP4] CH0 RK1

 3912 16:50:55.283988  [ModeRegInit_LP4] CH1 RK0

 3913 16:50:55.287173  [ModeRegInit_LP4] CH1 RK1

 3914 16:50:55.287255  match AC timing 17

 3915 16:50:55.294020  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3916 16:50:55.296891  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3917 16:50:55.300446  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3918 16:50:55.306918  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3919 16:50:55.310154  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3920 16:50:55.310236  ==

 3921 16:50:55.313436  Dram Type= 6, Freq= 0, CH_0, rank 0

 3922 16:50:55.316632  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3923 16:50:55.316714  ==

 3924 16:50:55.323499  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3925 16:50:55.329893  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3926 16:50:55.333227  [CA 0] Center 36 (5~67) winsize 63

 3927 16:50:55.336551  [CA 1] Center 36 (6~67) winsize 62

 3928 16:50:55.339757  [CA 2] Center 34 (4~65) winsize 62

 3929 16:50:55.343021  [CA 3] Center 34 (4~65) winsize 62

 3930 16:50:55.346387  [CA 4] Center 33 (3~64) winsize 62

 3931 16:50:55.349849  [CA 5] Center 33 (2~64) winsize 63

 3932 16:50:55.349931  

 3933 16:50:55.353226  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3934 16:50:55.353308  

 3935 16:50:55.356298  [CATrainingPosCal] consider 1 rank data

 3936 16:50:55.359947  u2DelayCellTimex100 = 270/100 ps

 3937 16:50:55.362839  CA0 delay=36 (5~67),Diff = 3 PI (28 cell)

 3938 16:50:55.366078  CA1 delay=36 (6~67),Diff = 3 PI (28 cell)

 3939 16:50:55.369382  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3940 16:50:55.376076  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 3941 16:50:55.379469  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 3942 16:50:55.382855  CA5 delay=33 (2~64),Diff = 0 PI (0 cell)

 3943 16:50:55.382937  

 3944 16:50:55.386302  CA PerBit enable=1, Macro0, CA PI delay=33

 3945 16:50:55.386434  

 3946 16:50:55.389492  [CBTSetCACLKResult] CA Dly = 33

 3947 16:50:55.389574  CS Dly: 5 (0~36)

 3948 16:50:55.389639  ==

 3949 16:50:55.392852  Dram Type= 6, Freq= 0, CH_0, rank 1

 3950 16:50:55.399147  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3951 16:50:55.399229  ==

 3952 16:50:55.402609  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3953 16:50:55.408997  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 3954 16:50:55.412726  [CA 0] Center 36 (6~67) winsize 62

 3955 16:50:55.415983  [CA 1] Center 36 (6~67) winsize 62

 3956 16:50:55.419202  [CA 2] Center 34 (4~65) winsize 62

 3957 16:50:55.422502  [CA 3] Center 34 (4~65) winsize 62

 3958 16:50:55.426331  [CA 4] Center 34 (3~65) winsize 63

 3959 16:50:55.429112  [CA 5] Center 33 (3~64) winsize 62

 3960 16:50:55.429194  

 3961 16:50:55.432329  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 3962 16:50:55.432412  

 3963 16:50:55.435710  [CATrainingPosCal] consider 2 rank data

 3964 16:50:55.438957  u2DelayCellTimex100 = 270/100 ps

 3965 16:50:55.442705  CA0 delay=36 (6~67),Diff = 3 PI (28 cell)

 3966 16:50:55.449172  CA1 delay=36 (6~67),Diff = 3 PI (28 cell)

 3967 16:50:55.452372  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3968 16:50:55.455575  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 3969 16:50:55.459192  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 3970 16:50:55.462716  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3971 16:50:55.462798  

 3972 16:50:55.465564  CA PerBit enable=1, Macro0, CA PI delay=33

 3973 16:50:55.465646  

 3974 16:50:55.468997  [CBTSetCACLKResult] CA Dly = 33

 3975 16:50:55.469079  CS Dly: 5 (0~37)

 3976 16:50:55.472101  

 3977 16:50:55.475437  ----->DramcWriteLeveling(PI) begin...

 3978 16:50:55.475520  ==

 3979 16:50:55.478688  Dram Type= 6, Freq= 0, CH_0, rank 0

 3980 16:50:55.482042  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3981 16:50:55.482124  ==

 3982 16:50:55.485664  Write leveling (Byte 0): 32 => 32

 3983 16:50:55.488921  Write leveling (Byte 1): 31 => 31

 3984 16:50:55.491988  DramcWriteLeveling(PI) end<-----

 3985 16:50:55.492071  

 3986 16:50:55.492136  ==

 3987 16:50:55.495198  Dram Type= 6, Freq= 0, CH_0, rank 0

 3988 16:50:55.498611  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3989 16:50:55.498698  ==

 3990 16:50:55.501810  [Gating] SW mode calibration

 3991 16:50:55.508429  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 3992 16:50:55.514992  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 3993 16:50:55.518317   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3994 16:50:55.521627   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3995 16:50:55.528385   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3996 16:50:55.531602   0  9 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)

 3997 16:50:55.534816   0  9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)

 3998 16:50:55.541638   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3999 16:50:55.544956   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4000 16:50:55.548190   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4001 16:50:55.554276   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4002 16:50:55.558035   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4003 16:50:55.561251   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4004 16:50:55.568284   0 10 12 | B1->B0 | 2626 3a39 | 1 1 | (0 0) (1 1)

 4005 16:50:55.571195   0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)

 4006 16:50:55.574435   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4007 16:50:55.581226   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4008 16:50:55.584253   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4009 16:50:55.587696   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4010 16:50:55.594574   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4011 16:50:55.597478   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4012 16:50:55.600980   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4013 16:50:55.607410   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4014 16:50:55.610871   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4015 16:50:55.614187   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4016 16:50:55.620563   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4017 16:50:55.624349   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4018 16:50:55.627419   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4019 16:50:55.634124   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4020 16:50:55.637080   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4021 16:50:55.640458   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4022 16:50:55.646981   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4023 16:50:55.650242   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4024 16:50:55.654000   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4025 16:50:55.660237   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4026 16:50:55.663859   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4027 16:50:55.667032   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4028 16:50:55.673683   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4029 16:50:55.676982   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4030 16:50:55.680479  Total UI for P1: 0, mck2ui 16

 4031 16:50:55.683678  best dqsien dly found for B0: ( 0, 13, 12)

 4032 16:50:55.687066   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4033 16:50:55.690048  Total UI for P1: 0, mck2ui 16

 4034 16:50:55.693137  best dqsien dly found for B1: ( 0, 13, 16)

 4035 16:50:55.696745  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4036 16:50:55.699998  best DQS1 dly(MCK, UI, PI) = (0, 13, 16)

 4037 16:50:55.700080  

 4038 16:50:55.706510  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4039 16:50:55.709766  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4040 16:50:55.709848  [Gating] SW calibration Done

 4041 16:50:55.713335  ==

 4042 16:50:55.716318  Dram Type= 6, Freq= 0, CH_0, rank 0

 4043 16:50:55.720048  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4044 16:50:55.720121  ==

 4045 16:50:55.720194  RX Vref Scan: 0

 4046 16:50:55.720255  

 4047 16:50:55.723294  RX Vref 0 -> 0, step: 1

 4048 16:50:55.723362  

 4049 16:50:55.726327  RX Delay -230 -> 252, step: 16

 4050 16:50:55.729496  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4051 16:50:55.733100  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4052 16:50:55.739409  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4053 16:50:55.743094  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4054 16:50:55.746290  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4055 16:50:55.749548  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4056 16:50:55.756062  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4057 16:50:55.759260  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4058 16:50:55.762859  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4059 16:50:55.766129  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4060 16:50:55.769297  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4061 16:50:55.776140  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4062 16:50:55.779357  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4063 16:50:55.782555  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4064 16:50:55.788906  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4065 16:50:55.792530  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4066 16:50:55.792614  ==

 4067 16:50:55.795493  Dram Type= 6, Freq= 0, CH_0, rank 0

 4068 16:50:55.799014  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4069 16:50:55.799099  ==

 4070 16:50:55.799167  DQS Delay:

 4071 16:50:55.802346  DQS0 = 0, DQS1 = 0

 4072 16:50:55.802465  DQM Delay:

 4073 16:50:55.805667  DQM0 = 51, DQM1 = 40

 4074 16:50:55.805750  DQ Delay:

 4075 16:50:55.809061  DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49

 4076 16:50:55.812263  DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57

 4077 16:50:55.815502  DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33

 4078 16:50:55.818982  DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41

 4079 16:50:55.819066  

 4080 16:50:55.819132  

 4081 16:50:55.819194  ==

 4082 16:50:55.822208  Dram Type= 6, Freq= 0, CH_0, rank 0

 4083 16:50:55.828807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4084 16:50:55.828891  ==

 4085 16:50:55.828959  

 4086 16:50:55.829020  

 4087 16:50:55.829080  	TX Vref Scan disable

 4088 16:50:55.832356   == TX Byte 0 ==

 4089 16:50:55.835571  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4090 16:50:55.841922  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4091 16:50:55.842006   == TX Byte 1 ==

 4092 16:50:55.845723  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4093 16:50:55.851959  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4094 16:50:55.852044  ==

 4095 16:50:55.855252  Dram Type= 6, Freq= 0, CH_0, rank 0

 4096 16:50:55.858410  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4097 16:50:55.858495  ==

 4098 16:50:55.858562  

 4099 16:50:55.858623  

 4100 16:50:55.861645  	TX Vref Scan disable

 4101 16:50:55.865524   == TX Byte 0 ==

 4102 16:50:55.868517  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4103 16:50:55.871496  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4104 16:50:55.874725   == TX Byte 1 ==

 4105 16:50:55.878031  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4106 16:50:55.881714  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4107 16:50:55.881797  

 4108 16:50:55.881864  [DATLAT]

 4109 16:50:55.884856  Freq=600, CH0 RK0

 4110 16:50:55.884939  

 4111 16:50:55.888000  DATLAT Default: 0x9

 4112 16:50:55.888083  0, 0xFFFF, sum = 0

 4113 16:50:55.891686  1, 0xFFFF, sum = 0

 4114 16:50:55.891770  2, 0xFFFF, sum = 0

 4115 16:50:55.894786  3, 0xFFFF, sum = 0

 4116 16:50:55.894869  4, 0xFFFF, sum = 0

 4117 16:50:55.897845  5, 0xFFFF, sum = 0

 4118 16:50:55.897928  6, 0xFFFF, sum = 0

 4119 16:50:55.901168  7, 0xFFFF, sum = 0

 4120 16:50:55.901287  8, 0x0, sum = 1

 4121 16:50:55.904505  9, 0x0, sum = 2

 4122 16:50:55.904589  10, 0x0, sum = 3

 4123 16:50:55.907763  11, 0x0, sum = 4

 4124 16:50:55.907847  best_step = 9

 4125 16:50:55.907913  

 4126 16:50:55.907974  ==

 4127 16:50:55.911205  Dram Type= 6, Freq= 0, CH_0, rank 0

 4128 16:50:55.914697  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4129 16:50:55.914780  ==

 4130 16:50:55.917928  RX Vref Scan: 1

 4131 16:50:55.918012  

 4132 16:50:55.921004  RX Vref 0 -> 0, step: 1

 4133 16:50:55.921090  

 4134 16:50:55.921157  RX Delay -179 -> 252, step: 8

 4135 16:50:55.924235  

 4136 16:50:55.924320  Set Vref, RX VrefLevel [Byte0]: 60

 4137 16:50:55.927846                           [Byte1]: 49

 4138 16:50:55.932540  

 4139 16:50:55.932627  Final RX Vref Byte 0 = 60 to rank0

 4140 16:50:55.935730  Final RX Vref Byte 1 = 49 to rank0

 4141 16:50:55.938903  Final RX Vref Byte 0 = 60 to rank1

 4142 16:50:55.942589  Final RX Vref Byte 1 = 49 to rank1==

 4143 16:50:55.945652  Dram Type= 6, Freq= 0, CH_0, rank 0

 4144 16:50:55.952447  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4145 16:50:55.952532  ==

 4146 16:50:55.952598  DQS Delay:

 4147 16:50:55.955628  DQS0 = 0, DQS1 = 0

 4148 16:50:55.955710  DQM Delay:

 4149 16:50:55.955776  DQM0 = 49, DQM1 = 37

 4150 16:50:55.958815  DQ Delay:

 4151 16:50:55.962003  DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44

 4152 16:50:55.965725  DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56

 4153 16:50:55.968822  DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32

 4154 16:50:55.972236  DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44

 4155 16:50:55.972318  

 4156 16:50:55.972383  

 4157 16:50:55.978502  [DQSOSCAuto] RK0, (LSB)MR18= 0x534d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps

 4158 16:50:55.982110  CH0 RK0: MR19=808, MR18=534D

 4159 16:50:55.988628  CH0_RK0: MR19=0x808, MR18=0x534D, DQSOSC=394, MR23=63, INC=168, DEC=112

 4160 16:50:55.988712  

 4161 16:50:55.991808  ----->DramcWriteLeveling(PI) begin...

 4162 16:50:55.991892  ==

 4163 16:50:55.994988  Dram Type= 6, Freq= 0, CH_0, rank 1

 4164 16:50:55.998309  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4165 16:50:55.998440  ==

 4166 16:50:56.001768  Write leveling (Byte 0): 35 => 35

 4167 16:50:56.004820  Write leveling (Byte 1): 28 => 28

 4168 16:50:56.008281  DramcWriteLeveling(PI) end<-----

 4169 16:50:56.008365  

 4170 16:50:56.008431  ==

 4171 16:50:56.011491  Dram Type= 6, Freq= 0, CH_0, rank 1

 4172 16:50:56.014728  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4173 16:50:56.018053  ==

 4174 16:50:56.018135  [Gating] SW mode calibration

 4175 16:50:56.028030  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4176 16:50:56.031204  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4177 16:50:56.034890   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4178 16:50:56.041117   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4179 16:50:56.044245   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4180 16:50:56.047532   0  9 12 | B1->B0 | 3030 3232 | 1 0 | (1 0) (1 0)

 4181 16:50:56.054108   0  9 16 | B1->B0 | 2727 2424 | 0 0 | (1 1) (0 0)

 4182 16:50:56.057448   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4183 16:50:56.060669   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4184 16:50:56.067328   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4185 16:50:56.070545   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4186 16:50:56.077404   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4187 16:50:56.080693   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4188 16:50:56.083845   0 10 12 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)

 4189 16:50:56.090263   0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 4190 16:50:56.093874   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4191 16:50:56.097081   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4192 16:50:56.103588   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4193 16:50:56.106850   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4194 16:50:56.110459   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4195 16:50:56.116681   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4196 16:50:56.120378   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4197 16:50:56.123686   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4198 16:50:56.127010   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4199 16:50:56.133609   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4200 16:50:56.136840   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4201 16:50:56.140098   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4202 16:50:56.146639   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4203 16:50:56.149877   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4204 16:50:56.153398   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4205 16:50:56.159561   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4206 16:50:56.163264   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4207 16:50:56.166453   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4208 16:50:56.172900   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4209 16:50:56.176191   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4210 16:50:56.182864   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4211 16:50:56.185923   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 4212 16:50:56.189590   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4213 16:50:56.195775   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4214 16:50:56.195859  Total UI for P1: 0, mck2ui 16

 4215 16:50:56.198988  best dqsien dly found for B0: ( 0, 13, 12)

 4216 16:50:56.202665  Total UI for P1: 0, mck2ui 16

 4217 16:50:56.205953  best dqsien dly found for B1: ( 0, 13, 14)

 4218 16:50:56.212532  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4219 16:50:56.215828  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4220 16:50:56.215910  

 4221 16:50:56.219028  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4222 16:50:56.222544  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4223 16:50:56.225604  [Gating] SW calibration Done

 4224 16:50:56.225687  ==

 4225 16:50:56.228855  Dram Type= 6, Freq= 0, CH_0, rank 1

 4226 16:50:56.232535  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4227 16:50:56.232620  ==

 4228 16:50:56.235709  RX Vref Scan: 0

 4229 16:50:56.235792  

 4230 16:50:56.235857  RX Vref 0 -> 0, step: 1

 4231 16:50:56.235919  

 4232 16:50:56.238994  RX Delay -230 -> 252, step: 16

 4233 16:50:56.242176  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4234 16:50:56.248964  iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288

 4235 16:50:56.252113  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4236 16:50:56.255564  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4237 16:50:56.258561  iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288

 4238 16:50:56.265283  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4239 16:50:56.268433  iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304

 4240 16:50:56.271640  iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304

 4241 16:50:56.275354  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4242 16:50:56.278547  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4243 16:50:56.285241  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4244 16:50:56.288437  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4245 16:50:56.291713  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4246 16:50:56.295021  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4247 16:50:56.301549  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4248 16:50:56.304674  iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288

 4249 16:50:56.304757  ==

 4250 16:50:56.308381  Dram Type= 6, Freq= 0, CH_0, rank 1

 4251 16:50:56.311409  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4252 16:50:56.311492  ==

 4253 16:50:56.314793  DQS Delay:

 4254 16:50:56.314875  DQS0 = 0, DQS1 = 0

 4255 16:50:56.314941  DQM Delay:

 4256 16:50:56.318113  DQM0 = 53, DQM1 = 43

 4257 16:50:56.318196  DQ Delay:

 4258 16:50:56.321782  DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49

 4259 16:50:56.325043  DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65

 4260 16:50:56.328279  DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41

 4261 16:50:56.331648  DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =57

 4262 16:50:56.331731  

 4263 16:50:56.331797  

 4264 16:50:56.331880  ==

 4265 16:50:56.334859  Dram Type= 6, Freq= 0, CH_0, rank 1

 4266 16:50:56.341462  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4267 16:50:56.341572  ==

 4268 16:50:56.341665  

 4269 16:50:56.341754  

 4270 16:50:56.341835  	TX Vref Scan disable

 4271 16:50:56.345162   == TX Byte 0 ==

 4272 16:50:56.348495  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 4273 16:50:56.354998  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 4274 16:50:56.355084   == TX Byte 1 ==

 4275 16:50:56.358260  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4276 16:50:56.365050  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4277 16:50:56.365133  ==

 4278 16:50:56.368225  Dram Type= 6, Freq= 0, CH_0, rank 1

 4279 16:50:56.371450  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4280 16:50:56.371534  ==

 4281 16:50:56.371600  

 4282 16:50:56.371660  

 4283 16:50:56.375133  	TX Vref Scan disable

 4284 16:50:56.378317   == TX Byte 0 ==

 4285 16:50:56.381629  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4286 16:50:56.384689  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4287 16:50:56.388224   == TX Byte 1 ==

 4288 16:50:56.391595  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4289 16:50:56.394828  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4290 16:50:56.394911  

 4291 16:50:56.394977  [DATLAT]

 4292 16:50:56.398095  Freq=600, CH0 RK1

 4293 16:50:56.398178  

 4294 16:50:56.401354  DATLAT Default: 0x9

 4295 16:50:56.401437  0, 0xFFFF, sum = 0

 4296 16:50:56.404608  1, 0xFFFF, sum = 0

 4297 16:50:56.404693  2, 0xFFFF, sum = 0

 4298 16:50:56.407720  3, 0xFFFF, sum = 0

 4299 16:50:56.407835  4, 0xFFFF, sum = 0

 4300 16:50:56.411026  5, 0xFFFF, sum = 0

 4301 16:50:56.411103  6, 0xFFFF, sum = 0

 4302 16:50:56.414584  7, 0xFFFF, sum = 0

 4303 16:50:56.414655  8, 0x0, sum = 1

 4304 16:50:56.417849  9, 0x0, sum = 2

 4305 16:50:56.417932  10, 0x0, sum = 3

 4306 16:50:56.421044  11, 0x0, sum = 4

 4307 16:50:56.421126  best_step = 9

 4308 16:50:56.421190  

 4309 16:50:56.421250  ==

 4310 16:50:56.424427  Dram Type= 6, Freq= 0, CH_0, rank 1

 4311 16:50:56.427984  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4312 16:50:56.428065  ==

 4313 16:50:56.430820  RX Vref Scan: 0

 4314 16:50:56.430901  

 4315 16:50:56.434509  RX Vref 0 -> 0, step: 1

 4316 16:50:56.434592  

 4317 16:50:56.434657  RX Delay -179 -> 252, step: 8

 4318 16:50:56.442230  iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296

 4319 16:50:56.445554  iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296

 4320 16:50:56.448808  iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296

 4321 16:50:56.452324  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4322 16:50:56.455742  iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296

 4323 16:50:56.462115  iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296

 4324 16:50:56.465683  iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296

 4325 16:50:56.468781  iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296

 4326 16:50:56.472060  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4327 16:50:56.478612  iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288

 4328 16:50:56.482301  iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296

 4329 16:50:56.485515  iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296

 4330 16:50:56.488756  iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296

 4331 16:50:56.495010  iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288

 4332 16:50:56.498297  iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288

 4333 16:50:56.501617  iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288

 4334 16:50:56.501705  ==

 4335 16:50:56.505254  Dram Type= 6, Freq= 0, CH_0, rank 1

 4336 16:50:56.508583  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4337 16:50:56.508680  ==

 4338 16:50:56.511799  DQS Delay:

 4339 16:50:56.511872  DQS0 = 0, DQS1 = 0

 4340 16:50:56.515187  DQM Delay:

 4341 16:50:56.515254  DQM0 = 48, DQM1 = 41

 4342 16:50:56.515313  DQ Delay:

 4343 16:50:56.518254  DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44

 4344 16:50:56.521757  DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56

 4345 16:50:56.524958  DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32

 4346 16:50:56.528199  DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =52

 4347 16:50:56.528281  

 4348 16:50:56.528345  

 4349 16:50:56.538050  [DQSOSCAuto] RK1, (LSB)MR18= 0x5d2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps

 4350 16:50:56.541209  CH0 RK1: MR19=808, MR18=5D2B

 4351 16:50:56.547846  CH0_RK1: MR19=0x808, MR18=0x5D2B, DQSOSC=392, MR23=63, INC=170, DEC=113

 4352 16:50:56.547927  [RxdqsGatingPostProcess] freq 600

 4353 16:50:56.554898  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4354 16:50:56.558109  Pre-setting of DQS Precalculation

 4355 16:50:56.561089  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4356 16:50:56.564720  ==

 4357 16:50:56.567986  Dram Type= 6, Freq= 0, CH_1, rank 0

 4358 16:50:56.571274  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4359 16:50:56.571358  ==

 4360 16:50:56.574445  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4361 16:50:56.581252  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31

 4362 16:50:56.584974  [CA 0] Center 35 (5~66) winsize 62

 4363 16:50:56.588588  [CA 1] Center 35 (5~66) winsize 62

 4364 16:50:56.591802  [CA 2] Center 34 (4~65) winsize 62

 4365 16:50:56.594882  [CA 3] Center 33 (3~64) winsize 62

 4366 16:50:56.598095  [CA 4] Center 34 (3~65) winsize 63

 4367 16:50:56.601817  [CA 5] Center 33 (3~64) winsize 62

 4368 16:50:56.601900  

 4369 16:50:56.605049  [CmdBusTrainingLP45] Vref(ca) range 1: 31

 4370 16:50:56.605159  

 4371 16:50:56.608432  [CATrainingPosCal] consider 1 rank data

 4372 16:50:56.611604  u2DelayCellTimex100 = 270/100 ps

 4373 16:50:56.614700  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4374 16:50:56.621556  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4375 16:50:56.625028  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4376 16:50:56.628156  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4377 16:50:56.631397  CA4 delay=34 (3~65),Diff = 1 PI (9 cell)

 4378 16:50:56.634535  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4379 16:50:56.634618  

 4380 16:50:56.638254  CA PerBit enable=1, Macro0, CA PI delay=33

 4381 16:50:56.638338  

 4382 16:50:56.641428  [CBTSetCACLKResult] CA Dly = 33

 4383 16:50:56.641512  CS Dly: 4 (0~35)

 4384 16:50:56.644608  ==

 4385 16:50:56.647750  Dram Type= 6, Freq= 0, CH_1, rank 1

 4386 16:50:56.651226  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4387 16:50:56.651309  ==

 4388 16:50:56.654531  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4389 16:50:56.661228  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4390 16:50:56.664952  [CA 0] Center 36 (6~66) winsize 61

 4391 16:50:56.668825  [CA 1] Center 36 (5~67) winsize 63

 4392 16:50:56.671925  [CA 2] Center 34 (4~65) winsize 62

 4393 16:50:56.675075  [CA 3] Center 34 (4~65) winsize 62

 4394 16:50:56.678114  [CA 4] Center 34 (4~65) winsize 62

 4395 16:50:56.681431  [CA 5] Center 34 (4~65) winsize 62

 4396 16:50:56.681519  

 4397 16:50:56.684687  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4398 16:50:56.684771  

 4399 16:50:56.688083  [CATrainingPosCal] consider 2 rank data

 4400 16:50:56.691311  u2DelayCellTimex100 = 270/100 ps

 4401 16:50:56.695111  CA0 delay=36 (6~66),Diff = 2 PI (19 cell)

 4402 16:50:56.701360  CA1 delay=35 (5~66),Diff = 1 PI (9 cell)

 4403 16:50:56.704605  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4404 16:50:56.708322  CA3 delay=34 (4~64),Diff = 0 PI (0 cell)

 4405 16:50:56.711486  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4406 16:50:56.714729  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 4407 16:50:56.714813  

 4408 16:50:56.717908  CA PerBit enable=1, Macro0, CA PI delay=34

 4409 16:50:56.718016  

 4410 16:50:56.721341  [CBTSetCACLKResult] CA Dly = 34

 4411 16:50:56.721427  CS Dly: 5 (0~37)

 4412 16:50:56.724685  

 4413 16:50:56.727862  ----->DramcWriteLeveling(PI) begin...

 4414 16:50:56.727946  ==

 4415 16:50:56.731373  Dram Type= 6, Freq= 0, CH_1, rank 0

 4416 16:50:56.734588  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4417 16:50:56.734673  ==

 4418 16:50:56.737709  Write leveling (Byte 0): 28 => 28

 4419 16:50:56.741059  Write leveling (Byte 1): 28 => 28

 4420 16:50:56.744338  DramcWriteLeveling(PI) end<-----

 4421 16:50:56.744421  

 4422 16:50:56.744486  ==

 4423 16:50:56.747975  Dram Type= 6, Freq= 0, CH_1, rank 0

 4424 16:50:56.751213  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4425 16:50:56.751296  ==

 4426 16:50:56.754522  [Gating] SW mode calibration

 4427 16:50:56.761225  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4428 16:50:56.767501  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4429 16:50:56.771016   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4430 16:50:56.774528   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4431 16:50:56.781039   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 4432 16:50:56.784129   0  9 12 | B1->B0 | 2c2c 2b2b | 0 1 | (0 1) (1 0)

 4433 16:50:56.787393   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4434 16:50:56.794044   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4435 16:50:56.797243   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4436 16:50:56.800886   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4437 16:50:56.807448   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4438 16:50:56.810693   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4439 16:50:56.813919   0 10  8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4440 16:50:56.820644   0 10 12 | B1->B0 | 3838 3f3f | 1 1 | (0 0) (0 0)

 4441 16:50:56.823908   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4442 16:50:56.827375   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4443 16:50:56.833799   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4444 16:50:56.836796   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4445 16:50:56.840578   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4446 16:50:56.846954   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4447 16:50:56.850227   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4448 16:50:56.853870   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4449 16:50:56.860158   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4450 16:50:56.863614   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4451 16:50:56.866827   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4452 16:50:56.873780   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4453 16:50:56.876678   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4454 16:50:56.880226   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4455 16:50:56.886895   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4456 16:50:56.890002   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4457 16:50:56.893491   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4458 16:50:56.899782   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4459 16:50:56.903361   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4460 16:50:56.906595   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4461 16:50:56.913191   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4462 16:50:56.916731   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4463 16:50:56.919629   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4464 16:50:56.926584   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4465 16:50:56.926668  Total UI for P1: 0, mck2ui 16

 4466 16:50:56.929709  best dqsien dly found for B0: ( 0, 13,  8)

 4467 16:50:56.932885  Total UI for P1: 0, mck2ui 16

 4468 16:50:56.935989  best dqsien dly found for B1: ( 0, 13,  8)

 4469 16:50:56.939581  best DQS0 dly(MCK, UI, PI) = (0, 13, 8)

 4470 16:50:56.946123  best DQS1 dly(MCK, UI, PI) = (0, 13, 8)

 4471 16:50:56.946207  

 4472 16:50:56.949309  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)

 4473 16:50:56.952638  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)

 4474 16:50:56.956276  [Gating] SW calibration Done

 4475 16:50:56.956359  ==

 4476 16:50:56.959422  Dram Type= 6, Freq= 0, CH_1, rank 0

 4477 16:50:56.962972  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4478 16:50:56.963057  ==

 4479 16:50:56.963123  RX Vref Scan: 0

 4480 16:50:56.965823  

 4481 16:50:56.965906  RX Vref 0 -> 0, step: 1

 4482 16:50:56.965972  

 4483 16:50:56.969666  RX Delay -230 -> 252, step: 16

 4484 16:50:56.972464  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4485 16:50:56.979331  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4486 16:50:56.982574  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4487 16:50:56.986059  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4488 16:50:56.989395  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4489 16:50:56.992682  iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288

 4490 16:50:56.999267  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4491 16:50:57.002111  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4492 16:50:57.005367  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4493 16:50:57.008843  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4494 16:50:57.015544  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4495 16:50:57.018822  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4496 16:50:57.022003  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4497 16:50:57.025571  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4498 16:50:57.031820  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4499 16:50:57.035503  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4500 16:50:57.035586  ==

 4501 16:50:57.038682  Dram Type= 6, Freq= 0, CH_1, rank 0

 4502 16:50:57.041953  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4503 16:50:57.042036  ==

 4504 16:50:57.045230  DQS Delay:

 4505 16:50:57.045314  DQS0 = 0, DQS1 = 0

 4506 16:50:57.045380  DQM Delay:

 4507 16:50:57.048408  DQM0 = 49, DQM1 = 44

 4508 16:50:57.048492  DQ Delay:

 4509 16:50:57.051632  DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49

 4510 16:50:57.054913  DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49

 4511 16:50:57.058687  DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41

 4512 16:50:57.061836  DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49

 4513 16:50:57.061919  

 4514 16:50:57.061985  

 4515 16:50:57.062046  ==

 4516 16:50:57.064958  Dram Type= 6, Freq= 0, CH_1, rank 0

 4517 16:50:57.071619  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4518 16:50:57.071703  ==

 4519 16:50:57.071769  

 4520 16:50:57.071829  

 4521 16:50:57.071887  	TX Vref Scan disable

 4522 16:50:57.075613   == TX Byte 0 ==

 4523 16:50:57.078627  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4524 16:50:57.085402  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4525 16:50:57.085486   == TX Byte 1 ==

 4526 16:50:57.089179  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4527 16:50:57.095192  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4528 16:50:57.095277  ==

 4529 16:50:57.098385  Dram Type= 6, Freq= 0, CH_1, rank 0

 4530 16:50:57.104993  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4531 16:50:57.105124  ==

 4532 16:50:57.105251  

 4533 16:50:57.105356  

 4534 16:50:57.105627  	TX Vref Scan disable

 4535 16:50:57.108591   == TX Byte 0 ==

 4536 16:50:57.111884  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4537 16:50:57.115101  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4538 16:50:57.118523   == TX Byte 1 ==

 4539 16:50:57.121916  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4540 16:50:57.124821  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4541 16:50:57.124906  

 4542 16:50:57.124971  [DATLAT]

 4543 16:50:57.128336  Freq=600, CH1 RK0

 4544 16:50:57.128420  

 4545 16:50:57.131342  DATLAT Default: 0x9

 4546 16:50:57.131425  0, 0xFFFF, sum = 0

 4547 16:50:57.134752  1, 0xFFFF, sum = 0

 4548 16:50:57.134837  2, 0xFFFF, sum = 0

 4549 16:50:57.138083  3, 0xFFFF, sum = 0

 4550 16:50:57.138168  4, 0xFFFF, sum = 0

 4551 16:50:57.141169  5, 0xFFFF, sum = 0

 4552 16:50:57.141254  6, 0xFFFF, sum = 0

 4553 16:50:57.144739  7, 0xFFFF, sum = 0

 4554 16:50:57.144823  8, 0x0, sum = 1

 4555 16:50:57.147642  9, 0x0, sum = 2

 4556 16:50:57.147727  10, 0x0, sum = 3

 4557 16:50:57.151292  11, 0x0, sum = 4

 4558 16:50:57.151376  best_step = 9

 4559 16:50:57.151442  

 4560 16:50:57.151502  ==

 4561 16:50:57.154528  Dram Type= 6, Freq= 0, CH_1, rank 0

 4562 16:50:57.157977  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4563 16:50:57.158062  ==

 4564 16:50:57.160993  RX Vref Scan: 1

 4565 16:50:57.161077  

 4566 16:50:57.164478  RX Vref 0 -> 0, step: 1

 4567 16:50:57.164561  

 4568 16:50:57.164627  RX Delay -163 -> 252, step: 8

 4569 16:50:57.167860  

 4570 16:50:57.167943  Set Vref, RX VrefLevel [Byte0]: 51

 4571 16:50:57.170858                           [Byte1]: 52

 4572 16:50:57.175764  

 4573 16:50:57.175848  Final RX Vref Byte 0 = 51 to rank0

 4574 16:50:57.179149  Final RX Vref Byte 1 = 52 to rank0

 4575 16:50:57.182221  Final RX Vref Byte 0 = 51 to rank1

 4576 16:50:57.185440  Final RX Vref Byte 1 = 52 to rank1==

 4577 16:50:57.189203  Dram Type= 6, Freq= 0, CH_1, rank 0

 4578 16:50:57.195591  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4579 16:50:57.195676  ==

 4580 16:50:57.195742  DQS Delay:

 4581 16:50:57.198710  DQS0 = 0, DQS1 = 0

 4582 16:50:57.198793  DQM Delay:

 4583 16:50:57.198859  DQM0 = 48, DQM1 = 40

 4584 16:50:57.202251  DQ Delay:

 4585 16:50:57.205393  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4586 16:50:57.208868  DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44

 4587 16:50:57.211940  DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =32

 4588 16:50:57.215568  DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48

 4589 16:50:57.215654  

 4590 16:50:57.215721  

 4591 16:50:57.221750  [DQSOSCAuto] RK0, (LSB)MR18= 0x486e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps

 4592 16:50:57.225334  CH1 RK0: MR19=808, MR18=486E

 4593 16:50:57.231891  CH1_RK0: MR19=0x808, MR18=0x486E, DQSOSC=389, MR23=63, INC=173, DEC=115

 4594 16:50:57.231984  

 4595 16:50:57.235018  ----->DramcWriteLeveling(PI) begin...

 4596 16:50:57.235103  ==

 4597 16:50:57.238623  Dram Type= 6, Freq= 0, CH_1, rank 1

 4598 16:50:57.241601  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4599 16:50:57.241686  ==

 4600 16:50:57.245406  Write leveling (Byte 0): 30 => 30

 4601 16:50:57.248435  Write leveling (Byte 1): 29 => 29

 4602 16:50:57.251824  DramcWriteLeveling(PI) end<-----

 4603 16:50:57.251908  

 4604 16:50:57.251974  ==

 4605 16:50:57.255037  Dram Type= 6, Freq= 0, CH_1, rank 1

 4606 16:50:57.258721  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4607 16:50:57.261681  ==

 4608 16:50:57.261764  [Gating] SW mode calibration

 4609 16:50:57.268509  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4610 16:50:57.274750  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4611 16:50:57.278293   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4612 16:50:57.284873   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4613 16:50:57.288323   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4614 16:50:57.291433   0  9 12 | B1->B0 | 2828 3131 | 0 1 | (1 0) (1 0)

 4615 16:50:57.297983   0  9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 4616 16:50:57.301535   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4617 16:50:57.304699   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4618 16:50:57.311278   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4619 16:50:57.314340   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4620 16:50:57.317899   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4621 16:50:57.324404   0 10  8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4622 16:50:57.328049   0 10 12 | B1->B0 | 3c3c 3030 | 1 0 | (0 0) (1 1)

 4623 16:50:57.330865   0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)

 4624 16:50:57.337744   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4625 16:50:57.340993   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4626 16:50:57.344417   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4627 16:50:57.350987   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4628 16:50:57.354176   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4629 16:50:57.357289   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4630 16:50:57.364343   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 4631 16:50:57.367439   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4632 16:50:57.370690   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4633 16:50:57.377151   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4634 16:50:57.381137   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4635 16:50:57.384063   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4636 16:50:57.390325   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4637 16:50:57.393898   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4638 16:50:57.397187   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4639 16:50:57.403786   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4640 16:50:57.407234   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4641 16:50:57.410380   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4642 16:50:57.416841   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4643 16:50:57.420228   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4644 16:50:57.423753   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4645 16:50:57.430065   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4646 16:50:57.433741   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4647 16:50:57.436692  Total UI for P1: 0, mck2ui 16

 4648 16:50:57.440016  best dqsien dly found for B0: ( 0, 13, 10)

 4649 16:50:57.443686   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4650 16:50:57.446649  Total UI for P1: 0, mck2ui 16

 4651 16:50:57.449723  best dqsien dly found for B1: ( 0, 13, 12)

 4652 16:50:57.453449  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4653 16:50:57.456541  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4654 16:50:57.456611  

 4655 16:50:57.463036  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4656 16:50:57.466771  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4657 16:50:57.466849  [Gating] SW calibration Done

 4658 16:50:57.469784  ==

 4659 16:50:57.473084  Dram Type= 6, Freq= 0, CH_1, rank 1

 4660 16:50:57.476402  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4661 16:50:57.476474  ==

 4662 16:50:57.476539  RX Vref Scan: 0

 4663 16:50:57.476596  

 4664 16:50:57.479759  RX Vref 0 -> 0, step: 1

 4665 16:50:57.479827  

 4666 16:50:57.482894  RX Delay -230 -> 252, step: 16

 4667 16:50:57.486284  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4668 16:50:57.489615  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4669 16:50:57.496148  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4670 16:50:57.499238  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4671 16:50:57.502747  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4672 16:50:57.505803  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4673 16:50:57.512776  iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304

 4674 16:50:57.515824  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4675 16:50:57.519335  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4676 16:50:57.522669  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4677 16:50:57.525973  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4678 16:50:57.532618  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4679 16:50:57.536172  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4680 16:50:57.539112  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4681 16:50:57.542475  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4682 16:50:57.549237  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4683 16:50:57.549313  ==

 4684 16:50:57.552195  Dram Type= 6, Freq= 0, CH_1, rank 1

 4685 16:50:57.555751  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4686 16:50:57.555841  ==

 4687 16:50:57.555908  DQS Delay:

 4688 16:50:57.559185  DQS0 = 0, DQS1 = 0

 4689 16:50:57.559268  DQM Delay:

 4690 16:50:57.562533  DQM0 = 48, DQM1 = 47

 4691 16:50:57.562616  DQ Delay:

 4692 16:50:57.565393  DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49

 4693 16:50:57.569139  DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49

 4694 16:50:57.572523  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4695 16:50:57.575589  DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57

 4696 16:50:57.575672  

 4697 16:50:57.575738  

 4698 16:50:57.575798  ==

 4699 16:50:57.578939  Dram Type= 6, Freq= 0, CH_1, rank 1

 4700 16:50:57.585081  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4701 16:50:57.585165  ==

 4702 16:50:57.585231  

 4703 16:50:57.585292  

 4704 16:50:57.585359  	TX Vref Scan disable

 4705 16:50:57.588622   == TX Byte 0 ==

 4706 16:50:57.592136  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4707 16:50:57.598499  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4708 16:50:57.598582   == TX Byte 1 ==

 4709 16:50:57.602125  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4710 16:50:57.608400  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4711 16:50:57.608484  ==

 4712 16:50:57.611586  Dram Type= 6, Freq= 0, CH_1, rank 1

 4713 16:50:57.615120  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4714 16:50:57.615203  ==

 4715 16:50:57.615270  

 4716 16:50:57.615331  

 4717 16:50:57.618253  	TX Vref Scan disable

 4718 16:50:57.621809   == TX Byte 0 ==

 4719 16:50:57.624773  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4720 16:50:57.628451  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4721 16:50:57.631369   == TX Byte 1 ==

 4722 16:50:57.634884  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4723 16:50:57.638168  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4724 16:50:57.638252  

 4725 16:50:57.638317  [DATLAT]

 4726 16:50:57.641603  Freq=600, CH1 RK1

 4727 16:50:57.641687  

 4728 16:50:57.644725  DATLAT Default: 0x9

 4729 16:50:57.644808  0, 0xFFFF, sum = 0

 4730 16:50:57.648070  1, 0xFFFF, sum = 0

 4731 16:50:57.648153  2, 0xFFFF, sum = 0

 4732 16:50:57.651251  3, 0xFFFF, sum = 0

 4733 16:50:57.651335  4, 0xFFFF, sum = 0

 4734 16:50:57.654594  5, 0xFFFF, sum = 0

 4735 16:50:57.654678  6, 0xFFFF, sum = 0

 4736 16:50:57.658206  7, 0xFFFF, sum = 0

 4737 16:50:57.658317  8, 0x0, sum = 1

 4738 16:50:57.661025  9, 0x0, sum = 2

 4739 16:50:57.661109  10, 0x0, sum = 3

 4740 16:50:57.664674  11, 0x0, sum = 4

 4741 16:50:57.664758  best_step = 9

 4742 16:50:57.664825  

 4743 16:50:57.664884  ==

 4744 16:50:57.668177  Dram Type= 6, Freq= 0, CH_1, rank 1

 4745 16:50:57.671229  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4746 16:50:57.671312  ==

 4747 16:50:57.674436  RX Vref Scan: 0

 4748 16:50:57.674519  

 4749 16:50:57.678103  RX Vref 0 -> 0, step: 1

 4750 16:50:57.678186  

 4751 16:50:57.678252  RX Delay -163 -> 252, step: 8

 4752 16:50:57.685694  iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272

 4753 16:50:57.689092  iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280

 4754 16:50:57.692672  iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280

 4755 16:50:57.695647  iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280

 4756 16:50:57.698736  iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280

 4757 16:50:57.705351  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4758 16:50:57.708921  iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280

 4759 16:50:57.711917  iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280

 4760 16:50:57.715320  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4761 16:50:57.722094  iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296

 4762 16:50:57.725174  iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288

 4763 16:50:57.728531  iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296

 4764 16:50:57.731881  iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296

 4765 16:50:57.735400  iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296

 4766 16:50:57.742188  iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296

 4767 16:50:57.745119  iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304

 4768 16:50:57.745196  ==

 4769 16:50:57.748232  Dram Type= 6, Freq= 0, CH_1, rank 1

 4770 16:50:57.751838  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4771 16:50:57.751919  ==

 4772 16:50:57.755035  DQS Delay:

 4773 16:50:57.755139  DQS0 = 0, DQS1 = 0

 4774 16:50:57.758131  DQM Delay:

 4775 16:50:57.758205  DQM0 = 49, DQM1 = 43

 4776 16:50:57.758265  DQ Delay:

 4777 16:50:57.761642  DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48

 4778 16:50:57.764627  DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48

 4779 16:50:57.768119  DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40

 4780 16:50:57.771290  DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52

 4781 16:50:57.771367  

 4782 16:50:57.771431  

 4783 16:50:57.781412  [DQSOSCAuto] RK1, (LSB)MR18= 0x5219, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps

 4784 16:50:57.784550  CH1 RK1: MR19=808, MR18=5219

 4785 16:50:57.791199  CH1_RK1: MR19=0x808, MR18=0x5219, DQSOSC=394, MR23=63, INC=168, DEC=112

 4786 16:50:57.791283  [RxdqsGatingPostProcess] freq 600

 4787 16:50:57.797766  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4788 16:50:57.801091  Pre-setting of DQS Precalculation

 4789 16:50:57.804513  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4790 16:50:57.814339  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4791 16:50:57.821190  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4792 16:50:57.821298  

 4793 16:50:57.821393  

 4794 16:50:57.824187  [Calibration Summary] 1200 Mbps

 4795 16:50:57.824264  CH 0, Rank 0

 4796 16:50:57.827826  SW Impedance     : PASS

 4797 16:50:57.827900  DUTY Scan        : NO K

 4798 16:50:57.831103  ZQ Calibration   : PASS

 4799 16:50:57.834344  Jitter Meter     : NO K

 4800 16:50:57.834424  CBT Training     : PASS

 4801 16:50:57.837697  Write leveling   : PASS

 4802 16:50:57.841209  RX DQS gating    : PASS

 4803 16:50:57.841282  RX DQ/DQS(RDDQC) : PASS

 4804 16:50:57.844141  TX DQ/DQS        : PASS

 4805 16:50:57.847391  RX DATLAT        : PASS

 4806 16:50:57.847469  RX DQ/DQS(Engine): PASS

 4807 16:50:57.850758  TX OE            : NO K

 4808 16:50:57.850832  All Pass.

 4809 16:50:57.850893  

 4810 16:50:57.854110  CH 0, Rank 1

 4811 16:50:57.854211  SW Impedance     : PASS

 4812 16:50:57.857239  DUTY Scan        : NO K

 4813 16:50:57.860663  ZQ Calibration   : PASS

 4814 16:50:57.860740  Jitter Meter     : NO K

 4815 16:50:57.863822  CBT Training     : PASS

 4816 16:50:57.867500  Write leveling   : PASS

 4817 16:50:57.867572  RX DQS gating    : PASS

 4818 16:50:57.870932  RX DQ/DQS(RDDQC) : PASS

 4819 16:50:57.873721  TX DQ/DQS        : PASS

 4820 16:50:57.873801  RX DATLAT        : PASS

 4821 16:50:57.876847  RX DQ/DQS(Engine): PASS

 4822 16:50:57.880418  TX OE            : NO K

 4823 16:50:57.880525  All Pass.

 4824 16:50:57.880629  

 4825 16:50:57.880721  CH 1, Rank 0

 4826 16:50:57.883897  SW Impedance     : PASS

 4827 16:50:57.887052  DUTY Scan        : NO K

 4828 16:50:57.887136  ZQ Calibration   : PASS

 4829 16:50:57.890337  Jitter Meter     : NO K

 4830 16:50:57.893588  CBT Training     : PASS

 4831 16:50:57.893671  Write leveling   : PASS

 4832 16:50:57.896761  RX DQS gating    : PASS

 4833 16:50:57.896863  RX DQ/DQS(RDDQC) : PASS

 4834 16:50:57.900230  TX DQ/DQS        : PASS

 4835 16:50:57.903709  RX DATLAT        : PASS

 4836 16:50:57.903806  RX DQ/DQS(Engine): PASS

 4837 16:50:57.929266  TX OE            : NO K

 4838 16:50:57.929351  All Pass.

 4839 16:50:57.929423  

 4840 16:50:57.929487  CH 1, Rank 1

 4841 16:50:57.929547  SW Impedance     : PASS

 4842 16:50:57.929607  DUTY Scan        : NO K

 4843 16:50:57.929669  ZQ Calibration   : PASS

 4844 16:50:57.929748  Jitter Meter     : NO K

 4845 16:50:57.929809  CBT Training     : PASS

 4846 16:50:57.929866  Write leveling   : PASS

 4847 16:50:57.929924  RX DQS gating    : PASS

 4848 16:50:57.929984  RX DQ/DQS(RDDQC) : PASS

 4849 16:50:57.930225  TX DQ/DQS        : PASS

 4850 16:50:57.930319  RX DATLAT        : PASS

 4851 16:50:57.933087  RX DQ/DQS(Engine): PASS

 4852 16:50:57.936201  TX OE            : NO K

 4853 16:50:57.936286  All Pass.

 4854 16:50:57.936352  

 4855 16:50:57.939616  DramC Write-DBI off

 4856 16:50:57.939700  	PER_BANK_REFRESH: Hybrid Mode

 4857 16:50:57.943526  TX_TRACKING: ON

 4858 16:50:57.949554  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4859 16:50:57.956301  [FAST_K] Save calibration result to emmc

 4860 16:50:57.959553  dramc_set_vcore_voltage set vcore to 662500

 4861 16:50:57.959630  Read voltage for 933, 3

 4862 16:50:57.962644  Vio18 = 0

 4863 16:50:57.962743  Vcore = 662500

 4864 16:50:57.962834  Vdram = 0

 4865 16:50:57.966099  Vddq = 0

 4866 16:50:57.966172  Vmddr = 0

 4867 16:50:57.969737  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4868 16:50:57.976183  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4869 16:50:57.979253  MEM_TYPE=3, freq_sel=17

 4870 16:50:57.982723  sv_algorithm_assistance_LP4_1600 

 4871 16:50:57.986251  ============ PULL DRAM RESETB DOWN ============

 4872 16:50:57.989322  ========== PULL DRAM RESETB DOWN end =========

 4873 16:50:57.996009  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4874 16:50:57.999020  =================================== 

 4875 16:50:57.999099  LPDDR4 DRAM CONFIGURATION

 4876 16:50:58.002810  =================================== 

 4877 16:50:58.006176  EX_ROW_EN[0]    = 0x0

 4878 16:50:58.006289  EX_ROW_EN[1]    = 0x0

 4879 16:50:58.009259  LP4Y_EN      = 0x0

 4880 16:50:58.009366  WORK_FSP     = 0x0

 4881 16:50:58.012351  WL           = 0x3

 4882 16:50:58.016093  RL           = 0x3

 4883 16:50:58.016193  BL           = 0x2

 4884 16:50:58.019102  RPST         = 0x0

 4885 16:50:58.019209  RD_PRE       = 0x0

 4886 16:50:58.022442  WR_PRE       = 0x1

 4887 16:50:58.022516  WR_PST       = 0x0

 4888 16:50:58.025560  DBI_WR       = 0x0

 4889 16:50:58.025636  DBI_RD       = 0x0

 4890 16:50:58.029000  OTF          = 0x1

 4891 16:50:58.032480  =================================== 

 4892 16:50:58.035714  =================================== 

 4893 16:50:58.035788  ANA top config

 4894 16:50:58.039052  =================================== 

 4895 16:50:58.042060  DLL_ASYNC_EN            =  0

 4896 16:50:58.045801  ALL_SLAVE_EN            =  1

 4897 16:50:58.045880  NEW_RANK_MODE           =  1

 4898 16:50:58.048729  DLL_IDLE_MODE           =  1

 4899 16:50:58.051958  LP45_APHY_COMB_EN       =  1

 4900 16:50:58.055578  TX_ODT_DIS              =  1

 4901 16:50:58.058918  NEW_8X_MODE             =  1

 4902 16:50:58.061968  =================================== 

 4903 16:50:58.065164  =================================== 

 4904 16:50:58.065264  data_rate                  = 1866

 4905 16:50:58.068664  CKR                        = 1

 4906 16:50:58.072034  DQ_P2S_RATIO               = 8

 4907 16:50:58.075316  =================================== 

 4908 16:50:58.078481  CA_P2S_RATIO               = 8

 4909 16:50:58.081923  DQ_CA_OPEN                 = 0

 4910 16:50:58.085304  DQ_SEMI_OPEN               = 0

 4911 16:50:58.085379  CA_SEMI_OPEN               = 0

 4912 16:50:58.088587  CA_FULL_RATE               = 0

 4913 16:50:58.092192  DQ_CKDIV4_EN               = 1

 4914 16:50:58.095267  CA_CKDIV4_EN               = 1

 4915 16:50:58.098698  CA_PREDIV_EN               = 0

 4916 16:50:58.101645  PH8_DLY                    = 0

 4917 16:50:58.101746  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4918 16:50:58.105000  DQ_AAMCK_DIV               = 4

 4919 16:50:58.108458  CA_AAMCK_DIV               = 4

 4920 16:50:58.111612  CA_ADMCK_DIV               = 4

 4921 16:50:58.115149  DQ_TRACK_CA_EN             = 0

 4922 16:50:58.118590  CA_PICK                    = 933

 4923 16:50:58.118664  CA_MCKIO                   = 933

 4924 16:50:58.121622  MCKIO_SEMI                 = 0

 4925 16:50:58.124863  PLL_FREQ                   = 3732

 4926 16:50:58.128564  DQ_UI_PI_RATIO             = 32

 4927 16:50:58.131364  CA_UI_PI_RATIO             = 0

 4928 16:50:58.134888  =================================== 

 4929 16:50:58.138073  =================================== 

 4930 16:50:58.142019  memory_type:LPDDR4         

 4931 16:50:58.142122  GP_NUM     : 10       

 4932 16:50:58.144638  SRAM_EN    : 1       

 4933 16:50:58.144742  MD32_EN    : 0       

 4934 16:50:58.147994  =================================== 

 4935 16:50:58.151368  [ANA_INIT] >>>>>>>>>>>>>> 

 4936 16:50:58.154900  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4937 16:50:58.157797  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4938 16:50:58.161417  =================================== 

 4939 16:50:58.164848  data_rate = 1866,PCW = 0X8f00

 4940 16:50:58.167959  =================================== 

 4941 16:50:58.171453  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4942 16:50:58.177740  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4943 16:50:58.181043  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4944 16:50:58.187658  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4945 16:50:58.191179  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4946 16:50:58.194669  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4947 16:50:58.194746  [ANA_INIT] flow start 

 4948 16:50:58.198152  [ANA_INIT] PLL >>>>>>>> 

 4949 16:50:58.201048  [ANA_INIT] PLL <<<<<<<< 

 4950 16:50:58.201147  [ANA_INIT] MIDPI >>>>>>>> 

 4951 16:50:58.204706  [ANA_INIT] MIDPI <<<<<<<< 

 4952 16:50:58.208013  [ANA_INIT] DLL >>>>>>>> 

 4953 16:50:58.208115  [ANA_INIT] flow end 

 4954 16:50:58.214338  ============ LP4 DIFF to SE enter ============

 4955 16:50:58.217615  ============ LP4 DIFF to SE exit  ============

 4956 16:50:58.221140  [ANA_INIT] <<<<<<<<<<<<< 

 4957 16:50:58.224293  [Flow] Enable top DCM control >>>>> 

 4958 16:50:58.227483  [Flow] Enable top DCM control <<<<< 

 4959 16:50:58.227583  Enable DLL master slave shuffle 

 4960 16:50:58.234311  ============================================================== 

 4961 16:50:58.237608  Gating Mode config

 4962 16:50:58.241170  ============================================================== 

 4963 16:50:58.244155  Config description: 

 4964 16:50:58.254554  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4965 16:50:58.260857  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4966 16:50:58.263967  SELPH_MODE            0: By rank         1: By Phase 

 4967 16:50:58.270629  ============================================================== 

 4968 16:50:58.273786  GAT_TRACK_EN                 =  1

 4969 16:50:58.276985  RX_GATING_MODE               =  2

 4970 16:50:58.280620  RX_GATING_TRACK_MODE         =  2

 4971 16:50:58.283776  SELPH_MODE                   =  1

 4972 16:50:58.286966  PICG_EARLY_EN                =  1

 4973 16:50:58.290303  VALID_LAT_VALUE              =  1

 4974 16:50:58.293458  ============================================================== 

 4975 16:50:58.296857  Enter into Gating configuration >>>> 

 4976 16:50:58.300474  Exit from Gating configuration <<<< 

 4977 16:50:58.303802  Enter into  DVFS_PRE_config >>>>> 

 4978 16:50:58.313302  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 4979 16:50:58.316650  Exit from  DVFS_PRE_config <<<<< 

 4980 16:50:58.319992  Enter into PICG configuration >>>> 

 4981 16:50:58.323382  Exit from PICG configuration <<<< 

 4982 16:50:58.326734  [RX_INPUT] configuration >>>>> 

 4983 16:50:58.329978  [RX_INPUT] configuration <<<<< 

 4984 16:50:58.336877  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 4985 16:50:58.339651  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 4986 16:50:58.346314  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 4987 16:50:58.352989  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 4988 16:50:58.359428  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 4989 16:50:58.365879  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 4990 16:50:58.369320  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 4991 16:50:58.372825  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 4992 16:50:58.375995  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 4993 16:50:58.382336  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 4994 16:50:58.385853  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 4995 16:50:58.389275  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4996 16:50:58.392674  =================================== 

 4997 16:50:58.395838  LPDDR4 DRAM CONFIGURATION

 4998 16:50:58.399073  =================================== 

 4999 16:50:58.402501  EX_ROW_EN[0]    = 0x0

 5000 16:50:58.402607  EX_ROW_EN[1]    = 0x0

 5001 16:50:58.405693  LP4Y_EN      = 0x0

 5002 16:50:58.405773  WORK_FSP     = 0x0

 5003 16:50:58.408921  WL           = 0x3

 5004 16:50:58.409000  RL           = 0x3

 5005 16:50:58.412663  BL           = 0x2

 5006 16:50:58.412734  RPST         = 0x0

 5007 16:50:58.415443  RD_PRE       = 0x0

 5008 16:50:58.415513  WR_PRE       = 0x1

 5009 16:50:58.418809  WR_PST       = 0x0

 5010 16:50:58.418912  DBI_WR       = 0x0

 5011 16:50:58.422253  DBI_RD       = 0x0

 5012 16:50:58.425746  OTF          = 0x1

 5013 16:50:58.428833  =================================== 

 5014 16:50:58.432103  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5015 16:50:58.435447  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5016 16:50:58.438524  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5017 16:50:58.442072  =================================== 

 5018 16:50:58.444998  LPDDR4 DRAM CONFIGURATION

 5019 16:50:58.448323  =================================== 

 5020 16:50:58.452124  EX_ROW_EN[0]    = 0x10

 5021 16:50:58.452195  EX_ROW_EN[1]    = 0x0

 5022 16:50:58.455179  LP4Y_EN      = 0x0

 5023 16:50:58.455263  WORK_FSP     = 0x0

 5024 16:50:58.458360  WL           = 0x3

 5025 16:50:58.458437  RL           = 0x3

 5026 16:50:58.461746  BL           = 0x2

 5027 16:50:58.461842  RPST         = 0x0

 5028 16:50:58.465048  RD_PRE       = 0x0

 5029 16:50:58.465120  WR_PRE       = 0x1

 5030 16:50:58.468431  WR_PST       = 0x0

 5031 16:50:58.468514  DBI_WR       = 0x0

 5032 16:50:58.471584  DBI_RD       = 0x0

 5033 16:50:58.474869  OTF          = 0x1

 5034 16:50:58.478290  =================================== 

 5035 16:50:58.481767  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5036 16:50:58.486696  nWR fixed to 30

 5037 16:50:58.489880  [ModeRegInit_LP4] CH0 RK0

 5038 16:50:58.489977  [ModeRegInit_LP4] CH0 RK1

 5039 16:50:58.493307  [ModeRegInit_LP4] CH1 RK0

 5040 16:50:58.496370  [ModeRegInit_LP4] CH1 RK1

 5041 16:50:58.496446  match AC timing 9

 5042 16:50:58.502986  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5043 16:50:58.506244  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5044 16:50:58.509448  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5045 16:50:58.516225  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5046 16:50:58.519339  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5047 16:50:58.519425  ==

 5048 16:50:58.522596  Dram Type= 6, Freq= 0, CH_0, rank 0

 5049 16:50:58.525825  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5050 16:50:58.525895  ==

 5051 16:50:58.532710  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5052 16:50:58.539523  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5053 16:50:58.542663  [CA 0] Center 37 (7~68) winsize 62

 5054 16:50:58.545821  [CA 1] Center 38 (8~69) winsize 62

 5055 16:50:58.549164  [CA 2] Center 35 (5~66) winsize 62

 5056 16:50:58.552271  [CA 3] Center 34 (4~65) winsize 62

 5057 16:50:58.555797  [CA 4] Center 34 (4~64) winsize 61

 5058 16:50:58.558846  [CA 5] Center 33 (3~64) winsize 62

 5059 16:50:58.558941  

 5060 16:50:58.562223  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5061 16:50:58.562293  

 5062 16:50:58.565882  [CATrainingPosCal] consider 1 rank data

 5063 16:50:58.568729  u2DelayCellTimex100 = 270/100 ps

 5064 16:50:58.572297  CA0 delay=37 (7~68),Diff = 4 PI (24 cell)

 5065 16:50:58.575475  CA1 delay=38 (8~69),Diff = 5 PI (31 cell)

 5066 16:50:58.578740  CA2 delay=35 (5~66),Diff = 2 PI (12 cell)

 5067 16:50:58.585463  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5068 16:50:58.588937  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5069 16:50:58.591846  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5070 16:50:58.591915  

 5071 16:50:58.595283  CA PerBit enable=1, Macro0, CA PI delay=33

 5072 16:50:58.595354  

 5073 16:50:58.598586  [CBTSetCACLKResult] CA Dly = 33

 5074 16:50:58.598659  CS Dly: 6 (0~37)

 5075 16:50:58.598721  ==

 5076 16:50:58.601726  Dram Type= 6, Freq= 0, CH_0, rank 1

 5077 16:50:58.608447  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5078 16:50:58.608554  ==

 5079 16:50:58.611552  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5080 16:50:58.618148  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 5081 16:50:58.621710  [CA 0] Center 38 (8~69) winsize 62

 5082 16:50:58.625094  [CA 1] Center 38 (8~69) winsize 62

 5083 16:50:58.628472  [CA 2] Center 36 (6~66) winsize 61

 5084 16:50:58.631945  [CA 3] Center 35 (5~66) winsize 62

 5085 16:50:58.635422  [CA 4] Center 34 (4~65) winsize 62

 5086 16:50:58.638176  [CA 5] Center 34 (4~64) winsize 61

 5087 16:50:58.638271  

 5088 16:50:58.641845  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 5089 16:50:58.641914  

 5090 16:50:58.644982  [CATrainingPosCal] consider 2 rank data

 5091 16:50:58.648415  u2DelayCellTimex100 = 270/100 ps

 5092 16:50:58.651395  CA0 delay=38 (8~68),Diff = 4 PI (24 cell)

 5093 16:50:58.655159  CA1 delay=38 (8~69),Diff = 4 PI (24 cell)

 5094 16:50:58.661606  CA2 delay=36 (6~66),Diff = 2 PI (12 cell)

 5095 16:50:58.664696  CA3 delay=35 (5~65),Diff = 1 PI (6 cell)

 5096 16:50:58.668130  CA4 delay=34 (4~64),Diff = 0 PI (0 cell)

 5097 16:50:58.671451  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5098 16:50:58.671521  

 5099 16:50:58.674943  CA PerBit enable=1, Macro0, CA PI delay=34

 5100 16:50:58.675010  

 5101 16:50:58.678200  [CBTSetCACLKResult] CA Dly = 34

 5102 16:50:58.678265  CS Dly: 7 (0~39)

 5103 16:50:58.678324  

 5104 16:50:58.681416  ----->DramcWriteLeveling(PI) begin...

 5105 16:50:58.684848  ==

 5106 16:50:58.688512  Dram Type= 6, Freq= 0, CH_0, rank 0

 5107 16:50:58.691427  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5108 16:50:58.691498  ==

 5109 16:50:58.694982  Write leveling (Byte 0): 33 => 33

 5110 16:50:58.698006  Write leveling (Byte 1): 27 => 27

 5111 16:50:58.701324  DramcWriteLeveling(PI) end<-----

 5112 16:50:58.701424  

 5113 16:50:58.701514  ==

 5114 16:50:58.705032  Dram Type= 6, Freq= 0, CH_0, rank 0

 5115 16:50:58.708117  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5116 16:50:58.708216  ==

 5117 16:50:58.711213  [Gating] SW mode calibration

 5118 16:50:58.718061  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5119 16:50:58.724762  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5120 16:50:58.727724   0 14  0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)

 5121 16:50:58.731463   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5122 16:50:58.738139   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5123 16:50:58.741285   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5124 16:50:58.744454   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5125 16:50:58.750866   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5126 16:50:58.754536   0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)

 5127 16:50:58.757608   0 14 28 | B1->B0 | 3030 2525 | 1 0 | (1 1) (0 0)

 5128 16:50:58.764278   0 15  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 5129 16:50:58.767840   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5130 16:50:58.771141   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5131 16:50:58.777628   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5132 16:50:58.781209   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5133 16:50:58.784058   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5134 16:50:58.790909   0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)

 5135 16:50:58.794216   0 15 28 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)

 5136 16:50:58.797429   1  0  0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)

 5137 16:50:58.803988   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5138 16:50:58.807311   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5139 16:50:58.810679   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5140 16:50:58.813821   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5141 16:50:58.820605   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5142 16:50:58.823745   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5143 16:50:58.826958   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5144 16:50:58.833582   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5145 16:50:58.837067   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5146 16:50:58.840669   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5147 16:50:58.847075   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5148 16:50:58.850542   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5149 16:50:58.854679   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5150 16:50:58.860288   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5151 16:50:58.863676   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5152 16:50:58.866769   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5153 16:50:58.873337   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5154 16:50:58.876762   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5155 16:50:58.879743   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5156 16:50:58.886333   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5157 16:50:58.889829   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5158 16:50:58.896330   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5159 16:50:58.899730   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5160 16:50:58.902736   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5161 16:50:58.906002  Total UI for P1: 0, mck2ui 16

 5162 16:50:58.909490  best dqsien dly found for B0: ( 1,  2, 28)

 5163 16:50:58.912709   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5164 16:50:58.916191  Total UI for P1: 0, mck2ui 16

 5165 16:50:58.919563  best dqsien dly found for B1: ( 1,  3,  0)

 5166 16:50:58.926282  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5167 16:50:58.929450  best DQS1 dly(MCK, UI, PI) = (1, 3, 0)

 5168 16:50:58.929534  

 5169 16:50:58.932746  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5170 16:50:58.935732  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5171 16:50:58.939055  [Gating] SW calibration Done

 5172 16:50:58.939136  ==

 5173 16:50:58.942111  Dram Type= 6, Freq= 0, CH_0, rank 0

 5174 16:50:58.945905  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5175 16:50:58.945982  ==

 5176 16:50:58.948861  RX Vref Scan: 0

 5177 16:50:58.948939  

 5178 16:50:58.949038  RX Vref 0 -> 0, step: 1

 5179 16:50:58.949139  

 5180 16:50:58.952504  RX Delay -80 -> 252, step: 8

 5181 16:50:58.955437  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5182 16:50:58.962248  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5183 16:50:58.965711  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5184 16:50:58.968803  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5185 16:50:58.972116  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5186 16:50:58.975694  iDelay=208, Bit 5, Center 99 (8 ~ 191) 184

 5187 16:50:58.978769  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5188 16:50:58.985428  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5189 16:50:58.989101  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5190 16:50:58.992016  iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176

 5191 16:50:58.995445  iDelay=208, Bit 10, Center 91 (0 ~ 183) 184

 5192 16:50:58.998936  iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184

 5193 16:50:59.001856  iDelay=208, Bit 12, Center 91 (0 ~ 183) 184

 5194 16:50:59.008756  iDelay=208, Bit 13, Center 91 (0 ~ 183) 184

 5195 16:50:59.011757  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5196 16:50:59.015425  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5197 16:50:59.015508  ==

 5198 16:50:59.018371  Dram Type= 6, Freq= 0, CH_0, rank 0

 5199 16:50:59.021507  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5200 16:50:59.021590  ==

 5201 16:50:59.024985  DQS Delay:

 5202 16:50:59.025067  DQS0 = 0, DQS1 = 0

 5203 16:50:59.028712  DQM Delay:

 5204 16:50:59.028793  DQM0 = 106, DQM1 = 90

 5205 16:50:59.028858  DQ Delay:

 5206 16:50:59.031384  DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99

 5207 16:50:59.035121  DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115

 5208 16:50:59.037990  DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =83

 5209 16:50:59.044919  DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99

 5210 16:50:59.045003  

 5211 16:50:59.045068  

 5212 16:50:59.045128  ==

 5213 16:50:59.048325  Dram Type= 6, Freq= 0, CH_0, rank 0

 5214 16:50:59.051233  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5215 16:50:59.051315  ==

 5216 16:50:59.051382  

 5217 16:50:59.051442  

 5218 16:50:59.054679  	TX Vref Scan disable

 5219 16:50:59.054760   == TX Byte 0 ==

 5220 16:50:59.061814  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5221 16:50:59.064341  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5222 16:50:59.064452   == TX Byte 1 ==

 5223 16:50:59.071194  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5224 16:50:59.074495  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5225 16:50:59.074577  ==

 5226 16:50:59.077468  Dram Type= 6, Freq= 0, CH_0, rank 0

 5227 16:50:59.081207  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5228 16:50:59.081289  ==

 5229 16:50:59.084058  

 5230 16:50:59.084140  

 5231 16:50:59.084204  	TX Vref Scan disable

 5232 16:50:59.087530   == TX Byte 0 ==

 5233 16:50:59.090737  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5234 16:50:59.097290  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5235 16:50:59.097410   == TX Byte 1 ==

 5236 16:50:59.100793  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5237 16:50:59.107075  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5238 16:50:59.107175  

 5239 16:50:59.107242  [DATLAT]

 5240 16:50:59.107303  Freq=933, CH0 RK0

 5241 16:50:59.107362  

 5242 16:50:59.110674  DATLAT Default: 0xd

 5243 16:50:59.110784  0, 0xFFFF, sum = 0

 5244 16:50:59.114149  1, 0xFFFF, sum = 0

 5245 16:50:59.117144  2, 0xFFFF, sum = 0

 5246 16:50:59.117227  3, 0xFFFF, sum = 0

 5247 16:50:59.120290  4, 0xFFFF, sum = 0

 5248 16:50:59.120373  5, 0xFFFF, sum = 0

 5249 16:50:59.124120  6, 0xFFFF, sum = 0

 5250 16:50:59.124230  7, 0xFFFF, sum = 0

 5251 16:50:59.127395  8, 0xFFFF, sum = 0

 5252 16:50:59.127480  9, 0xFFFF, sum = 0

 5253 16:50:59.130503  10, 0x0, sum = 1

 5254 16:50:59.130583  11, 0x0, sum = 2

 5255 16:50:59.133609  12, 0x0, sum = 3

 5256 16:50:59.133682  13, 0x0, sum = 4

 5257 16:50:59.133745  best_step = 11

 5258 16:50:59.137165  

 5259 16:50:59.137272  ==

 5260 16:50:59.140428  Dram Type= 6, Freq= 0, CH_0, rank 0

 5261 16:50:59.143522  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5262 16:50:59.143605  ==

 5263 16:50:59.143671  RX Vref Scan: 1

 5264 16:50:59.143732  

 5265 16:50:59.146971  RX Vref 0 -> 0, step: 1

 5266 16:50:59.147054  

 5267 16:50:59.150007  RX Delay -53 -> 252, step: 4

 5268 16:50:59.150116  

 5269 16:50:59.153315  Set Vref, RX VrefLevel [Byte0]: 60

 5270 16:50:59.156623                           [Byte1]: 49

 5271 16:50:59.156705  

 5272 16:50:59.160250  Final RX Vref Byte 0 = 60 to rank0

 5273 16:50:59.163726  Final RX Vref Byte 1 = 49 to rank0

 5274 16:50:59.166772  Final RX Vref Byte 0 = 60 to rank1

 5275 16:50:59.170152  Final RX Vref Byte 1 = 49 to rank1==

 5276 16:50:59.174069  Dram Type= 6, Freq= 0, CH_0, rank 0

 5277 16:50:59.179750  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5278 16:50:59.179837  ==

 5279 16:50:59.179933  DQS Delay:

 5280 16:50:59.180032  DQS0 = 0, DQS1 = 0

 5281 16:50:59.183458  DQM Delay:

 5282 16:50:59.183557  DQM0 = 107, DQM1 = 92

 5283 16:51:00.674912  DQ Delay:

 5284 16:51:00.675359  DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =104

 5285 16:51:00.675486  DQ4 =110, DQ5 =98, DQ6 =118, DQ7 =114

 5286 16:51:00.675578  DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =90

 5287 16:51:00.675676  DQ12 =94, DQ13 =96, DQ14 =104, DQ15 =100

 5288 16:51:00.675774  

 5289 16:51:00.675870  

 5290 16:51:00.675965  [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps

 5291 16:51:00.676059  CH0 RK0: MR19=505, MR18=2420

 5292 16:51:00.676154  CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42

 5293 16:51:00.676246  

 5294 16:51:00.676340  ----->DramcWriteLeveling(PI) begin...

 5295 16:51:00.676433  ==

 5296 16:51:00.676526  Dram Type= 6, Freq= 0, CH_0, rank 1

 5297 16:51:00.676638  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5298 16:51:00.676778  ==

 5299 16:51:00.676865  Write leveling (Byte 0): 33 => 33

 5300 16:51:00.676947  Write leveling (Byte 1): 28 => 28

 5301 16:51:00.677027  DramcWriteLeveling(PI) end<-----

 5302 16:51:00.677112  

 5303 16:51:00.677197  ==

 5304 16:51:00.677283  Dram Type= 6, Freq= 0, CH_0, rank 1

 5305 16:51:00.677364  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5306 16:51:00.677444  ==

 5307 16:51:00.677527  [Gating] SW mode calibration

 5308 16:51:00.677586  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5309 16:51:00.677654  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5310 16:51:00.677711   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5311 16:51:00.677766   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5312 16:51:00.677819   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5313 16:51:00.677871   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5314 16:51:00.677924   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5315 16:51:00.677976   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5316 16:51:00.678027   0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)

 5317 16:51:00.678079   0 14 28 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)

 5318 16:51:00.678130   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5319 16:51:00.678182   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5320 16:51:00.678233   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5321 16:51:00.678284   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5322 16:51:00.678335   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5323 16:51:00.678426   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5324 16:51:00.678478   0 15 24 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)

 5325 16:51:00.678529   0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)

 5326 16:51:00.678581   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5327 16:51:00.678632   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5328 16:51:00.678683   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5329 16:51:00.678735   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5330 16:51:00.678786   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5331 16:51:00.678838   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5332 16:51:00.678889   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5333 16:51:00.678941   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5334 16:51:00.678995   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5335 16:51:00.679047   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5336 16:51:00.679098   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5337 16:51:00.679149   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5338 16:51:00.679201   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5339 16:51:00.679253   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5340 16:51:00.679304   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5341 16:51:00.679355   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5342 16:51:00.679407   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5343 16:51:00.679458   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5344 16:51:00.679509   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5345 16:51:00.679560   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5346 16:51:00.679612   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5347 16:51:00.679663   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5348 16:51:00.679714   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5349 16:51:00.679765   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5350 16:51:00.679817   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5351 16:51:00.679868  Total UI for P1: 0, mck2ui 16

 5352 16:51:00.679920  best dqsien dly found for B0: ( 1,  2, 26)

 5353 16:51:00.679972  Total UI for P1: 0, mck2ui 16

 5354 16:51:00.680023  best dqsien dly found for B1: ( 1,  2, 26)

 5355 16:51:00.680074  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5356 16:51:00.680125  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5357 16:51:00.680177  

 5358 16:51:00.680228  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5359 16:51:00.680280  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5360 16:51:00.680331  [Gating] SW calibration Done

 5361 16:51:00.680382  ==

 5362 16:51:00.680434  Dram Type= 6, Freq= 0, CH_0, rank 1

 5363 16:51:00.680486  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5364 16:51:00.680537  ==

 5365 16:51:00.680618  RX Vref Scan: 0

 5366 16:51:00.680717  

 5367 16:51:00.680802  RX Vref 0 -> 0, step: 1

 5368 16:51:00.680897  

 5369 16:51:00.680988  RX Delay -80 -> 252, step: 8

 5370 16:51:00.681068  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5371 16:51:00.681149  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5372 16:51:00.681219  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5373 16:51:00.681271  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5374 16:51:00.681324  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5375 16:51:00.681392  iDelay=208, Bit 5, Center 95 (0 ~ 191) 192

 5376 16:51:00.681459  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5377 16:51:00.681540  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5378 16:51:00.681591  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5379 16:51:00.681643  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5380 16:51:00.681694  iDelay=208, Bit 10, Center 91 (0 ~ 183) 184

 5381 16:51:00.681746  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5382 16:51:00.681797  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5383 16:51:00.681848  iDelay=208, Bit 13, Center 91 (0 ~ 183) 184

 5384 16:51:00.682106  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5385 16:51:00.682167  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5386 16:51:00.682219  ==

 5387 16:51:00.682272  Dram Type= 6, Freq= 0, CH_0, rank 1

 5388 16:51:00.682323  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5389 16:51:00.682414  ==

 5390 16:51:00.682507  DQS Delay:

 5391 16:51:00.682586  DQS0 = 0, DQS1 = 0

 5392 16:51:00.682636  DQM Delay:

 5393 16:51:00.682715  DQM0 = 105, DQM1 = 91

 5394 16:51:00.682793  DQ Delay:

 5395 16:51:00.682843  DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99

 5396 16:51:00.682909  DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115

 5397 16:51:00.682980  DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87

 5398 16:51:00.683074  DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99

 5399 16:51:00.683166  

 5400 16:51:00.683215  

 5401 16:51:00.683280  ==

 5402 16:51:00.683370  Dram Type= 6, Freq= 0, CH_0, rank 1

 5403 16:51:00.683421  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5404 16:51:00.683472  ==

 5405 16:51:00.683521  

 5406 16:51:00.683600  

 5407 16:51:00.683690  	TX Vref Scan disable

 5408 16:51:00.683753   == TX Byte 0 ==

 5409 16:51:00.683803  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5410 16:51:00.683870  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5411 16:51:00.683962   == TX Byte 1 ==

 5412 16:51:00.684012  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5413 16:51:00.684063  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5414 16:51:00.684128  ==

 5415 16:51:00.684205  Dram Type= 6, Freq= 0, CH_0, rank 1

 5416 16:51:00.684295  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5417 16:51:00.684346  ==

 5418 16:51:00.684409  

 5419 16:51:00.684499  

 5420 16:51:00.684575  	TX Vref Scan disable

 5421 16:51:00.684682   == TX Byte 0 ==

 5422 16:51:00.684792  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5423 16:51:00.684875  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5424 16:51:00.684952   == TX Byte 1 ==

 5425 16:51:00.685029  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5426 16:51:00.685107  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5427 16:51:00.685163  

 5428 16:51:00.685216  [DATLAT]

 5429 16:51:00.685268  Freq=933, CH0 RK1

 5430 16:51:00.685320  

 5431 16:51:00.685371  DATLAT Default: 0xb

 5432 16:51:00.685423  0, 0xFFFF, sum = 0

 5433 16:51:00.685476  1, 0xFFFF, sum = 0

 5434 16:51:00.685528  2, 0xFFFF, sum = 0

 5435 16:51:00.685580  3, 0xFFFF, sum = 0

 5436 16:51:00.685644  4, 0xFFFF, sum = 0

 5437 16:51:00.685695  5, 0xFFFF, sum = 0

 5438 16:51:00.685746  6, 0xFFFF, sum = 0

 5439 16:51:00.685810  7, 0xFFFF, sum = 0

 5440 16:51:00.685901  8, 0xFFFF, sum = 0

 5441 16:51:00.685979  9, 0xFFFF, sum = 0

 5442 16:51:00.686043  10, 0x0, sum = 1

 5443 16:51:00.686120  11, 0x0, sum = 2

 5444 16:51:00.686172  12, 0x0, sum = 3

 5445 16:51:00.686223  13, 0x0, sum = 4

 5446 16:51:00.686275  best_step = 11

 5447 16:51:00.686325  

 5448 16:51:00.686431  ==

 5449 16:51:00.686522  Dram Type= 6, Freq= 0, CH_0, rank 1

 5450 16:51:00.686574  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5451 16:51:00.686626  ==

 5452 16:51:00.686704  RX Vref Scan: 0

 5453 16:51:00.686755  

 5454 16:51:00.686806  RX Vref 0 -> 0, step: 1

 5455 16:51:00.686857  

 5456 16:51:00.686908  RX Delay -53 -> 252, step: 4

 5457 16:51:00.686958  iDelay=203, Bit 0, Center 104 (19 ~ 190) 172

 5458 16:51:00.687009  iDelay=203, Bit 1, Center 106 (19 ~ 194) 176

 5459 16:51:00.687073  iDelay=203, Bit 2, Center 100 (15 ~ 186) 172

 5460 16:51:00.687123  iDelay=203, Bit 3, Center 98 (15 ~ 182) 168

 5461 16:51:00.687187  iDelay=203, Bit 4, Center 104 (19 ~ 190) 172

 5462 16:51:00.687277  iDelay=203, Bit 5, Center 96 (11 ~ 182) 172

 5463 16:51:00.687326  iDelay=203, Bit 6, Center 114 (27 ~ 202) 176

 5464 16:51:00.687376  iDelay=203, Bit 7, Center 112 (27 ~ 198) 172

 5465 16:51:00.687440  iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172

 5466 16:51:00.687517  iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164

 5467 16:51:00.687593  iDelay=203, Bit 10, Center 94 (11 ~ 178) 168

 5468 16:51:00.687644  iDelay=203, Bit 11, Center 92 (11 ~ 174) 164

 5469 16:51:00.687695  iDelay=203, Bit 12, Center 96 (11 ~ 182) 172

 5470 16:51:00.687746  iDelay=203, Bit 13, Center 94 (11 ~ 178) 168

 5471 16:51:00.687797  iDelay=203, Bit 14, Center 102 (15 ~ 190) 176

 5472 16:51:00.687847  iDelay=203, Bit 15, Center 96 (11 ~ 182) 172

 5473 16:51:00.687911  ==

 5474 16:51:00.687975  Dram Type= 6, Freq= 0, CH_0, rank 1

 5475 16:51:00.688027  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5476 16:51:00.688078  ==

 5477 16:51:00.688128  DQS Delay:

 5478 16:51:00.688178  DQS0 = 0, DQS1 = 0

 5479 16:51:00.688229  DQM Delay:

 5480 16:51:00.688318  DQM0 = 104, DQM1 = 92

 5481 16:51:00.688368  DQ Delay:

 5482 16:51:00.688417  DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98

 5483 16:51:00.688482  DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =112

 5484 16:51:00.688558  DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92

 5485 16:51:00.688608  DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =96

 5486 16:51:00.688659  

 5487 16:51:00.688709  

 5488 16:51:00.688760  [DQSOSCAuto] RK1, (LSB)MR18= 0x2506, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 410 ps

 5489 16:51:00.688824  CH0 RK1: MR19=505, MR18=2506

 5490 16:51:00.688874  CH0_RK1: MR19=0x505, MR18=0x2506, DQSOSC=410, MR23=63, INC=64, DEC=42

 5491 16:51:00.688938  [RxdqsGatingPostProcess] freq 933

 5492 16:51:00.689058  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5493 16:51:00.689186  best DQS0 dly(2T, 0.5T) = (0, 10)

 5494 16:51:00.689278  best DQS1 dly(2T, 0.5T) = (0, 11)

 5495 16:51:00.689382  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5496 16:51:00.689459  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5497 16:51:00.689529  best DQS0 dly(2T, 0.5T) = (0, 10)

 5498 16:51:00.689583  best DQS1 dly(2T, 0.5T) = (0, 10)

 5499 16:51:00.689648  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5500 16:51:00.689726  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5501 16:51:00.689776  Pre-setting of DQS Precalculation

 5502 16:51:00.689840  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5503 16:51:00.689931  ==

 5504 16:51:00.689982  Dram Type= 6, Freq= 0, CH_1, rank 0

 5505 16:51:00.690033  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5506 16:51:00.690097  ==

 5507 16:51:00.690174  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5508 16:51:00.690226  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31

 5509 16:51:00.690277  [CA 0] Center 37 (7~68) winsize 62

 5510 16:51:00.690329  [CA 1] Center 37 (7~68) winsize 62

 5511 16:51:00.690423  [CA 2] Center 35 (5~66) winsize 62

 5512 16:51:00.690519  [CA 3] Center 34 (4~65) winsize 62

 5513 16:51:00.690586  [CA 4] Center 35 (5~66) winsize 62

 5514 16:51:00.690662  [CA 5] Center 34 (4~65) winsize 62

 5515 16:51:00.690739  

 5516 16:51:00.690790  [CmdBusTrainingLP45] Vref(ca) range 1: 31

 5517 16:51:00.690853  

 5518 16:51:00.690903  [CATrainingPosCal] consider 1 rank data

 5519 16:51:00.690993  u2DelayCellTimex100 = 270/100 ps

 5520 16:51:00.691056  CA0 delay=37 (7~68),Diff = 3 PI (18 cell)

 5521 16:51:00.691106  CA1 delay=37 (7~68),Diff = 3 PI (18 cell)

 5522 16:51:00.691156  CA2 delay=35 (5~66),Diff = 1 PI (6 cell)

 5523 16:51:00.691422  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 5524 16:51:00.691479  CA4 delay=35 (5~66),Diff = 1 PI (6 cell)

 5525 16:51:00.691530  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 5526 16:51:00.691580  

 5527 16:51:00.691631  CA PerBit enable=1, Macro0, CA PI delay=34

 5528 16:51:00.691682  

 5529 16:51:00.691732  [CBTSetCACLKResult] CA Dly = 34

 5530 16:51:00.691782  CS Dly: 6 (0~37)

 5531 16:51:00.691849  ==

 5532 16:51:00.691939  Dram Type= 6, Freq= 0, CH_1, rank 1

 5533 16:51:00.691990  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5534 16:51:00.692053  ==

 5535 16:51:00.692117  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5536 16:51:00.692168  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5537 16:51:00.692232  [CA 0] Center 37 (7~68) winsize 62

 5538 16:51:00.692295  [CA 1] Center 38 (7~69) winsize 63

 5539 16:51:00.692372  [CA 2] Center 35 (5~66) winsize 62

 5540 16:51:00.692435  [CA 3] Center 35 (5~66) winsize 62

 5541 16:51:00.692486  [CA 4] Center 35 (5~66) winsize 62

 5542 16:51:00.692536  [CA 5] Center 34 (5~64) winsize 60

 5543 16:51:00.692587  

 5544 16:51:00.692650  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5545 16:51:00.692699  

 5546 16:51:00.692749  [CATrainingPosCal] consider 2 rank data

 5547 16:51:00.692799  u2DelayCellTimex100 = 270/100 ps

 5548 16:51:00.692862  CA0 delay=37 (7~68),Diff = 3 PI (18 cell)

 5549 16:51:00.692945  CA1 delay=37 (7~68),Diff = 3 PI (18 cell)

 5550 16:51:00.693008  CA2 delay=35 (5~66),Diff = 1 PI (6 cell)

 5551 16:51:00.693058  CA3 delay=35 (5~65),Diff = 1 PI (6 cell)

 5552 16:51:00.693122  CA4 delay=35 (5~66),Diff = 1 PI (6 cell)

 5553 16:51:00.693185  CA5 delay=34 (5~64),Diff = 0 PI (0 cell)

 5554 16:51:00.693234  

 5555 16:51:00.693284  CA PerBit enable=1, Macro0, CA PI delay=34

 5556 16:51:00.693334  

 5557 16:51:00.693411  [CBTSetCACLKResult] CA Dly = 34

 5558 16:51:00.693461  CS Dly: 7 (0~39)

 5559 16:51:00.693524  

 5560 16:51:00.693632  ----->DramcWriteLeveling(PI) begin...

 5561 16:51:00.693731  ==

 5562 16:51:00.693810  Dram Type= 6, Freq= 0, CH_1, rank 0

 5563 16:51:00.693886  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5564 16:51:00.693989  ==

 5565 16:51:00.694060  Write leveling (Byte 0): 28 => 28

 5566 16:51:00.694114  Write leveling (Byte 1): 29 => 29

 5567 16:51:00.694166  DramcWriteLeveling(PI) end<-----

 5568 16:51:00.694231  

 5569 16:51:00.694282  ==

 5570 16:51:00.694334  Dram Type= 6, Freq= 0, CH_1, rank 0

 5571 16:51:00.694427  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5572 16:51:00.694481  ==

 5573 16:51:00.694533  [Gating] SW mode calibration

 5574 16:51:00.694584  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5575 16:51:00.694636  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5576 16:51:00.694688   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5577 16:51:00.694739   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5578 16:51:00.694791   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5579 16:51:00.694842   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5580 16:51:00.694892   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5581 16:51:00.694943   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5582 16:51:00.695035   0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (1 0) (1 0)

 5583 16:51:00.695100   0 14 28 | B1->B0 | 2626 2424 | 0 0 | (0 1) (1 1)

 5584 16:51:00.695163   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5585 16:51:00.695213   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5586 16:51:00.695263   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5587 16:51:00.695313   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5588 16:51:00.695390   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5589 16:51:00.695439   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5590 16:51:00.695490   0 15 24 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (0 0)

 5591 16:51:00.695539   0 15 28 | B1->B0 | 4141 4242 | 1 0 | (0 0) (0 0)

 5592 16:51:00.695589   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5593 16:51:00.695653   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5594 16:51:00.695717   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5595 16:51:00.695767   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5596 16:51:00.695817   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5597 16:51:00.695867   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5598 16:51:00.695944   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5599 16:51:00.695994   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5600 16:51:00.696045   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5601 16:51:00.696094   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5602 16:51:00.696158   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5603 16:51:00.696237   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5604 16:51:00.696301   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5605 16:51:00.696351   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5606 16:51:00.696402   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5607 16:51:00.696479   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5608 16:51:00.696530   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5609 16:51:00.696579   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5610 16:51:00.696630   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5611 16:51:00.696680   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5612 16:51:00.696744   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5613 16:51:00.696807   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5614 16:51:00.696857   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5615 16:51:00.696940   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5616 16:51:00.696994  Total UI for P1: 0, mck2ui 16

 5617 16:51:00.697046  best dqsien dly found for B0: ( 1,  2, 24)

 5618 16:51:00.697110  Total UI for P1: 0, mck2ui 16

 5619 16:51:00.697160  best dqsien dly found for B1: ( 1,  2, 26)

 5620 16:51:00.697210  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5621 16:51:00.697260  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5622 16:51:00.697310  

 5623 16:51:00.697360  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5624 16:51:00.697411  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5625 16:51:00.697460  [Gating] SW calibration Done

 5626 16:51:00.697510  ==

 5627 16:51:00.697561  Dram Type= 6, Freq= 0, CH_1, rank 0

 5628 16:51:00.697611  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5629 16:51:00.697900  ==

 5630 16:51:00.697990  RX Vref Scan: 0

 5631 16:51:00.698070  

 5632 16:51:00.698141  RX Vref 0 -> 0, step: 1

 5633 16:51:00.698196  

 5634 16:51:00.698247  RX Delay -80 -> 252, step: 8

 5635 16:51:00.698299  iDelay=208, Bit 0, Center 103 (16 ~ 191) 176

 5636 16:51:00.698373  iDelay=208, Bit 1, Center 95 (8 ~ 183) 176

 5637 16:51:00.698455  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5638 16:51:00.698505  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5639 16:51:00.698556  iDelay=208, Bit 4, Center 103 (16 ~ 191) 176

 5640 16:51:00.698607  iDelay=208, Bit 5, Center 111 (24 ~ 199) 176

 5641 16:51:00.698657  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5642 16:51:00.698708  iDelay=208, Bit 7, Center 99 (8 ~ 191) 184

 5643 16:51:00.698759  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5644 16:51:00.698809  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5645 16:51:00.698859  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5646 16:51:00.698909  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5647 16:51:00.698965  iDelay=208, Bit 12, Center 103 (8 ~ 199) 192

 5648 16:51:00.699016  iDelay=208, Bit 13, Center 103 (8 ~ 199) 192

 5649 16:51:00.699066  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5650 16:51:00.699115  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5651 16:51:00.699165  ==

 5652 16:51:00.699216  Dram Type= 6, Freq= 0, CH_1, rank 0

 5653 16:51:00.699266  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5654 16:51:00.699317  ==

 5655 16:51:00.699368  DQS Delay:

 5656 16:51:00.699418  DQS0 = 0, DQS1 = 0

 5657 16:51:00.699468  DQM Delay:

 5658 16:51:00.699518  DQM0 = 101, DQM1 = 95

 5659 16:51:00.699568  DQ Delay:

 5660 16:51:00.699618  DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99

 5661 16:51:00.699668  DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99

 5662 16:51:00.699735  DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91

 5663 16:51:00.699799  DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99

 5664 16:51:00.699849  

 5665 16:51:00.699899  

 5666 16:51:00.699967  ==

 5667 16:51:00.700039  Dram Type= 6, Freq= 0, CH_1, rank 0

 5668 16:51:00.700091  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5669 16:51:00.700142  ==

 5670 16:51:00.700192  

 5671 16:51:00.700242  

 5672 16:51:00.700291  	TX Vref Scan disable

 5673 16:51:00.700342   == TX Byte 0 ==

 5674 16:51:00.700393  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5675 16:51:00.700444  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5676 16:51:00.700494   == TX Byte 1 ==

 5677 16:51:00.700544  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5678 16:51:00.700595  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5679 16:51:00.700645  ==

 5680 16:51:00.700695  Dram Type= 6, Freq= 0, CH_1, rank 0

 5681 16:51:00.700745  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5682 16:51:00.700796  ==

 5683 16:51:00.700845  

 5684 16:51:00.700896  

 5685 16:51:00.700979  	TX Vref Scan disable

 5686 16:51:00.701045   == TX Byte 0 ==

 5687 16:51:00.701096  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5688 16:51:00.701147  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5689 16:51:00.701197   == TX Byte 1 ==

 5690 16:51:00.701248  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5691 16:51:00.701297  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5692 16:51:00.701348  

 5693 16:51:00.701398  [DATLAT]

 5694 16:51:00.701447  Freq=933, CH1 RK0

 5695 16:51:00.701498  

 5696 16:51:00.701547  DATLAT Default: 0xd

 5697 16:51:00.701598  0, 0xFFFF, sum = 0

 5698 16:51:00.701649  1, 0xFFFF, sum = 0

 5699 16:51:00.701701  2, 0xFFFF, sum = 0

 5700 16:51:00.701752  3, 0xFFFF, sum = 0

 5701 16:51:00.701804  4, 0xFFFF, sum = 0

 5702 16:51:00.701855  5, 0xFFFF, sum = 0

 5703 16:51:00.701905  6, 0xFFFF, sum = 0

 5704 16:51:00.701957  7, 0xFFFF, sum = 0

 5705 16:51:00.702007  8, 0xFFFF, sum = 0

 5706 16:51:00.702058  9, 0xFFFF, sum = 0

 5707 16:51:00.702122  10, 0x0, sum = 1

 5708 16:51:00.702191  11, 0x0, sum = 2

 5709 16:51:00.702276  12, 0x0, sum = 3

 5710 16:51:00.702382  13, 0x0, sum = 4

 5711 16:51:00.702489  best_step = 11

 5712 16:51:00.702579  

 5713 16:51:00.702671  ==

 5714 16:51:00.702729  Dram Type= 6, Freq= 0, CH_1, rank 0

 5715 16:51:00.702798  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5716 16:51:00.702863  ==

 5717 16:51:00.702914  RX Vref Scan: 1

 5718 16:51:00.703003  

 5719 16:51:00.703070  RX Vref 0 -> 0, step: 1

 5720 16:51:00.703121  

 5721 16:51:00.703189  RX Delay -53 -> 252, step: 4

 5722 16:51:00.703254  

 5723 16:51:00.703305  Set Vref, RX VrefLevel [Byte0]: 51

 5724 16:51:00.703356                           [Byte1]: 52

 5725 16:51:00.703406  

 5726 16:51:00.703458  Final RX Vref Byte 0 = 51 to rank0

 5727 16:51:00.703522  Final RX Vref Byte 1 = 52 to rank0

 5728 16:51:00.703600  Final RX Vref Byte 0 = 51 to rank1

 5729 16:51:00.703651  Final RX Vref Byte 1 = 52 to rank1==

 5730 16:51:00.703702  Dram Type= 6, Freq= 0, CH_1, rank 0

 5731 16:51:00.703779  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5732 16:51:00.703829  ==

 5733 16:51:00.703880  DQS Delay:

 5734 16:51:00.703957  DQS0 = 0, DQS1 = 0

 5735 16:51:00.704008  DQM Delay:

 5736 16:51:00.704058  DQM0 = 104, DQM1 = 97

 5737 16:51:00.704121  DQ Delay:

 5738 16:51:00.704184  DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102

 5739 16:51:00.704234  DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102

 5740 16:51:00.704284  DQ8 =86, DQ9 =86, DQ10 =102, DQ11 =92

 5741 16:51:00.704334  DQ12 =106, DQ13 =100, DQ14 =104, DQ15 =104

 5742 16:51:00.704384  

 5743 16:51:00.704434  

 5744 16:51:00.704483  [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps

 5745 16:51:00.704534  CH1 RK0: MR19=505, MR18=1A32

 5746 16:51:00.704584  CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43

 5747 16:51:00.704635  

 5748 16:51:00.704685  ----->DramcWriteLeveling(PI) begin...

 5749 16:51:00.704735  ==

 5750 16:51:00.704801  Dram Type= 6, Freq= 0, CH_1, rank 1

 5751 16:51:00.704852  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5752 16:51:00.704903  ==

 5753 16:51:00.704974  Write leveling (Byte 0): 26 => 26

 5754 16:51:00.705059  Write leveling (Byte 1): 26 => 26

 5755 16:51:00.705117  DramcWriteLeveling(PI) end<-----

 5756 16:51:00.705169  

 5757 16:51:00.705221  ==

 5758 16:51:00.705272  Dram Type= 6, Freq= 0, CH_1, rank 1

 5759 16:51:00.705323  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5760 16:51:00.705376  ==

 5761 16:51:00.705427  [Gating] SW mode calibration

 5762 16:51:00.705478  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5763 16:51:00.705530  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5764 16:51:00.705582   0 14  0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 5765 16:51:00.705634   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5766 16:51:00.705685   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5767 16:51:00.705737   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5768 16:51:00.705789   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5769 16:51:00.705840   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5770 16:51:00.705891   0 14 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 1)

 5771 16:51:00.705942   0 14 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)

 5772 16:51:00.706015   0 15  0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 5773 16:51:00.706289   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5774 16:51:00.706419   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5775 16:51:00.706546   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5776 16:51:00.706679   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5777 16:51:00.706742   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5778 16:51:00.706796   0 15 24 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)

 5779 16:51:00.706849   0 15 28 | B1->B0 | 3f3f 3636 | 0 0 | (0 0) (0 0)

 5780 16:51:00.706901   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5781 16:51:00.706953   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5782 16:51:00.707004   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5783 16:51:00.707055   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5784 16:51:00.707106   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5785 16:51:00.707158   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5786 16:51:00.707209   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 5787 16:51:00.707260   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5788 16:51:00.707311   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5789 16:51:00.707362   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5790 16:51:00.707413   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5791 16:51:00.707464   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5792 16:51:00.707515   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5793 16:51:00.707566   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5794 16:51:00.707617   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5795 16:51:00.707681   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5796 16:51:00.709933   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5797 16:51:00.716105   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5798 16:51:00.719607   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5799 16:51:00.722818   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5800 16:51:00.729320   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5801 16:51:00.733038   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5802 16:51:00.736081   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5803 16:51:00.742791   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5804 16:51:00.742872  Total UI for P1: 0, mck2ui 16

 5805 16:51:00.746042  best dqsien dly found for B0: ( 1,  2, 26)

 5806 16:51:00.749410  Total UI for P1: 0, mck2ui 16

 5807 16:51:00.753068  best dqsien dly found for B1: ( 1,  2, 26)

 5808 16:51:00.756235  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5809 16:51:00.762640  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5810 16:51:00.762741  

 5811 16:51:00.766190  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5812 16:51:00.769447  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5813 16:51:00.772865  [Gating] SW calibration Done

 5814 16:51:00.772983  ==

 5815 16:51:00.776144  Dram Type= 6, Freq= 0, CH_1, rank 1

 5816 16:51:00.779302  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5817 16:51:00.779486  ==

 5818 16:51:00.782656  RX Vref Scan: 0

 5819 16:51:00.782804  

 5820 16:51:00.782918  RX Vref 0 -> 0, step: 1

 5821 16:51:00.783027  

 5822 16:51:00.785625  RX Delay -80 -> 252, step: 8

 5823 16:51:00.788983  iDelay=200, Bit 0, Center 107 (24 ~ 191) 168

 5824 16:51:00.795614  iDelay=200, Bit 1, Center 99 (16 ~ 183) 168

 5825 16:51:00.799424  iDelay=200, Bit 2, Center 87 (0 ~ 175) 176

 5826 16:51:00.802276  iDelay=200, Bit 3, Center 103 (16 ~ 191) 176

 5827 16:51:00.805647  iDelay=200, Bit 4, Center 103 (16 ~ 191) 176

 5828 16:51:00.809397  iDelay=200, Bit 5, Center 111 (24 ~ 199) 176

 5829 16:51:00.816003  iDelay=200, Bit 6, Center 111 (24 ~ 199) 176

 5830 16:51:00.818904  iDelay=200, Bit 7, Center 103 (16 ~ 191) 176

 5831 16:51:00.822255  iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184

 5832 16:51:00.825780  iDelay=200, Bit 9, Center 87 (0 ~ 175) 176

 5833 16:51:00.828826  iDelay=200, Bit 10, Center 95 (0 ~ 191) 192

 5834 16:51:00.832230  iDelay=200, Bit 11, Center 91 (0 ~ 183) 184

 5835 16:51:00.838300  iDelay=200, Bit 12, Center 107 (16 ~ 199) 184

 5836 16:51:00.841860  iDelay=200, Bit 13, Center 99 (8 ~ 191) 184

 5837 16:51:00.845071  iDelay=200, Bit 14, Center 103 (8 ~ 199) 192

 5838 16:51:00.848312  iDelay=200, Bit 15, Center 103 (8 ~ 199) 192

 5839 16:51:00.848408  ==

 5840 16:51:00.851929  Dram Type= 6, Freq= 0, CH_1, rank 1

 5841 16:51:00.858486  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5842 16:51:00.858599  ==

 5843 16:51:00.858688  DQS Delay:

 5844 16:51:00.858768  DQS0 = 0, DQS1 = 0

 5845 16:51:00.861821  DQM Delay:

 5846 16:51:00.861933  DQM0 = 103, DQM1 = 96

 5847 16:51:00.864991  DQ Delay:

 5848 16:51:00.868405  DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103

 5849 16:51:00.871445  DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103

 5850 16:51:00.875267  DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91

 5851 16:51:00.878508  DQ12 =107, DQ13 =99, DQ14 =103, DQ15 =103

 5852 16:51:00.878682  

 5853 16:51:00.878819  

 5854 16:51:00.878947  ==

 5855 16:51:00.881511  Dram Type= 6, Freq= 0, CH_1, rank 1

 5856 16:51:00.885253  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5857 16:51:00.885456  ==

 5858 16:51:00.885618  

 5859 16:51:00.885766  

 5860 16:51:00.888630  	TX Vref Scan disable

 5861 16:51:00.891559   == TX Byte 0 ==

 5862 16:51:00.895165  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5863 16:51:00.898259  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5864 16:51:00.901462   == TX Byte 1 ==

 5865 16:51:00.905174  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5866 16:51:00.908115  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5867 16:51:00.908582  ==

 5868 16:51:00.911639  Dram Type= 6, Freq= 0, CH_1, rank 1

 5869 16:51:00.918003  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5870 16:51:00.918684  ==

 5871 16:51:00.919264  

 5872 16:51:00.919867  

 5873 16:51:00.920443  	TX Vref Scan disable

 5874 16:51:00.922228   == TX Byte 0 ==

 5875 16:51:00.925274  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5876 16:51:00.931882  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5877 16:51:00.932592   == TX Byte 1 ==

 5878 16:51:00.935402  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5879 16:51:00.941704  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5880 16:51:00.942231  

 5881 16:51:00.942743  [DATLAT]

 5882 16:51:00.943159  Freq=933, CH1 RK1

 5883 16:51:00.943557  

 5884 16:51:00.945763  DATLAT Default: 0xb

 5885 16:51:00.948390  0, 0xFFFF, sum = 0

 5886 16:51:00.948855  1, 0xFFFF, sum = 0

 5887 16:51:00.951750  2, 0xFFFF, sum = 0

 5888 16:51:00.952303  3, 0xFFFF, sum = 0

 5889 16:51:00.955190  4, 0xFFFF, sum = 0

 5890 16:51:00.955659  5, 0xFFFF, sum = 0

 5891 16:51:00.958167  6, 0xFFFF, sum = 0

 5892 16:51:00.958705  7, 0xFFFF, sum = 0

 5893 16:51:00.961725  8, 0xFFFF, sum = 0

 5894 16:51:00.962323  9, 0xFFFF, sum = 0

 5895 16:51:00.964868  10, 0x0, sum = 1

 5896 16:51:00.965362  11, 0x0, sum = 2

 5897 16:51:00.968258  12, 0x0, sum = 3

 5898 16:51:00.968712  13, 0x0, sum = 4

 5899 16:51:00.971601  best_step = 11

 5900 16:51:00.972048  

 5901 16:51:00.972406  ==

 5902 16:51:00.974513  Dram Type= 6, Freq= 0, CH_1, rank 1

 5903 16:51:00.977715  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5904 16:51:00.978179  ==

 5905 16:51:00.978664  RX Vref Scan: 0

 5906 16:51:00.981426  

 5907 16:51:00.981891  RX Vref 0 -> 0, step: 1

 5908 16:51:00.982294  

 5909 16:51:00.984541  RX Delay -53 -> 252, step: 4

 5910 16:51:00.991156  iDelay=199, Bit 0, Center 110 (35 ~ 186) 152

 5911 16:51:00.994756  iDelay=199, Bit 1, Center 98 (19 ~ 178) 160

 5912 16:51:00.997741  iDelay=199, Bit 2, Center 94 (15 ~ 174) 160

 5913 16:51:01.001529  iDelay=199, Bit 3, Center 102 (19 ~ 186) 168

 5914 16:51:01.004504  iDelay=199, Bit 4, Center 104 (23 ~ 186) 164

 5915 16:51:01.011032  iDelay=199, Bit 5, Center 114 (31 ~ 198) 168

 5916 16:51:01.014153  iDelay=199, Bit 6, Center 112 (31 ~ 194) 164

 5917 16:51:01.017570  iDelay=199, Bit 7, Center 102 (23 ~ 182) 160

 5918 16:51:01.020857  iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172

 5919 16:51:01.024008  iDelay=199, Bit 9, Center 88 (3 ~ 174) 172

 5920 16:51:01.027688  iDelay=199, Bit 10, Center 96 (11 ~ 182) 172

 5921 16:51:01.033989  iDelay=199, Bit 11, Center 92 (7 ~ 178) 172

 5922 16:51:01.037421  iDelay=199, Bit 12, Center 104 (19 ~ 190) 172

 5923 16:51:01.040617  iDelay=199, Bit 13, Center 102 (15 ~ 190) 176

 5924 16:51:01.044012  iDelay=199, Bit 14, Center 104 (15 ~ 194) 180

 5925 16:51:01.050472  iDelay=199, Bit 15, Center 106 (19 ~ 194) 176

 5926 16:51:01.050925  ==

 5927 16:51:01.053847  Dram Type= 6, Freq= 0, CH_1, rank 1

 5928 16:51:01.057366  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5929 16:51:01.057864  ==

 5930 16:51:01.058238  DQS Delay:

 5931 16:51:01.060542  DQS0 = 0, DQS1 = 0

 5932 16:51:01.060994  DQM Delay:

 5933 16:51:01.063685  DQM0 = 104, DQM1 = 97

 5934 16:51:01.064145  DQ Delay:

 5935 16:51:01.067150  DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102

 5936 16:51:01.070088  DQ4 =104, DQ5 =114, DQ6 =112, DQ7 =102

 5937 16:51:01.073716  DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92

 5938 16:51:01.077116  DQ12 =104, DQ13 =102, DQ14 =104, DQ15 =106

 5939 16:51:01.077581  

 5940 16:51:01.078039  

 5941 16:51:01.086901  [DQSOSCAuto] RK1, (LSB)MR18= 0x21fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps

 5942 16:51:01.090335  CH1 RK1: MR19=504, MR18=21FE

 5943 16:51:01.093350  CH1_RK1: MR19=0x504, MR18=0x21FE, DQSOSC=411, MR23=63, INC=64, DEC=42

 5944 16:51:01.096982  [RxdqsGatingPostProcess] freq 933

 5945 16:51:01.103275  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5946 16:51:01.106450  best DQS0 dly(2T, 0.5T) = (0, 10)

 5947 16:51:01.109859  best DQS1 dly(2T, 0.5T) = (0, 10)

 5948 16:51:01.113393  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5949 16:51:01.116840  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5950 16:51:01.119816  best DQS0 dly(2T, 0.5T) = (0, 10)

 5951 16:51:01.123194  best DQS1 dly(2T, 0.5T) = (0, 10)

 5952 16:51:01.125994  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5953 16:51:01.129574  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5954 16:51:01.133278  Pre-setting of DQS Precalculation

 5955 16:51:01.136312  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5956 16:51:01.142796  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5957 16:51:01.149608  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5958 16:51:01.152779  

 5959 16:51:01.153412  

 5960 16:51:01.153922  [Calibration Summary] 1866 Mbps

 5961 16:51:01.156180  CH 0, Rank 0

 5962 16:51:01.156801  SW Impedance     : PASS

 5963 16:51:01.159429  DUTY Scan        : NO K

 5964 16:51:01.162779  ZQ Calibration   : PASS

 5965 16:51:01.163416  Jitter Meter     : NO K

 5966 16:51:01.166027  CBT Training     : PASS

 5967 16:51:01.169352  Write leveling   : PASS

 5968 16:51:01.169883  RX DQS gating    : PASS

 5969 16:51:01.172808  RX DQ/DQS(RDDQC) : PASS

 5970 16:51:01.176130  TX DQ/DQS        : PASS

 5971 16:51:01.176759  RX DATLAT        : PASS

 5972 16:51:01.179146  RX DQ/DQS(Engine): PASS

 5973 16:51:01.182856  TX OE            : NO K

 5974 16:51:01.183327  All Pass.

 5975 16:51:01.183703  

 5976 16:51:01.184058  CH 0, Rank 1

 5977 16:51:01.185827  SW Impedance     : PASS

 5978 16:51:01.189094  DUTY Scan        : NO K

 5979 16:51:01.189605  ZQ Calibration   : PASS

 5980 16:51:01.192892  Jitter Meter     : NO K

 5981 16:51:01.195566  CBT Training     : PASS

 5982 16:51:01.196098  Write leveling   : PASS

 5983 16:51:01.198928  RX DQS gating    : PASS

 5984 16:51:01.202476  RX DQ/DQS(RDDQC) : PASS

 5985 16:51:01.202983  TX DQ/DQS        : PASS

 5986 16:51:01.205381  RX DATLAT        : PASS

 5987 16:51:01.209066  RX DQ/DQS(Engine): PASS

 5988 16:51:01.209683  TX OE            : NO K

 5989 16:51:01.210130  All Pass.

 5990 16:51:01.212383  

 5991 16:51:01.213004  CH 1, Rank 0

 5992 16:51:01.215559  SW Impedance     : PASS

 5993 16:51:01.216200  DUTY Scan        : NO K

 5994 16:51:01.218810  ZQ Calibration   : PASS

 5995 16:51:01.221704  Jitter Meter     : NO K

 5996 16:51:01.222292  CBT Training     : PASS

 5997 16:51:01.225192  Write leveling   : PASS

 5998 16:51:01.225818  RX DQS gating    : PASS

 5999 16:51:01.228579  RX DQ/DQS(RDDQC) : PASS

 6000 16:51:01.232093  TX DQ/DQS        : PASS

 6001 16:51:01.232641  RX DATLAT        : PASS

 6002 16:51:01.235174  RX DQ/DQS(Engine): PASS

 6003 16:51:01.238255  TX OE            : NO K

 6004 16:51:01.238805  All Pass.

 6005 16:51:01.239247  

 6006 16:51:01.239655  CH 1, Rank 1

 6007 16:51:01.242291  SW Impedance     : PASS

 6008 16:51:01.244881  DUTY Scan        : NO K

 6009 16:51:01.245405  ZQ Calibration   : PASS

 6010 16:51:01.248424  Jitter Meter     : NO K

 6011 16:51:01.251537  CBT Training     : PASS

 6012 16:51:01.251999  Write leveling   : PASS

 6013 16:51:01.254924  RX DQS gating    : PASS

 6014 16:51:01.258068  RX DQ/DQS(RDDQC) : PASS

 6015 16:51:01.258647  TX DQ/DQS        : PASS

 6016 16:51:01.261301  RX DATLAT        : PASS

 6017 16:51:01.264855  RX DQ/DQS(Engine): PASS

 6018 16:51:01.265467  TX OE            : NO K

 6019 16:51:01.268130  All Pass.

 6020 16:51:01.268749  

 6021 16:51:01.269315  DramC Write-DBI off

 6022 16:51:01.271368  	PER_BANK_REFRESH: Hybrid Mode

 6023 16:51:01.271896  TX_TRACKING: ON

 6024 16:51:01.281197  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6025 16:51:01.284917  [FAST_K] Save calibration result to emmc

 6026 16:51:01.287778  dramc_set_vcore_voltage set vcore to 650000

 6027 16:51:01.291258  Read voltage for 400, 6

 6028 16:51:01.291799  Vio18 = 0

 6029 16:51:01.294414  Vcore = 650000

 6030 16:51:01.294926  Vdram = 0

 6031 16:51:01.295501  Vddq = 0

 6032 16:51:01.297822  Vmddr = 0

 6033 16:51:01.301086  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6034 16:51:01.307680  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6035 16:51:01.308310  MEM_TYPE=3, freq_sel=20

 6036 16:51:01.310759  sv_algorithm_assistance_LP4_800 

 6037 16:51:01.317322  ============ PULL DRAM RESETB DOWN ============

 6038 16:51:01.321167  ========== PULL DRAM RESETB DOWN end =========

 6039 16:51:01.324435  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6040 16:51:01.327561  =================================== 

 6041 16:51:01.330748  LPDDR4 DRAM CONFIGURATION

 6042 16:51:01.334043  =================================== 

 6043 16:51:01.337087  EX_ROW_EN[0]    = 0x0

 6044 16:51:01.337520  EX_ROW_EN[1]    = 0x0

 6045 16:51:01.340536  LP4Y_EN      = 0x0

 6046 16:51:01.340965  WORK_FSP     = 0x0

 6047 16:51:01.344120  WL           = 0x2

 6048 16:51:01.344550  RL           = 0x2

 6049 16:51:01.347225  BL           = 0x2

 6050 16:51:01.347800  RPST         = 0x0

 6051 16:51:01.350409  RD_PRE       = 0x0

 6052 16:51:01.350937  WR_PRE       = 0x1

 6053 16:51:01.354068  WR_PST       = 0x0

 6054 16:51:01.354589  DBI_WR       = 0x0

 6055 16:51:01.357455  DBI_RD       = 0x0

 6056 16:51:01.357969  OTF          = 0x1

 6057 16:51:01.360892  =================================== 

 6058 16:51:01.364020  =================================== 

 6059 16:51:01.367044  ANA top config

 6060 16:51:01.370708  =================================== 

 6061 16:51:01.373591  DLL_ASYNC_EN            =  0

 6062 16:51:01.374123  ALL_SLAVE_EN            =  1

 6063 16:51:01.376955  NEW_RANK_MODE           =  1

 6064 16:51:01.380394  DLL_IDLE_MODE           =  1

 6065 16:51:01.383599  LP45_APHY_COMB_EN       =  1

 6066 16:51:01.384174  TX_ODT_DIS              =  1

 6067 16:51:01.386751  NEW_8X_MODE             =  1

 6068 16:51:01.390236  =================================== 

 6069 16:51:01.393398  =================================== 

 6070 16:51:01.396871  data_rate                  =  800

 6071 16:51:01.400555  CKR                        = 1

 6072 16:51:01.403446  DQ_P2S_RATIO               = 4

 6073 16:51:01.407096  =================================== 

 6074 16:51:01.410112  CA_P2S_RATIO               = 4

 6075 16:51:01.410679  DQ_CA_OPEN                 = 0

 6076 16:51:01.413808  DQ_SEMI_OPEN               = 1

 6077 16:51:01.417002  CA_SEMI_OPEN               = 1

 6078 16:51:01.420059  CA_FULL_RATE               = 0

 6079 16:51:01.423340  DQ_CKDIV4_EN               = 0

 6080 16:51:01.426563  CA_CKDIV4_EN               = 1

 6081 16:51:01.427082  CA_PREDIV_EN               = 0

 6082 16:51:01.429765  PH8_DLY                    = 0

 6083 16:51:01.433468  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6084 16:51:01.436641  DQ_AAMCK_DIV               = 0

 6085 16:51:01.439815  CA_AAMCK_DIV               = 0

 6086 16:51:01.443810  CA_ADMCK_DIV               = 4

 6087 16:51:01.444282  DQ_TRACK_CA_EN             = 0

 6088 16:51:01.446673  CA_PICK                    = 800

 6089 16:51:01.449901  CA_MCKIO                   = 400

 6090 16:51:01.453081  MCKIO_SEMI                 = 400

 6091 16:51:01.456714  PLL_FREQ                   = 3016

 6092 16:51:01.459774  DQ_UI_PI_RATIO             = 32

 6093 16:51:01.463245  CA_UI_PI_RATIO             = 32

 6094 16:51:01.466507  =================================== 

 6095 16:51:01.469722  =================================== 

 6096 16:51:01.470142  memory_type:LPDDR4         

 6097 16:51:01.473234  GP_NUM     : 10       

 6098 16:51:01.476189  SRAM_EN    : 1       

 6099 16:51:01.476608  MD32_EN    : 0       

 6100 16:51:01.479561  =================================== 

 6101 16:51:01.483112  [ANA_INIT] >>>>>>>>>>>>>> 

 6102 16:51:01.486216  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6103 16:51:01.489418  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6104 16:51:01.492711  =================================== 

 6105 16:51:01.496168  data_rate = 800,PCW = 0X7400

 6106 16:51:01.499594  =================================== 

 6107 16:51:01.502641  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6108 16:51:01.505971  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6109 16:51:01.519211  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6110 16:51:01.522610  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6111 16:51:01.525752  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6112 16:51:01.529199  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6113 16:51:01.532496  [ANA_INIT] flow start 

 6114 16:51:01.535880  [ANA_INIT] PLL >>>>>>>> 

 6115 16:51:01.536312  [ANA_INIT] PLL <<<<<<<< 

 6116 16:51:01.539138  [ANA_INIT] MIDPI >>>>>>>> 

 6117 16:51:01.542045  [ANA_INIT] MIDPI <<<<<<<< 

 6118 16:51:01.545628  [ANA_INIT] DLL >>>>>>>> 

 6119 16:51:01.546055  [ANA_INIT] flow end 

 6120 16:51:01.548937  ============ LP4 DIFF to SE enter ============

 6121 16:51:01.555315  ============ LP4 DIFF to SE exit  ============

 6122 16:51:01.555746  [ANA_INIT] <<<<<<<<<<<<< 

 6123 16:51:01.558847  [Flow] Enable top DCM control >>>>> 

 6124 16:51:01.562029  [Flow] Enable top DCM control <<<<< 

 6125 16:51:01.565517  Enable DLL master slave shuffle 

 6126 16:51:01.572297  ============================================================== 

 6127 16:51:01.572840  Gating Mode config

 6128 16:51:01.578804  ============================================================== 

 6129 16:51:01.581968  Config description: 

 6130 16:51:01.591843  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6131 16:51:01.599349  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6132 16:51:01.602108  SELPH_MODE            0: By rank         1: By Phase 

 6133 16:51:01.608273  ============================================================== 

 6134 16:51:01.611669  GAT_TRACK_EN                 =  0

 6135 16:51:01.615103  RX_GATING_MODE               =  2

 6136 16:51:01.615604  RX_GATING_TRACK_MODE         =  2

 6137 16:51:01.618116  SELPH_MODE                   =  1

 6138 16:51:01.621519  PICG_EARLY_EN                =  1

 6139 16:51:01.624823  VALID_LAT_VALUE              =  1

 6140 16:51:01.631464  ============================================================== 

 6141 16:51:01.635066  Enter into Gating configuration >>>> 

 6142 16:51:01.637847  Exit from Gating configuration <<<< 

 6143 16:51:01.641107  Enter into  DVFS_PRE_config >>>>> 

 6144 16:51:01.651046  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6145 16:51:01.654708  Exit from  DVFS_PRE_config <<<<< 

 6146 16:51:01.657566  Enter into PICG configuration >>>> 

 6147 16:51:01.661064  Exit from PICG configuration <<<< 

 6148 16:51:01.664146  [RX_INPUT] configuration >>>>> 

 6149 16:51:01.667372  [RX_INPUT] configuration <<<<< 

 6150 16:51:01.670924  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6151 16:51:01.677383  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6152 16:51:01.684330  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6153 16:51:01.690854  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6154 16:51:01.697272  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6155 16:51:01.701149  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6156 16:51:01.707230  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6157 16:51:01.710693  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6158 16:51:01.714016  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6159 16:51:01.717205  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6160 16:51:01.724111  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6161 16:51:01.727370  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6162 16:51:01.730429  =================================== 

 6163 16:51:01.733657  LPDDR4 DRAM CONFIGURATION

 6164 16:51:01.737102  =================================== 

 6165 16:51:01.737523  EX_ROW_EN[0]    = 0x0

 6166 16:51:01.740455  EX_ROW_EN[1]    = 0x0

 6167 16:51:01.740879  LP4Y_EN      = 0x0

 6168 16:51:01.743643  WORK_FSP     = 0x0

 6169 16:51:01.744064  WL           = 0x2

 6170 16:51:01.747187  RL           = 0x2

 6171 16:51:01.747607  BL           = 0x2

 6172 16:51:01.750318  RPST         = 0x0

 6173 16:51:01.750788  RD_PRE       = 0x0

 6174 16:51:01.753785  WR_PRE       = 0x1

 6175 16:51:01.756697  WR_PST       = 0x0

 6176 16:51:01.757119  DBI_WR       = 0x0

 6177 16:51:01.760152  DBI_RD       = 0x0

 6178 16:51:01.760572  OTF          = 0x1

 6179 16:51:01.763896  =================================== 

 6180 16:51:01.766946  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6181 16:51:01.773817  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6182 16:51:01.776528  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6183 16:51:01.779723  =================================== 

 6184 16:51:01.783281  LPDDR4 DRAM CONFIGURATION

 6185 16:51:01.786290  =================================== 

 6186 16:51:01.786751  EX_ROW_EN[0]    = 0x10

 6187 16:51:01.789746  EX_ROW_EN[1]    = 0x0

 6188 16:51:01.790166  LP4Y_EN      = 0x0

 6189 16:51:01.792916  WORK_FSP     = 0x0

 6190 16:51:01.793369  WL           = 0x2

 6191 16:51:01.796509  RL           = 0x2

 6192 16:51:01.796927  BL           = 0x2

 6193 16:51:01.799624  RPST         = 0x0

 6194 16:51:01.802797  RD_PRE       = 0x0

 6195 16:51:01.803219  WR_PRE       = 0x1

 6196 16:51:01.806196  WR_PST       = 0x0

 6197 16:51:01.806726  DBI_WR       = 0x0

 6198 16:51:01.810000  DBI_RD       = 0x0

 6199 16:51:01.810466  OTF          = 0x1

 6200 16:51:01.813067  =================================== 

 6201 16:51:01.819650  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6202 16:51:01.823138  nWR fixed to 30

 6203 16:51:01.826658  [ModeRegInit_LP4] CH0 RK0

 6204 16:51:01.827087  [ModeRegInit_LP4] CH0 RK1

 6205 16:51:01.829743  [ModeRegInit_LP4] CH1 RK0

 6206 16:51:01.833117  [ModeRegInit_LP4] CH1 RK1

 6207 16:51:01.833689  match AC timing 19

 6208 16:51:01.839633  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6209 16:51:01.843208  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6210 16:51:01.846755  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6211 16:51:01.853217  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6212 16:51:01.856121  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6213 16:51:01.856642  ==

 6214 16:51:01.859310  Dram Type= 6, Freq= 0, CH_0, rank 0

 6215 16:51:01.862833  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6216 16:51:01.863411  ==

 6217 16:51:01.869567  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6218 16:51:01.876657  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6219 16:51:01.879242  [CA 0] Center 36 (8~64) winsize 57

 6220 16:51:01.882810  [CA 1] Center 36 (8~64) winsize 57

 6221 16:51:01.885954  [CA 2] Center 36 (8~64) winsize 57

 6222 16:51:01.889405  [CA 3] Center 36 (8~64) winsize 57

 6223 16:51:01.892394  [CA 4] Center 36 (8~64) winsize 57

 6224 16:51:01.892818  [CA 5] Center 36 (8~64) winsize 57

 6225 16:51:01.895943  

 6226 16:51:01.899168  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6227 16:51:01.899685  

 6228 16:51:01.902750  [CATrainingPosCal] consider 1 rank data

 6229 16:51:01.905614  u2DelayCellTimex100 = 270/100 ps

 6230 16:51:01.909378  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6231 16:51:01.912482  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6232 16:51:01.915532  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6233 16:51:01.919037  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6234 16:51:01.922253  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6235 16:51:01.925981  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6236 16:51:01.926662  

 6237 16:51:01.928981  CA PerBit enable=1, Macro0, CA PI delay=36

 6238 16:51:01.929541  

 6239 16:51:01.932556  [CBTSetCACLKResult] CA Dly = 36

 6240 16:51:01.935781  CS Dly: 1 (0~32)

 6241 16:51:01.936370  ==

 6242 16:51:01.938826  Dram Type= 6, Freq= 0, CH_0, rank 1

 6243 16:51:01.942273  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6244 16:51:01.942829  ==

 6245 16:51:01.948638  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6246 16:51:01.955347  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 6247 16:51:01.958647  [CA 0] Center 36 (8~64) winsize 57

 6248 16:51:01.962100  [CA 1] Center 36 (8~64) winsize 57

 6249 16:51:01.965136  [CA 2] Center 36 (8~64) winsize 57

 6250 16:51:01.965765  [CA 3] Center 36 (8~64) winsize 57

 6251 16:51:01.968688  [CA 4] Center 36 (8~64) winsize 57

 6252 16:51:01.971708  [CA 5] Center 36 (8~64) winsize 57

 6253 16:51:01.972258  

 6254 16:51:01.978258  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 6255 16:51:01.978837  

 6256 16:51:01.981829  [CATrainingPosCal] consider 2 rank data

 6257 16:51:01.985208  u2DelayCellTimex100 = 270/100 ps

 6258 16:51:01.988476  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6259 16:51:01.991656  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6260 16:51:01.994911  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6261 16:51:01.998410  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6262 16:51:02.001826  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6263 16:51:02.004861  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6264 16:51:02.005410  

 6265 16:51:02.008281  CA PerBit enable=1, Macro0, CA PI delay=36

 6266 16:51:02.008772  

 6267 16:51:02.011774  [CBTSetCACLKResult] CA Dly = 36

 6268 16:51:02.015066  CS Dly: 1 (0~32)

 6269 16:51:02.015488  

 6270 16:51:02.018108  ----->DramcWriteLeveling(PI) begin...

 6271 16:51:02.018580  ==

 6272 16:51:02.021738  Dram Type= 6, Freq= 0, CH_0, rank 0

 6273 16:51:02.025289  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6274 16:51:02.025718  ==

 6275 16:51:02.028389  Write leveling (Byte 0): 40 => 8

 6276 16:51:02.031526  Write leveling (Byte 1): 32 => 0

 6277 16:51:02.034807  DramcWriteLeveling(PI) end<-----

 6278 16:51:02.035236  

 6279 16:51:02.035579  ==

 6280 16:51:02.037969  Dram Type= 6, Freq= 0, CH_0, rank 0

 6281 16:51:02.041221  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6282 16:51:02.041650  ==

 6283 16:51:02.044868  [Gating] SW mode calibration

 6284 16:51:02.051150  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6285 16:51:02.057778  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6286 16:51:02.061008   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6287 16:51:02.064347   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6288 16:51:02.071406   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6289 16:51:02.074457   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6290 16:51:02.077801   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6291 16:51:02.084546   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6292 16:51:02.087627   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6293 16:51:02.090939   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6294 16:51:02.097447   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6295 16:51:02.100633  Total UI for P1: 0, mck2ui 16

 6296 16:51:02.104257  best dqsien dly found for B0: ( 0, 14, 24)

 6297 16:51:02.108026  Total UI for P1: 0, mck2ui 16

 6298 16:51:02.110926  best dqsien dly found for B1: ( 0, 14, 24)

 6299 16:51:02.113938  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6300 16:51:02.117573  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6301 16:51:02.117991  

 6302 16:51:02.120671  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6303 16:51:02.123893  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6304 16:51:02.127018  [Gating] SW calibration Done

 6305 16:51:02.127399  ==

 6306 16:51:02.131034  Dram Type= 6, Freq= 0, CH_0, rank 0

 6307 16:51:02.133781  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6308 16:51:02.134059  ==

 6309 16:51:02.137180  RX Vref Scan: 0

 6310 16:51:02.137461  

 6311 16:51:02.140055  RX Vref 0 -> 0, step: 1

 6312 16:51:02.140287  

 6313 16:51:02.140473  RX Delay -410 -> 252, step: 16

 6314 16:51:02.146840  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6315 16:51:02.150338  iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480

 6316 16:51:02.153483  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6317 16:51:02.160215  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6318 16:51:02.163229  iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480

 6319 16:51:02.166870  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6320 16:51:02.170219  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6321 16:51:02.173487  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6322 16:51:02.179937  iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480

 6323 16:51:02.183293  iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480

 6324 16:51:02.186764  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6325 16:51:02.193081  iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464

 6326 16:51:02.196438  iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480

 6327 16:51:02.199820  iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480

 6328 16:51:02.203037  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6329 16:51:02.209877  iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480

 6330 16:51:02.210199  ==

 6331 16:51:02.212726  Dram Type= 6, Freq= 0, CH_0, rank 0

 6332 16:51:02.216448  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6333 16:51:02.216709  ==

 6334 16:51:02.216932  DQS Delay:

 6335 16:51:02.219888  DQS0 = 27, DQS1 = 43

 6336 16:51:02.220177  DQM Delay:

 6337 16:51:02.223021  DQM0 = 12, DQM1 = 12

 6338 16:51:02.223403  DQ Delay:

 6339 16:51:02.225956  DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8

 6340 16:51:02.229643  DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24

 6341 16:51:02.232970  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6342 16:51:02.236379  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6343 16:51:02.236831  

 6344 16:51:02.237279  

 6345 16:51:02.237622  ==

 6346 16:51:02.239703  Dram Type= 6, Freq= 0, CH_0, rank 0

 6347 16:51:02.242961  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6348 16:51:02.243419  ==

 6349 16:51:02.246416  

 6350 16:51:02.247026  

 6351 16:51:02.247529  	TX Vref Scan disable

 6352 16:51:02.249348   == TX Byte 0 ==

 6353 16:51:02.252767  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6354 16:51:02.256115  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6355 16:51:02.259252   == TX Byte 1 ==

 6356 16:51:02.262711  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6357 16:51:02.265918  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6358 16:51:02.266493  ==

 6359 16:51:02.268986  Dram Type= 6, Freq= 0, CH_0, rank 0

 6360 16:51:02.275827  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6361 16:51:02.276241  ==

 6362 16:51:02.276566  

 6363 16:51:02.276862  

 6364 16:51:02.277147  	TX Vref Scan disable

 6365 16:51:02.279062   == TX Byte 0 ==

 6366 16:51:02.282424  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6367 16:51:02.285472  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6368 16:51:02.288614   == TX Byte 1 ==

 6369 16:51:02.292186  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6370 16:51:02.295334  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6371 16:51:02.295745  

 6372 16:51:02.298864  [DATLAT]

 6373 16:51:02.299273  Freq=400, CH0 RK0

 6374 16:51:02.299595  

 6375 16:51:02.302120  DATLAT Default: 0xf

 6376 16:51:02.302557  0, 0xFFFF, sum = 0

 6377 16:51:02.305387  1, 0xFFFF, sum = 0

 6378 16:51:02.305801  2, 0xFFFF, sum = 0

 6379 16:51:02.308968  3, 0xFFFF, sum = 0

 6380 16:51:02.309486  4, 0xFFFF, sum = 0

 6381 16:51:02.311857  5, 0xFFFF, sum = 0

 6382 16:51:02.312272  6, 0xFFFF, sum = 0

 6383 16:51:02.315025  7, 0xFFFF, sum = 0

 6384 16:51:02.318377  8, 0xFFFF, sum = 0

 6385 16:51:02.318807  9, 0xFFFF, sum = 0

 6386 16:51:02.321888  10, 0xFFFF, sum = 0

 6387 16:51:02.322303  11, 0xFFFF, sum = 0

 6388 16:51:02.325247  12, 0xFFFF, sum = 0

 6389 16:51:02.325663  13, 0x0, sum = 1

 6390 16:51:02.328451  14, 0x0, sum = 2

 6391 16:51:02.328867  15, 0x0, sum = 3

 6392 16:51:02.331675  16, 0x0, sum = 4

 6393 16:51:02.332219  best_step = 14

 6394 16:51:02.332555  

 6395 16:51:02.332860  ==

 6396 16:51:02.334970  Dram Type= 6, Freq= 0, CH_0, rank 0

 6397 16:51:02.338191  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6398 16:51:02.338646  ==

 6399 16:51:02.342279  RX Vref Scan: 1

 6400 16:51:02.342729  

 6401 16:51:02.344942  RX Vref 0 -> 0, step: 1

 6402 16:51:02.345349  

 6403 16:51:02.348306  RX Delay -327 -> 252, step: 8

 6404 16:51:02.348715  

 6405 16:51:02.349042  Set Vref, RX VrefLevel [Byte0]: 60

 6406 16:51:02.351450                           [Byte1]: 49

 6407 16:51:02.357268  

 6408 16:51:02.357674  Final RX Vref Byte 0 = 60 to rank0

 6409 16:51:02.360349  Final RX Vref Byte 1 = 49 to rank0

 6410 16:51:02.363677  Final RX Vref Byte 0 = 60 to rank1

 6411 16:51:02.366859  Final RX Vref Byte 1 = 49 to rank1==

 6412 16:51:02.370421  Dram Type= 6, Freq= 0, CH_0, rank 0

 6413 16:51:02.376956  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6414 16:51:02.377367  ==

 6415 16:51:02.377692  DQS Delay:

 6416 16:51:02.380018  DQS0 = 28, DQS1 = 48

 6417 16:51:02.380429  DQM Delay:

 6418 16:51:02.380757  DQM0 = 12, DQM1 = 15

 6419 16:51:02.383569  DQ Delay:

 6420 16:51:02.386891  DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8

 6421 16:51:02.390087  DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20

 6422 16:51:02.390529  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12

 6423 16:51:02.396655  DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24

 6424 16:51:02.397078  

 6425 16:51:02.397409  

 6426 16:51:02.403419  [DQSOSCAuto] RK0, (LSB)MR18= 0xada4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps

 6427 16:51:02.406911  CH0 RK0: MR19=C0C, MR18=ADA4

 6428 16:51:02.413239  CH0_RK0: MR19=0xC0C, MR18=0xADA4, DQSOSC=388, MR23=63, INC=392, DEC=261

 6429 16:51:02.413917  ==

 6430 16:51:02.416361  Dram Type= 6, Freq= 0, CH_0, rank 1

 6431 16:51:02.419817  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6432 16:51:02.420428  ==

 6433 16:51:02.423250  [Gating] SW mode calibration

 6434 16:51:02.429597  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6435 16:51:02.436539  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6436 16:51:02.439683   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6437 16:51:02.442934   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6438 16:51:02.449715   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6439 16:51:02.452801   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6440 16:51:02.456624   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6441 16:51:02.463091   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6442 16:51:02.465998   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6443 16:51:02.469852   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6444 16:51:02.476087   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6445 16:51:02.476599  Total UI for P1: 0, mck2ui 16

 6446 16:51:02.482867  best dqsien dly found for B0: ( 0, 14, 24)

 6447 16:51:02.483416  Total UI for P1: 0, mck2ui 16

 6448 16:51:02.489135  best dqsien dly found for B1: ( 0, 14, 24)

 6449 16:51:02.492606  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6450 16:51:02.495945  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6451 16:51:02.496488  

 6452 16:51:02.499563  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6453 16:51:02.502734  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6454 16:51:02.505953  [Gating] SW calibration Done

 6455 16:51:02.506592  ==

 6456 16:51:02.509061  Dram Type= 6, Freq= 0, CH_0, rank 1

 6457 16:51:02.512200  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6458 16:51:02.512824  ==

 6459 16:51:02.515740  RX Vref Scan: 0

 6460 16:51:02.516234  

 6461 16:51:02.516758  RX Vref 0 -> 0, step: 1

 6462 16:51:02.518791  

 6463 16:51:02.519219  RX Delay -410 -> 252, step: 16

 6464 16:51:02.525756  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6465 16:51:02.528834  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6466 16:51:02.532386  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6467 16:51:02.535505  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6468 16:51:02.542023  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6469 16:51:02.545187  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6470 16:51:02.548691  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6471 16:51:02.555072  iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480

 6472 16:51:02.558699  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6473 16:51:02.561900  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6474 16:51:02.565211  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6475 16:51:02.571920  iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464

 6476 16:51:02.574979  iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480

 6477 16:51:02.578000  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6478 16:51:02.581771  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6479 16:51:02.588332  iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480

 6480 16:51:02.588764  ==

 6481 16:51:02.591481  Dram Type= 6, Freq= 0, CH_0, rank 1

 6482 16:51:02.595117  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6483 16:51:02.595548  ==

 6484 16:51:02.595891  DQS Delay:

 6485 16:51:02.597998  DQS0 = 27, DQS1 = 35

 6486 16:51:02.598455  DQM Delay:

 6487 16:51:02.601155  DQM0 = 9, DQM1 = 7

 6488 16:51:02.601582  DQ Delay:

 6489 16:51:02.604733  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6490 16:51:02.607866  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6491 16:51:02.611037  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0

 6492 16:51:02.614459  DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =8

 6493 16:51:02.615086  

 6494 16:51:02.615660  

 6495 16:51:02.616180  ==

 6496 16:51:02.617702  Dram Type= 6, Freq= 0, CH_0, rank 1

 6497 16:51:02.621146  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6498 16:51:02.621709  ==

 6499 16:51:02.622265  

 6500 16:51:02.622758  

 6501 16:51:02.624221  	TX Vref Scan disable

 6502 16:51:02.624843   == TX Byte 0 ==

 6503 16:51:02.631480  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6504 16:51:02.634444  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6505 16:51:02.634927   == TX Byte 1 ==

 6506 16:51:02.640720  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6507 16:51:02.644282  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6508 16:51:02.644897  ==

 6509 16:51:02.647647  Dram Type= 6, Freq= 0, CH_0, rank 1

 6510 16:51:02.650576  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6511 16:51:02.651087  ==

 6512 16:51:02.651533  

 6513 16:51:02.651920  

 6514 16:51:02.654166  	TX Vref Scan disable

 6515 16:51:02.657066   == TX Byte 0 ==

 6516 16:51:02.660593  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6517 16:51:02.663891  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6518 16:51:02.667052   == TX Byte 1 ==

 6519 16:51:02.670636  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6520 16:51:02.673809  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6521 16:51:02.674238  

 6522 16:51:02.674704  [DATLAT]

 6523 16:51:02.677211  Freq=400, CH0 RK1

 6524 16:51:02.677671  

 6525 16:51:02.678111  DATLAT Default: 0xe

 6526 16:51:02.681067  0, 0xFFFF, sum = 0

 6527 16:51:02.683730  1, 0xFFFF, sum = 0

 6528 16:51:02.684274  2, 0xFFFF, sum = 0

 6529 16:51:02.686867  3, 0xFFFF, sum = 0

 6530 16:51:02.687387  4, 0xFFFF, sum = 0

 6531 16:51:02.690029  5, 0xFFFF, sum = 0

 6532 16:51:02.690545  6, 0xFFFF, sum = 0

 6533 16:51:02.693567  7, 0xFFFF, sum = 0

 6534 16:51:02.694056  8, 0xFFFF, sum = 0

 6535 16:51:02.696944  9, 0xFFFF, sum = 0

 6536 16:51:02.697563  10, 0xFFFF, sum = 0

 6537 16:51:02.700165  11, 0xFFFF, sum = 0

 6538 16:51:02.700672  12, 0xFFFF, sum = 0

 6539 16:51:02.703255  13, 0x0, sum = 1

 6540 16:51:02.703735  14, 0x0, sum = 2

 6541 16:51:02.706674  15, 0x0, sum = 3

 6542 16:51:02.707299  16, 0x0, sum = 4

 6543 16:51:02.709799  best_step = 14

 6544 16:51:02.710280  

 6545 16:51:02.710744  ==

 6546 16:51:02.713348  Dram Type= 6, Freq= 0, CH_0, rank 1

 6547 16:51:02.716345  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6548 16:51:02.716776  ==

 6549 16:51:02.719591  RX Vref Scan: 0

 6550 16:51:02.720021  

 6551 16:51:02.720361  RX Vref 0 -> 0, step: 1

 6552 16:51:02.720679  

 6553 16:51:02.723022  RX Delay -311 -> 252, step: 8

 6554 16:51:02.731201  iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456

 6555 16:51:02.734284  iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448

 6556 16:51:02.737301  iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440

 6557 16:51:02.744146  iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448

 6558 16:51:02.747237  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6559 16:51:02.750793  iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456

 6560 16:51:02.753972  iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448

 6561 16:51:02.757263  iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456

 6562 16:51:02.763896  iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456

 6563 16:51:02.767303  iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448

 6564 16:51:02.770640  iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456

 6565 16:51:02.777109  iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448

 6566 16:51:02.780968  iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448

 6567 16:51:02.783992  iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448

 6568 16:51:02.787590  iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448

 6569 16:51:02.793660  iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440

 6570 16:51:02.794267  ==

 6571 16:51:02.796769  Dram Type= 6, Freq= 0, CH_0, rank 1

 6572 16:51:02.800432  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6573 16:51:02.800912  ==

 6574 16:51:02.801341  DQS Delay:

 6575 16:51:02.803849  DQS0 = 28, DQS1 = 40

 6576 16:51:02.804326  DQM Delay:

 6577 16:51:02.806858  DQM0 = 10, DQM1 = 12

 6578 16:51:02.807358  DQ Delay:

 6579 16:51:02.810151  DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4

 6580 16:51:02.813678  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16

 6581 16:51:02.816800  DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8

 6582 16:51:02.819917  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20

 6583 16:51:02.820346  

 6584 16:51:02.820686  

 6585 16:51:02.826593  [DQSOSCAuto] RK1, (LSB)MR18= 0xb468, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps

 6586 16:51:02.830187  CH0 RK1: MR19=C0C, MR18=B468

 6587 16:51:02.836334  CH0_RK1: MR19=0xC0C, MR18=0xB468, DQSOSC=387, MR23=63, INC=394, DEC=262

 6588 16:51:02.839444  [RxdqsGatingPostProcess] freq 400

 6589 16:51:02.846288  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6590 16:51:02.849391  best DQS0 dly(2T, 0.5T) = (0, 10)

 6591 16:51:02.853110  best DQS1 dly(2T, 0.5T) = (0, 10)

 6592 16:51:02.856125  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6593 16:51:02.859457  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6594 16:51:02.862688  best DQS0 dly(2T, 0.5T) = (0, 10)

 6595 16:51:02.863142  best DQS1 dly(2T, 0.5T) = (0, 10)

 6596 16:51:02.866024  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6597 16:51:02.869705  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6598 16:51:02.872801  Pre-setting of DQS Precalculation

 6599 16:51:02.879525  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6600 16:51:02.879958  ==

 6601 16:51:02.882726  Dram Type= 6, Freq= 0, CH_1, rank 0

 6602 16:51:02.886211  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6603 16:51:02.886718  ==

 6604 16:51:02.892689  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6605 16:51:02.899124  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31

 6606 16:51:02.902441  [CA 0] Center 36 (8~64) winsize 57

 6607 16:51:02.905743  [CA 1] Center 36 (8~64) winsize 57

 6608 16:51:02.906302  [CA 2] Center 36 (8~64) winsize 57

 6609 16:51:02.909107  [CA 3] Center 36 (8~64) winsize 57

 6610 16:51:02.912798  [CA 4] Center 36 (8~64) winsize 57

 6611 16:51:02.915617  [CA 5] Center 36 (8~64) winsize 57

 6612 16:51:02.916148  

 6613 16:51:02.919251  [CmdBusTrainingLP45] Vref(ca) range 1: 31

 6614 16:51:02.922263  

 6615 16:51:02.925424  [CATrainingPosCal] consider 1 rank data

 6616 16:51:02.926070  u2DelayCellTimex100 = 270/100 ps

 6617 16:51:02.932432  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6618 16:51:02.935387  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6619 16:51:02.938963  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6620 16:51:02.942145  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6621 16:51:02.945241  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6622 16:51:02.948672  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6623 16:51:02.949164  

 6624 16:51:02.951714  CA PerBit enable=1, Macro0, CA PI delay=36

 6625 16:51:02.952357  

 6626 16:51:02.955319  [CBTSetCACLKResult] CA Dly = 36

 6627 16:51:02.958405  CS Dly: 1 (0~32)

 6628 16:51:02.959012  ==

 6629 16:51:02.961894  Dram Type= 6, Freq= 0, CH_1, rank 1

 6630 16:51:02.965016  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6631 16:51:02.965483  ==

 6632 16:51:02.971535  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6633 16:51:02.978431  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6634 16:51:02.978903  [CA 0] Center 36 (8~64) winsize 57

 6635 16:51:02.981515  [CA 1] Center 36 (8~64) winsize 57

 6636 16:51:02.985071  [CA 2] Center 36 (8~64) winsize 57

 6637 16:51:02.988549  [CA 3] Center 36 (8~64) winsize 57

 6638 16:51:02.991810  [CA 4] Center 36 (8~64) winsize 57

 6639 16:51:02.994731  [CA 5] Center 36 (8~64) winsize 57

 6640 16:51:02.995195  

 6641 16:51:02.998049  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6642 16:51:02.998579  

 6643 16:51:03.001563  [CATrainingPosCal] consider 2 rank data

 6644 16:51:03.004600  u2DelayCellTimex100 = 270/100 ps

 6645 16:51:03.008114  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6646 16:51:03.014656  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6647 16:51:03.018212  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6648 16:51:03.021364  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6649 16:51:03.024659  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6650 16:51:03.027795  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6651 16:51:03.028217  

 6652 16:51:03.031238  CA PerBit enable=1, Macro0, CA PI delay=36

 6653 16:51:03.031662  

 6654 16:51:03.034340  [CBTSetCACLKResult] CA Dly = 36

 6655 16:51:03.034834  CS Dly: 1 (0~32)

 6656 16:51:03.037745  

 6657 16:51:03.041078  ----->DramcWriteLeveling(PI) begin...

 6658 16:51:03.041505  ==

 6659 16:51:03.044156  Dram Type= 6, Freq= 0, CH_1, rank 0

 6660 16:51:03.047959  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6661 16:51:03.048395  ==

 6662 16:51:03.050902  Write leveling (Byte 0): 40 => 8

 6663 16:51:03.054135  Write leveling (Byte 1): 32 => 0

 6664 16:51:03.057478  DramcWriteLeveling(PI) end<-----

 6665 16:51:03.058076  

 6666 16:51:03.058663  ==

 6667 16:51:03.061086  Dram Type= 6, Freq= 0, CH_1, rank 0

 6668 16:51:03.064237  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6669 16:51:03.064740  ==

 6670 16:51:03.067325  [Gating] SW mode calibration

 6671 16:51:03.074145  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6672 16:51:03.080569  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6673 16:51:03.084270   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6674 16:51:03.087132   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6675 16:51:03.094086   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6676 16:51:03.097177   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6677 16:51:03.100576   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6678 16:51:03.107350   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6679 16:51:03.110481   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6680 16:51:03.114048   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6681 16:51:03.120255   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6682 16:51:03.120731  Total UI for P1: 0, mck2ui 16

 6683 16:51:03.126860  best dqsien dly found for B0: ( 0, 14, 24)

 6684 16:51:03.127245  Total UI for P1: 0, mck2ui 16

 6685 16:51:03.133392  best dqsien dly found for B1: ( 0, 14, 24)

 6686 16:51:03.136717  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6687 16:51:03.140311  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6688 16:51:03.140801  

 6689 16:51:03.143298  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6690 16:51:03.146645  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6691 16:51:03.150070  [Gating] SW calibration Done

 6692 16:51:03.150542  ==

 6693 16:51:03.153352  Dram Type= 6, Freq= 0, CH_1, rank 0

 6694 16:51:03.156492  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6695 16:51:03.156984  ==

 6696 16:51:03.159835  RX Vref Scan: 0

 6697 16:51:03.160341  

 6698 16:51:03.160732  RX Vref 0 -> 0, step: 1

 6699 16:51:03.162929  

 6700 16:51:03.163347  RX Delay -410 -> 252, step: 16

 6701 16:51:03.169743  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6702 16:51:03.173007  iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480

 6703 16:51:03.176164  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6704 16:51:03.179674  iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480

 6705 16:51:03.186559  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6706 16:51:03.189585  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6707 16:51:03.192793  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6708 16:51:03.196074  iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480

 6709 16:51:03.202839  iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480

 6710 16:51:03.205899  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6711 16:51:03.209139  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6712 16:51:03.213135  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6713 16:51:03.219512  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6714 16:51:03.222861  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6715 16:51:03.225859  iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480

 6716 16:51:03.232752  iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496

 6717 16:51:03.233219  ==

 6718 16:51:03.235960  Dram Type= 6, Freq= 0, CH_1, rank 0

 6719 16:51:03.239105  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6720 16:51:03.239566  ==

 6721 16:51:03.239949  DQS Delay:

 6722 16:51:03.242104  DQS0 = 27, DQS1 = 43

 6723 16:51:03.242616  DQM Delay:

 6724 16:51:03.245449  DQM0 = 7, DQM1 = 17

 6725 16:51:03.245937  DQ Delay:

 6726 16:51:03.248944  DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0

 6727 16:51:03.252151  DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0

 6728 16:51:03.255729  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16

 6729 16:51:03.258960  DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24

 6730 16:51:03.259421  

 6731 16:51:03.259797  

 6732 16:51:03.260151  ==

 6733 16:51:03.261842  Dram Type= 6, Freq= 0, CH_1, rank 0

 6734 16:51:03.265810  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6735 16:51:03.266315  ==

 6736 16:51:03.266732  

 6737 16:51:03.267087  

 6738 16:51:03.268907  	TX Vref Scan disable

 6739 16:51:03.271987   == TX Byte 0 ==

 6740 16:51:03.275538  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6741 16:51:03.278638  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6742 16:51:03.279119   == TX Byte 1 ==

 6743 16:51:03.285321  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6744 16:51:03.288471  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6745 16:51:03.288941  ==

 6746 16:51:03.292205  Dram Type= 6, Freq= 0, CH_1, rank 0

 6747 16:51:03.295006  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6748 16:51:03.295514  ==

 6749 16:51:03.298310  

 6750 16:51:03.298961  

 6751 16:51:03.299410  	TX Vref Scan disable

 6752 16:51:03.301998   == TX Byte 0 ==

 6753 16:51:03.305148  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6754 16:51:03.308468  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6755 16:51:03.311914   == TX Byte 1 ==

 6756 16:51:03.314703  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6757 16:51:03.318295  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6758 16:51:03.318803  

 6759 16:51:03.321739  [DATLAT]

 6760 16:51:03.322212  Freq=400, CH1 RK0

 6761 16:51:03.322759  

 6762 16:51:03.325028  DATLAT Default: 0xf

 6763 16:51:03.325483  0, 0xFFFF, sum = 0

 6764 16:51:03.328357  1, 0xFFFF, sum = 0

 6765 16:51:03.328827  2, 0xFFFF, sum = 0

 6766 16:51:03.331553  3, 0xFFFF, sum = 0

 6767 16:51:03.332021  4, 0xFFFF, sum = 0

 6768 16:51:03.335159  5, 0xFFFF, sum = 0

 6769 16:51:03.335696  6, 0xFFFF, sum = 0

 6770 16:51:03.338326  7, 0xFFFF, sum = 0

 6771 16:51:03.338833  8, 0xFFFF, sum = 0

 6772 16:51:03.341698  9, 0xFFFF, sum = 0

 6773 16:51:03.342251  10, 0xFFFF, sum = 0

 6774 16:51:03.345254  11, 0xFFFF, sum = 0

 6775 16:51:03.345795  12, 0xFFFF, sum = 0

 6776 16:51:03.348204  13, 0x0, sum = 1

 6777 16:51:03.348702  14, 0x0, sum = 2

 6778 16:51:03.351605  15, 0x0, sum = 3

 6779 16:51:03.352117  16, 0x0, sum = 4

 6780 16:51:03.354763  best_step = 14

 6781 16:51:03.355218  

 6782 16:51:03.355665  ==

 6783 16:51:03.357829  Dram Type= 6, Freq= 0, CH_1, rank 0

 6784 16:51:03.361541  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6785 16:51:03.362034  ==

 6786 16:51:03.364773  RX Vref Scan: 1

 6787 16:51:03.365234  

 6788 16:51:03.365615  RX Vref 0 -> 0, step: 1

 6789 16:51:03.366032  

 6790 16:51:03.368054  RX Delay -327 -> 252, step: 8

 6791 16:51:03.368517  

 6792 16:51:03.371096  Set Vref, RX VrefLevel [Byte0]: 51

 6793 16:51:03.374507                           [Byte1]: 52

 6794 16:51:03.379389  

 6795 16:51:03.379889  Final RX Vref Byte 0 = 51 to rank0

 6796 16:51:03.382525  Final RX Vref Byte 1 = 52 to rank0

 6797 16:51:03.386133  Final RX Vref Byte 0 = 51 to rank1

 6798 16:51:03.389282  Final RX Vref Byte 1 = 52 to rank1==

 6799 16:51:03.392289  Dram Type= 6, Freq= 0, CH_1, rank 0

 6800 16:51:03.398866  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6801 16:51:03.399375  ==

 6802 16:51:03.399748  DQS Delay:

 6803 16:51:03.402574  DQS0 = 32, DQS1 = 40

 6804 16:51:03.403036  DQM Delay:

 6805 16:51:03.403416  DQM0 = 10, DQM1 = 13

 6806 16:51:03.405760  DQ Delay:

 6807 16:51:03.408907  DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8

 6808 16:51:03.409364  DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8

 6809 16:51:03.412153  DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4

 6810 16:51:03.416134  DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20

 6811 16:51:03.416599  

 6812 16:51:03.418907  

 6813 16:51:03.425635  [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps

 6814 16:51:03.429300  CH1 RK0: MR19=C0C, MR18=8DC8

 6815 16:51:03.435964  CH1_RK0: MR19=0xC0C, MR18=0x8DC8, DQSOSC=385, MR23=63, INC=398, DEC=265

 6816 16:51:03.436400  ==

 6817 16:51:03.438610  Dram Type= 6, Freq= 0, CH_1, rank 1

 6818 16:51:03.441769  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6819 16:51:03.442174  ==

 6820 16:51:03.445563  [Gating] SW mode calibration

 6821 16:51:03.451982  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6822 16:51:03.458692  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6823 16:51:03.461733   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6824 16:51:03.465162   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6825 16:51:03.472333   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6826 16:51:03.475193   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6827 16:51:03.478606   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6828 16:51:03.485177   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6829 16:51:03.488386   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6830 16:51:03.491368   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6831 16:51:03.498205   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6832 16:51:03.498697  Total UI for P1: 0, mck2ui 16

 6833 16:51:03.504902  best dqsien dly found for B0: ( 0, 14, 24)

 6834 16:51:03.505353  Total UI for P1: 0, mck2ui 16

 6835 16:51:03.511226  best dqsien dly found for B1: ( 0, 14, 24)

 6836 16:51:03.514729  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6837 16:51:03.517819  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6838 16:51:03.518452  

 6839 16:51:03.521062  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6840 16:51:03.524447  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6841 16:51:03.527715  [Gating] SW calibration Done

 6842 16:51:03.528326  ==

 6843 16:51:03.531072  Dram Type= 6, Freq= 0, CH_1, rank 1

 6844 16:51:03.534515  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6845 16:51:03.534958  ==

 6846 16:51:03.537780  RX Vref Scan: 0

 6847 16:51:03.538204  

 6848 16:51:03.538588  RX Vref 0 -> 0, step: 1

 6849 16:51:03.538905  

 6850 16:51:03.541230  RX Delay -410 -> 252, step: 16

 6851 16:51:03.547599  iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448

 6852 16:51:03.550671  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6853 16:51:03.554313  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6854 16:51:03.557466  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6855 16:51:03.564504  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6856 16:51:03.567584  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6857 16:51:03.570978  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6858 16:51:03.574268  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6859 16:51:03.580821  iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480

 6860 16:51:03.584390  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6861 16:51:03.587393  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6862 16:51:03.590484  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6863 16:51:03.597391  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6864 16:51:03.600807  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6865 16:51:03.604385  iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480

 6866 16:51:03.607233  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6867 16:51:03.610395  ==

 6868 16:51:03.613812  Dram Type= 6, Freq= 0, CH_1, rank 1

 6869 16:51:03.617276  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6870 16:51:03.617676  ==

 6871 16:51:03.618016  DQS Delay:

 6872 16:51:03.620602  DQS0 = 35, DQS1 = 43

 6873 16:51:03.621001  DQM Delay:

 6874 16:51:03.623978  DQM0 = 18, DQM1 = 19

 6875 16:51:03.624408  DQ Delay:

 6876 16:51:03.627415  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6877 16:51:03.630626  DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16

 6878 16:51:03.633596  DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16

 6879 16:51:03.636814  DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32

 6880 16:51:03.637209  

 6881 16:51:03.637552  

 6882 16:51:03.637874  ==

 6883 16:51:03.640676  Dram Type= 6, Freq= 0, CH_1, rank 1

 6884 16:51:03.643620  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6885 16:51:03.644063  ==

 6886 16:51:03.644424  

 6887 16:51:03.644755  

 6888 16:51:03.646818  	TX Vref Scan disable

 6889 16:51:03.650820   == TX Byte 0 ==

 6890 16:51:03.653690  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6891 16:51:03.656820  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6892 16:51:03.660170   == TX Byte 1 ==

 6893 16:51:03.663217  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6894 16:51:03.667028  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6895 16:51:03.667472  ==

 6896 16:51:03.669893  Dram Type= 6, Freq= 0, CH_1, rank 1

 6897 16:51:03.673690  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6898 16:51:03.674138  ==

 6899 16:51:03.674524  

 6900 16:51:03.676627  

 6901 16:51:03.677005  	TX Vref Scan disable

 6902 16:51:03.680248   == TX Byte 0 ==

 6903 16:51:03.683244  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6904 16:51:03.686671  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6905 16:51:03.690093   == TX Byte 1 ==

 6906 16:51:03.693176  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6907 16:51:03.696366  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6908 16:51:03.696756  

 6909 16:51:03.697094  [DATLAT]

 6910 16:51:03.699795  Freq=400, CH1 RK1

 6911 16:51:03.700166  

 6912 16:51:03.700494  DATLAT Default: 0xe

 6913 16:51:03.703202  0, 0xFFFF, sum = 0

 6914 16:51:03.706337  1, 0xFFFF, sum = 0

 6915 16:51:03.706762  2, 0xFFFF, sum = 0

 6916 16:51:03.710150  3, 0xFFFF, sum = 0

 6917 16:51:03.710608  4, 0xFFFF, sum = 0

 6918 16:51:03.713346  5, 0xFFFF, sum = 0

 6919 16:51:03.713826  6, 0xFFFF, sum = 0

 6920 16:51:03.716558  7, 0xFFFF, sum = 0

 6921 16:51:03.716956  8, 0xFFFF, sum = 0

 6922 16:51:03.719414  9, 0xFFFF, sum = 0

 6923 16:51:03.719804  10, 0xFFFF, sum = 0

 6924 16:51:03.722569  11, 0xFFFF, sum = 0

 6925 16:51:03.722977  12, 0xFFFF, sum = 0

 6926 16:51:03.726218  13, 0x0, sum = 1

 6927 16:51:03.726661  14, 0x0, sum = 2

 6928 16:51:03.729518  15, 0x0, sum = 3

 6929 16:51:03.729968  16, 0x0, sum = 4

 6930 16:51:03.732469  best_step = 14

 6931 16:51:03.732864  

 6932 16:51:03.733205  ==

 6933 16:51:03.736122  Dram Type= 6, Freq= 0, CH_1, rank 1

 6934 16:51:03.739422  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6935 16:51:03.739825  ==

 6936 16:51:03.742830  RX Vref Scan: 0

 6937 16:51:03.743228  

 6938 16:51:03.743563  RX Vref 0 -> 0, step: 1

 6939 16:51:03.743885  

 6940 16:51:03.746010  RX Delay -327 -> 252, step: 8

 6941 16:51:03.753848  iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432

 6942 16:51:03.757013  iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432

 6943 16:51:03.760835  iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448

 6944 16:51:03.763904  iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448

 6945 16:51:03.770018  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6946 16:51:03.773671  iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456

 6947 16:51:03.776773  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 6948 16:51:03.783604  iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440

 6949 16:51:03.786695  iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456

 6950 16:51:03.789974  iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456

 6951 16:51:03.793277  iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448

 6952 16:51:03.799813  iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456

 6953 16:51:03.803031  iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456

 6954 16:51:03.806435  iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448

 6955 16:51:03.809945  iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456

 6956 16:51:03.816439  iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464

 6957 16:51:03.816882  ==

 6958 16:51:03.819608  Dram Type= 6, Freq= 0, CH_1, rank 1

 6959 16:51:03.822954  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6960 16:51:03.823427  ==

 6961 16:51:03.823801  DQS Delay:

 6962 16:51:03.826415  DQS0 = 32, DQS1 = 36

 6963 16:51:03.826885  DQM Delay:

 6964 16:51:03.829531  DQM0 = 12, DQM1 = 11

 6965 16:51:03.829997  DQ Delay:

 6966 16:51:03.832601  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6967 16:51:03.835915  DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12

 6968 16:51:03.839193  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8

 6969 16:51:03.843038  DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20

 6970 16:51:03.843504  

 6971 16:51:03.843875  

 6972 16:51:03.852758  [DQSOSCAuto] RK1, (LSB)MR18= 0xac53, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps

 6973 16:51:03.853202  CH1 RK1: MR19=C0C, MR18=AC53

 6974 16:51:03.859403  CH1_RK1: MR19=0xC0C, MR18=0xAC53, DQSOSC=388, MR23=63, INC=392, DEC=261

 6975 16:51:03.862891  [RxdqsGatingPostProcess] freq 400

 6976 16:51:03.869377  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6977 16:51:03.872185  best DQS0 dly(2T, 0.5T) = (0, 10)

 6978 16:51:03.875626  best DQS1 dly(2T, 0.5T) = (0, 10)

 6979 16:51:03.878805  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6980 16:51:03.882457  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6981 16:51:03.885420  best DQS0 dly(2T, 0.5T) = (0, 10)

 6982 16:51:03.888798  best DQS1 dly(2T, 0.5T) = (0, 10)

 6983 16:51:03.892033  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6984 16:51:03.895464  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6985 16:51:03.895893  Pre-setting of DQS Precalculation

 6986 16:51:03.902041  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6987 16:51:03.908759  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 6988 16:51:03.915036  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6989 16:51:03.915512  

 6990 16:51:03.916080  

 6991 16:51:03.918680  [Calibration Summary] 800 Mbps

 6992 16:51:03.921816  CH 0, Rank 0

 6993 16:51:03.922288  SW Impedance     : PASS

 6994 16:51:03.925364  DUTY Scan        : NO K

 6995 16:51:03.928528  ZQ Calibration   : PASS

 6996 16:51:03.928994  Jitter Meter     : NO K

 6997 16:51:03.931575  CBT Training     : PASS

 6998 16:51:03.935092  Write leveling   : PASS

 6999 16:51:03.935696  RX DQS gating    : PASS

 7000 16:51:03.938699  RX DQ/DQS(RDDQC) : PASS

 7001 16:51:03.939209  TX DQ/DQS        : PASS

 7002 16:51:03.941495  RX DATLAT        : PASS

 7003 16:51:03.945099  RX DQ/DQS(Engine): PASS

 7004 16:51:03.945570  TX OE            : NO K

 7005 16:51:03.948248  All Pass.

 7006 16:51:03.948888  

 7007 16:51:03.949398  CH 0, Rank 1

 7008 16:51:03.951407  SW Impedance     : PASS

 7009 16:51:03.951942  DUTY Scan        : NO K

 7010 16:51:03.955072  ZQ Calibration   : PASS

 7011 16:51:03.957930  Jitter Meter     : NO K

 7012 16:51:03.958511  CBT Training     : PASS

 7013 16:51:03.961747  Write leveling   : NO K

 7014 16:51:03.964469  RX DQS gating    : PASS

 7015 16:51:03.964937  RX DQ/DQS(RDDQC) : PASS

 7016 16:51:03.968114  TX DQ/DQS        : PASS

 7017 16:51:03.971220  RX DATLAT        : PASS

 7018 16:51:03.971777  RX DQ/DQS(Engine): PASS

 7019 16:51:03.975163  TX OE            : NO K

 7020 16:51:03.975631  All Pass.

 7021 16:51:03.976006  

 7022 16:51:03.978125  CH 1, Rank 0

 7023 16:51:03.978670  SW Impedance     : PASS

 7024 16:51:03.981550  DUTY Scan        : NO K

 7025 16:51:03.984564  ZQ Calibration   : PASS

 7026 16:51:03.985008  Jitter Meter     : NO K

 7027 16:51:03.987752  CBT Training     : PASS

 7028 16:51:03.991194  Write leveling   : PASS

 7029 16:51:03.991778  RX DQS gating    : PASS

 7030 16:51:03.994769  RX DQ/DQS(RDDQC) : PASS

 7031 16:51:03.997644  TX DQ/DQS        : PASS

 7032 16:51:03.998099  RX DATLAT        : PASS

 7033 16:51:04.000775  RX DQ/DQS(Engine): PASS

 7034 16:51:04.004480  TX OE            : NO K

 7035 16:51:04.004927  All Pass.

 7036 16:51:04.005310  

 7037 16:51:04.005742  CH 1, Rank 1

 7038 16:51:04.007477  SW Impedance     : PASS

 7039 16:51:04.011015  DUTY Scan        : NO K

 7040 16:51:04.011452  ZQ Calibration   : PASS

 7041 16:51:04.014016  Jitter Meter     : NO K

 7042 16:51:04.014507  CBT Training     : PASS

 7043 16:51:04.018275  Write leveling   : NO K

 7044 16:51:04.020561  RX DQS gating    : PASS

 7045 16:51:04.021140  RX DQ/DQS(RDDQC) : PASS

 7046 16:51:04.024305  TX DQ/DQS        : PASS

 7047 16:51:04.027418  RX DATLAT        : PASS

 7048 16:51:04.027865  RX DQ/DQS(Engine): PASS

 7049 16:51:04.030628  TX OE            : NO K

 7050 16:51:04.031068  All Pass.

 7051 16:51:04.031423  

 7052 16:51:04.034232  DramC Write-DBI off

 7053 16:51:04.037239  	PER_BANK_REFRESH: Hybrid Mode

 7054 16:51:04.037675  TX_TRACKING: ON

 7055 16:51:04.047261  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7056 16:51:04.050247  [FAST_K] Save calibration result to emmc

 7057 16:51:04.053661  dramc_set_vcore_voltage set vcore to 725000

 7058 16:51:04.056877  Read voltage for 1600, 0

 7059 16:51:04.057312  Vio18 = 0

 7060 16:51:04.060380  Vcore = 725000

 7061 16:51:04.060830  Vdram = 0

 7062 16:51:04.061187  Vddq = 0

 7063 16:51:04.061512  Vmddr = 0

 7064 16:51:04.067009  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7065 16:51:04.073620  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7066 16:51:04.074067  MEM_TYPE=3, freq_sel=13

 7067 16:51:04.077541  sv_algorithm_assistance_LP4_3733 

 7068 16:51:04.080219  ============ PULL DRAM RESETB DOWN ============

 7069 16:51:04.086712  ========== PULL DRAM RESETB DOWN end =========

 7070 16:51:04.090080  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7071 16:51:04.093343  =================================== 

 7072 16:51:04.096620  LPDDR4 DRAM CONFIGURATION

 7073 16:51:04.099624  =================================== 

 7074 16:51:04.100067  EX_ROW_EN[0]    = 0x0

 7075 16:51:04.103231  EX_ROW_EN[1]    = 0x0

 7076 16:51:04.103673  LP4Y_EN      = 0x0

 7077 16:51:04.106437  WORK_FSP     = 0x1

 7078 16:51:04.110143  WL           = 0x5

 7079 16:51:04.110636  RL           = 0x5

 7080 16:51:04.113102  BL           = 0x2

 7081 16:51:04.113667  RPST         = 0x0

 7082 16:51:04.116697  RD_PRE       = 0x0

 7083 16:51:04.117140  WR_PRE       = 0x1

 7084 16:51:04.119576  WR_PST       = 0x1

 7085 16:51:04.120025  DBI_WR       = 0x0

 7086 16:51:04.123149  DBI_RD       = 0x0

 7087 16:51:04.123586  OTF          = 0x1

 7088 16:51:04.126681  =================================== 

 7089 16:51:04.142395  =================================== 

 7090 16:51:04.142869  ANA top config

 7091 16:51:04.143227  =================================== 

 7092 16:51:04.143561  DLL_ASYNC_EN            =  0

 7093 16:51:04.143875  ALL_SLAVE_EN            =  0

 7094 16:51:04.144498  NEW_RANK_MODE           =  1

 7095 16:51:04.146242  DLL_IDLE_MODE           =  1

 7096 16:51:04.149207  LP45_APHY_COMB_EN       =  1

 7097 16:51:04.149878  TX_ODT_DIS              =  0

 7098 16:51:04.152803  NEW_8X_MODE             =  1

 7099 16:51:04.155906  =================================== 

 7100 16:51:04.159384  =================================== 

 7101 16:51:04.162649  data_rate                  = 3200

 7102 16:51:04.165806  CKR                        = 1

 7103 16:51:04.169373  DQ_P2S_RATIO               = 8

 7104 16:51:04.172596  =================================== 

 7105 16:51:04.173033  CA_P2S_RATIO               = 8

 7106 16:51:04.176014  DQ_CA_OPEN                 = 0

 7107 16:51:04.179207  DQ_SEMI_OPEN               = 0

 7108 16:51:04.182278  CA_SEMI_OPEN               = 0

 7109 16:51:04.185732  CA_FULL_RATE               = 0

 7110 16:51:04.189113  DQ_CKDIV4_EN               = 0

 7111 16:51:04.189625  CA_CKDIV4_EN               = 0

 7112 16:51:04.192442  CA_PREDIV_EN               = 0

 7113 16:51:04.195654  PH8_DLY                    = 12

 7114 16:51:04.198755  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7115 16:51:04.202424  DQ_AAMCK_DIV               = 4

 7116 16:51:04.205240  CA_AAMCK_DIV               = 4

 7117 16:51:04.208607  CA_ADMCK_DIV               = 4

 7118 16:51:04.209118  DQ_TRACK_CA_EN             = 0

 7119 16:51:04.212241  CA_PICK                    = 1600

 7120 16:51:04.215337  CA_MCKIO                   = 1600

 7121 16:51:04.218515  MCKIO_SEMI                 = 0

 7122 16:51:04.222083  PLL_FREQ                   = 3068

 7123 16:51:04.225049  DQ_UI_PI_RATIO             = 32

 7124 16:51:04.228403  CA_UI_PI_RATIO             = 0

 7125 16:51:04.231608  =================================== 

 7126 16:51:04.235100  =================================== 

 7127 16:51:04.235184  memory_type:LPDDR4         

 7128 16:51:04.238250  GP_NUM     : 10       

 7129 16:51:04.241382  SRAM_EN    : 1       

 7130 16:51:04.241465  MD32_EN    : 0       

 7131 16:51:04.244968  =================================== 

 7132 16:51:04.248295  [ANA_INIT] >>>>>>>>>>>>>> 

 7133 16:51:04.251460  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7134 16:51:04.254732  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7135 16:51:04.258207  =================================== 

 7136 16:51:04.261381  data_rate = 3200,PCW = 0X7600

 7137 16:51:04.264924  =================================== 

 7138 16:51:04.268053  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7139 16:51:04.271321  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7140 16:51:04.278085  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7141 16:51:04.281419  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7142 16:51:04.284324  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7143 16:51:04.287780  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7144 16:51:04.291382  [ANA_INIT] flow start 

 7145 16:51:04.294568  [ANA_INIT] PLL >>>>>>>> 

 7146 16:51:04.294650  [ANA_INIT] PLL <<<<<<<< 

 7147 16:51:04.297527  [ANA_INIT] MIDPI >>>>>>>> 

 7148 16:51:04.300814  [ANA_INIT] MIDPI <<<<<<<< 

 7149 16:51:04.304184  [ANA_INIT] DLL >>>>>>>> 

 7150 16:51:04.304267  [ANA_INIT] DLL <<<<<<<< 

 7151 16:51:04.308012  [ANA_INIT] flow end 

 7152 16:51:04.310911  ============ LP4 DIFF to SE enter ============

 7153 16:51:04.314022  ============ LP4 DIFF to SE exit  ============

 7154 16:51:04.317844  [ANA_INIT] <<<<<<<<<<<<< 

 7155 16:51:04.321026  [Flow] Enable top DCM control >>>>> 

 7156 16:51:04.324351  [Flow] Enable top DCM control <<<<< 

 7157 16:51:04.327496  Enable DLL master slave shuffle 

 7158 16:51:04.333744  ============================================================== 

 7159 16:51:04.333828  Gating Mode config

 7160 16:51:04.340475  ============================================================== 

 7161 16:51:04.340558  Config description: 

 7162 16:51:04.350831  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7163 16:51:04.357002  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7164 16:51:04.363663  SELPH_MODE            0: By rank         1: By Phase 

 7165 16:51:04.367084  ============================================================== 

 7166 16:51:04.370586  GAT_TRACK_EN                 =  1

 7167 16:51:04.373898  RX_GATING_MODE               =  2

 7168 16:51:04.377406  RX_GATING_TRACK_MODE         =  2

 7169 16:51:04.379975  SELPH_MODE                   =  1

 7170 16:51:04.383407  PICG_EARLY_EN                =  1

 7171 16:51:04.386915  VALID_LAT_VALUE              =  1

 7172 16:51:04.393878  ============================================================== 

 7173 16:51:04.397204  Enter into Gating configuration >>>> 

 7174 16:51:04.400107  Exit from Gating configuration <<<< 

 7175 16:51:04.403091  Enter into  DVFS_PRE_config >>>>> 

 7176 16:51:04.413201  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7177 16:51:04.416518  Exit from  DVFS_PRE_config <<<<< 

 7178 16:51:04.419799  Enter into PICG configuration >>>> 

 7179 16:51:04.423186  Exit from PICG configuration <<<< 

 7180 16:51:04.426825  [RX_INPUT] configuration >>>>> 

 7181 16:51:04.429757  [RX_INPUT] configuration <<<<< 

 7182 16:51:04.433036  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7183 16:51:04.439645  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7184 16:51:04.446410  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7185 16:51:04.449440  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7186 16:51:04.455997  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7187 16:51:04.463296  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7188 16:51:04.466245  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7189 16:51:04.469565  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7190 16:51:04.475884  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7191 16:51:04.479330  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7192 16:51:04.482748  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7193 16:51:04.489094  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7194 16:51:04.492292  =================================== 

 7195 16:51:04.492371  LPDDR4 DRAM CONFIGURATION

 7196 16:51:04.495545  =================================== 

 7197 16:51:04.498957  EX_ROW_EN[0]    = 0x0

 7198 16:51:04.502749  EX_ROW_EN[1]    = 0x0

 7199 16:51:04.502836  LP4Y_EN      = 0x0

 7200 16:51:04.506068  WORK_FSP     = 0x1

 7201 16:51:04.506168  WL           = 0x5

 7202 16:51:04.508942  RL           = 0x5

 7203 16:51:04.509019  BL           = 0x2

 7204 16:51:04.512075  RPST         = 0x0

 7205 16:51:04.512155  RD_PRE       = 0x0

 7206 16:51:04.515376  WR_PRE       = 0x1

 7207 16:51:04.515455  WR_PST       = 0x1

 7208 16:51:04.518709  DBI_WR       = 0x0

 7209 16:51:04.518789  DBI_RD       = 0x0

 7210 16:51:04.522259  OTF          = 0x1

 7211 16:51:04.525350  =================================== 

 7212 16:51:04.528327  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7213 16:51:04.531782  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7214 16:51:04.538219  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7215 16:51:04.541543  =================================== 

 7216 16:51:04.541620  LPDDR4 DRAM CONFIGURATION

 7217 16:51:04.545011  =================================== 

 7218 16:51:04.548331  EX_ROW_EN[0]    = 0x10

 7219 16:51:04.551520  EX_ROW_EN[1]    = 0x0

 7220 16:51:04.551594  LP4Y_EN      = 0x0

 7221 16:51:04.554650  WORK_FSP     = 0x1

 7222 16:51:04.554722  WL           = 0x5

 7223 16:51:04.557963  RL           = 0x5

 7224 16:51:04.558034  BL           = 0x2

 7225 16:51:04.561439  RPST         = 0x0

 7226 16:51:04.561517  RD_PRE       = 0x0

 7227 16:51:04.564571  WR_PRE       = 0x1

 7228 16:51:04.564643  WR_PST       = 0x1

 7229 16:51:04.568086  DBI_WR       = 0x0

 7230 16:51:04.568163  DBI_RD       = 0x0

 7231 16:51:04.571391  OTF          = 0x1

 7232 16:51:04.574493  =================================== 

 7233 16:51:04.580989  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7234 16:51:04.581066  ==

 7235 16:51:04.584097  Dram Type= 6, Freq= 0, CH_0, rank 0

 7236 16:51:04.587708  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7237 16:51:04.587784  ==

 7238 16:51:04.591252  [Duty_Offset_Calibration]

 7239 16:51:04.591326  	B0:2	B1:0	CA:1

 7240 16:51:04.591397  

 7241 16:51:04.594008  [DutyScan_Calibration_Flow] k_type=0

 7242 16:51:04.604880  

 7243 16:51:04.604960  ==CLK 0==

 7244 16:51:04.608317  Final CLK duty delay cell = -4

 7245 16:51:04.611849  [-4] MAX Duty = 5031%(X100), DQS PI = 30

 7246 16:51:04.614503  [-4] MIN Duty = 4813%(X100), DQS PI = 0

 7247 16:51:04.618243  [-4] AVG Duty = 4922%(X100)

 7248 16:51:04.618344  

 7249 16:51:04.621262  CH0 CLK Duty spec in!! Max-Min= 218%

 7250 16:51:04.624476  [DutyScan_Calibration_Flow] ====Done====

 7251 16:51:04.624564  

 7252 16:51:04.627619  [DutyScan_Calibration_Flow] k_type=1

 7253 16:51:04.644010  

 7254 16:51:04.644088  ==DQS 0 ==

 7255 16:51:04.647897  Final DQS duty delay cell = 0

 7256 16:51:04.651173  [0] MAX Duty = 5249%(X100), DQS PI = 32

 7257 16:51:04.654246  [0] MIN Duty = 4969%(X100), DQS PI = 0

 7258 16:51:04.654326  [0] AVG Duty = 5109%(X100)

 7259 16:51:04.657436  

 7260 16:51:04.657514  ==DQS 1 ==

 7261 16:51:04.660789  Final DQS duty delay cell = -4

 7262 16:51:04.664409  [-4] MAX Duty = 5125%(X100), DQS PI = 28

 7263 16:51:04.667631  [-4] MIN Duty = 4875%(X100), DQS PI = 4

 7264 16:51:04.670658  [-4] AVG Duty = 5000%(X100)

 7265 16:51:04.670731  

 7266 16:51:04.674405  CH0 DQS 0 Duty spec in!! Max-Min= 280%

 7267 16:51:04.674479  

 7268 16:51:04.677606  CH0 DQS 1 Duty spec in!! Max-Min= 250%

 7269 16:51:04.680871  [DutyScan_Calibration_Flow] ====Done====

 7270 16:51:04.680943  

 7271 16:51:04.683914  [DutyScan_Calibration_Flow] k_type=3

 7272 16:51:04.701629  

 7273 16:51:04.701706  ==DQM 0 ==

 7274 16:51:04.704861  Final DQM duty delay cell = 0

 7275 16:51:04.708015  [0] MAX Duty = 5093%(X100), DQS PI = 26

 7276 16:51:04.711655  [0] MIN Duty = 4813%(X100), DQS PI = 52

 7277 16:51:04.714687  [0] AVG Duty = 4953%(X100)

 7278 16:51:04.714763  

 7279 16:51:04.714827  ==DQM 1 ==

 7280 16:51:04.718187  Final DQM duty delay cell = 0

 7281 16:51:04.721397  [0] MAX Duty = 5249%(X100), DQS PI = 30

 7282 16:51:04.724791  [0] MIN Duty = 5000%(X100), DQS PI = 20

 7283 16:51:04.728120  [0] AVG Duty = 5124%(X100)

 7284 16:51:04.728203  

 7285 16:51:04.731224  CH0 DQM 0 Duty spec in!! Max-Min= 280%

 7286 16:51:04.731299  

 7287 16:51:04.735223  CH0 DQM 1 Duty spec in!! Max-Min= 249%

 7288 16:51:04.738224  [DutyScan_Calibration_Flow] ====Done====

 7289 16:51:04.738330  

 7290 16:51:04.741408  [DutyScan_Calibration_Flow] k_type=2

 7291 16:51:04.759063  

 7292 16:51:04.759139  ==DQ 0 ==

 7293 16:51:04.762357  Final DQ duty delay cell = 0

 7294 16:51:04.765589  [0] MAX Duty = 5156%(X100), DQS PI = 38

 7295 16:51:04.768766  [0] MIN Duty = 5000%(X100), DQS PI = 16

 7296 16:51:04.768839  [0] AVG Duty = 5078%(X100)

 7297 16:51:04.772396  

 7298 16:51:04.772469  ==DQ 1 ==

 7299 16:51:04.775446  Final DQ duty delay cell = 0

 7300 16:51:04.778834  [0] MAX Duty = 4969%(X100), DQS PI = 42

 7301 16:51:04.782405  [0] MIN Duty = 4875%(X100), DQS PI = 10

 7302 16:51:04.782478  [0] AVG Duty = 4922%(X100)

 7303 16:51:04.782540  

 7304 16:51:04.785619  CH0 DQ 0 Duty spec in!! Max-Min= 156%

 7305 16:51:04.788715  

 7306 16:51:04.792211  CH0 DQ 1 Duty spec in!! Max-Min= 94%

 7307 16:51:04.795375  [DutyScan_Calibration_Flow] ====Done====

 7308 16:51:04.795450  ==

 7309 16:51:04.798956  Dram Type= 6, Freq= 0, CH_1, rank 0

 7310 16:51:04.802249  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7311 16:51:04.802354  ==

 7312 16:51:04.805474  [Duty_Offset_Calibration]

 7313 16:51:04.805545  	B0:0	B1:-1	CA:2

 7314 16:51:04.805606  

 7315 16:51:04.808603  [DutyScan_Calibration_Flow] k_type=0

 7316 16:51:04.819201  

 7317 16:51:04.819287  ==CLK 0==

 7318 16:51:04.822642  Final CLK duty delay cell = 0

 7319 16:51:04.825850  [0] MAX Duty = 5156%(X100), DQS PI = 10

 7320 16:51:04.828858  [0] MIN Duty = 4938%(X100), DQS PI = 44

 7321 16:51:04.832477  [0] AVG Duty = 5047%(X100)

 7322 16:51:04.832547  

 7323 16:51:04.835721  CH1 CLK Duty spec in!! Max-Min= 218%

 7324 16:51:04.838869  [DutyScan_Calibration_Flow] ====Done====

 7325 16:51:04.838943  

 7326 16:51:04.842132  [DutyScan_Calibration_Flow] k_type=1

 7327 16:51:04.858974  

 7328 16:51:04.859052  ==DQS 0 ==

 7329 16:51:04.862571  Final DQS duty delay cell = 0

 7330 16:51:04.865351  [0] MAX Duty = 5093%(X100), DQS PI = 24

 7331 16:51:04.868831  [0] MIN Duty = 5000%(X100), DQS PI = 0

 7332 16:51:04.872109  [0] AVG Duty = 5046%(X100)

 7333 16:51:04.872181  

 7334 16:51:04.872242  ==DQS 1 ==

 7335 16:51:04.875384  Final DQS duty delay cell = 0

 7336 16:51:04.878521  [0] MAX Duty = 5187%(X100), DQS PI = 0

 7337 16:51:04.882085  [0] MIN Duty = 4844%(X100), DQS PI = 32

 7338 16:51:04.885301  [0] AVG Duty = 5015%(X100)

 7339 16:51:04.885372  

 7340 16:51:04.888767  CH1 DQS 0 Duty spec in!! Max-Min= 93%

 7341 16:51:04.888834  

 7342 16:51:04.892169  CH1 DQS 1 Duty spec in!! Max-Min= 343%

 7343 16:51:04.895240  [DutyScan_Calibration_Flow] ====Done====

 7344 16:51:04.895324  

 7345 16:51:04.898345  [DutyScan_Calibration_Flow] k_type=3

 7346 16:51:04.916664  

 7347 16:51:04.916747  ==DQM 0 ==

 7348 16:51:04.919597  Final DQM duty delay cell = 4

 7349 16:51:04.923206  [4] MAX Duty = 5125%(X100), DQS PI = 6

 7350 16:51:04.926559  [4] MIN Duty = 4969%(X100), DQS PI = 36

 7351 16:51:04.926655  [4] AVG Duty = 5047%(X100)

 7352 16:51:04.929885  

 7353 16:51:04.929969  ==DQM 1 ==

 7354 16:51:04.933499  Final DQM duty delay cell = 0

 7355 16:51:04.936272  [0] MAX Duty = 5281%(X100), DQS PI = 58

 7356 16:51:04.939808  [0] MIN Duty = 4876%(X100), DQS PI = 34

 7357 16:51:04.943191  [0] AVG Duty = 5078%(X100)

 7358 16:51:04.943268  

 7359 16:51:04.946390  CH1 DQM 0 Duty spec in!! Max-Min= 156%

 7360 16:51:04.946473  

 7361 16:51:04.949619  CH1 DQM 1 Duty spec in!! Max-Min= 405%

 7362 16:51:04.952807  [DutyScan_Calibration_Flow] ====Done====

 7363 16:51:04.952890  

 7364 16:51:04.956188  [DutyScan_Calibration_Flow] k_type=2

 7365 16:51:04.973487  

 7366 16:51:04.973564  ==DQ 0 ==

 7367 16:51:04.976397  Final DQ duty delay cell = 0

 7368 16:51:04.979969  [0] MAX Duty = 5093%(X100), DQS PI = 20

 7369 16:51:04.983304  [0] MIN Duty = 4969%(X100), DQS PI = 46

 7370 16:51:04.983379  [0] AVG Duty = 5031%(X100)

 7371 16:51:04.986271  

 7372 16:51:04.986345  ==DQ 1 ==

 7373 16:51:04.989867  Final DQ duty delay cell = 0

 7374 16:51:04.992981  [0] MAX Duty = 5062%(X100), DQS PI = 2

 7375 16:51:04.996245  [0] MIN Duty = 4813%(X100), DQS PI = 34

 7376 16:51:04.996327  [0] AVG Duty = 4937%(X100)

 7377 16:51:04.999906  

 7378 16:51:05.002977  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 7379 16:51:05.003052  

 7380 16:51:05.006612  CH1 DQ 1 Duty spec in!! Max-Min= 249%

 7381 16:51:05.009848  [DutyScan_Calibration_Flow] ====Done====

 7382 16:51:05.012918  nWR fixed to 30

 7383 16:51:05.012993  [ModeRegInit_LP4] CH0 RK0

 7384 16:51:05.016209  [ModeRegInit_LP4] CH0 RK1

 7385 16:51:05.019789  [ModeRegInit_LP4] CH1 RK0

 7386 16:51:05.023354  [ModeRegInit_LP4] CH1 RK1

 7387 16:51:05.023461  match AC timing 5

 7388 16:51:05.026240  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7389 16:51:05.033239  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7390 16:51:05.036369  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7391 16:51:05.042781  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7392 16:51:05.046616  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7393 16:51:05.046699  [MiockJmeterHQA]

 7394 16:51:05.046763  

 7395 16:51:05.049760  [DramcMiockJmeter] u1RxGatingPI = 0

 7396 16:51:05.052713  0 : 4252, 4027

 7397 16:51:05.052788  4 : 4363, 4137

 7398 16:51:05.055950  8 : 4363, 4138

 7399 16:51:05.056026  12 : 4253, 4027

 7400 16:51:05.056099  16 : 4363, 4137

 7401 16:51:05.059449  20 : 4253, 4026

 7402 16:51:05.059530  24 : 4363, 4138

 7403 16:51:05.062711  28 : 4253, 4026

 7404 16:51:05.062789  32 : 4252, 4027

 7405 16:51:05.065907  36 : 4252, 4027

 7406 16:51:05.065989  40 : 4255, 4029

 7407 16:51:05.069320  44 : 4250, 4027

 7408 16:51:05.069395  48 : 4360, 4137

 7409 16:51:05.069466  52 : 4361, 4137

 7410 16:51:05.072715  56 : 4250, 4027

 7411 16:51:05.072790  60 : 4250, 4026

 7412 16:51:05.075958  64 : 4250, 4027

 7413 16:51:05.076033  68 : 4249, 4027

 7414 16:51:05.079486  72 : 4253, 4029

 7415 16:51:05.079568  76 : 4361, 4138

 7416 16:51:05.082447  80 : 4250, 4026

 7417 16:51:05.082521  84 : 4250, 4027

 7418 16:51:05.082584  88 : 4250, 3322

 7419 16:51:05.085794  92 : 4253, 0

 7420 16:51:05.085869  96 : 4250, 0

 7421 16:51:05.089174  100 : 4253, 0

 7422 16:51:05.089248  104 : 4252, 0

 7423 16:51:05.089319  108 : 4253, 0

 7424 16:51:05.092444  112 : 4360, 0

 7425 16:51:05.092517  116 : 4361, 0

 7426 16:51:05.092579  120 : 4363, 0

 7427 16:51:05.095415  124 : 4250, 0

 7428 16:51:05.095516  128 : 4250, 0

 7429 16:51:05.098823  132 : 4250, 0

 7430 16:51:05.098897  136 : 4250, 0

 7431 16:51:05.098958  140 : 4250, 0

 7432 16:51:05.102527  144 : 4250, 0

 7433 16:51:05.102612  148 : 4253, 0

 7434 16:51:05.105616  152 : 4363, 0

 7435 16:51:05.105699  156 : 4250, 0

 7436 16:51:05.105766  160 : 4250, 0

 7437 16:51:05.108732  164 : 4360, 0

 7438 16:51:05.108806  168 : 4361, 0

 7439 16:51:05.112232  172 : 4363, 0

 7440 16:51:05.112313  176 : 4250, 0

 7441 16:51:05.112377  180 : 4360, 0

 7442 16:51:05.115433  184 : 4250, 0

 7443 16:51:05.115506  188 : 4250, 0

 7444 16:51:05.119097  192 : 4250, 0

 7445 16:51:05.119171  196 : 4250, 0

 7446 16:51:05.119234  200 : 4253, 3

 7447 16:51:05.122279  204 : 4250, 2433

 7448 16:51:05.122414  208 : 4250, 4026

 7449 16:51:05.125421  212 : 4363, 4140

 7450 16:51:05.125509  216 : 4250, 4027

 7451 16:51:05.128739  220 : 4250, 4027

 7452 16:51:05.128814  224 : 4253, 4026

 7453 16:51:05.131987  228 : 4253, 4029

 7454 16:51:05.132067  232 : 4250, 4027

 7455 16:51:05.135022  236 : 4249, 4027

 7456 16:51:05.135096  240 : 4360, 4137

 7457 16:51:05.138537  244 : 4250, 4027

 7458 16:51:05.138611  248 : 4250, 4027

 7459 16:51:05.138674  252 : 4360, 4138

 7460 16:51:05.141752  256 : 4250, 4027

 7461 16:51:05.141825  260 : 4250, 4026

 7462 16:51:05.145314  264 : 4363, 4140

 7463 16:51:05.145395  268 : 4250, 4027

 7464 16:51:05.148585  272 : 4251, 4027

 7465 16:51:05.148666  276 : 4250, 4026

 7466 16:51:05.151966  280 : 4253, 4029

 7467 16:51:05.152046  284 : 4250, 4027

 7468 16:51:05.155323  288 : 4250, 4027

 7469 16:51:05.155396  292 : 4360, 4137

 7470 16:51:05.158573  296 : 4250, 4027

 7471 16:51:05.158652  300 : 4250, 4027

 7472 16:51:05.161698  304 : 4361, 4138

 7473 16:51:05.161772  308 : 4250, 4027

 7474 16:51:05.164862  312 : 4250, 3891

 7475 16:51:05.164935  316 : 4363, 1847

 7476 16:51:05.164998  

 7477 16:51:05.168228  	MIOCK jitter meter	ch=0

 7478 16:51:05.168301  

 7479 16:51:05.171298  1T = (316-92) = 224 dly cells

 7480 16:51:05.174709  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps

 7481 16:51:05.174787  ==

 7482 16:51:05.178344  Dram Type= 6, Freq= 0, CH_0, rank 0

 7483 16:51:05.184629  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7484 16:51:05.184705  ==

 7485 16:51:05.187884  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7486 16:51:05.195067  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7487 16:51:05.197695  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7488 16:51:05.204534  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7489 16:51:05.212028  [CA 0] Center 43 (13~73) winsize 61

 7490 16:51:05.215304  [CA 1] Center 43 (13~73) winsize 61

 7491 16:51:05.218848  [CA 2] Center 38 (8~68) winsize 61

 7492 16:51:05.221894  [CA 3] Center 37 (8~67) winsize 60

 7493 16:51:05.225399  [CA 4] Center 36 (6~66) winsize 61

 7494 16:51:05.228540  [CA 5] Center 35 (5~65) winsize 61

 7495 16:51:05.228615  

 7496 16:51:05.232026  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7497 16:51:05.232100  

 7498 16:51:05.235541  [CATrainingPosCal] consider 1 rank data

 7499 16:51:05.238373  u2DelayCellTimex100 = 290/100 ps

 7500 16:51:05.245205  CA0 delay=43 (13~73),Diff = 8 PI (26 cell)

 7501 16:51:05.248287  CA1 delay=43 (13~73),Diff = 8 PI (26 cell)

 7502 16:51:05.251610  CA2 delay=38 (8~68),Diff = 3 PI (10 cell)

 7503 16:51:05.254889  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7504 16:51:05.258327  CA4 delay=36 (6~66),Diff = 1 PI (3 cell)

 7505 16:51:05.261806  CA5 delay=35 (5~65),Diff = 0 PI (0 cell)

 7506 16:51:05.261879  

 7507 16:51:05.264571  CA PerBit enable=1, Macro0, CA PI delay=35

 7508 16:51:05.264697  

 7509 16:51:05.267914  [CBTSetCACLKResult] CA Dly = 35

 7510 16:51:05.271586  CS Dly: 9 (0~40)

 7511 16:51:05.274750  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7512 16:51:05.278366  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7513 16:51:05.278454  ==

 7514 16:51:05.281473  Dram Type= 6, Freq= 0, CH_0, rank 1

 7515 16:51:05.287944  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7516 16:51:05.288030  ==

 7517 16:51:05.291439  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7518 16:51:05.297976  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7519 16:51:05.301619  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7520 16:51:05.307728  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7521 16:51:05.315420  [CA 0] Center 43 (13~73) winsize 61

 7522 16:51:05.318526  [CA 1] Center 43 (13~73) winsize 61

 7523 16:51:05.322203  [CA 2] Center 38 (9~67) winsize 59

 7524 16:51:05.325221  [CA 3] Center 38 (8~68) winsize 61

 7525 16:51:05.328794  [CA 4] Center 36 (6~67) winsize 62

 7526 16:51:05.331952  [CA 5] Center 36 (6~66) winsize 61

 7527 16:51:05.332045  

 7528 16:51:05.335493  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7529 16:51:05.335584  

 7530 16:51:05.338711  [CATrainingPosCal] consider 2 rank data

 7531 16:51:05.341807  u2DelayCellTimex100 = 290/100 ps

 7532 16:51:05.348494  CA0 delay=43 (13~73),Diff = 8 PI (26 cell)

 7533 16:51:05.351639  CA1 delay=43 (13~73),Diff = 8 PI (26 cell)

 7534 16:51:05.354956  CA2 delay=38 (9~67),Diff = 3 PI (10 cell)

 7535 16:51:05.358223  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7536 16:51:05.361674  CA4 delay=36 (6~66),Diff = 1 PI (3 cell)

 7537 16:51:05.365307  CA5 delay=35 (6~65),Diff = 0 PI (0 cell)

 7538 16:51:05.365381  

 7539 16:51:05.368437  CA PerBit enable=1, Macro0, CA PI delay=35

 7540 16:51:05.368517  

 7541 16:51:05.371719  [CBTSetCACLKResult] CA Dly = 35

 7542 16:51:05.374971  CS Dly: 10 (0~43)

 7543 16:51:05.378343  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7544 16:51:05.381504  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7545 16:51:05.381611  

 7546 16:51:05.384931  ----->DramcWriteLeveling(PI) begin...

 7547 16:51:05.385001  ==

 7548 16:51:05.388459  Dram Type= 6, Freq= 0, CH_0, rank 0

 7549 16:51:05.394912  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7550 16:51:05.394997  ==

 7551 16:51:05.398123  Write leveling (Byte 0): 37 => 37

 7552 16:51:05.401191  Write leveling (Byte 1): 33 => 33

 7553 16:51:05.401273  DramcWriteLeveling(PI) end<-----

 7554 16:51:05.401333  

 7555 16:51:05.405188  ==

 7556 16:51:05.408267  Dram Type= 6, Freq= 0, CH_0, rank 0

 7557 16:51:05.411439  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7558 16:51:05.411519  ==

 7559 16:51:05.415005  [Gating] SW mode calibration

 7560 16:51:05.421433  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7561 16:51:05.424832  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7562 16:51:05.431549   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7563 16:51:05.434616   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7564 16:51:05.438179   1  4  8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)

 7565 16:51:05.444655   1  4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 7566 16:51:05.447951   1  4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)

 7567 16:51:05.451067   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7568 16:51:05.457975   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7569 16:51:05.461157   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7570 16:51:05.464401   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7571 16:51:05.470805   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7572 16:51:05.474482   1  5  8 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 1)

 7573 16:51:05.477344   1  5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)

 7574 16:51:05.483889   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)

 7575 16:51:05.487147   1  5 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)

 7576 16:51:05.490665   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7577 16:51:05.497456   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7578 16:51:05.500430   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7579 16:51:05.504070   1  6  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7580 16:51:05.510452   1  6  8 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)

 7581 16:51:05.513644   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 7582 16:51:05.517381   1  6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)

 7583 16:51:05.523898   1  6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 7584 16:51:05.527032   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7585 16:51:05.530126   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7586 16:51:05.537089   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7587 16:51:05.540312   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7588 16:51:05.543764   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7589 16:51:05.550258   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7590 16:51:05.553476   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 7591 16:51:05.556861   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7592 16:51:05.563859   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7593 16:51:05.566686   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7594 16:51:05.569865   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7595 16:51:05.576564   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7596 16:51:05.580064   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7597 16:51:05.583107   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7598 16:51:05.589927   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7599 16:51:05.593299   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7600 16:51:05.596272   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7601 16:51:05.603233   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7602 16:51:05.606819   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7603 16:51:05.609614   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7604 16:51:05.616081   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7605 16:51:05.619594   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 7606 16:51:05.622797  Total UI for P1: 0, mck2ui 16

 7607 16:51:05.626493  best dqsien dly found for B0: ( 1,  9,  8)

 7608 16:51:05.629354   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 7609 16:51:05.636063   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7610 16:51:05.639128   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7611 16:51:05.642638  Total UI for P1: 0, mck2ui 16

 7612 16:51:05.645677  best dqsien dly found for B1: ( 1,  9, 20)

 7613 16:51:05.649204  best DQS0 dly(MCK, UI, PI) = (1, 9, 8)

 7614 16:51:05.652286  best DQS1 dly(MCK, UI, PI) = (1, 9, 20)

 7615 16:51:05.652384  

 7616 16:51:05.655468  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)

 7617 16:51:05.659139  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)

 7618 16:51:05.662260  [Gating] SW calibration Done

 7619 16:51:05.662381  ==

 7620 16:51:05.666481  Dram Type= 6, Freq= 0, CH_0, rank 0

 7621 16:51:05.668837  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7622 16:51:05.672122  ==

 7623 16:51:05.672218  RX Vref Scan: 0

 7624 16:51:05.672315  

 7625 16:51:05.675973  RX Vref 0 -> 0, step: 1

 7626 16:51:05.676045  

 7627 16:51:05.676106  RX Delay 0 -> 252, step: 8

 7628 16:51:05.682056  iDelay=200, Bit 0, Center 139 (88 ~ 191) 104

 7629 16:51:05.685693  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 7630 16:51:05.688707  iDelay=200, Bit 2, Center 135 (88 ~ 183) 96

 7631 16:51:05.692240  iDelay=200, Bit 3, Center 135 (88 ~ 183) 96

 7632 16:51:05.695702  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7633 16:51:05.702060  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7634 16:51:05.705471  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 7635 16:51:05.708741  iDelay=200, Bit 7, Center 147 (96 ~ 199) 104

 7636 16:51:05.711843  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 7637 16:51:05.715264  iDelay=200, Bit 9, Center 115 (64 ~ 167) 104

 7638 16:51:05.721854  iDelay=200, Bit 10, Center 123 (72 ~ 175) 104

 7639 16:51:05.724933  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7640 16:51:05.728435  iDelay=200, Bit 12, Center 131 (80 ~ 183) 104

 7641 16:51:05.731930  iDelay=200, Bit 13, Center 131 (88 ~ 175) 88

 7642 16:51:05.738706  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7643 16:51:05.742142  iDelay=200, Bit 15, Center 135 (88 ~ 183) 96

 7644 16:51:05.742252  ==

 7645 16:51:05.745038  Dram Type= 6, Freq= 0, CH_0, rank 0

 7646 16:51:05.748421  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7647 16:51:05.748530  ==

 7648 16:51:05.748624  DQS Delay:

 7649 16:51:05.751793  DQS0 = 0, DQS1 = 0

 7650 16:51:05.751893  DQM Delay:

 7651 16:51:05.754646  DQM0 = 138, DQM1 = 127

 7652 16:51:05.754745  DQ Delay:

 7653 16:51:05.758289  DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135

 7654 16:51:05.761390  DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147

 7655 16:51:05.764989  DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123

 7656 16:51:05.771454  DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135

 7657 16:51:05.771558  

 7658 16:51:05.771652  

 7659 16:51:05.771751  ==

 7660 16:51:05.774811  Dram Type= 6, Freq= 0, CH_0, rank 0

 7661 16:51:05.777768  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7662 16:51:05.777860  ==

 7663 16:51:05.777952  

 7664 16:51:05.778040  

 7665 16:51:05.781362  	TX Vref Scan disable

 7666 16:51:05.781464   == TX Byte 0 ==

 7667 16:51:05.787796  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 7668 16:51:05.791070  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 7669 16:51:05.791144   == TX Byte 1 ==

 7670 16:51:05.797969  Update DQ  dly =988 (3 ,6, 28)  DQ  OEN =(3 ,3)

 7671 16:51:05.801020  Update DQM dly =988 (3 ,6, 28)  DQM OEN =(3 ,3)

 7672 16:51:05.801122  ==

 7673 16:51:05.804187  Dram Type= 6, Freq= 0, CH_0, rank 0

 7674 16:51:05.807907  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7675 16:51:05.807983  ==

 7676 16:51:05.821540  

 7677 16:51:05.825024  TX Vref early break, caculate TX vref

 7678 16:51:05.828539  TX Vref=16, minBit 4, minWin=23, winSum=379

 7679 16:51:05.831552  TX Vref=18, minBit 7, minWin=23, winSum=387

 7680 16:51:05.834991  TX Vref=20, minBit 6, minWin=24, winSum=398

 7681 16:51:05.838157  TX Vref=22, minBit 0, minWin=25, winSum=407

 7682 16:51:05.841822  TX Vref=24, minBit 2, minWin=25, winSum=414

 7683 16:51:05.847886  TX Vref=26, minBit 7, minWin=25, winSum=423

 7684 16:51:05.851492  TX Vref=28, minBit 0, minWin=26, winSum=430

 7685 16:51:05.854740  TX Vref=30, minBit 2, minWin=26, winSum=422

 7686 16:51:05.857893  TX Vref=32, minBit 2, minWin=24, winSum=410

 7687 16:51:05.861328  TX Vref=34, minBit 2, minWin=24, winSum=404

 7688 16:51:05.867644  [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28

 7689 16:51:05.867749  

 7690 16:51:05.871582  Final TX Range 0 Vref 28

 7691 16:51:05.871684  

 7692 16:51:05.871776  ==

 7693 16:51:05.874702  Dram Type= 6, Freq= 0, CH_0, rank 0

 7694 16:51:05.877922  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7695 16:51:05.878022  ==

 7696 16:51:05.878112  

 7697 16:51:05.878203  

 7698 16:51:05.880987  	TX Vref Scan disable

 7699 16:51:05.887554  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 7700 16:51:05.887673   == TX Byte 0 ==

 7701 16:51:05.890726  u2DelayCellOfst[0]=16 cells (5 PI)

 7702 16:51:05.894208  u2DelayCellOfst[1]=20 cells (6 PI)

 7703 16:51:05.897771  u2DelayCellOfst[2]=13 cells (4 PI)

 7704 16:51:05.900776  u2DelayCellOfst[3]=13 cells (4 PI)

 7705 16:51:05.903886  u2DelayCellOfst[4]=10 cells (3 PI)

 7706 16:51:05.907299  u2DelayCellOfst[5]=0 cells (0 PI)

 7707 16:51:05.910665  u2DelayCellOfst[6]=20 cells (6 PI)

 7708 16:51:05.913970  u2DelayCellOfst[7]=16 cells (5 PI)

 7709 16:51:05.917311  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 7710 16:51:05.920472  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 7711 16:51:05.924096   == TX Byte 1 ==

 7712 16:51:05.927042  u2DelayCellOfst[8]=0 cells (0 PI)

 7713 16:51:05.930215  u2DelayCellOfst[9]=0 cells (0 PI)

 7714 16:51:05.933787  u2DelayCellOfst[10]=10 cells (3 PI)

 7715 16:51:05.933892  u2DelayCellOfst[11]=3 cells (1 PI)

 7716 16:51:05.937188  u2DelayCellOfst[12]=13 cells (4 PI)

 7717 16:51:05.940797  u2DelayCellOfst[13]=13 cells (4 PI)

 7718 16:51:05.943675  u2DelayCellOfst[14]=13 cells (4 PI)

 7719 16:51:05.947127  u2DelayCellOfst[15]=10 cells (3 PI)

 7720 16:51:05.953668  Update DQ  dly =986 (3 ,6, 26)  DQ  OEN =(3 ,3)

 7721 16:51:05.956747  Update DQM dly =988 (3 ,6, 28)  DQM OEN =(3 ,3)

 7722 16:51:05.956852  DramC Write-DBI on

 7723 16:51:05.960247  ==

 7724 16:51:05.963348  Dram Type= 6, Freq= 0, CH_0, rank 0

 7725 16:51:05.967025  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7726 16:51:05.967126  ==

 7727 16:51:05.967218  

 7728 16:51:05.967305  

 7729 16:51:05.970052  	TX Vref Scan disable

 7730 16:51:05.970147   == TX Byte 0 ==

 7731 16:51:05.976890  Update DQM dly =736 (2 ,6, 32)  DQM OEN =(3 ,3)

 7732 16:51:05.976992   == TX Byte 1 ==

 7733 16:51:05.980039  Update DQM dly =730 (2 ,6, 26)  DQM OEN =(3 ,3)

 7734 16:51:05.983344  DramC Write-DBI off

 7735 16:51:05.983442  

 7736 16:51:05.983534  [DATLAT]

 7737 16:51:05.986260  Freq=1600, CH0 RK0

 7738 16:51:05.986360  

 7739 16:51:05.986487  DATLAT Default: 0xf

 7740 16:51:05.989733  0, 0xFFFF, sum = 0

 7741 16:51:05.989834  1, 0xFFFF, sum = 0

 7742 16:51:05.993322  2, 0xFFFF, sum = 0

 7743 16:51:05.993424  3, 0xFFFF, sum = 0

 7744 16:51:05.996234  4, 0xFFFF, sum = 0

 7745 16:51:05.999762  5, 0xFFFF, sum = 0

 7746 16:51:05.999840  6, 0xFFFF, sum = 0

 7747 16:51:06.003212  7, 0xFFFF, sum = 0

 7748 16:51:06.003294  8, 0xFFFF, sum = 0

 7749 16:51:06.006275  9, 0xFFFF, sum = 0

 7750 16:51:06.006413  10, 0xFFFF, sum = 0

 7751 16:51:06.009882  11, 0xFFFF, sum = 0

 7752 16:51:06.009990  12, 0xFFFF, sum = 0

 7753 16:51:06.013824  13, 0xFFFF, sum = 0

 7754 16:51:06.013935  14, 0x0, sum = 1

 7755 16:51:06.016213  15, 0x0, sum = 2

 7756 16:51:06.016288  16, 0x0, sum = 3

 7757 16:51:06.019672  17, 0x0, sum = 4

 7758 16:51:06.019750  best_step = 15

 7759 16:51:06.019815  

 7760 16:51:06.019882  ==

 7761 16:51:06.022693  Dram Type= 6, Freq= 0, CH_0, rank 0

 7762 16:51:06.026598  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7763 16:51:06.029586  ==

 7764 16:51:06.029663  RX Vref Scan: 1

 7765 16:51:06.029754  

 7766 16:51:06.032872  Set Vref Range= 24 -> 127

 7767 16:51:06.032971  

 7768 16:51:06.035858  RX Vref 24 -> 127, step: 1

 7769 16:51:06.035956  

 7770 16:51:06.036046  RX Delay 19 -> 252, step: 4

 7771 16:51:06.036137  

 7772 16:51:06.039530  Set Vref, RX VrefLevel [Byte0]: 24

 7773 16:51:06.042795                           [Byte1]: 24

 7774 16:51:06.046550  

 7775 16:51:06.046639  Set Vref, RX VrefLevel [Byte0]: 25

 7776 16:51:06.049676                           [Byte1]: 25

 7777 16:51:06.054119  

 7778 16:51:06.054216  Set Vref, RX VrefLevel [Byte0]: 26

 7779 16:51:06.057288                           [Byte1]: 26

 7780 16:51:06.061734  

 7781 16:51:06.061833  Set Vref, RX VrefLevel [Byte0]: 27

 7782 16:51:06.064790                           [Byte1]: 27

 7783 16:51:06.069191  

 7784 16:51:06.069291  Set Vref, RX VrefLevel [Byte0]: 28

 7785 16:51:06.072323                           [Byte1]: 28

 7786 16:51:06.076562  

 7787 16:51:06.076664  Set Vref, RX VrefLevel [Byte0]: 29

 7788 16:51:06.079821                           [Byte1]: 29

 7789 16:51:06.084391  

 7790 16:51:06.084489  Set Vref, RX VrefLevel [Byte0]: 30

 7791 16:51:06.088203                           [Byte1]: 30

 7792 16:51:06.092044  

 7793 16:51:06.092140  Set Vref, RX VrefLevel [Byte0]: 31

 7794 16:51:06.095762                           [Byte1]: 31

 7795 16:51:06.099206  

 7796 16:51:06.099282  Set Vref, RX VrefLevel [Byte0]: 32

 7797 16:51:06.102657                           [Byte1]: 32

 7798 16:51:06.107217  

 7799 16:51:06.107314  Set Vref, RX VrefLevel [Byte0]: 33

 7800 16:51:06.110336                           [Byte1]: 33

 7801 16:51:06.114682  

 7802 16:51:06.114758  Set Vref, RX VrefLevel [Byte0]: 34

 7803 16:51:06.118189                           [Byte1]: 34

 7804 16:51:06.122603  

 7805 16:51:06.122711  Set Vref, RX VrefLevel [Byte0]: 35

 7806 16:51:06.125173                           [Byte1]: 35

 7807 16:51:06.129754  

 7808 16:51:06.129863  Set Vref, RX VrefLevel [Byte0]: 36

 7809 16:51:06.133099                           [Byte1]: 36

 7810 16:51:06.137258  

 7811 16:51:06.137359  Set Vref, RX VrefLevel [Byte0]: 37

 7812 16:51:06.140461                           [Byte1]: 37

 7813 16:51:06.144892  

 7814 16:51:06.144990  Set Vref, RX VrefLevel [Byte0]: 38

 7815 16:51:06.148023                           [Byte1]: 38

 7816 16:51:06.152679  

 7817 16:51:06.152782  Set Vref, RX VrefLevel [Byte0]: 39

 7818 16:51:06.155772                           [Byte1]: 39

 7819 16:51:06.159848  

 7820 16:51:06.159921  Set Vref, RX VrefLevel [Byte0]: 40

 7821 16:51:06.163467                           [Byte1]: 40

 7822 16:51:06.167760  

 7823 16:51:06.167861  Set Vref, RX VrefLevel [Byte0]: 41

 7824 16:51:06.171368                           [Byte1]: 41

 7825 16:51:06.175410  

 7826 16:51:06.175485  Set Vref, RX VrefLevel [Byte0]: 42

 7827 16:51:06.178364                           [Byte1]: 42

 7828 16:51:06.182710  

 7829 16:51:06.182806  Set Vref, RX VrefLevel [Byte0]: 43

 7830 16:51:06.186254                           [Byte1]: 43

 7831 16:51:06.190776  

 7832 16:51:06.190877  Set Vref, RX VrefLevel [Byte0]: 44

 7833 16:51:06.193420                           [Byte1]: 44

 7834 16:51:06.197822  

 7835 16:51:06.197923  Set Vref, RX VrefLevel [Byte0]: 45

 7836 16:51:06.201509                           [Byte1]: 45

 7837 16:51:06.205453  

 7838 16:51:06.205551  Set Vref, RX VrefLevel [Byte0]: 46

 7839 16:51:06.208714                           [Byte1]: 46

 7840 16:51:06.212850  

 7841 16:51:06.212945  Set Vref, RX VrefLevel [Byte0]: 47

 7842 16:51:06.216836                           [Byte1]: 47

 7843 16:51:06.220540  

 7844 16:51:06.220637  Set Vref, RX VrefLevel [Byte0]: 48

 7845 16:51:06.223738                           [Byte1]: 48

 7846 16:51:06.228142  

 7847 16:51:06.228246  Set Vref, RX VrefLevel [Byte0]: 49

 7848 16:51:06.231182                           [Byte1]: 49

 7849 16:51:06.235754  

 7850 16:51:06.235871  Set Vref, RX VrefLevel [Byte0]: 50

 7851 16:51:06.238815                           [Byte1]: 50

 7852 16:51:06.243098  

 7853 16:51:06.243199  Set Vref, RX VrefLevel [Byte0]: 51

 7854 16:51:06.246307                           [Byte1]: 51

 7855 16:51:06.250850  

 7856 16:51:06.250927  Set Vref, RX VrefLevel [Byte0]: 52

 7857 16:51:06.254047                           [Byte1]: 52

 7858 16:51:06.258267  

 7859 16:51:06.258412  Set Vref, RX VrefLevel [Byte0]: 53

 7860 16:51:06.261813                           [Byte1]: 53

 7861 16:51:06.266009  

 7862 16:51:06.266107  Set Vref, RX VrefLevel [Byte0]: 54

 7863 16:51:06.269311                           [Byte1]: 54

 7864 16:51:06.273732  

 7865 16:51:06.273829  Set Vref, RX VrefLevel [Byte0]: 55

 7866 16:51:06.276932                           [Byte1]: 55

 7867 16:51:06.280834  

 7868 16:51:06.284546  Set Vref, RX VrefLevel [Byte0]: 56

 7869 16:51:06.287526                           [Byte1]: 56

 7870 16:51:06.287599  

 7871 16:51:06.291033  Set Vref, RX VrefLevel [Byte0]: 57

 7872 16:51:06.294458                           [Byte1]: 57

 7873 16:51:06.294554  

 7874 16:51:06.297732  Set Vref, RX VrefLevel [Byte0]: 58

 7875 16:51:06.300871                           [Byte1]: 58

 7876 16:51:06.300944  

 7877 16:51:06.304043  Set Vref, RX VrefLevel [Byte0]: 59

 7878 16:51:06.307258                           [Byte1]: 59

 7879 16:51:06.311267  

 7880 16:51:06.311365  Set Vref, RX VrefLevel [Byte0]: 60

 7881 16:51:06.314783                           [Byte1]: 60

 7882 16:51:06.318839  

 7883 16:51:06.318912  Set Vref, RX VrefLevel [Byte0]: 61

 7884 16:51:06.322703                           [Byte1]: 61

 7885 16:51:06.326646  

 7886 16:51:06.326730  Set Vref, RX VrefLevel [Byte0]: 62

 7887 16:51:06.329986                           [Byte1]: 62

 7888 16:51:06.334298  

 7889 16:51:06.334433  Set Vref, RX VrefLevel [Byte0]: 63

 7890 16:51:06.337298                           [Byte1]: 63

 7891 16:51:06.341507  

 7892 16:51:06.341582  Set Vref, RX VrefLevel [Byte0]: 64

 7893 16:51:06.345023                           [Byte1]: 64

 7894 16:51:06.349593  

 7895 16:51:06.349697  Set Vref, RX VrefLevel [Byte0]: 65

 7896 16:51:06.352737                           [Byte1]: 65

 7897 16:51:06.357016  

 7898 16:51:06.357120  Set Vref, RX VrefLevel [Byte0]: 66

 7899 16:51:06.360138                           [Byte1]: 66

 7900 16:51:06.364260  

 7901 16:51:06.364359  Set Vref, RX VrefLevel [Byte0]: 67

 7902 16:51:06.367468                           [Byte1]: 67

 7903 16:51:06.371790  

 7904 16:51:06.371861  Set Vref, RX VrefLevel [Byte0]: 68

 7905 16:51:06.375353                           [Byte1]: 68

 7906 16:51:06.379851  

 7907 16:51:06.379947  Set Vref, RX VrefLevel [Byte0]: 69

 7908 16:51:06.383002                           [Byte1]: 69

 7909 16:51:06.387074  

 7910 16:51:06.387169  Set Vref, RX VrefLevel [Byte0]: 70

 7911 16:51:06.390444                           [Byte1]: 70

 7912 16:51:06.394779  

 7913 16:51:06.394878  Set Vref, RX VrefLevel [Byte0]: 71

 7914 16:51:06.397852                           [Byte1]: 71

 7915 16:51:06.402229  

 7916 16:51:06.402328  Set Vref, RX VrefLevel [Byte0]: 72

 7917 16:51:06.405943                           [Byte1]: 72

 7918 16:51:06.410171  

 7919 16:51:06.410274  Set Vref, RX VrefLevel [Byte0]: 73

 7920 16:51:06.416193                           [Byte1]: 73

 7921 16:51:06.416297  

 7922 16:51:06.419313  Set Vref, RX VrefLevel [Byte0]: 74

 7923 16:51:06.422927                           [Byte1]: 74

 7924 16:51:06.423023  

 7925 16:51:06.426108  Set Vref, RX VrefLevel [Byte0]: 75

 7926 16:51:06.429504                           [Byte1]: 75

 7927 16:51:06.429594  

 7928 16:51:06.432906  Set Vref, RX VrefLevel [Byte0]: 76

 7929 16:51:06.436092                           [Byte1]: 76

 7930 16:51:06.440277  

 7931 16:51:06.440350  Set Vref, RX VrefLevel [Byte0]: 77

 7932 16:51:06.443488                           [Byte1]: 77

 7933 16:51:06.447713  

 7934 16:51:06.447815  Set Vref, RX VrefLevel [Byte0]: 78

 7935 16:51:06.451308                           [Byte1]: 78

 7936 16:51:06.455100  

 7937 16:51:06.455206  Set Vref, RX VrefLevel [Byte0]: 79

 7938 16:51:06.458614                           [Byte1]: 79

 7939 16:51:06.462962  

 7940 16:51:06.463042  Final RX Vref Byte 0 = 62 to rank0

 7941 16:51:06.466246  Final RX Vref Byte 1 = 62 to rank0

 7942 16:51:06.469374  Final RX Vref Byte 0 = 62 to rank1

 7943 16:51:06.472776  Final RX Vref Byte 1 = 62 to rank1==

 7944 16:51:06.475891  Dram Type= 6, Freq= 0, CH_0, rank 0

 7945 16:51:06.482499  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7946 16:51:06.482578  ==

 7947 16:51:06.482642  DQS Delay:

 7948 16:51:06.485909  DQS0 = 0, DQS1 = 0

 7949 16:51:06.486005  DQM Delay:

 7950 16:51:06.486094  DQM0 = 137, DQM1 = 124

 7951 16:51:06.489326  DQ Delay:

 7952 16:51:06.492724  DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134

 7953 16:51:06.495952  DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144

 7954 16:51:06.499185  DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118

 7955 16:51:06.502250  DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134

 7956 16:51:06.502348  

 7957 16:51:06.502424  

 7958 16:51:06.502485  

 7959 16:51:06.505614  [DramC_TX_OE_Calibration] TA2

 7960 16:51:06.508907  Original DQ_B0 (3 6) =30, OEN = 27

 7961 16:51:06.512579  Original DQ_B1 (3 6) =30, OEN = 27

 7962 16:51:06.515597  24, 0x0, End_B0=24 End_B1=24

 7963 16:51:06.518628  25, 0x0, End_B0=25 End_B1=25

 7964 16:51:06.518703  26, 0x0, End_B0=26 End_B1=26

 7965 16:51:06.522211  27, 0x0, End_B0=27 End_B1=27

 7966 16:51:06.525568  28, 0x0, End_B0=28 End_B1=28

 7967 16:51:06.528805  29, 0x0, End_B0=29 End_B1=29

 7968 16:51:06.528922  30, 0x0, End_B0=30 End_B1=30

 7969 16:51:06.531882  31, 0x5151, End_B0=30 End_B1=30

 7970 16:51:06.535324  Byte0 end_step=30  best_step=27

 7971 16:51:06.538697  Byte1 end_step=30  best_step=27

 7972 16:51:06.541866  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7973 16:51:06.545197  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7974 16:51:06.545298  

 7975 16:51:06.545389  

 7976 16:51:06.552265  [DQSOSCAuto] RK0, (LSB)MR18= 0x1a18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps

 7977 16:51:06.555421  CH0 RK0: MR19=303, MR18=1A18

 7978 16:51:06.561952  CH0_RK0: MR19=0x303, MR18=0x1A18, DQSOSC=396, MR23=63, INC=23, DEC=15

 7979 16:51:06.562032  

 7980 16:51:06.565423  ----->DramcWriteLeveling(PI) begin...

 7981 16:51:06.565533  ==

 7982 16:51:06.568538  Dram Type= 6, Freq= 0, CH_0, rank 1

 7983 16:51:06.571960  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7984 16:51:06.572061  ==

 7985 16:51:06.574977  Write leveling (Byte 0): 39 => 39

 7986 16:51:06.578310  Write leveling (Byte 1): 29 => 29

 7987 16:51:06.581621  DramcWriteLeveling(PI) end<-----

 7988 16:51:06.581697  

 7989 16:51:06.581759  ==

 7990 16:51:06.584929  Dram Type= 6, Freq= 0, CH_0, rank 1

 7991 16:51:06.588527  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7992 16:51:06.591619  ==

 7993 16:51:06.591703  [Gating] SW mode calibration

 7994 16:51:06.601767  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7995 16:51:06.604604  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7996 16:51:06.607988   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7997 16:51:06.614132   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7998 16:51:06.617828   1  4  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7999 16:51:06.620844   1  4 12 | B1->B0 | 2525 3231 | 0 1 | (0 0) (1 1)

 8000 16:51:06.627765   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8001 16:51:06.630917   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8002 16:51:06.633931   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8003 16:51:06.640837   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8004 16:51:06.644010   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8005 16:51:06.647244   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8006 16:51:06.654192   1  5  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 8007 16:51:06.657605   1  5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)

 8008 16:51:06.660661   1  5 16 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)

 8009 16:51:06.667025   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8010 16:51:06.670386   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8011 16:51:06.673761   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8012 16:51:06.680534   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8013 16:51:06.683556   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8014 16:51:06.687169   1  6  8 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)

 8015 16:51:06.693332   1  6 12 | B1->B0 | 2929 4242 | 0 0 | (0 0) (0 0)

 8016 16:51:06.696871   1  6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 8017 16:51:06.700034   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8018 16:51:06.706789   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8019 16:51:06.710248   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8020 16:51:06.713362   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8021 16:51:06.720049   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8022 16:51:06.723691   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8023 16:51:06.727001   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8024 16:51:06.733457   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8025 16:51:06.736596   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8026 16:51:06.740188   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8027 16:51:06.746467   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8028 16:51:06.749532   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8029 16:51:06.753205   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8030 16:51:06.759913   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8031 16:51:06.763022   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8032 16:51:06.766236   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8033 16:51:06.772790   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8034 16:51:06.776129   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8035 16:51:06.779286   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8036 16:51:06.785963   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8037 16:51:06.789656   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8038 16:51:06.792760   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8039 16:51:06.799060   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8040 16:51:06.802615   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8041 16:51:06.805647  Total UI for P1: 0, mck2ui 16

 8042 16:51:06.809152  best dqsien dly found for B0: ( 1,  9, 10)

 8043 16:51:06.812324   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8044 16:51:06.815559  Total UI for P1: 0, mck2ui 16

 8045 16:51:06.819165  best dqsien dly found for B1: ( 1,  9, 14)

 8046 16:51:06.822505  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8047 16:51:06.825718  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8048 16:51:06.825833  

 8049 16:51:06.832483  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8050 16:51:06.835807  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8051 16:51:06.838842  [Gating] SW calibration Done

 8052 16:51:06.838925  ==

 8053 16:51:06.842337  Dram Type= 6, Freq= 0, CH_0, rank 1

 8054 16:51:06.845882  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8055 16:51:06.845966  ==

 8056 16:51:06.846032  RX Vref Scan: 0

 8057 16:51:06.848880  

 8058 16:51:06.848963  RX Vref 0 -> 0, step: 1

 8059 16:51:06.849029  

 8060 16:51:06.852354  RX Delay 0 -> 252, step: 8

 8061 16:51:06.855529  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8062 16:51:06.859190  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 8063 16:51:06.865759  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8064 16:51:06.868872  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 8065 16:51:06.872283  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8066 16:51:06.875219  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8067 16:51:06.878786  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8068 16:51:06.885289  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8069 16:51:06.888639  iDelay=200, Bit 8, Center 115 (64 ~ 167) 104

 8070 16:51:06.891657  iDelay=200, Bit 9, Center 111 (56 ~ 167) 112

 8071 16:51:06.895530  iDelay=200, Bit 10, Center 123 (72 ~ 175) 104

 8072 16:51:06.898535  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 8073 16:51:06.905024  iDelay=200, Bit 12, Center 127 (72 ~ 183) 112

 8074 16:51:06.908611  iDelay=200, Bit 13, Center 131 (80 ~ 183) 104

 8075 16:51:06.911719  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8076 16:51:06.915024  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8077 16:51:06.915113  ==

 8078 16:51:06.918220  Dram Type= 6, Freq= 0, CH_0, rank 1

 8079 16:51:06.924887  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8080 16:51:06.924964  ==

 8081 16:51:06.925028  DQS Delay:

 8082 16:51:06.928278  DQS0 = 0, DQS1 = 0

 8083 16:51:06.928387  DQM Delay:

 8084 16:51:06.928482  DQM0 = 136, DQM1 = 125

 8085 16:51:06.931662  DQ Delay:

 8086 16:51:06.934722  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131

 8087 16:51:06.938283  DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143

 8088 16:51:06.941388  DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123

 8089 16:51:06.944776  DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135

 8090 16:51:06.944861  

 8091 16:51:06.944927  

 8092 16:51:06.944988  ==

 8093 16:51:06.948135  Dram Type= 6, Freq= 0, CH_0, rank 1

 8094 16:51:06.954830  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8095 16:51:06.954923  ==

 8096 16:51:06.954991  

 8097 16:51:06.955061  

 8098 16:51:06.955120  	TX Vref Scan disable

 8099 16:51:06.958005   == TX Byte 0 ==

 8100 16:51:06.961421  Update DQ  dly =995 (3 ,6, 35)  DQ  OEN =(3 ,3)

 8101 16:51:06.968210  Update DQM dly =995 (3 ,6, 35)  DQM OEN =(3 ,3)

 8102 16:51:06.968288   == TX Byte 1 ==

 8103 16:51:06.971202  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8104 16:51:06.978162  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8105 16:51:06.978246  ==

 8106 16:51:06.981075  Dram Type= 6, Freq= 0, CH_0, rank 1

 8107 16:51:06.984306  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8108 16:51:06.984382  ==

 8109 16:51:06.999456  

 8110 16:51:07.002895  TX Vref early break, caculate TX vref

 8111 16:51:07.005995  TX Vref=16, minBit 0, minWin=23, winSum=387

 8112 16:51:07.009354  TX Vref=18, minBit 0, minWin=24, winSum=399

 8113 16:51:07.012362  TX Vref=20, minBit 2, minWin=24, winSum=405

 8114 16:51:07.016059  TX Vref=22, minBit 8, minWin=24, winSum=412

 8115 16:51:07.019475  TX Vref=24, minBit 0, minWin=25, winSum=421

 8116 16:51:07.025630  TX Vref=26, minBit 0, minWin=25, winSum=429

 8117 16:51:07.029089  TX Vref=28, minBit 0, minWin=26, winSum=430

 8118 16:51:07.032304  TX Vref=30, minBit 2, minWin=26, winSum=430

 8119 16:51:07.036012  TX Vref=32, minBit 8, minWin=25, winSum=422

 8120 16:51:07.039212  TX Vref=34, minBit 0, minWin=25, winSum=415

 8121 16:51:07.042439  TX Vref=36, minBit 2, minWin=24, winSum=402

 8122 16:51:07.049088  [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28

 8123 16:51:07.049169  

 8124 16:51:07.052283  Final TX Range 0 Vref 28

 8125 16:51:07.052357  

 8126 16:51:07.052428  ==

 8127 16:51:07.055804  Dram Type= 6, Freq= 0, CH_0, rank 1

 8128 16:51:07.058967  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8129 16:51:07.059052  ==

 8130 16:51:07.062064  

 8131 16:51:07.062141  

 8132 16:51:07.062204  	TX Vref Scan disable

 8133 16:51:07.068701  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8134 16:51:07.068787   == TX Byte 0 ==

 8135 16:51:07.071809  u2DelayCellOfst[0]=13 cells (4 PI)

 8136 16:51:07.075214  u2DelayCellOfst[1]=20 cells (6 PI)

 8137 16:51:07.078315  u2DelayCellOfst[2]=13 cells (4 PI)

 8138 16:51:07.081598  u2DelayCellOfst[3]=13 cells (4 PI)

 8139 16:51:07.085006  u2DelayCellOfst[4]=10 cells (3 PI)

 8140 16:51:07.088134  u2DelayCellOfst[5]=0 cells (0 PI)

 8141 16:51:07.091833  u2DelayCellOfst[6]=20 cells (6 PI)

 8142 16:51:07.095302  u2DelayCellOfst[7]=16 cells (5 PI)

 8143 16:51:07.098294  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 8144 16:51:07.101650  Update DQM dly =995 (3 ,6, 35)  DQM OEN =(3 ,3)

 8145 16:51:07.104700   == TX Byte 1 ==

 8146 16:51:07.108051  u2DelayCellOfst[8]=0 cells (0 PI)

 8147 16:51:07.111412  u2DelayCellOfst[9]=0 cells (0 PI)

 8148 16:51:07.114897  u2DelayCellOfst[10]=6 cells (2 PI)

 8149 16:51:07.118014  u2DelayCellOfst[11]=0 cells (0 PI)

 8150 16:51:07.121230  u2DelayCellOfst[12]=10 cells (3 PI)

 8151 16:51:07.124713  u2DelayCellOfst[13]=10 cells (3 PI)

 8152 16:51:07.127818  u2DelayCellOfst[14]=13 cells (4 PI)

 8153 16:51:07.127902  u2DelayCellOfst[15]=6 cells (2 PI)

 8154 16:51:07.134744  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8155 16:51:07.137883  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8156 16:51:07.141234  DramC Write-DBI on

 8157 16:51:07.141316  ==

 8158 16:51:07.144528  Dram Type= 6, Freq= 0, CH_0, rank 1

 8159 16:51:07.148072  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8160 16:51:07.148154  ==

 8161 16:51:07.148220  

 8162 16:51:07.148280  

 8163 16:51:07.151422  	TX Vref Scan disable

 8164 16:51:07.151504   == TX Byte 0 ==

 8165 16:51:07.157941  Update DQM dly =738 (2 ,6, 34)  DQM OEN =(3 ,3)

 8166 16:51:07.158024   == TX Byte 1 ==

 8167 16:51:07.161337  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 8168 16:51:07.164788  DramC Write-DBI off

 8169 16:51:07.164870  

 8170 16:51:07.164934  [DATLAT]

 8171 16:51:07.167885  Freq=1600, CH0 RK1

 8172 16:51:07.167967  

 8173 16:51:07.168032  DATLAT Default: 0xf

 8174 16:51:07.170848  0, 0xFFFF, sum = 0

 8175 16:51:07.170931  1, 0xFFFF, sum = 0

 8176 16:51:07.174736  2, 0xFFFF, sum = 0

 8177 16:51:07.177771  3, 0xFFFF, sum = 0

 8178 16:51:07.177854  4, 0xFFFF, sum = 0

 8179 16:51:07.180929  5, 0xFFFF, sum = 0

 8180 16:51:07.181017  6, 0xFFFF, sum = 0

 8181 16:51:07.184304  7, 0xFFFF, sum = 0

 8182 16:51:07.184388  8, 0xFFFF, sum = 0

 8183 16:51:07.187908  9, 0xFFFF, sum = 0

 8184 16:51:07.187991  10, 0xFFFF, sum = 0

 8185 16:51:07.190542  11, 0xFFFF, sum = 0

 8186 16:51:07.190626  12, 0xFFFF, sum = 0

 8187 16:51:07.193892  13, 0xFFFF, sum = 0

 8188 16:51:07.193976  14, 0x0, sum = 1

 8189 16:51:07.197367  15, 0x0, sum = 2

 8190 16:51:07.197449  16, 0x0, sum = 3

 8191 16:51:07.201067  17, 0x0, sum = 4

 8192 16:51:07.201177  best_step = 15

 8193 16:51:07.201245  

 8194 16:51:07.201307  ==

 8195 16:51:07.203878  Dram Type= 6, Freq= 0, CH_0, rank 1

 8196 16:51:07.210520  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8197 16:51:07.210604  ==

 8198 16:51:07.210670  RX Vref Scan: 0

 8199 16:51:07.210731  

 8200 16:51:07.213877  RX Vref 0 -> 0, step: 1

 8201 16:51:07.213960  

 8202 16:51:07.216969  RX Delay 11 -> 252, step: 4

 8203 16:51:07.220512  iDelay=191, Bit 0, Center 132 (83 ~ 182) 100

 8204 16:51:07.223864  iDelay=191, Bit 1, Center 136 (87 ~ 186) 100

 8205 16:51:07.227412  iDelay=191, Bit 2, Center 130 (79 ~ 182) 104

 8206 16:51:07.233652  iDelay=191, Bit 3, Center 130 (83 ~ 178) 96

 8207 16:51:07.237026  iDelay=191, Bit 4, Center 134 (87 ~ 182) 96

 8208 16:51:07.240120  iDelay=191, Bit 5, Center 124 (75 ~ 174) 100

 8209 16:51:07.243728  iDelay=191, Bit 6, Center 140 (91 ~ 190) 100

 8210 16:51:07.246891  iDelay=191, Bit 7, Center 138 (87 ~ 190) 104

 8211 16:51:07.253434  iDelay=191, Bit 8, Center 116 (67 ~ 166) 100

 8212 16:51:07.256794  iDelay=191, Bit 9, Center 110 (59 ~ 162) 104

 8213 16:51:07.259896  iDelay=191, Bit 10, Center 126 (79 ~ 174) 96

 8214 16:51:07.263266  iDelay=191, Bit 11, Center 120 (71 ~ 170) 100

 8215 16:51:07.266512  iDelay=191, Bit 12, Center 128 (75 ~ 182) 108

 8216 16:51:07.273347  iDelay=191, Bit 13, Center 128 (79 ~ 178) 100

 8217 16:51:07.276567  iDelay=191, Bit 14, Center 132 (79 ~ 186) 108

 8218 16:51:07.279691  iDelay=191, Bit 15, Center 130 (79 ~ 182) 104

 8219 16:51:07.279793  ==

 8220 16:51:07.283360  Dram Type= 6, Freq= 0, CH_0, rank 1

 8221 16:51:07.286285  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8222 16:51:07.289934  ==

 8223 16:51:07.290036  DQS Delay:

 8224 16:51:07.290130  DQS0 = 0, DQS1 = 0

 8225 16:51:07.293011  DQM Delay:

 8226 16:51:07.293113  DQM0 = 133, DQM1 = 123

 8227 16:51:07.296187  DQ Delay:

 8228 16:51:07.299566  DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130

 8229 16:51:07.303162  DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138

 8230 16:51:07.306873  DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120

 8231 16:51:07.309600  DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130

 8232 16:51:07.309675  

 8233 16:51:07.309741  

 8234 16:51:07.309800  

 8235 16:51:07.312752  [DramC_TX_OE_Calibration] TA2

 8236 16:51:07.316153  Original DQ_B0 (3 6) =30, OEN = 27

 8237 16:51:07.319377  Original DQ_B1 (3 6) =30, OEN = 27

 8238 16:51:07.322994  24, 0x0, End_B0=24 End_B1=24

 8239 16:51:07.323112  25, 0x0, End_B0=25 End_B1=25

 8240 16:51:07.326146  26, 0x0, End_B0=26 End_B1=26

 8241 16:51:07.329386  27, 0x0, End_B0=27 End_B1=27

 8242 16:51:07.332715  28, 0x0, End_B0=28 End_B1=28

 8243 16:51:07.336037  29, 0x0, End_B0=29 End_B1=29

 8244 16:51:07.336116  30, 0x0, End_B0=30 End_B1=30

 8245 16:51:07.339187  31, 0x4141, End_B0=30 End_B1=30

 8246 16:51:07.342852  Byte0 end_step=30  best_step=27

 8247 16:51:07.346244  Byte1 end_step=30  best_step=27

 8248 16:51:07.349113  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8249 16:51:07.352346  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8250 16:51:07.352448  

 8251 16:51:07.352542  

 8252 16:51:07.359087  [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps

 8253 16:51:07.362557  CH0 RK1: MR19=303, MR18=1E0B

 8254 16:51:07.369110  CH0_RK1: MR19=0x303, MR18=0x1E0B, DQSOSC=394, MR23=63, INC=23, DEC=15

 8255 16:51:07.372099  [RxdqsGatingPostProcess] freq 1600

 8256 16:51:07.375689  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8257 16:51:07.379041  best DQS0 dly(2T, 0.5T) = (1, 1)

 8258 16:51:07.382368  best DQS1 dly(2T, 0.5T) = (1, 1)

 8259 16:51:07.385440  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8260 16:51:07.389149  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8261 16:51:07.392318  best DQS0 dly(2T, 0.5T) = (1, 1)

 8262 16:51:07.395430  best DQS1 dly(2T, 0.5T) = (1, 1)

 8263 16:51:07.398752  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8264 16:51:07.402551  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8265 16:51:07.405478  Pre-setting of DQS Precalculation

 8266 16:51:07.408880  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8267 16:51:07.408958  ==

 8268 16:51:07.412039  Dram Type= 6, Freq= 0, CH_1, rank 0

 8269 16:51:07.415467  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8270 16:51:07.418499  ==

 8271 16:51:07.421777  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8272 16:51:07.425084  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8273 16:51:07.431614  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8274 16:51:07.438069  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8275 16:51:07.445565  [CA 0] Center 40 (11~70) winsize 60

 8276 16:51:07.449118  [CA 1] Center 41 (11~71) winsize 61

 8277 16:51:07.452336  [CA 2] Center 37 (8~67) winsize 60

 8278 16:51:07.455477  [CA 3] Center 36 (7~66) winsize 60

 8279 16:51:07.458715  [CA 4] Center 37 (7~67) winsize 61

 8280 16:51:07.462265  [CA 5] Center 36 (6~66) winsize 61

 8281 16:51:07.462406  

 8282 16:51:07.465907  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8283 16:51:07.466007  

 8284 16:51:07.468801  [CATrainingPosCal] consider 1 rank data

 8285 16:51:07.471910  u2DelayCellTimex100 = 290/100 ps

 8286 16:51:07.478815  CA0 delay=40 (11~70),Diff = 4 PI (13 cell)

 8287 16:51:07.482211  CA1 delay=41 (11~71),Diff = 5 PI (16 cell)

 8288 16:51:07.485304  CA2 delay=37 (8~67),Diff = 1 PI (3 cell)

 8289 16:51:07.488532  CA3 delay=36 (7~66),Diff = 0 PI (0 cell)

 8290 16:51:07.492019  CA4 delay=37 (7~67),Diff = 1 PI (3 cell)

 8291 16:51:07.495414  CA5 delay=36 (6~66),Diff = 0 PI (0 cell)

 8292 16:51:07.495527  

 8293 16:51:07.498294  CA PerBit enable=1, Macro0, CA PI delay=36

 8294 16:51:07.498414  

 8295 16:51:07.501870  [CBTSetCACLKResult] CA Dly = 36

 8296 16:51:07.505040  CS Dly: 8 (0~39)

 8297 16:51:07.508068  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8298 16:51:07.511560  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8299 16:51:07.511642  ==

 8300 16:51:07.514974  Dram Type= 6, Freq= 0, CH_1, rank 1

 8301 16:51:07.521576  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8302 16:51:07.521658  ==

 8303 16:51:07.524792  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8304 16:51:07.531319  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8305 16:51:07.535123  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8306 16:51:07.541250  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8307 16:51:07.548594  [CA 0] Center 41 (12~71) winsize 60

 8308 16:51:07.552349  [CA 1] Center 41 (12~71) winsize 60

 8309 16:51:07.555353  [CA 2] Center 38 (8~68) winsize 61

 8310 16:51:07.558840  [CA 3] Center 37 (8~67) winsize 60

 8311 16:51:07.562234  [CA 4] Center 37 (8~67) winsize 60

 8312 16:51:07.565563  [CA 5] Center 37 (7~67) winsize 61

 8313 16:51:07.565645  

 8314 16:51:07.568614  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8315 16:51:07.568694  

 8316 16:51:07.571969  [CATrainingPosCal] consider 2 rank data

 8317 16:51:07.575588  u2DelayCellTimex100 = 290/100 ps

 8318 16:51:07.581751  CA0 delay=41 (12~70),Diff = 5 PI (16 cell)

 8319 16:51:07.585209  CA1 delay=41 (12~71),Diff = 5 PI (16 cell)

 8320 16:51:07.588405  CA2 delay=37 (8~67),Diff = 1 PI (3 cell)

 8321 16:51:07.591688  CA3 delay=37 (8~66),Diff = 1 PI (3 cell)

 8322 16:51:07.594875  CA4 delay=37 (8~67),Diff = 1 PI (3 cell)

 8323 16:51:07.598517  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8324 16:51:07.598597  

 8325 16:51:07.601366  CA PerBit enable=1, Macro0, CA PI delay=36

 8326 16:51:07.601446  

 8327 16:51:07.604847  [CBTSetCACLKResult] CA Dly = 36

 8328 16:51:07.608234  CS Dly: 9 (0~42)

 8329 16:51:07.611355  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8330 16:51:07.614874  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8331 16:51:07.614954  

 8332 16:51:07.618281  ----->DramcWriteLeveling(PI) begin...

 8333 16:51:07.618386  ==

 8334 16:51:07.621209  Dram Type= 6, Freq= 0, CH_1, rank 0

 8335 16:51:07.628079  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8336 16:51:07.628165  ==

 8337 16:51:07.631103  Write leveling (Byte 0): 24 => 24

 8338 16:51:07.634860  Write leveling (Byte 1): 28 => 28

 8339 16:51:07.634940  DramcWriteLeveling(PI) end<-----

 8340 16:51:07.635003  

 8341 16:51:07.638496  ==

 8342 16:51:07.641493  Dram Type= 6, Freq= 0, CH_1, rank 0

 8343 16:51:07.644394  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8344 16:51:07.644475  ==

 8345 16:51:07.647799  [Gating] SW mode calibration

 8346 16:51:07.654333  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8347 16:51:07.657805  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8348 16:51:07.664301   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8349 16:51:07.667415   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8350 16:51:07.670835   1  4  8 | B1->B0 | 2e2e 2f2f | 0 1 | (0 0) (1 1)

 8351 16:51:07.678025   1  4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8352 16:51:07.680782   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8353 16:51:07.684110   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8354 16:51:07.690834   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8355 16:51:07.694233   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8356 16:51:07.697432   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8357 16:51:07.703911   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8358 16:51:07.707416   1  5  8 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (1 0)

 8359 16:51:07.710685   1  5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8360 16:51:07.717276   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8361 16:51:07.720554   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8362 16:51:07.724211   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8363 16:51:07.730929   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8364 16:51:07.733965   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8365 16:51:07.736965   1  6  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8366 16:51:07.743826   1  6  8 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)

 8367 16:51:07.747020   1  6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8368 16:51:07.750139   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8369 16:51:07.756681   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8370 16:51:07.760401   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8371 16:51:07.763448   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8372 16:51:07.769874   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8373 16:51:07.773582   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8374 16:51:07.776752   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8375 16:51:07.783327   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8376 16:51:07.786713   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8377 16:51:07.789704   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8378 16:51:07.796385   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8379 16:51:07.799968   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8380 16:51:07.802972   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8381 16:51:07.809628   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8382 16:51:07.813039   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8383 16:51:07.816386   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8384 16:51:07.823049   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8385 16:51:07.825949   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8386 16:51:07.829368   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8387 16:51:07.835912   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8388 16:51:07.839438   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8389 16:51:07.842493   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8390 16:51:07.849702   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8391 16:51:07.852516   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8392 16:51:07.855880  Total UI for P1: 0, mck2ui 16

 8393 16:51:07.859178  best dqsien dly found for B0: ( 1,  9,  6)

 8394 16:51:07.862951   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8395 16:51:07.866101  Total UI for P1: 0, mck2ui 16

 8396 16:51:07.869558  best dqsien dly found for B1: ( 1,  9, 10)

 8397 16:51:07.872452  best DQS0 dly(MCK, UI, PI) = (1, 9, 6)

 8398 16:51:07.875675  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8399 16:51:07.875760  

 8400 16:51:07.879562  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8401 16:51:07.885884  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8402 16:51:07.885994  [Gating] SW calibration Done

 8403 16:51:07.888861  ==

 8404 16:51:07.888946  Dram Type= 6, Freq= 0, CH_1, rank 0

 8405 16:51:07.895496  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8406 16:51:07.895583  ==

 8407 16:51:07.895669  RX Vref Scan: 0

 8408 16:51:07.895749  

 8409 16:51:07.898935  RX Vref 0 -> 0, step: 1

 8410 16:51:07.899019  

 8411 16:51:07.902483  RX Delay 0 -> 252, step: 8

 8412 16:51:07.905478  iDelay=200, Bit 0, Center 139 (96 ~ 183) 88

 8413 16:51:07.908629  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8414 16:51:07.912153  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8415 16:51:07.919262  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8416 16:51:07.922642  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 8417 16:51:07.925617  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8418 16:51:07.928857  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8419 16:51:07.932130  iDelay=200, Bit 7, Center 135 (88 ~ 183) 96

 8420 16:51:07.935287  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8421 16:51:07.942080  iDelay=200, Bit 9, Center 119 (72 ~ 167) 96

 8422 16:51:07.945338  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8423 16:51:07.948712  iDelay=200, Bit 11, Center 127 (80 ~ 175) 96

 8424 16:51:07.951870  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8425 16:51:07.958723  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8426 16:51:07.961961  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8427 16:51:07.965074  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8428 16:51:07.965160  ==

 8429 16:51:07.968413  Dram Type= 6, Freq= 0, CH_1, rank 0

 8430 16:51:07.971525  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8431 16:51:07.971610  ==

 8432 16:51:07.974888  DQS Delay:

 8433 16:51:07.974972  DQS0 = 0, DQS1 = 0

 8434 16:51:07.978296  DQM Delay:

 8435 16:51:07.978402  DQM0 = 136, DQM1 = 131

 8436 16:51:07.978487  DQ Delay:

 8437 16:51:07.984890  DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135

 8438 16:51:07.988335  DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135

 8439 16:51:07.991625  DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127

 8440 16:51:07.995171  DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139

 8441 16:51:07.995255  

 8442 16:51:07.995338  

 8443 16:51:07.995417  ==

 8444 16:51:07.998225  Dram Type= 6, Freq= 0, CH_1, rank 0

 8445 16:51:08.001633  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8446 16:51:08.001718  ==

 8447 16:51:08.001801  

 8448 16:51:08.001880  

 8449 16:51:08.004815  	TX Vref Scan disable

 8450 16:51:08.008398   == TX Byte 0 ==

 8451 16:51:08.011437  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8452 16:51:08.014916  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8453 16:51:08.017947   == TX Byte 1 ==

 8454 16:51:08.021163  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8455 16:51:08.024551  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8456 16:51:08.024635  ==

 8457 16:51:08.027977  Dram Type= 6, Freq= 0, CH_1, rank 0

 8458 16:51:08.034136  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8459 16:51:08.034222  ==

 8460 16:51:08.046033  

 8461 16:51:08.049028  TX Vref early break, caculate TX vref

 8462 16:51:08.052755  TX Vref=16, minBit 10, minWin=21, winSum=368

 8463 16:51:08.055759  TX Vref=18, minBit 9, minWin=22, winSum=379

 8464 16:51:08.059080  TX Vref=20, minBit 9, minWin=23, winSum=391

 8465 16:51:08.062267  TX Vref=22, minBit 10, minWin=23, winSum=399

 8466 16:51:08.069479  TX Vref=24, minBit 10, minWin=24, winSum=404

 8467 16:51:08.072146  TX Vref=26, minBit 15, minWin=24, winSum=417

 8468 16:51:08.075759  TX Vref=28, minBit 10, minWin=25, winSum=420

 8469 16:51:08.078833  TX Vref=30, minBit 13, minWin=24, winSum=417

 8470 16:51:08.082300  TX Vref=32, minBit 13, minWin=23, winSum=402

 8471 16:51:08.085521  TX Vref=34, minBit 9, minWin=23, winSum=398

 8472 16:51:08.091987  [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 28

 8473 16:51:08.092072  

 8474 16:51:08.095261  Final TX Range 0 Vref 28

 8475 16:51:08.095344  

 8476 16:51:08.095410  ==

 8477 16:51:08.098848  Dram Type= 6, Freq= 0, CH_1, rank 0

 8478 16:51:08.101944  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8479 16:51:08.105222  ==

 8480 16:51:08.105306  

 8481 16:51:08.105371  

 8482 16:51:08.105432  	TX Vref Scan disable

 8483 16:51:08.112013  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8484 16:51:08.112096   == TX Byte 0 ==

 8485 16:51:08.115496  u2DelayCellOfst[0]=16 cells (5 PI)

 8486 16:51:08.118554  u2DelayCellOfst[1]=10 cells (3 PI)

 8487 16:51:08.122087  u2DelayCellOfst[2]=0 cells (0 PI)

 8488 16:51:08.125459  u2DelayCellOfst[3]=3 cells (1 PI)

 8489 16:51:08.128684  u2DelayCellOfst[4]=6 cells (2 PI)

 8490 16:51:08.131851  u2DelayCellOfst[5]=16 cells (5 PI)

 8491 16:51:08.135091  u2DelayCellOfst[6]=16 cells (5 PI)

 8492 16:51:08.138101  u2DelayCellOfst[7]=6 cells (2 PI)

 8493 16:51:08.141555  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8494 16:51:08.145171  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8495 16:51:08.148170   == TX Byte 1 ==

 8496 16:51:08.151833  u2DelayCellOfst[8]=0 cells (0 PI)

 8497 16:51:08.155313  u2DelayCellOfst[9]=3 cells (1 PI)

 8498 16:51:08.158331  u2DelayCellOfst[10]=10 cells (3 PI)

 8499 16:51:08.161801  u2DelayCellOfst[11]=0 cells (0 PI)

 8500 16:51:08.164529  u2DelayCellOfst[12]=13 cells (4 PI)

 8501 16:51:08.167999  u2DelayCellOfst[13]=16 cells (5 PI)

 8502 16:51:08.171120  u2DelayCellOfst[14]=16 cells (5 PI)

 8503 16:51:08.171203  u2DelayCellOfst[15]=13 cells (4 PI)

 8504 16:51:08.177942  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8505 16:51:08.181541  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8506 16:51:08.184398  DramC Write-DBI on

 8507 16:51:08.184481  ==

 8508 16:51:08.187502  Dram Type= 6, Freq= 0, CH_1, rank 0

 8509 16:51:08.190975  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8510 16:51:08.191060  ==

 8511 16:51:08.191132  

 8512 16:51:08.191200  

 8513 16:51:08.194141  	TX Vref Scan disable

 8514 16:51:08.194223   == TX Byte 0 ==

 8515 16:51:08.200826  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8516 16:51:08.200910   == TX Byte 1 ==

 8517 16:51:08.204417  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8518 16:51:08.207802  DramC Write-DBI off

 8519 16:51:08.207884  

 8520 16:51:08.207948  [DATLAT]

 8521 16:51:08.210854  Freq=1600, CH1 RK0

 8522 16:51:08.210938  

 8523 16:51:08.211003  DATLAT Default: 0xf

 8524 16:51:08.214130  0, 0xFFFF, sum = 0

 8525 16:51:08.214215  1, 0xFFFF, sum = 0

 8526 16:51:08.217905  2, 0xFFFF, sum = 0

 8527 16:51:08.220693  3, 0xFFFF, sum = 0

 8528 16:51:08.220777  4, 0xFFFF, sum = 0

 8529 16:51:08.223686  5, 0xFFFF, sum = 0

 8530 16:51:08.223771  6, 0xFFFF, sum = 0

 8531 16:51:08.227354  7, 0xFFFF, sum = 0

 8532 16:51:08.227437  8, 0xFFFF, sum = 0

 8533 16:51:08.230454  9, 0xFFFF, sum = 0

 8534 16:51:08.230540  10, 0xFFFF, sum = 0

 8535 16:51:08.233601  11, 0xFFFF, sum = 0

 8536 16:51:08.233685  12, 0xFFFF, sum = 0

 8537 16:51:08.237108  13, 0xFFFF, sum = 0

 8538 16:51:08.237191  14, 0x0, sum = 1

 8539 16:51:08.240295  15, 0x0, sum = 2

 8540 16:51:08.240391  16, 0x0, sum = 3

 8541 16:51:08.243513  17, 0x0, sum = 4

 8542 16:51:08.243598  best_step = 15

 8543 16:51:08.243663  

 8544 16:51:08.243724  ==

 8545 16:51:08.246989  Dram Type= 6, Freq= 0, CH_1, rank 0

 8546 16:51:08.253595  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8547 16:51:08.253679  ==

 8548 16:51:08.253744  RX Vref Scan: 1

 8549 16:51:08.253806  

 8550 16:51:08.257188  Set Vref Range= 24 -> 127

 8551 16:51:08.257270  

 8552 16:51:08.260188  RX Vref 24 -> 127, step: 1

 8553 16:51:08.260270  

 8554 16:51:08.260336  RX Delay 19 -> 252, step: 4

 8555 16:51:08.260397  

 8556 16:51:08.263314  Set Vref, RX VrefLevel [Byte0]: 24

 8557 16:51:08.266833                           [Byte1]: 24

 8558 16:51:08.270888  

 8559 16:51:08.270971  Set Vref, RX VrefLevel [Byte0]: 25

 8560 16:51:08.274357                           [Byte1]: 25

 8561 16:51:08.278747  

 8562 16:51:08.278832  Set Vref, RX VrefLevel [Byte0]: 26

 8563 16:51:08.282176                           [Byte1]: 26

 8564 16:51:08.286272  

 8565 16:51:08.286359  Set Vref, RX VrefLevel [Byte0]: 27

 8566 16:51:08.289035                           [Byte1]: 27

 8567 16:51:08.293638  

 8568 16:51:08.293720  Set Vref, RX VrefLevel [Byte0]: 28

 8569 16:51:08.296990                           [Byte1]: 28

 8570 16:51:08.301255  

 8571 16:51:08.301338  Set Vref, RX VrefLevel [Byte0]: 29

 8572 16:51:08.304502                           [Byte1]: 29

 8573 16:51:08.308808  

 8574 16:51:08.308891  Set Vref, RX VrefLevel [Byte0]: 30

 8575 16:51:08.312017                           [Byte1]: 30

 8576 16:51:08.316346  

 8577 16:51:08.316428  Set Vref, RX VrefLevel [Byte0]: 31

 8578 16:51:08.319702                           [Byte1]: 31

 8579 16:51:08.323802  

 8580 16:51:08.323884  Set Vref, RX VrefLevel [Byte0]: 32

 8581 16:51:08.327318                           [Byte1]: 32

 8582 16:51:08.331401  

 8583 16:51:08.331484  Set Vref, RX VrefLevel [Byte0]: 33

 8584 16:51:08.334927                           [Byte1]: 33

 8585 16:51:08.338989  

 8586 16:51:08.339071  Set Vref, RX VrefLevel [Byte0]: 34

 8587 16:51:08.342151                           [Byte1]: 34

 8588 16:51:08.346552  

 8589 16:51:08.346634  Set Vref, RX VrefLevel [Byte0]: 35

 8590 16:51:08.350033                           [Byte1]: 35

 8591 16:51:08.354068  

 8592 16:51:08.354150  Set Vref, RX VrefLevel [Byte0]: 36

 8593 16:51:08.357510                           [Byte1]: 36

 8594 16:51:08.361902  

 8595 16:51:08.361985  Set Vref, RX VrefLevel [Byte0]: 37

 8596 16:51:08.364923                           [Byte1]: 37

 8597 16:51:08.369440  

 8598 16:51:08.369523  Set Vref, RX VrefLevel [Byte0]: 38

 8599 16:51:08.372586                           [Byte1]: 38

 8600 16:51:08.377094  

 8601 16:51:08.377177  Set Vref, RX VrefLevel [Byte0]: 39

 8602 16:51:08.380294                           [Byte1]: 39

 8603 16:51:08.384370  

 8604 16:51:08.384452  Set Vref, RX VrefLevel [Byte0]: 40

 8605 16:51:08.387785                           [Byte1]: 40

 8606 16:51:08.392871  

 8607 16:51:08.392953  Set Vref, RX VrefLevel [Byte0]: 41

 8608 16:51:08.395837                           [Byte1]: 41

 8609 16:51:08.399746  

 8610 16:51:08.399828  Set Vref, RX VrefLevel [Byte0]: 42

 8611 16:51:08.403221                           [Byte1]: 42

 8612 16:51:08.407766  

 8613 16:51:08.407849  Set Vref, RX VrefLevel [Byte0]: 43

 8614 16:51:08.410561                           [Byte1]: 43

 8615 16:51:08.414617  

 8616 16:51:08.414699  Set Vref, RX VrefLevel [Byte0]: 44

 8617 16:51:08.417939                           [Byte1]: 44

 8618 16:51:08.422319  

 8619 16:51:08.422422  Set Vref, RX VrefLevel [Byte0]: 45

 8620 16:51:08.425546                           [Byte1]: 45

 8621 16:51:08.429993  

 8622 16:51:08.430077  Set Vref, RX VrefLevel [Byte0]: 46

 8623 16:51:08.433231                           [Byte1]: 46

 8624 16:51:08.437478  

 8625 16:51:08.437560  Set Vref, RX VrefLevel [Byte0]: 47

 8626 16:51:08.440842                           [Byte1]: 47

 8627 16:51:08.445022  

 8628 16:51:08.445103  Set Vref, RX VrefLevel [Byte0]: 48

 8629 16:51:08.448349                           [Byte1]: 48

 8630 16:51:08.452916  

 8631 16:51:08.452997  Set Vref, RX VrefLevel [Byte0]: 49

 8632 16:51:08.455877                           [Byte1]: 49

 8633 16:51:08.460334  

 8634 16:51:08.460416  Set Vref, RX VrefLevel [Byte0]: 50

 8635 16:51:08.463404                           [Byte1]: 50

 8636 16:51:08.467699  

 8637 16:51:08.467781  Set Vref, RX VrefLevel [Byte0]: 51

 8638 16:51:08.471153                           [Byte1]: 51

 8639 16:51:08.475439  

 8640 16:51:08.475521  Set Vref, RX VrefLevel [Byte0]: 52

 8641 16:51:08.478768                           [Byte1]: 52

 8642 16:51:08.482863  

 8643 16:51:08.482945  Set Vref, RX VrefLevel [Byte0]: 53

 8644 16:51:08.486241                           [Byte1]: 53

 8645 16:51:08.490340  

 8646 16:51:08.490430  Set Vref, RX VrefLevel [Byte0]: 54

 8647 16:51:08.493626                           [Byte1]: 54

 8648 16:51:08.497839  

 8649 16:51:08.497921  Set Vref, RX VrefLevel [Byte0]: 55

 8650 16:51:08.501374                           [Byte1]: 55

 8651 16:51:08.505676  

 8652 16:51:08.505758  Set Vref, RX VrefLevel [Byte0]: 56

 8653 16:51:08.509211                           [Byte1]: 56

 8654 16:51:08.513404  

 8655 16:51:08.513486  Set Vref, RX VrefLevel [Byte0]: 57

 8656 16:51:08.516907                           [Byte1]: 57

 8657 16:51:08.520770  

 8658 16:51:08.520856  Set Vref, RX VrefLevel [Byte0]: 58

 8659 16:51:08.524264                           [Byte1]: 58

 8660 16:51:08.528277  

 8661 16:51:08.528359  Set Vref, RX VrefLevel [Byte0]: 59

 8662 16:51:08.531476                           [Byte1]: 59

 8663 16:51:08.535828  

 8664 16:51:08.535910  Set Vref, RX VrefLevel [Byte0]: 60

 8665 16:51:08.539256                           [Byte1]: 60

 8666 16:51:08.543291  

 8667 16:51:08.543372  Set Vref, RX VrefLevel [Byte0]: 61

 8668 16:51:08.546655                           [Byte1]: 61

 8669 16:51:08.551119  

 8670 16:51:08.551201  Set Vref, RX VrefLevel [Byte0]: 62

 8671 16:51:08.554462                           [Byte1]: 62

 8672 16:51:08.558422  

 8673 16:51:08.558504  Set Vref, RX VrefLevel [Byte0]: 63

 8674 16:51:08.561899                           [Byte1]: 63

 8675 16:51:08.566316  

 8676 16:51:08.566443  Set Vref, RX VrefLevel [Byte0]: 64

 8677 16:51:08.569455                           [Byte1]: 64

 8678 16:51:08.573960  

 8679 16:51:08.574069  Set Vref, RX VrefLevel [Byte0]: 65

 8680 16:51:08.577212                           [Byte1]: 65

 8681 16:51:08.581126  

 8682 16:51:08.581208  Set Vref, RX VrefLevel [Byte0]: 66

 8683 16:51:08.584586                           [Byte1]: 66

 8684 16:51:08.589053  

 8685 16:51:08.589136  Set Vref, RX VrefLevel [Byte0]: 67

 8686 16:51:08.592024                           [Byte1]: 67

 8687 16:51:08.596292  

 8688 16:51:08.596373  Set Vref, RX VrefLevel [Byte0]: 68

 8689 16:51:08.599507                           [Byte1]: 68

 8690 16:51:08.604411  

 8691 16:51:08.604494  Set Vref, RX VrefLevel [Byte0]: 69

 8692 16:51:08.607238                           [Byte1]: 69

 8693 16:51:08.612009  

 8694 16:51:08.612091  Set Vref, RX VrefLevel [Byte0]: 70

 8695 16:51:08.614745                           [Byte1]: 70

 8696 16:51:08.619170  

 8697 16:51:08.619252  Set Vref, RX VrefLevel [Byte0]: 71

 8698 16:51:08.622510                           [Byte1]: 71

 8699 16:51:08.626767  

 8700 16:51:08.626851  Set Vref, RX VrefLevel [Byte0]: 72

 8701 16:51:08.629868                           [Byte1]: 72

 8702 16:51:08.634399  

 8703 16:51:08.634482  Set Vref, RX VrefLevel [Byte0]: 73

 8704 16:51:08.637692                           [Byte1]: 73

 8705 16:51:08.641635  

 8706 16:51:08.641717  Set Vref, RX VrefLevel [Byte0]: 74

 8707 16:51:08.645303                           [Byte1]: 74

 8708 16:51:08.649480  

 8709 16:51:08.649562  Set Vref, RX VrefLevel [Byte0]: 75

 8710 16:51:08.652877                           [Byte1]: 75

 8711 16:51:08.657158  

 8712 16:51:08.657240  Final RX Vref Byte 0 = 54 to rank0

 8713 16:51:08.660101  Final RX Vref Byte 1 = 66 to rank0

 8714 16:51:08.663359  Final RX Vref Byte 0 = 54 to rank1

 8715 16:51:08.666894  Final RX Vref Byte 1 = 66 to rank1==

 8716 16:51:08.670018  Dram Type= 6, Freq= 0, CH_1, rank 0

 8717 16:51:08.676885  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8718 16:51:08.676969  ==

 8719 16:51:08.677036  DQS Delay:

 8720 16:51:08.680058  DQS0 = 0, DQS1 = 0

 8721 16:51:08.680141  DQM Delay:

 8722 16:51:08.680207  DQM0 = 133, DQM1 = 129

 8723 16:51:08.683554  DQ Delay:

 8724 16:51:08.686735  DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132

 8725 16:51:08.690014  DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130

 8726 16:51:08.693169  DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122

 8727 16:51:08.696705  DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136

 8728 16:51:08.696788  

 8729 16:51:08.696854  

 8730 16:51:08.696915  

 8731 16:51:08.699764  [DramC_TX_OE_Calibration] TA2

 8732 16:51:08.703579  Original DQ_B0 (3 6) =30, OEN = 27

 8733 16:51:08.706498  Original DQ_B1 (3 6) =30, OEN = 27

 8734 16:51:08.710007  24, 0x0, End_B0=24 End_B1=24

 8735 16:51:08.710091  25, 0x0, End_B0=25 End_B1=25

 8736 16:51:08.712952  26, 0x0, End_B0=26 End_B1=26

 8737 16:51:08.716727  27, 0x0, End_B0=27 End_B1=27

 8738 16:51:08.719766  28, 0x0, End_B0=28 End_B1=28

 8739 16:51:08.723203  29, 0x0, End_B0=29 End_B1=29

 8740 16:51:08.723288  30, 0x0, End_B0=30 End_B1=30

 8741 16:51:08.726223  31, 0x4141, End_B0=30 End_B1=30

 8742 16:51:08.729417  Byte0 end_step=30  best_step=27

 8743 16:51:08.732925  Byte1 end_step=30  best_step=27

 8744 16:51:08.736192  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8745 16:51:08.739350  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8746 16:51:08.739426  

 8747 16:51:08.739499  

 8748 16:51:08.746269  [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps

 8749 16:51:08.749423  CH1 RK0: MR19=303, MR18=1624

 8750 16:51:08.756410  CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16

 8751 16:51:08.756492  

 8752 16:51:08.759332  ----->DramcWriteLeveling(PI) begin...

 8753 16:51:08.759409  ==

 8754 16:51:08.762555  Dram Type= 6, Freq= 0, CH_1, rank 1

 8755 16:51:08.765893  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8756 16:51:08.765978  ==

 8757 16:51:08.769441  Write leveling (Byte 0): 23 => 23

 8758 16:51:08.772628  Write leveling (Byte 1): 28 => 28

 8759 16:51:08.775746  DramcWriteLeveling(PI) end<-----

 8760 16:51:08.775829  

 8761 16:51:08.775895  ==

 8762 16:51:08.778778  Dram Type= 6, Freq= 0, CH_1, rank 1

 8763 16:51:08.782117  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8764 16:51:08.785622  ==

 8765 16:51:08.785705  [Gating] SW mode calibration

 8766 16:51:08.795575  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8767 16:51:08.799186  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8768 16:51:08.802154   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8769 16:51:08.808885   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8770 16:51:08.812655   1  4  8 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)

 8771 16:51:08.815712   1  4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)

 8772 16:51:08.822140   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8773 16:51:08.825156   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8774 16:51:08.828309   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8775 16:51:08.835131   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8776 16:51:08.838706   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8777 16:51:08.842000   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8778 16:51:08.849074   1  5  8 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)

 8779 16:51:08.851656   1  5 12 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (0 1)

 8780 16:51:08.855020   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8781 16:51:08.862178   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8782 16:51:08.865176   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8783 16:51:08.868143   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8784 16:51:08.874947   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8785 16:51:08.878377   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8786 16:51:08.881746   1  6  8 | B1->B0 | 4040 2323 | 1 0 | (0 0) (0 0)

 8787 16:51:08.888239   1  6 12 | B1->B0 | 4646 3636 | 0 0 | (0 0) (0 0)

 8788 16:51:08.891355   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8789 16:51:08.894516   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8790 16:51:08.901319   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8791 16:51:08.904540   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8792 16:51:08.908070   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8793 16:51:08.914590   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8794 16:51:08.917628   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8795 16:51:08.921187   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8796 16:51:08.928007   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8797 16:51:08.930943   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8798 16:51:08.934653   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8799 16:51:08.940821   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8800 16:51:08.944420   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8801 16:51:08.947225   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8802 16:51:08.954592   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8803 16:51:08.957180   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8804 16:51:08.960548   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8805 16:51:08.967179   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8806 16:51:08.970172   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8807 16:51:08.973805   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8808 16:51:08.980494   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8809 16:51:08.984077   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8810 16:51:08.987074   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8811 16:51:08.993799   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8812 16:51:08.997210   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8813 16:51:09.000261  Total UI for P1: 0, mck2ui 16

 8814 16:51:09.003865  best dqsien dly found for B0: ( 1,  9, 10)

 8815 16:51:09.007169  Total UI for P1: 0, mck2ui 16

 8816 16:51:09.010568  best dqsien dly found for B1: ( 1,  9, 10)

 8817 16:51:09.014024  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8818 16:51:09.016958  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8819 16:51:09.017444  

 8820 16:51:09.020659  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8821 16:51:09.026823  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8822 16:51:09.027426  [Gating] SW calibration Done

 8823 16:51:09.027806  ==

 8824 16:51:09.030154  Dram Type= 6, Freq= 0, CH_1, rank 1

 8825 16:51:09.037018  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8826 16:51:09.037754  ==

 8827 16:51:09.038173  RX Vref Scan: 0

 8828 16:51:09.038593  

 8829 16:51:09.040201  RX Vref 0 -> 0, step: 1

 8830 16:51:09.040831  

 8831 16:51:09.043401  RX Delay 0 -> 252, step: 8

 8832 16:51:09.046861  iDelay=200, Bit 0, Center 143 (96 ~ 191) 96

 8833 16:51:09.050269  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8834 16:51:09.053092  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8835 16:51:09.056356  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8836 16:51:09.063168  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 8837 16:51:09.066138  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8838 16:51:09.069107  iDelay=200, Bit 6, Center 143 (96 ~ 191) 96

 8839 16:51:09.072826  iDelay=200, Bit 7, Center 135 (80 ~ 191) 112

 8840 16:51:09.076013  iDelay=200, Bit 8, Center 115 (64 ~ 167) 104

 8841 16:51:09.082402  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8842 16:51:09.086100  iDelay=200, Bit 10, Center 135 (80 ~ 191) 112

 8843 16:51:09.089093  iDelay=200, Bit 11, Center 127 (72 ~ 183) 112

 8844 16:51:09.092359  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8845 16:51:09.099429  iDelay=200, Bit 13, Center 143 (88 ~ 199) 112

 8846 16:51:09.102697  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8847 16:51:09.106319  iDelay=200, Bit 15, Center 143 (88 ~ 199) 112

 8848 16:51:09.106830  ==

 8849 16:51:09.109368  Dram Type= 6, Freq= 0, CH_1, rank 1

 8850 16:51:09.112674  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8851 16:51:09.113149  ==

 8852 16:51:09.116186  DQS Delay:

 8853 16:51:09.116649  DQS0 = 0, DQS1 = 0

 8854 16:51:09.119293  DQM Delay:

 8855 16:51:09.119760  DQM0 = 136, DQM1 = 132

 8856 16:51:09.120131  DQ Delay:

 8857 16:51:09.125831  DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135

 8858 16:51:09.129307  DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135

 8859 16:51:09.132811  DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127

 8860 16:51:09.135711  DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143

 8861 16:51:09.136181  

 8862 16:51:09.136550  

 8863 16:51:09.136893  ==

 8864 16:51:09.139044  Dram Type= 6, Freq= 0, CH_1, rank 1

 8865 16:51:09.142449  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8866 16:51:09.142923  ==

 8867 16:51:09.143293  

 8868 16:51:09.143634  

 8869 16:51:09.145501  	TX Vref Scan disable

 8870 16:51:09.149033   == TX Byte 0 ==

 8871 16:51:09.152552  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8872 16:51:09.155621  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8873 16:51:09.159109   == TX Byte 1 ==

 8874 16:51:09.162184  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8875 16:51:09.165260  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8876 16:51:09.165733  ==

 8877 16:51:09.168712  Dram Type= 6, Freq= 0, CH_1, rank 1

 8878 16:51:09.175299  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8879 16:51:09.175962  ==

 8880 16:51:09.187044  

 8881 16:51:09.190002  TX Vref early break, caculate TX vref

 8882 16:51:09.193434  TX Vref=16, minBit 10, minWin=22, winSum=380

 8883 16:51:09.196774  TX Vref=18, minBit 8, minWin=23, winSum=386

 8884 16:51:09.200176  TX Vref=20, minBit 9, minWin=23, winSum=396

 8885 16:51:09.203124  TX Vref=22, minBit 9, minWin=24, winSum=406

 8886 16:51:09.206691  TX Vref=24, minBit 9, minWin=24, winSum=414

 8887 16:51:09.213439  TX Vref=26, minBit 8, minWin=25, winSum=417

 8888 16:51:09.216709  TX Vref=28, minBit 13, minWin=25, winSum=426

 8889 16:51:09.220161  TX Vref=30, minBit 10, minWin=24, winSum=413

 8890 16:51:09.223263  TX Vref=32, minBit 9, minWin=24, winSum=405

 8891 16:51:09.226816  TX Vref=34, minBit 10, minWin=23, winSum=399

 8892 16:51:09.232877  [TxChooseVref] Worse bit 13, Min win 25, Win sum 426, Final Vref 28

 8893 16:51:09.233545  

 8894 16:51:09.236502  Final TX Range 0 Vref 28

 8895 16:51:09.236976  

 8896 16:51:09.237347  ==

 8897 16:51:09.239751  Dram Type= 6, Freq= 0, CH_1, rank 1

 8898 16:51:09.243143  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8899 16:51:09.243620  ==

 8900 16:51:09.246249  

 8901 16:51:09.246743  

 8902 16:51:09.247116  	TX Vref Scan disable

 8903 16:51:09.253041  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8904 16:51:09.253514   == TX Byte 0 ==

 8905 16:51:09.256657  u2DelayCellOfst[0]=16 cells (5 PI)

 8906 16:51:09.259554  u2DelayCellOfst[1]=10 cells (3 PI)

 8907 16:51:09.263805  u2DelayCellOfst[2]=0 cells (0 PI)

 8908 16:51:09.266438  u2DelayCellOfst[3]=3 cells (1 PI)

 8909 16:51:09.269199  u2DelayCellOfst[4]=6 cells (2 PI)

 8910 16:51:09.272645  u2DelayCellOfst[5]=16 cells (5 PI)

 8911 16:51:09.276140  u2DelayCellOfst[6]=16 cells (5 PI)

 8912 16:51:09.279663  u2DelayCellOfst[7]=3 cells (1 PI)

 8913 16:51:09.283496  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8914 16:51:09.285992  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8915 16:51:09.289648   == TX Byte 1 ==

 8916 16:51:09.293096  u2DelayCellOfst[8]=0 cells (0 PI)

 8917 16:51:09.296096  u2DelayCellOfst[9]=6 cells (2 PI)

 8918 16:51:09.299437  u2DelayCellOfst[10]=10 cells (3 PI)

 8919 16:51:09.299911  u2DelayCellOfst[11]=3 cells (1 PI)

 8920 16:51:09.303082  u2DelayCellOfst[12]=16 cells (5 PI)

 8921 16:51:09.305916  u2DelayCellOfst[13]=16 cells (5 PI)

 8922 16:51:09.308824  u2DelayCellOfst[14]=20 cells (6 PI)

 8923 16:51:09.312547  u2DelayCellOfst[15]=20 cells (6 PI)

 8924 16:51:09.318825  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8925 16:51:09.322594  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8926 16:51:09.323176  DramC Write-DBI on

 8927 16:51:09.325962  ==

 8928 16:51:09.328888  Dram Type= 6, Freq= 0, CH_1, rank 1

 8929 16:51:09.332299  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8930 16:51:09.332774  ==

 8931 16:51:09.333148  

 8932 16:51:09.333538  

 8933 16:51:09.335635  	TX Vref Scan disable

 8934 16:51:09.336212   == TX Byte 0 ==

 8935 16:51:09.341881  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8936 16:51:09.342387   == TX Byte 1 ==

 8937 16:51:09.345450  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8938 16:51:09.348766  DramC Write-DBI off

 8939 16:51:09.349345  

 8940 16:51:09.349720  [DATLAT]

 8941 16:51:09.352096  Freq=1600, CH1 RK1

 8942 16:51:09.352571  

 8943 16:51:09.352941  DATLAT Default: 0xf

 8944 16:51:09.355767  0, 0xFFFF, sum = 0

 8945 16:51:09.356355  1, 0xFFFF, sum = 0

 8946 16:51:09.358814  2, 0xFFFF, sum = 0

 8947 16:51:09.359295  3, 0xFFFF, sum = 0

 8948 16:51:09.362192  4, 0xFFFF, sum = 0

 8949 16:51:09.362694  5, 0xFFFF, sum = 0

 8950 16:51:09.365316  6, 0xFFFF, sum = 0

 8951 16:51:09.368471  7, 0xFFFF, sum = 0

 8952 16:51:09.368987  8, 0xFFFF, sum = 0

 8953 16:51:09.372278  9, 0xFFFF, sum = 0

 8954 16:51:09.372852  10, 0xFFFF, sum = 0

 8955 16:51:09.375210  11, 0xFFFF, sum = 0

 8956 16:51:09.375730  12, 0xFFFF, sum = 0

 8957 16:51:09.378550  13, 0xFFFF, sum = 0

 8958 16:51:09.379063  14, 0x0, sum = 1

 8959 16:51:09.381683  15, 0x0, sum = 2

 8960 16:51:09.382309  16, 0x0, sum = 3

 8961 16:51:09.384937  17, 0x0, sum = 4

 8962 16:51:09.385406  best_step = 15

 8963 16:51:09.385773  

 8964 16:51:09.386110  ==

 8965 16:51:09.388464  Dram Type= 6, Freq= 0, CH_1, rank 1

 8966 16:51:09.391748  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8967 16:51:09.394961  ==

 8968 16:51:09.395424  RX Vref Scan: 0

 8969 16:51:09.395792  

 8970 16:51:09.398586  RX Vref 0 -> 0, step: 1

 8971 16:51:09.399051  

 8972 16:51:09.402245  RX Delay 19 -> 252, step: 4

 8973 16:51:09.404900  iDelay=195, Bit 0, Center 138 (95 ~ 182) 88

 8974 16:51:09.408406  iDelay=195, Bit 1, Center 130 (83 ~ 178) 96

 8975 16:51:09.411326  iDelay=195, Bit 2, Center 120 (71 ~ 170) 100

 8976 16:51:09.414889  iDelay=195, Bit 3, Center 130 (83 ~ 178) 96

 8977 16:51:09.421472  iDelay=195, Bit 4, Center 134 (87 ~ 182) 96

 8978 16:51:09.424582  iDelay=195, Bit 5, Center 146 (99 ~ 194) 96

 8979 16:51:09.428070  iDelay=195, Bit 6, Center 142 (95 ~ 190) 96

 8980 16:51:09.431209  iDelay=195, Bit 7, Center 130 (83 ~ 178) 96

 8981 16:51:09.434403  iDelay=195, Bit 8, Center 112 (63 ~ 162) 100

 8982 16:51:09.441117  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 8983 16:51:09.444731  iDelay=195, Bit 10, Center 130 (79 ~ 182) 104

 8984 16:51:09.447830  iDelay=195, Bit 11, Center 126 (75 ~ 178) 104

 8985 16:51:09.451595  iDelay=195, Bit 12, Center 138 (87 ~ 190) 104

 8986 16:51:09.454157  iDelay=195, Bit 13, Center 136 (83 ~ 190) 108

 8987 16:51:09.461177  iDelay=195, Bit 14, Center 138 (91 ~ 186) 96

 8988 16:51:09.464097  iDelay=195, Bit 15, Center 138 (87 ~ 190) 104

 8989 16:51:09.464563  ==

 8990 16:51:09.467694  Dram Type= 6, Freq= 0, CH_1, rank 1

 8991 16:51:09.470787  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8992 16:51:09.471211  ==

 8993 16:51:09.473867  DQS Delay:

 8994 16:51:09.474329  DQS0 = 0, DQS1 = 0

 8995 16:51:09.477633  DQM Delay:

 8996 16:51:09.478103  DQM0 = 133, DQM1 = 129

 8997 16:51:09.478650  DQ Delay:

 8998 16:51:09.480517  DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =130

 8999 16:51:09.487062  DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130

 9000 16:51:09.490810  DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126

 9001 16:51:09.493635  DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138

 9002 16:51:09.494121  

 9003 16:51:09.494525  

 9004 16:51:09.494889  

 9005 16:51:09.496903  [DramC_TX_OE_Calibration] TA2

 9006 16:51:09.499816  Original DQ_B0 (3 6) =30, OEN = 27

 9007 16:51:09.503002  Original DQ_B1 (3 6) =30, OEN = 27

 9008 16:51:09.503084  24, 0x0, End_B0=24 End_B1=24

 9009 16:51:09.506525  25, 0x0, End_B0=25 End_B1=25

 9010 16:51:09.509991  26, 0x0, End_B0=26 End_B1=26

 9011 16:51:09.513002  27, 0x0, End_B0=27 End_B1=27

 9012 16:51:09.516350  28, 0x0, End_B0=28 End_B1=28

 9013 16:51:09.516434  29, 0x0, End_B0=29 End_B1=29

 9014 16:51:09.520159  30, 0x0, End_B0=30 End_B1=30

 9015 16:51:09.522833  31, 0x4545, End_B0=30 End_B1=30

 9016 16:51:09.525998  Byte0 end_step=30  best_step=27

 9017 16:51:09.529451  Byte1 end_step=30  best_step=27

 9018 16:51:09.532999  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9019 16:51:09.533109  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9020 16:51:09.533205  

 9021 16:51:09.533294  

 9022 16:51:09.542593  [DQSOSCAuto] RK1, (LSB)MR18= 0x1b07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps

 9023 16:51:09.546112  CH1 RK1: MR19=303, MR18=1B07

 9024 16:51:09.552349  CH1_RK1: MR19=0x303, MR18=0x1B07, DQSOSC=396, MR23=63, INC=23, DEC=15

 9025 16:51:09.555762  [RxdqsGatingPostProcess] freq 1600

 9026 16:51:09.559451  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9027 16:51:09.562827  best DQS0 dly(2T, 0.5T) = (1, 1)

 9028 16:51:09.565866  best DQS1 dly(2T, 0.5T) = (1, 1)

 9029 16:51:09.569199  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9030 16:51:09.572424  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9031 16:51:09.575599  best DQS0 dly(2T, 0.5T) = (1, 1)

 9032 16:51:09.579042  best DQS1 dly(2T, 0.5T) = (1, 1)

 9033 16:51:09.582293  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9034 16:51:09.585550  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9035 16:51:09.589446  Pre-setting of DQS Precalculation

 9036 16:51:09.592644  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9037 16:51:09.599140  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9038 16:51:09.605741  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9039 16:51:09.606164  

 9040 16:51:09.609229  

 9041 16:51:09.609645  [Calibration Summary] 3200 Mbps

 9042 16:51:09.612381  CH 0, Rank 0

 9043 16:51:09.612798  SW Impedance     : PASS

 9044 16:51:09.615418  DUTY Scan        : NO K

 9045 16:51:09.618810  ZQ Calibration   : PASS

 9046 16:51:09.618892  Jitter Meter     : NO K

 9047 16:51:09.622086  CBT Training     : PASS

 9048 16:51:09.625814  Write leveling   : PASS

 9049 16:51:09.625983  RX DQS gating    : PASS

 9050 16:51:09.629224  RX DQ/DQS(RDDQC) : PASS

 9051 16:51:09.632159  TX DQ/DQS        : PASS

 9052 16:51:09.632321  RX DATLAT        : PASS

 9053 16:51:09.635195  RX DQ/DQS(Engine): PASS

 9054 16:51:09.638471  TX OE            : PASS

 9055 16:51:09.638584  All Pass.

 9056 16:51:09.638674  

 9057 16:51:09.638756  CH 0, Rank 1

 9058 16:51:09.641794  SW Impedance     : PASS

 9059 16:51:09.645398  DUTY Scan        : NO K

 9060 16:51:09.645520  ZQ Calibration   : PASS

 9061 16:51:09.648995  Jitter Meter     : NO K

 9062 16:51:09.651896  CBT Training     : PASS

 9063 16:51:09.652116  Write leveling   : PASS

 9064 16:51:09.654995  RX DQS gating    : PASS

 9065 16:51:09.658256  RX DQ/DQS(RDDQC) : PASS

 9066 16:51:09.658544  TX DQ/DQS        : PASS

 9067 16:51:09.661948  RX DATLAT        : PASS

 9068 16:51:09.665095  RX DQ/DQS(Engine): PASS

 9069 16:51:09.665376  TX OE            : PASS

 9070 16:51:09.665542  All Pass.

 9071 16:51:09.668550  

 9072 16:51:09.668789  CH 1, Rank 0

 9073 16:51:09.671534  SW Impedance     : PASS

 9074 16:51:09.671774  DUTY Scan        : NO K

 9075 16:51:09.674774  ZQ Calibration   : PASS

 9076 16:51:09.678364  Jitter Meter     : NO K

 9077 16:51:09.678752  CBT Training     : PASS

 9078 16:51:09.681614  Write leveling   : PASS

 9079 16:51:09.682000  RX DQS gating    : PASS

 9080 16:51:09.684750  RX DQ/DQS(RDDQC) : PASS

 9081 16:51:09.688298  TX DQ/DQS        : PASS

 9082 16:51:09.688766  RX DATLAT        : PASS

 9083 16:51:09.691450  RX DQ/DQS(Engine): PASS

 9084 16:51:09.695006  TX OE            : PASS

 9085 16:51:09.695483  All Pass.

 9086 16:51:09.695853  

 9087 16:51:09.696196  CH 1, Rank 1

 9088 16:51:09.698001  SW Impedance     : PASS

 9089 16:51:09.701887  DUTY Scan        : NO K

 9090 16:51:09.702387  ZQ Calibration   : PASS

 9091 16:51:09.704687  Jitter Meter     : NO K

 9092 16:51:09.708034  CBT Training     : PASS

 9093 16:51:09.708500  Write leveling   : PASS

 9094 16:51:09.711748  RX DQS gating    : PASS

 9095 16:51:09.714923  RX DQ/DQS(RDDQC) : PASS

 9096 16:51:09.715389  TX DQ/DQS        : PASS

 9097 16:51:09.718067  RX DATLAT        : PASS

 9098 16:51:09.721390  RX DQ/DQS(Engine): PASS

 9099 16:51:09.721961  TX OE            : PASS

 9100 16:51:09.724680  All Pass.

 9101 16:51:09.725148  

 9102 16:51:09.725517  DramC Write-DBI on

 9103 16:51:09.728057  	PER_BANK_REFRESH: Hybrid Mode

 9104 16:51:09.728525  TX_TRACKING: ON

 9105 16:51:09.737671  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9106 16:51:09.747653  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9107 16:51:09.754379  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9108 16:51:09.757343  [FAST_K] Save calibration result to emmc

 9109 16:51:09.760774  sync common calibartion params.

 9110 16:51:09.761198  sync cbt_mode0:1, 1:1

 9111 16:51:09.764322  dram_init: ddr_geometry: 2

 9112 16:51:09.767420  dram_init: ddr_geometry: 2

 9113 16:51:09.767844  dram_init: ddr_geometry: 2

 9114 16:51:09.770657  0:dram_rank_size:100000000

 9115 16:51:09.774134  1:dram_rank_size:100000000

 9116 16:51:09.780767  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9117 16:51:09.781195  DFS_SHUFFLE_HW_MODE: ON

 9118 16:51:09.784099  dramc_set_vcore_voltage set vcore to 725000

 9119 16:51:09.787237  Read voltage for 1600, 0

 9120 16:51:09.787660  Vio18 = 0

 9121 16:51:09.790570  Vcore = 725000

 9122 16:51:09.790992  Vdram = 0

 9123 16:51:09.791327  Vddq = 0

 9124 16:51:09.793702  Vmddr = 0

 9125 16:51:09.794122  switch to 3200 Mbps bootup

 9126 16:51:09.797055  [DramcRunTimeConfig]

 9127 16:51:09.797478  PHYPLL

 9128 16:51:09.800611  DPM_CONTROL_AFTERK: ON

 9129 16:51:09.801031  PER_BANK_REFRESH: ON

 9130 16:51:09.803647  REFRESH_OVERHEAD_REDUCTION: ON

 9131 16:51:09.806842  CMD_PICG_NEW_MODE: OFF

 9132 16:51:09.807265  XRTWTW_NEW_MODE: ON

 9133 16:51:09.810216  XRTRTR_NEW_MODE: ON

 9134 16:51:09.810665  TX_TRACKING: ON

 9135 16:51:09.813648  RDSEL_TRACKING: OFF

 9136 16:51:09.817266  DQS Precalculation for DVFS: ON

 9137 16:51:09.817691  RX_TRACKING: OFF

 9138 16:51:09.820384  HW_GATING DBG: ON

 9139 16:51:09.820807  ZQCS_ENABLE_LP4: ON

 9140 16:51:09.823454  RX_PICG_NEW_MODE: ON

 9141 16:51:09.823916  TX_PICG_NEW_MODE: ON

 9142 16:51:09.826798  ENABLE_RX_DCM_DPHY: ON

 9143 16:51:09.830156  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9144 16:51:09.833636  DUMMY_READ_FOR_TRACKING: OFF

 9145 16:51:09.836610  !!! SPM_CONTROL_AFTERK: OFF

 9146 16:51:09.837143  !!! SPM could not control APHY

 9147 16:51:09.840034  IMPEDANCE_TRACKING: ON

 9148 16:51:09.840454  TEMP_SENSOR: ON

 9149 16:51:09.843518  HW_SAVE_FOR_SR: OFF

 9150 16:51:09.846689  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9151 16:51:09.850238  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9152 16:51:09.853343  Read ODT Tracking: ON

 9153 16:51:09.853801  Refresh Rate DeBounce: ON

 9154 16:51:09.856696  DFS_NO_QUEUE_FLUSH: ON

 9155 16:51:09.860006  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9156 16:51:09.863279  ENABLE_DFS_RUNTIME_MRW: OFF

 9157 16:51:09.863720  DDR_RESERVE_NEW_MODE: ON

 9158 16:51:09.866469  MR_CBT_SWITCH_FREQ: ON

 9159 16:51:09.870064  =========================

 9160 16:51:09.887473  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9161 16:51:09.890477  dram_init: ddr_geometry: 2

 9162 16:51:09.908748  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9163 16:51:09.912073  dram_init: dram init end (result: 0)

 9164 16:51:09.918868  DRAM-K: Full calibration passed in 24516 msecs

 9165 16:51:09.922176  MRC: failed to locate region type 0.

 9166 16:51:09.922640  DRAM rank0 size:0x100000000,

 9167 16:51:09.925326  DRAM rank1 size=0x100000000

 9168 16:51:09.935494  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9169 16:51:09.941669  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9170 16:51:09.948602  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9171 16:51:09.958493  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9172 16:51:09.959056  DRAM rank0 size:0x100000000,

 9173 16:51:09.962006  DRAM rank1 size=0x100000000

 9174 16:51:09.962560  CBMEM:

 9175 16:51:09.965293  IMD: root @ 0xfffff000 254 entries.

 9176 16:51:09.968691  IMD: root @ 0xffffec00 62 entries.

 9177 16:51:09.972148  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9178 16:51:09.978248  WARNING: RO_VPD is uninitialized or empty.

 9179 16:51:09.981595  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9180 16:51:09.989303  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9181 16:51:10.001715  read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps

 9182 16:51:10.013187  BS: romstage times (exec / console): total (unknown) / 24011 ms

 9183 16:51:10.013660  

 9184 16:51:10.014031  

 9185 16:51:10.022844  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9186 16:51:10.026389  ARM64: Exception handlers installed.

 9187 16:51:10.029440  ARM64: Testing exception

 9188 16:51:10.032828  ARM64: Done test exception

 9189 16:51:10.033301  Enumerating buses...

 9190 16:51:10.036138  Show all devs... Before device enumeration.

 9191 16:51:10.040101  Root Device: enabled 1

 9192 16:51:10.042875  CPU_CLUSTER: 0: enabled 1

 9193 16:51:10.043346  CPU: 00: enabled 1

 9194 16:51:10.046025  Compare with tree...

 9195 16:51:10.046569  Root Device: enabled 1

 9196 16:51:10.049439   CPU_CLUSTER: 0: enabled 1

 9197 16:51:10.052591    CPU: 00: enabled 1

 9198 16:51:10.053056  Root Device scanning...

 9199 16:51:10.056137  scan_static_bus for Root Device

 9200 16:51:10.059202  CPU_CLUSTER: 0 enabled

 9201 16:51:10.062789  scan_static_bus for Root Device done

 9202 16:51:10.065876  scan_bus: bus Root Device finished in 8 msecs

 9203 16:51:10.066379  done

 9204 16:51:10.072642  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9205 16:51:10.075532  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9206 16:51:10.082232  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9207 16:51:10.088849  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9208 16:51:10.089276  Allocating resources...

 9209 16:51:10.092163  Reading resources...

 9210 16:51:10.095265  Root Device read_resources bus 0 link: 0

 9211 16:51:10.098413  DRAM rank0 size:0x100000000,

 9212 16:51:10.098856  DRAM rank1 size=0x100000000

 9213 16:51:10.105117  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9214 16:51:10.105593  CPU: 00 missing read_resources

 9215 16:51:10.111726  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9216 16:51:10.115054  Root Device read_resources bus 0 link: 0 done

 9217 16:51:10.118410  Done reading resources.

 9218 16:51:10.121756  Show resources in subtree (Root Device)...After reading.

 9219 16:51:10.124979   Root Device child on link 0 CPU_CLUSTER: 0

 9220 16:51:10.128246    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9221 16:51:10.138472    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9222 16:51:10.138943     CPU: 00

 9223 16:51:10.144585  Root Device assign_resources, bus 0 link: 0

 9224 16:51:10.147790  CPU_CLUSTER: 0 missing set_resources

 9225 16:51:10.151560  Root Device assign_resources, bus 0 link: 0 done

 9226 16:51:10.154542  Done setting resources.

 9227 16:51:10.157749  Show resources in subtree (Root Device)...After assigning values.

 9228 16:51:10.164364   Root Device child on link 0 CPU_CLUSTER: 0

 9229 16:51:10.167805    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9230 16:51:10.174321    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9231 16:51:10.178655     CPU: 00

 9232 16:51:10.179074  Done allocating resources.

 9233 16:51:10.184370  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9234 16:51:10.187378  Enabling resources...

 9235 16:51:10.187800  done.

 9236 16:51:10.190835  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9237 16:51:10.194237  Initializing devices...

 9238 16:51:10.194804  Root Device init

 9239 16:51:10.197612  init hardware done!

 9240 16:51:10.200745  0x00000018: ctrlr->caps

 9241 16:51:10.201238  52.000 MHz: ctrlr->f_max

 9242 16:51:10.203990  0.400 MHz: ctrlr->f_min

 9243 16:51:10.206986  0x40ff8080: ctrlr->voltages

 9244 16:51:10.207458  sclk: 390625

 9245 16:51:10.207827  Bus Width = 1

 9246 16:51:10.210548  sclk: 390625

 9247 16:51:10.211010  Bus Width = 1

 9248 16:51:10.214117  Early init status = 3

 9249 16:51:10.216978  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9250 16:51:10.220764  in-header: 03 fc 00 00 01 00 00 00 

 9251 16:51:10.224694  in-data: 00 

 9252 16:51:10.227485  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9253 16:51:10.232195  in-header: 03 fd 00 00 00 00 00 00 

 9254 16:51:10.235255  in-data: 

 9255 16:51:10.238462  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9256 16:51:10.241780  in-header: 03 fc 00 00 01 00 00 00 

 9257 16:51:10.245368  in-data: 00 

 9258 16:51:10.248834  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9259 16:51:10.253670  in-header: 03 fd 00 00 00 00 00 00 

 9260 16:51:10.256605  in-data: 

 9261 16:51:10.259651  [SSUSB] Setting up USB HOST controller...

 9262 16:51:10.263422  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9263 16:51:10.266273  [SSUSB] phy power-on done.

 9264 16:51:10.269821  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9265 16:51:10.276355  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9266 16:51:10.279675  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9267 16:51:10.286333  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9268 16:51:10.292921  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9269 16:51:10.299257  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9270 16:51:10.306236  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9271 16:51:10.312730  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9272 16:51:10.315382  SPM: binary array size = 0x9dc

 9273 16:51:10.319092  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9274 16:51:10.326160  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9275 16:51:10.332485  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9276 16:51:10.339065  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9277 16:51:10.342467  configure_display: Starting display init

 9278 16:51:10.376596  anx7625_power_on_init: Init interface.

 9279 16:51:10.379757  anx7625_disable_pd_protocol: Disabled PD feature.

 9280 16:51:10.383025  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9281 16:51:10.410718  anx7625_start_dp_work: Secure OCM version=00

 9282 16:51:10.414673  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9283 16:51:10.429032  sp_tx_get_edid_block: EDID Block = 1

 9284 16:51:10.531406  Extracted contents:

 9285 16:51:10.535122  header:          00 ff ff ff ff ff ff 00

 9286 16:51:10.538209  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9287 16:51:10.541709  version:         01 04

 9288 16:51:10.544776  basic params:    95 1f 11 78 0a

 9289 16:51:10.547732  chroma info:     76 90 94 55 54 90 27 21 50 54

 9290 16:51:10.551433  established:     00 00 00

 9291 16:51:10.557791  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9292 16:51:10.564155  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9293 16:51:10.567788  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9294 16:51:10.574561  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9295 16:51:10.580439  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9296 16:51:10.583840  extensions:      00

 9297 16:51:10.583924  checksum:        fb

 9298 16:51:10.583989  

 9299 16:51:10.590628  Manufacturer: IVO Model 57d Serial Number 0

 9300 16:51:10.590710  Made week 0 of 2020

 9301 16:51:10.593739  EDID version: 1.4

 9302 16:51:10.593826  Digital display

 9303 16:51:10.597001  6 bits per primary color channel

 9304 16:51:10.597104  DisplayPort interface

 9305 16:51:10.600283  Maximum image size: 31 cm x 17 cm

 9306 16:51:10.603355  Gamma: 220%

 9307 16:51:10.603434  Check DPMS levels

 9308 16:51:10.610273  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9309 16:51:10.613772  First detailed timing is preferred timing

 9310 16:51:10.613846  Established timings supported:

 9311 16:51:10.617207  Standard timings supported:

 9312 16:51:10.620430  Detailed timings

 9313 16:51:10.623497  Hex of detail: 383680a07038204018303c0035ae10000019

 9314 16:51:10.629819  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9315 16:51:10.633378                 0780 0798 07c8 0820 hborder 0

 9316 16:51:10.636433                 0438 043b 0447 0458 vborder 0

 9317 16:51:10.640157                 -hsync -vsync

 9318 16:51:10.640251  Did detailed timing

 9319 16:51:10.646495  Hex of detail: 000000000000000000000000000000000000

 9320 16:51:10.649850  Manufacturer-specified data, tag 0

 9321 16:51:10.653579  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9322 16:51:10.656282  ASCII string: InfoVision

 9323 16:51:10.659718  Hex of detail: 000000fe00523134304e574635205248200a

 9324 16:51:10.662740  ASCII string: R140NWF5 RH 

 9325 16:51:10.662885  Checksum

 9326 16:51:10.666541  Checksum: 0xfb (valid)

 9327 16:51:10.669645  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9328 16:51:10.672899  DSI data_rate: 832800000 bps

 9329 16:51:10.679856  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9330 16:51:10.683074  anx7625_parse_edid: pixelclock(138800).

 9331 16:51:10.686391   hactive(1920), hsync(48), hfp(24), hbp(88)

 9332 16:51:10.689580   vactive(1080), vsync(12), vfp(3), vbp(17)

 9333 16:51:10.693507  anx7625_dsi_config: config dsi.

 9334 16:51:10.699467  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9335 16:51:10.713992  anx7625_dsi_config: success to config DSI

 9336 16:51:10.717256  anx7625_dp_start: MIPI phy setup OK.

 9337 16:51:10.720020  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9338 16:51:10.723883  mtk_ddp_mode_set invalid vrefresh 60

 9339 16:51:10.727173  main_disp_path_setup

 9340 16:51:10.727711  ovl_layer_smi_id_en

 9341 16:51:10.730330  ovl_layer_smi_id_en

 9342 16:51:10.730821  ccorr_config

 9343 16:51:10.731182  aal_config

 9344 16:51:10.733517  gamma_config

 9345 16:51:10.733974  postmask_config

 9346 16:51:10.736635  dither_config

 9347 16:51:10.740027  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9348 16:51:10.746500                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9349 16:51:10.749663  Root Device init finished in 551 msecs

 9350 16:51:10.752978  CPU_CLUSTER: 0 init

 9351 16:51:10.759534  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9352 16:51:10.766255  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9353 16:51:10.766968  APU_MBOX 0x190000b0 = 0x10001

 9354 16:51:10.769567  APU_MBOX 0x190001b0 = 0x10001

 9355 16:51:10.772725  APU_MBOX 0x190005b0 = 0x10001

 9356 16:51:10.776201  APU_MBOX 0x190006b0 = 0x10001

 9357 16:51:10.782846  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9358 16:51:10.792409  read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps

 9359 16:51:10.804942  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9360 16:51:10.812141  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9361 16:51:10.823358  read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps

 9362 16:51:10.832285  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9363 16:51:10.835641  CPU_CLUSTER: 0 init finished in 81 msecs

 9364 16:51:10.838998  Devices initialized

 9365 16:51:10.842338  Show all devs... After init.

 9366 16:51:10.842810  Root Device: enabled 1

 9367 16:51:10.845634  CPU_CLUSTER: 0: enabled 1

 9368 16:51:10.849006  CPU: 00: enabled 1

 9369 16:51:10.852151  BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms

 9370 16:51:10.855554  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9371 16:51:10.858689  ELOG: NV offset 0x57f000 size 0x1000

 9372 16:51:10.865278  read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps

 9373 16:51:10.871994  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9374 16:51:10.874972  ELOG: Event(17) added with size 13 at 2023-06-03 16:51:11 UTC

 9375 16:51:10.881786  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9376 16:51:10.885029  in-header: 03 20 00 00 2c 00 00 00 

 9377 16:51:10.898240  in-data: 3f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9378 16:51:10.901660  ELOG: Event(A1) added with size 10 at 2023-06-03 16:51:11 UTC

 9379 16:51:10.908152  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9380 16:51:10.914587  ELOG: Event(A0) added with size 9 at 2023-06-03 16:51:11 UTC

 9381 16:51:10.917825  elog_add_boot_reason: Logged dev mode boot

 9382 16:51:10.924308  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9383 16:51:10.924390  Finalize devices...

 9384 16:51:10.927353  Devices finalized

 9385 16:51:10.930718  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9386 16:51:10.933963  Writing coreboot table at 0xffe64000

 9387 16:51:10.940432   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9388 16:51:10.944332   1. 0000000040000000-00000000400fffff: RAM

 9389 16:51:10.947548   2. 0000000040100000-000000004032afff: RAMSTAGE

 9390 16:51:10.950736   3. 000000004032b000-00000000545fffff: RAM

 9391 16:51:10.954252   4. 0000000054600000-000000005465ffff: BL31

 9392 16:51:10.960644   5. 0000000054660000-00000000ffe63fff: RAM

 9393 16:51:10.963863   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9394 16:51:10.967062   7. 0000000100000000-000000023fffffff: RAM

 9395 16:51:10.970591  Passing 5 GPIOs to payload:

 9396 16:51:10.973730              NAME |       PORT | POLARITY |     VALUE

 9397 16:51:10.980309          EC in RW | 0x000000aa |      low | undefined

 9398 16:51:10.983704      EC interrupt | 0x00000005 |      low | undefined

 9399 16:51:10.990314     TPM interrupt | 0x000000ab |     high | undefined

 9400 16:51:10.993402    SD card detect | 0x00000011 |     high | undefined

 9401 16:51:11.000301    speaker enable | 0x00000093 |     high | undefined

 9402 16:51:11.003572  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9403 16:51:11.006649  in-header: 03 f9 00 00 02 00 00 00 

 9404 16:51:11.006733  in-data: 02 00 

 9405 16:51:11.010088  ADC[4]: Raw value=901401 ID=7

 9406 16:51:11.013249  ADC[3]: Raw value=213179 ID=1

 9407 16:51:11.013332  RAM Code: 0x71

 9408 16:51:11.016771  ADC[6]: Raw value=74502 ID=0

 9409 16:51:11.020074  ADC[5]: Raw value=212441 ID=1

 9410 16:51:11.020157  SKU Code: 0x1

 9411 16:51:11.026361  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3

 9412 16:51:11.029983  coreboot table: 964 bytes.

 9413 16:51:11.032834  IMD ROOT    0. 0xfffff000 0x00001000

 9414 16:51:11.036513  IMD SMALL   1. 0xffffe000 0x00001000

 9415 16:51:11.039604  RO MCACHE   2. 0xffffc000 0x00001104

 9416 16:51:11.042757  CONSOLE     3. 0xfff7c000 0x00080000

 9417 16:51:11.046235  FMAP        4. 0xfff7b000 0x00000452

 9418 16:51:11.049459  TIME STAMP  5. 0xfff7a000 0x00000910

 9419 16:51:11.052562  VBOOT WORK  6. 0xfff66000 0x00014000

 9420 16:51:11.055992  RAMOOPS     7. 0xffe66000 0x00100000

 9421 16:51:11.059265  COREBOOT    8. 0xffe64000 0x00002000

 9422 16:51:11.059352  IMD small region:

 9423 16:51:11.062678    IMD ROOT    0. 0xffffec00 0x00000400

 9424 16:51:11.066141    VPD         1. 0xffffeba0 0x0000004c

 9425 16:51:11.069399    MMC STATUS  2. 0xffffeb80 0x00000004

 9426 16:51:11.076115  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9427 16:51:11.076198  Probing TPM:  done!

 9428 16:51:11.082738  Connected to device vid:did:rid of 1ae0:0028:00

 9429 16:51:11.089317  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

 9430 16:51:11.096663  Initialized TPM device CR50 revision 0

 9431 16:51:11.096750  Checking cr50 for pending updates

 9432 16:51:11.102702  Reading cr50 TPM mode

 9433 16:51:11.110803  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9434 16:51:11.117456  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9435 16:51:11.157423  read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps

 9436 16:51:11.160554  Checking segment from ROM address 0x40100000

 9437 16:51:11.164008  Checking segment from ROM address 0x4010001c

 9438 16:51:11.170656  Loading segment from ROM address 0x40100000

 9439 16:51:11.170742    code (compression=0)

 9440 16:51:11.180694    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9441 16:51:11.187089  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9442 16:51:11.187170  it's not compressed!

 9443 16:51:11.193888  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9444 16:51:11.200245  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9445 16:51:11.217828  Loading segment from ROM address 0x4010001c

 9446 16:51:11.217908    Entry Point 0x80000000

 9447 16:51:11.221415  Loaded segments

 9448 16:51:11.224753  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9449 16:51:11.231343  Jumping to boot code at 0x80000000(0xffe64000)

 9450 16:51:11.237939  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9451 16:51:11.244587  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9452 16:51:11.252123  read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps

 9453 16:51:11.255476  Checking segment from ROM address 0x40100000

 9454 16:51:11.259100  Checking segment from ROM address 0x4010001c

 9455 16:51:11.265654  Loading segment from ROM address 0x40100000

 9456 16:51:11.265738    code (compression=1)

 9457 16:51:11.272399    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9458 16:51:11.282537  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9459 16:51:11.282617  using LZMA

 9460 16:51:11.291164  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9461 16:51:11.297893  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9462 16:51:11.301171  Loading segment from ROM address 0x4010001c

 9463 16:51:11.301272    Entry Point 0x54601000

 9464 16:51:11.304009  Loaded segments

 9465 16:51:11.307698  NOTICE:  MT8192 bl31_setup

 9466 16:51:11.314276  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9467 16:51:11.317510  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9468 16:51:11.320969  WARNING: region 0:

 9469 16:51:11.324541  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9470 16:51:11.324638  WARNING: region 1:

 9471 16:51:11.331075  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9472 16:51:11.334576  WARNING: region 2:

 9473 16:51:11.337653  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9474 16:51:11.340763  WARNING: region 3:

 9475 16:51:11.344472  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9476 16:51:11.347400  WARNING: region 4:

 9477 16:51:11.353907  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9478 16:51:11.354011  WARNING: region 5:

 9479 16:51:11.357160  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9480 16:51:11.360697  WARNING: region 6:

 9481 16:51:11.363653  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9482 16:51:11.367069  WARNING: region 7:

 9483 16:51:11.370506  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9484 16:51:11.376956  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9485 16:51:11.380375  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9486 16:51:11.386983  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9487 16:51:11.390174  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9488 16:51:11.393801  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9489 16:51:11.400461  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9490 16:51:11.403231  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9491 16:51:11.406986  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9492 16:51:11.413342  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9493 16:51:11.416554  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9494 16:51:11.423664  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9495 16:51:11.426652  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9496 16:51:11.429898  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9497 16:51:11.436558  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9498 16:51:11.440033  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9499 16:51:11.442925  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9500 16:51:11.449763  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9501 16:51:11.453120  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9502 16:51:11.459765  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9503 16:51:11.463030  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9504 16:51:11.466376  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9505 16:51:11.472853  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9506 16:51:11.476363  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9507 16:51:11.482636  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9508 16:51:11.486183  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9509 16:51:11.489428  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9510 16:51:11.495939  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9511 16:51:11.499645  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9512 16:51:11.505826  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9513 16:51:11.508909  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9514 16:51:11.515571  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9515 16:51:11.518767  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9516 16:51:11.522329  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9517 16:51:11.525853  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9518 16:51:11.532437  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9519 16:51:11.535356  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9520 16:51:11.538971  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9521 16:51:11.542206  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9522 16:51:11.548941  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9523 16:51:11.552296  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9524 16:51:11.556139  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9525 16:51:11.558784  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9526 16:51:11.566308  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9527 16:51:11.569468  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9528 16:51:11.572118  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9529 16:51:11.579021  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9530 16:51:11.582158  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9531 16:51:11.585386  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9532 16:51:11.591917  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9533 16:51:11.595656  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9534 16:51:11.598583  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9535 16:51:11.605137  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9536 16:51:11.608610  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9537 16:51:11.615030  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9538 16:51:11.618678  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9539 16:51:11.625346  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9540 16:51:11.628530  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9541 16:51:11.631941  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9542 16:51:11.638482  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9543 16:51:11.641495  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9544 16:51:11.648235  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9545 16:51:11.651597  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9546 16:51:11.658465  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9547 16:51:11.661504  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9548 16:51:11.668199  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9549 16:51:11.671546  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9550 16:51:11.674830  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9551 16:51:11.681624  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9552 16:51:11.684584  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9553 16:51:11.691402  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9554 16:51:11.694799  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9555 16:51:11.701425  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9556 16:51:11.704505  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9557 16:51:11.708508  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9558 16:51:11.715064  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9559 16:51:11.718072  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9560 16:51:11.725164  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9561 16:51:11.728033  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9562 16:51:11.734723  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9563 16:51:11.737870  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9564 16:51:11.744253  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9565 16:51:11.747617  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9566 16:51:11.750914  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9567 16:51:11.757624  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9568 16:51:11.760904  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9569 16:51:11.767351  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9570 16:51:11.771026  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9571 16:51:11.777172  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9572 16:51:11.780400  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9573 16:51:11.787108  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9574 16:51:11.790517  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9575 16:51:11.793672  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9576 16:51:11.800324  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9577 16:51:11.803380  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9578 16:51:11.810112  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9579 16:51:11.813827  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9580 16:51:11.820727  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9581 16:51:11.823565  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9582 16:51:11.827108  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9583 16:51:11.830063  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9584 16:51:11.833470  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9585 16:51:11.840099  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9586 16:51:11.843809  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9587 16:51:11.850083  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9588 16:51:11.853955  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9589 16:51:11.860310  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9590 16:51:11.863695  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9591 16:51:11.866681  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9592 16:51:11.873849  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9593 16:51:11.876778  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9594 16:51:11.883726  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9595 16:51:11.886674  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9596 16:51:11.889661  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9597 16:51:11.896383  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9598 16:51:11.899442  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9599 16:51:11.906286  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9600 16:51:11.909693  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9601 16:51:11.913130  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9602 16:51:11.916575  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9603 16:51:11.923052  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9604 16:51:11.926497  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9605 16:51:11.929817  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9606 16:51:11.932746  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9607 16:51:11.939834  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9608 16:51:11.942849  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9609 16:51:11.946146  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9610 16:51:11.952832  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9611 16:51:11.956158  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9612 16:51:11.962902  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9613 16:51:11.966049  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9614 16:51:11.969635  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9615 16:51:11.975936  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9616 16:51:11.979395  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9617 16:51:11.986121  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9618 16:51:11.989209  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9619 16:51:11.992737  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9620 16:51:11.999435  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9621 16:51:12.002444  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9622 16:51:12.009302  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9623 16:51:12.012402  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9624 16:51:12.016016  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9625 16:51:12.022288  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9626 16:51:12.025864  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9627 16:51:12.032239  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9628 16:51:12.035632  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9629 16:51:12.038930  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9630 16:51:12.046099  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9631 16:51:12.049244  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9632 16:51:12.055839  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9633 16:51:12.059434  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9634 16:51:12.062298  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9635 16:51:12.068938  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9636 16:51:12.072844  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9637 16:51:12.079108  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9638 16:51:12.082274  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9639 16:51:12.085713  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9640 16:51:12.092021  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9641 16:51:12.095590  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9642 16:51:12.098589  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9643 16:51:12.105178  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9644 16:51:12.108804  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9645 16:51:12.115320  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9646 16:51:12.118657  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9647 16:51:12.125490  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9648 16:51:12.128473  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9649 16:51:12.132027  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9650 16:51:12.138264  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9651 16:51:12.141681  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9652 16:51:12.145219  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9653 16:51:12.151878  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9654 16:51:12.154994  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9655 16:51:12.162209  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9656 16:51:12.165064  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9657 16:51:12.168441  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9658 16:51:12.174924  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9659 16:51:12.178204  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9660 16:51:12.184552  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9661 16:51:12.188143  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9662 16:51:12.191278  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9663 16:51:12.198263  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9664 16:51:12.201313  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9665 16:51:12.207857  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9666 16:51:12.211353  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9667 16:51:12.214641  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9668 16:51:12.220943  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9669 16:51:12.224422  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9670 16:51:12.230787  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9671 16:51:12.234435  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9672 16:51:12.240583  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9673 16:51:12.244043  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9674 16:51:12.247134  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9675 16:51:12.253563  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9676 16:51:12.256974  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9677 16:51:12.263930  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9678 16:51:12.267348  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9679 16:51:12.273666  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9680 16:51:12.276615  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9681 16:51:12.280160  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9682 16:51:12.286680  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9683 16:51:12.289743  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9684 16:51:12.296578  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9685 16:51:12.299772  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9686 16:51:12.306556  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9687 16:51:12.309709  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9688 16:51:12.312973  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9689 16:51:12.319916  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9690 16:51:12.322526  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9691 16:51:12.329411  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9692 16:51:12.332767  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9693 16:51:12.335761  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9694 16:51:12.342421  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9695 16:51:12.346012  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9696 16:51:12.352349  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9697 16:51:12.355704  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9698 16:51:12.362465  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9699 16:51:12.365862  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9700 16:51:12.369124  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9701 16:51:12.375265  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9702 16:51:12.378944  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9703 16:51:12.385485  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9704 16:51:12.388826  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9705 16:51:12.395589  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9706 16:51:12.398949  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9707 16:51:12.401964  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9708 16:51:12.408534  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9709 16:51:12.412402  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9710 16:51:12.418840  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9711 16:51:12.422031  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9712 16:51:12.428517  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9713 16:51:12.432393  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9714 16:51:12.435420  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9715 16:51:12.438783  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9716 16:51:12.441597  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9717 16:51:12.448380  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9718 16:51:12.451784  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9719 16:51:12.458373  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9720 16:51:12.461643  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9721 16:51:12.465039  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9722 16:51:12.471310  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9723 16:51:12.474831  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9724 16:51:12.477899  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9725 16:51:12.484438  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9726 16:51:12.487711  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9727 16:51:12.494662  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9728 16:51:12.497629  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9729 16:51:12.500784  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9730 16:51:12.507784  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9731 16:51:12.511104  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9732 16:51:12.514271  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9733 16:51:12.520898  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9734 16:51:12.524061  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9735 16:51:12.531184  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9736 16:51:12.533996  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9737 16:51:12.537153  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9738 16:51:12.543725  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9739 16:51:12.547390  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9740 16:51:12.550181  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9741 16:51:12.557465  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9742 16:51:12.560186  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9743 16:51:12.566763  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9744 16:51:12.570108  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9745 16:51:12.573286  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9746 16:51:12.580375  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9747 16:51:12.583697  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9748 16:51:12.586912  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9749 16:51:12.593313  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9750 16:51:12.596903  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9751 16:51:12.603213  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9752 16:51:12.606462  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9753 16:51:12.610131  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9754 16:51:12.613135  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9755 16:51:12.619923  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9756 16:51:12.622853  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9757 16:51:12.626530  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9758 16:51:12.629872  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9759 16:51:12.633316  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9760 16:51:12.639986  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9761 16:51:12.642859  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9762 16:51:12.646277  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9763 16:51:12.652827  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9764 16:51:12.655982  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9765 16:51:12.659507  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9766 16:51:12.666101  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9767 16:51:12.669609  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9768 16:51:12.672924  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9769 16:51:12.679091  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9770 16:51:12.682653  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9771 16:51:12.689591  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9772 16:51:12.693074  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9773 16:51:12.696354  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9774 16:51:12.702481  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9775 16:51:12.705460  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9776 16:51:12.712231  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9777 16:51:12.716535  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9778 16:51:12.722029  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9779 16:51:12.725384  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9780 16:51:12.732304  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9781 16:51:12.735467  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9782 16:51:12.738516  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9783 16:51:12.745071  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9784 16:51:12.749096  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9785 16:51:12.755011  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9786 16:51:12.758330  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9787 16:51:12.761602  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9788 16:51:12.768587  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9789 16:51:12.772039  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9790 16:51:12.778554  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9791 16:51:12.781274  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9792 16:51:12.784688  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9793 16:51:12.791041  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9794 16:51:12.794654  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9795 16:51:12.801133  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9796 16:51:12.804971  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9797 16:51:12.811188  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9798 16:51:12.814327  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9799 16:51:12.817802  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9800 16:51:12.824195  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9801 16:51:12.827650  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9802 16:51:12.834308  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9803 16:51:12.837620  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9804 16:51:12.844281  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9805 16:51:12.847700  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9806 16:51:12.850476  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9807 16:51:12.857345  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9808 16:51:12.860464  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9809 16:51:12.867353  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9810 16:51:12.870412  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9811 16:51:12.873703  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9812 16:51:12.880456  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9813 16:51:12.883593  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9814 16:51:12.890818  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9815 16:51:12.893627  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9816 16:51:12.896644  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9817 16:51:12.903252  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9818 16:51:12.906812  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9819 16:51:12.913452  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9820 16:51:12.916682  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9821 16:51:12.923012  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9822 16:51:12.926891  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9823 16:51:12.930110  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9824 16:51:12.936164  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9825 16:51:12.939573  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9826 16:51:12.945915  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9827 16:51:12.949803  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9828 16:51:12.956545  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9829 16:51:12.959550  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9830 16:51:12.962332  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9831 16:51:12.969299  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9832 16:51:12.972318  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9833 16:51:12.979355  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9834 16:51:12.982483  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9835 16:51:12.985881  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9836 16:51:12.992711  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9837 16:51:12.995808  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9838 16:51:13.002072  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9839 16:51:13.005653  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9840 16:51:13.011987  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9841 16:51:13.015590  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9842 16:51:13.021829  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9843 16:51:13.025094  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9844 16:51:13.028676  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9845 16:51:13.035389  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9846 16:51:13.038911  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9847 16:51:13.044922  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9848 16:51:13.048292  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9849 16:51:13.055023  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9850 16:51:13.058186  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9851 16:51:13.064739  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9852 16:51:13.068228  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9853 16:51:13.071305  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9854 16:51:13.078122  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9855 16:51:13.081403  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9856 16:51:13.087842  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9857 16:51:13.091495  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9858 16:51:13.097731  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9859 16:51:13.101246  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9860 16:51:13.107732  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9861 16:51:13.111254  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9862 16:51:13.114604  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9863 16:51:13.120919  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9864 16:51:13.124272  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9865 16:51:13.130467  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9866 16:51:13.134402  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9867 16:51:13.140735  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9868 16:51:13.143880  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9869 16:51:13.147541  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9870 16:51:13.153964  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9871 16:51:13.157012  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9872 16:51:13.163762  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9873 16:51:13.167289  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9874 16:51:13.173616  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9875 16:51:13.176579  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9876 16:51:13.183214  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9877 16:51:13.186448  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9878 16:51:13.192897  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9879 16:51:13.196415  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9880 16:51:13.202850  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9881 16:51:13.206200  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9882 16:51:13.209828  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9883 16:51:13.216651  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9884 16:51:13.219784  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9885 16:51:13.225796  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9886 16:51:13.229036  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9887 16:51:13.232699  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9888 16:51:13.238933  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9889 16:51:13.242475  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9890 16:51:13.248781  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9891 16:51:13.252282  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9892 16:51:13.259360  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9893 16:51:13.261957  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9894 16:51:13.268873  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9895 16:51:13.271884  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9896 16:51:13.278943  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9897 16:51:13.281931  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9898 16:51:13.288442  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9899 16:51:13.291594  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9900 16:51:13.298634  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9901 16:51:13.301635  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9902 16:51:13.308168  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9903 16:51:13.311690  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9904 16:51:13.318295  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9905 16:51:13.321922  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9906 16:51:13.328100  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9907 16:51:13.331282  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9908 16:51:13.338248  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9909 16:51:13.341083  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9910 16:51:13.347713  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9911 16:51:13.351324  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9912 16:51:13.357622  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9913 16:51:13.361113  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9914 16:51:13.367684  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9915 16:51:13.370811  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9916 16:51:13.377417  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9917 16:51:13.380924  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9918 16:51:13.387716  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9919 16:51:13.388166  INFO:    [APUAPC] vio 0

 9920 16:51:13.394762  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9921 16:51:13.397804  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9922 16:51:13.401655  INFO:    [APUAPC] D0_APC_0: 0x400510

 9923 16:51:13.404531  INFO:    [APUAPC] D0_APC_1: 0x0

 9924 16:51:13.407670  INFO:    [APUAPC] D0_APC_2: 0x1540

 9925 16:51:13.411372  INFO:    [APUAPC] D0_APC_3: 0x0

 9926 16:51:13.414405  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9927 16:51:13.418041  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9928 16:51:13.421116  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9929 16:51:13.424363  INFO:    [APUAPC] D1_APC_3: 0x0

 9930 16:51:13.427788  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9931 16:51:13.430840  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9932 16:51:13.434118  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9933 16:51:13.438000  INFO:    [APUAPC] D2_APC_3: 0x0

 9934 16:51:13.441070  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9935 16:51:13.444414  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9936 16:51:13.447386  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9937 16:51:13.450885  INFO:    [APUAPC] D3_APC_3: 0x0

 9938 16:51:13.454264  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9939 16:51:13.457336  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9940 16:51:13.461174  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9941 16:51:13.461618  INFO:    [APUAPC] D4_APC_3: 0x0

 9942 16:51:13.467457  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9943 16:51:13.470643  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9944 16:51:13.473853  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9945 16:51:13.474279  INFO:    [APUAPC] D5_APC_3: 0x0

 9946 16:51:13.480455  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9947 16:51:13.483903  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9948 16:51:13.486907  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9949 16:51:13.487355  INFO:    [APUAPC] D6_APC_3: 0x0

 9950 16:51:13.493302  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9951 16:51:13.497138  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9952 16:51:13.500103  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9953 16:51:13.500530  INFO:    [APUAPC] D7_APC_3: 0x0

 9954 16:51:13.503270  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9955 16:51:13.506738  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9956 16:51:13.510200  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9957 16:51:13.513250  INFO:    [APUAPC] D8_APC_3: 0x0

 9958 16:51:13.516830  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9959 16:51:13.519791  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9960 16:51:13.523329  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9961 16:51:13.526681  INFO:    [APUAPC] D9_APC_3: 0x0

 9962 16:51:13.529850  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9963 16:51:13.533092  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9964 16:51:13.536476  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9965 16:51:13.539393  INFO:    [APUAPC] D10_APC_3: 0x0

 9966 16:51:13.542809  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9967 16:51:13.546011  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9968 16:51:13.553345  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9969 16:51:13.553769  INFO:    [APUAPC] D11_APC_3: 0x0

 9970 16:51:13.555968  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9971 16:51:13.562508  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9972 16:51:13.565593  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9973 16:51:13.566046  INFO:    [APUAPC] D12_APC_3: 0x0

 9974 16:51:13.572228  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9975 16:51:13.576033  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9976 16:51:13.578812  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9977 16:51:13.582372  INFO:    [APUAPC] D13_APC_3: 0x0

 9978 16:51:13.585555  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9979 16:51:13.588922  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9980 16:51:13.591978  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9981 16:51:13.595589  INFO:    [APUAPC] D14_APC_3: 0x0

 9982 16:51:13.598677  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9983 16:51:13.602372  INFO:    [APUAPC] D15_APC_1: 0xffffffff

 9984 16:51:13.605557  INFO:    [APUAPC] D15_APC_2: 0x3fffff

 9985 16:51:13.608906  INFO:    [APUAPC] D15_APC_3: 0x0

 9986 16:51:13.609337  INFO:    [APUAPC] APC_CON: 0x4

 9987 16:51:13.612227  INFO:    [NOCDAPC] D0_APC_0: 0x0

 9988 16:51:13.615818  INFO:    [NOCDAPC] D0_APC_1: 0x0

 9989 16:51:13.618523  INFO:    [NOCDAPC] D1_APC_0: 0x0

 9990 16:51:13.621840  INFO:    [NOCDAPC] D1_APC_1: 0xfff

 9991 16:51:13.624763  INFO:    [NOCDAPC] D2_APC_0: 0x0

 9992 16:51:13.628292  INFO:    [NOCDAPC] D2_APC_1: 0xfff

 9993 16:51:13.631436  INFO:    [NOCDAPC] D3_APC_0: 0x0

 9994 16:51:13.634554  INFO:    [NOCDAPC] D3_APC_1: 0xfff

 9995 16:51:13.637983  INFO:    [NOCDAPC] D4_APC_0: 0x0

 9996 16:51:13.641145  INFO:    [NOCDAPC] D4_APC_1: 0xfff

 9997 16:51:13.641228  INFO:    [NOCDAPC] D5_APC_0: 0x0

 9998 16:51:13.644757  INFO:    [NOCDAPC] D5_APC_1: 0xfff

 9999 16:51:13.647886  INFO:    [NOCDAPC] D6_APC_0: 0x0

10000 16:51:13.651089  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10001 16:51:13.654516  INFO:    [NOCDAPC] D7_APC_0: 0x0

10002 16:51:13.657577  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10003 16:51:13.661231  INFO:    [NOCDAPC] D8_APC_0: 0x0

10004 16:51:13.664239  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10005 16:51:13.667492  INFO:    [NOCDAPC] D9_APC_0: 0x0

10006 16:51:13.670698  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10007 16:51:13.674102  INFO:    [NOCDAPC] D10_APC_0: 0x0

10008 16:51:13.677668  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10009 16:51:13.681110  INFO:    [NOCDAPC] D11_APC_0: 0x0

10010 16:51:13.684296  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10011 16:51:13.684394  INFO:    [NOCDAPC] D12_APC_0: 0x0

10012 16:51:13.687280  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10013 16:51:13.690791  INFO:    [NOCDAPC] D13_APC_0: 0x0

10014 16:51:13.693710  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10015 16:51:13.697233  INFO:    [NOCDAPC] D14_APC_0: 0x0

10016 16:51:13.700440  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10017 16:51:13.703622  INFO:    [NOCDAPC] D15_APC_0: 0x0

10018 16:51:13.706920  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10019 16:51:13.710274  INFO:    [NOCDAPC] APC_CON: 0x4

10020 16:51:13.713852  INFO:    [APUAPC] set_apusys_apc done

10021 16:51:13.716922  INFO:    [DEVAPC] devapc_init done

10022 16:51:13.720175  INFO:    GICv3 without legacy support detected.

10023 16:51:13.723384  INFO:    ARM GICv3 driver initialized in EL3

10024 16:51:13.726874  INFO:    Maximum SPI INTID supported: 639

10025 16:51:13.733361  INFO:    BL31: Initializing runtime services

10026 16:51:13.736673  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10027 16:51:13.740223  INFO:    SPM: enable CPC mode

10028 16:51:13.746488  INFO:    mcdi ready for mcusys-off-idle and system suspend

10029 16:51:13.749637  INFO:    BL31: Preparing for EL3 exit to normal world

10030 16:51:13.753403  INFO:    Entry point address = 0x80000000

10031 16:51:13.756665  INFO:    SPSR = 0x8

10032 16:51:13.762272  

10033 16:51:13.762406  

10034 16:51:13.762496  

10035 16:51:13.765203  Starting depthcharge on Spherion...

10036 16:51:13.765278  

10037 16:51:13.765344  Wipe memory regions:

10038 16:51:13.765408  

10039 16:51:13.766075  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10040 16:51:13.766182  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10041 16:51:13.766270  Setting prompt string to ['asurada:']
10042 16:51:13.766419  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10043 16:51:13.768460  	[0x00000040000000, 0x00000054600000)

10044 16:51:13.891205  

10045 16:51:13.891365  	[0x00000054660000, 0x00000080000000)

10046 16:51:14.151743  

10047 16:51:14.151911  	[0x000000821a7280, 0x000000ffe64000)

10048 16:51:14.896942  

10049 16:51:14.897465  	[0x00000100000000, 0x00000240000000)

10050 16:51:16.787012  

10051 16:51:16.790135  Initializing XHCI USB controller at 0x11200000.

10052 16:51:17.827774  

10053 16:51:17.831042  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10054 16:51:17.831517  

10055 16:51:17.831886  

10056 16:51:17.832234  

10057 16:51:17.833046  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10059 16:51:17.934505  asurada: tftpboot 192.168.201.1 10576309/tftp-deploy-3kot0kcr/kernel/image.itb 10576309/tftp-deploy-3kot0kcr/kernel/cmdline 

10060 16:51:17.935174  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 16:51:17.935749  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10062 16:51:17.940272  tftpboot 192.168.201.1 10576309/tftp-deploy-3kot0kcr/kernel/image.itp-deploy-3kot0kcr/kernel/cmdline 

10063 16:51:17.940770  

10064 16:51:17.941117  Waiting for link

10065 16:51:18.100542  

10066 16:51:18.101209  R8152: Initializing

10067 16:51:18.101596  

10068 16:51:18.104326  Version 9 (ocp_data = 6010)

10069 16:51:18.104813  

10070 16:51:18.106998  R8152: Done initializing

10071 16:51:18.107421  

10072 16:51:18.107757  Adding net device

10073 16:51:19.976266  

10074 16:51:19.977134  done.

10075 16:51:19.977544  

10076 16:51:19.977898  MAC: 00:e0:4c:72:2d:d6

10077 16:51:19.978245  

10078 16:51:19.979392  Sending DHCP discover... done.

10079 16:51:19.979862  

10080 16:51:19.982790  Waiting for reply... done.

10081 16:51:19.983354  

10082 16:51:19.986223  Sending DHCP request... done.

10083 16:51:19.986744  

10084 16:51:20.002666  Waiting for reply... done.

10085 16:51:20.002853  

10086 16:51:20.002955  My ip is 192.168.201.21

10087 16:51:20.003040  

10088 16:51:20.006137  The DHCP server ip is 192.168.201.1

10089 16:51:20.006326  

10090 16:51:20.012806  TFTP server IP predefined by user: 192.168.201.1

10091 16:51:20.013003  

10092 16:51:20.018741  Bootfile predefined by user: 10576309/tftp-deploy-3kot0kcr/kernel/image.itb

10093 16:51:20.018977  

10094 16:51:20.022387  Sending tftp read request... done.

10095 16:51:20.022581  

10096 16:51:20.025890  Waiting for the transfer... 

10097 16:51:20.026063  

10098 16:51:20.346207  00000000 ################################################################

10099 16:51:20.346345  

10100 16:51:20.642039  00080000 ################################################################

10101 16:51:20.642176  

10102 16:51:20.938739  00100000 ################################################################

10103 16:51:20.938868  

10104 16:51:21.200080  00180000 ################################################################

10105 16:51:21.200206  

10106 16:51:21.452087  00200000 ################################################################

10107 16:51:21.452220  

10108 16:51:21.703674  00280000 ################################################################

10109 16:51:21.703805  

10110 16:51:21.958124  00300000 ################################################################

10111 16:51:21.958276  

10112 16:51:22.325805  00380000 ################################################################

10113 16:51:22.326315  

10114 16:51:22.702412  00400000 ################################################################

10115 16:51:22.702543  

10116 16:51:22.970801  00480000 ################################################################

10117 16:51:22.970944  

10118 16:51:23.222875  00500000 ################################################################

10119 16:51:23.223013  

10120 16:51:23.475395  00580000 ################################################################

10121 16:51:23.475535  

10122 16:51:23.728756  00600000 ################################################################

10123 16:51:23.728913  

10124 16:51:23.995228  00680000 ################################################################

10125 16:51:23.995373  

10126 16:51:24.281690  00700000 ################################################################

10127 16:51:24.281858  

10128 16:51:24.527744  00780000 ################################################################

10129 16:51:24.527884  

10130 16:51:24.799837  00800000 ################################################################

10131 16:51:24.799972  

10132 16:51:25.057325  00880000 ################################################################

10133 16:51:25.057453  

10134 16:51:25.306172  00900000 ################################################################

10135 16:51:25.306301  

10136 16:51:25.554808  00980000 ################################################################

10137 16:51:25.554943  

10138 16:51:25.806798  00a00000 ################################################################

10139 16:51:25.806934  

10140 16:51:26.053990  00a80000 ################################################################

10141 16:51:26.054146  

10142 16:51:26.298953  00b00000 ################################################################

10143 16:51:26.299097  

10144 16:51:26.543128  00b80000 ################################################################

10145 16:51:26.543269  

10146 16:51:26.813981  00c00000 ################################################################

10147 16:51:26.814134  

10148 16:51:27.086920  00c80000 ################################################################

10149 16:51:27.087067  

10150 16:51:27.354726  00d00000 ################################################################

10151 16:51:27.354866  

10152 16:51:27.623319  00d80000 ################################################################

10153 16:51:27.623447  

10154 16:51:27.909421  00e00000 ################################################################

10155 16:51:27.909572  

10156 16:51:28.199561  00e80000 ################################################################

10157 16:51:28.199715  

10158 16:51:28.488537  00f00000 ################################################################

10159 16:51:28.488705  

10160 16:51:28.777830  00f80000 ################################################################

10161 16:51:28.777961  

10162 16:51:29.048935  01000000 ################################################################

10163 16:51:29.049105  

10164 16:51:29.298026  01080000 ################################################################

10165 16:51:29.298186  

10166 16:51:29.549458  01100000 ################################################################

10167 16:51:29.549594  

10168 16:51:29.799290  01180000 ################################################################

10169 16:51:29.799457  

10170 16:51:30.073598  01200000 ################################################################

10171 16:51:30.073734  

10172 16:51:30.361105  01280000 ################################################################

10173 16:51:30.361242  

10174 16:51:30.647599  01300000 ################################################################

10175 16:51:30.647737  

10176 16:51:30.925314  01380000 ################################################################

10177 16:51:30.925486  

10178 16:51:31.218710  01400000 ################################################################

10179 16:51:31.218878  

10180 16:51:31.507411  01480000 ################################################################

10181 16:51:31.507538  

10182 16:51:31.790514  01500000 ################################################################

10183 16:51:31.790642  

10184 16:51:32.085077  01580000 ################################################################

10185 16:51:32.085229  

10186 16:51:32.372398  01600000 ################################################################

10187 16:51:32.372531  

10188 16:51:32.670964  01680000 ################################################################

10189 16:51:32.671122  

10190 16:51:32.953664  01700000 ################################################################

10191 16:51:32.953808  

10192 16:51:33.237390  01780000 ################################################################

10193 16:51:33.237552  

10194 16:51:33.508632  01800000 ################################################################

10195 16:51:33.508797  

10196 16:51:33.776996  01880000 ################################################################

10197 16:51:33.777128  

10198 16:51:34.078009  01900000 ################################################################

10199 16:51:34.078173  

10200 16:51:34.376465  01980000 ################################################################

10201 16:51:34.376599  

10202 16:51:34.665954  01a00000 ################################################################

10203 16:51:34.666084  

10204 16:51:34.942185  01a80000 ################################################################

10205 16:51:34.942315  

10206 16:51:35.215698  01b00000 ################################################################

10207 16:51:35.215854  

10208 16:51:35.467543  01b80000 ################################################################

10209 16:51:35.467693  

10210 16:51:35.738906  01c00000 ################################################################

10211 16:51:35.739032  

10212 16:51:35.993910  01c80000 ################################################################

10213 16:51:35.994075  

10214 16:51:36.250237  01d00000 ################################################################

10215 16:51:36.250443  

10216 16:51:36.517488  01d80000 ################################################################

10217 16:51:36.517671  

10218 16:51:36.795746  01e00000 ################################################################

10219 16:51:36.795884  

10220 16:51:37.080143  01e80000 ################################################################

10221 16:51:37.080316  

10222 16:51:37.348493  01f00000 ################################################################

10223 16:51:37.348666  

10224 16:51:37.595511  01f80000 ################################################################

10225 16:51:37.595660  

10226 16:51:37.840648  02000000 ################################################################

10227 16:51:37.840793  

10228 16:51:38.084025  02080000 ################################################################

10229 16:51:38.084175  

10230 16:51:38.326962  02100000 ################################################################

10231 16:51:38.327144  

10232 16:51:38.569359  02180000 ################################################################

10233 16:51:38.569537  

10234 16:51:38.818342  02200000 ################################################################

10235 16:51:38.818554  

10236 16:51:39.066176  02280000 ################################################################

10237 16:51:39.066353  

10238 16:51:39.336866  02300000 ################################################################

10239 16:51:39.337040  

10240 16:51:39.605102  02380000 ################################################################

10241 16:51:39.605278  

10242 16:51:39.878105  02400000 ################################################################

10243 16:51:39.878282  

10244 16:51:40.153818  02480000 ################################################################

10245 16:51:40.153995  

10246 16:51:40.421178  02500000 ################################################################

10247 16:51:40.421356  

10248 16:51:40.703911  02580000 ################################################################

10249 16:51:40.704084  

10250 16:51:40.953699  02600000 ################################################################

10251 16:51:40.953871  

10252 16:51:41.197570  02680000 ################################################################

10253 16:51:41.197740  

10254 16:51:41.441909  02700000 ################################################################

10255 16:51:41.442082  

10256 16:51:41.685365  02780000 ################################################################

10257 16:51:41.685512  

10258 16:51:41.931120  02800000 ################################################################

10259 16:51:41.931290  

10260 16:51:42.178400  02880000 ################################################################

10261 16:51:42.178538  

10262 16:51:42.433464  02900000 ################################################################

10263 16:51:42.433633  

10264 16:51:42.722032  02980000 ################################################################

10265 16:51:42.722206  

10266 16:51:42.975099  02a00000 ################################################################

10267 16:51:42.975266  

10268 16:51:43.238554  02a80000 ################################################################

10269 16:51:43.238707  

10270 16:51:43.500692  02b00000 ################################################################

10271 16:51:43.500833  

10272 16:51:43.745014  02b80000 ################################################################

10273 16:51:43.745157  

10274 16:51:44.015984  02c00000 ################################################################

10275 16:51:44.016158  

10276 16:51:44.260077  02c80000 ################################################################

10277 16:51:44.260224  

10278 16:51:44.505661  02d00000 ################################################################

10279 16:51:44.505808  

10280 16:51:44.771155  02d80000 ################################################################

10281 16:51:44.771326  

10282 16:51:45.037320  02e00000 ################################################################

10283 16:51:45.037490  

10284 16:51:45.314035  02e80000 ################################################################

10285 16:51:45.314208  

10286 16:51:45.578467  02f00000 ################################################################

10287 16:51:45.578617  

10288 16:51:45.853967  02f80000 ################################################################

10289 16:51:45.854121  

10290 16:51:46.132803  03000000 ################################################################

10291 16:51:46.132951  

10292 16:51:46.403147  03080000 ################################################################

10293 16:51:46.403297  

10294 16:51:46.647515  03100000 ################################################################

10295 16:51:46.647675  

10296 16:51:46.907093  03180000 ################################################################

10297 16:51:46.907242  

10298 16:51:47.182274  03200000 ################################################################

10299 16:51:47.182430  

10300 16:51:47.453952  03280000 ################################################################

10301 16:51:47.454103  

10302 16:51:47.711648  03300000 ################################################################

10303 16:51:47.711798  

10304 16:51:47.956294  03380000 ################################################################

10305 16:51:47.956444  

10306 16:51:48.208305  03400000 ################################################################

10307 16:51:48.208458  

10308 16:51:48.480086  03480000 ################################################################

10309 16:51:48.480233  

10310 16:51:48.748982  03500000 ################################################################

10311 16:51:48.749133  

10312 16:51:49.027593  03580000 ################################################################

10313 16:51:49.027743  

10314 16:51:49.305903  03600000 ################################################################

10315 16:51:49.306056  

10316 16:51:49.580868  03680000 ################################################################

10317 16:51:49.581024  

10318 16:51:49.857716  03700000 ################################################################

10319 16:51:49.857873  

10320 16:51:50.137231  03780000 ################################################################

10321 16:51:50.137381  

10322 16:51:50.397751  03800000 ################################################################

10323 16:51:50.397901  

10324 16:51:50.643467  03880000 ################################################################

10325 16:51:50.643619  

10326 16:51:50.892849  03900000 ################################################################

10327 16:51:50.893000  

10328 16:51:51.161444  03980000 ################################################################

10329 16:51:51.161595  

10330 16:51:51.422785  03a00000 ################################################################

10331 16:51:51.422944  

10332 16:51:51.689740  03a80000 ################################################################

10333 16:51:51.689896  

10334 16:51:51.973660  03b00000 ################################################################

10335 16:51:51.973802  

10336 16:51:52.267596  03b80000 ################################################################

10337 16:51:52.267738  

10338 16:51:52.552938  03c00000 ################################################################

10339 16:51:52.553070  

10340 16:51:52.844428  03c80000 ################################################################

10341 16:51:52.844560  

10342 16:51:53.127468  03d00000 ################################################################

10343 16:51:53.127612  

10344 16:51:53.402506  03d80000 ################################################################

10345 16:51:53.402647  

10346 16:51:53.678912  03e00000 ################################################################

10347 16:51:53.679041  

10348 16:51:53.967573  03e80000 ################################################################

10349 16:51:53.967733  

10350 16:51:54.261100  03f00000 ################################################################

10351 16:51:54.261234  

10352 16:51:54.546035  03f80000 ################################################################

10353 16:51:54.546167  

10354 16:51:54.797583  04000000 ################################################################

10355 16:51:54.797716  

10356 16:51:55.046348  04080000 ################################################################

10357 16:51:55.046501  

10358 16:51:55.302925  04100000 ################################################################

10359 16:51:55.303059  

10360 16:51:55.585330  04180000 ################################################################

10361 16:51:55.585463  

10362 16:51:55.856341  04200000 ################################################################

10363 16:51:55.856475  

10364 16:51:56.121093  04280000 ################################################################

10365 16:51:56.121229  

10366 16:51:56.367861  04300000 ################################################################

10367 16:51:56.367997  

10368 16:51:56.617349  04380000 ################################################################

10369 16:51:56.617483  

10370 16:51:56.867315  04400000 ################################################################

10371 16:51:56.867442  

10372 16:51:57.126976  04480000 ################################################################

10373 16:51:57.127113  

10374 16:51:57.392045  04500000 ################################################################

10375 16:51:57.392179  

10376 16:51:57.680226  04580000 ################################################################

10377 16:51:57.680387  

10378 16:51:57.969459  04600000 ################################################################

10379 16:51:57.969589  

10380 16:51:58.222664  04680000 ################################################################

10381 16:51:58.222796  

10382 16:51:58.506389  04700000 ################################################################

10383 16:51:58.506520  

10384 16:51:58.798705  04780000 ################################################################

10385 16:51:58.798840  

10386 16:51:59.077675  04800000 ################################################################

10387 16:51:59.077804  

10388 16:51:59.343086  04880000 ################################################################

10389 16:51:59.343218  

10390 16:51:59.627041  04900000 ################################################################

10391 16:51:59.627175  

10392 16:51:59.909972  04980000 ################################################################

10393 16:51:59.910102  

10394 16:52:00.165388  04a00000 ################################################################

10395 16:52:00.165523  

10396 16:52:00.422841  04a80000 ################################################################

10397 16:52:00.422972  

10398 16:52:00.676761  04b00000 ################################################################

10399 16:52:00.676891  

10400 16:52:00.926001  04b80000 ################################################################

10401 16:52:00.926127  

10402 16:52:01.173880  04c00000 ################################################################

10403 16:52:01.174012  

10404 16:52:01.460593  04c80000 ################################################################

10405 16:52:01.460727  

10406 16:52:01.708892  04d00000 ################################################################

10407 16:52:01.709021  

10408 16:52:01.964681  04d80000 ################################################################

10409 16:52:01.964811  

10410 16:52:02.239438  04e00000 ################################################################

10411 16:52:02.239571  

10412 16:52:02.535666  04e80000 ################################################################

10413 16:52:02.535789  

10414 16:52:02.832750  04f00000 ################################################################

10415 16:52:02.832881  

10416 16:52:03.101399  04f80000 ################################################################

10417 16:52:03.101527  

10418 16:52:03.370748  05000000 ################################################################

10419 16:52:03.370885  

10420 16:52:03.661461  05080000 ################################################################

10421 16:52:03.661596  

10422 16:52:03.914203  05100000 ################################################################

10423 16:52:03.914358  

10424 16:52:04.170614  05180000 ################################################################

10425 16:52:04.170741  

10426 16:52:04.428852  05200000 ################################################################

10427 16:52:04.428984  

10428 16:52:04.716007  05280000 ################################################################

10429 16:52:04.716154  

10430 16:52:04.993939  05300000 ################################################################

10431 16:52:04.994074  

10432 16:52:05.253168  05380000 ################################################################

10433 16:52:05.253329  

10434 16:52:05.525973  05400000 ################################################################

10435 16:52:05.526110  

10436 16:52:05.787571  05480000 ################################################################

10437 16:52:05.787707  

10438 16:52:06.035381  05500000 ################################################################

10439 16:52:06.035513  

10440 16:52:06.286530  05580000 ################################################################

10441 16:52:06.286667  

10442 16:52:06.562342  05600000 ################################################################

10443 16:52:06.562515  

10444 16:52:06.828645  05680000 ################################################################

10445 16:52:06.828782  

10446 16:52:07.080145  05700000 ################################################################

10447 16:52:07.080274  

10448 16:52:07.333267  05780000 ################################################################

10449 16:52:07.333389  

10450 16:52:07.610031  05800000 ################################################################

10451 16:52:07.610162  

10452 16:52:07.858246  05880000 ################################################################

10453 16:52:07.858446  

10454 16:52:08.108308  05900000 ################################################################

10455 16:52:08.108465  

10456 16:52:08.373806  05980000 ################################################################

10457 16:52:08.373962  

10458 16:52:08.632712  05a00000 ################################################################

10459 16:52:08.632870  

10460 16:52:08.883950  05a80000 ################################################################

10461 16:52:08.884083  

10462 16:52:09.147085  05b00000 ################################################################

10463 16:52:09.147240  

10464 16:52:09.396044  05b80000 ################################################################

10465 16:52:09.396174  

10466 16:52:09.650852  05c00000 ################################################################

10467 16:52:09.651000  

10468 16:52:09.912129  05c80000 ################################################################

10469 16:52:09.912261  

10470 16:52:10.192086  05d00000 ################################################################

10471 16:52:10.192218  

10472 16:52:10.473732  05d80000 ################################################################

10473 16:52:10.473865  

10474 16:52:10.751375  05e00000 ################################################################

10475 16:52:10.751507  

10476 16:52:11.026084  05e80000 ################################################################

10477 16:52:11.026215  

10478 16:52:11.286369  05f00000 ################################################################

10479 16:52:11.286500  

10480 16:52:11.540266  05f80000 ################################################################

10481 16:52:11.540424  

10482 16:52:11.788502  06000000 ################################################################

10483 16:52:11.788640  

10484 16:52:12.041284  06080000 ################################################################

10485 16:52:12.041416  

10486 16:52:12.301190  06100000 ################################################################

10487 16:52:12.301316  

10488 16:52:12.550208  06180000 ################################################################

10489 16:52:12.550342  

10490 16:52:12.801869  06200000 ################################################################

10491 16:52:12.802000  

10492 16:52:13.075883  06280000 ################################################################

10493 16:52:13.076012  

10494 16:52:13.362153  06300000 ################################################################

10495 16:52:13.362311  

10496 16:52:13.619857  06380000 ################################################################

10497 16:52:13.619988  

10498 16:52:13.872849  06400000 ################################################################

10499 16:52:13.872981  

10500 16:52:14.126676  06480000 ################################################################

10501 16:52:14.126834  

10502 16:52:14.393205  06500000 ################################################################

10503 16:52:14.393333  

10504 16:52:14.656896  06580000 ################################################################

10505 16:52:14.657025  

10506 16:52:14.907334  06600000 ################################################################

10507 16:52:14.907463  

10508 16:52:15.160813  06680000 ################################################################

10509 16:52:15.160946  

10510 16:52:15.297860  06700000 #################################### done.

10511 16:52:15.297979  

10512 16:52:15.300988  The bootfile was 108290626 bytes long.

10513 16:52:15.301107  

10514 16:52:15.304899  Sending tftp read request... done.

10515 16:52:15.304995  

10516 16:52:15.308026  Waiting for the transfer... 

10517 16:52:15.308122  

10518 16:52:15.308219  00000000 # done.

10519 16:52:15.308335  

10520 16:52:15.314330  Command line loaded dynamically from TFTP file: 10576309/tftp-deploy-3kot0kcr/kernel/cmdline

10521 16:52:15.317593  

10522 16:52:15.327462  The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10523 16:52:15.327673  

10524 16:52:15.327797  Loading FIT.

10525 16:52:15.327906  

10526 16:52:15.330715  Image ramdisk-1 has 98158195 bytes.

10527 16:52:15.330874  

10528 16:52:15.334021  Image fdt-1 has 46924 bytes.

10529 16:52:15.334198  

10530 16:52:15.337596  Image kernel-1 has 10083474 bytes.

10531 16:52:15.337854  

10532 16:52:15.347319  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10533 16:52:15.347649  

10534 16:52:15.363848  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10535 16:52:15.364649  

10536 16:52:15.371083  Choosing best match conf-1 for compat google,spherion-rev2.

10537 16:52:15.371553  

10538 16:52:15.377312  Connected to device vid:did:rid of 1ae0:0028:00

10539 16:52:15.385267  

10540 16:52:15.388323  tpm_get_response: command 0x17b, return code 0x0

10541 16:52:15.388798  

10542 16:52:15.392146  ec_init: CrosEC protocol v3 supported (256, 248)

10543 16:52:15.396100  

10544 16:52:15.399515  tpm_cleanup: add release locality here.

10545 16:52:15.399985  

10546 16:52:15.400363  Shutting down all USB controllers.

10547 16:52:15.402941  

10548 16:52:15.403523  Removing current net device

10549 16:52:15.403904  

10550 16:52:15.409634  Exiting depthcharge with code 4 at timestamp: 90959266

10551 16:52:15.410106  

10552 16:52:15.412812  LZMA decompressing kernel-1 to 0x821a6718

10553 16:52:15.413277  

10554 16:52:15.416210  LZMA decompressing kernel-1 to 0x40000000

10555 16:52:16.682098  

10556 16:52:16.682727  jumping to kernel

10557 16:52:16.684508  end: 2.2.4 bootloader-commands (duration 00:01:03) [common]
10558 16:52:16.685041  start: 2.2.5 auto-login-action (timeout 00:03:22) [common]
10559 16:52:16.685459  Setting prompt string to ['Linux version [0-9]']
10560 16:52:16.685843  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10561 16:52:16.686222  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10562 16:52:16.763529  

10563 16:52:16.767016  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10564 16:52:16.770740  start: 2.2.5.1 login-action (timeout 00:03:22) [common]
10565 16:52:16.771240  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10566 16:52:16.771753  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10567 16:52:16.772301  Using line separator: #'\n'#
10568 16:52:16.772653  No login prompt set.
10569 16:52:16.772998  Parsing kernel messages
10570 16:52:16.773314  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10571 16:52:16.773965  [login-action] Waiting for messages, (timeout 00:03:22)
10572 16:52:16.790038  [    0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun  3 16:27:28 UTC 2023

10573 16:52:16.793104  [    0.000000] random: crng init done

10574 16:52:16.799657  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10575 16:52:16.800102  [    0.000000] efi: UEFI not found.

10576 16:52:16.809630  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10577 16:52:16.816180  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10578 16:52:16.826294  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10579 16:52:16.836545  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10580 16:52:16.842977  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10581 16:52:16.849495  [    0.000000] printk: bootconsole [mtk8250] enabled

10582 16:52:16.856481  [    0.000000] NUMA: No NUMA configuration found

10583 16:52:16.862731  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10584 16:52:16.866326  [    0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]

10585 16:52:16.869562  [    0.000000] Zone ranges:

10586 16:52:16.875767  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10587 16:52:16.879515  [    0.000000]   DMA32    empty

10588 16:52:16.885773  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10589 16:52:16.889738  [    0.000000] Movable zone start for each node

10590 16:52:16.892334  [    0.000000] Early memory node ranges

10591 16:52:16.899198  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10592 16:52:16.905508  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10593 16:52:16.912333  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10594 16:52:16.918768  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10595 16:52:16.922401  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10596 16:52:16.928738  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10597 16:52:16.987403  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10598 16:52:16.993830  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10599 16:52:17.000617  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10600 16:52:17.003551  [    0.000000] psci: probing for conduit method from DT.

10601 16:52:17.010304  [    0.000000] psci: PSCIv1.1 detected in firmware.

10602 16:52:17.013760  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10603 16:52:17.020213  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10604 16:52:17.023589  [    0.000000] psci: SMC Calling Convention v1.2

10605 16:52:17.030113  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10606 16:52:17.033820  [    0.000000] Detected VIPT I-cache on CPU0

10607 16:52:17.039891  [    0.000000] CPU features: detected: GIC system register CPU interface

10608 16:52:17.046653  [    0.000000] CPU features: detected: Virtualization Host Extensions

10609 16:52:17.053574  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10610 16:52:17.060138  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10611 16:52:17.070076  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10612 16:52:17.076397  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10613 16:52:17.079584  [    0.000000] alternatives: applying boot alternatives

10614 16:52:17.086700  [    0.000000] Fallback order for Node 0: 0 

10615 16:52:17.092935  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10616 16:52:17.096589  [    0.000000] Policy zone: Normal

10617 16:52:17.106024  [    0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10618 16:52:17.119150  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10619 16:52:17.129371  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10620 16:52:17.139454  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10621 16:52:17.146145  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10622 16:52:17.149347  <6>[    0.000000] software IO TLB: area num 8.

10623 16:52:17.206635  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10624 16:52:17.355781  <6>[    0.000000] Memory: 7877084K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 475684K reserved, 32768K cma-reserved)

10625 16:52:17.362634  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10626 16:52:17.368860  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10627 16:52:17.372491  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10628 16:52:17.378831  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10629 16:52:17.386090  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10630 16:52:17.389153  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10631 16:52:17.399009  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10632 16:52:17.405432  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10633 16:52:17.412044  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10634 16:52:17.418605  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10635 16:52:17.422088  <6>[    0.000000] GICv3: 608 SPIs implemented

10636 16:52:17.425375  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10637 16:52:17.431968  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10638 16:52:17.435305  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10639 16:52:17.442114  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10640 16:52:17.455005  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10641 16:52:17.468321  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10642 16:52:17.474877  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10643 16:52:17.482339  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10644 16:52:17.495832  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10645 16:52:17.501964  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10646 16:52:17.508769  <6>[    0.009176] Console: colour dummy device 80x25

10647 16:52:17.518478  <6>[    0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10648 16:52:17.525262  <6>[    0.024411] pid_max: default: 32768 minimum: 301

10649 16:52:17.528446  <6>[    0.029284] LSM: Security Framework initializing

10650 16:52:17.535604  <6>[    0.034253] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10651 16:52:17.545221  <6>[    0.042114] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10652 16:52:17.555003  <6>[    0.051534] cblist_init_generic: Setting adjustable number of callback queues.

10653 16:52:17.561733  <6>[    0.059036] cblist_init_generic: Setting shift to 3 and lim to 1.

10654 16:52:17.564792  <6>[    0.065374] cblist_init_generic: Setting shift to 3 and lim to 1.

10655 16:52:17.571237  <6>[    0.071821] rcu: Hierarchical SRCU implementation.

10656 16:52:17.578125  <6>[    0.076865] rcu: 	Max phase no-delay instances is 1000.

10657 16:52:17.584640  <6>[    0.083885] EFI services will not be available.

10658 16:52:17.587910  <6>[    0.088863] smp: Bringing up secondary CPUs ...

10659 16:52:17.596313  <6>[    0.093943] Detected VIPT I-cache on CPU1

10660 16:52:17.602487  <6>[    0.094015] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10661 16:52:17.609309  <6>[    0.094044] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10662 16:52:17.613140  <6>[    0.094386] Detected VIPT I-cache on CPU2

10663 16:52:17.619260  <6>[    0.094439] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10664 16:52:17.629379  <6>[    0.094456] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10665 16:52:17.632242  <6>[    0.094718] Detected VIPT I-cache on CPU3

10666 16:52:17.639006  <6>[    0.094766] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10667 16:52:17.646037  <6>[    0.094780] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10668 16:52:17.649257  <6>[    0.095086] CPU features: detected: Spectre-v4

10669 16:52:17.655417  <6>[    0.095092] CPU features: detected: Spectre-BHB

10670 16:52:17.659012  <6>[    0.095098] Detected PIPT I-cache on CPU4

10671 16:52:17.665390  <6>[    0.095158] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10672 16:52:17.671782  <6>[    0.095175] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10673 16:52:17.678338  <6>[    0.095472] Detected PIPT I-cache on CPU5

10674 16:52:17.685201  <6>[    0.095535] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10675 16:52:17.692054  <6>[    0.095551] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10676 16:52:17.694915  <6>[    0.095833] Detected PIPT I-cache on CPU6

10677 16:52:17.701749  <6>[    0.095898] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10678 16:52:17.708405  <6>[    0.095914] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10679 16:52:17.715274  <6>[    0.096211] Detected PIPT I-cache on CPU7

10680 16:52:17.721498  <6>[    0.096275] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10681 16:52:17.728407  <6>[    0.096291] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10682 16:52:17.731513  <6>[    0.096337] smp: Brought up 1 node, 8 CPUs

10683 16:52:17.738344  <6>[    0.237690] SMP: Total of 8 processors activated.

10684 16:52:17.741566  <6>[    0.242611] CPU features: detected: 32-bit EL0 Support

10685 16:52:17.751282  <6>[    0.247973] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10686 16:52:17.757866  <6>[    0.256773] CPU features: detected: Common not Private translations

10687 16:52:17.764170  <6>[    0.263289] CPU features: detected: CRC32 instructions

10688 16:52:17.767529  <6>[    0.268640] CPU features: detected: RCpc load-acquire (LDAPR)

10689 16:52:17.774301  <6>[    0.274637] CPU features: detected: LSE atomic instructions

10690 16:52:17.780715  <6>[    0.280418] CPU features: detected: Privileged Access Never

10691 16:52:17.787103  <6>[    0.286197] CPU features: detected: RAS Extension Support

10692 16:52:17.793845  <6>[    0.291806] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10693 16:52:17.797319  <6>[    0.299025] CPU: All CPU(s) started at EL2

10694 16:52:17.803655  <6>[    0.303341] alternatives: applying system-wide alternatives

10695 16:52:17.813520  <6>[    0.314095] devtmpfs: initialized

10696 16:52:17.829174  <6>[    0.322881] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10697 16:52:17.835578  <6>[    0.332846] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10698 16:52:17.842493  <6>[    0.340773] pinctrl core: initialized pinctrl subsystem

10699 16:52:17.845705  <6>[    0.347429] DMI not present or invalid.

10700 16:52:17.851993  <6>[    0.351849] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10701 16:52:17.862200  <6>[    0.358745] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10702 16:52:17.868446  <6>[    0.366328] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10703 16:52:17.878506  <6>[    0.374543] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10704 16:52:17.881645  <6>[    0.382794] audit: initializing netlink subsys (disabled)

10705 16:52:17.892367  <5>[    0.388499] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1

10706 16:52:17.898327  <6>[    0.389212] thermal_sys: Registered thermal governor 'step_wise'

10707 16:52:17.904824  <6>[    0.396467] thermal_sys: Registered thermal governor 'power_allocator'

10708 16:52:17.908298  <6>[    0.402725] cpuidle: using governor menu

10709 16:52:17.914398  <6>[    0.413691] NET: Registered PF_QIPCRTR protocol family

10710 16:52:17.921623  <6>[    0.419208] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10711 16:52:17.928367  <6>[    0.426311] ASID allocator initialised with 32768 entries

10712 16:52:17.931778  <6>[    0.432890] Serial: AMBA PL011 UART driver

10713 16:52:17.940876  <4>[    0.441581] Trying to register duplicate clock ID: 134

10714 16:52:17.994817  <6>[    0.498663] KASLR enabled

10715 16:52:18.009230  <6>[    0.506327] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10716 16:52:18.015765  <6>[    0.513343] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10717 16:52:18.022123  <6>[    0.519833] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10718 16:52:18.029115  <6>[    0.526840] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10719 16:52:18.035365  <6>[    0.533327] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10720 16:52:18.042461  <6>[    0.540335] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10721 16:52:18.048320  <6>[    0.546822] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10722 16:52:18.054911  <6>[    0.553829] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10723 16:52:18.058287  <6>[    0.561310] ACPI: Interpreter disabled.

10724 16:52:18.067854  <6>[    0.567745] iommu: Default domain type: Translated 

10725 16:52:18.074059  <6>[    0.572859] iommu: DMA domain TLB invalidation policy: strict mode 

10726 16:52:18.077436  <5>[    0.579522] SCSI subsystem initialized

10727 16:52:18.084308  <6>[    0.583758] usbcore: registered new interface driver usbfs

10728 16:52:18.090456  <6>[    0.589490] usbcore: registered new interface driver hub

10729 16:52:18.093497  <6>[    0.595045] usbcore: registered new device driver usb

10730 16:52:18.100627  <6>[    0.601145] pps_core: LinuxPPS API ver. 1 registered

10731 16:52:18.110712  <6>[    0.606339] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10732 16:52:18.113839  <6>[    0.615686] PTP clock support registered

10733 16:52:18.117129  <6>[    0.619925] EDAC MC: Ver: 3.0.0

10734 16:52:18.124660  <6>[    0.625123] FPGA manager framework

10735 16:52:18.131181  <6>[    0.628802] Advanced Linux Sound Architecture Driver Initialized.

10736 16:52:18.134120  <6>[    0.635575] vgaarb: loaded

10737 16:52:18.141093  <6>[    0.638745] clocksource: Switched to clocksource arch_sys_counter

10738 16:52:18.144566  <5>[    0.645194] VFS: Disk quotas dquot_6.6.0

10739 16:52:18.151060  <6>[    0.649382] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10740 16:52:18.154305  <6>[    0.656573] pnp: PnP ACPI: disabled

10741 16:52:18.162859  <6>[    0.663312] NET: Registered PF_INET protocol family

10742 16:52:18.173088  <6>[    0.668913] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10743 16:52:18.184304  <6>[    0.681217] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10744 16:52:18.193823  <6>[    0.690036] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10745 16:52:18.200234  <6>[    0.698007] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10746 16:52:18.210645  <6>[    0.706709] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10747 16:52:18.216829  <6>[    0.716454] TCP: Hash tables configured (established 65536 bind 65536)

10748 16:52:18.223450  <6>[    0.723313] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10749 16:52:18.233224  <6>[    0.730512] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10750 16:52:18.239899  <6>[    0.738212] NET: Registered PF_UNIX/PF_LOCAL protocol family

10751 16:52:18.246285  <6>[    0.744304] RPC: Registered named UNIX socket transport module.

10752 16:52:18.249955  <6>[    0.750453] RPC: Registered udp transport module.

10753 16:52:18.256263  <6>[    0.755384] RPC: Registered tcp transport module.

10754 16:52:18.262849  <6>[    0.760316] RPC: Registered tcp NFSv4.1 backchannel transport module.

10755 16:52:18.266022  <6>[    0.766986] PCI: CLS 0 bytes, default 64

10756 16:52:18.269908  <6>[    0.771376] Unpacking initramfs...

10757 16:52:18.293549  <6>[    0.790851] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10758 16:52:18.303486  <6>[    0.799520] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10759 16:52:18.306679  <6>[    0.808368] kvm [1]: IPA Size Limit: 40 bits

10760 16:52:18.313302  <6>[    0.812891] kvm [1]: GICv3: no GICV resource entry

10761 16:52:18.316707  <6>[    0.817915] kvm [1]: disabling GICv2 emulation

10762 16:52:18.323035  <6>[    0.822604] kvm [1]: GIC system register CPU interface enabled

10763 16:52:18.327093  <6>[    0.828769] kvm [1]: vgic interrupt IRQ18

10764 16:52:18.333309  <6>[    0.833136] kvm [1]: VHE mode initialized successfully

10765 16:52:18.339764  <5>[    0.839635] Initialise system trusted keyrings

10766 16:52:18.346516  <6>[    0.844423] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10767 16:52:18.353821  <6>[    0.854438] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10768 16:52:18.360550  <5>[    0.860830] NFS: Registering the id_resolver key type

10769 16:52:18.363578  <5>[    0.866135] Key type id_resolver registered

10770 16:52:18.370650  <5>[    0.870552] Key type id_legacy registered

10771 16:52:18.377593  <6>[    0.874834] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10772 16:52:18.383717  <6>[    0.881758] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10773 16:52:18.390158  <6>[    0.889481] 9p: Installing v9fs 9p2000 file system support

10774 16:52:18.426873  <5>[    0.927280] Key type asymmetric registered

10775 16:52:18.429963  <5>[    0.931614] Asymmetric key parser 'x509' registered

10776 16:52:18.440012  <6>[    0.936758] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10777 16:52:18.443092  <6>[    0.944401] io scheduler mq-deadline registered

10778 16:52:18.446443  <6>[    0.949182] io scheduler kyber registered

10779 16:52:18.465395  <6>[    0.966148] EINJ: ACPI disabled.

10780 16:52:18.497616  <4>[    0.991699] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10781 16:52:18.507373  <4>[    1.002353] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10782 16:52:18.523020  <6>[    1.023107] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10783 16:52:18.530899  <6>[    1.031206] printk: console [ttyS0] disabled

10784 16:52:18.558541  <6>[    1.055851] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10785 16:52:18.565267  <6>[    1.065327] printk: console [ttyS0] enabled

10786 16:52:18.569056  <6>[    1.065327] printk: console [ttyS0] enabled

10787 16:52:18.575280  <6>[    1.074220] printk: bootconsole [mtk8250] disabled

10788 16:52:18.578644  <6>[    1.074220] printk: bootconsole [mtk8250] disabled

10789 16:52:18.585484  <6>[    1.085442] SuperH (H)SCI(F) driver initialized

10790 16:52:18.588491  <6>[    1.090721] msm_serial: driver initialized

10791 16:52:18.602620  <6>[    1.099627] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10792 16:52:18.612386  <6>[    1.108173] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10793 16:52:18.618759  <6>[    1.116716] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10794 16:52:18.629253  <6>[    1.125344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10795 16:52:18.638682  <6>[    1.134048] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10796 16:52:18.645582  <6>[    1.142771] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10797 16:52:18.655155  <6>[    1.151314] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10798 16:52:18.662159  <6>[    1.160117] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10799 16:52:18.671680  <6>[    1.168662] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10800 16:52:18.683458  <6>[    1.184186] loop: module loaded

10801 16:52:18.690430  <6>[    1.190177] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10802 16:52:18.712489  <4>[    1.213110] mtk-pmic-keys: Failed to locate of_node [id: -1]

10803 16:52:18.719382  <6>[    1.220025] megasas: 07.719.03.00-rc1

10804 16:52:18.729423  <6>[    1.229697] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10805 16:52:18.738103  <6>[    1.238111] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10806 16:52:18.754485  <6>[    1.254551] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10807 16:52:18.813902  <6>[    1.307734] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7

10808 16:52:22.252018  <6>[    4.752728] Freeing initrd memory: 95852K

10809 16:52:22.261788  <6>[    4.762992] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10810 16:52:22.273231  <6>[    4.773892] tun: Universal TUN/TAP device driver, 1.6

10811 16:52:22.276274  <6>[    4.779958] thunder_xcv, ver 1.0

10812 16:52:22.279187  <6>[    4.783465] thunder_bgx, ver 1.0

10813 16:52:22.282687  <6>[    4.786960] nicpf, ver 1.0

10814 16:52:22.293423  <6>[    4.790957] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10815 16:52:22.296629  <6>[    4.798432] hns3: Copyright (c) 2017 Huawei Corporation.

10816 16:52:22.303045  <6>[    4.804018] hclge is initializing

10817 16:52:22.306418  <6>[    4.807599] e1000: Intel(R) PRO/1000 Network Driver

10818 16:52:22.313248  <6>[    4.812727] e1000: Copyright (c) 1999-2006 Intel Corporation.

10819 16:52:22.316537  <6>[    4.818745] e1000e: Intel(R) PRO/1000 Network Driver

10820 16:52:22.323191  <6>[    4.823961] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10821 16:52:22.329750  <6>[    4.830145] igb: Intel(R) Gigabit Ethernet Network Driver

10822 16:52:22.336496  <6>[    4.835794] igb: Copyright (c) 2007-2014 Intel Corporation.

10823 16:52:22.343031  <6>[    4.841633] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10824 16:52:22.349591  <6>[    4.848150] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10825 16:52:22.352758  <6>[    4.854606] sky2: driver version 1.30

10826 16:52:22.360029  <6>[    4.859581] VFIO - User Level meta-driver version: 0.3

10827 16:52:22.366656  <6>[    4.867701] usbcore: registered new interface driver usb-storage

10828 16:52:22.373689  <6>[    4.874145] usbcore: registered new device driver onboard-usb-hub

10829 16:52:22.381961  <6>[    4.883137] mt6397-rtc mt6359-rtc: registered as rtc0

10830 16:52:22.392177  <6>[    4.888603] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:52:22 UTC (1685811142)

10831 16:52:22.395439  <6>[    4.898164] i2c_dev: i2c /dev entries driver

10832 16:52:22.411884  <6>[    4.909790] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10833 16:52:22.419140  <6>[    4.920003] sdhci: Secure Digital Host Controller Interface driver

10834 16:52:22.425820  <6>[    4.926442] sdhci: Copyright(c) Pierre Ossman

10835 16:52:22.432092  <6>[    4.931840] Synopsys Designware Multimedia Card Interface Driver

10836 16:52:22.435590  <6>[    4.938459] mmc0: CQHCI version 5.10

10837 16:52:22.442725  <6>[    4.938992] sdhci-pltfm: SDHCI platform and OF driver helper

10838 16:52:22.450198  <6>[    4.950300] ledtrig-cpu: registered to indicate activity on CPUs

10839 16:52:22.460104  <6>[    4.957649] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10840 16:52:22.466347  <6>[    4.965033] usbcore: registered new interface driver usbhid

10841 16:52:22.469734  <6>[    4.970860] usbhid: USB HID core driver

10842 16:52:22.476468  <6>[    4.975109] spi_master spi0: will run message pump with realtime priority

10843 16:52:22.519850  <6>[    5.014224] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10844 16:52:22.538736  <6>[    5.029406] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10845 16:52:22.542422  <6>[    5.042971] mmc0: Command Queue Engine enabled

10846 16:52:22.549007  <6>[    5.047730] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10847 16:52:22.555741  <6>[    5.054651] cros-ec-spi spi0.0: Chrome EC device registered

10848 16:52:22.558568  <6>[    5.055001] mmcblk0: mmc0:0001 DA4128 116 GiB 

10849 16:52:22.568943  <6>[    5.069941]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10850 16:52:22.576283  <6>[    5.077257] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10851 16:52:22.583195  <6>[    5.083124] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10852 16:52:22.589341  <6>[    5.089034] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10853 16:52:22.606000  <6>[    5.103873] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10854 16:52:22.614837  <6>[    5.115232] NET: Registered PF_PACKET protocol family

10855 16:52:22.617676  <6>[    5.120657] 9pnet: Installing 9P2000 support

10856 16:52:22.624368  <5>[    5.125232] Key type dns_resolver registered

10857 16:52:22.627693  <6>[    5.130241] registered taskstats version 1

10858 16:52:22.634306  <5>[    5.134636] Loading compiled-in X.509 certificates

10859 16:52:22.668403  <4>[    5.162565] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10860 16:52:22.677988  <4>[    5.173246] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10861 16:52:22.688063  <3>[    5.185772] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10862 16:52:22.700683  <6>[    5.201256] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10863 16:52:22.707248  <6>[    5.208035] xhci-mtk 11200000.usb: xHCI Host Controller

10864 16:52:22.714300  <6>[    5.213536] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10865 16:52:22.723686  <6>[    5.221387] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10866 16:52:22.730535  <6>[    5.230857] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10867 16:52:22.737243  <6>[    5.237054] xhci-mtk 11200000.usb: xHCI Host Controller

10868 16:52:22.743808  <6>[    5.242572] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10869 16:52:22.750707  <6>[    5.250235] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10870 16:52:22.757010  <6>[    5.258135] hub 1-0:1.0: USB hub found

10871 16:52:22.760817  <6>[    5.262190] hub 1-0:1.0: 1 port detected

10872 16:52:22.770580  <6>[    5.266540] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10873 16:52:22.773820  <6>[    5.275353] hub 2-0:1.0: USB hub found

10874 16:52:22.777038  <6>[    5.279394] hub 2-0:1.0: 1 port detected

10875 16:52:22.785255  <6>[    5.286245] mtk-msdc 11f70000.mmc: Got CD GPIO

10876 16:52:22.802809  <6>[    5.300023] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10877 16:52:22.809208  <6>[    5.308155] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10878 16:52:22.818907  <4>[    5.316142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10879 16:52:22.829223  <6>[    5.325851] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10880 16:52:22.835502  <6>[    5.333939] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10881 16:52:22.845520  <6>[    5.342010] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10882 16:52:22.851831  <6>[    5.349929] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10883 16:52:22.858935  <6>[    5.357787] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10884 16:52:22.868687  <6>[    5.365618] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10885 16:52:22.879011  <6>[    5.376403] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10886 16:52:22.888746  <6>[    5.384766] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10887 16:52:22.895474  <6>[    5.393187] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10888 16:52:22.905321  <6>[    5.401537] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10889 16:52:22.911585  <6>[    5.409905] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10890 16:52:22.921858  <6>[    5.418251] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10891 16:52:22.928330  <6>[    5.426620] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10892 16:52:22.938578  <6>[    5.434965] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10893 16:52:22.945033  <6>[    5.443329] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10894 16:52:22.954862  <6>[    5.451673] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10895 16:52:22.961115  <6>[    5.460016] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10896 16:52:22.971285  <6>[    5.468360] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10897 16:52:22.978285  <6>[    5.476706] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10898 16:52:22.988187  <6>[    5.485050] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10899 16:52:22.994610  <6>[    5.493391] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10900 16:52:23.001671  <6>[    5.502267] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10901 16:52:23.008560  <6>[    5.509707] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10902 16:52:23.015868  <6>[    5.516741] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10903 16:52:23.026415  <6>[    5.523883] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10904 16:52:23.032571  <6>[    5.531185] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10905 16:52:23.042584  <6>[    5.538082] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10906 16:52:23.049724  <6>[    5.547225] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10907 16:52:23.059147  <6>[    5.556414] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10908 16:52:23.069297  <6>[    5.565836] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10909 16:52:23.078833  <6>[    5.575313] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10910 16:52:23.089080  <6>[    5.584787] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10911 16:52:23.098891  <6>[    5.593914] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10912 16:52:23.105278  <6>[    5.603388] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10913 16:52:23.115401  <6>[    5.612517] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10914 16:52:23.125241  <6>[    5.621824] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10915 16:52:23.135096  <6>[    5.632021] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10916 16:52:23.145919  <6>[    5.643470] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10917 16:52:23.193441  <6>[    5.691018] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10918 16:52:23.347486  <6>[    5.848429] hub 1-1:1.0: USB hub found

10919 16:52:23.350467  <6>[    5.852875] hub 1-1:1.0: 4 ports detected

10920 16:52:23.473592  <6>[    5.971228] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10921 16:52:23.500609  <6>[    6.001405] hub 2-1:1.0: USB hub found

10922 16:52:23.503964  <6>[    6.005865] hub 2-1:1.0: 3 ports detected

10923 16:52:23.673106  <6>[    6.171014] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10924 16:52:23.806197  <6>[    6.307191] hub 1-1.4:1.0: USB hub found

10925 16:52:23.809456  <6>[    6.311869] hub 1-1.4:1.0: 2 ports detected

10926 16:52:23.885831  <6>[    6.383265] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10927 16:52:24.104868  <6>[    6.603016] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10928 16:52:24.297425  <6>[    6.795016] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10929 16:52:35.426091  <6>[   17.931644] ALSA device list:

10930 16:52:35.432397  <6>[   17.934891]   No soundcards found.

10931 16:52:35.444870  <6>[   17.947318] Freeing unused kernel memory: 8384K

10932 16:52:35.447898  <6>[   17.952245] Run /init as init process

10933 16:52:35.478427  <6>[   17.980818] NET: Registered PF_INET6 protocol family

10934 16:52:35.484937  <6>[   17.986904] Segment Routing with IPv6

10935 16:52:35.488116  <6>[   17.990835] In-situ OAM (IOAM) with IPv6

10936 16:52:35.522307  <30>[   18.005056] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10937 16:52:35.526176  <30>[   18.028877] systemd[1]: Detected architecture arm64.

10938 16:52:35.526839  

10939 16:52:35.531993  Welcome to Debian GNU/Linux 11 (bullseye)!

10940 16:52:35.532611  

10941 16:52:35.544696  <30>[   18.047082] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10942 16:52:35.698930  <30>[   18.197854] systemd[1]: Queued start job for default target Graphical Interface.

10943 16:52:35.721927  <30>[   18.224205] systemd[1]: Created slice system-getty.slice.

10944 16:52:35.728072  [  OK  ] Created slice system-getty.slice.

10945 16:52:35.744994  <30>[   18.247608] systemd[1]: Created slice system-modprobe.slice.

10946 16:52:35.752061  [  OK  ] Created slice system-modprobe.slice.

10947 16:52:35.769819  <30>[   18.272166] systemd[1]: Created slice system-serial\x2dgetty.slice.

10948 16:52:35.779719  [  OK  ] Created slice system-serial\x2dgetty.slice.

10949 16:52:35.793358  <30>[   18.295486] systemd[1]: Created slice User and Session Slice.

10950 16:52:35.799761  [  OK  ] Created slice User and Session Slice.

10951 16:52:35.820040  <30>[   18.319241] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10952 16:52:35.829835  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10953 16:52:35.843899  <30>[   18.343167] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10954 16:52:35.850243  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10955 16:52:35.871131  <30>[   18.367093] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10956 16:52:35.878119  <30>[   18.379115] systemd[1]: Reached target Local Encrypted Volumes.

10957 16:52:35.884200  [  OK  ] Reached target Local Encrypted Volumes.

10958 16:52:35.901128  <30>[   18.403095] systemd[1]: Reached target Paths.

10959 16:52:35.903983  [  OK  ] Reached target Paths.

10960 16:52:35.920621  <30>[   18.423045] systemd[1]: Reached target Remote File Systems.

10961 16:52:35.927286  [  OK  ] Reached target Remote File Systems.

10962 16:52:35.944694  <30>[   18.446976] systemd[1]: Reached target Slices.

10963 16:52:35.947993  [  OK  ] Reached target Slices.

10964 16:52:35.964520  <30>[   18.467060] systemd[1]: Reached target Swap.

10965 16:52:35.967652  [  OK  ] Reached target Swap.

10966 16:52:35.988398  <30>[   18.487245] systemd[1]: Listening on initctl Compatibility Named Pipe.

10967 16:52:35.994492  [  OK  ] Listening on initctl Compatibility Named Pipe.

10968 16:52:36.001573  <30>[   18.501950] systemd[1]: Listening on Journal Audit Socket.

10969 16:52:36.007457  [  OK  ] Listening on Journal Audit Socket.

10970 16:52:36.020901  <30>[   18.523307] systemd[1]: Listening on Journal Socket (/dev/log).

10971 16:52:36.027126  [  OK  ] Listening on Journal Socket (/dev/log).

10972 16:52:36.045311  <30>[   18.547787] systemd[1]: Listening on Journal Socket.

10973 16:52:36.051882  [  OK  ] Listening on Journal Socket.

10974 16:52:36.064794  <30>[   18.567344] systemd[1]: Listening on udev Control Socket.

10975 16:52:36.071209  [  OK  ] Listening on udev Control Socket.

10976 16:52:36.089395  <30>[   18.591677] systemd[1]: Listening on udev Kernel Socket.

10977 16:52:36.095531  [  OK  ] Listening on udev Kernel Socket.

10978 16:52:36.128754  <30>[   18.631158] systemd[1]: Mounting Huge Pages File System...

10979 16:52:36.135154           Mounting Huge Pages File System...

10980 16:52:36.150778  <30>[   18.653206] systemd[1]: Mounting POSIX Message Queue File System...

10981 16:52:36.157615           Mounting POSIX Message Queue File System...

10982 16:52:36.174700  <30>[   18.677227] systemd[1]: Mounting Kernel Debug File System...

10983 16:52:36.181364           Mounting Kernel Debug File System...

10984 16:52:36.200786  <30>[   18.699347] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10985 16:52:36.244128  <30>[   18.743475] systemd[1]: Starting Create list of static device nodes for the current kernel...

10986 16:52:36.250838           Starting Create list of st…odes for the current kernel...

10987 16:52:36.271181  <30>[   18.773640] systemd[1]: Starting Load Kernel Module configfs...

10988 16:52:36.277687           Starting Load Kernel Module configfs...

10989 16:52:36.295512  <30>[   18.797516] systemd[1]: Starting Load Kernel Module drm...

10990 16:52:36.301813           Starting Load Kernel Module drm...

10991 16:52:36.319438  <30>[   18.819214] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10992 16:52:36.330098  <30>[   18.832990] systemd[1]: Starting Journal Service...

10993 16:52:36.333248           Starting Journal Service...

10994 16:52:36.351355  <30>[   18.853743] systemd[1]: Starting Load Kernel Modules...

10995 16:52:36.357555           Starting Load Kernel Modules...

10996 16:52:36.378382  <30>[   18.878014] systemd[1]: Starting Remount Root and Kernel File Systems...

10997 16:52:36.385259           Starting Remount Root and Kernel File Systems...

10998 16:52:36.402600  <30>[   18.905607] systemd[1]: Starting Coldplug All udev Devices...

10999 16:52:36.409466           Starting Coldplug All udev Devices...

11000 16:52:36.427491  <30>[   18.929883] systemd[1]: Mounted Huge Pages File System.

11001 16:52:36.434082  [  OK  ] Mounted Huge Pages File System.

11002 16:52:36.449079  <30>[   18.951637] systemd[1]: Started Journal Service.

11003 16:52:36.455525  [  OK  ] Started Journal Service.

11004 16:52:36.470333  [  OK  ] Mounted POSIX Message Queue File System.

11005 16:52:36.485235  [  OK  ] Mounted Kernel Debug File System.

11006 16:52:36.504820  [  OK  ] Finished Create list of st… nodes for the current kernel.

11007 16:52:36.522157  [  OK  ] Finished Load Kernel Module configfs.

11008 16:52:36.538106  [  OK  ] Finished Load Kernel Module drm.

11009 16:52:36.554029  [  OK  ] Finished Load Kernel Modules.

11010 16:52:36.573361  [FAILED] Failed to start Remount Root and Kernel File Systems.

11011 16:52:36.588537  See 'systemctl status systemd-remount-fs.service' for details.

11012 16:52:36.630591           Mounting Kernel Configuration File System...

11013 16:52:36.647183           Starting Flush Journal to Persistent Storage...

11014 16:52:36.664957  <46>[   19.164208] systemd-journald[173]: Received client request to flush runtime journal.

11015 16:52:36.673639           Starting Load/Save Random Seed...

11016 16:52:36.695558           Starting Apply Kernel Variables...

11017 16:52:36.715038           Starting Create System Users...

11018 16:52:36.740605  [  OK  ] Mounted Kernel Configuration File System.

11019 16:52:36.756676  [  OK  ] Finished Flush Journal to Persistent Storage.

11020 16:52:36.769616  [  OK  ] Finished Load/Save Random Seed.

11021 16:52:36.785759  [  OK  ] Finished Apply Kernel Variables.

11022 16:52:36.802179  [  OK  ] Finished Coldplug All udev Devices.

11023 16:52:36.818294  [  OK  ] Finished Create System Users.

11024 16:52:36.865607           Starting Create Static Device Nodes in /dev...

11025 16:52:36.888769  [  OK  ] Finished Create Static Device Nodes in /dev.

11026 16:52:36.901103  [  OK  ] Reached target Local File Systems (Pre).

11027 16:52:36.916669  [  OK  ] Reached target Local File Systems.

11028 16:52:36.966394           Starting Create Volatile Files and Directories...

11029 16:52:36.988299           Starting Rule-based Manage…for Device Events and Files...

11030 16:52:37.005671  [  OK  ] Finished Create Volatile Files and Directories.

11031 16:52:37.025010  [  OK  ] Started Rule-based Manager for Device Events and Files.

11032 16:52:37.077701           Starting Network Time Synchronization...

11033 16:52:37.096850           Starting Update UTMP about System Boot/Shutdown...

11034 16:52:37.125539  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

11035 16:52:37.183611  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

11036 16:52:37.194212  <6>[   19.693495] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

11037 16:52:37.208098  <6>[   19.710161] remoteproc remoteproc0: scp is available

11038 16:52:37.217685  <4>[   19.716081] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

11039 16:52:37.224852  <6>[   19.727689] remoteproc remoteproc0: powering up scp

11040 16:52:37.234996  <4>[   19.733404] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

11041 16:52:37.241681  <3>[   19.743496] remoteproc remoteproc0: request_firmware failed: -2

11042 16:52:37.256506           Starting Load/Save Screen …o<3>[   19.755214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

11043 16:52:37.266259  f leds:white:kbd<3>[   19.764683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

11044 16:52:37.276206  _backlight..<3>[   19.774493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

11045 16:52:37.276682  .

11046 16:52:37.285998  <3>[   19.785376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

11047 16:52:37.292480  <3>[   19.793536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

11048 16:52:37.302298  <3>[   19.801656] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

11049 16:52:37.308970  <3>[   19.809764] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

11050 16:52:37.318752  <3>[   19.809774] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

11051 16:52:37.325252  <6>[   19.813183] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

11052 16:52:37.332225  <4>[   19.813686] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

11053 16:52:37.342012  [  OK  [<6>[   19.814715] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

11054 16:52:37.351846  <6>[   19.814754] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

11055 16:52:37.362205  0m] Started [0;<6>[   19.814765] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

11056 16:52:37.369095  1;39mNetwork Tim<4>[   19.830174] elants_i2c 4-0010: supply vccio not found, using dummy regulator

11057 16:52:37.378780  e Synchronizatio<4>[   19.836006] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

11058 16:52:37.385314  <4>[   19.836006] Fallback method does not support PEC.

11059 16:52:37.392105  <3>[   19.838342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

11060 16:52:37.392627  n.

11061 16:52:37.402006  <3>[   19.838457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

11062 16:52:37.408711  <3>[   19.838466] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

11063 16:52:37.418857  <3>[   19.838473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

11064 16:52:37.425662  <3>[   19.849267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

11065 16:52:37.431096  <6>[   19.878719] mc: Linux media interface: v0.10

11066 16:52:37.437990  <3>[   19.892490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

11067 16:52:37.447828  <3>[   19.909229] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11068 16:52:37.451480  <6>[   19.913727] usbcore: registered new interface driver r8152

11069 16:52:37.461467  <3>[   19.917281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

11070 16:52:37.468509  <6>[   19.928642] videodev: Linux video capture interface: v2.00

11071 16:52:37.475527  <3>[   19.933454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

11072 16:52:37.481800  <6>[   19.942236] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

11073 16:52:37.492099  <3>[   19.946063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

11074 16:52:37.498226  <3>[   19.946152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

11075 16:52:37.505231  <3>[   19.955052] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff

11076 16:52:37.511741  <6>[   19.955162] pci_bus 0000:00: root bus resource [bus 00-ff]

11077 16:52:37.518652  <6>[   19.955186] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

11078 16:52:37.528550  <6>[   19.955205] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

11079 16:52:37.535003  <6>[   19.955349] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

11080 16:52:37.542097  <6>[   19.955402] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

11081 16:52:37.548277  <6>[   19.955593] pci 0000:00:00.0: supports D1 D2

11082 16:52:37.555069  <6>[   19.955601] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

11083 16:52:37.561621  <6>[   19.958083] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

11084 16:52:37.568339  <6>[   19.958254] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

11085 16:52:37.574630  <6>[   19.958289] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

11086 16:52:37.585017  <6>[   19.958311] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

11087 16:52:37.591761  <6>[   19.958331] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

11088 16:52:37.595066  <6>[   19.958477] pci 0000:01:00.0: supports D1 D2

11089 16:52:37.602083  <6>[   19.958481] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

11090 16:52:37.611561  <6>[   19.963748] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003

11091 16:52:37.618292  <6>[   19.978570] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

11092 16:52:37.628238  <6>[   19.984220] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2

11093 16:52:37.635786  <6>[   19.990553] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

11094 16:52:37.645898  <6>[   19.990599] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

11095 16:52:37.652571  <6>[   19.990655] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

11096 16:52:37.658599  <6>[   19.990681] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

11097 16:52:37.668846  <6>[   19.990701] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

11098 16:52:37.678414  <3>[   20.000387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11099 16:52:37.685010  <3>[   20.003272] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6

11100 16:52:37.691964  <6>[   20.007534] pci 0000:00:00.0: PCI bridge to [bus 01]

11101 16:52:37.698402  <6>[   20.011070] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

11102 16:52:37.705131  <3>[   20.033244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11103 16:52:37.715096  <4>[   20.034029] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

11104 16:52:37.725106  <4>[   20.034040] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

11105 16:52:37.731595  <6>[   20.036364] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

11106 16:52:37.741748  <3>[   20.062909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11107 16:52:37.747872  <3>[   20.066931] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff

11108 16:52:37.754720  <6>[   20.070044] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

11109 16:52:37.757845  <6>[   20.086808] r8152 2-1.3:1.0 eth0: v1.12.13

11110 16:52:37.764803  <6>[   20.091821] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

11111 16:52:37.771174  <3>[   20.107840] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11112 16:52:37.777739  <6>[   20.110205] pcieport 0000:00:00.0: AER: enabled with IRQ 282

11113 16:52:37.787706  <3>[   20.143196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11114 16:52:37.794731  <3>[   20.170988] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff

11115 16:52:37.801207  [  OK  [<3>[   20.301624] elants_i2c 4-0010: (read fw id) unexpected response: ff ff

11116 16:52:37.811256  0m] Finished [0<6>[   20.309863] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3

11117 16:52:37.821695  <3>[   20.318091] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11118 16:52:37.828417  ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight.

11119 16:52:37.834631  <6>[   20.334999] usbcore: registered new interface driver cdc_ether

11120 16:52:37.841330  <6>[   20.343168] usbcore: registered new interface driver r8153_ecm

11121 16:52:37.857350  <6>[   20.356558] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

11122 16:52:37.870188  [  OK  ] Found device<6>[   20.365674] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

11123 16:52:37.876948   /dev/t<6>[   20.366564] Bluetooth: Core ver 2.22

11124 16:52:37.877430  tyS0.

11125 16:52:37.887813  <5>[   20.368191] cfg80211: Loading compiled-in X.509 certificates for regulatory database

11126 16:52:37.893445  <6>[   20.368244] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0

11127 16:52:37.900144  <5>[   20.379058] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

11128 16:52:37.903330  <6>[   20.380106] usbcore: registered new interface driver uvcvideo

11129 16:52:37.910824  <6>[   20.385068] NET: Registered PF_BLUETOOTH protocol family

11130 16:52:37.917624  <6>[   20.387781] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

11131 16:52:37.920890  <6>[   20.392946] remoteproc remoteproc0: powering up scp

11132 16:52:37.931822  <4>[   20.392993] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

11133 16:52:37.938772  <3>[   20.393001] remoteproc remoteproc0: request_firmware failed: -2

11134 16:52:37.945176  <3>[   20.393004] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!

11135 16:52:37.955154  <4>[   20.400331] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

11136 16:52:37.961818  <6>[   20.406418] Bluetooth: HCI device and connection manager initialized

11137 16:52:37.964962  <6>[   20.406439] Bluetooth: HCI socket layer initialized

11138 16:52:37.971311  <6>[   20.412439] cfg80211: failed to load regulatory.db

11139 16:52:37.978180  <6>[   20.418011] Bluetooth: L2CAP socket layer initialized

11140 16:52:37.985094  <3>[   20.428052] power_supply sbs-5-000b: driver failed to report `capacity' property: -6

11141 16:52:37.991560  <6>[   20.429678] Bluetooth: SCO socket layer initialized

11142 16:52:37.997516  <3>[   20.441226] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11143 16:52:38.007333  <6>[   20.473685] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

11144 16:52:38.010665  <6>[   20.493414] usbcore: registered new interface driver btusb

11145 16:52:38.017747  <6>[   20.497528] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

11146 16:52:38.027271  <4>[   20.506680] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

11147 16:52:38.033969  <6>[   20.530929] mt7921e 0000:01:00.0: ASIC revision: 79610010

11148 16:52:38.041333  <3>[   20.536305] Bluetooth: hci0: Failed to load firmware file (-2)

11149 16:52:38.045024  <3>[   20.548007] Bluetooth: hci0: Failed to set up firmware (-2)

11150 16:52:38.058515  <4>[   20.553834] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

11151 16:52:38.061393  [  OK  ] Reached target Bluetooth.

11152 16:52:38.076605  [  OK  ] Reached target System Initialization.

11153 16:52:38.095797  [  OK  ] Started Daily Cleanup of Temporary Directories.

11154 16:52:38.108797  [  OK  ] Reached target System Time Set.

11155 16:52:38.129896  [  OK  ] Reached target System Time Synchronized.

11156 16:52:38.143249  <4>[   20.638725] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11157 16:52:38.154020  [  OK  ] Started Discard unused blocks once a week.

11158 16:52:38.168453  [  OK  ] Reached target Timers.

11159 16:52:38.188136  [  OK  ] Listening on D-Bus System Message Bus Socket.

11160 16:52:38.200544  [  OK  ] Reached target Sockets.

11161 16:52:38.216527  [  OK  ] Reached target Basic System.

11162 16:52:38.235972  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

11163 16:52:38.261918  <4>[   20.758241] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11164 16:52:38.296832  [  OK  ] Started D-Bus System Message Bus.

11165 16:52:38.323003           Starting User Login Management...

11166 16:52:38.338506           Starting Permit User Sessions...

11167 16:52:38.356214           Starting Load/Save RF Kill Switch Status...

11168 16:52:38.378702  [  OK  ] Finished Permit User Sessions.

11169 16:52:38.392024  <4>[   20.887369] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11170 16:52:38.398194  [  OK  ] Started Load/Save RF Kill Switch Status.

11171 16:52:38.449435  [  OK  ] Started Getty on tty1.

11172 16:52:38.467665  [  OK  ] Started Serial Getty on ttyS0.

11173 16:52:38.488985  [  OK  ] Reached target Login Prompts.

11174 16:52:38.517056  <4>[   21.013331] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11175 16:52:38.523370  [  OK  ] Started User Login Management.

11176 16:52:38.530958  [  OK  ] Reached target Multi-User System.

11177 16:52:38.548541  [  OK  ] Reached target Graphical Interface.

11178 16:52:38.600286           Starting Update UTMP about System Runlevel Changes...

11179 16:52:38.641069  [  OK  ] Finished [0<4>[   21.135551] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11180 16:52:38.643938  ;1;39mUpdate UTMP about System Runlevel Changes.

11181 16:52:38.663663  

11182 16:52:38.664223  

11183 16:52:38.666583  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

11184 16:52:38.667140  

11185 16:52:38.669894  debian-bullseye-arm64 login: root (automatic login)

11186 16:52:38.670508  

11187 16:52:38.670892  

11188 16:52:38.686770  Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun  3 16:27:28 UTC 2023 aarch64

11189 16:52:38.687347  

11190 16:52:38.693393  The programs included with the Debian GNU/Linux system are free software;

11191 16:52:38.699701  the exact distribution terms for each program are described in the

11192 16:52:38.702900  individual files in /usr/share/doc/*/copyright.

11193 16:52:38.703369  

11194 16:52:38.709934  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

11195 16:52:38.712588  permitted by applicable law.

11196 16:52:38.713838  Matched prompt #10: / #
11198 16:52:38.715013  Setting prompt string to ['/ #']
11199 16:52:38.715486  end: 2.2.5.1 login-action (duration 00:00:22) [common]
11201 16:52:38.716884  end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11202 16:52:38.717363  start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11203 16:52:38.717782  Setting prompt string to ['/ #']
11204 16:52:38.718142  Forcing a shell prompt, looking for ['/ #']
11206 16:52:38.769055  / # 

11207 16:52:38.769714  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11208 16:52:38.770278  Waiting using forced prompt support (timeout 00:02:30)
11209 16:52:38.770851  <4>[   21.261269] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11210 16:52:38.775777  

11211 16:52:38.776735  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11212 16:52:38.777496  start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11213 16:52:38.778056  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11214 16:52:38.778626  end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11215 16:52:38.779128  end: 2 depthcharge-action (duration 00:02:00) [common]
11216 16:52:38.779597  start: 3 lava-test-retry (timeout 00:05:00) [common]
11217 16:52:38.780064  start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11218 16:52:38.780465  Using namespace: common
11220 16:52:38.881555  / # #

11221 16:52:38.882316  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11222 16:52:38.884770  #<4>[   21.380857] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11223 16:52:38.927005  

11224 16:52:38.928176  Using /lava-10576309
11226 16:52:39.029360  / # export SHELL=/bin/sh

11227 16:52:39.030059  export SHELL=/bin/sh<4>[   21.501245] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11228 16:52:39.035025  

11230 16:52:39.136281  / # . /lava-10576309/environment

11231 16:52:39.136513  . /lava-10576309/environment<4>[   21.621202] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11232 16:52:39.141406  

11234 16:52:39.242014  / # /lava-10576309/bin/lava-test-runner /lava-10576309/0

11235 16:52:39.242295  Test shell timeout: 10s (minimum of the action and connection timeout)
11236 16:52:39.244658  /lava-10576309/bin/lava-test-runner /lava-10576309/0<4>[   21.741237] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11237 16:52:39.286816  

11238 16:52:39.287343  + export TESTRUN_ID=0_sleep

11239 16:52:39.287726  + cd /lava-10576309/0/tests/0_sleep

11240 16:52:39.288084  + cat uuid

11241 16:52:39.288423  + UUID=10576309_1.5.2.3.1

11242 16:52:39.289041  + set +x

11243 16:52:39.290765  <LAVA_SIGNAL_STARTRUN 0_sleep 10576309_1.5.2.3.1>

11244 16:52:39.291512  Received signal: <STARTRUN> 0_sleep 10576309_1.5.2.3.1
11245 16:52:39.291936  Starting test lava.0_sleep (10576309_1.5.2.3.1)
11246 16:52:39.292407  Skipping test definition patterns.
11247 16:52:39.294322  + ./config/lava/sleep/sleep.sh mem freeze

11248 16:52:39.297547  Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11250 16:52:39.300777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>

11251 16:52:39.304045  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>

11252 16:52:39.304896  Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11254 16:52:39.307400  rtcwake: assuming RTC uses UTC ...

11255 16:52:39.314045  rtcwake: wakeup from "mem" u<6>[   21.818177] PM: suspend entry (deep)

11256 16:52:39.320548  sing rtc0 at Sat<6>[   21.822404] Filesystems sync: 0.000 seconds

11257 16:52:39.324595   Jun  3 16:52:45 2023

11258 16:52:39.327056  <6>[   21.830643] Freezing user space processes

11259 16:52:39.337559  <6>[   21.836722] Freezing user space processes completed (elapsed 0.001 seconds)

11260 16:52:39.341108  <6>[   21.843961] OOM killer disabled.

11261 16:52:39.343566  <6>[   21.847446] Freezing remaining freezable tasks

11262 16:52:39.354678  <6>[   21.854195] Freezing remaining freezable tasks completed (elapsed 0.002 seconds)

11263 16:52:39.358303  <3>[   21.859432] mt7921e 0000:01:00.0: hardware init failed

11264 16:52:39.367571  <6>[   21.861875] printk: Suspending console(s) (use no_console_suspend to debug)

11265 16:52:42.414453  <3>[   21.876387] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11266 16:52:42.420601  <3>[   21.876425] elants_i2c 4-0010: PM: failed to suspend async: error -16

11267 16:52:42.427286  <3>[   24.906994] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout

11268 16:52:42.437479  <3>[   24.907018] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11269 16:52:42.444657  <3>[   24.907043] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11270 16:52:42.450825  <3>[   24.907065] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11271 16:52:42.460533  <3>[   24.907466] PM: Some devices failed to suspend, or early wake event detected

11272 16:52:42.463984  <6>[   24.967699] OOM killer enabled.

11273 16:52:42.466902  <6>[   24.971096] Restarting tasks ... done.

11274 16:52:42.473624  <5>[   24.976486] random: crng reseeded on system resumption

11275 16:52:42.477167  <6>[   24.983974] PM: suspend exit

11276 16:52:42.480441  rtcwake: write error

11277 16:52:42.489146  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>

11278 16:52:42.489981  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11280 16:52:42.492308  rtcwake: assuming RTC uses UTC ...

11281 16:52:42.498531  rtcwake: wakeup from "mem" using rtc0 at Sat Jun  3 16:52:48 2023

11282 16:52:42.511509  <6>[   25.015067] PM: suspend entry (deep)

11283 16:52:42.515382  <6>[   25.018957] Filesystems sync: 0.000 seconds

11284 16:52:42.521680  <6>[   25.024140] Freezing user space processes

11285 16:52:42.528311  <6>[   25.030074] Freezing user space processes completed (elapsed 0.001 seconds)

11286 16:52:42.531899  <6>[   25.037360] OOM killer disabled.

11287 16:52:42.537977  <6>[   25.040856] Freezing remaining freezable tasks

11288 16:52:42.545020  <6>[   25.046787] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11289 16:52:42.554543  <6>[   25.054439] printk: Suspending console(s) (use no_console_suspend to debug)

11290 16:52:45.741978  <3>[   25.062689] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11291 16:52:45.748710  <3>[   25.062747] elants_i2c 4-0010: PM: failed to suspend async: error -16

11292 16:52:45.754950  <3>[   28.235050] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout

11293 16:52:45.765643  <3>[   28.235078] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11294 16:52:45.772050  <3>[   28.235117] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11295 16:52:45.777976  <3>[   28.235141] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11296 16:52:45.788580  <3>[   28.235585] PM: Some devices failed to suspend, or early wake event detected

11297 16:52:45.791933  <6>[   28.295461] OOM killer enabled.

11298 16:52:45.794746  <6>[   28.298859] Restarting tasks ... done.

11299 16:52:45.801471  <5>[   28.304144] random: crng reseeded on system resumption

11300 16:52:45.804844  <6>[   28.310625] PM: suspend exit

11301 16:52:45.808238  rtcwake: write error

11302 16:52:45.815010  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>

11303 16:52:45.815790  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11305 16:52:45.818592  rtcwake: assuming RTC uses UTC ...

11306 16:52:45.825114  rtcwake: wakeup from "mem" using rtc0 at Sat Jun  3 16:52:52 2023

11307 16:52:45.838337  <6>[   28.341467] PM: suspend entry (deep)

11308 16:52:45.841047  <6>[   28.345370] Filesystems sync: 0.000 seconds

11309 16:52:45.847727  <6>[   28.350571] Freezing user space processes

11310 16:52:45.854220  <6>[   28.356698] Freezing user space processes completed (elapsed 0.001 seconds)

11311 16:52:45.857642  <6>[   28.363929] OOM killer disabled.

11312 16:52:45.864464  <6>[   28.367411] Freezing remaining freezable tasks

11313 16:52:45.870874  <6>[   28.373366] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11314 16:52:45.880895  <6>[   28.381029] printk: Suspending console(s) (use no_console_suspend to debug)

11315 16:52:49.070089  <3>[   28.389355] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11316 16:52:49.077091  <3>[   28.389397] elants_i2c 4-0010: PM: failed to suspend async: error -16

11317 16:52:49.082956  <3>[   31.563000] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout

11318 16:52:49.093286  <3>[   31.563024] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11319 16:52:49.099817  <3>[   31.563049] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11320 16:52:49.106222  <3>[   31.563071] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11321 16:52:49.116232  <3>[   31.563452] PM: Some devices failed to suspend, or early wake event detected

11322 16:52:49.120013  <6>[   31.623867] OOM killer enabled.

11323 16:52:49.122993  <6>[   31.627278] Restarting tasks ... done.

11324 16:52:49.129578  <5>[   31.632606] random: crng reseeded on system resumption

11325 16:52:49.133142  <6>[   31.639011] PM: suspend exit

11326 16:52:49.135561  rtcwake: write error

11327 16:52:49.142584  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>

11328 16:52:49.143343  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11330 16:52:49.146340  rtcwake: assuming RTC uses UTC ...

11331 16:52:49.152742  rtcwake: wakeup from "mem" using rtc0 at Sat Jun  3 16:52:55 2023

11332 16:52:49.165954  <6>[   31.669682] PM: suspend entry (deep)

11333 16:52:49.169399  <6>[   31.673585] Filesystems sync: 0.000 seconds

11334 16:52:49.175364  <6>[   31.678713] Freezing user space processes

11335 16:52:49.182154  <6>[   31.684707] Freezing user space processes completed (elapsed 0.001 seconds)

11336 16:52:49.185071  <6>[   31.691973] OOM killer disabled.

11337 16:52:49.192170  <6>[   31.695455] Freezing remaining freezable tasks

11338 16:52:49.198908  <6>[   31.701514] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11339 16:52:49.208634  <6>[   31.709209] printk: Suspending console(s) (use no_console_suspend to debug)

11340 16:52:52.396735  <3>[   31.717462] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11341 16:52:52.403004  <3>[   31.717512] elants_i2c 4-0010: PM: failed to suspend async: error -16

11342 16:52:52.409436  <3>[   34.891041] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout

11343 16:52:52.419200  <3>[   34.891065] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11344 16:52:52.426045  <3>[   34.891098] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11345 16:52:52.432548  <3>[   34.891120] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11346 16:52:52.442829  <3>[   34.891554] PM: Some devices failed to suspend, or early wake event detected

11347 16:52:52.445990  <6>[   34.951059] OOM killer enabled.

11348 16:52:52.449201  <6>[   34.954453] Restarting tasks ... done.

11349 16:52:52.456667  <5>[   34.959774] random: crng reseeded on system resumption

11350 16:52:52.459092  <6>[   34.966146] PM: suspend exit

11351 16:52:52.462985  rtcwake: write error

11352 16:52:52.469672  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>

11353 16:52:52.470518  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11355 16:52:52.473335  rtcwake: assuming RTC uses UTC ...

11356 16:52:52.479398  rtcwake: wakeup from "mem" using rtc0 at Sat Jun  3 16:52:58 2023

11357 16:52:52.492696  <6>[   34.997028] PM: suspend entry (deep)

11358 16:52:52.495844  <6>[   35.000923] Filesystems sync: 0.000 seconds

11359 16:52:52.502682  <6>[   35.006121] Freezing user space processes

11360 16:52:52.509068  <6>[   35.012214] Freezing user space processes completed (elapsed 0.001 seconds)

11361 16:52:52.512701  <6>[   35.019454] OOM killer disabled.

11362 16:52:52.519284  <6>[   35.022942] Freezing remaining freezable tasks

11363 16:52:52.525623  <6>[   35.028936] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11364 16:52:52.535434  <6>[   35.036599] printk: Suspending console(s) (use no_console_suspend to debug)

11365 16:52:55.725055  <3>[   35.044974] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11366 16:52:55.731295  <3>[   35.045008] elants_i2c 4-0010: PM: failed to suspend async: error -16

11367 16:52:55.738031  <3>[   38.219085] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout

11368 16:52:55.747745  <3>[   38.219153] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11369 16:52:55.754624  <3>[   38.219211] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11370 16:52:55.761374  <3>[   38.219234] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11371 16:52:55.770921  <3>[   38.219608] PM: Some devices failed to suspend, or early wake event detected

11372 16:52:55.774557  <6>[   38.279800] OOM killer enabled.

11373 16:52:55.777560  <6>[   38.283198] Restarting tasks ... done.

11374 16:52:55.784512  <5>[   38.288648] random: crng reseeded on system resumption

11375 16:52:55.787644  <6>[   38.295076] PM: suspend exit

11376 16:52:55.790971  rtcwake: write error

11377 16:52:55.799172  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>

11378 16:52:55.800198  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11380 16:52:55.801529  rtcwake: assuming RTC uses UTC ...

11381 16:52:55.808801  rtcwake: wakeup from "mem" using rtc0 at Sat Jun  3 16:53:02 2023

11382 16:52:55.821387  <6>[   38.326042] PM: suspend entry (deep)

11383 16:52:55.824756  <6>[   38.329937] Filesystems sync: 0.000 seconds

11384 16:52:55.830887  <6>[   38.335204] Freezing user space processes

11385 16:52:55.837381  <6>[   38.341234] Freezing user space processes completed (elapsed 0.001 seconds)

11386 16:52:55.840537  <6>[   38.348465] OOM killer disabled.

11387 16:52:55.847113  <6>[   38.351949] Freezing remaining freezable tasks

11388 16:52:55.856906  <6>[   38.357990] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11389 16:52:55.863557  <6>[   38.365655] printk: Suspending console(s) (use no_console_suspend to debug)

11390 16:52:59.052450  <3>[   38.374030] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11391 16:52:59.059072  <3>[   38.374059] elants_i2c 4-0010: PM: failed to suspend async: error -16

11392 16:52:59.065665  <3>[   41.547025] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout

11393 16:52:59.076035  <3>[   41.547050] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11394 16:52:59.082331  <3>[   41.547082] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11395 16:52:59.088812  <3>[   41.547104] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11396 16:52:59.098612  <3>[   41.547429] PM: Some devices failed to suspend, or early wake event detected

11397 16:52:59.102295  <6>[   41.607965] OOM killer enabled.

11398 16:52:59.105775  <6>[   41.611377] Restarting tasks ... done.

11399 16:52:59.111911  <5>[   41.616776] random: crng reseeded on system resumption

11400 16:52:59.115543  <6>[   41.623264] PM: suspend exit

11401 16:52:59.119188  rtcwake: write error

11402 16:52:59.126580  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>

11403 16:52:59.127278  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11405 16:52:59.129332  rtcwake: assuming RTC uses UTC ...

11406 16:52:59.136143  rtcwake: wakeup from "mem" using rtc0 at Sat Jun  3 16:53:05 2023

11407 16:52:59.149393  <6>[   41.654308] PM: suspend entry (deep)

11408 16:52:59.152424  <6>[   41.658210] Filesystems sync: 0.000 seconds

11409 16:52:59.158764  <6>[   41.663405] Freezing user space processes

11410 16:52:59.165641  <6>[   41.669385] Freezing user space processes completed (elapsed 0.001 seconds)

11411 16:52:59.168749  <6>[   41.676672] OOM killer disabled.

11412 16:52:59.175842  <6>[   41.680157] Freezing remaining freezable tasks

11413 16:52:59.182268  <6>[   41.686113] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11414 16:52:59.191670  <6>[   41.693772] printk: Suspending console(s) (use no_console_suspend to debug)

11415 16:53:02.379989  <3>[   41.702022] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11416 16:53:02.386710  <3>[   41.702062] elants_i2c 4-0010: PM: failed to suspend async: error -16

11417 16:53:02.393794  <3>[   44.875034] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout

11418 16:53:02.403123  <3>[   44.875062] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11419 16:53:02.410213  <3>[   44.875096] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11420 16:53:02.416345  <3>[   44.875116] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11421 16:53:02.426550  <3>[   44.875375] PM: Some devices failed to suspend, or early wake event detected

11422 16:53:02.429740  <6>[   44.935903] OOM killer enabled.

11423 16:53:02.433295  <6>[   44.939340] Restarting tasks ... done.

11424 16:53:02.439858  <5>[   44.944852] random: crng reseeded on system resumption

11425 16:53:02.442826  <6>[   44.951365] PM: suspend exit

11426 16:53:02.446334  rtcwake: write error

11427 16:53:02.454416  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>

11428 16:53:02.455481  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11430 16:53:02.457282  rtcwake: assuming RTC uses UTC ...

11431 16:53:02.464358  rtcwake: wakeup from "mem" using rtc0 at Sat Jun  3 16:53:08 2023

11432 16:53:02.477159  <6>[   44.982570] PM: suspend entry (deep)

11433 16:53:02.480251  <6>[   44.986461] Filesystems sync: 0.000 seconds

11434 16:53:02.487179  <6>[   44.991656] Freezing user space processes

11435 16:53:02.493217  <6>[   44.997682] Freezing user space processes completed (elapsed 0.001 seconds)

11436 16:53:02.496831  <6>[   45.004917] OOM killer disabled.

11437 16:53:02.503254  <6>[   45.008401] Freezing remaining freezable tasks

11438 16:53:02.509930  <6>[   45.014334] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11439 16:53:02.519362  <6>[   45.021993] printk: Suspending console(s) (use no_console_suspend to debug)

11440 16:53:05.706334  <3>[   45.030186] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11441 16:53:05.713189  <3>[   45.030225] elants_i2c 4-0010: PM: failed to suspend async: error -16

11442 16:53:05.719932  <3>[   48.203117] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout

11443 16:53:05.720360  <6>[   48.203147] vpu: disabling

11444 16:53:05.729831  <3>[   48.203155] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11445 16:53:05.739789  <3>[   48.203185] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11446 16:53:05.746305  <3>[   48.203206] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11447 16:53:05.749656  <6>[   48.203232] vproc2: disabling

11448 16:53:05.752928  <6>[   48.203271] vproc1: disabling

11449 16:53:05.756007  <6>[   48.203314] vaud18: disabling

11450 16:53:05.763121  <3>[   48.203471] PM: Some devices failed to suspend, or early wake event detected

11451 16:53:05.769450  <6>[   48.203500] vsram_others: disabling

11452 16:53:05.770017  <6>[   48.203632] va09: disabling

11453 16:53:05.775866  <6>[   48.203688] vsram_md: disabling

11454 16:53:05.776305  <6>[   48.203787] Vgpu: disabling

11455 16:53:05.779473  <6>[   48.288594] OOM killer enabled.

11456 16:53:05.787549  <6>[   48.291991] Restarting tasks ... done.

11457 16:53:05.790814  <5>[   48.297543] random: crng reseeded on system resumption

11458 16:53:05.794571  <6>[   48.303827] PM: suspend exit

11459 16:53:05.797980  rtcwake: write error

11460 16:53:05.805585  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>

11461 16:53:05.806284  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11463 16:53:05.808885  rtcwake: assuming RTC uses UTC ...

11464 16:53:05.815327  rtcwake: wakeup from "mem" using rtc0 at Sat Jun  3 16:53:12 2023

11465 16:53:05.828205  <6>[   48.334242] PM: suspend entry (deep)

11466 16:53:05.831863  <6>[   48.338166] Filesystems sync: 0.000 seconds

11467 16:53:05.838004  <6>[   48.343344] Freezing user space processes

11468 16:53:05.844721  <6>[   48.349385] Freezing user space processes completed (elapsed 0.001 seconds)

11469 16:53:05.847975  <6>[   48.356629] OOM killer disabled.

11470 16:53:05.854580  <6>[   48.360120] Freezing remaining freezable tasks

11471 16:53:05.861309  <6>[   48.366087] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11472 16:53:05.871025  <6>[   48.373766] printk: Suspending console(s) (use no_console_suspend to debug)

11473 16:53:09.035190  <3>[   48.382014] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11474 16:53:09.041908  <3>[   48.382048] elants_i2c 4-0010: PM: failed to suspend async: error -16

11475 16:53:09.047996  <3>[   51.531240] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout

11476 16:53:09.058095  <3>[   51.531389] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11477 16:53:09.065585  <3>[   51.531483] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11478 16:53:09.071625  <3>[   51.531506] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11479 16:53:09.081273  <3>[   51.531713] PM: Some devices failed to suspend, or early wake event detected

11480 16:53:09.084632  <6>[   51.591509] OOM killer enabled.

11481 16:53:09.088417  <6>[   51.594945] Restarting tasks ... done.

11482 16:53:09.094957  <5>[   51.600418] random: crng reseeded on system resumption

11483 16:53:09.097613  <6>[   51.606705] PM: suspend exit

11484 16:53:09.100650  rtcwake: write error

11485 16:53:09.108542  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>

11486 16:53:09.109389  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11488 16:53:09.111852  rtcwake: assuming RTC uses UTC ...

11489 16:53:09.118157  rtcwake: wakeup from "mem" using rtc0 at Sat Jun  3 16:53:15 2023

11490 16:53:09.131150  <6>[   51.637645] PM: suspend entry (deep)

11491 16:53:09.134995  <6>[   51.641557] Filesystems sync: 0.000 seconds

11492 16:53:09.141911  <6>[   51.646830] Freezing user space processes

11493 16:53:09.147763  <6>[   51.652796] Freezing user space processes completed (elapsed 0.001 seconds)

11494 16:53:09.151282  <6>[   51.660042] OOM killer disabled.

11495 16:53:09.157724  <6>[   51.663525] Freezing remaining freezable tasks

11496 16:53:09.164661  <6>[   51.669581] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11497 16:53:09.174127  <6>[   51.677267] printk: Suspending console(s) (use no_console_suspend to debug)

11498 16:53:12.363028  <3>[   51.685544] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11499 16:53:12.369687  <3>[   51.685590] elants_i2c 4-0010: PM: failed to suspend async: error -16

11500 16:53:12.376093  <3>[   54.859031] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout

11501 16:53:12.386333  <3>[   54.859056] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11502 16:53:12.392736  <3>[   54.859081] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11503 16:53:12.399237  <3>[   54.859103] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11504 16:53:12.409583  <3>[   54.859425] PM: Some devices failed to suspend, or early wake event detected

11505 16:53:12.412280  <6>[   54.919791] OOM killer enabled.

11506 16:53:12.416006  <6>[   54.923190] Restarting tasks ... done.

11507 16:53:12.422455  <5>[   54.928595] random: crng reseeded on system resumption

11508 16:53:12.426003  <6>[   54.934999] PM: suspend exit

11509 16:53:12.428920  rtcwake: write error

11510 16:53:12.436332  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>

11511 16:53:12.437249  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11513 16:53:12.440493  rtcwake: assuming RTC uses UTC ...

11514 16:53:12.446425  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:18 2023

11515 16:53:12.460672  <6>[   54.967348] PM: suspend entry (s2idle)

11516 16:53:12.464939  <6>[   54.971418] Filesystems sync: 0.000 seconds

11517 16:53:12.470430  <6>[   54.976630] Freezing user space processes

11518 16:53:12.477679  <6>[   54.982674] Freezing user space processes completed (elapsed 0.001 seconds)

11519 16:53:12.480466  <6>[   54.989902] OOM killer disabled.

11520 16:53:12.487617  <6>[   54.993383] Freezing remaining freezable tasks

11521 16:53:12.493734  <6>[   54.999328] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11522 16:53:12.503390  <6>[   55.006983] printk: Suspending console(s) (use no_console_suspend to debug)

11523 16:53:15.689805  <3>[   55.015290] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11524 16:53:15.696394  <3>[   55.015322] elants_i2c 4-0010: PM: failed to suspend async: error -16

11525 16:53:15.703710  <3>[   58.187042] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout

11526 16:53:15.713112  <3>[   58.187066] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11527 16:53:15.720315  <3>[   58.187098] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11528 16:53:15.726422  <3>[   58.187119] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11529 16:53:15.736324  <3>[   58.187444] PM: Some devices failed to suspend, or early wake event detected

11530 16:53:15.739306  <6>[   58.247116] OOM killer enabled.

11531 16:53:15.743137  <6>[   58.250509] Restarting tasks ... done.

11532 16:53:15.749366  <5>[   58.255906] random: crng reseeded on system resumption

11533 16:53:15.752886  <6>[   58.262360] PM: suspend exit

11534 16:53:15.756194  rtcwake: write error

11535 16:53:15.763222  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>

11536 16:53:15.764075  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11538 16:53:15.766313  rtcwake: assuming RTC uses UTC ...

11539 16:53:15.774102  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:21 2023

11540 16:53:15.786441  <6>[   58.293263] PM: suspend entry (s2idle)

11541 16:53:15.789873  <6>[   58.297324] Filesystems sync: 0.000 seconds

11542 16:53:15.796064  <6>[   58.302441] Freezing user space processes

11543 16:53:15.802953  <6>[   58.308512] Freezing user space processes completed (elapsed 0.001 seconds)

11544 16:53:15.806683  <6>[   58.315764] OOM killer disabled.

11545 16:53:15.812389  <6>[   58.319250] Freezing remaining freezable tasks

11546 16:53:15.822177  <6>[   58.325264] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11547 16:53:15.829225  <6>[   58.332980] printk: Suspending console(s) (use no_console_suspend to debug)

11548 16:53:19.018322  <3>[   58.341299] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11549 16:53:19.024887  <3>[   58.341343] elants_i2c 4-0010: PM: failed to suspend async: error -16

11550 16:53:19.031415  <3>[   61.515025] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout

11551 16:53:19.042197  <3>[   61.515049] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11552 16:53:19.048176  <3>[   61.515075] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11553 16:53:19.055247  <3>[   61.515098] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11554 16:53:19.064705  <3>[   61.515514] PM: Some devices failed to suspend, or early wake event detected

11555 16:53:19.067980  <6>[   61.575778] OOM killer enabled.

11556 16:53:19.071093  <6>[   61.579177] Restarting tasks ... done.

11557 16:53:19.077698  <5>[   61.584491] random: crng reseeded on system resumption

11558 16:53:19.082445  <6>[   61.592677] PM: suspend exit

11559 16:53:19.085161  rtcwake: write error

11560 16:53:19.092893  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>

11561 16:53:19.093707  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11563 16:53:19.096853  rtcwake: assuming RTC uses UTC ...

11564 16:53:19.103000  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:25 2023

11565 16:53:19.115843  <6>[   61.623520] PM: suspend entry (s2idle)

11566 16:53:19.119317  <6>[   61.627600] Filesystems sync: 0.000 seconds

11567 16:53:19.126270  <6>[   61.632785] Freezing user space processes

11568 16:53:19.132730  <6>[   61.638491] Freezing user space processes completed (elapsed 0.001 seconds)

11569 16:53:19.135540  <6>[   61.645802] OOM killer disabled.

11570 16:53:19.143134  <6>[   61.649291] Freezing remaining freezable tasks

11571 16:53:19.149438  <6>[   61.654773] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)

11572 16:53:19.155328  <6>[   61.662430] printk: Suspending console(s) (use no_console_suspend to debug)

11573 16:53:22.346428  <3>[   61.670573] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11574 16:53:22.353541  <3>[   61.670603] elants_i2c 4-0010: PM: failed to suspend async: error -16

11575 16:53:22.360416  <3>[   64.843039] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout

11576 16:53:22.369459  <3>[   64.843064] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11577 16:53:22.376363  <3>[   64.843099] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11578 16:53:22.383230  <3>[   64.843124] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11579 16:53:22.392894  <3>[   64.843719] PM: Some devices failed to suspend, or early wake event detected

11580 16:53:22.395798  <6>[   64.903959] OOM killer enabled.

11581 16:53:22.399076  <6>[   64.907359] Restarting tasks ... done.

11582 16:53:22.405578  <5>[   64.912159] random: crng reseeded on system resumption

11583 16:53:22.408570  <6>[   64.918625] PM: suspend exit

11584 16:53:22.412554  rtcwake: write error

11585 16:53:22.418449  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>

11586 16:53:22.419199  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11588 16:53:22.422456  rtcwake: assuming RTC uses UTC ...

11589 16:53:22.428572  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:28 2023

11590 16:53:22.441079  <6>[   64.949205] PM: suspend entry (s2idle)

11591 16:53:22.444518  <6>[   64.953265] Filesystems sync: 0.000 seconds

11592 16:53:22.451356  <6>[   64.958331] Freezing user space processes

11593 16:53:22.457859  <6>[   64.964015] Freezing user space processes completed (elapsed 0.001 seconds)

11594 16:53:22.461361  <6>[   64.971243] OOM killer disabled.

11595 16:53:22.467839  <6>[   64.974721] Freezing remaining freezable tasks

11596 16:53:22.474851  <6>[   64.980647] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11597 16:53:22.484428  <6>[   64.988316] printk: Suspending console(s) (use no_console_suspend to debug)

11598 16:53:25.673706  <3>[   64.996742] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11599 16:53:25.680516  <3>[   64.996779] elants_i2c 4-0010: PM: failed to suspend async: error -16

11600 16:53:25.687211  <3>[   68.171017] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout

11601 16:53:25.696907  <3>[   68.171041] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11602 16:53:25.703650  <3>[   68.171074] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11603 16:53:25.710106  <3>[   68.171096] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11604 16:53:25.720391  <3>[   68.171524] PM: Some devices failed to suspend, or early wake event detected

11605 16:53:25.724339  <6>[   68.232162] OOM killer enabled.

11606 16:53:25.727207  <6>[   68.235596] Restarting tasks ... done.

11607 16:53:25.733931  <5>[   68.240289] random: crng reseeded on system resumption

11608 16:53:25.736849  <6>[   68.246728] PM: suspend exit

11609 16:53:25.739689  rtcwake: write error

11610 16:53:25.747092  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>

11611 16:53:25.747972  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11613 16:53:25.749817  rtcwake: assuming RTC uses UTC ...

11614 16:53:25.757219  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:31 2023

11615 16:53:25.769044  <6>[   68.277190] PM: suspend entry (s2idle)

11616 16:53:25.772437  <6>[   68.281329] Filesystems sync: 0.000 seconds

11617 16:53:25.778556  <6>[   68.286415] Freezing user space processes

11618 16:53:25.785541  <6>[   68.292148] Freezing user space processes completed (elapsed 0.001 seconds)

11619 16:53:25.788730  <6>[   68.299397] OOM killer disabled.

11620 16:53:25.795619  <6>[   68.302882] Freezing remaining freezable tasks

11621 16:53:25.802164  <6>[   68.308884] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11622 16:53:25.811899  <6>[   68.316602] printk: Suspending console(s) (use no_console_suspend to debug)

11623 16:53:29.001509  <3>[   68.324874] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11624 16:53:29.007633  <3>[   68.324917] elants_i2c 4-0010: PM: failed to suspend async: error -16

11625 16:53:29.014934  <3>[   71.499043] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout

11626 16:53:29.024501  <3>[   71.499070] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11627 16:53:29.030851  <3>[   71.499107] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11628 16:53:29.037477  <3>[   71.499129] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11629 16:53:29.047496  <3>[   71.499645] PM: Some devices failed to suspend, or early wake event detected

11630 16:53:29.050623  <6>[   71.559792] OOM killer enabled.

11631 16:53:29.054087  <6>[   71.563191] Restarting tasks ... done.

11632 16:53:29.060289  <5>[   71.568020] random: crng reseeded on system resumption

11633 16:53:29.064907  <6>[   71.574561] PM: suspend exit

11634 16:53:29.067083  rtcwake: write error

11635 16:53:29.073800  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>

11636 16:53:29.074693  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11638 16:53:29.077493  rtcwake: assuming RTC uses UTC ...

11639 16:53:29.083726  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:35 2023

11640 16:53:29.096538  <6>[   71.605096] PM: suspend entry (s2idle)

11641 16:53:29.099920  <6>[   71.609178] Filesystems sync: 0.000 seconds

11642 16:53:29.106975  <6>[   71.614326] Freezing user space processes

11643 16:53:29.113210  <6>[   71.620124] Freezing user space processes completed (elapsed 0.001 seconds)

11644 16:53:29.116157  <6>[   71.627455] OOM killer disabled.

11645 16:53:29.122803  <6>[   71.630945] Freezing remaining freezable tasks

11646 16:53:29.130252  <6>[   71.636963] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11647 16:53:29.139046  <6>[   71.644652] printk: Suspending console(s) (use no_console_suspend to debug)

11648 16:53:32.329056  <3>[   71.652892] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11649 16:53:32.335237  <3>[   71.652924] elants_i2c 4-0010: PM: failed to suspend async: error -16

11650 16:53:32.341804  <3>[   74.827018] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout

11651 16:53:32.351702  <3>[   74.827043] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11652 16:53:32.358058  <3>[   74.827075] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11653 16:53:32.364978  <3>[   74.827096] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11654 16:53:32.374469  <3>[   74.827496] PM: Some devices failed to suspend, or early wake event detected

11655 16:53:32.378127  <6>[   74.887355] OOM killer enabled.

11656 16:53:32.381346  <6>[   74.890754] Restarting tasks ... done.

11657 16:53:32.388190  <5>[   74.895655] random: crng reseeded on system resumption

11658 16:53:32.391057  <6>[   74.902040] PM: suspend exit

11659 16:53:32.394330  rtcwake: write error

11660 16:53:32.401338  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>

11661 16:53:32.402185  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11663 16:53:32.404104  rtcwake: assuming RTC uses UTC ...

11664 16:53:32.411121  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:38 2023

11665 16:53:32.424162  <6>[   74.932781] PM: suspend entry (s2idle)

11666 16:53:32.427076  <6>[   74.936828] Filesystems sync: 0.000 seconds

11667 16:53:32.433356  <6>[   74.941971] Freezing user space processes

11668 16:53:32.440451  <6>[   74.947703] Freezing user space processes completed (elapsed 0.001 seconds)

11669 16:53:32.443676  <6>[   74.954923] OOM killer disabled.

11670 16:53:32.450581  <6>[   74.958401] Freezing remaining freezable tasks

11671 16:53:32.457372  <6>[   74.964305] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11672 16:53:32.466847  <6>[   74.971972] printk: Suspending console(s) (use no_console_suspend to debug)

11673 16:53:35.655502  <3>[   74.980324] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11674 16:53:35.662188  <3>[   74.980359] elants_i2c 4-0010: PM: failed to suspend async: error -16

11675 16:53:35.668773  <3>[   78.155036] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout

11676 16:53:35.678647  <3>[   78.155061] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11677 16:53:35.684824  <3>[   78.155096] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11678 16:53:35.691664  <3>[   78.155126] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11679 16:53:35.701767  <3>[   78.155439] PM: Some devices failed to suspend, or early wake event detected

11680 16:53:35.705437  <6>[   78.215014] OOM killer enabled.

11681 16:53:35.708842  <6>[   78.218408] Restarting tasks ... done.

11682 16:53:35.715011  <5>[   78.223315] random: crng reseeded on system resumption

11683 16:53:35.718451  <6>[   78.229863] PM: suspend exit

11684 16:53:35.721548  rtcwake: write error

11685 16:53:35.730077  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>

11686 16:53:35.730961  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11688 16:53:35.733318  rtcwake: assuming RTC uses UTC ...

11689 16:53:35.738797  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:41 2023

11690 16:53:35.751759  <6>[   78.261077] PM: suspend entry (s2idle)

11691 16:53:35.755150  <6>[   78.265137] Filesystems sync: 0.000 seconds

11692 16:53:35.761975  <6>[   78.270312] Freezing user space processes

11693 16:53:35.767819  <6>[   78.276147] Freezing user space processes completed (elapsed 0.001 seconds)

11694 16:53:35.771511  <6>[   78.283372] OOM killer disabled.

11695 16:53:35.777893  <6>[   78.286859] Freezing remaining freezable tasks

11696 16:53:35.785346  <6>[   78.292778] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11697 16:53:35.794245  <6>[   78.300436] printk: Suspending console(s) (use no_console_suspend to debug)

11698 16:53:38.984241  <3>[   78.308747] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11699 16:53:38.991185  <3>[   78.308778] elants_i2c 4-0010: PM: failed to suspend async: error -16

11700 16:53:38.998065  <3>[   81.483097] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout

11701 16:53:39.007321  <3>[   81.483170] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11702 16:53:39.014064  <3>[   81.483251] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11703 16:53:39.020991  <3>[   81.483315] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11704 16:53:39.030665  <3>[   81.483698] PM: Some devices failed to suspend, or early wake event detected

11705 16:53:39.033990  <6>[   81.544199] OOM killer enabled.

11706 16:53:39.037502  <6>[   81.547611] Restarting tasks ... done.

11707 16:53:39.043984  <5>[   81.552433] random: crng reseeded on system resumption

11708 16:53:39.046990  <6>[   81.558841] PM: suspend exit

11709 16:53:39.050641  rtcwake: write error

11710 16:53:39.056971  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>

11711 16:53:39.057829  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11713 16:53:39.060454  rtcwake: assuming RTC uses UTC ...

11714 16:53:39.067213  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:45 2023

11715 16:53:39.078709  <6>[   81.589021] PM: suspend entry (s2idle)

11716 16:53:39.081811  <6>[   81.593071] Filesystems sync: 0.000 seconds

11717 16:53:39.088259  <6>[   81.598273] Freezing user space processes

11718 16:53:39.095433  <6>[   81.604174] Freezing user space processes completed (elapsed 0.001 seconds)

11719 16:53:39.098889  <6>[   81.611412] OOM killer disabled.

11720 16:53:39.105094  <6>[   81.614895] Freezing remaining freezable tasks

11721 16:53:39.112056  <6>[   81.620802] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11722 16:53:39.121385  <6>[   81.628471] printk: Suspending console(s) (use no_console_suspend to debug)

11723 16:53:42.311053  <3>[   81.636592] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11724 16:53:42.317806  <3>[   81.636624] elants_i2c 4-0010: PM: failed to suspend async: error -16

11725 16:53:42.324903  <3>[   84.811022] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout

11726 16:53:42.333995  <3>[   84.811047] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11727 16:53:42.341291  <3>[   84.811080] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11728 16:53:42.347590  <3>[   84.811101] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11729 16:53:42.357983  <3>[   84.811444] PM: Some devices failed to suspend, or early wake event detected

11730 16:53:42.360849  <6>[   84.871568] OOM killer enabled.

11731 16:53:42.364269  <6>[   84.874979] Restarting tasks ... done.

11732 16:53:42.370620  <5>[   84.879776] random: crng reseeded on system resumption

11733 16:53:42.374300  <6>[   84.886195] PM: suspend exit

11734 16:53:42.377714  rtcwake: write error

11735 16:53:42.384502  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>

11736 16:53:42.385352  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11738 16:53:42.387179  rtcwake: assuming RTC uses UTC ...

11739 16:53:42.394729  rtcwake: wakeup from "freeze" using rtc0 at Sat Jun  3 16:53:48 2023

11740 16:53:42.406966  <6>[   84.917002] PM: suspend entry (s2idle)

11741 16:53:42.410623  <6>[   84.921104] Filesystems sync: 0.000 seconds

11742 16:53:42.416724  <6>[   84.926386] Freezing user space processes

11743 16:53:42.423676  <6>[   84.932211] Freezing user space processes completed (elapsed 0.001 seconds)

11744 16:53:42.426218  <6>[   84.939453] OOM killer disabled.

11745 16:53:42.433003  <6>[   84.942938] Freezing remaining freezable tasks

11746 16:53:42.440122  <6>[   84.948858] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11747 16:53:42.449737  <6>[   84.956519] printk: Suspending console(s) (use no_console_suspend to debug)

11748 16:53:45.638814  <3>[   84.964981] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16

11749 16:53:45.645380  <3>[   84.965021] elants_i2c 4-0010: PM: failed to suspend async: error -16

11750 16:53:45.652650  <3>[   88.139025] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout

11751 16:53:45.662021  <3>[   88.139049] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110

11752 16:53:45.668733  <3>[   88.139074] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110

11753 16:53:45.675639  <3>[   88.139097] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110

11754 16:53:45.685394  <3>[   88.139424] PM: Some devices failed to suspend, or early wake event detected

11755 16:53:45.688721  <6>[   88.199561] OOM killer enabled.

11756 16:53:45.691583  <6>[   88.202998] Restarting tasks ... done.

11757 16:53:45.698479  <5>[   88.207764] random: crng reseeded on system resumption

11758 16:53:45.701613  <6>[   88.214997] PM: suspend exit

11759 16:53:45.704748  rtcwake: write error

11760 16:53:45.712809  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>

11761 16:53:45.713673  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11763 16:53:45.715424  + set +x

11764 16:53:45.718961  <LAVA_SIGNAL_ENDRUN 0_sleep 10576309_1.5.2.3.1>

11765 16:53:45.719440  <LAVA_TEST_RUNNER EXIT>

11766 16:53:45.720084  Received signal: <ENDRUN> 0_sleep 10576309_1.5.2.3.1
11767 16:53:45.720537  Ending use of test pattern.
11768 16:53:45.720890  Ending test lava.0_sleep (10576309_1.5.2.3.1), duration 66.43
11770 16:53:45.722986  ok: lava_test_shell seems to have completed
11771 16:53:45.724038  rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail

11772 16:53:45.724545  end: 3.1 lava-test-shell (duration 00:01:07) [common]
11773 16:53:45.725004  end: 3 lava-test-retry (duration 00:01:07) [common]
11774 16:53:45.725481  start: 4 finalize (timeout 00:06:24) [common]
11775 16:53:45.725960  start: 4.1 power-off (timeout 00:00:30) [common]
11776 16:53:45.726801  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11777 16:53:45.811582  >> Command sent successfully.

11778 16:53:45.816012  Returned 0 in 0 seconds
11779 16:53:45.916980  end: 4.1 power-off (duration 00:00:00) [common]
11781 16:53:45.918550  start: 4.2 read-feedback (timeout 00:06:24) [common]
11782 16:53:45.919836  Listened to connection for namespace 'common' for up to 1s
11783 16:53:45.920716  Listened to connection for namespace 'common' for up to 1s
11784 16:53:46.920588  Finalising connection for namespace 'common'
11785 16:53:46.921274  Disconnecting from shell: Finalise
11786 16:53:46.921758  / # 
11787 16:53:47.022767  end: 4.2 read-feedback (duration 00:00:01) [common]
11788 16:53:47.023502  end: 4 finalize (duration 00:00:01) [common]
11789 16:53:47.024092  Cleaning after the job
11790 16:53:47.024609  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/ramdisk
11791 16:53:47.065104  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/kernel
11792 16:53:47.089808  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/dtb
11793 16:53:47.090058  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576309/tftp-deploy-3kot0kcr/modules
11794 16:53:47.095796  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576309
11795 16:53:47.230987  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576309
11796 16:53:47.231168  Job finished correctly