Boot log: mt8192-asurada-spherion-r0

    1 16:51:17.012282  lava-dispatcher, installed at version: 2023.03
    2 16:51:17.012503  start: 0 validate
    3 16:51:17.012673  Start time: 2023-06-03 16:51:17.012664+00:00 (UTC)
    4 16:51:17.012847  Using caching service: 'http://localhost/cache/?uri=%s'
    5 16:51:17.013040  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
    6 16:51:17.304401  Using caching service: 'http://localhost/cache/?uri=%s'
    7 16:51:17.304603  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 16:51:17.597834  Using caching service: 'http://localhost/cache/?uri=%s'
    9 16:51:17.598014  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 16:51:17.896357  Using caching service: 'http://localhost/cache/?uri=%s'
   11 16:51:17.896605  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 16:51:18.191175  validate duration: 1.18
   14 16:51:18.191512  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 16:51:18.191643  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 16:51:18.191766  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 16:51:18.191926  Not decompressing ramdisk as can be used compressed.
   18 16:51:18.192089  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
   19 16:51:18.192187  saving as /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/ramdisk/rootfs.cpio.gz
   20 16:51:18.192278  total size: 27151647 (25MB)
   21 16:51:18.193778  progress   0% (0MB)
   22 16:51:18.201367  progress   5% (1MB)
   23 16:51:18.208862  progress  10% (2MB)
   24 16:51:18.216644  progress  15% (3MB)
   25 16:51:18.224120  progress  20% (5MB)
   26 16:51:18.231380  progress  25% (6MB)
   27 16:51:18.238467  progress  30% (7MB)
   28 16:51:18.245901  progress  35% (9MB)
   29 16:51:18.253656  progress  40% (10MB)
   30 16:51:18.260871  progress  45% (11MB)
   31 16:51:18.268204  progress  50% (12MB)
   32 16:51:18.275412  progress  55% (14MB)
   33 16:51:18.282794  progress  60% (15MB)
   34 16:51:18.290156  progress  65% (16MB)
   35 16:51:18.297511  progress  70% (18MB)
   36 16:51:18.304753  progress  75% (19MB)
   37 16:51:18.311974  progress  80% (20MB)
   38 16:51:18.319225  progress  85% (22MB)
   39 16:51:18.326187  progress  90% (23MB)
   40 16:51:18.333301  progress  95% (24MB)
   41 16:51:18.340274  progress 100% (25MB)
   42 16:51:18.340491  25MB downloaded in 0.15s (174.71MB/s)
   43 16:51:18.340688  end: 1.1.1 http-download (duration 00:00:00) [common]
   45 16:51:18.340934  end: 1.1 download-retry (duration 00:00:00) [common]
   46 16:51:18.341020  start: 1.2 download-retry (timeout 00:10:00) [common]
   47 16:51:18.341105  start: 1.2.1 http-download (timeout 00:10:00) [common]
   48 16:51:18.341268  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 16:51:18.341372  saving as /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/kernel/Image
   50 16:51:18.341446  total size: 45746688 (43MB)
   51 16:51:18.341508  No compression specified
   52 16:51:18.342613  progress   0% (0MB)
   53 16:51:18.354509  progress   5% (2MB)
   54 16:51:18.366362  progress  10% (4MB)
   55 16:51:18.378474  progress  15% (6MB)
   56 16:51:18.390411  progress  20% (8MB)
   57 16:51:18.402451  progress  25% (10MB)
   58 16:51:18.414212  progress  30% (13MB)
   59 16:51:18.426170  progress  35% (15MB)
   60 16:51:18.438116  progress  40% (17MB)
   61 16:51:18.450684  progress  45% (19MB)
   62 16:51:18.463313  progress  50% (21MB)
   63 16:51:18.475774  progress  55% (24MB)
   64 16:51:18.489071  progress  60% (26MB)
   65 16:51:18.502299  progress  65% (28MB)
   66 16:51:18.516144  progress  70% (30MB)
   67 16:51:18.529638  progress  75% (32MB)
   68 16:51:18.542587  progress  80% (34MB)
   69 16:51:18.555540  progress  85% (37MB)
   70 16:51:18.568368  progress  90% (39MB)
   71 16:51:18.580865  progress  95% (41MB)
   72 16:51:18.593758  progress 100% (43MB)
   73 16:51:18.593943  43MB downloaded in 0.25s (172.79MB/s)
   74 16:51:18.594153  end: 1.2.1 http-download (duration 00:00:00) [common]
   76 16:51:18.594542  end: 1.2 download-retry (duration 00:00:00) [common]
   77 16:51:18.594675  start: 1.3 download-retry (timeout 00:10:00) [common]
   78 16:51:18.594802  start: 1.3.1 http-download (timeout 00:10:00) [common]
   79 16:51:18.594981  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 16:51:18.595072  saving as /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/dtb/mt8192-asurada-spherion-r0.dtb
   81 16:51:18.595168  total size: 46924 (0MB)
   82 16:51:18.595257  No compression specified
   83 16:51:18.597073  progress  69% (0MB)
   84 16:51:18.597386  progress 100% (0MB)
   85 16:51:18.597584  0MB downloaded in 0.00s (18.55MB/s)
   86 16:51:18.597754  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 16:51:18.598128  end: 1.3 download-retry (duration 00:00:00) [common]
   89 16:51:18.598264  start: 1.4 download-retry (timeout 00:10:00) [common]
   90 16:51:18.598379  start: 1.4.1 http-download (timeout 00:10:00) [common]
   91 16:51:18.598524  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 16:51:18.598619  saving as /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/modules/modules.tar
   93 16:51:18.598733  total size: 8545664 (8MB)
   94 16:51:18.598825  Using unxz to decompress xz
   95 16:51:18.603196  progress   0% (0MB)
   96 16:51:18.625228  progress   5% (0MB)
   97 16:51:18.650475  progress  10% (0MB)
   98 16:51:18.678476  progress  15% (1MB)
   99 16:51:18.703408  progress  20% (1MB)
  100 16:51:18.729395  progress  25% (2MB)
  101 16:51:18.754568  progress  30% (2MB)
  102 16:51:18.780125  progress  35% (2MB)
  103 16:51:18.805086  progress  40% (3MB)
  104 16:51:18.830419  progress  45% (3MB)
  105 16:51:18.854759  progress  50% (4MB)
  106 16:51:18.877933  progress  55% (4MB)
  107 16:51:18.903041  progress  60% (4MB)
  108 16:51:18.928349  progress  65% (5MB)
  109 16:51:18.953998  progress  70% (5MB)
  110 16:51:18.980938  progress  75% (6MB)
  111 16:51:19.010405  progress  80% (6MB)
  112 16:51:19.032967  progress  85% (6MB)
  113 16:51:19.058122  progress  90% (7MB)
  114 16:51:19.081847  progress  95% (7MB)
  115 16:51:19.106201  progress 100% (8MB)
  116 16:51:19.112479  8MB downloaded in 0.51s (15.86MB/s)
  117 16:51:19.112779  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 16:51:19.113049  end: 1.4 download-retry (duration 00:00:01) [common]
  120 16:51:19.113143  start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
  121 16:51:19.113241  start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
  122 16:51:19.113331  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 16:51:19.113426  start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
  124 16:51:19.113636  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628
  125 16:51:19.113778  makedir: /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin
  126 16:51:19.113888  makedir: /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/tests
  127 16:51:19.113984  makedir: /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/results
  128 16:51:19.114101  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-add-keys
  129 16:51:19.114245  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-add-sources
  130 16:51:19.114373  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-background-process-start
  131 16:51:19.114502  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-background-process-stop
  132 16:51:19.114624  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-common-functions
  133 16:51:19.114769  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-echo-ipv4
  134 16:51:19.114895  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-install-packages
  135 16:51:19.115019  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-installed-packages
  136 16:51:19.115139  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-os-build
  137 16:51:19.115260  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-probe-channel
  138 16:51:19.115380  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-probe-ip
  139 16:51:19.115500  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-target-ip
  140 16:51:19.115621  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-target-mac
  141 16:51:19.115740  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-target-storage
  142 16:51:19.115871  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-test-case
  143 16:51:19.116056  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-test-event
  144 16:51:19.116176  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-test-feedback
  145 16:51:19.116297  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-test-raise
  146 16:51:19.116421  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-test-reference
  147 16:51:19.116541  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-test-runner
  148 16:51:19.116669  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-test-set
  149 16:51:19.116799  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-test-shell
  150 16:51:19.116931  Updating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-install-packages (oe)
  151 16:51:19.117079  Updating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/bin/lava-installed-packages (oe)
  152 16:51:19.117206  Creating /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/environment
  153 16:51:19.117308  LAVA metadata
  154 16:51:19.117389  - LAVA_JOB_ID=10576311
  155 16:51:19.117457  - LAVA_DISPATCHER_IP=192.168.201.1
  156 16:51:19.117563  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
  157 16:51:19.117629  skipped lava-vland-overlay
  158 16:51:19.117715  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 16:51:19.117816  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
  160 16:51:19.117885  skipped lava-multinode-overlay
  161 16:51:19.117959  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 16:51:19.118043  start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
  163 16:51:19.118119  Loading test definitions
  164 16:51:19.118213  start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
  165 16:51:19.118288  Using /lava-10576311 at stage 0
  166 16:51:19.118588  uuid=10576311_1.5.2.3.1 testdef=None
  167 16:51:19.118676  end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
  168 16:51:19.118761  start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
  169 16:51:19.119266  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  171 16:51:19.119496  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
  172 16:51:19.120147  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  174 16:51:19.120379  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
  175 16:51:19.120970  runner path: /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10576311_1.5.2.3.1
  176 16:51:19.121123  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  178 16:51:19.121328  Creating lava-test-runner.conf files
  179 16:51:19.121394  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576311/lava-overlay-keyvz628/lava-10576311/0 for stage 0
  180 16:51:19.121501  - 0_v4l2-compliance-mtk-vcodec-enc
  181 16:51:19.121604  end: 1.5.2.3 test-definition (duration 00:00:00) [common]
  182 16:51:19.121689  start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
  183 16:51:19.128349  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  184 16:51:19.128470  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
  185 16:51:19.128558  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  186 16:51:19.128643  end: 1.5.2 lava-overlay (duration 00:00:00) [common]
  187 16:51:19.128730  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
  188 16:51:19.840563  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  189 16:51:19.840928  start: 1.5.4 extract-modules (timeout 00:09:58) [common]
  190 16:51:19.841040  extracting modules file /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576311/extract-overlay-ramdisk-27is50fl/ramdisk
  191 16:51:20.052613  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  192 16:51:20.052783  start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
  193 16:51:20.052880  [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576311/compress-overlay-qzglczdm/overlay-1.5.2.4.tar.gz to ramdisk
  194 16:51:20.052954  [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576311/compress-overlay-qzglczdm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576311/extract-overlay-ramdisk-27is50fl/ramdisk
  195 16:51:20.059221  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  196 16:51:20.059335  start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
  197 16:51:20.059428  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  198 16:51:20.059515  start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
  199 16:51:20.059597  Building ramdisk /var/lib/lava/dispatcher/tmp/10576311/extract-overlay-ramdisk-27is50fl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576311/extract-overlay-ramdisk-27is50fl/ramdisk
  200 16:51:20.653234  >> 230334 blocks

  201 16:51:24.826277  rename /var/lib/lava/dispatcher/tmp/10576311/extract-overlay-ramdisk-27is50fl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/ramdisk/ramdisk.cpio.gz
  202 16:51:24.826753  end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
  203 16:51:24.826917  start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
  204 16:51:24.827058  start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
  205 16:51:24.827189  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/kernel/Image'
  206 16:51:36.776371  Returned 0 in 11 seconds
  207 16:51:36.877241  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/kernel/image.itb
  208 16:51:37.484511  output: FIT description: Kernel Image image with one or more FDT blobs
  209 16:51:37.484883  output: Created:         Sat Jun  3 17:51:37 2023
  210 16:51:37.484968  output:  Image 0 (kernel-1)
  211 16:51:37.485041  output:   Description:  
  212 16:51:37.485104  output:   Created:      Sat Jun  3 17:51:37 2023
  213 16:51:37.485176  output:   Type:         Kernel Image
  214 16:51:37.485238  output:   Compression:  lzma compressed
  215 16:51:37.485296  output:   Data Size:    10083474 Bytes = 9847.14 KiB = 9.62 MiB
  216 16:51:37.485358  output:   Architecture: AArch64
  217 16:51:37.485422  output:   OS:           Linux
  218 16:51:37.485480  output:   Load Address: 0x00000000
  219 16:51:37.485539  output:   Entry Point:  0x00000000
  220 16:51:37.485607  output:   Hash algo:    crc32
  221 16:51:37.485661  output:   Hash value:   b48eba69
  222 16:51:37.485714  output:  Image 1 (fdt-1)
  223 16:51:37.485784  output:   Description:  mt8192-asurada-spherion-r0
  224 16:51:37.485839  output:   Created:      Sat Jun  3 17:51:37 2023
  225 16:51:37.485892  output:   Type:         Flat Device Tree
  226 16:51:37.485957  output:   Compression:  uncompressed
  227 16:51:37.486040  output:   Data Size:    46924 Bytes = 45.82 KiB = 0.04 MiB
  228 16:51:37.486128  output:   Architecture: AArch64
  229 16:51:37.486212  output:   Hash algo:    crc32
  230 16:51:37.486294  output:   Hash value:   1df858fa
  231 16:51:37.486381  output:  Image 2 (ramdisk-1)
  232 16:51:37.486463  output:   Description:  unavailable
  233 16:51:37.486551  output:   Created:      Sat Jun  3 17:51:37 2023
  234 16:51:37.486633  output:   Type:         RAMDisk Image
  235 16:51:37.486724  output:   Compression:  Unknown Compression
  236 16:51:37.486857  output:   Data Size:    40137592 Bytes = 39196.87 KiB = 38.28 MiB
  237 16:51:37.486947  output:   Architecture: AArch64
  238 16:51:37.487039  output:   OS:           Linux
  239 16:51:37.487119  output:   Load Address: unavailable
  240 16:51:37.487174  output:   Entry Point:  unavailable
  241 16:51:37.487228  output:   Hash algo:    crc32
  242 16:51:37.487290  output:   Hash value:   a87cb22e
  243 16:51:37.487346  output:  Default Configuration: 'conf-1'
  244 16:51:37.487399  output:  Configuration 0 (conf-1)
  245 16:51:37.487454  output:   Description:  mt8192-asurada-spherion-r0
  246 16:51:37.487540  output:   Kernel:       kernel-1
  247 16:51:37.487622  output:   Init Ramdisk: ramdisk-1
  248 16:51:37.487711  output:   FDT:          fdt-1
  249 16:51:37.487793  output:   Loadables:    kernel-1
  250 16:51:37.487883  output: 
  251 16:51:37.488149  end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
  252 16:51:37.488259  end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
  253 16:51:37.488361  end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
  254 16:51:37.488459  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
  255 16:51:37.488538  No LXC device requested
  256 16:51:37.488627  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  257 16:51:37.488761  start: 1.7 deploy-device-env (timeout 00:09:41) [common]
  258 16:51:37.488870  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  259 16:51:37.488939  Checking files for TFTP limit of 4294967296 bytes.
  260 16:51:37.489563  end: 1 tftp-deploy (duration 00:00:19) [common]
  261 16:51:37.489699  start: 2 depthcharge-action (timeout 00:05:00) [common]
  262 16:51:37.489825  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  263 16:51:37.489994  substitutions:
  264 16:51:37.490088  - {DTB}: 10576311/tftp-deploy-n2rwzs5_/dtb/mt8192-asurada-spherion-r0.dtb
  265 16:51:37.490187  - {INITRD}: 10576311/tftp-deploy-n2rwzs5_/ramdisk/ramdisk.cpio.gz
  266 16:51:37.490277  - {KERNEL}: 10576311/tftp-deploy-n2rwzs5_/kernel/Image
  267 16:51:37.490379  - {LAVA_MAC}: None
  268 16:51:37.490467  - {PRESEED_CONFIG}: None
  269 16:51:37.490557  - {PRESEED_LOCAL}: None
  270 16:51:37.490643  - {RAMDISK}: 10576311/tftp-deploy-n2rwzs5_/ramdisk/ramdisk.cpio.gz
  271 16:51:37.490747  - {ROOT_PART}: None
  272 16:51:37.490838  - {ROOT}: None
  273 16:51:37.490928  - {SERVER_IP}: 192.168.201.1
  274 16:51:37.491013  - {TEE}: None
  275 16:51:37.491096  Parsed boot commands:
  276 16:51:37.491169  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  277 16:51:37.491349  Parsed boot commands: tftpboot 192.168.201.1 10576311/tftp-deploy-n2rwzs5_/kernel/image.itb 10576311/tftp-deploy-n2rwzs5_/kernel/cmdline 
  278 16:51:37.491439  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  279 16:51:37.491529  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  280 16:51:37.491655  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  281 16:51:37.491781  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  282 16:51:37.491881  Not connected, no need to disconnect.
  283 16:51:37.492042  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  284 16:51:37.492155  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  285 16:51:37.492223  [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
  286 16:51:37.495801  Setting prompt string to ['lava-test: # ']
  287 16:51:37.496215  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  288 16:51:37.496330  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  289 16:51:37.496457  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  290 16:51:37.496587  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  291 16:51:37.496943  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
  292 16:51:42.642985  >> Command sent successfully.

  293 16:51:42.653396  Returned 0 in 5 seconds
  294 16:51:42.754552  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  296 16:51:42.757307  end: 2.2.2 reset-device (duration 00:00:05) [common]
  297 16:51:42.757817  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  298 16:51:42.758309  Setting prompt string to 'Starting depthcharge on Spherion...'
  299 16:51:42.758655  Changing prompt to 'Starting depthcharge on Spherion...'
  300 16:51:42.759055  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  301 16:51:42.760418  [Enter `^Ec?' for help]

  302 16:51:42.919948  

  303 16:51:42.920513  

  304 16:51:42.920853  F0: 102B 0000

  305 16:51:42.921176  

  306 16:51:42.921479  F3: 1001 0000 [0200]

  307 16:51:42.921778  

  308 16:51:42.923080  F3: 1001 0000

  309 16:51:42.923500  

  310 16:51:42.923881  F7: 102D 0000

  311 16:51:42.924230  

  312 16:51:42.926688  F1: 0000 0000

  313 16:51:42.927165  

  314 16:51:42.927515  V0: 0000 0000 [0001]

  315 16:51:42.927833  

  316 16:51:42.930498  00: 0007 8000

  317 16:51:42.930959  

  318 16:51:42.931296  01: 0000 0000

  319 16:51:42.931620  

  320 16:51:42.931917  BP: 0C00 0209 [0000]

  321 16:51:42.933557  

  322 16:51:42.933974  G0: 1182 0000

  323 16:51:42.934385  

  324 16:51:42.934727  EC: 0000 0021 [4000]

  325 16:51:42.937179  

  326 16:51:42.937598  S7: 0000 0000 [0000]

  327 16:51:42.937932  

  328 16:51:42.940605  CC: 0000 0000 [0001]

  329 16:51:42.941063  

  330 16:51:42.941407  T0: 0000 0040 [010F]

  331 16:51:42.941730  

  332 16:51:42.942033  Jump to BL

  333 16:51:42.942332  

  334 16:51:42.967235  

  335 16:51:42.967785  

  336 16:51:42.968152  

  337 16:51:42.974535  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  338 16:51:42.977646  ARM64: Exception handlers installed.

  339 16:51:42.981259  ARM64: Testing exception

  340 16:51:42.984695  ARM64: Done test exception

  341 16:51:42.992145  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  342 16:51:43.003028  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  343 16:51:43.009899  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  344 16:51:43.019670  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  345 16:51:43.026234  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  346 16:51:43.032824  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  347 16:51:43.043733  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  348 16:51:43.050631  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  349 16:51:43.070062  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  350 16:51:43.073203  WDT: Last reset was cold boot

  351 16:51:43.076727  SPI1(PAD0) initialized at 2873684 Hz

  352 16:51:43.079840  SPI5(PAD0) initialized at 992727 Hz

  353 16:51:43.083228  VBOOT: Loading verstage.

  354 16:51:43.090105  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  355 16:51:43.093262  FMAP: Found "FLASH" version 1.1 at 0x20000.

  356 16:51:43.096799  FMAP: base = 0x0 size = 0x800000 #areas = 25

  357 16:51:43.100298  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  358 16:51:43.107397  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  359 16:51:43.113655  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  360 16:51:43.124548  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  361 16:51:43.125181  

  362 16:51:43.125546  

  363 16:51:43.134618  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  364 16:51:43.138379  ARM64: Exception handlers installed.

  365 16:51:43.141339  ARM64: Testing exception

  366 16:51:43.141806  ARM64: Done test exception

  367 16:51:43.147929  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  368 16:51:43.151396  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  369 16:51:43.165696  Probing TPM: . done!

  370 16:51:43.166224  TPM ready after 0 ms

  371 16:51:43.172977  Connected to device vid:did:rid of 1ae0:0028:00

  372 16:51:43.179642  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

  373 16:51:43.238835  Initialized TPM device CR50 revision 0

  374 16:51:43.250662  tlcl_send_startup: Startup return code is 0

  375 16:51:43.251108  TPM: setup succeeded

  376 16:51:43.262648  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  377 16:51:43.271133  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  378 16:51:43.282765  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  379 16:51:43.292025  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  380 16:51:43.295623  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  381 16:51:43.302867  in-header: 03 07 00 00 08 00 00 00 

  382 16:51:43.306394  in-data: aa e4 47 04 13 02 00 00 

  383 16:51:43.309952  Chrome EC: UHEPI supported

  384 16:51:43.316681  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  385 16:51:43.320360  in-header: 03 ad 00 00 08 00 00 00 

  386 16:51:43.324496  in-data: 00 20 20 08 00 00 00 00 

  387 16:51:43.324915  Phase 1

  388 16:51:43.328165  FMAP: area GBB found @ 3f5000 (12032 bytes)

  389 16:51:43.335613  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  390 16:51:43.339138  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  391 16:51:43.342713  Recovery requested (1009000e)

  392 16:51:43.351861  TPM: Extending digest for VBOOT: boot mode into PCR 0

  393 16:51:43.357612  tlcl_extend: response is 0

  394 16:51:43.367744  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  395 16:51:43.373655  tlcl_extend: response is 0

  396 16:51:43.380454  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  397 16:51:43.400797  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  398 16:51:43.407460  BS: bootblock times (exec / console): total (unknown) / 148 ms

  399 16:51:43.407564  

  400 16:51:43.407630  

  401 16:51:43.418056  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  402 16:51:43.421410  ARM64: Exception handlers installed.

  403 16:51:43.421504  ARM64: Testing exception

  404 16:51:43.425197  ARM64: Done test exception

  405 16:51:43.446108  pmic_efuse_setting: Set efuses in 11 msecs

  406 16:51:43.449579  pmwrap_interface_init: Select PMIF_VLD_RDY

  407 16:51:43.455977  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  408 16:51:43.459524  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  409 16:51:43.466409  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  410 16:51:43.470342  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  411 16:51:43.473764  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  412 16:51:43.481043  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  413 16:51:43.485067  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  414 16:51:43.488536  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  415 16:51:43.492195  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  416 16:51:43.499885  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  417 16:51:43.503349  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  418 16:51:43.507037  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  419 16:51:43.510517  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  420 16:51:43.518075  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  421 16:51:43.525118  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  422 16:51:43.529031  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  423 16:51:43.536324  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  424 16:51:43.539804  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  425 16:51:43.547635  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  426 16:51:43.550903  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  427 16:51:43.558563  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  428 16:51:43.562755  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  429 16:51:43.570031  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  430 16:51:43.573275  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  431 16:51:43.580742  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  432 16:51:43.584370  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  433 16:51:43.591362  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  434 16:51:43.594966  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  435 16:51:43.599014  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  436 16:51:43.606904  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  437 16:51:43.610140  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  438 16:51:43.613554  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  439 16:51:43.620917  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  440 16:51:43.624373  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  441 16:51:43.628636  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  442 16:51:43.635801  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  443 16:51:43.639796  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  444 16:51:43.642997  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  445 16:51:43.650737  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  446 16:51:43.654161  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  447 16:51:43.658184  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  448 16:51:43.661716  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  449 16:51:43.665393  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  450 16:51:43.672626  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  451 16:51:43.676642  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  452 16:51:43.680614  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  453 16:51:43.684077  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  454 16:51:43.688169  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  455 16:51:43.691782  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  456 16:51:43.694973  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  457 16:51:43.702404  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  458 16:51:43.709858  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  459 16:51:43.716916  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  460 16:51:43.720756  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  461 16:51:43.731808  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  462 16:51:43.739488  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  463 16:51:43.743060  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  464 16:51:43.747108  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  465 16:51:43.750493  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  466 16:51:43.759356  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0

  467 16:51:43.766012  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  468 16:51:43.770170  [RTC]rtc_osc_init,62: osc32con val = 0xde6f

  469 16:51:43.773067  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  470 16:51:43.783455  [RTC]rtc_get_frequency_meter,154: input=15, output=790

  471 16:51:43.793048  [RTC]rtc_get_frequency_meter,154: input=23, output=979

  472 16:51:43.802578  [RTC]rtc_get_frequency_meter,154: input=19, output=884

  473 16:51:43.811397  [RTC]rtc_get_frequency_meter,154: input=17, output=838

  474 16:51:43.821344  [RTC]rtc_get_frequency_meter,154: input=16, output=814

  475 16:51:43.830701  [RTC]rtc_get_frequency_meter,154: input=15, output=791

  476 16:51:43.840845  [RTC]rtc_get_frequency_meter,154: input=16, output=814

  477 16:51:43.844454  [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16

  478 16:51:43.847883  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f

  479 16:51:43.854918  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  480 16:51:43.858513  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  481 16:51:43.861739  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  482 16:51:43.865605  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  483 16:51:43.869232  ADC[4]: Raw value=902066 ID=7

  484 16:51:43.873229  ADC[3]: Raw value=213336 ID=1

  485 16:51:43.873315  RAM Code: 0x71

  486 16:51:43.876238  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  487 16:51:43.883922  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  488 16:51:43.891216  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  489 16:51:43.898946  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  490 16:51:43.902314  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  491 16:51:43.906367  in-header: 03 07 00 00 08 00 00 00 

  492 16:51:43.909184  in-data: aa e4 47 04 13 02 00 00 

  493 16:51:43.909304  Chrome EC: UHEPI supported

  494 16:51:43.916510  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  495 16:51:43.920775  in-header: 03 ed 00 00 08 00 00 00 

  496 16:51:43.924198  in-data: 80 20 60 08 00 00 00 00 

  497 16:51:43.927837  MRC: failed to locate region type 0.

  498 16:51:43.935716  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  499 16:51:43.939348  DRAM-K: Running full calibration

  500 16:51:43.943089  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  501 16:51:43.946486  header.status = 0x0

  502 16:51:43.950513  header.version = 0x6 (expected: 0x6)

  503 16:51:43.953949  header.size = 0xd00 (expected: 0xd00)

  504 16:51:43.954063  header.flags = 0x0

  505 16:51:43.961086  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  506 16:51:43.978710  read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps

  507 16:51:43.986492  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  508 16:51:43.986636  dram_init: ddr_geometry: 2

  509 16:51:43.989998  [EMI] MDL number = 2

  510 16:51:43.993735  [EMI] Get MDL freq = 0

  511 16:51:43.993840  dram_init: ddr_type: 0

  512 16:51:43.997306  is_discrete_lpddr4: 1

  513 16:51:44.000921  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  514 16:51:44.001092  

  515 16:51:44.001196  

  516 16:51:44.001287  [Bian_co] ETT version 0.0.0.1

  517 16:51:44.008185   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  518 16:51:44.008335  

  519 16:51:44.011982  dramc_set_vcore_voltage set vcore to 650000

  520 16:51:44.012137  Read voltage for 800, 4

  521 16:51:44.015391  Vio18 = 0

  522 16:51:44.015588  Vcore = 650000

  523 16:51:44.015777  Vdram = 0

  524 16:51:44.016029  Vddq = 0

  525 16:51:44.019745  Vmddr = 0

  526 16:51:44.020372  dram_init: config_dvfs: 1

  527 16:51:44.026660  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  528 16:51:44.030898  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  529 16:51:44.034380  [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10

  530 16:51:44.038279  freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10

  531 16:51:44.041106  [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9

  532 16:51:44.047782  freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9

  533 16:51:44.048264  MEM_TYPE=3, freq_sel=18

  534 16:51:44.051081  sv_algorithm_assistance_LP4_1600 

  535 16:51:44.054622  ============ PULL DRAM RESETB DOWN ============

  536 16:51:44.061087  ========== PULL DRAM RESETB DOWN end =========

  537 16:51:44.064486  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  538 16:51:44.067829  =================================== 

  539 16:51:44.071233  LPDDR4 DRAM CONFIGURATION

  540 16:51:44.074580  =================================== 

  541 16:51:44.074932  EX_ROW_EN[0]    = 0x0

  542 16:51:44.077477  EX_ROW_EN[1]    = 0x0

  543 16:51:44.077785  LP4Y_EN      = 0x0

  544 16:51:44.080911  WORK_FSP     = 0x0

  545 16:51:44.081150  WL           = 0x2

  546 16:51:44.084257  RL           = 0x2

  547 16:51:44.084454  BL           = 0x2

  548 16:51:44.087246  RPST         = 0x0

  549 16:51:44.091070  RD_PRE       = 0x0

  550 16:51:44.091240  WR_PRE       = 0x1

  551 16:51:44.093880  WR_PST       = 0x0

  552 16:51:44.094041  DBI_WR       = 0x0

  553 16:51:44.097384  DBI_RD       = 0x0

  554 16:51:44.097540  OTF          = 0x1

  555 16:51:44.100852  =================================== 

  556 16:51:44.104373  =================================== 

  557 16:51:44.104496  ANA top config

  558 16:51:44.107200  =================================== 

  559 16:51:44.110511  DLL_ASYNC_EN            =  0

  560 16:51:44.113727  ALL_SLAVE_EN            =  1

  561 16:51:44.117138  NEW_RANK_MODE           =  1

  562 16:51:44.120363  DLL_IDLE_MODE           =  1

  563 16:51:44.120475  LP45_APHY_COMB_EN       =  1

  564 16:51:44.123829  TX_ODT_DIS              =  1

  565 16:51:44.127253  NEW_8X_MODE             =  1

  566 16:51:44.130267  =================================== 

  567 16:51:44.133753  =================================== 

  568 16:51:44.137265  data_rate                  = 1600

  569 16:51:44.140405  CKR                        = 1

  570 16:51:44.140490  DQ_P2S_RATIO               = 8

  571 16:51:44.143771  =================================== 

  572 16:51:44.147435  CA_P2S_RATIO               = 8

  573 16:51:44.150201  DQ_CA_OPEN                 = 0

  574 16:51:44.153734  DQ_SEMI_OPEN               = 0

  575 16:51:44.157366  CA_SEMI_OPEN               = 0

  576 16:51:44.160302  CA_FULL_RATE               = 0

  577 16:51:44.160377  DQ_CKDIV4_EN               = 1

  578 16:51:44.164448  CA_CKDIV4_EN               = 1

  579 16:51:44.167328  CA_PREDIV_EN               = 0

  580 16:51:44.170775  PH8_DLY                    = 0

  581 16:51:44.174494  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  582 16:51:44.174599  DQ_AAMCK_DIV               = 4

  583 16:51:44.177284  CA_AAMCK_DIV               = 4

  584 16:51:44.181193  CA_ADMCK_DIV               = 4

  585 16:51:44.184509  DQ_TRACK_CA_EN             = 0

  586 16:51:44.187521  CA_PICK                    = 800

  587 16:51:44.191036  CA_MCKIO                   = 800

  588 16:51:44.191174  MCKIO_SEMI                 = 0

  589 16:51:44.194584  PLL_FREQ                   = 3068

  590 16:51:44.198388  DQ_UI_PI_RATIO             = 32

  591 16:51:44.202015  CA_UI_PI_RATIO             = 0

  592 16:51:44.205434  =================================== 

  593 16:51:44.209652  =================================== 

  594 16:51:44.209984  memory_type:LPDDR4         

  595 16:51:44.213113  GP_NUM     : 10       

  596 16:51:44.213356  SRAM_EN    : 1       

  597 16:51:44.217290  MD32_EN    : 0       

  598 16:51:44.220599  =================================== 

  599 16:51:44.221059  [ANA_INIT] >>>>>>>>>>>>>> 

  600 16:51:44.224734  <<<<<< [CONFIGURE PHASE]: ANA_TX

  601 16:51:44.228338  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  602 16:51:44.231630  =================================== 

  603 16:51:44.234946  data_rate = 1600,PCW = 0X7600

  604 16:51:44.238376  =================================== 

  605 16:51:44.241581  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  606 16:51:44.248064  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  607 16:51:44.251336  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  608 16:51:44.257884  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  609 16:51:44.261330  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  610 16:51:44.264884  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  611 16:51:44.265320  [ANA_INIT] flow start 

  612 16:51:44.268358  [ANA_INIT] PLL >>>>>>>> 

  613 16:51:44.271537  [ANA_INIT] PLL <<<<<<<< 

  614 16:51:44.272086  [ANA_INIT] MIDPI >>>>>>>> 

  615 16:51:44.274999  [ANA_INIT] MIDPI <<<<<<<< 

  616 16:51:44.277964  [ANA_INIT] DLL >>>>>>>> 

  617 16:51:44.278395  [ANA_INIT] flow end 

  618 16:51:44.284555  ============ LP4 DIFF to SE enter ============

  619 16:51:44.288118  ============ LP4 DIFF to SE exit  ============

  620 16:51:44.288551  [ANA_INIT] <<<<<<<<<<<<< 

  621 16:51:44.291676  [Flow] Enable top DCM control >>>>> 

  622 16:51:44.294718  [Flow] Enable top DCM control <<<<< 

  623 16:51:44.298242  Enable DLL master slave shuffle 

  624 16:51:44.304864  ============================================================== 

  625 16:51:44.305297  Gating Mode config

  626 16:51:44.311566  ============================================================== 

  627 16:51:44.314929  Config description: 

  628 16:51:44.325018  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  629 16:51:44.331424  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  630 16:51:44.334883  SELPH_MODE            0: By rank         1: By Phase 

  631 16:51:44.341693  ============================================================== 

  632 16:51:44.345149  GAT_TRACK_EN                 =  1

  633 16:51:44.348117  RX_GATING_MODE               =  2

  634 16:51:44.348550  RX_GATING_TRACK_MODE         =  2

  635 16:51:44.351642  SELPH_MODE                   =  1

  636 16:51:44.355027  PICG_EARLY_EN                =  1

  637 16:51:44.358677  VALID_LAT_VALUE              =  1

  638 16:51:44.365066  ============================================================== 

  639 16:51:44.368446  Enter into Gating configuration >>>> 

  640 16:51:44.371939  Exit from Gating configuration <<<< 

  641 16:51:44.374926  Enter into  DVFS_PRE_config >>>>> 

  642 16:51:44.385516  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  643 16:51:44.388329  Exit from  DVFS_PRE_config <<<<< 

  644 16:51:44.391572  Enter into PICG configuration >>>> 

  645 16:51:44.394997  Exit from PICG configuration <<<< 

  646 16:51:44.398660  [RX_INPUT] configuration >>>>> 

  647 16:51:44.401516  [RX_INPUT] configuration <<<<< 

  648 16:51:44.404839  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  649 16:51:44.412255  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  650 16:51:44.415919  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  651 16:51:44.422460  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  652 16:51:44.429264  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  653 16:51:44.436137  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  654 16:51:44.438939  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  655 16:51:44.442539  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  656 16:51:44.446025  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  657 16:51:44.452560  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  658 16:51:44.456250  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  659 16:51:44.459353  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  660 16:51:44.462368  =================================== 

  661 16:51:44.465979  LPDDR4 DRAM CONFIGURATION

  662 16:51:44.469500  =================================== 

  663 16:51:44.472566  EX_ROW_EN[0]    = 0x0

  664 16:51:44.473044  EX_ROW_EN[1]    = 0x0

  665 16:51:44.475909  LP4Y_EN      = 0x0

  666 16:51:44.476384  WORK_FSP     = 0x0

  667 16:51:44.479413  WL           = 0x2

  668 16:51:44.480009  RL           = 0x2

  669 16:51:44.482723  BL           = 0x2

  670 16:51:44.483150  RPST         = 0x0

  671 16:51:44.486503  RD_PRE       = 0x0

  672 16:51:44.486951  WR_PRE       = 0x1

  673 16:51:44.489409  WR_PST       = 0x0

  674 16:51:44.489836  DBI_WR       = 0x0

  675 16:51:44.492930  DBI_RD       = 0x0

  676 16:51:44.493354  OTF          = 0x1

  677 16:51:44.496158  =================================== 

  678 16:51:44.499574  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  679 16:51:44.506154  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  680 16:51:44.509189  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  681 16:51:44.512808  =================================== 

  682 16:51:44.516171  LPDDR4 DRAM CONFIGURATION

  683 16:51:44.519668  =================================== 

  684 16:51:44.520183  EX_ROW_EN[0]    = 0x10

  685 16:51:44.522787  EX_ROW_EN[1]    = 0x0

  686 16:51:44.526352  LP4Y_EN      = 0x0

  687 16:51:44.526835  WORK_FSP     = 0x0

  688 16:51:44.529308  WL           = 0x2

  689 16:51:44.529908  RL           = 0x2

  690 16:51:44.532893  BL           = 0x2

  691 16:51:44.533347  RPST         = 0x0

  692 16:51:44.536327  RD_PRE       = 0x0

  693 16:51:44.536752  WR_PRE       = 0x1

  694 16:51:44.539509  WR_PST       = 0x0

  695 16:51:44.539984  DBI_WR       = 0x0

  696 16:51:44.542545  DBI_RD       = 0x0

  697 16:51:44.543102  OTF          = 0x1

  698 16:51:44.546011  =================================== 

  699 16:51:44.552508  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  700 16:51:44.556407  nWR fixed to 40

  701 16:51:44.560094  [ModeRegInit_LP4] CH0 RK0

  702 16:51:44.560541  [ModeRegInit_LP4] CH0 RK1

  703 16:51:44.563396  [ModeRegInit_LP4] CH1 RK0

  704 16:51:44.566717  [ModeRegInit_LP4] CH1 RK1

  705 16:51:44.567268  match AC timing 13

  706 16:51:44.573189  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  707 16:51:44.576281  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  708 16:51:44.579773  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  709 16:51:44.586354  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  710 16:51:44.589800  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  711 16:51:44.590235  [EMI DOE] emi_dcm 0

  712 16:51:44.596659  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  713 16:51:44.597086  ==

  714 16:51:44.600114  Dram Type= 6, Freq= 0, CH_0, rank 0

  715 16:51:44.603596  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  716 16:51:44.604142  ==

  717 16:51:44.609901  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  718 16:51:44.616618  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  719 16:51:44.624208  [CA 0] Center 37 (7~68) winsize 62

  720 16:51:44.627690  [CA 1] Center 37 (6~68) winsize 63

  721 16:51:44.630953  [CA 2] Center 35 (5~66) winsize 62

  722 16:51:44.634233  [CA 3] Center 34 (4~65) winsize 62

  723 16:51:44.638240  [CA 4] Center 33 (3~64) winsize 62

  724 16:51:44.640803  [CA 5] Center 33 (3~64) winsize 62

  725 16:51:44.641236  

  726 16:51:44.644072  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  727 16:51:44.644506  

  728 16:51:44.647349  [CATrainingPosCal] consider 1 rank data

  729 16:51:44.650699  u2DelayCellTimex100 = 270/100 ps

  730 16:51:44.654092  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  731 16:51:44.657574  CA1 delay=37 (6~68),Diff = 4 PI (28 cell)

  732 16:51:44.663980  CA2 delay=35 (5~66),Diff = 2 PI (14 cell)

  733 16:51:44.667318  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  734 16:51:44.670997  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

  735 16:51:44.674210  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  736 16:51:44.674642  

  737 16:51:44.677836  CA PerBit enable=1, Macro0, CA PI delay=33

  738 16:51:44.678268  

  739 16:51:44.680831  [CBTSetCACLKResult] CA Dly = 33

  740 16:51:44.681258  CS Dly: 5 (0~36)

  741 16:51:44.684451  ==

  742 16:51:44.684881  Dram Type= 6, Freq= 0, CH_0, rank 1

  743 16:51:44.690581  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  744 16:51:44.691140  ==

  745 16:51:44.693940  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  746 16:51:44.701144  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  747 16:51:44.710963  [CA 0] Center 37 (6~68) winsize 63

  748 16:51:44.713786  [CA 1] Center 37 (6~68) winsize 63

  749 16:51:44.717149  [CA 2] Center 35 (5~66) winsize 62

  750 16:51:44.720220  [CA 3] Center 35 (4~66) winsize 63

  751 16:51:44.723802  [CA 4] Center 34 (4~65) winsize 62

  752 16:51:44.727366  [CA 5] Center 33 (3~64) winsize 62

  753 16:51:44.727784  

  754 16:51:44.730424  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  755 16:51:44.730866  

  756 16:51:44.733771  [CATrainingPosCal] consider 2 rank data

  757 16:51:44.737184  u2DelayCellTimex100 = 270/100 ps

  758 16:51:44.740622  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  759 16:51:44.744090  CA1 delay=37 (6~68),Diff = 4 PI (28 cell)

  760 16:51:44.750365  CA2 delay=35 (5~66),Diff = 2 PI (14 cell)

  761 16:51:44.754291  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  762 16:51:44.757085  CA4 delay=34 (4~64),Diff = 1 PI (7 cell)

  763 16:51:44.760561  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  764 16:51:44.761012  

  765 16:51:44.764129  CA PerBit enable=1, Macro0, CA PI delay=33

  766 16:51:44.764571  

  767 16:51:44.767360  [CBTSetCACLKResult] CA Dly = 33

  768 16:51:44.767896  CS Dly: 5 (0~37)

  769 16:51:44.768400  

  770 16:51:44.770933  ----->DramcWriteLeveling(PI) begin...

  771 16:51:44.773573  ==

  772 16:51:44.777302  Dram Type= 6, Freq= 0, CH_0, rank 0

  773 16:51:44.780649  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  774 16:51:44.781139  ==

  775 16:51:44.784518  Write leveling (Byte 0): 30 => 30

  776 16:51:44.785032  Write leveling (Byte 1): 30 => 30

  777 16:51:44.787990  DramcWriteLeveling(PI) end<-----

  778 16:51:44.788442  

  779 16:51:44.788936  ==

  780 16:51:44.792029  Dram Type= 6, Freq= 0, CH_0, rank 0

  781 16:51:44.795094  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  782 16:51:44.798491  ==

  783 16:51:44.798915  [Gating] SW mode calibration

  784 16:51:44.805368  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  785 16:51:44.812309  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  786 16:51:44.815323   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  787 16:51:44.822245   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  788 16:51:44.825973   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  789 16:51:44.828870   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  790 16:51:44.832328   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  791 16:51:44.838796   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  792 16:51:44.842265   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  793 16:51:44.845866   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  794 16:51:44.852034   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  795 16:51:44.855942   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  796 16:51:44.859114   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  797 16:51:44.865309   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  798 16:51:44.869066   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  799 16:51:44.872496   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 16:51:44.878706   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 16:51:44.882201   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 16:51:44.885925   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 16:51:44.892298   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  804 16:51:44.895761   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

  805 16:51:44.898789   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  806 16:51:44.905500   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  807 16:51:44.908968   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  808 16:51:44.911847   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  809 16:51:44.918752   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  810 16:51:44.922215   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  811 16:51:44.925842   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  812 16:51:44.928710   0  9  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  813 16:51:44.935757   0  9 12 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (1 1)

  814 16:51:44.938759   0  9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

  815 16:51:44.942364   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  816 16:51:44.949132   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  817 16:51:44.952356   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  818 16:51:44.955878   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  819 16:51:44.962471   0 10  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  820 16:51:44.965722   0 10  8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)

  821 16:51:44.968697   0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (0 0)

  822 16:51:44.975478   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  823 16:51:44.978553   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  824 16:51:44.981936   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  825 16:51:44.988626   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  826 16:51:44.992272   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  827 16:51:44.995699   0 11  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  828 16:51:45.002300   0 11  8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

  829 16:51:45.005347   0 11 12 | B1->B0 | 3939 3d3d | 0 0 | (0 0) (1 1)

  830 16:51:45.008652   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  831 16:51:45.015374   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  832 16:51:45.018962   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  833 16:51:45.021972   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  834 16:51:45.028928   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  835 16:51:45.031988   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  836 16:51:45.035455   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  837 16:51:45.038594   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  838 16:51:45.045774   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  839 16:51:45.048991   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  840 16:51:45.052304   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  841 16:51:45.058828   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  842 16:51:45.062567   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  843 16:51:45.065484   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  844 16:51:45.072042   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  845 16:51:45.075679   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  846 16:51:45.079182   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  847 16:51:45.085735   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  848 16:51:45.089070   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  849 16:51:45.092487   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  850 16:51:45.099028   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  851 16:51:45.102537   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  852 16:51:45.105371   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  853 16:51:45.112259   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  854 16:51:45.112907  Total UI for P1: 0, mck2ui 16

  855 16:51:45.115898  best dqsien dly found for B0: ( 0, 14, 10)

  856 16:51:45.122457   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  857 16:51:45.127031  Total UI for P1: 0, mck2ui 16

  858 16:51:45.128823  best dqsien dly found for B1: ( 0, 14, 12)

  859 16:51:45.132273  best DQS0 dly(MCK, UI, PI) = (0, 14, 10)

  860 16:51:45.135648  best DQS1 dly(MCK, UI, PI) = (0, 14, 12)

  861 16:51:45.136261  

  862 16:51:45.139211  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)

  863 16:51:45.141871  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)

  864 16:51:45.145319  [Gating] SW calibration Done

  865 16:51:45.145571  ==

  866 16:51:45.148334  Dram Type= 6, Freq= 0, CH_0, rank 0

  867 16:51:45.151623  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  868 16:51:45.151869  ==

  869 16:51:45.155151  RX Vref Scan: 0

  870 16:51:45.155302  

  871 16:51:45.158510  RX Vref 0 -> 0, step: 1

  872 16:51:45.158671  

  873 16:51:45.158815  RX Delay -130 -> 252, step: 16

  874 16:51:45.165267  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

  875 16:51:45.168667  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

  876 16:51:45.171756  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  877 16:51:45.175323  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  878 16:51:45.178784  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

  879 16:51:45.185232  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

  880 16:51:45.188603  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

  881 16:51:45.192285  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

  882 16:51:45.195714  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

  883 16:51:45.198885  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

  884 16:51:45.205539  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

  885 16:51:45.208764  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

  886 16:51:45.212232  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

  887 16:51:45.215838  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

  888 16:51:45.218998  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

  889 16:51:45.225809  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

  890 16:51:45.226235  ==

  891 16:51:45.229240  Dram Type= 6, Freq= 0, CH_0, rank 0

  892 16:51:45.232845  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  893 16:51:45.233272  ==

  894 16:51:45.233619  DQS Delay:

  895 16:51:45.235543  DQS0 = 0, DQS1 = 0

  896 16:51:45.236066  DQM Delay:

  897 16:51:45.239113  DQM0 = 84, DQM1 = 77

  898 16:51:45.239534  DQ Delay:

  899 16:51:45.242202  DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85

  900 16:51:45.245865  DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85

  901 16:51:45.248858  DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69

  902 16:51:45.252344  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

  903 16:51:45.252765  

  904 16:51:45.253098  

  905 16:51:45.253408  ==

  906 16:51:45.255945  Dram Type= 6, Freq= 0, CH_0, rank 0

  907 16:51:45.258805  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  908 16:51:45.259227  ==

  909 16:51:45.259574  

  910 16:51:45.260100  

  911 16:51:45.262586  	TX Vref Scan disable

  912 16:51:45.265679   == TX Byte 0 ==

  913 16:51:45.269054  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

  914 16:51:45.272627  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

  915 16:51:45.275751   == TX Byte 1 ==

  916 16:51:45.279160  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  917 16:51:45.282052  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  918 16:51:45.282477  ==

  919 16:51:45.285501  Dram Type= 6, Freq= 0, CH_0, rank 0

  920 16:51:45.292376  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  921 16:51:45.292803  ==

  922 16:51:45.304143  TX Vref=22, minBit 5, minWin=27, winSum=442

  923 16:51:45.307252  TX Vref=24, minBit 5, minWin=27, winSum=442

  924 16:51:45.310432  TX Vref=26, minBit 9, minWin=27, winSum=449

  925 16:51:45.313851  TX Vref=28, minBit 9, minWin=27, winSum=449

  926 16:51:45.317014  TX Vref=30, minBit 5, minWin=27, winSum=452

  927 16:51:45.324112  TX Vref=32, minBit 2, minWin=28, winSum=451

  928 16:51:45.327503  [TxChooseVref] Worse bit 2, Min win 28, Win sum 451, Final Vref 32

  929 16:51:45.327936  

  930 16:51:45.330757  Final TX Range 1 Vref 32

  931 16:51:45.331187  

  932 16:51:45.331529  ==

  933 16:51:45.333783  Dram Type= 6, Freq= 0, CH_0, rank 0

  934 16:51:45.337083  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  935 16:51:45.337538  ==

  936 16:51:45.337884  

  937 16:51:45.340826  

  938 16:51:45.341397  	TX Vref Scan disable

  939 16:51:45.343705   == TX Byte 0 ==

  940 16:51:45.347343  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

  941 16:51:45.351011  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

  942 16:51:45.354026   == TX Byte 1 ==

  943 16:51:45.357457  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  944 16:51:45.360850  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  945 16:51:45.363725  

  946 16:51:45.364190  [DATLAT]

  947 16:51:45.364531  Freq=800, CH0 RK0

  948 16:51:45.364850  

  949 16:51:45.367209  DATLAT Default: 0xa

  950 16:51:45.367654  0, 0xFFFF, sum = 0

  951 16:51:45.370859  1, 0xFFFF, sum = 0

  952 16:51:45.371395  2, 0xFFFF, sum = 0

  953 16:51:45.373912  3, 0xFFFF, sum = 0

  954 16:51:45.374372  4, 0xFFFF, sum = 0

  955 16:51:45.377433  5, 0xFFFF, sum = 0

  956 16:51:45.377866  6, 0xFFFF, sum = 0

  957 16:51:45.380448  7, 0xFFFF, sum = 0

  958 16:51:45.384049  8, 0xFFFF, sum = 0

  959 16:51:45.384484  9, 0x0, sum = 1

  960 16:51:45.384832  10, 0x0, sum = 2

  961 16:51:45.387555  11, 0x0, sum = 3

  962 16:51:45.388124  12, 0x0, sum = 4

  963 16:51:45.390430  best_step = 10

  964 16:51:45.390853  

  965 16:51:45.391196  ==

  966 16:51:45.393981  Dram Type= 6, Freq= 0, CH_0, rank 0

  967 16:51:45.396925  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  968 16:51:45.397366  ==

  969 16:51:45.400346  RX Vref Scan: 1

  970 16:51:45.400766  

  971 16:51:45.401102  Set Vref Range= 32 -> 127

  972 16:51:45.401418  

  973 16:51:45.403708  RX Vref 32 -> 127, step: 1

  974 16:51:45.404211  

  975 16:51:45.407363  RX Delay -95 -> 252, step: 8

  976 16:51:45.407787  

  977 16:51:45.410230  Set Vref, RX VrefLevel [Byte0]: 32

  978 16:51:45.414025                           [Byte1]: 32

  979 16:51:45.414449  

  980 16:51:45.417970  Set Vref, RX VrefLevel [Byte0]: 33

  981 16:51:45.421384                           [Byte1]: 33

  982 16:51:45.421808  

  983 16:51:45.424328  Set Vref, RX VrefLevel [Byte0]: 34

  984 16:51:45.428026                           [Byte1]: 34

  985 16:51:45.431512  

  986 16:51:45.431930  Set Vref, RX VrefLevel [Byte0]: 35

  987 16:51:45.434894                           [Byte1]: 35

  988 16:51:45.438975  

  989 16:51:45.439413  Set Vref, RX VrefLevel [Byte0]: 36

  990 16:51:45.443047                           [Byte1]: 36

  991 16:51:45.447105  

  992 16:51:45.447543  Set Vref, RX VrefLevel [Byte0]: 37

  993 16:51:45.450616                           [Byte1]: 37

  994 16:51:45.454783  

  995 16:51:45.455222  Set Vref, RX VrefLevel [Byte0]: 38

  996 16:51:45.458517                           [Byte1]: 38

  997 16:51:45.462475  

  998 16:51:45.463046  Set Vref, RX VrefLevel [Byte0]: 39

  999 16:51:45.465837                           [Byte1]: 39

 1000 16:51:45.469850  

 1001 16:51:45.470291  Set Vref, RX VrefLevel [Byte0]: 40

 1002 16:51:45.473383                           [Byte1]: 40

 1003 16:51:45.477228  

 1004 16:51:45.480511  Set Vref, RX VrefLevel [Byte0]: 41

 1005 16:51:45.480934                           [Byte1]: 41

 1006 16:51:45.484768  

 1007 16:51:45.485190  Set Vref, RX VrefLevel [Byte0]: 42

 1008 16:51:45.488397                           [Byte1]: 42

 1009 16:51:45.492386  

 1010 16:51:45.492828  Set Vref, RX VrefLevel [Byte0]: 43

 1011 16:51:45.495911                           [Byte1]: 43

 1012 16:51:45.499906  

 1013 16:51:45.500403  Set Vref, RX VrefLevel [Byte0]: 44

 1014 16:51:45.503443                           [Byte1]: 44

 1015 16:51:45.507520  

 1016 16:51:45.507941  Set Vref, RX VrefLevel [Byte0]: 45

 1017 16:51:45.510978                           [Byte1]: 45

 1018 16:51:45.515356  

 1019 16:51:45.515776  Set Vref, RX VrefLevel [Byte0]: 46

 1020 16:51:45.518435                           [Byte1]: 46

 1021 16:51:45.522909  

 1022 16:51:45.523351  Set Vref, RX VrefLevel [Byte0]: 47

 1023 16:51:45.526024                           [Byte1]: 47

 1024 16:51:45.530519  

 1025 16:51:45.530956  Set Vref, RX VrefLevel [Byte0]: 48

 1026 16:51:45.533886                           [Byte1]: 48

 1027 16:51:45.538380  

 1028 16:51:45.539042  Set Vref, RX VrefLevel [Byte0]: 49

 1029 16:51:45.541070                           [Byte1]: 49

 1030 16:51:45.545415  

 1031 16:51:45.545852  Set Vref, RX VrefLevel [Byte0]: 50

 1032 16:51:45.549280                           [Byte1]: 50

 1033 16:51:45.553594  

 1034 16:51:45.554147  Set Vref, RX VrefLevel [Byte0]: 51

 1035 16:51:45.556413                           [Byte1]: 51

 1036 16:51:45.560618  

 1037 16:51:45.561037  Set Vref, RX VrefLevel [Byte0]: 52

 1038 16:51:45.564255                           [Byte1]: 52

 1039 16:51:45.568250  

 1040 16:51:45.568666  Set Vref, RX VrefLevel [Byte0]: 53

 1041 16:51:45.571653                           [Byte1]: 53

 1042 16:51:45.575734  

 1043 16:51:45.576217  Set Vref, RX VrefLevel [Byte0]: 54

 1044 16:51:45.579324                           [Byte1]: 54

 1045 16:51:45.583610  

 1046 16:51:45.584066  Set Vref, RX VrefLevel [Byte0]: 55

 1047 16:51:45.586724                           [Byte1]: 55

 1048 16:51:45.591206  

 1049 16:51:45.591619  Set Vref, RX VrefLevel [Byte0]: 56

 1050 16:51:45.594965                           [Byte1]: 56

 1051 16:51:45.599001  

 1052 16:51:45.599485  Set Vref, RX VrefLevel [Byte0]: 57

 1053 16:51:45.601979                           [Byte1]: 57

 1054 16:51:45.606243  

 1055 16:51:45.606760  Set Vref, RX VrefLevel [Byte0]: 58

 1056 16:51:45.609442                           [Byte1]: 58

 1057 16:51:45.614010  

 1058 16:51:45.614427  Set Vref, RX VrefLevel [Byte0]: 59

 1059 16:51:45.617535                           [Byte1]: 59

 1060 16:51:45.621571  

 1061 16:51:45.621984  Set Vref, RX VrefLevel [Byte0]: 60

 1062 16:51:45.624836                           [Byte1]: 60

 1063 16:51:45.629119  

 1064 16:51:45.629532  Set Vref, RX VrefLevel [Byte0]: 61

 1065 16:51:45.632563                           [Byte1]: 61

 1066 16:51:45.636879  

 1067 16:51:45.637321  Set Vref, RX VrefLevel [Byte0]: 62

 1068 16:51:45.640361                           [Byte1]: 62

 1069 16:51:45.644115  

 1070 16:51:45.644531  Set Vref, RX VrefLevel [Byte0]: 63

 1071 16:51:45.647907                           [Byte1]: 63

 1072 16:51:45.651908  

 1073 16:51:45.652373  Set Vref, RX VrefLevel [Byte0]: 64

 1074 16:51:45.655310                           [Byte1]: 64

 1075 16:51:45.659323  

 1076 16:51:45.659741  Set Vref, RX VrefLevel [Byte0]: 65

 1077 16:51:45.663050                           [Byte1]: 65

 1078 16:51:45.666670  

 1079 16:51:45.667153  Set Vref, RX VrefLevel [Byte0]: 66

 1080 16:51:45.670597                           [Byte1]: 66

 1081 16:51:45.674564  

 1082 16:51:45.674979  Set Vref, RX VrefLevel [Byte0]: 67

 1083 16:51:45.678187                           [Byte1]: 67

 1084 16:51:45.682379  

 1085 16:51:45.682863  Set Vref, RX VrefLevel [Byte0]: 68

 1086 16:51:45.685480                           [Byte1]: 68

 1087 16:51:45.689980  

 1088 16:51:45.690392  Set Vref, RX VrefLevel [Byte0]: 69

 1089 16:51:45.693634                           [Byte1]: 69

 1090 16:51:45.697523  

 1091 16:51:45.697939  Set Vref, RX VrefLevel [Byte0]: 70

 1092 16:51:45.701043                           [Byte1]: 70

 1093 16:51:45.705465  

 1094 16:51:45.705974  Set Vref, RX VrefLevel [Byte0]: 71

 1095 16:51:45.708270                           [Byte1]: 71

 1096 16:51:45.712590  

 1097 16:51:45.713004  Set Vref, RX VrefLevel [Byte0]: 72

 1098 16:51:45.716223                           [Byte1]: 72

 1099 16:51:45.720077  

 1100 16:51:45.720515  Set Vref, RX VrefLevel [Byte0]: 73

 1101 16:51:45.723774                           [Byte1]: 73

 1102 16:51:45.727809  

 1103 16:51:45.728299  Set Vref, RX VrefLevel [Byte0]: 74

 1104 16:51:45.730941                           [Byte1]: 74

 1105 16:51:45.735319  

 1106 16:51:45.735755  Set Vref, RX VrefLevel [Byte0]: 75

 1107 16:51:45.741948                           [Byte1]: 75

 1108 16:51:45.742462  

 1109 16:51:45.745265  Set Vref, RX VrefLevel [Byte0]: 76

 1110 16:51:45.748239                           [Byte1]: 76

 1111 16:51:45.748656  

 1112 16:51:45.751620  Set Vref, RX VrefLevel [Byte0]: 77

 1113 16:51:45.755413                           [Byte1]: 77

 1114 16:51:45.756013  

 1115 16:51:45.758483  Final RX Vref Byte 0 = 61 to rank0

 1116 16:51:45.762099  Final RX Vref Byte 1 = 57 to rank0

 1117 16:51:45.765009  Final RX Vref Byte 0 = 61 to rank1

 1118 16:51:45.768588  Final RX Vref Byte 1 = 57 to rank1==

 1119 16:51:45.772241  Dram Type= 6, Freq= 0, CH_0, rank 0

 1120 16:51:45.775215  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1121 16:51:45.778765  ==

 1122 16:51:45.779176  DQS Delay:

 1123 16:51:45.779505  DQS0 = 0, DQS1 = 0

 1124 16:51:45.782385  DQM Delay:

 1125 16:51:45.782798  DQM0 = 88, DQM1 = 79

 1126 16:51:45.783206  DQ Delay:

 1127 16:51:45.785000  DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84

 1128 16:51:45.788953  DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96

 1129 16:51:45.791851  DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76

 1130 16:51:45.795631  DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88

 1131 16:51:45.796104  

 1132 16:51:45.796487  

 1133 16:51:45.805704  [DQSOSCAuto] RK0, (LSB)MR18= 0x290f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps

 1134 16:51:45.808474  CH0 RK0: MR19=606, MR18=290F

 1135 16:51:45.815460  CH0_RK0: MR19=0x606, MR18=0x290F, DQSOSC=399, MR23=63, INC=92, DEC=61

 1136 16:51:45.816216  

 1137 16:51:45.818399  ----->DramcWriteLeveling(PI) begin...

 1138 16:51:45.818818  ==

 1139 16:51:45.822234  Dram Type= 6, Freq= 0, CH_0, rank 1

 1140 16:51:45.825171  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1141 16:51:45.825585  ==

 1142 16:51:45.828625  Write leveling (Byte 0): 29 => 29

 1143 16:51:45.831747  Write leveling (Byte 1): 28 => 28

 1144 16:51:45.835328  DramcWriteLeveling(PI) end<-----

 1145 16:51:45.835881  

 1146 16:51:45.836284  ==

 1147 16:51:45.838395  Dram Type= 6, Freq= 0, CH_0, rank 1

 1148 16:51:45.842164  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1149 16:51:45.842684  ==

 1150 16:51:45.845407  [Gating] SW mode calibration

 1151 16:51:45.851837  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1152 16:51:45.899816  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1153 16:51:45.900621   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1154 16:51:45.901547   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1155 16:51:45.901942   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1156 16:51:45.902288   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1157 16:51:45.902619   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1158 16:51:45.902938   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1159 16:51:45.903252   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1160 16:51:45.903666   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1161 16:51:45.904174   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1162 16:51:45.904596   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1163 16:51:45.904901   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1164 16:51:45.911448   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1165 16:51:45.914225   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1166 16:51:45.917670   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1167 16:51:45.924210   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1168 16:51:45.927429   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1169 16:51:45.930783   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1170 16:51:45.937888   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)

 1171 16:51:45.941192   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1172 16:51:45.944455   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1173 16:51:45.950920   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1174 16:51:45.954724   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1175 16:51:45.957810   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1176 16:51:45.964527   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1177 16:51:45.967652   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1178 16:51:45.970819   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1179 16:51:45.977735   0  9  8 | B1->B0 | 2322 3131 | 1 0 | (0 0) (0 0)

 1180 16:51:45.980888   0  9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)

 1181 16:51:45.984351   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1182 16:51:45.987421   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1183 16:51:45.994222   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1184 16:51:45.997737   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1185 16:51:46.000823   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1186 16:51:46.007557   0 10  4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)

 1187 16:51:46.011292   0 10  8 | B1->B0 | 3131 2828 | 0 0 | (0 1) (0 0)

 1188 16:51:46.014638   0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1189 16:51:46.021063   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1190 16:51:46.024584   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1191 16:51:46.028063   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1192 16:51:46.031297   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1193 16:51:46.038827   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1194 16:51:46.041841   0 11  4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)

 1195 16:51:46.045410   0 11  8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)

 1196 16:51:46.052379   0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)

 1197 16:51:46.055857   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1198 16:51:46.059364   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1199 16:51:46.062349   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1200 16:51:46.069875   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1201 16:51:46.072492   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1202 16:51:46.075951   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1203 16:51:46.082656   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1204 16:51:46.086137   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1205 16:51:46.089744   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1206 16:51:46.096292   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1207 16:51:46.099398   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1208 16:51:46.103048   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1209 16:51:46.109212   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1210 16:51:46.112525   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1211 16:51:46.115853   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1212 16:51:46.119548   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1213 16:51:46.126020   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1214 16:51:46.129523   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1215 16:51:46.132959   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1216 16:51:46.139687   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1217 16:51:46.142735   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1218 16:51:46.146334   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1219 16:51:46.152554   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1220 16:51:46.152969  Total UI for P1: 0, mck2ui 16

 1221 16:51:46.159147  best dqsien dly found for B0: ( 0, 14,  4)

 1222 16:51:46.162654   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1223 16:51:46.165916  Total UI for P1: 0, mck2ui 16

 1224 16:51:46.169606  best dqsien dly found for B1: ( 0, 14,  8)

 1225 16:51:46.172948  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1226 16:51:46.175857  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1227 16:51:46.176338  

 1228 16:51:46.179486  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1229 16:51:46.182832  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1230 16:51:46.186364  [Gating] SW calibration Done

 1231 16:51:46.186787  ==

 1232 16:51:46.190206  Dram Type= 6, Freq= 0, CH_0, rank 1

 1233 16:51:46.192892  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1234 16:51:46.193344  ==

 1235 16:51:46.196221  RX Vref Scan: 0

 1236 16:51:46.196647  

 1237 16:51:46.199666  RX Vref 0 -> 0, step: 1

 1238 16:51:46.200145  

 1239 16:51:46.200575  RX Delay -130 -> 252, step: 16

 1240 16:51:46.206745  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1241 16:51:46.209809  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

 1242 16:51:46.212886  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1243 16:51:46.216066  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1244 16:51:46.219540  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1245 16:51:46.226235  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

 1246 16:51:46.229848  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

 1247 16:51:46.232764  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

 1248 16:51:46.236272  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1249 16:51:46.239685  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1250 16:51:46.246502  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

 1251 16:51:46.250129  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1252 16:51:46.252997  iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224

 1253 16:51:46.256525  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1254 16:51:46.259665  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1255 16:51:46.266450  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1256 16:51:46.266968  ==

 1257 16:51:46.270042  Dram Type= 6, Freq= 0, CH_0, rank 1

 1258 16:51:46.273427  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1259 16:51:46.273861  ==

 1260 16:51:46.274199  DQS Delay:

 1261 16:51:46.276274  DQS0 = 0, DQS1 = 0

 1262 16:51:46.276770  DQM Delay:

 1263 16:51:46.279805  DQM0 = 86, DQM1 = 76

 1264 16:51:46.280270  DQ Delay:

 1265 16:51:46.283139  DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85

 1266 16:51:46.286721  DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101

 1267 16:51:46.289666  DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69

 1268 16:51:46.293124  DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85

 1269 16:51:46.293547  

 1270 16:51:46.293884  

 1271 16:51:46.294196  ==

 1272 16:51:46.296617  Dram Type= 6, Freq= 0, CH_0, rank 1

 1273 16:51:46.300051  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1274 16:51:46.300472  ==

 1275 16:51:46.300913  

 1276 16:51:46.301243  

 1277 16:51:46.303268  	TX Vref Scan disable

 1278 16:51:46.306226   == TX Byte 0 ==

 1279 16:51:46.309828  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1280 16:51:46.313122  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1281 16:51:46.316336   == TX Byte 1 ==

 1282 16:51:46.319808  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1283 16:51:46.323263  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1284 16:51:46.323705  ==

 1285 16:51:46.326753  Dram Type= 6, Freq= 0, CH_0, rank 1

 1286 16:51:46.333069  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1287 16:51:46.333595  ==

 1288 16:51:46.344804  TX Vref=22, minBit 3, minWin=27, winSum=443

 1289 16:51:46.348249  TX Vref=24, minBit 7, minWin=27, winSum=445

 1290 16:51:46.351405  TX Vref=26, minBit 3, minWin=27, winSum=448

 1291 16:51:46.354712  TX Vref=28, minBit 9, minWin=27, winSum=453

 1292 16:51:46.357804  TX Vref=30, minBit 0, minWin=28, winSum=455

 1293 16:51:46.364556  TX Vref=32, minBit 13, minWin=27, winSum=452

 1294 16:51:46.368000  [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30

 1295 16:51:46.368428  

 1296 16:51:46.371713  Final TX Range 1 Vref 30

 1297 16:51:46.372192  

 1298 16:51:46.372619  ==

 1299 16:51:46.374639  Dram Type= 6, Freq= 0, CH_0, rank 1

 1300 16:51:46.378099  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1301 16:51:46.378513  ==

 1302 16:51:46.378875  

 1303 16:51:46.381768  

 1304 16:51:46.382190  	TX Vref Scan disable

 1305 16:51:46.385133   == TX Byte 0 ==

 1306 16:51:46.388335  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1307 16:51:46.391672  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1308 16:51:46.394789   == TX Byte 1 ==

 1309 16:51:46.398392  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1310 16:51:46.401396  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1311 16:51:46.404954  

 1312 16:51:46.405364  [DATLAT]

 1313 16:51:46.405693  Freq=800, CH0 RK1

 1314 16:51:46.406025  

 1315 16:51:46.408446  DATLAT Default: 0xa

 1316 16:51:46.408856  0, 0xFFFF, sum = 0

 1317 16:51:46.411286  1, 0xFFFF, sum = 0

 1318 16:51:46.411719  2, 0xFFFF, sum = 0

 1319 16:51:46.414798  3, 0xFFFF, sum = 0

 1320 16:51:46.415235  4, 0xFFFF, sum = 0

 1321 16:51:46.418278  5, 0xFFFF, sum = 0

 1322 16:51:46.418698  6, 0xFFFF, sum = 0

 1323 16:51:46.421611  7, 0xFFFF, sum = 0

 1324 16:51:46.424895  8, 0xFFFF, sum = 0

 1325 16:51:46.425374  9, 0x0, sum = 1

 1326 16:51:46.425714  10, 0x0, sum = 2

 1327 16:51:46.428036  11, 0x0, sum = 3

 1328 16:51:46.428471  12, 0x0, sum = 4

 1329 16:51:46.431380  best_step = 10

 1330 16:51:46.431805  

 1331 16:51:46.432175  ==

 1332 16:51:46.435002  Dram Type= 6, Freq= 0, CH_0, rank 1

 1333 16:51:46.438325  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1334 16:51:46.438738  ==

 1335 16:51:46.441421  RX Vref Scan: 0

 1336 16:51:46.441830  

 1337 16:51:46.442163  RX Vref 0 -> 0, step: 1

 1338 16:51:46.442469  

 1339 16:51:46.444874  RX Delay -95 -> 252, step: 8

 1340 16:51:46.451402  iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224

 1341 16:51:46.454792  iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224

 1342 16:51:46.458218  iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232

 1343 16:51:46.461696  iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232

 1344 16:51:46.465405  iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224

 1345 16:51:46.471567  iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232

 1346 16:51:46.475059  iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224

 1347 16:51:46.478118  iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224

 1348 16:51:46.481855  iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216

 1349 16:51:46.485315  iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216

 1350 16:51:46.488250  iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224

 1351 16:51:46.494964  iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216

 1352 16:51:46.498484  iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224

 1353 16:51:46.502062  iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216

 1354 16:51:46.504992  iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224

 1355 16:51:46.511950  iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224

 1356 16:51:46.512396  ==

 1357 16:51:46.514821  Dram Type= 6, Freq= 0, CH_0, rank 1

 1358 16:51:46.518418  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1359 16:51:46.518853  ==

 1360 16:51:46.519185  DQS Delay:

 1361 16:51:46.521944  DQS0 = 0, DQS1 = 0

 1362 16:51:46.522352  DQM Delay:

 1363 16:51:46.525510  DQM0 = 87, DQM1 = 78

 1364 16:51:46.525920  DQ Delay:

 1365 16:51:46.528445  DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84

 1366 16:51:46.531719  DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96

 1367 16:51:46.534996  DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68

 1368 16:51:46.538637  DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88

 1369 16:51:46.539049  

 1370 16:51:46.539375  

 1371 16:51:46.545226  [DQSOSCAuto] RK1, (LSB)MR18= 0x2f18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps

 1372 16:51:46.548038  CH0 RK1: MR19=606, MR18=2F18

 1373 16:51:46.555131  CH0_RK1: MR19=0x606, MR18=0x2F18, DQSOSC=397, MR23=63, INC=93, DEC=62

 1374 16:51:46.558161  [RxdqsGatingPostProcess] freq 800

 1375 16:51:46.564905  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1376 16:51:46.565327  Pre-setting of DQS Precalculation

 1377 16:51:46.571552  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1378 16:51:46.572008  ==

 1379 16:51:46.575084  Dram Type= 6, Freq= 0, CH_1, rank 0

 1380 16:51:46.578642  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1381 16:51:46.579067  ==

 1382 16:51:46.585148  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1383 16:51:46.591647  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1384 16:51:46.599658  [CA 0] Center 36 (6~66) winsize 61

 1385 16:51:46.602398  [CA 1] Center 36 (6~66) winsize 61

 1386 16:51:46.605983  [CA 2] Center 34 (4~65) winsize 62

 1387 16:51:46.609306  [CA 3] Center 33 (3~64) winsize 62

 1388 16:51:46.612907  [CA 4] Center 34 (4~65) winsize 62

 1389 16:51:46.615788  [CA 5] Center 33 (3~64) winsize 62

 1390 16:51:46.616252  

 1391 16:51:46.618758  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1392 16:51:46.618840  

 1393 16:51:46.622097  [CATrainingPosCal] consider 1 rank data

 1394 16:51:46.625721  u2DelayCellTimex100 = 270/100 ps

 1395 16:51:46.629208  CA0 delay=36 (6~66),Diff = 3 PI (21 cell)

 1396 16:51:46.632201  CA1 delay=36 (6~66),Diff = 3 PI (21 cell)

 1397 16:51:46.639086  CA2 delay=34 (4~65),Diff = 1 PI (7 cell)

 1398 16:51:46.642523  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 1399 16:51:46.645811  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

 1400 16:51:46.649389  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1401 16:51:46.649471  

 1402 16:51:46.652202  CA PerBit enable=1, Macro0, CA PI delay=33

 1403 16:51:46.652285  

 1404 16:51:46.655809  [CBTSetCACLKResult] CA Dly = 33

 1405 16:51:46.655891  CS Dly: 5 (0~36)

 1406 16:51:46.659441  ==

 1407 16:51:46.659522  Dram Type= 6, Freq= 0, CH_1, rank 1

 1408 16:51:46.665682  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1409 16:51:46.665770  ==

 1410 16:51:46.668625  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1411 16:51:46.675600  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1412 16:51:46.685371  [CA 0] Center 36 (6~66) winsize 61

 1413 16:51:46.688401  [CA 1] Center 36 (6~66) winsize 61

 1414 16:51:46.692433  [CA 2] Center 34 (4~65) winsize 62

 1415 16:51:46.695407  [CA 3] Center 33 (3~64) winsize 62

 1416 16:51:46.699408  [CA 4] Center 34 (4~65) winsize 62

 1417 16:51:46.702753  [CA 5] Center 33 (3~64) winsize 62

 1418 16:51:46.702832  

 1419 16:51:46.706787  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1420 16:51:46.706884  

 1421 16:51:46.710345  [CATrainingPosCal] consider 2 rank data

 1422 16:51:46.713895  u2DelayCellTimex100 = 270/100 ps

 1423 16:51:46.717393  CA0 delay=36 (6~66),Diff = 3 PI (21 cell)

 1424 16:51:46.721399  CA1 delay=36 (6~66),Diff = 3 PI (21 cell)

 1425 16:51:46.724875  CA2 delay=34 (4~65),Diff = 1 PI (7 cell)

 1426 16:51:46.728296  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 1427 16:51:46.731813  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

 1428 16:51:46.734777  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1429 16:51:46.734874  

 1430 16:51:46.738451  CA PerBit enable=1, Macro0, CA PI delay=33

 1431 16:51:46.738549  

 1432 16:51:46.741383  [CBTSetCACLKResult] CA Dly = 33

 1433 16:51:46.741480  CS Dly: 5 (0~36)

 1434 16:51:46.741575  

 1435 16:51:46.744816  ----->DramcWriteLeveling(PI) begin...

 1436 16:51:46.748171  ==

 1437 16:51:46.751583  Dram Type= 6, Freq= 0, CH_1, rank 0

 1438 16:51:46.754990  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1439 16:51:46.755073  ==

 1440 16:51:46.758203  Write leveling (Byte 0): 27 => 27

 1441 16:51:46.761456  Write leveling (Byte 1): 29 => 29

 1442 16:51:46.764834  DramcWriteLeveling(PI) end<-----

 1443 16:51:46.764916  

 1444 16:51:46.764981  ==

 1445 16:51:46.768395  Dram Type= 6, Freq= 0, CH_1, rank 0

 1446 16:51:46.771725  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1447 16:51:46.771807  ==

 1448 16:51:46.774660  [Gating] SW mode calibration

 1449 16:51:46.781635  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1450 16:51:46.784900  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1451 16:51:46.791727   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1452 16:51:46.795152   0  6  4 | B1->B0 | 2322 2323 | 1 0 | (1 1) (1 0)

 1453 16:51:46.798102   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1454 16:51:46.804747   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1455 16:51:46.808594   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1456 16:51:46.811772   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1457 16:51:46.818735   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1458 16:51:46.821973   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1459 16:51:46.825181   0  7  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1460 16:51:46.831768   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1461 16:51:46.835552   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1462 16:51:46.838670   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1463 16:51:46.845008   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1464 16:51:46.848587   0  7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1465 16:51:46.852297   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1466 16:51:46.858781   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1467 16:51:46.861652   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1468 16:51:46.865369   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1469 16:51:46.871897   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1470 16:51:46.875150   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1471 16:51:46.878610   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1472 16:51:46.885152   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1473 16:51:46.888704   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1474 16:51:46.891876   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1475 16:51:46.895514   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1476 16:51:46.902116   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1477 16:51:46.904877   0  9  8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)

 1478 16:51:46.908551   0  9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 1479 16:51:46.920877   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1480 16:51:46.921538   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1481 16:51:46.922212   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1482 16:51:46.928457   0  9 28 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)

 1483 16:51:46.931881   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1484 16:51:46.935249   0 10  4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)

 1485 16:51:46.941753   0 10  8 | B1->B0 | 2e2e 2c2c | 0 0 | (1 1) (1 1)

 1486 16:51:46.944700   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1487 16:51:46.948351   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1488 16:51:46.955137   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1489 16:51:46.958426   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1490 16:51:46.961883   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1491 16:51:46.968422   0 11  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1492 16:51:46.971837   0 11  4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 1493 16:51:46.975142   0 11  8 | B1->B0 | 3434 2f2f | 1 0 | (0 0) (0 0)

 1494 16:51:46.981741   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1495 16:51:46.984765   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1496 16:51:46.988416   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1497 16:51:46.994736   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1498 16:51:46.998092   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1499 16:51:47.001691   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1500 16:51:47.008295   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1501 16:51:47.011737   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1502 16:51:47.014630   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1503 16:51:47.018251   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1504 16:51:47.024889   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1505 16:51:47.027941   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1506 16:51:47.031753   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1507 16:51:47.038102   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1508 16:51:47.041474   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1509 16:51:47.044920   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1510 16:51:47.051675   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1511 16:51:47.054780   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1512 16:51:47.058308   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1513 16:51:47.064988   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1514 16:51:47.067854   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1515 16:51:47.071415   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1516 16:51:47.078373   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1517 16:51:47.081201   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1518 16:51:47.084923  Total UI for P1: 0, mck2ui 16

 1519 16:51:47.088240  best dqsien dly found for B1: ( 0, 14,  6)

 1520 16:51:47.091625   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1521 16:51:47.094822  Total UI for P1: 0, mck2ui 16

 1522 16:51:47.098101  best dqsien dly found for B0: ( 0, 14,  8)

 1523 16:51:47.101468  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1524 16:51:47.104631  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1525 16:51:47.105053  

 1526 16:51:47.107661  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1527 16:51:47.114719  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1528 16:51:47.115187  [Gating] SW calibration Done

 1529 16:51:47.115527  ==

 1530 16:51:47.117848  Dram Type= 6, Freq= 0, CH_1, rank 0

 1531 16:51:47.124964  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1532 16:51:47.125594  ==

 1533 16:51:47.126175  RX Vref Scan: 0

 1534 16:51:47.126648  

 1535 16:51:47.128156  RX Vref 0 -> 0, step: 1

 1536 16:51:47.128605  

 1537 16:51:47.131689  RX Delay -130 -> 252, step: 16

 1538 16:51:47.134643  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

 1539 16:51:47.138089  iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224

 1540 16:51:47.141714  iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240

 1541 16:51:47.148383  iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240

 1542 16:51:47.151306  iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240

 1543 16:51:47.154991  iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224

 1544 16:51:47.157954  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1545 16:51:47.161408  iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240

 1546 16:51:47.164878  iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240

 1547 16:51:47.171201  iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224

 1548 16:51:47.174577  iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240

 1549 16:51:47.178197  iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240

 1550 16:51:47.181768  iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240

 1551 16:51:47.187995  iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240

 1552 16:51:47.191357  iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240

 1553 16:51:47.195044  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

 1554 16:51:47.195466  ==

 1555 16:51:47.198365  Dram Type= 6, Freq= 0, CH_1, rank 0

 1556 16:51:47.201498  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1557 16:51:47.201922  ==

 1558 16:51:47.204754  DQS Delay:

 1559 16:51:47.205174  DQS0 = 0, DQS1 = 0

 1560 16:51:47.208192  DQM Delay:

 1561 16:51:47.208610  DQM0 = 84, DQM1 = 76

 1562 16:51:47.209083  DQ Delay:

 1563 16:51:47.211688  DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85

 1564 16:51:47.214649  DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85

 1565 16:51:47.217987  DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69

 1566 16:51:47.221469  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1567 16:51:47.221893  

 1568 16:51:47.222226  

 1569 16:51:47.222569  ==

 1570 16:51:47.224981  Dram Type= 6, Freq= 0, CH_1, rank 0

 1571 16:51:47.231366  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1572 16:51:47.231796  ==

 1573 16:51:47.232159  

 1574 16:51:47.232467  

 1575 16:51:47.232902  	TX Vref Scan disable

 1576 16:51:47.235272   == TX Byte 0 ==

 1577 16:51:47.238100  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1578 16:51:47.245184  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1579 16:51:47.245622   == TX Byte 1 ==

 1580 16:51:47.248906  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1581 16:51:47.254973  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1582 16:51:47.255419  ==

 1583 16:51:47.258471  Dram Type= 6, Freq= 0, CH_1, rank 0

 1584 16:51:47.261287  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1585 16:51:47.261715  ==

 1586 16:51:47.274722  TX Vref=22, minBit 3, minWin=27, winSum=439

 1587 16:51:47.277994  TX Vref=24, minBit 0, minWin=27, winSum=442

 1588 16:51:47.281289  TX Vref=26, minBit 8, minWin=27, winSum=446

 1589 16:51:47.284375  TX Vref=28, minBit 11, minWin=27, winSum=453

 1590 16:51:47.288016  TX Vref=30, minBit 1, minWin=28, winSum=457

 1591 16:51:47.291464  TX Vref=32, minBit 0, minWin=28, winSum=455

 1592 16:51:47.297836  [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30

 1593 16:51:47.298257  

 1594 16:51:47.301204  Final TX Range 1 Vref 30

 1595 16:51:47.301627  

 1596 16:51:47.302008  ==

 1597 16:51:47.304550  Dram Type= 6, Freq= 0, CH_1, rank 0

 1598 16:51:47.307729  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1599 16:51:47.308222  ==

 1600 16:51:47.308608  

 1601 16:51:47.311206  

 1602 16:51:47.311632  	TX Vref Scan disable

 1603 16:51:47.314214   == TX Byte 0 ==

 1604 16:51:47.317750  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1605 16:51:47.321285  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1606 16:51:47.324294   == TX Byte 1 ==

 1607 16:51:47.327831  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1608 16:51:47.331292  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1609 16:51:47.331704  

 1610 16:51:47.334538  [DATLAT]

 1611 16:51:47.334950  Freq=800, CH1 RK0

 1612 16:51:47.335343  

 1613 16:51:47.337918  DATLAT Default: 0xa

 1614 16:51:47.338331  0, 0xFFFF, sum = 0

 1615 16:51:47.340802  1, 0xFFFF, sum = 0

 1616 16:51:47.341222  2, 0xFFFF, sum = 0

 1617 16:51:47.344242  3, 0xFFFF, sum = 0

 1618 16:51:47.344663  4, 0xFFFF, sum = 0

 1619 16:51:47.348030  5, 0xFFFF, sum = 0

 1620 16:51:47.348461  6, 0xFFFF, sum = 0

 1621 16:51:47.350830  7, 0xFFFF, sum = 0

 1622 16:51:47.351257  8, 0xFFFF, sum = 0

 1623 16:51:47.354316  9, 0x0, sum = 1

 1624 16:51:47.354766  10, 0x0, sum = 2

 1625 16:51:47.357826  11, 0x0, sum = 3

 1626 16:51:47.358253  12, 0x0, sum = 4

 1627 16:51:47.361199  best_step = 10

 1628 16:51:47.361891  

 1629 16:51:47.362253  ==

 1630 16:51:47.364377  Dram Type= 6, Freq= 0, CH_1, rank 0

 1631 16:51:47.367874  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1632 16:51:47.368331  ==

 1633 16:51:47.371313  RX Vref Scan: 1

 1634 16:51:47.371735  

 1635 16:51:47.372131  Set Vref Range= 32 -> 127

 1636 16:51:47.372459  

 1637 16:51:47.374084  RX Vref 32 -> 127, step: 1

 1638 16:51:47.374567  

 1639 16:51:47.377734  RX Delay -95 -> 252, step: 8

 1640 16:51:47.378191  

 1641 16:51:47.380804  Set Vref, RX VrefLevel [Byte0]: 32

 1642 16:51:47.384624                           [Byte1]: 32

 1643 16:51:47.385077  

 1644 16:51:47.387918  Set Vref, RX VrefLevel [Byte0]: 33

 1645 16:51:47.391017                           [Byte1]: 33

 1646 16:51:47.394339  

 1647 16:51:47.394758  Set Vref, RX VrefLevel [Byte0]: 34

 1648 16:51:47.398107                           [Byte1]: 34

 1649 16:51:47.402302  

 1650 16:51:47.402722  Set Vref, RX VrefLevel [Byte0]: 35

 1651 16:51:47.405590                           [Byte1]: 35

 1652 16:51:47.409636  

 1653 16:51:47.410104  Set Vref, RX VrefLevel [Byte0]: 36

 1654 16:51:47.413398                           [Byte1]: 36

 1655 16:51:47.417202  

 1656 16:51:47.417624  Set Vref, RX VrefLevel [Byte0]: 37

 1657 16:51:47.420361                           [Byte1]: 37

 1658 16:51:47.425491  

 1659 16:51:47.425909  Set Vref, RX VrefLevel [Byte0]: 38

 1660 16:51:47.428244                           [Byte1]: 38

 1661 16:51:47.432291  

 1662 16:51:47.432710  Set Vref, RX VrefLevel [Byte0]: 39

 1663 16:51:47.435779                           [Byte1]: 39

 1664 16:51:47.439884  

 1665 16:51:47.440347  Set Vref, RX VrefLevel [Byte0]: 40

 1666 16:51:47.443374                           [Byte1]: 40

 1667 16:51:47.447778  

 1668 16:51:47.448285  Set Vref, RX VrefLevel [Byte0]: 41

 1669 16:51:47.451064                           [Byte1]: 41

 1670 16:51:47.455174  

 1671 16:51:47.455607  Set Vref, RX VrefLevel [Byte0]: 42

 1672 16:51:47.458860                           [Byte1]: 42

 1673 16:51:47.463010  

 1674 16:51:47.463537  Set Vref, RX VrefLevel [Byte0]: 43

 1675 16:51:47.466533                           [Byte1]: 43

 1676 16:51:47.470423  

 1677 16:51:47.470842  Set Vref, RX VrefLevel [Byte0]: 44

 1678 16:51:47.473906                           [Byte1]: 44

 1679 16:51:47.477931  

 1680 16:51:47.478511  Set Vref, RX VrefLevel [Byte0]: 45

 1681 16:51:47.481386                           [Byte1]: 45

 1682 16:51:47.485921  

 1683 16:51:47.486338  Set Vref, RX VrefLevel [Byte0]: 46

 1684 16:51:47.489165                           [Byte1]: 46

 1685 16:51:47.493236  

 1686 16:51:47.493651  Set Vref, RX VrefLevel [Byte0]: 47

 1687 16:51:47.496703                           [Byte1]: 47

 1688 16:51:47.500732  

 1689 16:51:47.504332  Set Vref, RX VrefLevel [Byte0]: 48

 1690 16:51:47.504765                           [Byte1]: 48

 1691 16:51:47.508298  

 1692 16:51:47.508714  Set Vref, RX VrefLevel [Byte0]: 49

 1693 16:51:47.511732                           [Byte1]: 49

 1694 16:51:47.515796  

 1695 16:51:47.516243  Set Vref, RX VrefLevel [Byte0]: 50

 1696 16:51:47.519427                           [Byte1]: 50

 1697 16:51:47.523861  

 1698 16:51:47.524330  Set Vref, RX VrefLevel [Byte0]: 51

 1699 16:51:47.526743                           [Byte1]: 51

 1700 16:51:47.530957  

 1701 16:51:47.531387  Set Vref, RX VrefLevel [Byte0]: 52

 1702 16:51:47.534380                           [Byte1]: 52

 1703 16:51:47.538935  

 1704 16:51:47.539458  Set Vref, RX VrefLevel [Byte0]: 53

 1705 16:51:47.542190                           [Byte1]: 53

 1706 16:51:47.546248  

 1707 16:51:47.546667  Set Vref, RX VrefLevel [Byte0]: 54

 1708 16:51:47.549458                           [Byte1]: 54

 1709 16:51:47.554286  

 1710 16:51:47.554697  Set Vref, RX VrefLevel [Byte0]: 55

 1711 16:51:47.557026                           [Byte1]: 55

 1712 16:51:47.561615  

 1713 16:51:47.562029  Set Vref, RX VrefLevel [Byte0]: 56

 1714 16:51:47.565084                           [Byte1]: 56

 1715 16:51:47.569356  

 1716 16:51:47.569766  Set Vref, RX VrefLevel [Byte0]: 57

 1717 16:51:47.572291                           [Byte1]: 57

 1718 16:51:47.577003  

 1719 16:51:47.577414  Set Vref, RX VrefLevel [Byte0]: 58

 1720 16:51:47.579936                           [Byte1]: 58

 1721 16:51:47.584591  

 1722 16:51:47.585020  Set Vref, RX VrefLevel [Byte0]: 59

 1723 16:51:47.587593                           [Byte1]: 59

 1724 16:51:47.592140  

 1725 16:51:47.592561  Set Vref, RX VrefLevel [Byte0]: 60

 1726 16:51:47.595459                           [Byte1]: 60

 1727 16:51:47.599466  

 1728 16:51:47.599943  Set Vref, RX VrefLevel [Byte0]: 61

 1729 16:51:47.602948                           [Byte1]: 61

 1730 16:51:47.607423  

 1731 16:51:47.608030  Set Vref, RX VrefLevel [Byte0]: 62

 1732 16:51:47.610641                           [Byte1]: 62

 1733 16:51:47.614892  

 1734 16:51:47.615331  Set Vref, RX VrefLevel [Byte0]: 63

 1735 16:51:47.618347                           [Byte1]: 63

 1736 16:51:47.622380  

 1737 16:51:47.622792  Set Vref, RX VrefLevel [Byte0]: 64

 1738 16:51:47.625896                           [Byte1]: 64

 1739 16:51:47.629853  

 1740 16:51:47.630290  Set Vref, RX VrefLevel [Byte0]: 65

 1741 16:51:47.636299                           [Byte1]: 65

 1742 16:51:47.636728  

 1743 16:51:47.639571  Set Vref, RX VrefLevel [Byte0]: 66

 1744 16:51:47.642995                           [Byte1]: 66

 1745 16:51:47.643551  

 1746 16:51:47.646658  Set Vref, RX VrefLevel [Byte0]: 67

 1747 16:51:47.649970                           [Byte1]: 67

 1748 16:51:47.650391  

 1749 16:51:47.653593  Set Vref, RX VrefLevel [Byte0]: 68

 1750 16:51:47.656249                           [Byte1]: 68

 1751 16:51:47.660421  

 1752 16:51:47.660841  Set Vref, RX VrefLevel [Byte0]: 69

 1753 16:51:47.663899                           [Byte1]: 69

 1754 16:51:47.668491  

 1755 16:51:47.669005  Set Vref, RX VrefLevel [Byte0]: 70

 1756 16:51:47.671470                           [Byte1]: 70

 1757 16:51:47.675714  

 1758 16:51:47.676179  Set Vref, RX VrefLevel [Byte0]: 71

 1759 16:51:47.679143                           [Byte1]: 71

 1760 16:51:47.683299  

 1761 16:51:47.683779  Set Vref, RX VrefLevel [Byte0]: 72

 1762 16:51:47.686947                           [Byte1]: 72

 1763 16:51:47.690858  

 1764 16:51:47.691279  Set Vref, RX VrefLevel [Byte0]: 73

 1765 16:51:47.694598                           [Byte1]: 73

 1766 16:51:47.698918  

 1767 16:51:47.699472  Set Vref, RX VrefLevel [Byte0]: 74

 1768 16:51:47.702043                           [Byte1]: 74

 1769 16:51:47.706365  

 1770 16:51:47.706940  Set Vref, RX VrefLevel [Byte0]: 75

 1771 16:51:47.709185                           [Byte1]: 75

 1772 16:51:47.713920  

 1773 16:51:47.714379  Set Vref, RX VrefLevel [Byte0]: 76

 1774 16:51:47.716951                           [Byte1]: 76

 1775 16:51:47.721415  

 1776 16:51:47.721856  Set Vref, RX VrefLevel [Byte0]: 77

 1777 16:51:47.724401                           [Byte1]: 77

 1778 16:51:47.728813  

 1779 16:51:47.729231  Final RX Vref Byte 0 = 60 to rank0

 1780 16:51:47.731927  Final RX Vref Byte 1 = 55 to rank0

 1781 16:51:47.735586  Final RX Vref Byte 0 = 60 to rank1

 1782 16:51:47.739252  Final RX Vref Byte 1 = 55 to rank1==

 1783 16:51:47.741876  Dram Type= 6, Freq= 0, CH_1, rank 0

 1784 16:51:47.748344  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1785 16:51:47.748787  ==

 1786 16:51:47.749121  DQS Delay:

 1787 16:51:47.749426  DQS0 = 0, DQS1 = 0

 1788 16:51:47.751881  DQM Delay:

 1789 16:51:47.752358  DQM0 = 83, DQM1 = 74

 1790 16:51:47.755539  DQ Delay:

 1791 16:51:47.759090  DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84

 1792 16:51:47.759611  DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80

 1793 16:51:47.762655  DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68

 1794 16:51:47.768653  DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76

 1795 16:51:47.769215  

 1796 16:51:47.769542  

 1797 16:51:47.775468  [DQSOSCAuto] RK0, (LSB)MR18= 0x27fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps

 1798 16:51:47.778798  CH1 RK0: MR19=605, MR18=27FC

 1799 16:51:47.785556  CH1_RK0: MR19=0x605, MR18=0x27FC, DQSOSC=400, MR23=63, INC=92, DEC=61

 1800 16:51:47.786084  

 1801 16:51:47.788929  ----->DramcWriteLeveling(PI) begin...

 1802 16:51:47.789434  ==

 1803 16:51:47.791902  Dram Type= 6, Freq= 0, CH_1, rank 1

 1804 16:51:47.795367  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1805 16:51:47.795788  ==

 1806 16:51:47.798703  Write leveling (Byte 0): 27 => 27

 1807 16:51:47.801692  Write leveling (Byte 1): 30 => 30

 1808 16:51:47.805351  DramcWriteLeveling(PI) end<-----

 1809 16:51:47.805768  

 1810 16:51:47.806096  ==

 1811 16:51:47.808821  Dram Type= 6, Freq= 0, CH_1, rank 1

 1812 16:51:47.811855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1813 16:51:47.812303  ==

 1814 16:51:47.815421  [Gating] SW mode calibration

 1815 16:51:47.822018  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1816 16:51:47.828734  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1817 16:51:47.832067   0  6  0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)

 1818 16:51:47.835646   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1819 16:51:47.842282   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1820 16:51:47.845130   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1821 16:51:47.848544   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1822 16:51:47.855182   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1823 16:51:47.858659   0  6 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1824 16:51:47.862346   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1825 16:51:47.868463   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1826 16:51:47.871785   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1827 16:51:47.875463   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1828 16:51:47.881727   0  7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1829 16:51:47.885293   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1830 16:51:47.888911   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1831 16:51:47.891819   0  7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1832 16:51:47.898486   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1833 16:51:47.901928   0  8  0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)

 1834 16:51:47.905488   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1835 16:51:47.911676   0  8  8 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)

 1836 16:51:47.915153   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1837 16:51:47.918730   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1838 16:51:47.925636   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1839 16:51:47.928805   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1840 16:51:47.931630   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1841 16:51:47.938548   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1842 16:51:47.942086   0  9  4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)

 1843 16:51:47.945039   0  9  8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)

 1844 16:51:47.951653   0  9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 1845 16:51:47.955580   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1846 16:51:47.958447   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1847 16:51:47.965178   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1848 16:51:47.968723   0  9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)

 1849 16:51:47.972060   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1850 16:51:47.978553   0 10  4 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 1)

 1851 16:51:47.981941   0 10  8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 1852 16:51:47.985384   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1853 16:51:47.991765   0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1854 16:51:47.995401   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1855 16:51:47.998768   0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1856 16:51:48.001779   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1857 16:51:48.008771   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1858 16:51:48.011732   0 11  4 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)

 1859 16:51:48.015058   0 11  8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)

 1860 16:51:48.022124   0 11 12 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)

 1861 16:51:48.025341   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1862 16:51:48.028677   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1863 16:51:48.035135   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1864 16:51:48.038544   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1865 16:51:48.041941   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1866 16:51:48.048462   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1867 16:51:48.051480   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1868 16:51:48.054923   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1869 16:51:48.061338   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1870 16:51:48.064760   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1871 16:51:48.068741   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1872 16:51:48.075269   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1873 16:51:48.078618   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1874 16:51:48.081711   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1875 16:51:48.088550   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1876 16:51:48.091742   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1877 16:51:48.094961   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1878 16:51:48.101465   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1879 16:51:48.104920   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1880 16:51:48.108429   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1881 16:51:48.111394   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1882 16:51:48.118468   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1883 16:51:48.121669   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1884 16:51:48.125118  Total UI for P1: 0, mck2ui 16

 1885 16:51:48.128073  best dqsien dly found for B0: ( 0, 14,  4)

 1886 16:51:48.131700   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1887 16:51:48.135264  Total UI for P1: 0, mck2ui 16

 1888 16:51:48.138216  best dqsien dly found for B1: ( 0, 14,  8)

 1889 16:51:48.141645  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1890 16:51:48.145084  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1891 16:51:48.145506  

 1892 16:51:48.151427  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1893 16:51:48.155125  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1894 16:51:48.155650  [Gating] SW calibration Done

 1895 16:51:48.158370  ==

 1896 16:51:48.161478  Dram Type= 6, Freq= 0, CH_1, rank 1

 1897 16:51:48.164968  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1898 16:51:48.165388  ==

 1899 16:51:48.165721  RX Vref Scan: 0

 1900 16:51:48.166033  

 1901 16:51:48.168526  RX Vref 0 -> 0, step: 1

 1902 16:51:48.168944  

 1903 16:51:48.171693  RX Delay -130 -> 252, step: 16

 1904 16:51:48.175204  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

 1905 16:51:48.178210  iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240

 1906 16:51:48.184980  iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240

 1907 16:51:48.188546  iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240

 1908 16:51:48.191372  iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240

 1909 16:51:48.194892  iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224

 1910 16:51:48.198305  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1911 16:51:48.201485  iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224

 1912 16:51:48.208044  iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240

 1913 16:51:48.211332  iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240

 1914 16:51:48.214906  iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256

 1915 16:51:48.218492  iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240

 1916 16:51:48.221373  iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240

 1917 16:51:48.228123  iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240

 1918 16:51:48.231859  iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240

 1919 16:51:48.234753  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

 1920 16:51:48.235172  ==

 1921 16:51:48.238197  Dram Type= 6, Freq= 0, CH_1, rank 1

 1922 16:51:48.241781  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1923 16:51:48.245142  ==

 1924 16:51:48.245562  DQS Delay:

 1925 16:51:48.245924  DQS0 = 0, DQS1 = 0

 1926 16:51:48.248439  DQM Delay:

 1927 16:51:48.249035  DQM0 = 82, DQM1 = 78

 1928 16:51:48.251107  DQ Delay:

 1929 16:51:48.254882  DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85

 1930 16:51:48.255431  DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77

 1931 16:51:48.258284  DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69

 1932 16:51:48.261736  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1933 16:51:48.264601  

 1934 16:51:48.265023  

 1935 16:51:48.265356  ==

 1936 16:51:48.268090  Dram Type= 6, Freq= 0, CH_1, rank 1

 1937 16:51:48.271613  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1938 16:51:48.272074  ==

 1939 16:51:48.272416  

 1940 16:51:48.272752  

 1941 16:51:48.274737  	TX Vref Scan disable

 1942 16:51:48.275281   == TX Byte 0 ==

 1943 16:51:48.281421  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1944 16:51:48.284415  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1945 16:51:48.284842   == TX Byte 1 ==

 1946 16:51:48.291009  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1947 16:51:48.295005  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1948 16:51:48.295531  ==

 1949 16:51:48.298004  Dram Type= 6, Freq= 0, CH_1, rank 1

 1950 16:51:48.301257  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1951 16:51:48.301682  ==

 1952 16:51:48.315579  TX Vref=22, minBit 1, minWin=27, winSum=441

 1953 16:51:48.318423  TX Vref=24, minBit 15, minWin=27, winSum=448

 1954 16:51:48.321841  TX Vref=26, minBit 11, minWin=27, winSum=447

 1955 16:51:48.324830  TX Vref=28, minBit 15, minWin=27, winSum=450

 1956 16:51:48.328167  TX Vref=30, minBit 0, minWin=28, winSum=454

 1957 16:51:48.334614  TX Vref=32, minBit 0, minWin=28, winSum=452

 1958 16:51:48.338126  [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30

 1959 16:51:48.338548  

 1960 16:51:48.341731  Final TX Range 1 Vref 30

 1961 16:51:48.342153  

 1962 16:51:48.342489  ==

 1963 16:51:48.344598  Dram Type= 6, Freq= 0, CH_1, rank 1

 1964 16:51:48.348259  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1965 16:51:48.351620  ==

 1966 16:51:48.352081  

 1967 16:51:48.352418  

 1968 16:51:48.352731  	TX Vref Scan disable

 1969 16:51:48.355027   == TX Byte 0 ==

 1970 16:51:48.358473  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1971 16:51:48.364863  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1972 16:51:48.365307   == TX Byte 1 ==

 1973 16:51:48.368293  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1974 16:51:48.371821  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1975 16:51:48.375191  

 1976 16:51:48.375606  [DATLAT]

 1977 16:51:48.375943  Freq=800, CH1 RK1

 1978 16:51:48.376294  

 1979 16:51:48.378623  DATLAT Default: 0xa

 1980 16:51:48.379044  0, 0xFFFF, sum = 0

 1981 16:51:48.381551  1, 0xFFFF, sum = 0

 1982 16:51:48.382033  2, 0xFFFF, sum = 0

 1983 16:51:48.385100  3, 0xFFFF, sum = 0

 1984 16:51:48.385543  4, 0xFFFF, sum = 0

 1985 16:51:48.388640  5, 0xFFFF, sum = 0

 1986 16:51:48.391572  6, 0xFFFF, sum = 0

 1987 16:51:48.392032  7, 0xFFFF, sum = 0

 1988 16:51:48.395146  8, 0xFFFF, sum = 0

 1989 16:51:48.395607  9, 0x0, sum = 1

 1990 16:51:48.395951  10, 0x0, sum = 2

 1991 16:51:48.398609  11, 0x0, sum = 3

 1992 16:51:48.399034  12, 0x0, sum = 4

 1993 16:51:48.401783  best_step = 10

 1994 16:51:48.402219  

 1995 16:51:48.402575  ==

 1996 16:51:48.404885  Dram Type= 6, Freq= 0, CH_1, rank 1

 1997 16:51:48.408214  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1998 16:51:48.408639  ==

 1999 16:51:48.411710  RX Vref Scan: 0

 2000 16:51:48.412176  

 2001 16:51:48.412512  RX Vref 0 -> 0, step: 1

 2002 16:51:48.412827  

 2003 16:51:48.415061  RX Delay -95 -> 252, step: 8

 2004 16:51:48.421759  iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232

 2005 16:51:48.424860  iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232

 2006 16:51:48.428495  iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232

 2007 16:51:48.431972  iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232

 2008 16:51:48.434925  iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240

 2009 16:51:48.442051  iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232

 2010 16:51:48.445649  iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232

 2011 16:51:48.448430  iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232

 2012 16:51:48.452079  iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232

 2013 16:51:48.455069  iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224

 2014 16:51:48.461866  iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232

 2015 16:51:48.464983  iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232

 2016 16:51:48.468547  iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224

 2017 16:51:48.471945  iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232

 2018 16:51:48.475198  iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232

 2019 16:51:48.481849  iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232

 2020 16:51:48.482270  ==

 2021 16:51:48.485191  Dram Type= 6, Freq= 0, CH_1, rank 1

 2022 16:51:48.488723  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2023 16:51:48.489147  ==

 2024 16:51:48.489483  DQS Delay:

 2025 16:51:48.491706  DQS0 = 0, DQS1 = 0

 2026 16:51:48.492150  DQM Delay:

 2027 16:51:48.495472  DQM0 = 80, DQM1 = 76

 2028 16:51:48.496034  DQ Delay:

 2029 16:51:48.498231  DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76

 2030 16:51:48.502114  DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76

 2031 16:51:48.505288  DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68

 2032 16:51:48.508617  DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84

 2033 16:51:48.509045  

 2034 16:51:48.509390  

 2035 16:51:48.518604  [DQSOSCAuto] RK1, (LSB)MR18= 0x1b25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps

 2036 16:51:48.519239  CH1 RK1: MR19=606, MR18=1B25

 2037 16:51:48.525008  CH1_RK1: MR19=0x606, MR18=0x1B25, DQSOSC=400, MR23=63, INC=92, DEC=61

 2038 16:51:48.528446  [RxdqsGatingPostProcess] freq 800

 2039 16:51:48.535201  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2040 16:51:48.538642  Pre-setting of DQS Precalculation

 2041 16:51:48.541701  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2042 16:51:48.548231  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2043 16:51:48.554796  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2044 16:51:48.555238  

 2045 16:51:48.558038  

 2046 16:51:48.558584  [Calibration Summary] 1600 Mbps

 2047 16:51:48.561727  CH 0, Rank 0

 2048 16:51:48.562168  SW Impedance     : PASS

 2049 16:51:48.565244  DUTY Scan        : NO K

 2050 16:51:48.568342  ZQ Calibration   : PASS

 2051 16:51:48.568770  Jitter Meter     : NO K

 2052 16:51:48.571413  CBT Training     : PASS

 2053 16:51:48.574978  Write leveling   : PASS

 2054 16:51:48.575408  RX DQS gating    : PASS

 2055 16:51:48.578503  RX DQ/DQS(RDDQC) : PASS

 2056 16:51:48.581217  TX DQ/DQS        : PASS

 2057 16:51:48.581683  RX DATLAT        : PASS

 2058 16:51:48.584920  RX DQ/DQS(Engine): PASS

 2059 16:51:48.588283  TX OE            : NO K

 2060 16:51:48.588705  All Pass.

 2061 16:51:48.589038  

 2062 16:51:48.589285  CH 0, Rank 1

 2063 16:51:48.591571  SW Impedance     : PASS

 2064 16:51:48.591866  DUTY Scan        : NO K

 2065 16:51:48.594971  ZQ Calibration   : PASS

 2066 16:51:48.597845  Jitter Meter     : NO K

 2067 16:51:48.598071  CBT Training     : PASS

 2068 16:51:48.601245  Write leveling   : PASS

 2069 16:51:48.604844  RX DQS gating    : PASS

 2070 16:51:48.605000  RX DQ/DQS(RDDQC) : PASS

 2071 16:51:48.607763  TX DQ/DQS        : PASS

 2072 16:51:48.611755  RX DATLAT        : PASS

 2073 16:51:48.611885  RX DQ/DQS(Engine): PASS

 2074 16:51:48.615059  TX OE            : NO K

 2075 16:51:48.615173  All Pass.

 2076 16:51:48.615263  

 2077 16:51:48.618038  CH 1, Rank 0

 2078 16:51:48.618157  SW Impedance     : PASS

 2079 16:51:48.621558  DUTY Scan        : NO K

 2080 16:51:48.624363  ZQ Calibration   : PASS

 2081 16:51:48.624463  Jitter Meter     : NO K

 2082 16:51:48.627987  CBT Training     : PASS

 2083 16:51:48.630989  Write leveling   : PASS

 2084 16:51:48.631089  RX DQS gating    : PASS

 2085 16:51:48.634384  RX DQ/DQS(RDDQC) : PASS

 2086 16:51:48.634501  TX DQ/DQS        : PASS

 2087 16:51:48.637683  RX DATLAT        : PASS

 2088 16:51:48.641050  RX DQ/DQS(Engine): PASS

 2089 16:51:48.641150  TX OE            : NO K

 2090 16:51:48.644792  All Pass.

 2091 16:51:48.644892  

 2092 16:51:48.644971  CH 1, Rank 1

 2093 16:51:48.647943  SW Impedance     : PASS

 2094 16:51:48.648049  DUTY Scan        : NO K

 2095 16:51:48.651190  ZQ Calibration   : PASS

 2096 16:51:48.654714  Jitter Meter     : NO K

 2097 16:51:48.654834  CBT Training     : PASS

 2098 16:51:48.657466  Write leveling   : PASS

 2099 16:51:48.661088  RX DQS gating    : PASS

 2100 16:51:48.661220  RX DQ/DQS(RDDQC) : PASS

 2101 16:51:48.664770  TX DQ/DQS        : PASS

 2102 16:51:48.668108  RX DATLAT        : PASS

 2103 16:51:48.668258  RX DQ/DQS(Engine): PASS

 2104 16:51:48.670911  TX OE            : NO K

 2105 16:51:48.671083  All Pass.

 2106 16:51:48.671218  

 2107 16:51:48.674605  DramC Write-DBI off

 2108 16:51:48.678192  	PER_BANK_REFRESH: Hybrid Mode

 2109 16:51:48.678389  TX_TRACKING: ON

 2110 16:51:48.681311  [GetDramInforAfterCalByMRR] Vendor 6.

 2111 16:51:48.684798  [GetDramInforAfterCalByMRR] Revision 606.

 2112 16:51:48.687781  [GetDramInforAfterCalByMRR] Revision 2 0.

 2113 16:51:48.691535  MR0 0x3b3b

 2114 16:51:48.692005  MR8 0x5151

 2115 16:51:48.695034  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2116 16:51:48.695507  

 2117 16:51:48.695838  MR0 0x3b3b

 2118 16:51:48.698005  MR8 0x5151

 2119 16:51:48.701459  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2120 16:51:48.701870  

 2121 16:51:48.707998  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2122 16:51:48.715007  [FAST_K] Save calibration result to emmc

 2123 16:51:48.718205  [FAST_K] Save calibration result to emmc

 2124 16:51:48.718627  dram_init: config_dvfs: 1

 2125 16:51:48.724726  dramc_set_vcore_voltage set vcore to 662500

 2126 16:51:48.725143  Read voltage for 1200, 2

 2127 16:51:48.725474  Vio18 = 0

 2128 16:51:48.728288  Vcore = 662500

 2129 16:51:48.728711  Vdram = 0

 2130 16:51:48.729043  Vddq = 0

 2131 16:51:48.731162  Vmddr = 0

 2132 16:51:48.734645  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2133 16:51:48.741693  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2134 16:51:48.742102  MEM_TYPE=3, freq_sel=15

 2135 16:51:48.744732  sv_algorithm_assistance_LP4_1600 

 2136 16:51:48.751461  ============ PULL DRAM RESETB DOWN ============

 2137 16:51:48.754737  ========== PULL DRAM RESETB DOWN end =========

 2138 16:51:48.758272  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2139 16:51:48.761383  =================================== 

 2140 16:51:48.764860  LPDDR4 DRAM CONFIGURATION

 2141 16:51:48.768418  =================================== 

 2142 16:51:48.771472  EX_ROW_EN[0]    = 0x0

 2143 16:51:48.771888  EX_ROW_EN[1]    = 0x0

 2144 16:51:48.774664  LP4Y_EN      = 0x0

 2145 16:51:48.775079  WORK_FSP     = 0x0

 2146 16:51:48.778042  WL           = 0x4

 2147 16:51:48.778459  RL           = 0x4

 2148 16:51:48.781451  BL           = 0x2

 2149 16:51:48.781867  RPST         = 0x0

 2150 16:51:48.785078  RD_PRE       = 0x0

 2151 16:51:48.785492  WR_PRE       = 0x1

 2152 16:51:48.788062  WR_PST       = 0x0

 2153 16:51:48.788505  DBI_WR       = 0x0

 2154 16:51:48.791723  DBI_RD       = 0x0

 2155 16:51:48.792182  OTF          = 0x1

 2156 16:51:48.795055  =================================== 

 2157 16:51:48.798043  =================================== 

 2158 16:51:48.801624  ANA top config

 2159 16:51:48.805007  =================================== 

 2160 16:51:48.805427  DLL_ASYNC_EN            =  0

 2161 16:51:48.808620  ALL_SLAVE_EN            =  0

 2162 16:51:48.811645  NEW_RANK_MODE           =  1

 2163 16:51:48.814658  DLL_IDLE_MODE           =  1

 2164 16:51:48.818345  LP45_APHY_COMB_EN       =  1

 2165 16:51:48.818760  TX_ODT_DIS              =  1

 2166 16:51:48.821682  NEW_8X_MODE             =  1

 2167 16:51:48.825114  =================================== 

 2168 16:51:48.828299  =================================== 

 2169 16:51:48.831863  data_rate                  = 2400

 2170 16:51:48.835013  CKR                        = 1

 2171 16:51:48.838536  DQ_P2S_RATIO               = 8

 2172 16:51:48.841732  =================================== 

 2173 16:51:48.842246  CA_P2S_RATIO               = 8

 2174 16:51:48.844952  DQ_CA_OPEN                 = 0

 2175 16:51:48.848063  DQ_SEMI_OPEN               = 0

 2176 16:51:48.851600  CA_SEMI_OPEN               = 0

 2177 16:51:48.854865  CA_FULL_RATE               = 0

 2178 16:51:48.858478  DQ_CKDIV4_EN               = 0

 2179 16:51:48.859006  CA_CKDIV4_EN               = 0

 2180 16:51:48.861893  CA_PREDIV_EN               = 0

 2181 16:51:48.865140  PH8_DLY                    = 17

 2182 16:51:48.868642  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2183 16:51:48.871819  DQ_AAMCK_DIV               = 4

 2184 16:51:48.874914  CA_AAMCK_DIV               = 4

 2185 16:51:48.875485  CA_ADMCK_DIV               = 4

 2186 16:51:48.878479  DQ_TRACK_CA_EN             = 0

 2187 16:51:48.881709  CA_PICK                    = 1200

 2188 16:51:48.885141  CA_MCKIO                   = 1200

 2189 16:51:48.888560  MCKIO_SEMI                 = 0

 2190 16:51:48.892107  PLL_FREQ                   = 2366

 2191 16:51:48.895035  DQ_UI_PI_RATIO             = 32

 2192 16:51:48.895450  CA_UI_PI_RATIO             = 0

 2193 16:51:48.898667  =================================== 

 2194 16:51:48.901750  =================================== 

 2195 16:51:48.905239  memory_type:LPDDR4         

 2196 16:51:48.908700  GP_NUM     : 10       

 2197 16:51:48.909114  SRAM_EN    : 1       

 2198 16:51:48.911669  MD32_EN    : 0       

 2199 16:51:48.915100  =================================== 

 2200 16:51:48.918621  [ANA_INIT] >>>>>>>>>>>>>> 

 2201 16:51:48.919033  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2202 16:51:48.925161  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2203 16:51:48.928091  =================================== 

 2204 16:51:48.928508  data_rate = 2400,PCW = 0X5b00

 2205 16:51:48.931738  =================================== 

 2206 16:51:48.934675  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2207 16:51:48.941616  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2208 16:51:48.948420  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2209 16:51:48.951444  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2210 16:51:48.954991  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2211 16:51:48.959093  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2212 16:51:48.961864  [ANA_INIT] flow start 

 2213 16:51:48.962280  [ANA_INIT] PLL >>>>>>>> 

 2214 16:51:48.965528  [ANA_INIT] PLL <<<<<<<< 

 2215 16:51:48.968127  [ANA_INIT] MIDPI >>>>>>>> 

 2216 16:51:48.968545  [ANA_INIT] MIDPI <<<<<<<< 

 2217 16:51:48.971849  [ANA_INIT] DLL >>>>>>>> 

 2218 16:51:48.975033  [ANA_INIT] DLL <<<<<<<< 

 2219 16:51:48.975456  [ANA_INIT] flow end 

 2220 16:51:48.981382  ============ LP4 DIFF to SE enter ============

 2221 16:51:48.984845  ============ LP4 DIFF to SE exit  ============

 2222 16:51:48.988232  [ANA_INIT] <<<<<<<<<<<<< 

 2223 16:51:48.991437  [Flow] Enable top DCM control >>>>> 

 2224 16:51:48.994836  [Flow] Enable top DCM control <<<<< 

 2225 16:51:48.995348  Enable DLL master slave shuffle 

 2226 16:51:49.001460  ============================================================== 

 2227 16:51:49.004845  Gating Mode config

 2228 16:51:49.008046  ============================================================== 

 2229 16:51:49.011731  Config description: 

 2230 16:51:49.021644  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2231 16:51:49.028192  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2232 16:51:49.031696  SELPH_MODE            0: By rank         1: By Phase 

 2233 16:51:49.038561  ============================================================== 

 2234 16:51:49.041856  GAT_TRACK_EN                 =  1

 2235 16:51:49.044952  RX_GATING_MODE               =  2

 2236 16:51:49.048435  RX_GATING_TRACK_MODE         =  2

 2237 16:51:49.048851  SELPH_MODE                   =  1

 2238 16:51:49.051937  PICG_EARLY_EN                =  1

 2239 16:51:49.054883  VALID_LAT_VALUE              =  1

 2240 16:51:49.061268  ============================================================== 

 2241 16:51:49.064691  Enter into Gating configuration >>>> 

 2242 16:51:49.068074  Exit from Gating configuration <<<< 

 2243 16:51:49.071744  Enter into  DVFS_PRE_config >>>>> 

 2244 16:51:49.081531  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2245 16:51:49.084864  Exit from  DVFS_PRE_config <<<<< 

 2246 16:51:49.088312  Enter into PICG configuration >>>> 

 2247 16:51:49.091468  Exit from PICG configuration <<<< 

 2248 16:51:49.095142  [RX_INPUT] configuration >>>>> 

 2249 16:51:49.098102  [RX_INPUT] configuration <<<<< 

 2250 16:51:49.101292  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2251 16:51:49.108442  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2252 16:51:49.114577  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2253 16:51:49.121703  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2254 16:51:49.125090  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2255 16:51:49.131741  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2256 16:51:49.138244  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2257 16:51:49.141554  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2258 16:51:49.144923  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2259 16:51:49.147909  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2260 16:51:49.151501  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2261 16:51:49.157911  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2262 16:51:49.161452  =================================== 

 2263 16:51:49.164914  LPDDR4 DRAM CONFIGURATION

 2264 16:51:49.167860  =================================== 

 2265 16:51:49.168305  EX_ROW_EN[0]    = 0x0

 2266 16:51:49.171240  EX_ROW_EN[1]    = 0x0

 2267 16:51:49.171695  LP4Y_EN      = 0x0

 2268 16:51:49.174684  WORK_FSP     = 0x0

 2269 16:51:49.175180  WL           = 0x4

 2270 16:51:49.177678  RL           = 0x4

 2271 16:51:49.178091  BL           = 0x2

 2272 16:51:49.181379  RPST         = 0x0

 2273 16:51:49.181800  RD_PRE       = 0x0

 2274 16:51:49.184776  WR_PRE       = 0x1

 2275 16:51:49.185192  WR_PST       = 0x0

 2276 16:51:49.188286  DBI_WR       = 0x0

 2277 16:51:49.188702  DBI_RD       = 0x0

 2278 16:51:49.191621  OTF          = 0x1

 2279 16:51:49.194368  =================================== 

 2280 16:51:49.197577  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2281 16:51:49.201024  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2282 16:51:49.207648  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2283 16:51:49.211514  =================================== 

 2284 16:51:49.211934  LPDDR4 DRAM CONFIGURATION

 2285 16:51:49.214957  =================================== 

 2286 16:51:49.217912  EX_ROW_EN[0]    = 0x10

 2287 16:51:49.221321  EX_ROW_EN[1]    = 0x0

 2288 16:51:49.221745  LP4Y_EN      = 0x0

 2289 16:51:49.224607  WORK_FSP     = 0x0

 2290 16:51:49.225027  WL           = 0x4

 2291 16:51:49.227558  RL           = 0x4

 2292 16:51:49.228003  BL           = 0x2

 2293 16:51:49.231023  RPST         = 0x0

 2294 16:51:49.231432  RD_PRE       = 0x0

 2295 16:51:49.234462  WR_PRE       = 0x1

 2296 16:51:49.234956  WR_PST       = 0x0

 2297 16:51:49.237614  DBI_WR       = 0x0

 2298 16:51:49.238147  DBI_RD       = 0x0

 2299 16:51:49.241111  OTF          = 0x1

 2300 16:51:49.244722  =================================== 

 2301 16:51:49.250864  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2302 16:51:49.251282  ==

 2303 16:51:49.254327  Dram Type= 6, Freq= 0, CH_0, rank 0

 2304 16:51:49.257376  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2305 16:51:49.257673  ==

 2306 16:51:49.260880  [Duty_Offset_Calibration]

 2307 16:51:49.261173  	B0:2	B1:-1	CA:1

 2308 16:51:49.261407  

 2309 16:51:49.263928  [DutyScan_Calibration_Flow] k_type=0

 2310 16:51:49.273872  

 2311 16:51:49.274162  ==CLK 0==

 2312 16:51:49.276713  Final CLK duty delay cell = -4

 2313 16:51:49.280959  [-4] MAX Duty = 5031%(X100), DQS PI = 4

 2314 16:51:49.283738  [-4] MIN Duty = 4875%(X100), DQS PI = 30

 2315 16:51:49.287024  [-4] AVG Duty = 4953%(X100)

 2316 16:51:49.287319  

 2317 16:51:49.290069  CH0 CLK Duty spec in!! Max-Min= 156%

 2318 16:51:49.293552  [DutyScan_Calibration_Flow] ====Done====

 2319 16:51:49.293864  

 2320 16:51:49.296909  [DutyScan_Calibration_Flow] k_type=1

 2321 16:51:49.311909  

 2322 16:51:49.312348  ==DQS 0 ==

 2323 16:51:49.315304  Final DQS duty delay cell = -4

 2324 16:51:49.318398  [-4] MAX Duty = 5000%(X100), DQS PI = 48

 2325 16:51:49.321813  [-4] MIN Duty = 4876%(X100), DQS PI = 12

 2326 16:51:49.325284  [-4] AVG Duty = 4938%(X100)

 2327 16:51:49.325692  

 2328 16:51:49.326107  ==DQS 1 ==

 2329 16:51:49.328330  Final DQS duty delay cell = -4

 2330 16:51:49.331780  [-4] MAX Duty = 5124%(X100), DQS PI = 16

 2331 16:51:49.335266  [-4] MIN Duty = 5000%(X100), DQS PI = 44

 2332 16:51:49.338693  [-4] AVG Duty = 5062%(X100)

 2333 16:51:49.339100  

 2334 16:51:49.341668  CH0 DQS 0 Duty spec in!! Max-Min= 124%

 2335 16:51:49.342181  

 2336 16:51:49.345200  CH0 DQS 1 Duty spec in!! Max-Min= 124%

 2337 16:51:49.348809  [DutyScan_Calibration_Flow] ====Done====

 2338 16:51:49.349314  

 2339 16:51:49.351586  [DutyScan_Calibration_Flow] k_type=3

 2340 16:51:49.368845  

 2341 16:51:49.369497  ==DQM 0 ==

 2342 16:51:49.372386  Final DQM duty delay cell = 0

 2343 16:51:49.375932  [0] MAX Duty = 5000%(X100), DQS PI = 54

 2344 16:51:49.378824  [0] MIN Duty = 4907%(X100), DQS PI = 2

 2345 16:51:49.379344  [0] AVG Duty = 4953%(X100)

 2346 16:51:49.382690  

 2347 16:51:49.383221  ==DQM 1 ==

 2348 16:51:49.385721  Final DQM duty delay cell = 0

 2349 16:51:49.389293  [0] MAX Duty = 5156%(X100), DQS PI = 62

 2350 16:51:49.392554  [0] MIN Duty = 4969%(X100), DQS PI = 10

 2351 16:51:49.393141  [0] AVG Duty = 5062%(X100)

 2352 16:51:49.395498  

 2353 16:51:49.398955  CH0 DQM 0 Duty spec in!! Max-Min= 93%

 2354 16:51:49.399517  

 2355 16:51:49.402463  CH0 DQM 1 Duty spec in!! Max-Min= 187%

 2356 16:51:49.405811  [DutyScan_Calibration_Flow] ====Done====

 2357 16:51:49.406375  

 2358 16:51:49.408828  [DutyScan_Calibration_Flow] k_type=2

 2359 16:51:49.424841  

 2360 16:51:49.425409  ==DQ 0 ==

 2361 16:51:49.428146  Final DQ duty delay cell = -4

 2362 16:51:49.431314  [-4] MAX Duty = 5031%(X100), DQS PI = 0

 2363 16:51:49.434491  [-4] MIN Duty = 4844%(X100), DQS PI = 18

 2364 16:51:49.438064  [-4] AVG Duty = 4937%(X100)

 2365 16:51:49.438509  

 2366 16:51:49.438840  ==DQ 1 ==

 2367 16:51:49.441691  Final DQ duty delay cell = 0

 2368 16:51:49.445123  [0] MAX Duty = 5031%(X100), DQS PI = 26

 2369 16:51:49.448018  [0] MIN Duty = 4907%(X100), DQS PI = 46

 2370 16:51:49.448439  [0] AVG Duty = 4969%(X100)

 2371 16:51:49.451494  

 2372 16:51:49.454813  CH0 DQ 0 Duty spec in!! Max-Min= 187%

 2373 16:51:49.455500  

 2374 16:51:49.458362  CH0 DQ 1 Duty spec in!! Max-Min= 124%

 2375 16:51:49.461367  [DutyScan_Calibration_Flow] ====Done====

 2376 16:51:49.461783  ==

 2377 16:51:49.464850  Dram Type= 6, Freq= 0, CH_1, rank 0

 2378 16:51:49.468595  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2379 16:51:49.469042  ==

 2380 16:51:49.471353  [Duty_Offset_Calibration]

 2381 16:51:49.471768  	B0:1	B1:1	CA:2

 2382 16:51:49.472159  

 2383 16:51:49.474804  [DutyScan_Calibration_Flow] k_type=0

 2384 16:51:49.484822  

 2385 16:51:49.485239  ==CLK 0==

 2386 16:51:49.488278  Final CLK duty delay cell = 0

 2387 16:51:49.491657  [0] MAX Duty = 5156%(X100), DQS PI = 24

 2388 16:51:49.494669  [0] MIN Duty = 4969%(X100), DQS PI = 40

 2389 16:51:49.495084  [0] AVG Duty = 5062%(X100)

 2390 16:51:49.498329  

 2391 16:51:49.501701  CH1 CLK Duty spec in!! Max-Min= 187%

 2392 16:51:49.505213  [DutyScan_Calibration_Flow] ====Done====

 2393 16:51:49.505633  

 2394 16:51:49.507884  [DutyScan_Calibration_Flow] k_type=1

 2395 16:51:49.524158  

 2396 16:51:49.524741  ==DQS 0 ==

 2397 16:51:49.527698  Final DQS duty delay cell = 0

 2398 16:51:49.531329  [0] MAX Duty = 5031%(X100), DQS PI = 18

 2399 16:51:49.534083  [0] MIN Duty = 4844%(X100), DQS PI = 48

 2400 16:51:49.534558  [0] AVG Duty = 4937%(X100)

 2401 16:51:49.537301  

 2402 16:51:49.537717  ==DQS 1 ==

 2403 16:51:49.540804  Final DQS duty delay cell = 0

 2404 16:51:49.544293  [0] MAX Duty = 5062%(X100), DQS PI = 36

 2405 16:51:49.547462  [0] MIN Duty = 4907%(X100), DQS PI = 8

 2406 16:51:49.547898  [0] AVG Duty = 4984%(X100)

 2407 16:51:49.550644  

 2408 16:51:49.554239  CH1 DQS 0 Duty spec in!! Max-Min= 187%

 2409 16:51:49.554656  

 2410 16:51:49.557881  CH1 DQS 1 Duty spec in!! Max-Min= 155%

 2411 16:51:49.560697  [DutyScan_Calibration_Flow] ====Done====

 2412 16:51:49.561117  

 2413 16:51:49.564242  [DutyScan_Calibration_Flow] k_type=3

 2414 16:51:49.581139  

 2415 16:51:49.581559  ==DQM 0 ==

 2416 16:51:49.583995  Final DQM duty delay cell = 0

 2417 16:51:49.587550  [0] MAX Duty = 5093%(X100), DQS PI = 18

 2418 16:51:49.590996  [0] MIN Duty = 4875%(X100), DQS PI = 48

 2419 16:51:49.591611  [0] AVG Duty = 4984%(X100)

 2420 16:51:49.594024  

 2421 16:51:49.594459  ==DQM 1 ==

 2422 16:51:49.597273  Final DQM duty delay cell = 0

 2423 16:51:49.600945  [0] MAX Duty = 5156%(X100), DQS PI = 62

 2424 16:51:49.604360  [0] MIN Duty = 4938%(X100), DQS PI = 22

 2425 16:51:49.604772  [0] AVG Duty = 5047%(X100)

 2426 16:51:49.607842  

 2427 16:51:49.610833  CH1 DQM 0 Duty spec in!! Max-Min= 218%

 2428 16:51:49.611247  

 2429 16:51:49.614188  CH1 DQM 1 Duty spec in!! Max-Min= 218%

 2430 16:51:49.617630  [DutyScan_Calibration_Flow] ====Done====

 2431 16:51:49.618045  

 2432 16:51:49.620635  [DutyScan_Calibration_Flow] k_type=2

 2433 16:51:49.637343  

 2434 16:51:49.637755  ==DQ 0 ==

 2435 16:51:49.640825  Final DQ duty delay cell = 0

 2436 16:51:49.644297  [0] MAX Duty = 5124%(X100), DQS PI = 18

 2437 16:51:49.647629  [0] MIN Duty = 4938%(X100), DQS PI = 60

 2438 16:51:49.648131  [0] AVG Duty = 5031%(X100)

 2439 16:51:49.648507  

 2440 16:51:49.650649  ==DQ 1 ==

 2441 16:51:49.653897  Final DQ duty delay cell = 0

 2442 16:51:49.657325  [0] MAX Duty = 5093%(X100), DQS PI = 10

 2443 16:51:49.660759  [0] MIN Duty = 5031%(X100), DQS PI = 2

 2444 16:51:49.661261  [0] AVG Duty = 5062%(X100)

 2445 16:51:49.661600  

 2446 16:51:49.663854  CH1 DQ 0 Duty spec in!! Max-Min= 186%

 2447 16:51:49.664372  

 2448 16:51:49.667575  CH1 DQ 1 Duty spec in!! Max-Min= 62%

 2449 16:51:49.674275  [DutyScan_Calibration_Flow] ====Done====

 2450 16:51:49.677584  nWR fixed to 30

 2451 16:51:49.678054  [ModeRegInit_LP4] CH0 RK0

 2452 16:51:49.681033  [ModeRegInit_LP4] CH0 RK1

 2453 16:51:49.683940  [ModeRegInit_LP4] CH1 RK0

 2454 16:51:49.684466  [ModeRegInit_LP4] CH1 RK1

 2455 16:51:49.687466  match AC timing 7

 2456 16:51:49.691002  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2457 16:51:49.693982  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2458 16:51:49.701036  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2459 16:51:49.704084  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2460 16:51:49.710954  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2461 16:51:49.711376  ==

 2462 16:51:49.714431  Dram Type= 6, Freq= 0, CH_0, rank 0

 2463 16:51:49.717372  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2464 16:51:49.717964  ==

 2465 16:51:49.724480  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2466 16:51:49.727477  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2467 16:51:49.737044  [CA 0] Center 40 (10~71) winsize 62

 2468 16:51:49.740567  [CA 1] Center 39 (9~70) winsize 62

 2469 16:51:49.743913  [CA 2] Center 36 (6~67) winsize 62

 2470 16:51:49.746952  [CA 3] Center 36 (5~67) winsize 63

 2471 16:51:49.750339  [CA 4] Center 35 (5~65) winsize 61

 2472 16:51:49.753815  [CA 5] Center 34 (4~65) winsize 62

 2473 16:51:49.754353  

 2474 16:51:49.757240  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 2475 16:51:49.757818  

 2476 16:51:49.760555  [CATrainingPosCal] consider 1 rank data

 2477 16:51:49.764015  u2DelayCellTimex100 = 270/100 ps

 2478 16:51:49.767054  CA0 delay=40 (10~71),Diff = 6 PI (28 cell)

 2479 16:51:49.774169  CA1 delay=39 (9~70),Diff = 5 PI (24 cell)

 2480 16:51:49.777166  CA2 delay=36 (6~67),Diff = 2 PI (9 cell)

 2481 16:51:49.780668  CA3 delay=36 (5~67),Diff = 2 PI (9 cell)

 2482 16:51:49.783694  CA4 delay=35 (5~65),Diff = 1 PI (4 cell)

 2483 16:51:49.787151  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 2484 16:51:49.787569  

 2485 16:51:49.790760  CA PerBit enable=1, Macro0, CA PI delay=34

 2486 16:51:49.791177  

 2487 16:51:49.793835  [CBTSetCACLKResult] CA Dly = 34

 2488 16:51:49.794256  CS Dly: 7 (0~38)

 2489 16:51:49.797366  ==

 2490 16:51:49.797812  Dram Type= 6, Freq= 0, CH_0, rank 1

 2491 16:51:49.804044  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2492 16:51:49.804471  ==

 2493 16:51:49.807517  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2494 16:51:49.814043  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2495 16:51:49.822933  [CA 0] Center 39 (9~70) winsize 62

 2496 16:51:49.826538  [CA 1] Center 40 (10~70) winsize 61

 2497 16:51:49.829594  [CA 2] Center 36 (6~67) winsize 62

 2498 16:51:49.832639  [CA 3] Center 35 (5~66) winsize 62

 2499 16:51:49.836254  [CA 4] Center 34 (4~65) winsize 62

 2500 16:51:49.839433  [CA 5] Center 34 (4~64) winsize 61

 2501 16:51:49.839566  

 2502 16:51:49.842776  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2503 16:51:49.842884  

 2504 16:51:49.846435  [CATrainingPosCal] consider 2 rank data

 2505 16:51:49.849519  u2DelayCellTimex100 = 270/100 ps

 2506 16:51:49.853079  CA0 delay=40 (10~70),Diff = 6 PI (28 cell)

 2507 16:51:49.859479  CA1 delay=40 (10~70),Diff = 6 PI (28 cell)

 2508 16:51:49.862843  CA2 delay=36 (6~67),Diff = 2 PI (9 cell)

 2509 16:51:49.866131  CA3 delay=35 (5~66),Diff = 1 PI (4 cell)

 2510 16:51:49.869590  CA4 delay=35 (5~65),Diff = 1 PI (4 cell)

 2511 16:51:49.872915  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 2512 16:51:49.873118  

 2513 16:51:49.876248  CA PerBit enable=1, Macro0, CA PI delay=34

 2514 16:51:49.876574  

 2515 16:51:49.879355  [CBTSetCACLKResult] CA Dly = 34

 2516 16:51:49.879691  CS Dly: 8 (0~41)

 2517 16:51:49.882694  

 2518 16:51:49.886579  ----->DramcWriteLeveling(PI) begin...

 2519 16:51:49.886971  ==

 2520 16:51:49.890039  Dram Type= 6, Freq= 0, CH_0, rank 0

 2521 16:51:49.893018  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2522 16:51:49.893531  ==

 2523 16:51:49.896559  Write leveling (Byte 0): 32 => 32

 2524 16:51:49.900071  Write leveling (Byte 1): 29 => 29

 2525 16:51:49.903140  DramcWriteLeveling(PI) end<-----

 2526 16:51:49.903550  

 2527 16:51:49.904004  ==

 2528 16:51:49.906571  Dram Type= 6, Freq= 0, CH_0, rank 0

 2529 16:51:49.909881  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2530 16:51:49.910373  ==

 2531 16:51:49.913404  [Gating] SW mode calibration

 2532 16:51:49.919848  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2533 16:51:49.926699  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2534 16:51:49.929732   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2535 16:51:49.933116   0 15  4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)

 2536 16:51:49.936665   0 15  8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 2537 16:51:49.943171   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2538 16:51:49.946353   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2539 16:51:49.949953   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2540 16:51:49.956218   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2541 16:51:49.959806   0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2542 16:51:49.963352   1  0  0 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)

 2543 16:51:49.969901   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 2544 16:51:49.973206   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2545 16:51:49.975874   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2546 16:51:49.983682   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2547 16:51:49.986329   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2548 16:51:49.989757   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2549 16:51:49.996391   1  0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2550 16:51:49.999801   1  1  0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)

 2551 16:51:50.003307   1  1  4 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)

 2552 16:51:50.009832   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2553 16:51:50.013179   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2554 16:51:50.016280   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2555 16:51:50.023390   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2556 16:51:50.026310   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2557 16:51:50.029495   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2558 16:51:50.032974   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2559 16:51:50.040146   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2560 16:51:50.043024   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2561 16:51:50.046555   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2562 16:51:50.053244   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2563 16:51:50.056646   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2564 16:51:50.059924   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2565 16:51:50.066595   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2566 16:51:50.069626   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2567 16:51:50.073117   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2568 16:51:50.079608   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2569 16:51:50.083239   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2570 16:51:50.086572   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2571 16:51:50.092905   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2572 16:51:50.096253   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2573 16:51:50.099793   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2574 16:51:50.106096   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2575 16:51:50.109804   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2576 16:51:50.112885  Total UI for P1: 0, mck2ui 16

 2577 16:51:50.116050  best dqsien dly found for B0: ( 1,  4,  0)

 2578 16:51:50.119497  Total UI for P1: 0, mck2ui 16

 2579 16:51:50.123522  best dqsien dly found for B1: ( 1,  4,  0)

 2580 16:51:50.126217  best DQS0 dly(MCK, UI, PI) = (1, 4, 0)

 2581 16:51:50.129837  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2582 16:51:50.130293  

 2583 16:51:50.133464  best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2584 16:51:50.136132  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2585 16:51:50.139763  [Gating] SW calibration Done

 2586 16:51:50.140243  ==

 2587 16:51:50.143220  Dram Type= 6, Freq= 0, CH_0, rank 0

 2588 16:51:50.146637  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2589 16:51:50.147071  ==

 2590 16:51:50.149580  RX Vref Scan: 0

 2591 16:51:50.149955  

 2592 16:51:50.150378  RX Vref 0 -> 0, step: 1

 2593 16:51:50.153061  

 2594 16:51:50.153487  RX Delay -40 -> 252, step: 8

 2595 16:51:50.159818  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 2596 16:51:50.163145  iDelay=200, Bit 1, Center 115 (40 ~ 191) 152

 2597 16:51:50.166530  iDelay=200, Bit 2, Center 111 (40 ~ 183) 144

 2598 16:51:50.169496  iDelay=200, Bit 3, Center 111 (40 ~ 183) 144

 2599 16:51:50.173017  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2600 16:51:50.176033  iDelay=200, Bit 5, Center 111 (40 ~ 183) 144

 2601 16:51:50.183213  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 2602 16:51:50.186183  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2603 16:51:50.189607  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2604 16:51:50.192836  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2605 16:51:50.196489  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 2606 16:51:50.202892  iDelay=200, Bit 11, Center 99 (32 ~ 167) 136

 2607 16:51:50.206188  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2608 16:51:50.209800  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2609 16:51:50.213292  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2610 16:51:50.216105  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 2611 16:51:50.219575  ==

 2612 16:51:50.223265  Dram Type= 6, Freq= 0, CH_0, rank 0

 2613 16:51:50.226500  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2614 16:51:50.227003  ==

 2615 16:51:50.227444  DQS Delay:

 2616 16:51:50.229339  DQS0 = 0, DQS1 = 0

 2617 16:51:50.229792  DQM Delay:

 2618 16:51:50.233042  DQM0 = 115, DQM1 = 107

 2619 16:51:50.233469  DQ Delay:

 2620 16:51:50.235949  DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111

 2621 16:51:50.239514  DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123

 2622 16:51:50.242912  DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99

 2623 16:51:50.246480  DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115

 2624 16:51:50.246895  

 2625 16:51:50.247221  

 2626 16:51:50.247524  ==

 2627 16:51:50.249379  Dram Type= 6, Freq= 0, CH_0, rank 0

 2628 16:51:50.255774  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2629 16:51:50.256272  ==

 2630 16:51:50.256617  

 2631 16:51:50.257007  

 2632 16:51:50.257310  	TX Vref Scan disable

 2633 16:51:50.259362   == TX Byte 0 ==

 2634 16:51:50.262864  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2635 16:51:50.269790  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2636 16:51:50.270333   == TX Byte 1 ==

 2637 16:51:50.272687  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2638 16:51:50.276227  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2639 16:51:50.279505  ==

 2640 16:51:50.282621  Dram Type= 6, Freq= 0, CH_0, rank 0

 2641 16:51:50.286142  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2642 16:51:50.286569  ==

 2643 16:51:50.297888  TX Vref=22, minBit 0, minWin=25, winSum=414

 2644 16:51:50.301030  TX Vref=24, minBit 5, minWin=25, winSum=422

 2645 16:51:50.304468  TX Vref=26, minBit 0, minWin=26, winSum=427

 2646 16:51:50.307770  TX Vref=28, minBit 0, minWin=26, winSum=428

 2647 16:51:50.310961  TX Vref=30, minBit 0, minWin=26, winSum=429

 2648 16:51:50.313988  TX Vref=32, minBit 0, minWin=26, winSum=433

 2649 16:51:50.321080  [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 32

 2650 16:51:50.321499  

 2651 16:51:50.324811  Final TX Range 1 Vref 32

 2652 16:51:50.325261  

 2653 16:51:50.325591  ==

 2654 16:51:50.327572  Dram Type= 6, Freq= 0, CH_0, rank 0

 2655 16:51:50.330976  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2656 16:51:50.331448  ==

 2657 16:51:50.331905  

 2658 16:51:50.332356  

 2659 16:51:50.334616  	TX Vref Scan disable

 2660 16:51:50.337554   == TX Byte 0 ==

 2661 16:51:50.341051  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2662 16:51:50.344550  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2663 16:51:50.347749   == TX Byte 1 ==

 2664 16:51:50.351325  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2665 16:51:50.354261  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2666 16:51:50.354737  

 2667 16:51:50.357911  [DATLAT]

 2668 16:51:50.358356  Freq=1200, CH0 RK0

 2669 16:51:50.358687  

 2670 16:51:50.361380  DATLAT Default: 0xd

 2671 16:51:50.361802  0, 0xFFFF, sum = 0

 2672 16:51:50.364295  1, 0xFFFF, sum = 0

 2673 16:51:50.364718  2, 0xFFFF, sum = 0

 2674 16:51:50.367819  3, 0xFFFF, sum = 0

 2675 16:51:50.368266  4, 0xFFFF, sum = 0

 2676 16:51:50.370996  5, 0xFFFF, sum = 0

 2677 16:51:50.371420  6, 0xFFFF, sum = 0

 2678 16:51:50.374455  7, 0xFFFF, sum = 0

 2679 16:51:50.374877  8, 0xFFFF, sum = 0

 2680 16:51:50.378220  9, 0xFFFF, sum = 0

 2681 16:51:50.378643  10, 0xFFFF, sum = 0

 2682 16:51:50.381599  11, 0xFFFF, sum = 0

 2683 16:51:50.382025  12, 0x0, sum = 1

 2684 16:51:50.384472  13, 0x0, sum = 2

 2685 16:51:50.384899  14, 0x0, sum = 3

 2686 16:51:50.388040  15, 0x0, sum = 4

 2687 16:51:50.388462  best_step = 13

 2688 16:51:50.388789  

 2689 16:51:50.389098  ==

 2690 16:51:50.390947  Dram Type= 6, Freq= 0, CH_0, rank 0

 2691 16:51:50.397833  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2692 16:51:50.398252  ==

 2693 16:51:50.398586  RX Vref Scan: 1

 2694 16:51:50.398898  

 2695 16:51:50.401270  Set Vref Range= 32 -> 127

 2696 16:51:50.401684  

 2697 16:51:50.404746  RX Vref 32 -> 127, step: 1

 2698 16:51:50.405163  

 2699 16:51:50.407528  RX Delay -21 -> 252, step: 4

 2700 16:51:50.407943  

 2701 16:51:50.411408  Set Vref, RX VrefLevel [Byte0]: 32

 2702 16:51:50.414341                           [Byte1]: 32

 2703 16:51:50.414767  

 2704 16:51:50.417407  Set Vref, RX VrefLevel [Byte0]: 33

 2705 16:51:50.420734                           [Byte1]: 33

 2706 16:51:50.421159  

 2707 16:51:50.424217  Set Vref, RX VrefLevel [Byte0]: 34

 2708 16:51:50.427811                           [Byte1]: 34

 2709 16:51:50.431383  

 2710 16:51:50.431803  Set Vref, RX VrefLevel [Byte0]: 35

 2711 16:51:50.434964                           [Byte1]: 35

 2712 16:51:50.439617  

 2713 16:51:50.440064  Set Vref, RX VrefLevel [Byte0]: 36

 2714 16:51:50.442729                           [Byte1]: 36

 2715 16:51:50.447282  

 2716 16:51:50.447700  Set Vref, RX VrefLevel [Byte0]: 37

 2717 16:51:50.450722                           [Byte1]: 37

 2718 16:51:50.455220  

 2719 16:51:50.458801  Set Vref, RX VrefLevel [Byte0]: 38

 2720 16:51:50.459408                           [Byte1]: 38

 2721 16:51:50.463364  

 2722 16:51:50.463879  Set Vref, RX VrefLevel [Byte0]: 39

 2723 16:51:50.466465                           [Byte1]: 39

 2724 16:51:50.471768  

 2725 16:51:50.472334  Set Vref, RX VrefLevel [Byte0]: 40

 2726 16:51:50.474556                           [Byte1]: 40

 2727 16:51:50.479202  

 2728 16:51:50.479662  Set Vref, RX VrefLevel [Byte0]: 41

 2729 16:51:50.482666                           [Byte1]: 41

 2730 16:51:50.487324  

 2731 16:51:50.487808  Set Vref, RX VrefLevel [Byte0]: 42

 2732 16:51:50.490295                           [Byte1]: 42

 2733 16:51:50.495141  

 2734 16:51:50.495560  Set Vref, RX VrefLevel [Byte0]: 43

 2735 16:51:50.498562                           [Byte1]: 43

 2736 16:51:50.502914  

 2737 16:51:50.503359  Set Vref, RX VrefLevel [Byte0]: 44

 2738 16:51:50.506611                           [Byte1]: 44

 2739 16:51:50.511274  

 2740 16:51:50.511908  Set Vref, RX VrefLevel [Byte0]: 45

 2741 16:51:50.514464                           [Byte1]: 45

 2742 16:51:50.518923  

 2743 16:51:50.519339  Set Vref, RX VrefLevel [Byte0]: 46

 2744 16:51:50.525405                           [Byte1]: 46

 2745 16:51:50.525830  

 2746 16:51:50.528798  Set Vref, RX VrefLevel [Byte0]: 47

 2747 16:51:50.532070                           [Byte1]: 47

 2748 16:51:50.532491  

 2749 16:51:50.535279  Set Vref, RX VrefLevel [Byte0]: 48

 2750 16:51:50.538800                           [Byte1]: 48

 2751 16:51:50.542572  

 2752 16:51:50.543020  Set Vref, RX VrefLevel [Byte0]: 49

 2753 16:51:50.545966                           [Byte1]: 49

 2754 16:51:50.550742  

 2755 16:51:50.551324  Set Vref, RX VrefLevel [Byte0]: 50

 2756 16:51:50.553700                           [Byte1]: 50

 2757 16:51:50.558223  

 2758 16:51:50.558891  Set Vref, RX VrefLevel [Byte0]: 51

 2759 16:51:50.561474                           [Byte1]: 51

 2760 16:51:50.566339  

 2761 16:51:50.566783  Set Vref, RX VrefLevel [Byte0]: 52

 2762 16:51:50.569828                           [Byte1]: 52

 2763 16:51:50.574364  

 2764 16:51:50.574935  Set Vref, RX VrefLevel [Byte0]: 53

 2765 16:51:50.577431                           [Byte1]: 53

 2766 16:51:50.582500  

 2767 16:51:50.582917  Set Vref, RX VrefLevel [Byte0]: 54

 2768 16:51:50.585879                           [Byte1]: 54

 2769 16:51:50.590016  

 2770 16:51:50.590568  Set Vref, RX VrefLevel [Byte0]: 55

 2771 16:51:50.593730                           [Byte1]: 55

 2772 16:51:50.597978  

 2773 16:51:50.598427  Set Vref, RX VrefLevel [Byte0]: 56

 2774 16:51:50.601422                           [Byte1]: 56

 2775 16:51:50.606075  

 2776 16:51:50.606517  Set Vref, RX VrefLevel [Byte0]: 57

 2777 16:51:50.609676                           [Byte1]: 57

 2778 16:51:50.613776  

 2779 16:51:50.614335  Set Vref, RX VrefLevel [Byte0]: 58

 2780 16:51:50.617178                           [Byte1]: 58

 2781 16:51:50.622041  

 2782 16:51:50.622453  Set Vref, RX VrefLevel [Byte0]: 59

 2783 16:51:50.624998                           [Byte1]: 59

 2784 16:51:50.629579  

 2785 16:51:50.630139  Set Vref, RX VrefLevel [Byte0]: 60

 2786 16:51:50.633170                           [Byte1]: 60

 2787 16:51:50.637772  

 2788 16:51:50.638200  Set Vref, RX VrefLevel [Byte0]: 61

 2789 16:51:50.641185                           [Byte1]: 61

 2790 16:51:50.645643  

 2791 16:51:50.646055  Set Vref, RX VrefLevel [Byte0]: 62

 2792 16:51:50.648764                           [Byte1]: 62

 2793 16:51:50.653729  

 2794 16:51:50.654145  Set Vref, RX VrefLevel [Byte0]: 63

 2795 16:51:50.656729                           [Byte1]: 63

 2796 16:51:50.661646  

 2797 16:51:50.662064  Set Vref, RX VrefLevel [Byte0]: 64

 2798 16:51:50.665245                           [Byte1]: 64

 2799 16:51:50.669753  

 2800 16:51:50.670167  Set Vref, RX VrefLevel [Byte0]: 65

 2801 16:51:50.672656                           [Byte1]: 65

 2802 16:51:50.677652  

 2803 16:51:50.678067  Set Vref, RX VrefLevel [Byte0]: 66

 2804 16:51:50.680530                           [Byte1]: 66

 2805 16:51:50.685573  

 2806 16:51:50.685986  Set Vref, RX VrefLevel [Byte0]: 67

 2807 16:51:50.688226                           [Byte1]: 67

 2808 16:51:50.693438  

 2809 16:51:50.693851  Set Vref, RX VrefLevel [Byte0]: 68

 2810 16:51:50.696636                           [Byte1]: 68

 2811 16:51:50.701481  

 2812 16:51:50.701897  Final RX Vref Byte 0 = 56 to rank0

 2813 16:51:50.704402  Final RX Vref Byte 1 = 52 to rank0

 2814 16:51:50.707930  Final RX Vref Byte 0 = 56 to rank1

 2815 16:51:50.711487  Final RX Vref Byte 1 = 52 to rank1==

 2816 16:51:50.714395  Dram Type= 6, Freq= 0, CH_0, rank 0

 2817 16:51:50.720822  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2818 16:51:50.721241  ==

 2819 16:51:50.721574  DQS Delay:

 2820 16:51:50.721884  DQS0 = 0, DQS1 = 0

 2821 16:51:50.724554  DQM Delay:

 2822 16:51:50.724970  DQM0 = 114, DQM1 = 105

 2823 16:51:50.728151  DQ Delay:

 2824 16:51:50.730901  DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =112

 2825 16:51:50.734594  DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122

 2826 16:51:50.738045  DQ8 =92, DQ9 =90, DQ10 =108, DQ11 =96

 2827 16:51:50.741291  DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114

 2828 16:51:50.741708  

 2829 16:51:50.742041  

 2830 16:51:50.747876  [DQSOSCAuto] RK0, (LSB)MR18= 0xfbeb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps

 2831 16:51:50.751447  CH0 RK0: MR19=303, MR18=FBEB

 2832 16:51:50.757459  CH0_RK0: MR19=0x303, MR18=0xFBEB, DQSOSC=412, MR23=63, INC=38, DEC=25

 2833 16:51:50.757542  

 2834 16:51:50.760518  ----->DramcWriteLeveling(PI) begin...

 2835 16:51:50.760601  ==

 2836 16:51:50.763932  Dram Type= 6, Freq= 0, CH_0, rank 1

 2837 16:51:50.767736  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2838 16:51:50.767824  ==

 2839 16:51:50.771017  Write leveling (Byte 0): 32 => 32

 2840 16:51:50.774370  Write leveling (Byte 1): 28 => 28

 2841 16:51:50.777343  DramcWriteLeveling(PI) end<-----

 2842 16:51:50.777444  

 2843 16:51:50.777524  ==

 2844 16:51:50.781133  Dram Type= 6, Freq= 0, CH_0, rank 1

 2845 16:51:50.787827  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2846 16:51:50.787997  ==

 2847 16:51:50.788097  [Gating] SW mode calibration

 2848 16:51:50.798059  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2849 16:51:50.800969  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2850 16:51:50.804409   0 15  0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 2851 16:51:50.811026   0 15  4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)

 2852 16:51:50.814745   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2853 16:51:50.817673   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2854 16:51:50.824650   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2855 16:51:50.827358   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2856 16:51:50.831031   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 2857 16:51:50.837649   0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)

 2858 16:51:50.841063   1  0  0 | B1->B0 | 2e2e 2727 | 1 0 | (1 0) (0 0)

 2859 16:51:50.844478   1  0  4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)

 2860 16:51:50.850795   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2861 16:51:50.854478   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2862 16:51:50.857912   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2863 16:51:50.864627   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2864 16:51:50.867373   1  0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)

 2865 16:51:50.871441   1  0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)

 2866 16:51:50.878071   1  1  0 | B1->B0 | 3231 4343 | 1 0 | (0 0) (0 0)

 2867 16:51:50.881302   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2868 16:51:50.884597   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2869 16:51:50.888005   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2870 16:51:50.894553   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2871 16:51:50.897956   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2872 16:51:50.900797   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2873 16:51:50.907875   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2874 16:51:50.910777   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 2875 16:51:50.914347   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2876 16:51:50.920814   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2877 16:51:50.924403   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2878 16:51:50.927779   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2879 16:51:50.934343   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2880 16:51:50.937446   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2881 16:51:50.941067   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2882 16:51:50.947843   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2883 16:51:50.950905   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2884 16:51:50.954332   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2885 16:51:50.960727   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2886 16:51:50.964589   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2887 16:51:50.967575   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2888 16:51:50.974028   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2889 16:51:50.977472   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2890 16:51:50.980850   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2891 16:51:50.983922  Total UI for P1: 0, mck2ui 16

 2892 16:51:50.987354  best dqsien dly found for B0: ( 1,  3, 26)

 2893 16:51:50.990708   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2894 16:51:50.997632   1  4  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2895 16:51:51.000568  Total UI for P1: 0, mck2ui 16

 2896 16:51:51.003903  best dqsien dly found for B1: ( 1,  4,  2)

 2897 16:51:51.007450  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2898 16:51:51.010901  best DQS1 dly(MCK, UI, PI) = (1, 4, 2)

 2899 16:51:51.011321  

 2900 16:51:51.014648  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2901 16:51:51.017876  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)

 2902 16:51:51.020842  [Gating] SW calibration Done

 2903 16:51:51.021258  ==

 2904 16:51:51.024387  Dram Type= 6, Freq= 0, CH_0, rank 1

 2905 16:51:51.027827  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2906 16:51:51.028274  ==

 2907 16:51:51.030700  RX Vref Scan: 0

 2908 16:51:51.031115  

 2909 16:51:51.031448  RX Vref 0 -> 0, step: 1

 2910 16:51:51.034213  

 2911 16:51:51.034628  RX Delay -40 -> 252, step: 8

 2912 16:51:51.041062  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 2913 16:51:51.044437  iDelay=200, Bit 1, Center 115 (40 ~ 191) 152

 2914 16:51:51.048027  iDelay=200, Bit 2, Center 111 (40 ~ 183) 144

 2915 16:51:51.050767  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 2916 16:51:51.054473  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2917 16:51:51.057403  iDelay=200, Bit 5, Center 107 (32 ~ 183) 152

 2918 16:51:51.064519  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 2919 16:51:51.067266  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2920 16:51:51.070996  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2921 16:51:51.074214  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2922 16:51:51.077707  iDelay=200, Bit 10, Center 103 (32 ~ 175) 144

 2923 16:51:51.084739  iDelay=200, Bit 11, Center 99 (32 ~ 167) 136

 2924 16:51:51.087457  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2925 16:51:51.090685  iDelay=200, Bit 13, Center 111 (40 ~ 183) 144

 2926 16:51:51.094523  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2927 16:51:51.097818  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 2928 16:51:51.098246  ==

 2929 16:51:51.100982  Dram Type= 6, Freq= 0, CH_0, rank 1

 2930 16:51:51.107608  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2931 16:51:51.108053  ==

 2932 16:51:51.108477  DQS Delay:

 2933 16:51:51.110817  DQS0 = 0, DQS1 = 0

 2934 16:51:51.111271  DQM Delay:

 2935 16:51:51.114490  DQM0 = 115, DQM1 = 106

 2936 16:51:51.114925  DQ Delay:

 2937 16:51:51.117950  DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115

 2938 16:51:51.120818  DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123

 2939 16:51:51.124364  DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99

 2940 16:51:51.127857  DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111

 2941 16:51:51.128315  

 2942 16:51:51.128690  

 2943 16:51:51.129015  ==

 2944 16:51:51.131377  Dram Type= 6, Freq= 0, CH_0, rank 1

 2945 16:51:51.134200  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2946 16:51:51.137694  ==

 2947 16:51:51.138110  

 2948 16:51:51.138618  

 2949 16:51:51.138943  	TX Vref Scan disable

 2950 16:51:51.141344   == TX Byte 0 ==

 2951 16:51:51.144253  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2952 16:51:51.147559  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2953 16:51:51.151197   == TX Byte 1 ==

 2954 16:51:51.154506  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2955 16:51:51.158099  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2956 16:51:51.158514  ==

 2957 16:51:51.161130  Dram Type= 6, Freq= 0, CH_0, rank 1

 2958 16:51:51.167941  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2959 16:51:51.168428  ==

 2960 16:51:51.179037  TX Vref=22, minBit 4, minWin=25, winSum=422

 2961 16:51:51.182379  TX Vref=24, minBit 3, minWin=25, winSum=427

 2962 16:51:51.185344  TX Vref=26, minBit 0, minWin=26, winSum=436

 2963 16:51:51.188798  TX Vref=28, minBit 4, minWin=26, winSum=438

 2964 16:51:51.191710  TX Vref=30, minBit 0, minWin=27, winSum=440

 2965 16:51:51.198690  TX Vref=32, minBit 0, minWin=26, winSum=436

 2966 16:51:51.201827  [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 30

 2967 16:51:51.202263  

 2968 16:51:51.205789  Final TX Range 1 Vref 30

 2969 16:51:51.206353  

 2970 16:51:51.206731  ==

 2971 16:51:51.208445  Dram Type= 6, Freq= 0, CH_0, rank 1

 2972 16:51:51.211719  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2973 16:51:51.212196  ==

 2974 16:51:51.215280  

 2975 16:51:51.215694  

 2976 16:51:51.216175  	TX Vref Scan disable

 2977 16:51:51.218803   == TX Byte 0 ==

 2978 16:51:51.221804  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2979 16:51:51.228456  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2980 16:51:51.228969   == TX Byte 1 ==

 2981 16:51:51.231627  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2982 16:51:51.238292  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2983 16:51:51.238801  

 2984 16:51:51.239137  [DATLAT]

 2985 16:51:51.239448  Freq=1200, CH0 RK1

 2986 16:51:51.239744  

 2987 16:51:51.241801  DATLAT Default: 0xd

 2988 16:51:51.242230  0, 0xFFFF, sum = 0

 2989 16:51:51.245262  1, 0xFFFF, sum = 0

 2990 16:51:51.248304  2, 0xFFFF, sum = 0

 2991 16:51:51.248723  3, 0xFFFF, sum = 0

 2992 16:51:51.251511  4, 0xFFFF, sum = 0

 2993 16:51:51.252001  5, 0xFFFF, sum = 0

 2994 16:51:51.255042  6, 0xFFFF, sum = 0

 2995 16:51:51.255462  7, 0xFFFF, sum = 0

 2996 16:51:51.258525  8, 0xFFFF, sum = 0

 2997 16:51:51.258942  9, 0xFFFF, sum = 0

 2998 16:51:51.261571  10, 0xFFFF, sum = 0

 2999 16:51:51.261990  11, 0xFFFF, sum = 0

 3000 16:51:51.264892  12, 0x0, sum = 1

 3001 16:51:51.265315  13, 0x0, sum = 2

 3002 16:51:51.268551  14, 0x0, sum = 3

 3003 16:51:51.269136  15, 0x0, sum = 4

 3004 16:51:51.271339  best_step = 13

 3005 16:51:51.271751  

 3006 16:51:51.272166  ==

 3007 16:51:51.274809  Dram Type= 6, Freq= 0, CH_0, rank 1

 3008 16:51:51.278356  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3009 16:51:51.278771  ==

 3010 16:51:51.279102  RX Vref Scan: 0

 3011 16:51:51.281409  

 3012 16:51:51.281820  RX Vref 0 -> 0, step: 1

 3013 16:51:51.282151  

 3014 16:51:51.284935  RX Delay -21 -> 252, step: 4

 3015 16:51:51.291252  iDelay=195, Bit 0, Center 114 (43 ~ 186) 144

 3016 16:51:51.294659  iDelay=195, Bit 1, Center 114 (43 ~ 186) 144

 3017 16:51:51.298248  iDelay=195, Bit 2, Center 110 (39 ~ 182) 144

 3018 16:51:51.301788  iDelay=195, Bit 3, Center 114 (43 ~ 186) 144

 3019 16:51:51.304568  iDelay=195, Bit 4, Center 112 (43 ~ 182) 140

 3020 16:51:51.308237  iDelay=195, Bit 5, Center 104 (35 ~ 174) 140

 3021 16:51:51.314657  iDelay=195, Bit 6, Center 120 (47 ~ 194) 148

 3022 16:51:51.317961  iDelay=195, Bit 7, Center 122 (51 ~ 194) 144

 3023 16:51:51.321320  iDelay=195, Bit 8, Center 94 (27 ~ 162) 136

 3024 16:51:51.324265  iDelay=195, Bit 9, Center 92 (23 ~ 162) 140

 3025 16:51:51.328000  iDelay=195, Bit 10, Center 106 (39 ~ 174) 136

 3026 16:51:51.334875  iDelay=195, Bit 11, Center 94 (27 ~ 162) 136

 3027 16:51:51.337665  iDelay=195, Bit 12, Center 110 (43 ~ 178) 136

 3028 16:51:51.341410  iDelay=195, Bit 13, Center 110 (43 ~ 178) 136

 3029 16:51:51.344200  iDelay=195, Bit 14, Center 118 (55 ~ 182) 128

 3030 16:51:51.350761  iDelay=195, Bit 15, Center 114 (47 ~ 182) 136

 3031 16:51:51.351195  ==

 3032 16:51:51.354307  Dram Type= 6, Freq= 0, CH_0, rank 1

 3033 16:51:51.357623  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3034 16:51:51.358060  ==

 3035 16:51:51.358398  DQS Delay:

 3036 16:51:51.360997  DQS0 = 0, DQS1 = 0

 3037 16:51:51.361418  DQM Delay:

 3038 16:51:51.364632  DQM0 = 113, DQM1 = 104

 3039 16:51:51.365086  DQ Delay:

 3040 16:51:51.367594  DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114

 3041 16:51:51.370882  DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =122

 3042 16:51:51.374111  DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94

 3043 16:51:51.378082  DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114

 3044 16:51:51.378504  

 3045 16:51:51.378841  

 3046 16:51:51.387392  [DQSOSCAuto] RK1, (LSB)MR18= 0x3f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps

 3047 16:51:51.390782  CH0 RK1: MR19=403, MR18=3F5

 3048 16:51:51.393983  CH0_RK1: MR19=0x403, MR18=0x3F5, DQSOSC=408, MR23=63, INC=39, DEC=26

 3049 16:51:51.397742  [RxdqsGatingPostProcess] freq 1200

 3050 16:51:51.403915  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3051 16:51:51.407611  best DQS0 dly(2T, 0.5T) = (0, 12)

 3052 16:51:51.411024  best DQS1 dly(2T, 0.5T) = (0, 12)

 3053 16:51:51.414406  best DQS0 P1 dly(2T, 0.5T) = (1, 0)

 3054 16:51:51.417195  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3055 16:51:51.420819  best DQS0 dly(2T, 0.5T) = (0, 11)

 3056 16:51:51.421343  best DQS1 dly(2T, 0.5T) = (0, 12)

 3057 16:51:51.424281  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3058 16:51:51.427444  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3059 16:51:51.430943  Pre-setting of DQS Precalculation

 3060 16:51:51.437472  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3061 16:51:51.437942  ==

 3062 16:51:51.440913  Dram Type= 6, Freq= 0, CH_1, rank 0

 3063 16:51:51.444631  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3064 16:51:51.445221  ==

 3065 16:51:51.450820  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3066 16:51:51.457371  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3067 16:51:51.464190  [CA 0] Center 38 (8~68) winsize 61

 3068 16:51:51.467793  [CA 1] Center 38 (8~68) winsize 61

 3069 16:51:51.470814  [CA 2] Center 35 (5~65) winsize 61

 3070 16:51:51.474516  [CA 3] Center 34 (4~65) winsize 62

 3071 16:51:51.477762  [CA 4] Center 34 (4~65) winsize 62

 3072 16:51:51.481074  [CA 5] Center 34 (4~64) winsize 61

 3073 16:51:51.481492  

 3074 16:51:51.483829  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3075 16:51:51.484254  

 3076 16:51:51.487350  [CATrainingPosCal] consider 1 rank data

 3077 16:51:51.490915  u2DelayCellTimex100 = 270/100 ps

 3078 16:51:51.493894  CA0 delay=38 (8~68),Diff = 4 PI (19 cell)

 3079 16:51:51.500841  CA1 delay=38 (8~68),Diff = 4 PI (19 cell)

 3080 16:51:51.504380  CA2 delay=35 (5~65),Diff = 1 PI (4 cell)

 3081 16:51:51.507257  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 3082 16:51:51.510764  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 3083 16:51:51.514406  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3084 16:51:51.514834  

 3085 16:51:51.517277  CA PerBit enable=1, Macro0, CA PI delay=34

 3086 16:51:51.517723  

 3087 16:51:51.520810  [CBTSetCACLKResult] CA Dly = 34

 3088 16:51:51.521228  CS Dly: 6 (0~37)

 3089 16:51:51.524373  ==

 3090 16:51:51.524902  Dram Type= 6, Freq= 0, CH_1, rank 1

 3091 16:51:51.530771  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3092 16:51:51.531255  ==

 3093 16:51:51.534501  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3094 16:51:51.540748  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3095 16:51:51.549726  [CA 0] Center 38 (8~68) winsize 61

 3096 16:51:51.553025  [CA 1] Center 38 (9~68) winsize 60

 3097 16:51:51.556723  [CA 2] Center 34 (4~65) winsize 62

 3098 16:51:51.560203  [CA 3] Center 34 (4~65) winsize 62

 3099 16:51:51.563251  [CA 4] Center 34 (4~65) winsize 62

 3100 16:51:51.566743  [CA 5] Center 33 (3~63) winsize 61

 3101 16:51:51.567158  

 3102 16:51:51.570069  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3103 16:51:51.570534  

 3104 16:51:51.573138  [CATrainingPosCal] consider 2 rank data

 3105 16:51:51.577050  u2DelayCellTimex100 = 270/100 ps

 3106 16:51:51.580196  CA0 delay=38 (8~68),Diff = 5 PI (24 cell)

 3107 16:51:51.586448  CA1 delay=38 (9~68),Diff = 5 PI (24 cell)

 3108 16:51:51.589696  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3109 16:51:51.593359  CA3 delay=34 (4~65),Diff = 1 PI (4 cell)

 3110 16:51:51.596270  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 3111 16:51:51.599622  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3112 16:51:51.600085  

 3113 16:51:51.603163  CA PerBit enable=1, Macro0, CA PI delay=33

 3114 16:51:51.603632  

 3115 16:51:51.606462  [CBTSetCACLKResult] CA Dly = 33

 3116 16:51:51.607000  CS Dly: 7 (0~40)

 3117 16:51:51.607339  

 3118 16:51:51.609930  ----->DramcWriteLeveling(PI) begin...

 3119 16:51:51.612936  ==

 3120 16:51:51.616224  Dram Type= 6, Freq= 0, CH_1, rank 0

 3121 16:51:51.619825  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3122 16:51:51.620406  ==

 3123 16:51:51.622838  Write leveling (Byte 0): 25 => 25

 3124 16:51:51.626285  Write leveling (Byte 1): 30 => 30

 3125 16:51:51.629973  DramcWriteLeveling(PI) end<-----

 3126 16:51:51.630546  

 3127 16:51:51.631028  ==

 3128 16:51:51.632821  Dram Type= 6, Freq= 0, CH_1, rank 0

 3129 16:51:51.636171  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3130 16:51:51.636617  ==

 3131 16:51:51.639771  [Gating] SW mode calibration

 3132 16:51:51.646107  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3133 16:51:51.653182  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3134 16:51:51.656169   0 15  0 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)

 3135 16:51:51.659711   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3136 16:51:51.663170   0 15  8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 3137 16:51:51.669680   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3138 16:51:51.673010   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3139 16:51:51.676426   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3140 16:51:51.682782   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 3141 16:51:51.686509   0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 3142 16:51:51.689878   1  0  0 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (1 1)

 3143 16:51:51.696026   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3144 16:51:51.699457   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3145 16:51:51.702618   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3146 16:51:51.709655   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3147 16:51:51.712742   1  0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 3148 16:51:51.716430   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3149 16:51:51.722921   1  0 28 | B1->B0 | 2c2c 2727 | 0 1 | (0 0) (0 0)

 3150 16:51:51.726365   1  1  0 | B1->B0 | 4343 3939 | 0 0 | (0 0) (0 0)

 3151 16:51:51.729393   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3152 16:51:51.735763   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3153 16:51:51.739328   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3154 16:51:51.742737   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3155 16:51:51.749340   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3156 16:51:51.752557   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3157 16:51:51.756208   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3158 16:51:51.762526   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3159 16:51:51.765922   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3160 16:51:51.769493   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3161 16:51:51.775827   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3162 16:51:51.779210   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3163 16:51:51.782766   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3164 16:51:51.785793   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3165 16:51:51.792732   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3166 16:51:51.796365   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3167 16:51:51.799542   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3168 16:51:51.806645   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3169 16:51:51.809642   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3170 16:51:51.812975   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3171 16:51:51.819649   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3172 16:51:51.823069   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3173 16:51:51.826223   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3174 16:51:51.833391   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3175 16:51:51.833821  Total UI for P1: 0, mck2ui 16

 3176 16:51:51.836290  best dqsien dly found for B0: ( 1,  3, 28)

 3177 16:51:51.839649  Total UI for P1: 0, mck2ui 16

 3178 16:51:51.843258  best dqsien dly found for B1: ( 1,  3, 30)

 3179 16:51:51.846348  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 3180 16:51:51.852867  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 3181 16:51:51.853284  

 3182 16:51:51.856150  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 3183 16:51:51.859751  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 3184 16:51:51.862868  [Gating] SW calibration Done

 3185 16:51:51.863290  ==

 3186 16:51:51.866043  Dram Type= 6, Freq= 0, CH_1, rank 0

 3187 16:51:51.869750  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3188 16:51:51.870192  ==

 3189 16:51:51.872853  RX Vref Scan: 0

 3190 16:51:51.873272  

 3191 16:51:51.873603  RX Vref 0 -> 0, step: 1

 3192 16:51:51.873913  

 3193 16:51:51.876228  RX Delay -40 -> 252, step: 8

 3194 16:51:51.879730  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3195 16:51:51.886059  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 3196 16:51:51.889476  iDelay=200, Bit 2, Center 103 (32 ~ 175) 144

 3197 16:51:51.892538  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3198 16:51:51.896339  iDelay=200, Bit 4, Center 111 (40 ~ 183) 144

 3199 16:51:51.899706  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3200 16:51:51.902761  iDelay=200, Bit 6, Center 127 (64 ~ 191) 128

 3201 16:51:51.909408  iDelay=200, Bit 7, Center 115 (48 ~ 183) 136

 3202 16:51:51.912971  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3203 16:51:51.915836  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 3204 16:51:51.919546  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 3205 16:51:51.922737  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3206 16:51:51.929298  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3207 16:51:51.932853  iDelay=200, Bit 13, Center 119 (56 ~ 183) 128

 3208 16:51:51.935999  iDelay=200, Bit 14, Center 111 (40 ~ 183) 144

 3209 16:51:51.939515  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 3210 16:51:51.940156  ==

 3211 16:51:51.943006  Dram Type= 6, Freq= 0, CH_1, rank 0

 3212 16:51:51.949731  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3213 16:51:51.950158  ==

 3214 16:51:51.950533  DQS Delay:

 3215 16:51:51.952343  DQS0 = 0, DQS1 = 0

 3216 16:51:51.952762  DQM Delay:

 3217 16:51:51.953118  DQM0 = 117, DQM1 = 109

 3218 16:51:51.956203  DQ Delay:

 3219 16:51:51.959112  DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =119

 3220 16:51:51.962683  DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115

 3221 16:51:51.965892  DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107

 3222 16:51:51.969535  DQ12 =123, DQ13 =119, DQ14 =111, DQ15 =115

 3223 16:51:51.969967  

 3224 16:51:51.970372  

 3225 16:51:51.970698  ==

 3226 16:51:51.972718  Dram Type= 6, Freq= 0, CH_1, rank 0

 3227 16:51:51.975881  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3228 16:51:51.979361  ==

 3229 16:51:51.979933  

 3230 16:51:51.980461  

 3231 16:51:51.980790  	TX Vref Scan disable

 3232 16:51:51.982525   == TX Byte 0 ==

 3233 16:51:51.985996  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3234 16:51:51.989315  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3235 16:51:51.992901   == TX Byte 1 ==

 3236 16:51:51.995859  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 3237 16:51:51.999346  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 3238 16:51:51.999819  ==

 3239 16:51:52.002936  Dram Type= 6, Freq= 0, CH_1, rank 0

 3240 16:51:52.009068  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3241 16:51:52.009504  ==

 3242 16:51:52.020691  TX Vref=22, minBit 1, minWin=25, winSum=411

 3243 16:51:52.023624  TX Vref=24, minBit 5, minWin=25, winSum=416

 3244 16:51:52.027124  TX Vref=26, minBit 0, minWin=26, winSum=423

 3245 16:51:52.030548  TX Vref=28, minBit 0, minWin=26, winSum=425

 3246 16:51:52.033495  TX Vref=30, minBit 0, minWin=26, winSum=429

 3247 16:51:52.040055  TX Vref=32, minBit 12, minWin=25, winSum=429

 3248 16:51:52.043647  [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30

 3249 16:51:52.044244  

 3250 16:51:52.046683  Final TX Range 1 Vref 30

 3251 16:51:52.047260  

 3252 16:51:52.047608  ==

 3253 16:51:52.050215  Dram Type= 6, Freq= 0, CH_1, rank 0

 3254 16:51:52.053752  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3255 16:51:52.054348  ==

 3256 16:51:52.056836  

 3257 16:51:52.057250  

 3258 16:51:52.057578  	TX Vref Scan disable

 3259 16:51:52.060291   == TX Byte 0 ==

 3260 16:51:52.063852  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3261 16:51:52.066775  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3262 16:51:52.070194   == TX Byte 1 ==

 3263 16:51:52.073846  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 3264 16:51:52.076685  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 3265 16:51:52.080374  

 3266 16:51:52.080848  [DATLAT]

 3267 16:51:52.081194  Freq=1200, CH1 RK0

 3268 16:51:52.081508  

 3269 16:51:52.083314  DATLAT Default: 0xd

 3270 16:51:52.083858  0, 0xFFFF, sum = 0

 3271 16:51:52.086607  1, 0xFFFF, sum = 0

 3272 16:51:52.087166  2, 0xFFFF, sum = 0

 3273 16:51:52.090479  3, 0xFFFF, sum = 0

 3274 16:51:52.090900  4, 0xFFFF, sum = 0

 3275 16:51:52.093663  5, 0xFFFF, sum = 0

 3276 16:51:52.094087  6, 0xFFFF, sum = 0

 3277 16:51:52.096833  7, 0xFFFF, sum = 0

 3278 16:51:52.100743  8, 0xFFFF, sum = 0

 3279 16:51:52.101181  9, 0xFFFF, sum = 0

 3280 16:51:52.103699  10, 0xFFFF, sum = 0

 3281 16:51:52.104169  11, 0xFFFF, sum = 0

 3282 16:51:52.107258  12, 0x0, sum = 1

 3283 16:51:52.107701  13, 0x0, sum = 2

 3284 16:51:52.108091  14, 0x0, sum = 3

 3285 16:51:52.110728  15, 0x0, sum = 4

 3286 16:51:52.111150  best_step = 13

 3287 16:51:52.111482  

 3288 16:51:52.113484  ==

 3289 16:51:52.114048  Dram Type= 6, Freq= 0, CH_1, rank 0

 3290 16:51:52.120286  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3291 16:51:52.120712  ==

 3292 16:51:52.121045  RX Vref Scan: 1

 3293 16:51:52.121351  

 3294 16:51:52.123945  Set Vref Range= 32 -> 127

 3295 16:51:52.124389  

 3296 16:51:52.127389  RX Vref 32 -> 127, step: 1

 3297 16:51:52.127797  

 3298 16:51:52.130447  RX Delay -21 -> 252, step: 4

 3299 16:51:52.130854  

 3300 16:51:52.133679  Set Vref, RX VrefLevel [Byte0]: 32

 3301 16:51:52.136810                           [Byte1]: 32

 3302 16:51:52.137278  

 3303 16:51:52.140244  Set Vref, RX VrefLevel [Byte0]: 33

 3304 16:51:52.143244                           [Byte1]: 33

 3305 16:51:52.143548  

 3306 16:51:52.146670  Set Vref, RX VrefLevel [Byte0]: 34

 3307 16:51:52.149720                           [Byte1]: 34

 3308 16:51:52.154486  

 3309 16:51:52.154660  Set Vref, RX VrefLevel [Byte0]: 35

 3310 16:51:52.157336                           [Byte1]: 35

 3311 16:51:52.161974  

 3312 16:51:52.162120  Set Vref, RX VrefLevel [Byte0]: 36

 3313 16:51:52.165626                           [Byte1]: 36

 3314 16:51:52.170291  

 3315 16:51:52.170447  Set Vref, RX VrefLevel [Byte0]: 37

 3316 16:51:52.173215                           [Byte1]: 37

 3317 16:51:52.177816  

 3318 16:51:52.177961  Set Vref, RX VrefLevel [Byte0]: 38

 3319 16:51:52.184557                           [Byte1]: 38

 3320 16:51:52.184716  

 3321 16:51:52.187827  Set Vref, RX VrefLevel [Byte0]: 39

 3322 16:51:52.191157                           [Byte1]: 39

 3323 16:51:52.191325  

 3324 16:51:52.194709  Set Vref, RX VrefLevel [Byte0]: 40

 3325 16:51:52.197744                           [Byte1]: 40

 3326 16:51:52.201788  

 3327 16:51:52.202020  Set Vref, RX VrefLevel [Byte0]: 41

 3328 16:51:52.204874                           [Byte1]: 41

 3329 16:51:52.209485  

 3330 16:51:52.209771  Set Vref, RX VrefLevel [Byte0]: 42

 3331 16:51:52.213057                           [Byte1]: 42

 3332 16:51:52.217887  

 3333 16:51:52.218449  Set Vref, RX VrefLevel [Byte0]: 43

 3334 16:51:52.221121                           [Byte1]: 43

 3335 16:51:52.225544  

 3336 16:51:52.225954  Set Vref, RX VrefLevel [Byte0]: 44

 3337 16:51:52.228981                           [Byte1]: 44

 3338 16:51:52.233350  

 3339 16:51:52.233755  Set Vref, RX VrefLevel [Byte0]: 45

 3340 16:51:52.236793                           [Byte1]: 45

 3341 16:51:52.241781  

 3342 16:51:52.242318  Set Vref, RX VrefLevel [Byte0]: 46

 3343 16:51:52.244635                           [Byte1]: 46

 3344 16:51:52.249413  

 3345 16:51:52.249820  Set Vref, RX VrefLevel [Byte0]: 47

 3346 16:51:52.253012                           [Byte1]: 47

 3347 16:51:52.257815  

 3348 16:51:52.258237  Set Vref, RX VrefLevel [Byte0]: 48

 3349 16:51:52.260776                           [Byte1]: 48

 3350 16:51:52.265379  

 3351 16:51:52.265799  Set Vref, RX VrefLevel [Byte0]: 49

 3352 16:51:52.268424                           [Byte1]: 49

 3353 16:51:52.273188  

 3354 16:51:52.273589  Set Vref, RX VrefLevel [Byte0]: 50

 3355 16:51:52.276818                           [Byte1]: 50

 3356 16:51:52.281522  

 3357 16:51:52.281929  Set Vref, RX VrefLevel [Byte0]: 51

 3358 16:51:52.284401                           [Byte1]: 51

 3359 16:51:52.289259  

 3360 16:51:52.289750  Set Vref, RX VrefLevel [Byte0]: 52

 3361 16:51:52.292369                           [Byte1]: 52

 3362 16:51:52.297299  

 3363 16:51:52.297849  Set Vref, RX VrefLevel [Byte0]: 53

 3364 16:51:52.300541                           [Byte1]: 53

 3365 16:51:52.305052  

 3366 16:51:52.305562  Set Vref, RX VrefLevel [Byte0]: 54

 3367 16:51:52.308202                           [Byte1]: 54

 3368 16:51:52.312704  

 3369 16:51:52.313123  Set Vref, RX VrefLevel [Byte0]: 55

 3370 16:51:52.316311                           [Byte1]: 55

 3371 16:51:52.320974  

 3372 16:51:52.321393  Set Vref, RX VrefLevel [Byte0]: 56

 3373 16:51:52.324309                           [Byte1]: 56

 3374 16:51:52.328447  

 3375 16:51:52.328877  Set Vref, RX VrefLevel [Byte0]: 57

 3376 16:51:52.331865                           [Byte1]: 57

 3377 16:51:52.336843  

 3378 16:51:52.337275  Set Vref, RX VrefLevel [Byte0]: 58

 3379 16:51:52.339643                           [Byte1]: 58

 3380 16:51:52.344452  

 3381 16:51:52.344899  Set Vref, RX VrefLevel [Byte0]: 59

 3382 16:51:52.347929                           [Byte1]: 59

 3383 16:51:52.352514  

 3384 16:51:52.352954  Set Vref, RX VrefLevel [Byte0]: 60

 3385 16:51:52.355566                           [Byte1]: 60

 3386 16:51:52.360310  

 3387 16:51:52.360726  Set Vref, RX VrefLevel [Byte0]: 61

 3388 16:51:52.363731                           [Byte1]: 61

 3389 16:51:52.368478  

 3390 16:51:52.368901  Set Vref, RX VrefLevel [Byte0]: 62

 3391 16:51:52.371379                           [Byte1]: 62

 3392 16:51:52.376059  

 3393 16:51:52.376473  Set Vref, RX VrefLevel [Byte0]: 63

 3394 16:51:52.379690                           [Byte1]: 63

 3395 16:51:52.384373  

 3396 16:51:52.384814  Set Vref, RX VrefLevel [Byte0]: 64

 3397 16:51:52.387251                           [Byte1]: 64

 3398 16:51:52.391927  

 3399 16:51:52.392385  Set Vref, RX VrefLevel [Byte0]: 65

 3400 16:51:52.395540                           [Byte1]: 65

 3401 16:51:52.400168  

 3402 16:51:52.400605  Set Vref, RX VrefLevel [Byte0]: 66

 3403 16:51:52.403565                           [Byte1]: 66

 3404 16:51:52.408134  

 3405 16:51:52.408551  Set Vref, RX VrefLevel [Byte0]: 67

 3406 16:51:52.411596                           [Byte1]: 67

 3407 16:51:52.415938  

 3408 16:51:52.416391  Set Vref, RX VrefLevel [Byte0]: 68

 3409 16:51:52.419078                           [Byte1]: 68

 3410 16:51:52.423884  

 3411 16:51:52.424338  Set Vref, RX VrefLevel [Byte0]: 69

 3412 16:51:52.427302                           [Byte1]: 69

 3413 16:51:52.432038  

 3414 16:51:52.432522  Set Vref, RX VrefLevel [Byte0]: 70

 3415 16:51:52.434828                           [Byte1]: 70

 3416 16:51:52.439494  

 3417 16:51:52.440117  Set Vref, RX VrefLevel [Byte0]: 71

 3418 16:51:52.442993                           [Byte1]: 71

 3419 16:51:52.447711  

 3420 16:51:52.448248  Final RX Vref Byte 0 = 56 to rank0

 3421 16:51:52.450795  Final RX Vref Byte 1 = 50 to rank0

 3422 16:51:52.454220  Final RX Vref Byte 0 = 56 to rank1

 3423 16:51:52.457442  Final RX Vref Byte 1 = 50 to rank1==

 3424 16:51:52.460997  Dram Type= 6, Freq= 0, CH_1, rank 0

 3425 16:51:52.467329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3426 16:51:52.467994  ==

 3427 16:51:52.468359  DQS Delay:

 3428 16:51:52.468677  DQS0 = 0, DQS1 = 0

 3429 16:51:52.470934  DQM Delay:

 3430 16:51:52.471492  DQM0 = 115, DQM1 = 108

 3431 16:51:52.473955  DQ Delay:

 3432 16:51:52.477515  DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114

 3433 16:51:52.481205  DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114

 3434 16:51:52.483931  DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =106

 3435 16:51:52.487438  DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =112

 3436 16:51:52.487928  

 3437 16:51:52.488399  

 3438 16:51:52.493998  [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps

 3439 16:51:52.497762  CH1 RK0: MR19=303, MR18=FCE1

 3440 16:51:52.504032  CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25

 3441 16:51:52.504457  

 3442 16:51:52.507181  ----->DramcWriteLeveling(PI) begin...

 3443 16:51:52.507665  ==

 3444 16:51:52.511163  Dram Type= 6, Freq= 0, CH_1, rank 1

 3445 16:51:52.514799  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3446 16:51:52.515272  ==

 3447 16:51:52.517663  Write leveling (Byte 0): 28 => 28

 3448 16:51:52.520929  Write leveling (Byte 1): 28 => 28

 3449 16:51:52.524093  DramcWriteLeveling(PI) end<-----

 3450 16:51:52.524642  

 3451 16:51:52.525111  ==

 3452 16:51:52.527404  Dram Type= 6, Freq= 0, CH_1, rank 1

 3453 16:51:52.534548  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3454 16:51:52.534963  ==

 3455 16:51:52.535296  [Gating] SW mode calibration

 3456 16:51:52.544305  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3457 16:51:52.547448  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3458 16:51:52.551006   0 15  0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 3459 16:51:52.557818   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3460 16:51:52.561014   0 15  8 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)

 3461 16:51:52.564290   0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 3462 16:51:52.571331   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3463 16:51:52.574229   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 3464 16:51:52.577798   0 15 24 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (0 1)

 3465 16:51:52.584381   0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)

 3466 16:51:52.587811   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3467 16:51:52.590901   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3468 16:51:52.597936   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3469 16:51:52.600731   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3470 16:51:52.604247   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3471 16:51:52.610745   1  0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 3472 16:51:52.614326   1  0 24 | B1->B0 | 2726 3e3e | 1 0 | (0 0) (0 0)

 3473 16:51:52.617292   1  0 28 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)

 3474 16:51:52.624182   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3475 16:51:52.627075   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3476 16:51:52.630397   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3477 16:51:52.637237   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3478 16:51:52.640535   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3479 16:51:52.643889   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3480 16:51:52.650425   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3481 16:51:52.653620   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 3482 16:51:52.657221   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3483 16:51:52.660402   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3484 16:51:52.666815   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3485 16:51:52.670465   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3486 16:51:52.674021   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3487 16:51:52.680295   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3488 16:51:52.683812   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3489 16:51:52.687279   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3490 16:51:52.693728   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3491 16:51:52.697311   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3492 16:51:52.700882   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3493 16:51:52.707374   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3494 16:51:52.710480   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3495 16:51:52.713934   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3496 16:51:52.720517   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3497 16:51:52.723690   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3498 16:51:52.727019   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3499 16:51:52.730496  Total UI for P1: 0, mck2ui 16

 3500 16:51:52.733420  best dqsien dly found for B0: ( 1,  3, 26)

 3501 16:51:52.736860  Total UI for P1: 0, mck2ui 16

 3502 16:51:52.740398  best dqsien dly found for B1: ( 1,  3, 30)

 3503 16:51:52.743945  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3504 16:51:52.747039  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 3505 16:51:52.747512  

 3506 16:51:52.750397  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3507 16:51:52.756946  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 3508 16:51:52.757442  [Gating] SW calibration Done

 3509 16:51:52.760231  ==

 3510 16:51:52.760720  Dram Type= 6, Freq= 0, CH_1, rank 1

 3511 16:51:52.766889  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3512 16:51:52.767311  ==

 3513 16:51:52.767697  RX Vref Scan: 0

 3514 16:51:52.768054  

 3515 16:51:52.770549  RX Vref 0 -> 0, step: 1

 3516 16:51:52.771175  

 3517 16:51:52.773416  RX Delay -40 -> 252, step: 8

 3518 16:51:52.776765  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 3519 16:51:52.780454  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 3520 16:51:52.783763  iDelay=200, Bit 2, Center 103 (32 ~ 175) 144

 3521 16:51:52.790048  iDelay=200, Bit 3, Center 111 (40 ~ 183) 144

 3522 16:51:52.793767  iDelay=200, Bit 4, Center 111 (40 ~ 183) 144

 3523 16:51:52.797277  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3524 16:51:52.800019  iDelay=200, Bit 6, Center 119 (48 ~ 191) 144

 3525 16:51:52.803668  iDelay=200, Bit 7, Center 111 (40 ~ 183) 144

 3526 16:51:52.810276  iDelay=200, Bit 8, Center 99 (24 ~ 175) 152

 3527 16:51:52.813330  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 3528 16:51:52.816639  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3529 16:51:52.820536  iDelay=200, Bit 11, Center 99 (32 ~ 167) 136

 3530 16:51:52.823900  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 3531 16:51:52.830551  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3532 16:51:52.833714  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3533 16:51:52.836965  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 3534 16:51:52.837409  ==

 3535 16:51:52.840553  Dram Type= 6, Freq= 0, CH_1, rank 1

 3536 16:51:52.843422  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3537 16:51:52.843846  ==

 3538 16:51:52.846728  DQS Delay:

 3539 16:51:52.847144  DQS0 = 0, DQS1 = 0

 3540 16:51:52.849812  DQM Delay:

 3541 16:51:52.850231  DQM0 = 113, DQM1 = 109

 3542 16:51:52.850565  DQ Delay:

 3543 16:51:52.856825  DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111

 3544 16:51:52.860389  DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111

 3545 16:51:52.863510  DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =99

 3546 16:51:52.866789  DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115

 3547 16:51:52.867205  

 3548 16:51:52.867533  

 3549 16:51:52.867846  ==

 3550 16:51:52.869993  Dram Type= 6, Freq= 0, CH_1, rank 1

 3551 16:51:52.873456  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3552 16:51:52.873884  ==

 3553 16:51:52.874212  

 3554 16:51:52.874516  

 3555 16:51:52.876896  	TX Vref Scan disable

 3556 16:51:52.880092   == TX Byte 0 ==

 3557 16:51:52.883602  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3558 16:51:52.886416  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3559 16:51:52.890120   == TX Byte 1 ==

 3560 16:51:52.893695  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3561 16:51:52.896441  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3562 16:51:52.896872  ==

 3563 16:51:52.899828  Dram Type= 6, Freq= 0, CH_1, rank 1

 3564 16:51:52.903281  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3565 16:51:52.903698  ==

 3566 16:51:52.916403  TX Vref=22, minBit 3, minWin=25, winSum=422

 3567 16:51:52.919348  TX Vref=24, minBit 1, minWin=26, winSum=425

 3568 16:51:52.923019  TX Vref=26, minBit 2, minWin=26, winSum=430

 3569 16:51:52.926689  TX Vref=28, minBit 2, minWin=26, winSum=432

 3570 16:51:52.929445  TX Vref=30, minBit 2, minWin=26, winSum=432

 3571 16:51:52.932738  TX Vref=32, minBit 2, minWin=26, winSum=431

 3572 16:51:52.939411  [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 28

 3573 16:51:52.939927  

 3574 16:51:52.942724  Final TX Range 1 Vref 28

 3575 16:51:52.943138  

 3576 16:51:52.943531  ==

 3577 16:51:52.946240  Dram Type= 6, Freq= 0, CH_1, rank 1

 3578 16:51:52.949810  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3579 16:51:52.950263  ==

 3580 16:51:52.953336  

 3581 16:51:52.953746  

 3582 16:51:52.954070  	TX Vref Scan disable

 3583 16:51:52.956248   == TX Byte 0 ==

 3584 16:51:52.959312  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3585 16:51:52.962880  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3586 16:51:52.966296   == TX Byte 1 ==

 3587 16:51:52.969471  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3588 16:51:52.973006  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3589 16:51:52.976028  

 3590 16:51:52.976435  [DATLAT]

 3591 16:51:52.976763  Freq=1200, CH1 RK1

 3592 16:51:52.977070  

 3593 16:51:52.979275  DATLAT Default: 0xd

 3594 16:51:52.979685  0, 0xFFFF, sum = 0

 3595 16:51:52.982765  1, 0xFFFF, sum = 0

 3596 16:51:52.983183  2, 0xFFFF, sum = 0

 3597 16:51:52.985962  3, 0xFFFF, sum = 0

 3598 16:51:52.986381  4, 0xFFFF, sum = 0

 3599 16:51:52.989458  5, 0xFFFF, sum = 0

 3600 16:51:52.993008  6, 0xFFFF, sum = 0

 3601 16:51:52.993426  7, 0xFFFF, sum = 0

 3602 16:51:52.995746  8, 0xFFFF, sum = 0

 3603 16:51:52.996249  9, 0xFFFF, sum = 0

 3604 16:51:52.999348  10, 0xFFFF, sum = 0

 3605 16:51:52.999763  11, 0xFFFF, sum = 0

 3606 16:51:53.002883  12, 0x0, sum = 1

 3607 16:51:53.003298  13, 0x0, sum = 2

 3608 16:51:53.005815  14, 0x0, sum = 3

 3609 16:51:53.006233  15, 0x0, sum = 4

 3610 16:51:53.006564  best_step = 13

 3611 16:51:53.006963  

 3612 16:51:53.009298  ==

 3613 16:51:53.012410  Dram Type= 6, Freq= 0, CH_1, rank 1

 3614 16:51:53.016044  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3615 16:51:53.016459  ==

 3616 16:51:53.016793  RX Vref Scan: 0

 3617 16:51:53.017103  

 3618 16:51:53.019037  RX Vref 0 -> 0, step: 1

 3619 16:51:53.019456  

 3620 16:51:53.022648  RX Delay -21 -> 252, step: 4

 3621 16:51:53.025494  iDelay=191, Bit 0, Center 112 (43 ~ 182) 140

 3622 16:51:53.032241  iDelay=191, Bit 1, Center 110 (43 ~ 178) 136

 3623 16:51:53.035482  iDelay=191, Bit 2, Center 106 (43 ~ 170) 128

 3624 16:51:53.038874  iDelay=191, Bit 3, Center 110 (43 ~ 178) 136

 3625 16:51:53.041938  iDelay=191, Bit 4, Center 114 (47 ~ 182) 136

 3626 16:51:53.045567  iDelay=191, Bit 5, Center 124 (59 ~ 190) 132

 3627 16:51:53.052078  iDelay=191, Bit 6, Center 122 (55 ~ 190) 136

 3628 16:51:53.055583  iDelay=191, Bit 7, Center 108 (43 ~ 174) 132

 3629 16:51:53.058745  iDelay=191, Bit 8, Center 96 (31 ~ 162) 132

 3630 16:51:53.062146  iDelay=191, Bit 9, Center 98 (35 ~ 162) 128

 3631 16:51:53.065409  iDelay=191, Bit 10, Center 110 (43 ~ 178) 136

 3632 16:51:53.068576  iDelay=191, Bit 11, Center 100 (35 ~ 166) 132

 3633 16:51:53.075649  iDelay=191, Bit 12, Center 114 (51 ~ 178) 128

 3634 16:51:53.079070  iDelay=191, Bit 13, Center 120 (55 ~ 186) 132

 3635 16:51:53.082439  iDelay=191, Bit 14, Center 118 (55 ~ 182) 128

 3636 16:51:53.085722  iDelay=191, Bit 15, Center 116 (51 ~ 182) 132

 3637 16:51:53.086135  ==

 3638 16:51:53.089179  Dram Type= 6, Freq= 0, CH_1, rank 1

 3639 16:51:53.095449  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3640 16:51:53.095889  ==

 3641 16:51:53.096284  DQS Delay:

 3642 16:51:53.099043  DQS0 = 0, DQS1 = 0

 3643 16:51:53.099578  DQM Delay:

 3644 16:51:53.102589  DQM0 = 113, DQM1 = 109

 3645 16:51:53.103047  DQ Delay:

 3646 16:51:53.105471  DQ0 =112, DQ1 =110, DQ2 =106, DQ3 =110

 3647 16:51:53.108886  DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =108

 3648 16:51:53.112011  DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100

 3649 16:51:53.115594  DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116

 3650 16:51:53.116157  

 3651 16:51:53.116508  

 3652 16:51:53.125267  [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps

 3653 16:51:53.125684  CH1 RK1: MR19=304, MR18=FA01

 3654 16:51:53.131704  CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26

 3655 16:51:53.135263  [RxdqsGatingPostProcess] freq 1200

 3656 16:51:53.142062  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3657 16:51:53.145088  best DQS0 dly(2T, 0.5T) = (0, 11)

 3658 16:51:53.148596  best DQS1 dly(2T, 0.5T) = (0, 11)

 3659 16:51:53.151985  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3660 16:51:53.154933  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3661 16:51:53.158342  best DQS0 dly(2T, 0.5T) = (0, 11)

 3662 16:51:53.161897  best DQS1 dly(2T, 0.5T) = (0, 11)

 3663 16:51:53.164936  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3664 16:51:53.168327  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3665 16:51:53.168803  Pre-setting of DQS Precalculation

 3666 16:51:53.175192  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3667 16:51:53.181662  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3668 16:51:53.188201  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3669 16:51:53.188616  

 3670 16:51:53.188938  

 3671 16:51:53.191663  [Calibration Summary] 2400 Mbps

 3672 16:51:53.195011  CH 0, Rank 0

 3673 16:51:53.195423  SW Impedance     : PASS

 3674 16:51:53.198326  DUTY Scan        : NO K

 3675 16:51:53.201377  ZQ Calibration   : PASS

 3676 16:51:53.201806  Jitter Meter     : NO K

 3677 16:51:53.204943  CBT Training     : PASS

 3678 16:51:53.207946  Write leveling   : PASS

 3679 16:51:53.208410  RX DQS gating    : PASS

 3680 16:51:53.211629  RX DQ/DQS(RDDQC) : PASS

 3681 16:51:53.212100  TX DQ/DQS        : PASS

 3682 16:51:53.214884  RX DATLAT        : PASS

 3683 16:51:53.217958  RX DQ/DQS(Engine): PASS

 3684 16:51:53.218377  TX OE            : NO K

 3685 16:51:53.221481  All Pass.

 3686 16:51:53.221912  

 3687 16:51:53.222254  CH 0, Rank 1

 3688 16:51:53.224327  SW Impedance     : PASS

 3689 16:51:53.224751  DUTY Scan        : NO K

 3690 16:51:53.227801  ZQ Calibration   : PASS

 3691 16:51:53.231580  Jitter Meter     : NO K

 3692 16:51:53.232138  CBT Training     : PASS

 3693 16:51:53.234516  Write leveling   : PASS

 3694 16:51:53.238134  RX DQS gating    : PASS

 3695 16:51:53.238550  RX DQ/DQS(RDDQC) : PASS

 3696 16:51:53.240962  TX DQ/DQS        : PASS

 3697 16:51:53.244478  RX DATLAT        : PASS

 3698 16:51:53.244890  RX DQ/DQS(Engine): PASS

 3699 16:51:53.247791  TX OE            : NO K

 3700 16:51:53.248251  All Pass.

 3701 16:51:53.248598  

 3702 16:51:53.251343  CH 1, Rank 0

 3703 16:51:53.251766  SW Impedance     : PASS

 3704 16:51:53.254258  DUTY Scan        : NO K

 3705 16:51:53.257481  ZQ Calibration   : PASS

 3706 16:51:53.257797  Jitter Meter     : NO K

 3707 16:51:53.261069  CBT Training     : PASS

 3708 16:51:53.264037  Write leveling   : PASS

 3709 16:51:53.264258  RX DQS gating    : PASS

 3710 16:51:53.267435  RX DQ/DQS(RDDQC) : PASS

 3711 16:51:53.271128  TX DQ/DQS        : PASS

 3712 16:51:53.271279  RX DATLAT        : PASS

 3713 16:51:53.274023  RX DQ/DQS(Engine): PASS

 3714 16:51:53.274176  TX OE            : NO K

 3715 16:51:53.277529  All Pass.

 3716 16:51:53.277680  

 3717 16:51:53.277783  CH 1, Rank 1

 3718 16:51:53.280835  SW Impedance     : PASS

 3719 16:51:53.280948  DUTY Scan        : NO K

 3720 16:51:53.284167  ZQ Calibration   : PASS

 3721 16:51:53.287407  Jitter Meter     : NO K

 3722 16:51:53.287514  CBT Training     : PASS

 3723 16:51:53.290685  Write leveling   : PASS

 3724 16:51:53.294058  RX DQS gating    : PASS

 3725 16:51:53.294217  RX DQ/DQS(RDDQC) : PASS

 3726 16:51:53.297592  TX DQ/DQS        : PASS

 3727 16:51:53.300815  RX DATLAT        : PASS

 3728 16:51:53.300959  RX DQ/DQS(Engine): PASS

 3729 16:51:53.304106  TX OE            : NO K

 3730 16:51:53.304232  All Pass.

 3731 16:51:53.304303  

 3732 16:51:53.307889  DramC Write-DBI off

 3733 16:51:53.311341  	PER_BANK_REFRESH: Hybrid Mode

 3734 16:51:53.311755  TX_TRACKING: ON

 3735 16:51:53.320774  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3736 16:51:53.324487  [FAST_K] Save calibration result to emmc

 3737 16:51:53.327558  dramc_set_vcore_voltage set vcore to 650000

 3738 16:51:53.331198  Read voltage for 600, 5

 3739 16:51:53.331723  Vio18 = 0

 3740 16:51:53.332141  Vcore = 650000

 3741 16:51:53.334369  Vdram = 0

 3742 16:51:53.334913  Vddq = 0

 3743 16:51:53.335388  Vmddr = 0

 3744 16:51:53.340964  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3745 16:51:53.344496  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3746 16:51:53.347454  MEM_TYPE=3, freq_sel=19

 3747 16:51:53.350935  sv_algorithm_assistance_LP4_1600 

 3748 16:51:53.353754  ============ PULL DRAM RESETB DOWN ============

 3749 16:51:53.357177  ========== PULL DRAM RESETB DOWN end =========

 3750 16:51:53.364434  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3751 16:51:53.367347  =================================== 

 3752 16:51:53.367873  LPDDR4 DRAM CONFIGURATION

 3753 16:51:53.370868  =================================== 

 3754 16:51:53.373692  EX_ROW_EN[0]    = 0x0

 3755 16:51:53.377406  EX_ROW_EN[1]    = 0x0

 3756 16:51:53.377817  LP4Y_EN      = 0x0

 3757 16:51:53.380480  WORK_FSP     = 0x0

 3758 16:51:53.380890  WL           = 0x2

 3759 16:51:53.384015  RL           = 0x2

 3760 16:51:53.384429  BL           = 0x2

 3761 16:51:53.387443  RPST         = 0x0

 3762 16:51:53.388046  RD_PRE       = 0x0

 3763 16:51:53.390628  WR_PRE       = 0x1

 3764 16:51:53.391080  WR_PST       = 0x0

 3765 16:51:53.393752  DBI_WR       = 0x0

 3766 16:51:53.394228  DBI_RD       = 0x0

 3767 16:51:53.396883  OTF          = 0x1

 3768 16:51:53.400311  =================================== 

 3769 16:51:53.403643  =================================== 

 3770 16:51:53.404156  ANA top config

 3771 16:51:53.407347  =================================== 

 3772 16:51:53.410575  DLL_ASYNC_EN            =  0

 3773 16:51:53.413429  ALL_SLAVE_EN            =  1

 3774 16:51:53.416784  NEW_RANK_MODE           =  1

 3775 16:51:53.417199  DLL_IDLE_MODE           =  1

 3776 16:51:53.420304  LP45_APHY_COMB_EN       =  1

 3777 16:51:53.423829  TX_ODT_DIS              =  1

 3778 16:51:53.426835  NEW_8X_MODE             =  1

 3779 16:51:53.430472  =================================== 

 3780 16:51:53.433983  =================================== 

 3781 16:51:53.436824  data_rate                  = 1200

 3782 16:51:53.437238  CKR                        = 1

 3783 16:51:53.440320  DQ_P2S_RATIO               = 8

 3784 16:51:53.443478  =================================== 

 3785 16:51:53.446845  CA_P2S_RATIO               = 8

 3786 16:51:53.450149  DQ_CA_OPEN                 = 0

 3787 16:51:53.453418  DQ_SEMI_OPEN               = 0

 3788 16:51:53.456608  CA_SEMI_OPEN               = 0

 3789 16:51:53.457023  CA_FULL_RATE               = 0

 3790 16:51:53.460115  DQ_CKDIV4_EN               = 1

 3791 16:51:53.463785  CA_CKDIV4_EN               = 1

 3792 16:51:53.466518  CA_PREDIV_EN               = 0

 3793 16:51:53.469961  PH8_DLY                    = 0

 3794 16:51:53.473566  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3795 16:51:53.473982  DQ_AAMCK_DIV               = 4

 3796 16:51:53.476662  CA_AAMCK_DIV               = 4

 3797 16:51:53.480321  CA_ADMCK_DIV               = 4

 3798 16:51:53.483131  DQ_TRACK_CA_EN             = 0

 3799 16:51:53.486800  CA_PICK                    = 600

 3800 16:51:53.490267  CA_MCKIO                   = 600

 3801 16:51:53.492963  MCKIO_SEMI                 = 0

 3802 16:51:53.493373  PLL_FREQ                   = 2288

 3803 16:51:53.496647  DQ_UI_PI_RATIO             = 32

 3804 16:51:53.499808  CA_UI_PI_RATIO             = 0

 3805 16:51:53.502981  =================================== 

 3806 16:51:53.506781  =================================== 

 3807 16:51:53.509779  memory_type:LPDDR4         

 3808 16:51:53.510189  GP_NUM     : 10       

 3809 16:51:53.512994  SRAM_EN    : 1       

 3810 16:51:53.516705  MD32_EN    : 0       

 3811 16:51:53.519864  =================================== 

 3812 16:51:53.520557  [ANA_INIT] >>>>>>>>>>>>>> 

 3813 16:51:53.522838  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3814 16:51:53.526767  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3815 16:51:53.529602  =================================== 

 3816 16:51:53.533408  data_rate = 1200,PCW = 0X5800

 3817 16:51:53.536626  =================================== 

 3818 16:51:53.539548  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3819 16:51:53.546742  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3820 16:51:53.549710  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3821 16:51:53.556424  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3822 16:51:53.559685  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3823 16:51:53.562573  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3824 16:51:53.566496  [ANA_INIT] flow start 

 3825 16:51:53.566917  [ANA_INIT] PLL >>>>>>>> 

 3826 16:51:53.569372  [ANA_INIT] PLL <<<<<<<< 

 3827 16:51:53.572877  [ANA_INIT] MIDPI >>>>>>>> 

 3828 16:51:53.573289  [ANA_INIT] MIDPI <<<<<<<< 

 3829 16:51:53.576326  [ANA_INIT] DLL >>>>>>>> 

 3830 16:51:53.579805  [ANA_INIT] flow end 

 3831 16:51:53.582784  ============ LP4 DIFF to SE enter ============

 3832 16:51:53.586382  ============ LP4 DIFF to SE exit  ============

 3833 16:51:53.589476  [ANA_INIT] <<<<<<<<<<<<< 

 3834 16:51:53.593077  [Flow] Enable top DCM control >>>>> 

 3835 16:51:53.595896  [Flow] Enable top DCM control <<<<< 

 3836 16:51:53.599799  Enable DLL master slave shuffle 

 3837 16:51:53.603124  ============================================================== 

 3838 16:51:53.605924  Gating Mode config

 3839 16:51:53.612535  ============================================================== 

 3840 16:51:53.612986  Config description: 

 3841 16:51:53.622640  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3842 16:51:53.629293  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3843 16:51:53.633078  SELPH_MODE            0: By rank         1: By Phase 

 3844 16:51:53.639310  ============================================================== 

 3845 16:51:53.642789  GAT_TRACK_EN                 =  1

 3846 16:51:53.645769  RX_GATING_MODE               =  2

 3847 16:51:53.649393  RX_GATING_TRACK_MODE         =  2

 3848 16:51:53.652829  SELPH_MODE                   =  1

 3849 16:51:53.655785  PICG_EARLY_EN                =  1

 3850 16:51:53.659447  VALID_LAT_VALUE              =  1

 3851 16:51:53.662242  ============================================================== 

 3852 16:51:53.665913  Enter into Gating configuration >>>> 

 3853 16:51:53.669323  Exit from Gating configuration <<<< 

 3854 16:51:53.672680  Enter into  DVFS_PRE_config >>>>> 

 3855 16:51:53.682794  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3856 16:51:53.685774  Exit from  DVFS_PRE_config <<<<< 

 3857 16:51:53.689289  Enter into PICG configuration >>>> 

 3858 16:51:53.692449  Exit from PICG configuration <<<< 

 3859 16:51:53.695635  [RX_INPUT] configuration >>>>> 

 3860 16:51:53.699310  [RX_INPUT] configuration <<<<< 

 3861 16:51:53.705743  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3862 16:51:53.709265  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3863 16:51:53.715276  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3864 16:51:53.722002  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3865 16:51:53.728502  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3866 16:51:53.735005  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3867 16:51:53.738700  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3868 16:51:53.742108  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3869 16:51:53.745119  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3870 16:51:53.752184  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3871 16:51:53.755001  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3872 16:51:53.758538  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3873 16:51:53.762146  =================================== 

 3874 16:51:53.765289  LPDDR4 DRAM CONFIGURATION

 3875 16:51:53.768741  =================================== 

 3876 16:51:53.768822  EX_ROW_EN[0]    = 0x0

 3877 16:51:53.771716  EX_ROW_EN[1]    = 0x0

 3878 16:51:53.771797  LP4Y_EN      = 0x0

 3879 16:51:53.774908  WORK_FSP     = 0x0

 3880 16:51:53.778309  WL           = 0x2

 3881 16:51:53.778391  RL           = 0x2

 3882 16:51:53.781996  BL           = 0x2

 3883 16:51:53.782077  RPST         = 0x0

 3884 16:51:53.784991  RD_PRE       = 0x0

 3885 16:51:53.785087  WR_PRE       = 0x1

 3886 16:51:53.788466  WR_PST       = 0x0

 3887 16:51:53.788552  DBI_WR       = 0x0

 3888 16:51:53.792058  DBI_RD       = 0x0

 3889 16:51:53.792151  OTF          = 0x1

 3890 16:51:53.795193  =================================== 

 3891 16:51:53.798212  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3892 16:51:53.805338  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3893 16:51:53.808176  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3894 16:51:53.811914  =================================== 

 3895 16:51:53.815266  LPDDR4 DRAM CONFIGURATION

 3896 16:51:53.818740  =================================== 

 3897 16:51:53.818890  EX_ROW_EN[0]    = 0x10

 3898 16:51:53.822136  EX_ROW_EN[1]    = 0x0

 3899 16:51:53.822305  LP4Y_EN      = 0x0

 3900 16:51:53.825077  WORK_FSP     = 0x0

 3901 16:51:53.825274  WL           = 0x2

 3902 16:51:53.828420  RL           = 0x2

 3903 16:51:53.828616  BL           = 0x2

 3904 16:51:53.831748  RPST         = 0x0

 3905 16:51:53.831999  RD_PRE       = 0x0

 3906 16:51:53.834927  WR_PRE       = 0x1

 3907 16:51:53.838321  WR_PST       = 0x0

 3908 16:51:53.838614  DBI_WR       = 0x0

 3909 16:51:53.842191  DBI_RD       = 0x0

 3910 16:51:53.842588  OTF          = 0x1

 3911 16:51:53.845300  =================================== 

 3912 16:51:53.851913  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3913 16:51:53.855338  nWR fixed to 30

 3914 16:51:53.859091  [ModeRegInit_LP4] CH0 RK0

 3915 16:51:53.859505  [ModeRegInit_LP4] CH0 RK1

 3916 16:51:53.862089  [ModeRegInit_LP4] CH1 RK0

 3917 16:51:53.865569  [ModeRegInit_LP4] CH1 RK1

 3918 16:51:53.865985  match AC timing 17

 3919 16:51:53.872056  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3920 16:51:53.875510  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3921 16:51:53.879014  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3922 16:51:53.885438  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3923 16:51:53.889045  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3924 16:51:53.889465  ==

 3925 16:51:53.892071  Dram Type= 6, Freq= 0, CH_0, rank 0

 3926 16:51:53.895716  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3927 16:51:53.896176  ==

 3928 16:51:53.902226  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3929 16:51:53.908868  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 3930 16:51:53.911991  [CA 0] Center 36 (6~66) winsize 61

 3931 16:51:53.915067  [CA 1] Center 36 (6~66) winsize 61

 3932 16:51:53.918767  [CA 2] Center 34 (4~65) winsize 62

 3933 16:51:53.921644  [CA 3] Center 34 (4~65) winsize 62

 3934 16:51:53.925666  [CA 4] Center 34 (4~64) winsize 61

 3935 16:51:53.928457  [CA 5] Center 33 (3~64) winsize 62

 3936 16:51:53.928873  

 3937 16:51:53.932064  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3938 16:51:53.932478  

 3939 16:51:53.935018  [CATrainingPosCal] consider 1 rank data

 3940 16:51:53.938603  u2DelayCellTimex100 = 270/100 ps

 3941 16:51:53.941816  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 3942 16:51:53.944924  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 3943 16:51:53.948315  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3944 16:51:53.951580  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 3945 16:51:53.954898  CA4 delay=34 (4~64),Diff = 1 PI (9 cell)

 3946 16:51:53.961997  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3947 16:51:53.962418  

 3948 16:51:53.964934  CA PerBit enable=1, Macro0, CA PI delay=33

 3949 16:51:53.965479  

 3950 16:51:53.968322  [CBTSetCACLKResult] CA Dly = 33

 3951 16:51:53.968735  CS Dly: 5 (0~36)

 3952 16:51:53.969067  ==

 3953 16:51:53.971916  Dram Type= 6, Freq= 0, CH_0, rank 1

 3954 16:51:53.975462  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3955 16:51:53.978391  ==

 3956 16:51:53.981653  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3957 16:51:53.988281  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3958 16:51:53.991999  [CA 0] Center 36 (6~66) winsize 61

 3959 16:51:53.994863  [CA 1] Center 36 (6~66) winsize 61

 3960 16:51:53.998478  [CA 2] Center 34 (4~65) winsize 62

 3961 16:51:54.001832  [CA 3] Center 34 (4~65) winsize 62

 3962 16:51:54.005057  [CA 4] Center 33 (3~64) winsize 62

 3963 16:51:54.008517  [CA 5] Center 33 (3~64) winsize 62

 3964 16:51:54.008932  

 3965 16:51:54.011471  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3966 16:51:54.011886  

 3967 16:51:54.015009  [CATrainingPosCal] consider 2 rank data

 3968 16:51:54.018309  u2DelayCellTimex100 = 270/100 ps

 3969 16:51:54.021961  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 3970 16:51:54.024886  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 3971 16:51:54.028244  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3972 16:51:54.031338  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 3973 16:51:54.037779  CA4 delay=34 (4~64),Diff = 1 PI (9 cell)

 3974 16:51:54.041363  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3975 16:51:54.041781  

 3976 16:51:54.044774  CA PerBit enable=1, Macro0, CA PI delay=33

 3977 16:51:54.045195  

 3978 16:51:54.048342  [CBTSetCACLKResult] CA Dly = 33

 3979 16:51:54.048857  CS Dly: 5 (0~36)

 3980 16:51:54.049237  

 3981 16:51:54.051403  ----->DramcWriteLeveling(PI) begin...

 3982 16:51:54.051825  ==

 3983 16:51:54.054764  Dram Type= 6, Freq= 0, CH_0, rank 0

 3984 16:51:54.061365  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3985 16:51:54.061788  ==

 3986 16:51:54.064350  Write leveling (Byte 0): 32 => 32

 3987 16:51:54.068226  Write leveling (Byte 1): 30 => 30

 3988 16:51:54.068651  DramcWriteLeveling(PI) end<-----

 3989 16:51:54.068986  

 3990 16:51:54.071672  ==

 3991 16:51:54.074507  Dram Type= 6, Freq= 0, CH_0, rank 0

 3992 16:51:54.077957  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3993 16:51:54.078401  ==

 3994 16:51:54.080898  [Gating] SW mode calibration

 3995 16:51:54.087474  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 3996 16:51:54.091137  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 3997 16:51:54.097443   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3998 16:51:54.101070   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3999 16:51:54.104214   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4000 16:51:54.110857   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4001 16:51:54.114325   0  9 16 | B1->B0 | 3131 2e2e | 1 1 | (1 0) (1 0)

 4002 16:51:54.117627   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4003 16:51:54.123705   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4004 16:51:54.127119   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4005 16:51:54.130696   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4006 16:51:54.137445   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4007 16:51:54.140739   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4008 16:51:54.143827   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4009 16:51:54.150320   0 10 16 | B1->B0 | 2f2f 3838 | 0 0 | (0 0) (0 0)

 4010 16:51:54.154159   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4011 16:51:54.157405   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4012 16:51:54.163845   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4013 16:51:54.166925   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4014 16:51:54.170319   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4015 16:51:54.176950   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4016 16:51:54.180167   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 4017 16:51:54.183539   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4018 16:51:54.190752   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4019 16:51:54.193535   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4020 16:51:54.196933   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4021 16:51:54.203397   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4022 16:51:54.206996   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4023 16:51:54.209922   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4024 16:51:54.216440   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4025 16:51:54.220079   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4026 16:51:54.223113   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4027 16:51:54.226640   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4028 16:51:54.233313   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4029 16:51:54.236566   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4030 16:51:54.240077   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4031 16:51:54.246255   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4032 16:51:54.249877   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4033 16:51:54.253533   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4034 16:51:54.256388  Total UI for P1: 0, mck2ui 16

 4035 16:51:54.260142  best dqsien dly found for B0: ( 0, 13, 14)

 4036 16:51:54.266544   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4037 16:51:54.269605   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4038 16:51:54.273044  Total UI for P1: 0, mck2ui 16

 4039 16:51:54.276266  best dqsien dly found for B1: ( 0, 13, 18)

 4040 16:51:54.279993  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4041 16:51:54.282789  best DQS1 dly(MCK, UI, PI) = (0, 13, 18)

 4042 16:51:54.282872  

 4043 16:51:54.286116  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4044 16:51:54.290034  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)

 4045 16:51:54.292844  [Gating] SW calibration Done

 4046 16:51:54.292926  ==

 4047 16:51:54.296453  Dram Type= 6, Freq= 0, CH_0, rank 0

 4048 16:51:54.302748  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4049 16:51:54.302846  ==

 4050 16:51:54.302920  RX Vref Scan: 0

 4051 16:51:54.302990  

 4052 16:51:54.306524  RX Vref 0 -> 0, step: 1

 4053 16:51:54.306628  

 4054 16:51:54.309994  RX Delay -230 -> 252, step: 16

 4055 16:51:54.312825  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4056 16:51:54.316458  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4057 16:51:54.319928  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4058 16:51:54.326456  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4059 16:51:54.329391  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4060 16:51:54.333264  iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336

 4061 16:51:54.336108  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4062 16:51:54.343259  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4063 16:51:54.346166  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4064 16:51:54.349356  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4065 16:51:54.352981  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4066 16:51:54.356108  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4067 16:51:54.362850  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4068 16:51:54.366433  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4069 16:51:54.369966  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4070 16:51:54.372768  iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336

 4071 16:51:54.376045  ==

 4072 16:51:54.379599  Dram Type= 6, Freq= 0, CH_0, rank 0

 4073 16:51:54.382854  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4074 16:51:54.383273  ==

 4075 16:51:54.383605  DQS Delay:

 4076 16:51:54.386031  DQS0 = 0, DQS1 = 0

 4077 16:51:54.386445  DQM Delay:

 4078 16:51:54.389596  DQM0 = 41, DQM1 = 33

 4079 16:51:54.390012  DQ Delay:

 4080 16:51:54.392534  DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41

 4081 16:51:54.395837  DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49

 4082 16:51:54.399767  DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25

 4083 16:51:54.402741  DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49

 4084 16:51:54.403157  

 4085 16:51:54.403493  

 4086 16:51:54.403801  ==

 4087 16:51:54.406144  Dram Type= 6, Freq= 0, CH_0, rank 0

 4088 16:51:54.409440  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4089 16:51:54.409951  ==

 4090 16:51:54.410288  

 4091 16:51:54.410595  

 4092 16:51:54.412531  	TX Vref Scan disable

 4093 16:51:54.416293   == TX Byte 0 ==

 4094 16:51:54.419311  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4095 16:51:54.422644  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4096 16:51:54.426351   == TX Byte 1 ==

 4097 16:51:54.429372  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4098 16:51:54.432810  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4099 16:51:54.433227  ==

 4100 16:51:54.436511  Dram Type= 6, Freq= 0, CH_0, rank 0

 4101 16:51:54.442328  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4102 16:51:54.442780  ==

 4103 16:51:54.443279  

 4104 16:51:54.443609  

 4105 16:51:54.443916  	TX Vref Scan disable

 4106 16:51:54.446884   == TX Byte 0 ==

 4107 16:51:54.449909  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4108 16:51:54.456534  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4109 16:51:54.456950   == TX Byte 1 ==

 4110 16:51:54.459879  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4111 16:51:54.466527  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4112 16:51:54.466946  

 4113 16:51:54.467278  [DATLAT]

 4114 16:51:54.467584  Freq=600, CH0 RK0

 4115 16:51:54.467887  

 4116 16:51:54.469718  DATLAT Default: 0x9

 4117 16:51:54.473340  0, 0xFFFF, sum = 0

 4118 16:51:54.473764  1, 0xFFFF, sum = 0

 4119 16:51:54.476171  2, 0xFFFF, sum = 0

 4120 16:51:54.476598  3, 0xFFFF, sum = 0

 4121 16:51:54.479941  4, 0xFFFF, sum = 0

 4122 16:51:54.480400  5, 0xFFFF, sum = 0

 4123 16:51:54.483519  6, 0xFFFF, sum = 0

 4124 16:51:54.484028  7, 0xFFFF, sum = 0

 4125 16:51:54.486425  8, 0x0, sum = 1

 4126 16:51:54.486853  9, 0x0, sum = 2

 4127 16:51:54.487340  10, 0x0, sum = 3

 4128 16:51:54.489853  11, 0x0, sum = 4

 4129 16:51:54.490274  best_step = 9

 4130 16:51:54.490635  

 4131 16:51:54.491070  ==

 4132 16:51:54.492998  Dram Type= 6, Freq= 0, CH_0, rank 0

 4133 16:51:54.499701  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4134 16:51:54.500137  ==

 4135 16:51:54.500471  RX Vref Scan: 1

 4136 16:51:54.500781  

 4137 16:51:54.502782  RX Vref 0 -> 0, step: 1

 4138 16:51:54.503201  

 4139 16:51:54.506140  RX Delay -195 -> 252, step: 8

 4140 16:51:54.506557  

 4141 16:51:54.509602  Set Vref, RX VrefLevel [Byte0]: 56

 4142 16:51:54.513271                           [Byte1]: 52

 4143 16:51:54.513687  

 4144 16:51:54.516431  Final RX Vref Byte 0 = 56 to rank0

 4145 16:51:54.519449  Final RX Vref Byte 1 = 52 to rank0

 4146 16:51:54.522785  Final RX Vref Byte 0 = 56 to rank1

 4147 16:51:54.526021  Final RX Vref Byte 1 = 52 to rank1==

 4148 16:51:54.529507  Dram Type= 6, Freq= 0, CH_0, rank 0

 4149 16:51:54.532904  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4150 16:51:54.533323  ==

 4151 16:51:54.536043  DQS Delay:

 4152 16:51:54.536731  DQS0 = 0, DQS1 = 0

 4153 16:51:54.540009  DQM Delay:

 4154 16:51:54.540566  DQM0 = 43, DQM1 = 33

 4155 16:51:54.542368  DQ Delay:

 4156 16:51:54.542778  DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40

 4157 16:51:54.548954  DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52

 4158 16:51:54.549712  DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28

 4159 16:51:54.552540  DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44

 4160 16:51:54.552974  

 4161 16:51:54.556057  

 4162 16:51:54.562722  [DQSOSCAuto] RK0, (LSB)MR18= 0x3a18, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps

 4163 16:51:54.565486  CH0 RK0: MR19=808, MR18=3A18

 4164 16:51:54.572454  CH0_RK0: MR19=0x808, MR18=0x3A18, DQSOSC=398, MR23=63, INC=165, DEC=110

 4165 16:51:54.572884  

 4166 16:51:54.575909  ----->DramcWriteLeveling(PI) begin...

 4167 16:51:54.576380  ==

 4168 16:51:54.579366  Dram Type= 6, Freq= 0, CH_0, rank 1

 4169 16:51:54.582262  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4170 16:51:54.582693  ==

 4171 16:51:54.585619  Write leveling (Byte 0): 32 => 32

 4172 16:51:54.588893  Write leveling (Byte 1): 32 => 32

 4173 16:51:54.592009  DramcWriteLeveling(PI) end<-----

 4174 16:51:54.592246  

 4175 16:51:54.592430  ==

 4176 16:51:54.595359  Dram Type= 6, Freq= 0, CH_0, rank 1

 4177 16:51:54.598484  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4178 16:51:54.598832  ==

 4179 16:51:54.602180  [Gating] SW mode calibration

 4180 16:51:54.608576  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4181 16:51:54.615279  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4182 16:51:54.618370   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4183 16:51:54.621639   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4184 16:51:54.628714   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4185 16:51:54.631526   0  9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)

 4186 16:51:54.635172   0  9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)

 4187 16:51:54.641398   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4188 16:51:54.644944   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4189 16:51:54.648187   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4190 16:51:54.655384   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4191 16:51:54.658302   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4192 16:51:54.661342   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4193 16:51:54.668089   0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)

 4194 16:51:54.671770   0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)

 4195 16:51:54.674500   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4196 16:51:54.681361   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4197 16:51:54.684439   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4198 16:51:54.687891   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4199 16:51:54.694320   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4200 16:51:54.697800   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4201 16:51:54.701192   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4202 16:51:54.708041   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4203 16:51:54.711090   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4204 16:51:54.714174   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4205 16:51:54.720590   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4206 16:51:54.724715   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4207 16:51:54.727934   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4208 16:51:54.734272   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4209 16:51:54.737800   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4210 16:51:54.740988   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4211 16:51:54.747488   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4212 16:51:54.750892   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4213 16:51:54.753879   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4214 16:51:54.760787   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4215 16:51:54.764324   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4216 16:51:54.767286   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4217 16:51:54.770905   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4218 16:51:54.777146   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4219 16:51:54.780905  Total UI for P1: 0, mck2ui 16

 4220 16:51:54.784387  best dqsien dly found for B0: ( 0, 13, 12)

 4221 16:51:54.787172  Total UI for P1: 0, mck2ui 16

 4222 16:51:54.790822  best dqsien dly found for B1: ( 0, 13, 14)

 4223 16:51:54.794120  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4224 16:51:54.797090  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4225 16:51:54.797193  

 4226 16:51:54.800593  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4227 16:51:54.804238  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4228 16:51:54.807624  [Gating] SW calibration Done

 4229 16:51:54.807737  ==

 4230 16:51:54.810614  Dram Type= 6, Freq= 0, CH_0, rank 1

 4231 16:51:54.813972  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4232 16:51:54.814106  ==

 4233 16:51:54.817407  RX Vref Scan: 0

 4234 16:51:54.817524  

 4235 16:51:54.820799  RX Vref 0 -> 0, step: 1

 4236 16:51:54.820905  

 4237 16:51:54.820998  RX Delay -230 -> 252, step: 16

 4238 16:51:54.827135  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4239 16:51:54.830605  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4240 16:51:54.833601  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4241 16:51:54.837032  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4242 16:51:54.844137  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4243 16:51:54.847024  iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320

 4244 16:51:54.850444  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4245 16:51:54.853845  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4246 16:51:54.857281  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4247 16:51:54.863728  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4248 16:51:54.867241  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4249 16:51:54.870076  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4250 16:51:54.873683  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4251 16:51:54.880214  iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320

 4252 16:51:54.883835  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4253 16:51:54.886941  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4254 16:51:54.887025  ==

 4255 16:51:54.890458  Dram Type= 6, Freq= 0, CH_0, rank 1

 4256 16:51:54.893841  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4257 16:51:54.896814  ==

 4258 16:51:54.896929  DQS Delay:

 4259 16:51:54.897023  DQS0 = 0, DQS1 = 0

 4260 16:51:54.900403  DQM Delay:

 4261 16:51:54.900506  DQM0 = 40, DQM1 = 33

 4262 16:51:54.903779  DQ Delay:

 4263 16:51:54.906816  DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41

 4264 16:51:54.906917  DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49

 4265 16:51:54.910159  DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25

 4266 16:51:54.913464  DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41

 4267 16:51:54.916450  

 4268 16:51:54.916564  

 4269 16:51:54.916661  ==

 4270 16:51:54.919782  Dram Type= 6, Freq= 0, CH_0, rank 1

 4271 16:51:54.923292  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4272 16:51:54.923413  ==

 4273 16:51:54.923507  

 4274 16:51:54.923598  

 4275 16:51:54.926623  	TX Vref Scan disable

 4276 16:51:54.926728   == TX Byte 0 ==

 4277 16:51:54.933689  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4278 16:51:54.936676  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4279 16:51:54.936759   == TX Byte 1 ==

 4280 16:51:54.943126  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4281 16:51:54.946598  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4282 16:51:54.946683  ==

 4283 16:51:54.950228  Dram Type= 6, Freq= 0, CH_0, rank 1

 4284 16:51:54.953403  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4285 16:51:54.953491  ==

 4286 16:51:54.953554  

 4287 16:51:54.953614  

 4288 16:51:54.956756  	TX Vref Scan disable

 4289 16:51:54.960034   == TX Byte 0 ==

 4290 16:51:54.963290  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4291 16:51:54.966158  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4292 16:51:54.969949   == TX Byte 1 ==

 4293 16:51:54.973320  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4294 16:51:54.976487  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4295 16:51:54.980031  

 4296 16:51:54.980126  [DATLAT]

 4297 16:51:54.980189  Freq=600, CH0 RK1

 4298 16:51:54.980248  

 4299 16:51:54.982905  DATLAT Default: 0x9

 4300 16:51:54.982985  0, 0xFFFF, sum = 0

 4301 16:51:54.986423  1, 0xFFFF, sum = 0

 4302 16:51:54.986505  2, 0xFFFF, sum = 0

 4303 16:51:54.989948  3, 0xFFFF, sum = 0

 4304 16:51:54.990029  4, 0xFFFF, sum = 0

 4305 16:51:54.992833  5, 0xFFFF, sum = 0

 4306 16:51:54.996565  6, 0xFFFF, sum = 0

 4307 16:51:54.996649  7, 0xFFFF, sum = 0

 4308 16:51:54.996713  8, 0x0, sum = 1

 4309 16:51:54.999645  9, 0x0, sum = 2

 4310 16:51:54.999754  10, 0x0, sum = 3

 4311 16:51:55.002890  11, 0x0, sum = 4

 4312 16:51:55.002971  best_step = 9

 4313 16:51:55.003033  

 4314 16:51:55.003092  ==

 4315 16:51:55.006290  Dram Type= 6, Freq= 0, CH_0, rank 1

 4316 16:51:55.013179  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4317 16:51:55.013263  ==

 4318 16:51:55.013326  RX Vref Scan: 0

 4319 16:51:55.013385  

 4320 16:51:55.016537  RX Vref 0 -> 0, step: 1

 4321 16:51:55.016617  

 4322 16:51:55.019963  RX Delay -195 -> 252, step: 8

 4323 16:51:55.023472  iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312

 4324 16:51:55.030273  iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304

 4325 16:51:55.033058  iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312

 4326 16:51:55.036197  iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312

 4327 16:51:55.039408  iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312

 4328 16:51:55.042677  iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312

 4329 16:51:55.049555  iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312

 4330 16:51:55.053117  iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312

 4331 16:51:55.056108  iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312

 4332 16:51:55.059297  iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312

 4333 16:51:55.065906  iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304

 4334 16:51:55.069191  iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304

 4335 16:51:55.072842  iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320

 4336 16:51:55.075895  iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320

 4337 16:51:55.082698  iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304

 4338 16:51:55.085960  iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312

 4339 16:51:55.086046  ==

 4340 16:51:55.089433  Dram Type= 6, Freq= 0, CH_0, rank 1

 4341 16:51:55.092520  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4342 16:51:55.092602  ==

 4343 16:51:55.095879  DQS Delay:

 4344 16:51:55.095966  DQS0 = 0, DQS1 = 0

 4345 16:51:55.096060  DQM Delay:

 4346 16:51:55.099786  DQM0 = 41, DQM1 = 33

 4347 16:51:55.099866  DQ Delay:

 4348 16:51:55.102268  DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40

 4349 16:51:55.105882  DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48

 4350 16:51:55.109276  DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28

 4351 16:51:55.112309  DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40

 4352 16:51:55.112390  

 4353 16:51:55.112453  

 4354 16:51:55.122809  [DQSOSCAuto] RK1, (LSB)MR18= 0x4828, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps

 4355 16:51:55.122900  CH0 RK1: MR19=808, MR18=4828

 4356 16:51:55.129229  CH0_RK1: MR19=0x808, MR18=0x4828, DQSOSC=396, MR23=63, INC=167, DEC=111

 4357 16:51:55.132437  [RxdqsGatingPostProcess] freq 600

 4358 16:51:55.138862  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4359 16:51:55.142660  Pre-setting of DQS Precalculation

 4360 16:51:55.145553  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4361 16:51:55.145638  ==

 4362 16:51:55.149194  Dram Type= 6, Freq= 0, CH_1, rank 0

 4363 16:51:55.155469  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4364 16:51:55.155555  ==

 4365 16:51:55.159297  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4366 16:51:55.165404  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4367 16:51:55.168814  [CA 0] Center 35 (5~66) winsize 62

 4368 16:51:55.172363  [CA 1] Center 35 (5~66) winsize 62

 4369 16:51:55.175242  [CA 2] Center 33 (3~64) winsize 62

 4370 16:51:55.178991  [CA 3] Center 33 (3~64) winsize 62

 4371 16:51:55.182502  [CA 4] Center 34 (3~65) winsize 63

 4372 16:51:55.185652  [CA 5] Center 33 (2~64) winsize 63

 4373 16:51:55.185734  

 4374 16:51:55.188459  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4375 16:51:55.188561  

 4376 16:51:55.192074  [CATrainingPosCal] consider 1 rank data

 4377 16:51:55.195494  u2DelayCellTimex100 = 270/100 ps

 4378 16:51:55.198593  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4379 16:51:55.201804  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4380 16:51:55.208791  CA2 delay=33 (3~64),Diff = 0 PI (0 cell)

 4381 16:51:55.212342  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4382 16:51:55.215247  CA4 delay=34 (3~65),Diff = 1 PI (9 cell)

 4383 16:51:55.218773  CA5 delay=33 (2~64),Diff = 0 PI (0 cell)

 4384 16:51:55.218866  

 4385 16:51:55.222018  CA PerBit enable=1, Macro0, CA PI delay=33

 4386 16:51:55.222197  

 4387 16:51:55.225220  [CBTSetCACLKResult] CA Dly = 33

 4388 16:51:55.225383  CS Dly: 5 (0~36)

 4389 16:51:55.228433  ==

 4390 16:51:55.231904  Dram Type= 6, Freq= 0, CH_1, rank 1

 4391 16:51:55.235122  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4392 16:51:55.235273  ==

 4393 16:51:55.238526  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4394 16:51:55.244986  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4395 16:51:55.248717  [CA 0] Center 35 (5~66) winsize 62

 4396 16:51:55.252168  [CA 1] Center 35 (5~66) winsize 62

 4397 16:51:55.255417  [CA 2] Center 34 (4~65) winsize 62

 4398 16:51:55.258838  [CA 3] Center 33 (3~64) winsize 62

 4399 16:51:55.262307  [CA 4] Center 34 (3~65) winsize 63

 4400 16:51:55.265547  [CA 5] Center 33 (3~64) winsize 62

 4401 16:51:55.265713  

 4402 16:51:55.268944  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4403 16:51:55.269083  

 4404 16:51:55.271915  [CATrainingPosCal] consider 2 rank data

 4405 16:51:55.275535  u2DelayCellTimex100 = 270/100 ps

 4406 16:51:55.278758  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4407 16:51:55.285694  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4408 16:51:55.288815  CA2 delay=34 (4~64),Diff = 1 PI (9 cell)

 4409 16:51:55.292242  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4410 16:51:55.295497  CA4 delay=34 (3~65),Diff = 1 PI (9 cell)

 4411 16:51:55.298526  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4412 16:51:55.298708  

 4413 16:51:55.302121  CA PerBit enable=1, Macro0, CA PI delay=33

 4414 16:51:55.302317  

 4415 16:51:55.305347  [CBTSetCACLKResult] CA Dly = 33

 4416 16:51:55.308905  CS Dly: 5 (0~36)

 4417 16:51:55.309109  

 4418 16:51:55.311577  ----->DramcWriteLeveling(PI) begin...

 4419 16:51:55.311752  ==

 4420 16:51:55.315336  Dram Type= 6, Freq= 0, CH_1, rank 0

 4421 16:51:55.318788  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4422 16:51:55.319040  ==

 4423 16:51:55.321630  Write leveling (Byte 0): 28 => 28

 4424 16:51:55.325127  Write leveling (Byte 1): 30 => 30

 4425 16:51:55.328550  DramcWriteLeveling(PI) end<-----

 4426 16:51:55.328852  

 4427 16:51:55.329040  ==

 4428 16:51:55.331590  Dram Type= 6, Freq= 0, CH_1, rank 0

 4429 16:51:55.335306  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4430 16:51:55.335578  ==

 4431 16:51:55.338863  [Gating] SW mode calibration

 4432 16:51:55.345284  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4433 16:51:55.352345  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4434 16:51:55.355220   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4435 16:51:55.358352   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4436 16:51:55.365513   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4437 16:51:55.368532   0  9 12 | B1->B0 | 3434 3232 | 1 0 | (0 0) (0 0)

 4438 16:51:55.372018   0  9 16 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)

 4439 16:51:55.378314   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4440 16:51:55.381567   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4441 16:51:55.385125   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4442 16:51:55.392176   0 10  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4443 16:51:55.395333   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4444 16:51:55.398689   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4445 16:51:55.404890   0 10 12 | B1->B0 | 2727 2a2a | 0 0 | (0 0) (0 0)

 4446 16:51:55.408286   0 10 16 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)

 4447 16:51:55.411850   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4448 16:51:55.414646   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4449 16:51:55.421819   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4450 16:51:55.424671   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4451 16:51:55.428423   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4452 16:51:55.435077   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4453 16:51:55.437899   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4454 16:51:55.441255   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 4455 16:51:55.448148   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4456 16:51:55.451424   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4457 16:51:55.454737   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4458 16:51:55.461392   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4459 16:51:55.464805   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4460 16:51:55.468415   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4461 16:51:55.475001   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4462 16:51:55.477830   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4463 16:51:55.481025   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4464 16:51:55.487764   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4465 16:51:55.491655   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4466 16:51:55.494510   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4467 16:51:55.501156   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4468 16:51:55.504402   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4469 16:51:55.508336   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4470 16:51:55.514803   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 4471 16:51:55.515371  Total UI for P1: 0, mck2ui 16

 4472 16:51:55.521377  best dqsien dly found for B1: ( 0, 13, 14)

 4473 16:51:55.524900   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4474 16:51:55.528555  Total UI for P1: 0, mck2ui 16

 4475 16:51:55.531272  best dqsien dly found for B0: ( 0, 13, 14)

 4476 16:51:55.534449  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4477 16:51:55.537877  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4478 16:51:55.538372  

 4479 16:51:55.541372  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4480 16:51:55.544956  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4481 16:51:55.548019  [Gating] SW calibration Done

 4482 16:51:55.548507  ==

 4483 16:51:55.550933  Dram Type= 6, Freq= 0, CH_1, rank 0

 4484 16:51:55.554526  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4485 16:51:55.554995  ==

 4486 16:51:55.557842  RX Vref Scan: 0

 4487 16:51:55.558367  

 4488 16:51:55.563622  RX Vref 0 -> 0, step: 1

 4489 16:51:55.564088  

 4490 16:51:55.564754  RX Delay -230 -> 252, step: 16

 4491 16:51:55.567701  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4492 16:51:55.571029  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4493 16:51:55.574356  iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320

 4494 16:51:55.577388  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4495 16:51:55.583991  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4496 16:51:55.587291  iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336

 4497 16:51:55.590389  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4498 16:51:55.594243  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4499 16:51:55.600532  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4500 16:51:55.603878  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4501 16:51:55.607197  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4502 16:51:55.610456  iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336

 4503 16:51:55.617102  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4504 16:51:55.620376  iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320

 4505 16:51:55.623926  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4506 16:51:55.627318  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4507 16:51:55.627742  ==

 4508 16:51:55.631171  Dram Type= 6, Freq= 0, CH_1, rank 0

 4509 16:51:55.637302  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4510 16:51:55.637873  ==

 4511 16:51:55.638228  DQS Delay:

 4512 16:51:55.640676  DQS0 = 0, DQS1 = 0

 4513 16:51:55.641145  DQM Delay:

 4514 16:51:55.641482  DQM0 = 42, DQM1 = 35

 4515 16:51:55.644080  DQ Delay:

 4516 16:51:55.647038  DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41

 4517 16:51:55.650505  DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41

 4518 16:51:55.654055  DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33

 4519 16:51:55.657275  DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41

 4520 16:51:55.657699  

 4521 16:51:55.658032  

 4522 16:51:55.658363  ==

 4523 16:51:55.660722  Dram Type= 6, Freq= 0, CH_1, rank 0

 4524 16:51:55.663676  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4525 16:51:55.664170  ==

 4526 16:51:55.664511  

 4527 16:51:55.664848  

 4528 16:51:55.667044  	TX Vref Scan disable

 4529 16:51:55.667462   == TX Byte 0 ==

 4530 16:51:55.673442  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4531 16:51:55.676901  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4532 16:51:55.680419   == TX Byte 1 ==

 4533 16:51:55.683481  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4534 16:51:55.687722  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4535 16:51:55.688188  ==

 4536 16:51:55.690607  Dram Type= 6, Freq= 0, CH_1, rank 0

 4537 16:51:55.693941  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4538 16:51:55.696814  ==

 4539 16:51:55.697278  

 4540 16:51:55.697626  

 4541 16:51:55.697948  	TX Vref Scan disable

 4542 16:51:55.700585   == TX Byte 0 ==

 4543 16:51:55.703645  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4544 16:51:55.710277  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4545 16:51:55.710712   == TX Byte 1 ==

 4546 16:51:55.713939  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4547 16:51:55.720700  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4548 16:51:55.721117  

 4549 16:51:55.721463  [DATLAT]

 4550 16:51:55.721792  Freq=600, CH1 RK0

 4551 16:51:55.722087  

 4552 16:51:55.723600  DATLAT Default: 0x9

 4553 16:51:55.724080  0, 0xFFFF, sum = 0

 4554 16:51:55.726995  1, 0xFFFF, sum = 0

 4555 16:51:55.730982  2, 0xFFFF, sum = 0

 4556 16:51:55.731520  3, 0xFFFF, sum = 0

 4557 16:51:55.733769  4, 0xFFFF, sum = 0

 4558 16:51:55.734201  5, 0xFFFF, sum = 0

 4559 16:51:55.736894  6, 0xFFFF, sum = 0

 4560 16:51:55.737330  7, 0xFFFF, sum = 0

 4561 16:51:55.740074  8, 0x0, sum = 1

 4562 16:51:55.740508  9, 0x0, sum = 2

 4563 16:51:55.740948  10, 0x0, sum = 3

 4564 16:51:55.743483  11, 0x0, sum = 4

 4565 16:51:55.743919  best_step = 9

 4566 16:51:55.744382  

 4567 16:51:55.744788  ==

 4568 16:51:55.747067  Dram Type= 6, Freq= 0, CH_1, rank 0

 4569 16:51:55.753403  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4570 16:51:55.753831  ==

 4571 16:51:55.754260  RX Vref Scan: 1

 4572 16:51:55.754663  

 4573 16:51:55.756720  RX Vref 0 -> 0, step: 1

 4574 16:51:55.757149  

 4575 16:51:55.760226  RX Delay -195 -> 252, step: 8

 4576 16:51:55.760649  

 4577 16:51:55.763707  Set Vref, RX VrefLevel [Byte0]: 56

 4578 16:51:55.766738                           [Byte1]: 50

 4579 16:51:55.767199  

 4580 16:51:55.770021  Final RX Vref Byte 0 = 56 to rank0

 4581 16:51:55.773871  Final RX Vref Byte 1 = 50 to rank0

 4582 16:51:55.776628  Final RX Vref Byte 0 = 56 to rank1

 4583 16:51:55.780409  Final RX Vref Byte 1 = 50 to rank1==

 4584 16:51:55.783155  Dram Type= 6, Freq= 0, CH_1, rank 0

 4585 16:51:55.786539  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4586 16:51:55.786978  ==

 4587 16:51:55.790040  DQS Delay:

 4588 16:51:55.790463  DQS0 = 0, DQS1 = 0

 4589 16:51:55.793810  DQM Delay:

 4590 16:51:55.794229  DQM0 = 41, DQM1 = 32

 4591 16:51:55.794563  DQ Delay:

 4592 16:51:55.796533  DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44

 4593 16:51:55.799684  DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36

 4594 16:51:55.803424  DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28

 4595 16:51:55.806514  DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40

 4596 16:51:55.806933  

 4597 16:51:55.807266  

 4598 16:51:55.832217  [DQSOSCAuto] RK0, (LSB)MR18= 0x3d04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps

 4599 16:51:55.833056  CH1 RK0: MR19=808, MR18=3D04

 4600 16:51:55.833417  CH1_RK0: MR19=0x808, MR18=0x3D04, DQSOSC=398, MR23=63, INC=165, DEC=110

 4601 16:51:55.833737  

 4602 16:51:55.834041  ----->DramcWriteLeveling(PI) begin...

 4603 16:51:55.834342  ==

 4604 16:51:55.834631  Dram Type= 6, Freq= 0, CH_1, rank 1

 4605 16:51:55.836611  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4606 16:51:55.837031  ==

 4607 16:51:55.839608  Write leveling (Byte 0): 30 => 30

 4608 16:51:55.842816  Write leveling (Byte 1): 31 => 31

 4609 16:51:55.846435  DramcWriteLeveling(PI) end<-----

 4610 16:51:55.846857  

 4611 16:51:55.847206  ==

 4612 16:51:55.849914  Dram Type= 6, Freq= 0, CH_1, rank 1

 4613 16:51:55.852533  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4614 16:51:55.852928  ==

 4615 16:51:55.856425  [Gating] SW mode calibration

 4616 16:51:55.862738  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4617 16:51:55.869492  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4618 16:51:55.872970   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4619 16:51:55.876655   0  9  4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 4620 16:51:55.883123   0  9  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)

 4621 16:51:55.886023   0  9 12 | B1->B0 | 3232 2d2d | 1 1 | (1 1) (1 0)

 4622 16:51:55.889300   0  9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 4623 16:51:55.896454   0  9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4624 16:51:55.899776   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4625 16:51:55.902907   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4626 16:51:55.909881   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4627 16:51:55.913076   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4628 16:51:55.916707   0 10  8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 4629 16:51:55.922490   0 10 12 | B1->B0 | 2f2f 4343 | 0 0 | (0 0) (0 0)

 4630 16:51:55.926504   0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 4631 16:51:55.929291   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4632 16:51:55.935731   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4633 16:51:55.939237   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4634 16:51:55.942695   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4635 16:51:55.949511   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4636 16:51:55.952682   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4637 16:51:55.956061   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 4638 16:51:55.959044   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4639 16:51:55.965660   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4640 16:51:55.969087   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4641 16:51:55.972620   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4642 16:51:55.979033   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4643 16:51:55.982507   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4644 16:51:55.986087   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4645 16:51:55.992355   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4646 16:51:55.995687   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4647 16:51:55.998785   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4648 16:51:56.005650   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4649 16:51:56.008436   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4650 16:51:56.011621   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4651 16:51:56.018489   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4652 16:51:56.021441   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4653 16:51:56.025051   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4654 16:51:56.031705   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4655 16:51:56.034986  Total UI for P1: 0, mck2ui 16

 4656 16:51:56.038223  best dqsien dly found for B0: ( 0, 13, 10)

 4657 16:51:56.041660  Total UI for P1: 0, mck2ui 16

 4658 16:51:56.044938  best dqsien dly found for B1: ( 0, 13, 14)

 4659 16:51:56.048219  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4660 16:51:56.051398  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4661 16:51:56.051601  

 4662 16:51:56.054857  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4663 16:51:56.058671  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4664 16:51:56.061482  [Gating] SW calibration Done

 4665 16:51:56.061716  ==

 4666 16:51:56.064710  Dram Type= 6, Freq= 0, CH_1, rank 1

 4667 16:51:56.068424  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4668 16:51:56.068846  ==

 4669 16:51:56.071502  RX Vref Scan: 0

 4670 16:51:56.071918  

 4671 16:51:56.075076  RX Vref 0 -> 0, step: 1

 4672 16:51:56.075532  

 4673 16:51:56.075897  RX Delay -230 -> 252, step: 16

 4674 16:51:56.082024  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4675 16:51:56.085010  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4676 16:51:56.088564  iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320

 4677 16:51:56.092391  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4678 16:51:56.098767  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4679 16:51:56.101923  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4680 16:51:56.104764  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4681 16:51:56.108064  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4682 16:51:56.111617  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4683 16:51:56.118520  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4684 16:51:56.121449  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4685 16:51:56.124601  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4686 16:51:56.128333  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4687 16:51:56.135388  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4688 16:51:56.138680  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4689 16:51:56.141594  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4690 16:51:56.142021  ==

 4691 16:51:56.144729  Dram Type= 6, Freq= 0, CH_1, rank 1

 4692 16:51:56.148159  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4693 16:51:56.148672  ==

 4694 16:51:56.151388  DQS Delay:

 4695 16:51:56.151806  DQS0 = 0, DQS1 = 0

 4696 16:51:56.155009  DQM Delay:

 4697 16:51:56.155423  DQM0 = 42, DQM1 = 36

 4698 16:51:56.155757  DQ Delay:

 4699 16:51:56.158234  DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41

 4700 16:51:56.161320  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41

 4701 16:51:56.165001  DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25

 4702 16:51:56.168514  DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41

 4703 16:51:56.168933  

 4704 16:51:56.171334  

 4705 16:51:56.171750  ==

 4706 16:51:56.174735  Dram Type= 6, Freq= 0, CH_1, rank 1

 4707 16:51:56.178460  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4708 16:51:56.178975  ==

 4709 16:51:56.179318  

 4710 16:51:56.179629  

 4711 16:51:56.181574  	TX Vref Scan disable

 4712 16:51:56.181991   == TX Byte 0 ==

 4713 16:51:56.188302  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4714 16:51:56.192085  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4715 16:51:56.192595   == TX Byte 1 ==

 4716 16:51:56.198457  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4717 16:51:56.201661  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4718 16:51:56.202081  ==

 4719 16:51:56.204526  Dram Type= 6, Freq= 0, CH_1, rank 1

 4720 16:51:56.207939  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4721 16:51:56.208489  ==

 4722 16:51:56.208829  

 4723 16:51:56.209138  

 4724 16:51:56.211798  	TX Vref Scan disable

 4725 16:51:56.214500   == TX Byte 0 ==

 4726 16:51:56.217852  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4727 16:51:56.221574  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4728 16:51:56.224934   == TX Byte 1 ==

 4729 16:51:56.228040  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4730 16:51:56.231684  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4731 16:51:56.232246  

 4732 16:51:56.234516  [DATLAT]

 4733 16:51:56.234931  Freq=600, CH1 RK1

 4734 16:51:56.235261  

 4735 16:51:56.237978  DATLAT Default: 0x9

 4736 16:51:56.238492  0, 0xFFFF, sum = 0

 4737 16:51:56.241229  1, 0xFFFF, sum = 0

 4738 16:51:56.241651  2, 0xFFFF, sum = 0

 4739 16:51:56.244681  3, 0xFFFF, sum = 0

 4740 16:51:56.245103  4, 0xFFFF, sum = 0

 4741 16:51:56.247615  5, 0xFFFF, sum = 0

 4742 16:51:56.248067  6, 0xFFFF, sum = 0

 4743 16:51:56.251393  7, 0xFFFF, sum = 0

 4744 16:51:56.251816  8, 0x0, sum = 1

 4745 16:51:56.254242  9, 0x0, sum = 2

 4746 16:51:56.254768  10, 0x0, sum = 3

 4747 16:51:56.257782  11, 0x0, sum = 4

 4748 16:51:56.258203  best_step = 9

 4749 16:51:56.258598  

 4750 16:51:56.258942  ==

 4751 16:51:56.260870  Dram Type= 6, Freq= 0, CH_1, rank 1

 4752 16:51:56.264628  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4753 16:51:56.267456  ==

 4754 16:51:56.267887  RX Vref Scan: 0

 4755 16:51:56.268275  

 4756 16:51:56.271468  RX Vref 0 -> 0, step: 1

 4757 16:51:56.271923  

 4758 16:51:56.274197  RX Delay -179 -> 252, step: 8

 4759 16:51:56.277302  iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304

 4760 16:51:56.280413  iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312

 4761 16:51:56.286901  iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312

 4762 16:51:56.290368  iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304

 4763 16:51:56.293757  iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312

 4764 16:51:56.297441  iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312

 4765 16:51:56.303659  iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304

 4766 16:51:56.307261  iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304

 4767 16:51:56.310164  iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320

 4768 16:51:56.313614  iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312

 4769 16:51:56.317071  iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320

 4770 16:51:56.323697  iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312

 4771 16:51:56.327059  iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312

 4772 16:51:56.330162  iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312

 4773 16:51:56.333815  iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312

 4774 16:51:56.339867  iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312

 4775 16:51:56.339999  ==

 4776 16:51:56.343119  Dram Type= 6, Freq= 0, CH_1, rank 1

 4777 16:51:56.346962  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4778 16:51:56.347045  ==

 4779 16:51:56.347134  DQS Delay:

 4780 16:51:56.349719  DQS0 = 0, DQS1 = 0

 4781 16:51:56.349793  DQM Delay:

 4782 16:51:56.353394  DQM0 = 39, DQM1 = 33

 4783 16:51:56.353503  DQ Delay:

 4784 16:51:56.356893  DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36

 4785 16:51:56.359942  DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36

 4786 16:51:56.363503  DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24

 4787 16:51:56.366786  DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40

 4788 16:51:56.366883  

 4789 16:51:56.366983  

 4790 16:51:56.376376  [DQSOSCAuto] RK1, (LSB)MR18= 0x3a49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps

 4791 16:51:56.376482  CH1 RK1: MR19=808, MR18=3A49

 4792 16:51:56.383177  CH1_RK1: MR19=0x808, MR18=0x3A49, DQSOSC=396, MR23=63, INC=167, DEC=111

 4793 16:51:56.386488  [RxdqsGatingPostProcess] freq 600

 4794 16:51:56.393241  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4795 16:51:56.396560  Pre-setting of DQS Precalculation

 4796 16:51:56.399568  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4797 16:51:56.406327  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4798 16:51:56.416484  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4799 16:51:56.416565  

 4800 16:51:56.416628  

 4801 16:51:56.416686  [Calibration Summary] 1200 Mbps

 4802 16:51:56.419824  CH 0, Rank 0

 4803 16:51:56.419930  SW Impedance     : PASS

 4804 16:51:56.423152  DUTY Scan        : NO K

 4805 16:51:56.426020  ZQ Calibration   : PASS

 4806 16:51:56.426100  Jitter Meter     : NO K

 4807 16:51:56.429560  CBT Training     : PASS

 4808 16:51:56.433325  Write leveling   : PASS

 4809 16:51:56.433405  RX DQS gating    : PASS

 4810 16:51:56.436440  RX DQ/DQS(RDDQC) : PASS

 4811 16:51:56.439801  TX DQ/DQS        : PASS

 4812 16:51:56.439907  RX DATLAT        : PASS

 4813 16:51:56.443012  RX DQ/DQS(Engine): PASS

 4814 16:51:56.446310  TX OE            : NO K

 4815 16:51:56.446391  All Pass.

 4816 16:51:56.446455  

 4817 16:51:56.446513  CH 0, Rank 1

 4818 16:51:56.449714  SW Impedance     : PASS

 4819 16:51:56.452502  DUTY Scan        : NO K

 4820 16:51:56.452582  ZQ Calibration   : PASS

 4821 16:51:56.456085  Jitter Meter     : NO K

 4822 16:51:56.459220  CBT Training     : PASS

 4823 16:51:56.459300  Write leveling   : PASS

 4824 16:51:56.462771  RX DQS gating    : PASS

 4825 16:51:56.465813  RX DQ/DQS(RDDQC) : PASS

 4826 16:51:56.465886  TX DQ/DQS        : PASS

 4827 16:51:56.469359  RX DATLAT        : PASS

 4828 16:51:56.469433  RX DQ/DQS(Engine): PASS

 4829 16:51:56.472330  TX OE            : NO K

 4830 16:51:56.472399  All Pass.

 4831 16:51:56.472458  

 4832 16:51:56.476228  CH 1, Rank 0

 4833 16:51:56.476315  SW Impedance     : PASS

 4834 16:51:56.479518  DUTY Scan        : NO K

 4835 16:51:56.482605  ZQ Calibration   : PASS

 4836 16:51:56.482700  Jitter Meter     : NO K

 4837 16:51:56.486011  CBT Training     : PASS

 4838 16:51:56.489170  Write leveling   : PASS

 4839 16:51:56.489272  RX DQS gating    : PASS

 4840 16:51:56.492370  RX DQ/DQS(RDDQC) : PASS

 4841 16:51:56.495917  TX DQ/DQS        : PASS

 4842 16:51:56.496063  RX DATLAT        : PASS

 4843 16:51:56.499153  RX DQ/DQS(Engine): PASS

 4844 16:51:56.502445  TX OE            : NO K

 4845 16:51:56.502585  All Pass.

 4846 16:51:56.502694  

 4847 16:51:56.502797  CH 1, Rank 1

 4848 16:51:56.506315  SW Impedance     : PASS

 4849 16:51:56.509031  DUTY Scan        : NO K

 4850 16:51:56.509188  ZQ Calibration   : PASS

 4851 16:51:56.512615  Jitter Meter     : NO K

 4852 16:51:56.515914  CBT Training     : PASS

 4853 16:51:56.516137  Write leveling   : PASS

 4854 16:51:56.519444  RX DQS gating    : PASS

 4855 16:51:56.522430  RX DQ/DQS(RDDQC) : PASS

 4856 16:51:56.522684  TX DQ/DQS        : PASS

 4857 16:51:56.526035  RX DATLAT        : PASS

 4858 16:51:56.526367  RX DQ/DQS(Engine): PASS

 4859 16:51:56.529590  TX OE            : NO K

 4860 16:51:56.529913  All Pass.

 4861 16:51:56.530168  

 4862 16:51:56.532626  DramC Write-DBI off

 4863 16:51:56.536198  	PER_BANK_REFRESH: Hybrid Mode

 4864 16:51:56.536719  TX_TRACKING: ON

 4865 16:51:56.545825  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4866 16:51:56.549066  [FAST_K] Save calibration result to emmc

 4867 16:51:56.552886  dramc_set_vcore_voltage set vcore to 662500

 4868 16:51:56.555885  Read voltage for 933, 3

 4869 16:51:56.556333  Vio18 = 0

 4870 16:51:56.559444  Vcore = 662500

 4871 16:51:56.559859  Vdram = 0

 4872 16:51:56.560250  Vddq = 0

 4873 16:51:56.560566  Vmddr = 0

 4874 16:51:56.565939  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4875 16:51:56.572555  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4876 16:51:56.573112  MEM_TYPE=3, freq_sel=17

 4877 16:51:56.575627  sv_algorithm_assistance_LP4_1600 

 4878 16:51:56.578922  ============ PULL DRAM RESETB DOWN ============

 4879 16:51:56.585778  ========== PULL DRAM RESETB DOWN end =========

 4880 16:51:56.589323  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4881 16:51:56.592620  =================================== 

 4882 16:51:56.596096  LPDDR4 DRAM CONFIGURATION

 4883 16:51:56.598887  =================================== 

 4884 16:51:56.599305  EX_ROW_EN[0]    = 0x0

 4885 16:51:56.602299  EX_ROW_EN[1]    = 0x0

 4886 16:51:56.602715  LP4Y_EN      = 0x0

 4887 16:51:56.605897  WORK_FSP     = 0x0

 4888 16:51:56.606313  WL           = 0x3

 4889 16:51:56.608872  RL           = 0x3

 4890 16:51:56.609289  BL           = 0x2

 4891 16:51:56.612437  RPST         = 0x0

 4892 16:51:56.615946  RD_PRE       = 0x0

 4893 16:51:56.616449  WR_PRE       = 0x1

 4894 16:51:56.618802  WR_PST       = 0x0

 4895 16:51:56.619217  DBI_WR       = 0x0

 4896 16:51:56.622246  DBI_RD       = 0x0

 4897 16:51:56.622665  OTF          = 0x1

 4898 16:51:56.625568  =================================== 

 4899 16:51:56.628608  =================================== 

 4900 16:51:56.629027  ANA top config

 4901 16:51:56.632224  =================================== 

 4902 16:51:56.635634  DLL_ASYNC_EN            =  0

 4903 16:51:56.638554  ALL_SLAVE_EN            =  1

 4904 16:51:56.642001  NEW_RANK_MODE           =  1

 4905 16:51:56.645437  DLL_IDLE_MODE           =  1

 4906 16:51:56.645851  LP45_APHY_COMB_EN       =  1

 4907 16:51:56.648806  TX_ODT_DIS              =  1

 4908 16:51:56.652484  NEW_8X_MODE             =  1

 4909 16:51:56.655704  =================================== 

 4910 16:51:56.659219  =================================== 

 4911 16:51:56.662052  data_rate                  = 1866

 4912 16:51:56.665666  CKR                        = 1

 4913 16:51:56.666085  DQ_P2S_RATIO               = 8

 4914 16:51:56.668670  =================================== 

 4915 16:51:56.672000  CA_P2S_RATIO               = 8

 4916 16:51:56.675202  DQ_CA_OPEN                 = 0

 4917 16:51:56.678733  DQ_SEMI_OPEN               = 0

 4918 16:51:56.682274  CA_SEMI_OPEN               = 0

 4919 16:51:56.685490  CA_FULL_RATE               = 0

 4920 16:51:56.685909  DQ_CKDIV4_EN               = 1

 4921 16:51:56.688852  CA_CKDIV4_EN               = 1

 4922 16:51:56.692002  CA_PREDIV_EN               = 0

 4923 16:51:56.695219  PH8_DLY                    = 0

 4924 16:51:56.698512  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4925 16:51:56.702168  DQ_AAMCK_DIV               = 4

 4926 16:51:56.702587  CA_AAMCK_DIV               = 4

 4927 16:51:56.705407  CA_ADMCK_DIV               = 4

 4928 16:51:56.708626  DQ_TRACK_CA_EN             = 0

 4929 16:51:56.712103  CA_PICK                    = 933

 4930 16:51:56.714934  CA_MCKIO                   = 933

 4931 16:51:56.718629  MCKIO_SEMI                 = 0

 4932 16:51:56.721675  PLL_FREQ                   = 3732

 4933 16:51:56.722098  DQ_UI_PI_RATIO             = 32

 4934 16:51:56.725131  CA_UI_PI_RATIO             = 0

 4935 16:51:56.728649  =================================== 

 4936 16:51:56.731771  =================================== 

 4937 16:51:56.734756  memory_type:LPDDR4         

 4938 16:51:56.738277  GP_NUM     : 10       

 4939 16:51:56.738702  SRAM_EN    : 1       

 4940 16:51:56.741805  MD32_EN    : 0       

 4941 16:51:56.744803  =================================== 

 4942 16:51:56.748237  [ANA_INIT] >>>>>>>>>>>>>> 

 4943 16:51:56.748791  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4944 16:51:56.755056  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4945 16:51:56.758494  =================================== 

 4946 16:51:56.758916  data_rate = 1866,PCW = 0X8f00

 4947 16:51:56.761367  =================================== 

 4948 16:51:56.765543  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4949 16:51:56.771540  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4950 16:51:56.778579  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4951 16:51:56.781677  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4952 16:51:56.784774  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4953 16:51:56.788153  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4954 16:51:56.791375  [ANA_INIT] flow start 

 4955 16:51:56.791812  [ANA_INIT] PLL >>>>>>>> 

 4956 16:51:56.794402  [ANA_INIT] PLL <<<<<<<< 

 4957 16:51:56.797749  [ANA_INIT] MIDPI >>>>>>>> 

 4958 16:51:56.801473  [ANA_INIT] MIDPI <<<<<<<< 

 4959 16:51:56.801945  [ANA_INIT] DLL >>>>>>>> 

 4960 16:51:56.804551  [ANA_INIT] flow end 

 4961 16:51:56.808041  ============ LP4 DIFF to SE enter ============

 4962 16:51:56.811814  ============ LP4 DIFF to SE exit  ============

 4963 16:51:56.814383  [ANA_INIT] <<<<<<<<<<<<< 

 4964 16:51:56.818131  [Flow] Enable top DCM control >>>>> 

 4965 16:51:56.821288  [Flow] Enable top DCM control <<<<< 

 4966 16:51:56.825023  Enable DLL master slave shuffle 

 4967 16:51:56.831283  ============================================================== 

 4968 16:51:56.831795  Gating Mode config

 4969 16:51:56.837634  ============================================================== 

 4970 16:51:56.838150  Config description: 

 4971 16:51:56.847836  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4972 16:51:56.854705  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4973 16:51:56.861346  SELPH_MODE            0: By rank         1: By Phase 

 4974 16:51:56.864022  ============================================================== 

 4975 16:51:56.867796  GAT_TRACK_EN                 =  1

 4976 16:51:56.871244  RX_GATING_MODE               =  2

 4977 16:51:56.874628  RX_GATING_TRACK_MODE         =  2

 4978 16:51:56.877852  SELPH_MODE                   =  1

 4979 16:51:56.880886  PICG_EARLY_EN                =  1

 4980 16:51:56.884121  VALID_LAT_VALUE              =  1

 4981 16:51:56.887522  ============================================================== 

 4982 16:51:56.890867  Enter into Gating configuration >>>> 

 4983 16:51:56.894531  Exit from Gating configuration <<<< 

 4984 16:51:56.897576  Enter into  DVFS_PRE_config >>>>> 

 4985 16:51:56.911253  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 4986 16:51:56.914702  Exit from  DVFS_PRE_config <<<<< 

 4987 16:51:56.915180  Enter into PICG configuration >>>> 

 4988 16:51:56.917950  Exit from PICG configuration <<<< 

 4989 16:51:56.920927  [RX_INPUT] configuration >>>>> 

 4990 16:51:56.924162  [RX_INPUT] configuration <<<<< 

 4991 16:51:56.930498  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 4992 16:51:56.933799  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 4993 16:51:56.940632  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 4994 16:51:56.947203  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 4995 16:51:56.953550  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 4996 16:51:56.960579  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 4997 16:51:56.964095  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 4998 16:51:56.966797  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 4999 16:51:56.970210  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5000 16:51:56.977220  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5001 16:51:56.980077  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5002 16:51:56.983460  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5003 16:51:56.986588  =================================== 

 5004 16:51:56.989857  LPDDR4 DRAM CONFIGURATION

 5005 16:51:56.993370  =================================== 

 5006 16:51:56.997058  EX_ROW_EN[0]    = 0x0

 5007 16:51:56.997146  EX_ROW_EN[1]    = 0x0

 5008 16:51:56.999883  LP4Y_EN      = 0x0

 5009 16:51:56.999990  WORK_FSP     = 0x0

 5010 16:51:57.003689  WL           = 0x3

 5011 16:51:57.003778  RL           = 0x3

 5012 16:51:57.006718  BL           = 0x2

 5013 16:51:57.006801  RPST         = 0x0

 5014 16:51:57.009950  RD_PRE       = 0x0

 5015 16:51:57.010032  WR_PRE       = 0x1

 5016 16:51:57.013310  WR_PST       = 0x0

 5017 16:51:57.013394  DBI_WR       = 0x0

 5018 16:51:57.016547  DBI_RD       = 0x0

 5019 16:51:57.016630  OTF          = 0x1

 5020 16:51:57.019730  =================================== 

 5021 16:51:57.026741  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5022 16:51:57.030169  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5023 16:51:57.032968  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5024 16:51:57.036453  =================================== 

 5025 16:51:57.040211  LPDDR4 DRAM CONFIGURATION

 5026 16:51:57.043470  =================================== 

 5027 16:51:57.046775  EX_ROW_EN[0]    = 0x10

 5028 16:51:57.046868  EX_ROW_EN[1]    = 0x0

 5029 16:51:57.050014  LP4Y_EN      = 0x0

 5030 16:51:57.050107  WORK_FSP     = 0x0

 5031 16:51:57.053386  WL           = 0x3

 5032 16:51:57.053496  RL           = 0x3

 5033 16:51:57.056291  BL           = 0x2

 5034 16:51:57.056374  RPST         = 0x0

 5035 16:51:57.059761  RD_PRE       = 0x0

 5036 16:51:57.059872  WR_PRE       = 0x1

 5037 16:51:57.063101  WR_PST       = 0x0

 5038 16:51:57.063204  DBI_WR       = 0x0

 5039 16:51:57.066581  DBI_RD       = 0x0

 5040 16:51:57.066671  OTF          = 0x1

 5041 16:51:57.069939  =================================== 

 5042 16:51:57.076235  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5043 16:51:57.080716  nWR fixed to 30

 5044 16:51:57.084204  [ModeRegInit_LP4] CH0 RK0

 5045 16:51:57.084296  [ModeRegInit_LP4] CH0 RK1

 5046 16:51:57.087910  [ModeRegInit_LP4] CH1 RK0

 5047 16:51:57.091353  [ModeRegInit_LP4] CH1 RK1

 5048 16:51:57.091441  match AC timing 9

 5049 16:51:57.097775  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5050 16:51:57.101117  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5051 16:51:57.104423  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5052 16:51:57.111232  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5053 16:51:57.113926  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5054 16:51:57.114009  ==

 5055 16:51:57.117468  Dram Type= 6, Freq= 0, CH_0, rank 0

 5056 16:51:57.120931  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5057 16:51:57.121013  ==

 5058 16:51:57.127533  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5059 16:51:57.134175  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5060 16:51:57.137353  [CA 0] Center 38 (8~69) winsize 62

 5061 16:51:57.140914  [CA 1] Center 38 (7~69) winsize 63

 5062 16:51:57.144414  [CA 2] Center 35 (5~66) winsize 62

 5063 16:51:57.147220  [CA 3] Center 34 (4~65) winsize 62

 5064 16:51:57.150432  [CA 4] Center 34 (4~64) winsize 61

 5065 16:51:57.153763  [CA 5] Center 34 (4~64) winsize 61

 5066 16:51:57.153931  

 5067 16:51:57.157272  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5068 16:51:57.157389  

 5069 16:51:57.160661  [CATrainingPosCal] consider 1 rank data

 5070 16:51:57.164030  u2DelayCellTimex100 = 270/100 ps

 5071 16:51:57.166964  CA0 delay=38 (8~69),Diff = 4 PI (24 cell)

 5072 16:51:57.170475  CA1 delay=38 (7~69),Diff = 4 PI (24 cell)

 5073 16:51:57.173886  CA2 delay=35 (5~66),Diff = 1 PI (6 cell)

 5074 16:51:57.177250  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 5075 16:51:57.180765  CA4 delay=34 (4~64),Diff = 0 PI (0 cell)

 5076 16:51:57.184123  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5077 16:51:57.184234  

 5078 16:51:57.190545  CA PerBit enable=1, Macro0, CA PI delay=34

 5079 16:51:57.190718  

 5080 16:51:57.194423  [CBTSetCACLKResult] CA Dly = 34

 5081 16:51:57.194638  CS Dly: 6 (0~37)

 5082 16:51:57.194757  ==

 5083 16:51:57.197194  Dram Type= 6, Freq= 0, CH_0, rank 1

 5084 16:51:57.200464  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5085 16:51:57.200675  ==

 5086 16:51:57.207032  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5087 16:51:57.213484  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5088 16:51:57.217227  [CA 0] Center 38 (8~69) winsize 62

 5089 16:51:57.220413  [CA 1] Center 38 (7~69) winsize 63

 5090 16:51:57.223544  [CA 2] Center 35 (5~66) winsize 62

 5091 16:51:57.226894  [CA 3] Center 35 (5~65) winsize 61

 5092 16:51:57.230627  [CA 4] Center 33 (3~64) winsize 62

 5093 16:51:57.233860  [CA 5] Center 33 (3~64) winsize 62

 5094 16:51:57.234296  

 5095 16:51:57.236746  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5096 16:51:57.237203  

 5097 16:51:57.240304  [CATrainingPosCal] consider 2 rank data

 5098 16:51:57.243588  u2DelayCellTimex100 = 270/100 ps

 5099 16:51:57.247208  CA0 delay=38 (8~69),Diff = 4 PI (24 cell)

 5100 16:51:57.250593  CA1 delay=38 (7~69),Diff = 4 PI (24 cell)

 5101 16:51:57.253555  CA2 delay=35 (5~66),Diff = 1 PI (6 cell)

 5102 16:51:57.257432  CA3 delay=35 (5~65),Diff = 1 PI (6 cell)

 5103 16:51:57.260465  CA4 delay=34 (4~64),Diff = 0 PI (0 cell)

 5104 16:51:57.267095  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5105 16:51:57.267590  

 5106 16:51:57.270157  CA PerBit enable=1, Macro0, CA PI delay=34

 5107 16:51:57.270721  

 5108 16:51:57.273435  [CBTSetCACLKResult] CA Dly = 34

 5109 16:51:57.274013  CS Dly: 7 (0~39)

 5110 16:51:57.274524  

 5111 16:51:57.277087  ----->DramcWriteLeveling(PI) begin...

 5112 16:51:57.277510  ==

 5113 16:51:57.280309  Dram Type= 6, Freq= 0, CH_0, rank 0

 5114 16:51:57.286537  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5115 16:51:57.286620  ==

 5116 16:51:57.290246  Write leveling (Byte 0): 32 => 32

 5117 16:51:57.290329  Write leveling (Byte 1): 29 => 29

 5118 16:51:57.293374  DramcWriteLeveling(PI) end<-----

 5119 16:51:57.293455  

 5120 16:51:57.293519  ==

 5121 16:51:57.296562  Dram Type= 6, Freq= 0, CH_0, rank 0

 5122 16:51:57.303506  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5123 16:51:57.303588  ==

 5124 16:51:57.306541  [Gating] SW mode calibration

 5125 16:51:57.313296  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5126 16:51:57.316776  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5127 16:51:57.323049   0 14  0 | B1->B0 | 2424 2e2e | 1 0 | (1 1) (0 0)

 5128 16:51:57.326461   0 14  4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)

 5129 16:51:57.329506   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5130 16:51:57.335884   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5131 16:51:57.339611   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5132 16:51:57.342873   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5133 16:51:57.349272   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5134 16:51:57.352805   0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)

 5135 16:51:57.356144   0 15  0 | B1->B0 | 2f2f 2a2a | 0 0 | (0 1) (0 1)

 5136 16:51:57.362970   0 15  4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)

 5137 16:51:57.365838   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5138 16:51:57.369296   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5139 16:51:57.376258   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5140 16:51:57.379239   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5141 16:51:57.382765   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5142 16:51:57.389195   0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)

 5143 16:51:57.392505   1  0  0 | B1->B0 | 2c2c 3c3c | 0 0 | (0 0) (0 0)

 5144 16:51:57.395736   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5145 16:51:57.402699   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5146 16:51:57.405948   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5147 16:51:57.408899   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5148 16:51:57.412507   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5149 16:51:57.419143   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5150 16:51:57.422502   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5151 16:51:57.425841   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5152 16:51:57.432467   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5153 16:51:57.435523   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5154 16:51:57.439262   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5155 16:51:57.445952   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5156 16:51:57.448973   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5157 16:51:57.452264   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5158 16:51:57.459148   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5159 16:51:57.462036   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5160 16:51:57.465334   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5161 16:51:57.472683   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5162 16:51:57.475765   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5163 16:51:57.479293   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5164 16:51:57.485519   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5165 16:51:57.488990   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5166 16:51:57.491819   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5167 16:51:57.498763   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5168 16:51:57.502714   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5169 16:51:57.505875   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5170 16:51:57.508539  Total UI for P1: 0, mck2ui 16

 5171 16:51:57.511925  best dqsien dly found for B0: ( 1,  3,  0)

 5172 16:51:57.515533  Total UI for P1: 0, mck2ui 16

 5173 16:51:57.518789  best dqsien dly found for B1: ( 1,  3,  0)

 5174 16:51:57.521968  best DQS0 dly(MCK, UI, PI) = (1, 3, 0)

 5175 16:51:57.525161  best DQS1 dly(MCK, UI, PI) = (1, 3, 0)

 5176 16:51:57.525618  

 5177 16:51:57.531948  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5178 16:51:57.535286  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5179 16:51:57.535742  [Gating] SW calibration Done

 5180 16:51:57.538420  ==

 5181 16:51:57.541646  Dram Type= 6, Freq= 0, CH_0, rank 0

 5182 16:51:57.545194  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5183 16:51:57.545612  ==

 5184 16:51:57.545938  RX Vref Scan: 0

 5185 16:51:57.546248  

 5186 16:51:57.548523  RX Vref 0 -> 0, step: 1

 5187 16:51:57.548935  

 5188 16:51:57.551679  RX Delay -80 -> 252, step: 8

 5189 16:51:57.555149  iDelay=200, Bit 0, Center 95 (0 ~ 191) 192

 5190 16:51:57.558058  iDelay=200, Bit 1, Center 99 (0 ~ 199) 200

 5191 16:51:57.561243  iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200

 5192 16:51:57.568447  iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200

 5193 16:51:57.572130  iDelay=200, Bit 4, Center 99 (0 ~ 199) 200

 5194 16:51:57.574814  iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192

 5195 16:51:57.578125  iDelay=200, Bit 6, Center 103 (8 ~ 199) 192

 5196 16:51:57.581656  iDelay=200, Bit 7, Center 103 (8 ~ 199) 192

 5197 16:51:57.584607  iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184

 5198 16:51:57.591744  iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184

 5199 16:51:57.594562  iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192

 5200 16:51:57.597975  iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192

 5201 16:51:57.601282  iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200

 5202 16:51:57.604640  iDelay=200, Bit 13, Center 95 (0 ~ 191) 192

 5203 16:51:57.611530  iDelay=200, Bit 14, Center 95 (0 ~ 191) 192

 5204 16:51:57.614578  iDelay=200, Bit 15, Center 95 (0 ~ 191) 192

 5205 16:51:57.615001  ==

 5206 16:51:57.617877  Dram Type= 6, Freq= 0, CH_0, rank 0

 5207 16:51:57.621405  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5208 16:51:57.621827  ==

 5209 16:51:57.622178  DQS Delay:

 5210 16:51:57.624975  DQS0 = 0, DQS1 = 0

 5211 16:51:57.625395  DQM Delay:

 5212 16:51:57.627846  DQM0 = 96, DQM1 = 86

 5213 16:51:57.628288  DQ Delay:

 5214 16:51:57.631467  DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91

 5215 16:51:57.634779  DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103

 5216 16:51:57.638084  DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79

 5217 16:51:57.641829  DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95

 5218 16:51:57.642252  

 5219 16:51:57.642587  

 5220 16:51:57.642901  ==

 5221 16:51:57.644096  Dram Type= 6, Freq= 0, CH_0, rank 0

 5222 16:51:57.650928  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5223 16:51:57.651375  ==

 5224 16:51:57.651731  

 5225 16:51:57.652115  

 5226 16:51:57.652423  	TX Vref Scan disable

 5227 16:51:57.654691   == TX Byte 0 ==

 5228 16:51:57.657916  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5229 16:51:57.664060  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5230 16:51:57.664551   == TX Byte 1 ==

 5231 16:51:57.667660  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5232 16:51:57.674726  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5233 16:51:57.675140  ==

 5234 16:51:57.677621  Dram Type= 6, Freq= 0, CH_0, rank 0

 5235 16:51:57.681125  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5236 16:51:57.681540  ==

 5237 16:51:57.681866  

 5238 16:51:57.682169  

 5239 16:51:57.684645  	TX Vref Scan disable

 5240 16:51:57.685073   == TX Byte 0 ==

 5241 16:51:57.691011  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5242 16:51:57.694034  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5243 16:51:57.694451   == TX Byte 1 ==

 5244 16:51:57.700685  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5245 16:51:57.704204  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5246 16:51:57.704632  

 5247 16:51:57.704966  [DATLAT]

 5248 16:51:57.707239  Freq=933, CH0 RK0

 5249 16:51:57.707654  

 5250 16:51:57.708012  DATLAT Default: 0xd

 5251 16:51:57.710312  0, 0xFFFF, sum = 0

 5252 16:51:57.713658  1, 0xFFFF, sum = 0

 5253 16:51:57.714271  2, 0xFFFF, sum = 0

 5254 16:51:57.717372  3, 0xFFFF, sum = 0

 5255 16:51:57.717792  4, 0xFFFF, sum = 0

 5256 16:51:57.721152  5, 0xFFFF, sum = 0

 5257 16:51:57.721720  6, 0xFFFF, sum = 0

 5258 16:51:57.723669  7, 0xFFFF, sum = 0

 5259 16:51:57.724129  8, 0xFFFF, sum = 0

 5260 16:51:57.727050  9, 0xFFFF, sum = 0

 5261 16:51:57.727470  10, 0x0, sum = 1

 5262 16:51:57.730502  11, 0x0, sum = 2

 5263 16:51:57.730923  12, 0x0, sum = 3

 5264 16:51:57.733831  13, 0x0, sum = 4

 5265 16:51:57.734355  best_step = 11

 5266 16:51:57.734685  

 5267 16:51:57.734993  ==

 5268 16:51:57.736961  Dram Type= 6, Freq= 0, CH_0, rank 0

 5269 16:51:57.740681  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5270 16:51:57.743546  ==

 5271 16:51:57.744117  RX Vref Scan: 1

 5272 16:51:57.744469  

 5273 16:51:57.747078  RX Vref 0 -> 0, step: 1

 5274 16:51:57.747589  

 5275 16:51:57.747925  RX Delay -61 -> 252, step: 4

 5276 16:51:57.750756  

 5277 16:51:57.751276  Set Vref, RX VrefLevel [Byte0]: 56

 5278 16:51:57.753488                           [Byte1]: 52

 5279 16:51:57.758322  

 5280 16:51:57.758735  Final RX Vref Byte 0 = 56 to rank0

 5281 16:51:57.761677  Final RX Vref Byte 1 = 52 to rank0

 5282 16:51:57.765337  Final RX Vref Byte 0 = 56 to rank1

 5283 16:51:57.768644  Final RX Vref Byte 1 = 52 to rank1==

 5284 16:51:57.771656  Dram Type= 6, Freq= 0, CH_0, rank 0

 5285 16:51:57.778520  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5286 16:51:57.779052  ==

 5287 16:51:57.779392  DQS Delay:

 5288 16:51:57.779699  DQS0 = 0, DQS1 = 0

 5289 16:51:57.781416  DQM Delay:

 5290 16:51:57.781827  DQM0 = 96, DQM1 = 87

 5291 16:51:57.784917  DQ Delay:

 5292 16:51:57.788184  DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92

 5293 16:51:57.791690  DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =102

 5294 16:51:57.795092  DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80

 5295 16:51:57.797869  DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96

 5296 16:51:57.798272  

 5297 16:51:57.798588  

 5298 16:51:57.804919  [DQSOSCAuto] RK0, (LSB)MR18= 0xffa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 417 ps

 5299 16:51:57.807719  CH0 RK0: MR19=504, MR18=FFA

 5300 16:51:57.814970  CH0_RK0: MR19=0x504, MR18=0xFFA, DQSOSC=417, MR23=63, INC=62, DEC=41

 5301 16:51:57.815476  

 5302 16:51:57.818038  ----->DramcWriteLeveling(PI) begin...

 5303 16:51:57.818447  ==

 5304 16:51:57.821114  Dram Type= 6, Freq= 0, CH_0, rank 1

 5305 16:51:57.824625  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5306 16:51:57.825033  ==

 5307 16:51:57.828227  Write leveling (Byte 0): 28 => 28

 5308 16:51:57.831462  Write leveling (Byte 1): 28 => 28

 5309 16:51:57.834807  DramcWriteLeveling(PI) end<-----

 5310 16:51:57.835211  

 5311 16:51:57.835528  ==

 5312 16:51:57.837717  Dram Type= 6, Freq= 0, CH_0, rank 1

 5313 16:51:57.841631  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5314 16:51:57.842140  ==

 5315 16:51:57.844310  [Gating] SW mode calibration

 5316 16:51:57.851487  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5317 16:51:57.857904  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5318 16:51:57.861132   0 14  0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)

 5319 16:51:57.867568   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5320 16:51:57.870642   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5321 16:51:57.874810   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5322 16:51:57.881139   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5323 16:51:57.884378   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5324 16:51:57.887465   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 5325 16:51:57.894250   0 14 28 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 1)

 5326 16:51:57.897701   0 15  0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)

 5327 16:51:57.901363   0 15  4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 5328 16:51:57.904106   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5329 16:51:57.911139   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5330 16:51:57.914076   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5331 16:51:57.917218   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5332 16:51:57.924114   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5333 16:51:57.927274   0 15 28 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)

 5334 16:51:57.931261   1  0  0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)

 5335 16:51:57.937494   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5336 16:51:57.941333   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5337 16:51:57.944673   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5338 16:51:57.950868   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5339 16:51:57.954454   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5340 16:51:57.957401   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5341 16:51:57.963943   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5342 16:51:57.967514   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5343 16:51:57.970709   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5344 16:51:57.977087   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5345 16:51:57.980225   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5346 16:51:57.984072   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5347 16:51:57.990137   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5348 16:51:57.993498   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5349 16:51:57.996747   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5350 16:51:58.003617   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5351 16:51:58.006836   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5352 16:51:58.009910   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5353 16:51:58.017059   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5354 16:51:58.020479   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5355 16:51:58.023755   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5356 16:51:58.030368   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5357 16:51:58.033849   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5358 16:51:58.036605   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5359 16:51:58.040128  Total UI for P1: 0, mck2ui 16

 5360 16:51:58.043708  best dqsien dly found for B0: ( 1,  2, 28)

 5361 16:51:58.047106   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5362 16:51:58.053725   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5363 16:51:58.057207  Total UI for P1: 0, mck2ui 16

 5364 16:51:58.059827  best dqsien dly found for B1: ( 1,  3,  2)

 5365 16:51:58.063792  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5366 16:51:58.067263  best DQS1 dly(MCK, UI, PI) = (1, 3, 2)

 5367 16:51:58.067830  

 5368 16:51:58.070059  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5369 16:51:58.073270  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)

 5370 16:51:58.076411  [Gating] SW calibration Done

 5371 16:51:58.076875  ==

 5372 16:51:58.080125  Dram Type= 6, Freq= 0, CH_0, rank 1

 5373 16:51:58.083200  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5374 16:51:58.083770  ==

 5375 16:51:58.086296  RX Vref Scan: 0

 5376 16:51:58.086775  

 5377 16:51:58.089605  RX Vref 0 -> 0, step: 1

 5378 16:51:58.090257  

 5379 16:51:58.090640  RX Delay -80 -> 252, step: 8

 5380 16:51:58.096200  iDelay=208, Bit 0, Center 99 (0 ~ 199) 200

 5381 16:51:58.099780  iDelay=208, Bit 1, Center 99 (0 ~ 199) 200

 5382 16:51:58.103038  iDelay=208, Bit 2, Center 95 (0 ~ 191) 192

 5383 16:51:58.106098  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5384 16:51:58.109491  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5385 16:51:58.113020  iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192

 5386 16:51:58.119482  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5387 16:51:58.122860  iDelay=208, Bit 7, Center 107 (8 ~ 207) 200

 5388 16:51:58.126320  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5389 16:51:58.129273  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5390 16:51:58.132783  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5391 16:51:58.139672  iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192

 5392 16:51:58.143022  iDelay=208, Bit 12, Center 91 (0 ~ 183) 184

 5393 16:51:58.146117  iDelay=208, Bit 13, Center 91 (0 ~ 183) 184

 5394 16:51:58.149883  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5395 16:51:58.152684  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5396 16:51:58.153282  ==

 5397 16:51:58.156021  Dram Type= 6, Freq= 0, CH_0, rank 1

 5398 16:51:58.162898  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5399 16:51:58.163439  ==

 5400 16:51:58.163814  DQS Delay:

 5401 16:51:58.164236  DQS0 = 0, DQS1 = 0

 5402 16:51:58.165828  DQM Delay:

 5403 16:51:58.166608  DQM0 = 97, DQM1 = 87

 5404 16:51:58.169087  DQ Delay:

 5405 16:51:58.172738  DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91

 5406 16:51:58.176559  DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107

 5407 16:51:58.179423  DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79

 5408 16:51:58.182818  DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95

 5409 16:51:58.183373  

 5410 16:51:58.183739  

 5411 16:51:58.184136  ==

 5412 16:51:58.185677  Dram Type= 6, Freq= 0, CH_0, rank 1

 5413 16:51:58.189218  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5414 16:51:58.189690  ==

 5415 16:51:58.190082  

 5416 16:51:58.190674  

 5417 16:51:58.192294  	TX Vref Scan disable

 5418 16:51:58.192760   == TX Byte 0 ==

 5419 16:51:58.199432  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5420 16:51:58.202289  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5421 16:51:58.202757   == TX Byte 1 ==

 5422 16:51:58.209308  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5423 16:51:58.212799  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5424 16:51:58.213261  ==

 5425 16:51:58.216043  Dram Type= 6, Freq= 0, CH_0, rank 1

 5426 16:51:58.219221  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5427 16:51:58.219787  ==

 5428 16:51:58.220211  

 5429 16:51:58.220560  

 5430 16:51:58.222671  	TX Vref Scan disable

 5431 16:51:58.226068   == TX Byte 0 ==

 5432 16:51:58.229277  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5433 16:51:58.232368  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5434 16:51:58.235646   == TX Byte 1 ==

 5435 16:51:58.239001  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5436 16:51:58.242759  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5437 16:51:58.243277  

 5438 16:51:58.245794  [DATLAT]

 5439 16:51:58.246210  Freq=933, CH0 RK1

 5440 16:51:58.246568  

 5441 16:51:58.249567  DATLAT Default: 0xb

 5442 16:51:58.250081  0, 0xFFFF, sum = 0

 5443 16:51:58.252549  1, 0xFFFF, sum = 0

 5444 16:51:58.252975  2, 0xFFFF, sum = 0

 5445 16:51:58.256539  3, 0xFFFF, sum = 0

 5446 16:51:58.256964  4, 0xFFFF, sum = 0

 5447 16:51:58.259177  5, 0xFFFF, sum = 0

 5448 16:51:58.259601  6, 0xFFFF, sum = 0

 5449 16:51:58.262549  7, 0xFFFF, sum = 0

 5450 16:51:58.262973  8, 0xFFFF, sum = 0

 5451 16:51:58.266233  9, 0xFFFF, sum = 0

 5452 16:51:58.266752  10, 0x0, sum = 1

 5453 16:51:58.269139  11, 0x0, sum = 2

 5454 16:51:58.269670  12, 0x0, sum = 3

 5455 16:51:58.272709  13, 0x0, sum = 4

 5456 16:51:58.273279  best_step = 11

 5457 16:51:58.273621  

 5458 16:51:58.273931  ==

 5459 16:51:58.275915  Dram Type= 6, Freq= 0, CH_0, rank 1

 5460 16:51:58.282496  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5461 16:51:58.283018  ==

 5462 16:51:58.283357  RX Vref Scan: 0

 5463 16:51:58.283673  

 5464 16:51:58.286030  RX Vref 0 -> 0, step: 1

 5465 16:51:58.286546  

 5466 16:51:58.288951  RX Delay -61 -> 252, step: 4

 5467 16:51:58.292407  iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192

 5468 16:51:58.295855  iDelay=199, Bit 1, Center 96 (-1 ~ 194) 196

 5469 16:51:58.302340  iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188

 5470 16:51:58.305896  iDelay=199, Bit 3, Center 92 (-5 ~ 190) 196

 5471 16:51:58.308767  iDelay=199, Bit 4, Center 94 (3 ~ 186) 184

 5472 16:51:58.311872  iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188

 5473 16:51:58.315469  iDelay=199, Bit 6, Center 104 (11 ~ 198) 188

 5474 16:51:58.322365  iDelay=199, Bit 7, Center 104 (11 ~ 198) 188

 5475 16:51:58.325289  iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180

 5476 16:51:58.328511  iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176

 5477 16:51:58.331824  iDelay=199, Bit 10, Center 90 (3 ~ 178) 176

 5478 16:51:58.335048  iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176

 5479 16:51:58.338848  iDelay=199, Bit 12, Center 92 (3 ~ 182) 180

 5480 16:51:58.345350  iDelay=199, Bit 13, Center 92 (3 ~ 182) 180

 5481 16:51:58.348353  iDelay=199, Bit 14, Center 96 (7 ~ 186) 180

 5482 16:51:58.351700  iDelay=199, Bit 15, Center 96 (7 ~ 186) 180

 5483 16:51:58.351830  ==

 5484 16:51:58.355129  Dram Type= 6, Freq= 0, CH_0, rank 1

 5485 16:51:58.357965  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5486 16:51:58.358080  ==

 5487 16:51:58.361360  DQS Delay:

 5488 16:51:58.361461  DQS0 = 0, DQS1 = 0

 5489 16:51:58.361542  DQM Delay:

 5490 16:51:58.365207  DQM0 = 95, DQM1 = 87

 5491 16:51:58.365308  DQ Delay:

 5492 16:51:58.368077  DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92

 5493 16:51:58.371430  DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =104

 5494 16:51:58.375302  DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =78

 5495 16:51:58.378222  DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =96

 5496 16:51:58.378305  

 5497 16:51:58.378369  

 5498 16:51:58.388113  [DQSOSCAuto] RK1, (LSB)MR18= 0x1907, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps

 5499 16:51:58.391501  CH0 RK1: MR19=505, MR18=1907

 5500 16:51:58.394530  CH0_RK1: MR19=0x505, MR18=0x1907, DQSOSC=413, MR23=63, INC=63, DEC=42

 5501 16:51:58.398081  [RxdqsGatingPostProcess] freq 933

 5502 16:51:58.404805  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5503 16:51:58.408560  best DQS0 dly(2T, 0.5T) = (0, 11)

 5504 16:51:58.411634  best DQS1 dly(2T, 0.5T) = (0, 11)

 5505 16:51:58.414590  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 5506 16:51:58.418188  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5507 16:51:58.421484  best DQS0 dly(2T, 0.5T) = (0, 10)

 5508 16:51:58.424716  best DQS1 dly(2T, 0.5T) = (0, 11)

 5509 16:51:58.427906  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5510 16:51:58.431110  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5511 16:51:58.431195  Pre-setting of DQS Precalculation

 5512 16:51:58.437691  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5513 16:51:58.437781  ==

 5514 16:51:58.441354  Dram Type= 6, Freq= 0, CH_1, rank 0

 5515 16:51:58.444643  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5516 16:51:58.444793  ==

 5517 16:51:58.451501  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5518 16:51:58.457685  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5519 16:51:58.461020  [CA 0] Center 36 (6~67) winsize 62

 5520 16:51:58.464322  [CA 1] Center 36 (6~67) winsize 62

 5521 16:51:58.467768  [CA 2] Center 34 (4~64) winsize 61

 5522 16:51:58.470722  [CA 3] Center 33 (3~64) winsize 62

 5523 16:51:58.474505  [CA 4] Center 33 (3~64) winsize 62

 5524 16:51:58.478035  [CA 5] Center 33 (3~64) winsize 62

 5525 16:51:58.478130  

 5526 16:51:58.480986  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5527 16:51:58.481069  

 5528 16:51:58.484281  [CATrainingPosCal] consider 1 rank data

 5529 16:51:58.487551  u2DelayCellTimex100 = 270/100 ps

 5530 16:51:58.491026  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5531 16:51:58.494474  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5532 16:51:58.497848  CA2 delay=34 (4~64),Diff = 1 PI (6 cell)

 5533 16:51:58.500866  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5534 16:51:58.504404  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 5535 16:51:58.507381  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5536 16:51:58.511413  

 5537 16:51:58.514027  CA PerBit enable=1, Macro0, CA PI delay=33

 5538 16:51:58.514112  

 5539 16:51:58.517614  [CBTSetCACLKResult] CA Dly = 33

 5540 16:51:58.517699  CS Dly: 4 (0~35)

 5541 16:51:58.517765  ==

 5542 16:51:58.520826  Dram Type= 6, Freq= 0, CH_1, rank 1

 5543 16:51:58.524269  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5544 16:51:58.524356  ==

 5545 16:51:58.530583  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5546 16:51:58.537771  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5547 16:51:58.540641  [CA 0] Center 36 (6~67) winsize 62

 5548 16:51:58.544250  [CA 1] Center 36 (6~67) winsize 62

 5549 16:51:58.547138  [CA 2] Center 33 (3~64) winsize 62

 5550 16:51:58.550401  [CA 3] Center 33 (3~64) winsize 62

 5551 16:51:58.553824  [CA 4] Center 33 (3~64) winsize 62

 5552 16:51:58.557321  [CA 5] Center 33 (3~63) winsize 61

 5553 16:51:58.557408  

 5554 16:51:58.560653  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5555 16:51:58.560737  

 5556 16:51:58.564621  [CATrainingPosCal] consider 2 rank data

 5557 16:51:58.567468  u2DelayCellTimex100 = 270/100 ps

 5558 16:51:58.570374  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5559 16:51:58.573901  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5560 16:51:58.577178  CA2 delay=34 (4~64),Diff = 1 PI (6 cell)

 5561 16:51:58.580575  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5562 16:51:58.584383  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 5563 16:51:58.590698  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 5564 16:51:58.590789  

 5565 16:51:58.594170  CA PerBit enable=1, Macro0, CA PI delay=33

 5566 16:51:58.594257  

 5567 16:51:58.597576  [CBTSetCACLKResult] CA Dly = 33

 5568 16:51:58.597661  CS Dly: 5 (0~38)

 5569 16:51:58.597726  

 5570 16:51:58.600507  ----->DramcWriteLeveling(PI) begin...

 5571 16:51:58.600591  ==

 5572 16:51:58.603908  Dram Type= 6, Freq= 0, CH_1, rank 0

 5573 16:51:58.607292  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5574 16:51:58.610647  ==

 5575 16:51:58.613882  Write leveling (Byte 0): 24 => 24

 5576 16:51:58.613967  Write leveling (Byte 1): 29 => 29

 5577 16:51:58.617030  DramcWriteLeveling(PI) end<-----

 5578 16:51:58.617112  

 5579 16:51:58.617176  ==

 5580 16:51:58.620387  Dram Type= 6, Freq= 0, CH_1, rank 0

 5581 16:51:58.627004  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5582 16:51:58.627134  ==

 5583 16:51:58.630193  [Gating] SW mode calibration

 5584 16:51:58.636976  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5585 16:51:58.640603  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5586 16:51:58.647140   0 14  0 | B1->B0 | 2f2f 3333 | 1 1 | (1 1) (0 0)

 5587 16:51:58.650169   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5588 16:51:58.653579   0 14  8 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)

 5589 16:51:58.660371   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5590 16:51:58.663818   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5591 16:51:58.666764   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5592 16:51:58.673530   0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)

 5593 16:51:58.676522   0 14 28 | B1->B0 | 3131 3131 | 1 1 | (1 0) (1 0)

 5594 16:51:58.679772   0 15  0 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)

 5595 16:51:58.686469   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5596 16:51:58.689849   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5597 16:51:58.693260   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5598 16:51:58.700297   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5599 16:51:58.703698   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5600 16:51:58.706577   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5601 16:51:58.709877   0 15 28 | B1->B0 | 3131 2a2a | 0 0 | (0 0) (1 1)

 5602 16:51:58.716785   1  0  0 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)

 5603 16:51:58.719982   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5604 16:51:58.723043   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5605 16:51:58.729828   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5606 16:51:58.733432   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5607 16:51:58.736695   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5608 16:51:58.743357   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5609 16:51:58.746623   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5610 16:51:58.749790   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5611 16:51:58.756140   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5612 16:51:58.759754   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5613 16:51:58.763204   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5614 16:51:58.769539   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5615 16:51:58.772872   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5616 16:51:58.776371   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5617 16:51:58.782860   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5618 16:51:58.786514   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5619 16:51:58.789604   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5620 16:51:58.795877   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5621 16:51:58.799241   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5622 16:51:58.802662   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5623 16:51:58.809584   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5624 16:51:58.812377   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5625 16:51:58.816162   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5626 16:51:58.822359   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5627 16:51:58.822451  Total UI for P1: 0, mck2ui 16

 5628 16:51:58.828999  best dqsien dly found for B0: ( 1,  2, 28)

 5629 16:51:58.829097  Total UI for P1: 0, mck2ui 16

 5630 16:51:58.835546  best dqsien dly found for B1: ( 1,  2, 28)

 5631 16:51:58.839424  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5632 16:51:58.842113  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5633 16:51:58.842262  

 5634 16:51:58.845298  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5635 16:51:58.848709  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5636 16:51:58.851907  [Gating] SW calibration Done

 5637 16:51:58.852085  ==

 5638 16:51:58.855551  Dram Type= 6, Freq= 0, CH_1, rank 0

 5639 16:51:58.858571  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5640 16:51:58.858714  ==

 5641 16:51:58.861789  RX Vref Scan: 0

 5642 16:51:58.861927  

 5643 16:51:58.862048  RX Vref 0 -> 0, step: 1

 5644 16:51:58.862166  

 5645 16:51:58.865271  RX Delay -80 -> 252, step: 8

 5646 16:51:58.871885  iDelay=208, Bit 0, Center 99 (8 ~ 191) 184

 5647 16:51:58.874975  iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200

 5648 16:51:58.878501  iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184

 5649 16:51:58.881598  iDelay=208, Bit 3, Center 95 (0 ~ 191) 192

 5650 16:51:58.885114  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5651 16:51:58.888231  iDelay=208, Bit 5, Center 107 (8 ~ 207) 200

 5652 16:51:58.894732  iDelay=208, Bit 6, Center 107 (16 ~ 199) 184

 5653 16:51:58.898467  iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200

 5654 16:51:58.901980  iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200

 5655 16:51:58.904739  iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200

 5656 16:51:58.908230  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5657 16:51:58.911712  iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200

 5658 16:51:58.918365  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5659 16:51:58.921657  iDelay=208, Bit 13, Center 95 (0 ~ 191) 192

 5660 16:51:58.924949  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5661 16:51:58.927933  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5662 16:51:58.928135  ==

 5663 16:51:58.931165  Dram Type= 6, Freq= 0, CH_1, rank 0

 5664 16:51:58.934870  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5665 16:51:58.938394  ==

 5666 16:51:58.938534  DQS Delay:

 5667 16:51:58.938661  DQS0 = 0, DQS1 = 0

 5668 16:51:58.941820  DQM Delay:

 5669 16:51:58.941962  DQM0 = 96, DQM1 = 87

 5670 16:51:58.944954  DQ Delay:

 5671 16:51:58.947926  DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95

 5672 16:51:58.951301  DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91

 5673 16:51:58.951393  DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83

 5674 16:51:58.957925  DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95

 5675 16:51:58.958017  

 5676 16:51:58.958082  

 5677 16:51:58.958143  ==

 5678 16:51:58.961315  Dram Type= 6, Freq= 0, CH_1, rank 0

 5679 16:51:58.964671  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5680 16:51:58.964758  ==

 5681 16:51:58.964831  

 5682 16:51:58.964892  

 5683 16:51:58.967975  	TX Vref Scan disable

 5684 16:51:58.968092   == TX Byte 0 ==

 5685 16:51:58.974543  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5686 16:51:58.978017  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5687 16:51:58.978117   == TX Byte 1 ==

 5688 16:51:58.984571  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5689 16:51:58.987856  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5690 16:51:58.987995  ==

 5691 16:51:58.991471  Dram Type= 6, Freq= 0, CH_1, rank 0

 5692 16:51:58.994284  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5693 16:51:58.994418  ==

 5694 16:51:58.994489  

 5695 16:51:58.994550  

 5696 16:51:58.997977  	TX Vref Scan disable

 5697 16:51:59.001250   == TX Byte 0 ==

 5698 16:51:59.004856  Update DQ  dly =707 (2 ,5, 35)  DQ  OEN =(2 ,2)

 5699 16:51:59.007702  Update DQM dly =707 (2 ,5, 35)  DQM OEN =(2 ,2)

 5700 16:51:59.011122   == TX Byte 1 ==

 5701 16:51:59.014525  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5702 16:51:59.017902  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5703 16:51:59.020794  

 5704 16:51:59.020877  [DATLAT]

 5705 16:51:59.020942  Freq=933, CH1 RK0

 5706 16:51:59.021003  

 5707 16:51:59.024125  DATLAT Default: 0xd

 5708 16:51:59.024208  0, 0xFFFF, sum = 0

 5709 16:51:59.027395  1, 0xFFFF, sum = 0

 5710 16:51:59.027480  2, 0xFFFF, sum = 0

 5711 16:51:59.030883  3, 0xFFFF, sum = 0

 5712 16:51:59.030968  4, 0xFFFF, sum = 0

 5713 16:51:59.034488  5, 0xFFFF, sum = 0

 5714 16:51:59.034572  6, 0xFFFF, sum = 0

 5715 16:51:59.037390  7, 0xFFFF, sum = 0

 5716 16:51:59.040737  8, 0xFFFF, sum = 0

 5717 16:51:59.040822  9, 0xFFFF, sum = 0

 5718 16:51:59.044068  10, 0x0, sum = 1

 5719 16:51:59.044152  11, 0x0, sum = 2

 5720 16:51:59.044217  12, 0x0, sum = 3

 5721 16:51:59.047362  13, 0x0, sum = 4

 5722 16:51:59.047446  best_step = 11

 5723 16:51:59.047511  

 5724 16:51:59.051246  ==

 5725 16:51:59.051334  Dram Type= 6, Freq= 0, CH_1, rank 0

 5726 16:51:59.057379  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5727 16:51:59.057466  ==

 5728 16:51:59.057532  RX Vref Scan: 1

 5729 16:51:59.057592  

 5730 16:51:59.060712  RX Vref 0 -> 0, step: 1

 5731 16:51:59.060795  

 5732 16:51:59.064290  RX Delay -69 -> 252, step: 4

 5733 16:51:59.064374  

 5734 16:51:59.067809  Set Vref, RX VrefLevel [Byte0]: 56

 5735 16:51:59.071285                           [Byte1]: 50

 5736 16:51:59.071367  

 5737 16:51:59.074122  Final RX Vref Byte 0 = 56 to rank0

 5738 16:51:59.077546  Final RX Vref Byte 1 = 50 to rank0

 5739 16:51:59.080516  Final RX Vref Byte 0 = 56 to rank1

 5740 16:51:59.084051  Final RX Vref Byte 1 = 50 to rank1==

 5741 16:51:59.087370  Dram Type= 6, Freq= 0, CH_1, rank 0

 5742 16:51:59.090522  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5743 16:51:59.090606  ==

 5744 16:51:59.093972  DQS Delay:

 5745 16:51:59.094059  DQS0 = 0, DQS1 = 0

 5746 16:51:59.097127  DQM Delay:

 5747 16:51:59.097210  DQM0 = 97, DQM1 = 90

 5748 16:51:59.097276  DQ Delay:

 5749 16:51:59.100825  DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96

 5750 16:51:59.103773  DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =94

 5751 16:51:59.107352  DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =86

 5752 16:51:59.110840  DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =92

 5753 16:51:59.110923  

 5754 16:51:59.114163  

 5755 16:51:59.120442  [DQSOSCAuto] RK0, (LSB)MR18= 0x14f1, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps

 5756 16:51:59.123860  CH1 RK0: MR19=504, MR18=14F1

 5757 16:51:59.130551  CH1_RK0: MR19=0x504, MR18=0x14F1, DQSOSC=415, MR23=63, INC=62, DEC=41

 5758 16:51:59.130643  

 5759 16:51:59.133792  ----->DramcWriteLeveling(PI) begin...

 5760 16:51:59.133877  ==

 5761 16:51:59.137334  Dram Type= 6, Freq= 0, CH_1, rank 1

 5762 16:51:59.140969  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5763 16:51:59.141054  ==

 5764 16:51:59.143579  Write leveling (Byte 0): 25 => 25

 5765 16:51:59.146879  Write leveling (Byte 1): 32 => 32

 5766 16:51:59.150343  DramcWriteLeveling(PI) end<-----

 5767 16:51:59.150427  

 5768 16:51:59.150491  ==

 5769 16:51:59.153521  Dram Type= 6, Freq= 0, CH_1, rank 1

 5770 16:51:59.157135  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5771 16:51:59.157219  ==

 5772 16:51:59.160727  [Gating] SW mode calibration

 5773 16:51:59.166872  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5774 16:51:59.173706  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5775 16:51:59.177083   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5776 16:51:59.180081   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5777 16:51:59.186951   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5778 16:51:59.191138   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5779 16:51:59.193845   0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 5780 16:51:59.200499   0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 5781 16:51:59.204019   0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (1 1)

 5782 16:51:59.207293   0 14 28 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)

 5783 16:51:59.213438   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 5784 16:51:59.216698   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5785 16:51:59.220155   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5786 16:51:59.226817   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5787 16:51:59.229846   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5788 16:51:59.233277   0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 5789 16:51:59.239844   0 15 24 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)

 5790 16:51:59.243303   0 15 28 | B1->B0 | 3a3a 4444 | 0 1 | (0 0) (0 0)

 5791 16:51:59.246833   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5792 16:51:59.253427   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5793 16:51:59.256451   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5794 16:51:59.259802   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5795 16:51:59.266672   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5796 16:51:59.270096   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5797 16:51:59.273391   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5798 16:51:59.279647   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5799 16:51:59.283000   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5800 16:51:59.286381   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5801 16:51:59.293569   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5802 16:51:59.296264   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5803 16:51:59.299745   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5804 16:51:59.306021   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5805 16:51:59.309731   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5806 16:51:59.313341   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5807 16:51:59.316625   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5808 16:51:59.322884   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5809 16:51:59.326186   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5810 16:51:59.329804   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5811 16:51:59.336121   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5812 16:51:59.339477   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5813 16:51:59.343012   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5814 16:51:59.346455  Total UI for P1: 0, mck2ui 16

 5815 16:51:59.349408  best dqsien dly found for B0: ( 1,  2, 22)

 5816 16:51:59.352839  Total UI for P1: 0, mck2ui 16

 5817 16:51:59.356207  best dqsien dly found for B1: ( 1,  2, 22)

 5818 16:51:59.359530  best DQS0 dly(MCK, UI, PI) = (1, 2, 22)

 5819 16:51:59.362992  best DQS1 dly(MCK, UI, PI) = (1, 2, 22)

 5820 16:51:59.363070  

 5821 16:51:59.369570  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)

 5822 16:51:59.372452  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)

 5823 16:51:59.375888  [Gating] SW calibration Done

 5824 16:51:59.375978  ==

 5825 16:51:59.379152  Dram Type= 6, Freq= 0, CH_1, rank 1

 5826 16:51:59.383052  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5827 16:51:59.383136  ==

 5828 16:51:59.383200  RX Vref Scan: 0

 5829 16:51:59.383258  

 5830 16:51:59.386111  RX Vref 0 -> 0, step: 1

 5831 16:51:59.386193  

 5832 16:51:59.389483  RX Delay -80 -> 252, step: 8

 5833 16:51:59.393116  iDelay=200, Bit 0, Center 95 (0 ~ 191) 192

 5834 16:51:59.396502  iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200

 5835 16:51:59.402710  iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200

 5836 16:51:59.405755  iDelay=200, Bit 3, Center 95 (0 ~ 191) 192

 5837 16:51:59.408966  iDelay=200, Bit 4, Center 95 (0 ~ 191) 192

 5838 16:51:59.412256  iDelay=200, Bit 5, Center 103 (8 ~ 199) 192

 5839 16:51:59.415562  iDelay=200, Bit 6, Center 103 (8 ~ 199) 192

 5840 16:51:59.419481  iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192

 5841 16:51:59.426100  iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192

 5842 16:51:59.429044  iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192

 5843 16:51:59.432144  iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192

 5844 16:51:59.435572  iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192

 5845 16:51:59.438923  iDelay=200, Bit 12, Center 95 (0 ~ 191) 192

 5846 16:51:59.442415  iDelay=200, Bit 13, Center 95 (0 ~ 191) 192

 5847 16:51:59.448780  iDelay=200, Bit 14, Center 95 (0 ~ 191) 192

 5848 16:51:59.452223  iDelay=200, Bit 15, Center 95 (0 ~ 191) 192

 5849 16:51:59.452308  ==

 5850 16:51:59.455653  Dram Type= 6, Freq= 0, CH_1, rank 1

 5851 16:51:59.459572  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5852 16:51:59.459680  ==

 5853 16:51:59.462484  DQS Delay:

 5854 16:51:59.462565  DQS0 = 0, DQS1 = 0

 5855 16:51:59.462631  DQM Delay:

 5856 16:51:59.465504  DQM0 = 94, DQM1 = 88

 5857 16:51:59.465585  DQ Delay:

 5858 16:51:59.468856  DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =95

 5859 16:51:59.471900  DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87

 5860 16:51:59.475411  DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79

 5861 16:51:59.478688  DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95

 5862 16:51:59.478774  

 5863 16:51:59.478838  

 5864 16:51:59.478896  ==

 5865 16:51:59.482150  Dram Type= 6, Freq= 0, CH_1, rank 1

 5866 16:51:59.488488  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5867 16:51:59.488578  ==

 5868 16:51:59.488643  

 5869 16:51:59.488702  

 5870 16:51:59.488758  	TX Vref Scan disable

 5871 16:51:59.492462   == TX Byte 0 ==

 5872 16:51:59.495357  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5873 16:51:59.502139  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5874 16:51:59.502231   == TX Byte 1 ==

 5875 16:51:59.505307  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5876 16:51:59.511819  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5877 16:51:59.511934  ==

 5878 16:51:59.515598  Dram Type= 6, Freq= 0, CH_1, rank 1

 5879 16:51:59.518846  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5880 16:51:59.518933  ==

 5881 16:51:59.519017  

 5882 16:51:59.519097  

 5883 16:51:59.522138  	TX Vref Scan disable

 5884 16:51:59.522222   == TX Byte 0 ==

 5885 16:51:59.528530  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5886 16:51:59.531814  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5887 16:51:59.531897   == TX Byte 1 ==

 5888 16:51:59.538953  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5889 16:51:59.542071  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5890 16:51:59.542157  

 5891 16:51:59.542222  [DATLAT]

 5892 16:51:59.545013  Freq=933, CH1 RK1

 5893 16:51:59.545097  

 5894 16:51:59.545161  DATLAT Default: 0xb

 5895 16:51:59.548354  0, 0xFFFF, sum = 0

 5896 16:51:59.548496  1, 0xFFFF, sum = 0

 5897 16:51:59.551551  2, 0xFFFF, sum = 0

 5898 16:51:59.555008  3, 0xFFFF, sum = 0

 5899 16:51:59.555091  4, 0xFFFF, sum = 0

 5900 16:51:59.558177  5, 0xFFFF, sum = 0

 5901 16:51:59.558260  6, 0xFFFF, sum = 0

 5902 16:51:59.562165  7, 0xFFFF, sum = 0

 5903 16:51:59.562249  8, 0xFFFF, sum = 0

 5904 16:51:59.564985  9, 0xFFFF, sum = 0

 5905 16:51:59.565069  10, 0x0, sum = 1

 5906 16:51:59.568430  11, 0x0, sum = 2

 5907 16:51:59.568512  12, 0x0, sum = 3

 5908 16:51:59.571906  13, 0x0, sum = 4

 5909 16:51:59.572036  best_step = 11

 5910 16:51:59.572102  

 5911 16:51:59.572160  ==

 5912 16:51:59.575054  Dram Type= 6, Freq= 0, CH_1, rank 1

 5913 16:51:59.578131  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5914 16:51:59.578212  ==

 5915 16:51:59.581460  RX Vref Scan: 0

 5916 16:51:59.581556  

 5917 16:51:59.584990  RX Vref 0 -> 0, step: 1

 5918 16:51:59.585071  

 5919 16:51:59.585135  RX Delay -61 -> 252, step: 4

 5920 16:51:59.592892  iDelay=199, Bit 0, Center 98 (7 ~ 190) 184

 5921 16:51:59.595778  iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184

 5922 16:51:59.599867  iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184

 5923 16:51:59.602704  iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188

 5924 16:51:59.606047  iDelay=199, Bit 4, Center 96 (3 ~ 190) 188

 5925 16:51:59.612431  iDelay=199, Bit 5, Center 106 (15 ~ 198) 184

 5926 16:51:59.615874  iDelay=199, Bit 6, Center 104 (15 ~ 194) 180

 5927 16:51:59.619310  iDelay=199, Bit 7, Center 92 (3 ~ 182) 180

 5928 16:51:59.622766  iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180

 5929 16:51:59.625819  iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180

 5930 16:51:59.628826  iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184

 5931 16:51:59.635918  iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184

 5932 16:51:59.639248  iDelay=199, Bit 12, Center 98 (11 ~ 186) 176

 5933 16:51:59.642241  iDelay=199, Bit 13, Center 100 (11 ~ 190) 180

 5934 16:51:59.645747  iDelay=199, Bit 14, Center 100 (11 ~ 190) 180

 5935 16:51:59.648937  iDelay=199, Bit 15, Center 100 (11 ~ 190) 180

 5936 16:51:59.652215  ==

 5937 16:51:59.655624  Dram Type= 6, Freq= 0, CH_1, rank 1

 5938 16:51:59.659013  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5939 16:51:59.659095  ==

 5940 16:51:59.659159  DQS Delay:

 5941 16:51:59.662971  DQS0 = 0, DQS1 = 0

 5942 16:51:59.663051  DQM Delay:

 5943 16:51:59.665633  DQM0 = 95, DQM1 = 91

 5944 16:51:59.665714  DQ Delay:

 5945 16:51:59.669000  DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92

 5946 16:51:59.672393  DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92

 5947 16:51:59.675200  DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =82

 5948 16:51:59.679407  DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100

 5949 16:51:59.679488  

 5950 16:51:59.679551  

 5951 16:51:59.685528  [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps

 5952 16:51:59.689022  CH1 RK1: MR19=505, MR18=E17

 5953 16:51:59.695895  CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42

 5954 16:51:59.698736  [RxdqsGatingPostProcess] freq 933

 5955 16:51:59.705335  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5956 16:51:59.705418  best DQS0 dly(2T, 0.5T) = (0, 10)

 5957 16:51:59.708808  best DQS1 dly(2T, 0.5T) = (0, 10)

 5958 16:51:59.712229  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5959 16:51:59.715199  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5960 16:51:59.718753  best DQS0 dly(2T, 0.5T) = (0, 10)

 5961 16:51:59.722460  best DQS1 dly(2T, 0.5T) = (0, 10)

 5962 16:51:59.725231  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5963 16:51:59.728429  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5964 16:51:59.732019  Pre-setting of DQS Precalculation

 5965 16:51:59.738816  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5966 16:51:59.744968  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5967 16:51:59.751911  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5968 16:51:59.752034  

 5969 16:51:59.752099  

 5970 16:51:59.755263  [Calibration Summary] 1866 Mbps

 5971 16:51:59.755344  CH 0, Rank 0

 5972 16:51:59.758288  SW Impedance     : PASS

 5973 16:51:59.761609  DUTY Scan        : NO K

 5974 16:51:59.761689  ZQ Calibration   : PASS

 5975 16:51:59.764861  Jitter Meter     : NO K

 5976 16:51:59.764941  CBT Training     : PASS

 5977 16:51:59.768777  Write leveling   : PASS

 5978 16:51:59.771575  RX DQS gating    : PASS

 5979 16:51:59.771655  RX DQ/DQS(RDDQC) : PASS

 5980 16:51:59.774924  TX DQ/DQS        : PASS

 5981 16:51:59.778081  RX DATLAT        : PASS

 5982 16:51:59.778161  RX DQ/DQS(Engine): PASS

 5983 16:51:59.781875  TX OE            : NO K

 5984 16:51:59.781956  All Pass.

 5985 16:51:59.782020  

 5986 16:51:59.784977  CH 0, Rank 1

 5987 16:51:59.785057  SW Impedance     : PASS

 5988 16:51:59.788278  DUTY Scan        : NO K

 5989 16:51:59.791711  ZQ Calibration   : PASS

 5990 16:51:59.791791  Jitter Meter     : NO K

 5991 16:51:59.794977  CBT Training     : PASS

 5992 16:51:59.797944  Write leveling   : PASS

 5993 16:51:59.798025  RX DQS gating    : PASS

 5994 16:51:59.801745  RX DQ/DQS(RDDQC) : PASS

 5995 16:51:59.805091  TX DQ/DQS        : PASS

 5996 16:51:59.805172  RX DATLAT        : PASS

 5997 16:51:59.807910  RX DQ/DQS(Engine): PASS

 5998 16:51:59.811511  TX OE            : NO K

 5999 16:51:59.811592  All Pass.

 6000 16:51:59.811655  

 6001 16:51:59.811714  CH 1, Rank 0

 6002 16:51:59.814886  SW Impedance     : PASS

 6003 16:51:59.818259  DUTY Scan        : NO K

 6004 16:51:59.818339  ZQ Calibration   : PASS

 6005 16:51:59.821101  Jitter Meter     : NO K

 6006 16:51:59.824511  CBT Training     : PASS

 6007 16:51:59.824591  Write leveling   : PASS

 6008 16:51:59.828096  RX DQS gating    : PASS

 6009 16:51:59.828177  RX DQ/DQS(RDDQC) : PASS

 6010 16:51:59.831163  TX DQ/DQS        : PASS

 6011 16:51:59.834665  RX DATLAT        : PASS

 6012 16:51:59.834746  RX DQ/DQS(Engine): PASS

 6013 16:51:59.837732  TX OE            : NO K

 6014 16:51:59.837813  All Pass.

 6015 16:51:59.837876  

 6016 16:51:59.841298  CH 1, Rank 1

 6017 16:51:59.841378  SW Impedance     : PASS

 6018 16:51:59.844713  DUTY Scan        : NO K

 6019 16:51:59.847895  ZQ Calibration   : PASS

 6020 16:51:59.848062  Jitter Meter     : NO K

 6021 16:51:59.851182  CBT Training     : PASS

 6022 16:51:59.854314  Write leveling   : PASS

 6023 16:51:59.854395  RX DQS gating    : PASS

 6024 16:51:59.858038  RX DQ/DQS(RDDQC) : PASS

 6025 16:51:59.860981  TX DQ/DQS        : PASS

 6026 16:51:59.861061  RX DATLAT        : PASS

 6027 16:51:59.864545  RX DQ/DQS(Engine): PASS

 6028 16:51:59.867855  TX OE            : NO K

 6029 16:51:59.867966  All Pass.

 6030 16:51:59.868033  

 6031 16:51:59.868092  DramC Write-DBI off

 6032 16:51:59.871145  	PER_BANK_REFRESH: Hybrid Mode

 6033 16:51:59.874586  TX_TRACKING: ON

 6034 16:51:59.881102  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6035 16:51:59.884269  [FAST_K] Save calibration result to emmc

 6036 16:51:59.891134  dramc_set_vcore_voltage set vcore to 650000

 6037 16:51:59.891215  Read voltage for 400, 6

 6038 16:51:59.894457  Vio18 = 0

 6039 16:51:59.894537  Vcore = 650000

 6040 16:51:59.894601  Vdram = 0

 6041 16:51:59.897906  Vddq = 0

 6042 16:51:59.897985  Vmddr = 0

 6043 16:51:59.901246  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6044 16:51:59.907256  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6045 16:51:59.910701  MEM_TYPE=3, freq_sel=20

 6046 16:51:59.910782  sv_algorithm_assistance_LP4_800 

 6047 16:51:59.917681  ============ PULL DRAM RESETB DOWN ============

 6048 16:51:59.920482  ========== PULL DRAM RESETB DOWN end =========

 6049 16:51:59.924343  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6050 16:51:59.927162  =================================== 

 6051 16:51:59.930471  LPDDR4 DRAM CONFIGURATION

 6052 16:51:59.934192  =================================== 

 6053 16:51:59.937127  EX_ROW_EN[0]    = 0x0

 6054 16:51:59.937207  EX_ROW_EN[1]    = 0x0

 6055 16:51:59.940860  LP4Y_EN      = 0x0

 6056 16:51:59.940940  WORK_FSP     = 0x0

 6057 16:51:59.943837  WL           = 0x2

 6058 16:51:59.943917  RL           = 0x2

 6059 16:51:59.947305  BL           = 0x2

 6060 16:51:59.947386  RPST         = 0x0

 6061 16:51:59.950686  RD_PRE       = 0x0

 6062 16:51:59.950766  WR_PRE       = 0x1

 6063 16:51:59.954052  WR_PST       = 0x0

 6064 16:51:59.954133  DBI_WR       = 0x0

 6065 16:51:59.957406  DBI_RD       = 0x0

 6066 16:51:59.957486  OTF          = 0x1

 6067 16:51:59.960850  =================================== 

 6068 16:51:59.964103  =================================== 

 6069 16:51:59.967005  ANA top config

 6070 16:51:59.971067  =================================== 

 6071 16:51:59.973938  DLL_ASYNC_EN            =  0

 6072 16:51:59.974018  ALL_SLAVE_EN            =  1

 6073 16:51:59.977270  NEW_RANK_MODE           =  1

 6074 16:51:59.980604  DLL_IDLE_MODE           =  1

 6075 16:51:59.984128  LP45_APHY_COMB_EN       =  1

 6076 16:51:59.987431  TX_ODT_DIS              =  1

 6077 16:51:59.987512  NEW_8X_MODE             =  1

 6078 16:51:59.990785  =================================== 

 6079 16:51:59.993872  =================================== 

 6080 16:51:59.996911  data_rate                  =  800

 6081 16:52:00.000226  CKR                        = 1

 6082 16:52:00.003639  DQ_P2S_RATIO               = 4

 6083 16:52:00.007477  =================================== 

 6084 16:52:00.010436  CA_P2S_RATIO               = 4

 6085 16:52:00.014000  DQ_CA_OPEN                 = 0

 6086 16:52:00.014080  DQ_SEMI_OPEN               = 1

 6087 16:52:00.016840  CA_SEMI_OPEN               = 1

 6088 16:52:00.020317  CA_FULL_RATE               = 0

 6089 16:52:00.023838  DQ_CKDIV4_EN               = 0

 6090 16:52:00.027160  CA_CKDIV4_EN               = 1

 6091 16:52:00.030348  CA_PREDIV_EN               = 0

 6092 16:52:00.030429  PH8_DLY                    = 0

 6093 16:52:00.033415  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6094 16:52:00.036805  DQ_AAMCK_DIV               = 0

 6095 16:52:00.040229  CA_AAMCK_DIV               = 0

 6096 16:52:00.043793  CA_ADMCK_DIV               = 4

 6097 16:52:00.046612  DQ_TRACK_CA_EN             = 0

 6098 16:52:00.046693  CA_PICK                    = 800

 6099 16:52:00.049936  CA_MCKIO                   = 400

 6100 16:52:00.054037  MCKIO_SEMI                 = 400

 6101 16:52:00.057057  PLL_FREQ                   = 3016

 6102 16:52:00.059900  DQ_UI_PI_RATIO             = 32

 6103 16:52:00.063774  CA_UI_PI_RATIO             = 32

 6104 16:52:00.066711  =================================== 

 6105 16:52:00.069906  =================================== 

 6106 16:52:00.073311  memory_type:LPDDR4         

 6107 16:52:00.073420  GP_NUM     : 10       

 6108 16:52:00.077027  SRAM_EN    : 1       

 6109 16:52:00.077108  MD32_EN    : 0       

 6110 16:52:00.080340  =================================== 

 6111 16:52:00.083259  [ANA_INIT] >>>>>>>>>>>>>> 

 6112 16:52:00.086419  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6113 16:52:00.089923  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6114 16:52:00.093013  =================================== 

 6115 16:52:00.096701  data_rate = 800,PCW = 0X7400

 6116 16:52:00.099920  =================================== 

 6117 16:52:00.103463  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6118 16:52:00.106293  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6119 16:52:00.120007  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6120 16:52:00.123261  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6121 16:52:00.126658  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6122 16:52:00.130162  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6123 16:52:00.132948  [ANA_INIT] flow start 

 6124 16:52:00.136328  [ANA_INIT] PLL >>>>>>>> 

 6125 16:52:00.136415  [ANA_INIT] PLL <<<<<<<< 

 6126 16:52:00.139369  [ANA_INIT] MIDPI >>>>>>>> 

 6127 16:52:00.143159  [ANA_INIT] MIDPI <<<<<<<< 

 6128 16:52:00.143243  [ANA_INIT] DLL >>>>>>>> 

 6129 16:52:00.146758  [ANA_INIT] flow end 

 6130 16:52:00.150019  ============ LP4 DIFF to SE enter ============

 6131 16:52:00.152668  ============ LP4 DIFF to SE exit  ============

 6132 16:52:00.156199  [ANA_INIT] <<<<<<<<<<<<< 

 6133 16:52:00.159220  [Flow] Enable top DCM control >>>>> 

 6134 16:52:00.162964  [Flow] Enable top DCM control <<<<< 

 6135 16:52:00.166060  Enable DLL master slave shuffle 

 6136 16:52:00.172512  ============================================================== 

 6137 16:52:00.172608  Gating Mode config

 6138 16:52:00.179517  ============================================================== 

 6139 16:52:00.182692  Config description: 

 6140 16:52:00.189298  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6141 16:52:00.195911  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6142 16:52:00.202385  SELPH_MODE            0: By rank         1: By Phase 

 6143 16:52:00.209280  ============================================================== 

 6144 16:52:00.209372  GAT_TRACK_EN                 =  0

 6145 16:52:00.212467  RX_GATING_MODE               =  2

 6146 16:52:00.215942  RX_GATING_TRACK_MODE         =  2

 6147 16:52:00.219509  SELPH_MODE                   =  1

 6148 16:52:00.222759  PICG_EARLY_EN                =  1

 6149 16:52:00.226102  VALID_LAT_VALUE              =  1

 6150 16:52:00.232764  ============================================================== 

 6151 16:52:00.235678  Enter into Gating configuration >>>> 

 6152 16:52:00.239053  Exit from Gating configuration <<<< 

 6153 16:52:00.242501  Enter into  DVFS_PRE_config >>>>> 

 6154 16:52:00.252615  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6155 16:52:00.255888  Exit from  DVFS_PRE_config <<<<< 

 6156 16:52:00.259100  Enter into PICG configuration >>>> 

 6157 16:52:00.262430  Exit from PICG configuration <<<< 

 6158 16:52:00.265862  [RX_INPUT] configuration >>>>> 

 6159 16:52:00.265947  [RX_INPUT] configuration <<<<< 

 6160 16:52:00.272311  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6161 16:52:00.279233  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6162 16:52:00.282850  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6163 16:52:00.289372  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6164 16:52:00.295785  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6165 16:52:00.301964  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6166 16:52:00.305722  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6167 16:52:00.309221  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6168 16:52:00.315350  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6169 16:52:00.318628  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6170 16:52:00.322126  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6171 16:52:00.328918  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6172 16:52:00.332320  =================================== 

 6173 16:52:00.332407  LPDDR4 DRAM CONFIGURATION

 6174 16:52:00.335623  =================================== 

 6175 16:52:00.339292  EX_ROW_EN[0]    = 0x0

 6176 16:52:00.339377  EX_ROW_EN[1]    = 0x0

 6177 16:52:00.342297  LP4Y_EN      = 0x0

 6178 16:52:00.342381  WORK_FSP     = 0x0

 6179 16:52:00.345662  WL           = 0x2

 6180 16:52:00.348938  RL           = 0x2

 6181 16:52:00.349022  BL           = 0x2

 6182 16:52:00.352353  RPST         = 0x0

 6183 16:52:00.352438  RD_PRE       = 0x0

 6184 16:52:00.355846  WR_PRE       = 0x1

 6185 16:52:00.355930  WR_PST       = 0x0

 6186 16:52:00.358619  DBI_WR       = 0x0

 6187 16:52:00.358703  DBI_RD       = 0x0

 6188 16:52:00.362074  OTF          = 0x1

 6189 16:52:00.365720  =================================== 

 6190 16:52:00.368903  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6191 16:52:00.372016  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6192 16:52:00.375393  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6193 16:52:00.378587  =================================== 

 6194 16:52:00.382088  LPDDR4 DRAM CONFIGURATION

 6195 16:52:00.385579  =================================== 

 6196 16:52:00.388312  EX_ROW_EN[0]    = 0x10

 6197 16:52:00.388399  EX_ROW_EN[1]    = 0x0

 6198 16:52:00.391613  LP4Y_EN      = 0x0

 6199 16:52:00.391719  WORK_FSP     = 0x0

 6200 16:52:00.395468  WL           = 0x2

 6201 16:52:00.395547  RL           = 0x2

 6202 16:52:00.398496  BL           = 0x2

 6203 16:52:00.401977  RPST         = 0x0

 6204 16:52:00.402060  RD_PRE       = 0x0

 6205 16:52:00.405281  WR_PRE       = 0x1

 6206 16:52:00.405395  WR_PST       = 0x0

 6207 16:52:00.408585  DBI_WR       = 0x0

 6208 16:52:00.408669  DBI_RD       = 0x0

 6209 16:52:00.411578  OTF          = 0x1

 6210 16:52:00.415586  =================================== 

 6211 16:52:00.418210  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6212 16:52:00.423856  nWR fixed to 30

 6213 16:52:00.426901  [ModeRegInit_LP4] CH0 RK0

 6214 16:52:00.426985  [ModeRegInit_LP4] CH0 RK1

 6215 16:52:00.430177  [ModeRegInit_LP4] CH1 RK0

 6216 16:52:00.433620  [ModeRegInit_LP4] CH1 RK1

 6217 16:52:00.433733  match AC timing 19

 6218 16:52:00.440290  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6219 16:52:00.443778  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6220 16:52:00.446837  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6221 16:52:00.453839  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6222 16:52:00.456837  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6223 16:52:00.456920  ==

 6224 16:52:00.460297  Dram Type= 6, Freq= 0, CH_0, rank 0

 6225 16:52:00.463697  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6226 16:52:00.463781  ==

 6227 16:52:00.470278  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6228 16:52:00.476859  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6229 16:52:00.480447  [CA 0] Center 36 (8~64) winsize 57

 6230 16:52:00.483396  [CA 1] Center 36 (8~64) winsize 57

 6231 16:52:00.486508  [CA 2] Center 36 (8~64) winsize 57

 6232 16:52:00.490081  [CA 3] Center 36 (8~64) winsize 57

 6233 16:52:00.490166  [CA 4] Center 36 (8~64) winsize 57

 6234 16:52:00.493781  [CA 5] Center 36 (8~64) winsize 57

 6235 16:52:00.493873  

 6236 16:52:00.499906  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6237 16:52:00.500017  

 6238 16:52:00.503453  [CATrainingPosCal] consider 1 rank data

 6239 16:52:00.506678  u2DelayCellTimex100 = 270/100 ps

 6240 16:52:00.509833  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6241 16:52:00.513253  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6242 16:52:00.516692  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6243 16:52:00.520281  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6244 16:52:00.523652  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6245 16:52:00.526574  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6246 16:52:00.526660  

 6247 16:52:00.530041  CA PerBit enable=1, Macro0, CA PI delay=36

 6248 16:52:00.530126  

 6249 16:52:00.533459  [CBTSetCACLKResult] CA Dly = 36

 6250 16:52:00.536822  CS Dly: 1 (0~32)

 6251 16:52:00.536908  ==

 6252 16:52:00.540078  Dram Type= 6, Freq= 0, CH_0, rank 1

 6253 16:52:00.543294  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6254 16:52:00.543379  ==

 6255 16:52:00.550109  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6256 16:52:00.553000  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6257 16:52:00.556830  [CA 0] Center 36 (8~64) winsize 57

 6258 16:52:00.559701  [CA 1] Center 36 (8~64) winsize 57

 6259 16:52:00.563153  [CA 2] Center 36 (8~64) winsize 57

 6260 16:52:00.566617  [CA 3] Center 36 (8~64) winsize 57

 6261 16:52:00.569645  [CA 4] Center 36 (8~64) winsize 57

 6262 16:52:00.573193  [CA 5] Center 36 (8~64) winsize 57

 6263 16:52:00.573276  

 6264 16:52:00.576829  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6265 16:52:00.576913  

 6266 16:52:00.579778  [CATrainingPosCal] consider 2 rank data

 6267 16:52:00.583281  u2DelayCellTimex100 = 270/100 ps

 6268 16:52:00.586833  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6269 16:52:00.589870  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6270 16:52:00.596435  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6271 16:52:00.600326  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6272 16:52:00.603140  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6273 16:52:00.606422  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6274 16:52:00.606506  

 6275 16:52:00.609435  CA PerBit enable=1, Macro0, CA PI delay=36

 6276 16:52:00.609518  

 6277 16:52:00.612904  [CBTSetCACLKResult] CA Dly = 36

 6278 16:52:00.612987  CS Dly: 1 (0~32)

 6279 16:52:00.613100  

 6280 16:52:00.616230  ----->DramcWriteLeveling(PI) begin...

 6281 16:52:00.619436  ==

 6282 16:52:00.622849  Dram Type= 6, Freq= 0, CH_0, rank 0

 6283 16:52:00.625989  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6284 16:52:00.626098  ==

 6285 16:52:00.629276  Write leveling (Byte 0): 40 => 8

 6286 16:52:00.632731  Write leveling (Byte 1): 32 => 0

 6287 16:52:00.636143  DramcWriteLeveling(PI) end<-----

 6288 16:52:00.636224  

 6289 16:52:00.636287  ==

 6290 16:52:00.639660  Dram Type= 6, Freq= 0, CH_0, rank 0

 6291 16:52:00.642983  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6292 16:52:00.643065  ==

 6293 16:52:00.645822  [Gating] SW mode calibration

 6294 16:52:00.652790  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6295 16:52:00.656214  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6296 16:52:00.662930   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6297 16:52:00.666369   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6298 16:52:00.669419   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6299 16:52:00.675891   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6300 16:52:00.679141   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6301 16:52:00.682322   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6302 16:52:00.689021   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6303 16:52:00.692466   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6304 16:52:00.696188   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6305 16:52:00.699224  Total UI for P1: 0, mck2ui 16

 6306 16:52:00.702559  best dqsien dly found for B0: ( 0, 14, 24)

 6307 16:52:00.705595  Total UI for P1: 0, mck2ui 16

 6308 16:52:00.709413  best dqsien dly found for B1: ( 0, 14, 24)

 6309 16:52:00.712076  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6310 16:52:00.718996  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6311 16:52:00.719080  

 6312 16:52:00.722094  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6313 16:52:00.725627  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6314 16:52:00.729060  [Gating] SW calibration Done

 6315 16:52:00.729141  ==

 6316 16:52:00.732692  Dram Type= 6, Freq= 0, CH_0, rank 0

 6317 16:52:00.735926  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6318 16:52:00.736044  ==

 6319 16:52:00.736108  RX Vref Scan: 0

 6320 16:52:00.738772  

 6321 16:52:00.738851  RX Vref 0 -> 0, step: 1

 6322 16:52:00.738914  

 6323 16:52:00.742220  RX Delay -410 -> 252, step: 16

 6324 16:52:00.745805  iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480

 6325 16:52:00.752601  iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512

 6326 16:52:00.755618  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6327 16:52:00.758823  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6328 16:52:00.762223  iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496

 6329 16:52:00.768859  iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512

 6330 16:52:00.772294  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6331 16:52:00.775473  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6332 16:52:00.778875  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6333 16:52:00.785638  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6334 16:52:00.788642  iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496

 6335 16:52:00.791930  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6336 16:52:00.795423  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6337 16:52:00.801872  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6338 16:52:00.805476  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6339 16:52:00.809333  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6340 16:52:00.809413  ==

 6341 16:52:00.812270  Dram Type= 6, Freq= 0, CH_0, rank 0

 6342 16:52:00.818557  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6343 16:52:00.818637  ==

 6344 16:52:00.818707  DQS Delay:

 6345 16:52:00.821930  DQS0 = 43, DQS1 = 51

 6346 16:52:00.822009  DQM Delay:

 6347 16:52:00.822072  DQM0 = 15, DQM1 = 10

 6348 16:52:00.824898  DQ Delay:

 6349 16:52:00.828524  DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8

 6350 16:52:00.832039  DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24

 6351 16:52:00.832122  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6352 16:52:00.835000  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6353 16:52:00.838219  

 6354 16:52:00.838298  

 6355 16:52:00.838360  ==

 6356 16:52:00.841704  Dram Type= 6, Freq= 0, CH_0, rank 0

 6357 16:52:00.845372  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6358 16:52:00.845450  ==

 6359 16:52:00.845513  

 6360 16:52:00.845571  

 6361 16:52:00.848748  	TX Vref Scan disable

 6362 16:52:00.848828   == TX Byte 0 ==

 6363 16:52:00.851819  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6364 16:52:00.858129  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6365 16:52:00.858209   == TX Byte 1 ==

 6366 16:52:00.862137  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6367 16:52:00.868292  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6368 16:52:00.868372  ==

 6369 16:52:00.871822  Dram Type= 6, Freq= 0, CH_0, rank 0

 6370 16:52:00.874927  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6371 16:52:00.875013  ==

 6372 16:52:00.875077  

 6373 16:52:00.875134  

 6374 16:52:00.878537  	TX Vref Scan disable

 6375 16:52:00.878620   == TX Byte 0 ==

 6376 16:52:00.884691  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6377 16:52:00.888125  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6378 16:52:00.888207   == TX Byte 1 ==

 6379 16:52:00.891577  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6380 16:52:00.898535  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6381 16:52:00.898625  

 6382 16:52:00.898689  [DATLAT]

 6383 16:52:00.901282  Freq=400, CH0 RK0

 6384 16:52:00.901363  

 6385 16:52:00.901426  DATLAT Default: 0xf

 6386 16:52:00.904818  0, 0xFFFF, sum = 0

 6387 16:52:00.904900  1, 0xFFFF, sum = 0

 6388 16:52:00.907918  2, 0xFFFF, sum = 0

 6389 16:52:00.908035  3, 0xFFFF, sum = 0

 6390 16:52:00.911393  4, 0xFFFF, sum = 0

 6391 16:52:00.911475  5, 0xFFFF, sum = 0

 6392 16:52:00.914630  6, 0xFFFF, sum = 0

 6393 16:52:00.914711  7, 0xFFFF, sum = 0

 6394 16:52:00.918246  8, 0xFFFF, sum = 0

 6395 16:52:00.918332  9, 0xFFFF, sum = 0

 6396 16:52:00.921594  10, 0xFFFF, sum = 0

 6397 16:52:00.921680  11, 0xFFFF, sum = 0

 6398 16:52:00.924667  12, 0xFFFF, sum = 0

 6399 16:52:00.924755  13, 0x0, sum = 1

 6400 16:52:00.927875  14, 0x0, sum = 2

 6401 16:52:00.927983  15, 0x0, sum = 3

 6402 16:52:00.931515  16, 0x0, sum = 4

 6403 16:52:00.931599  best_step = 14

 6404 16:52:00.931664  

 6405 16:52:00.931724  ==

 6406 16:52:00.934782  Dram Type= 6, Freq= 0, CH_0, rank 0

 6407 16:52:00.941363  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6408 16:52:00.941452  ==

 6409 16:52:00.941520  RX Vref Scan: 1

 6410 16:52:00.941580  

 6411 16:52:00.944649  RX Vref 0 -> 0, step: 1

 6412 16:52:00.944732  

 6413 16:52:00.947877  RX Delay -343 -> 252, step: 8

 6414 16:52:00.947995  

 6415 16:52:00.951902  Set Vref, RX VrefLevel [Byte0]: 56

 6416 16:52:00.954849                           [Byte1]: 52

 6417 16:52:00.957992  

 6418 16:52:00.958075  Final RX Vref Byte 0 = 56 to rank0

 6419 16:52:00.961267  Final RX Vref Byte 1 = 52 to rank0

 6420 16:52:00.964264  Final RX Vref Byte 0 = 56 to rank1

 6421 16:52:00.968134  Final RX Vref Byte 1 = 52 to rank1==

 6422 16:52:00.971358  Dram Type= 6, Freq= 0, CH_0, rank 0

 6423 16:52:00.978216  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6424 16:52:00.978302  ==

 6425 16:52:00.978368  DQS Delay:

 6426 16:52:00.980806  DQS0 = 44, DQS1 = 60

 6427 16:52:00.980888  DQM Delay:

 6428 16:52:00.980952  DQM0 = 11, DQM1 = 15

 6429 16:52:00.984847  DQ Delay:

 6430 16:52:00.987483  DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8

 6431 16:52:00.987567  DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20

 6432 16:52:00.990996  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12

 6433 16:52:00.994498  DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28

 6434 16:52:00.994579  

 6435 16:52:00.997888  

 6436 16:52:01.004770  [DQSOSCAuto] RK0, (LSB)MR18= 0x8553, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps

 6437 16:52:01.007726  CH0 RK0: MR19=C0C, MR18=8553

 6438 16:52:01.014327  CH0_RK0: MR19=0xC0C, MR18=0x8553, DQSOSC=393, MR23=63, INC=382, DEC=254

 6439 16:52:01.014430  ==

 6440 16:52:01.017850  Dram Type= 6, Freq= 0, CH_0, rank 1

 6441 16:52:01.020899  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6442 16:52:01.020982  ==

 6443 16:52:01.024781  [Gating] SW mode calibration

 6444 16:52:01.030673  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6445 16:52:01.037270  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6446 16:52:01.041008   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6447 16:52:01.044201   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6448 16:52:01.047339   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6449 16:52:01.054172   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6450 16:52:01.057436   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6451 16:52:01.060828   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6452 16:52:01.067528   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6453 16:52:01.071065   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6454 16:52:01.073795   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6455 16:52:01.077231  Total UI for P1: 0, mck2ui 16

 6456 16:52:01.080688  best dqsien dly found for B0: ( 0, 14, 24)

 6457 16:52:01.084042  Total UI for P1: 0, mck2ui 16

 6458 16:52:01.087578  best dqsien dly found for B1: ( 0, 14, 24)

 6459 16:52:01.090592  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6460 16:52:01.097385  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6461 16:52:01.097470  

 6462 16:52:01.100961  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6463 16:52:01.104289  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6464 16:52:01.107704  [Gating] SW calibration Done

 6465 16:52:01.107785  ==

 6466 16:52:01.110928  Dram Type= 6, Freq= 0, CH_0, rank 1

 6467 16:52:01.113945  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6468 16:52:01.114027  ==

 6469 16:52:01.114091  RX Vref Scan: 0

 6470 16:52:01.117440  

 6471 16:52:01.117522  RX Vref 0 -> 0, step: 1

 6472 16:52:01.117586  

 6473 16:52:01.120774  RX Delay -410 -> 252, step: 16

 6474 16:52:01.123713  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6475 16:52:01.130836  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6476 16:52:01.133937  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6477 16:52:01.137029  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6478 16:52:01.140325  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6479 16:52:01.146882  iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496

 6480 16:52:01.151070  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6481 16:52:01.153730  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6482 16:52:01.157587  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6483 16:52:01.163932  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6484 16:52:01.167480  iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496

 6485 16:52:01.170168  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6486 16:52:01.173748  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6487 16:52:01.180822  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6488 16:52:01.183923  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6489 16:52:01.186699  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6490 16:52:01.186780  ==

 6491 16:52:01.190608  Dram Type= 6, Freq= 0, CH_0, rank 1

 6492 16:52:01.196772  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6493 16:52:01.196887  ==

 6494 16:52:01.196991  DQS Delay:

 6495 16:52:01.200159  DQS0 = 35, DQS1 = 51

 6496 16:52:01.200240  DQM Delay:

 6497 16:52:01.200303  DQM0 = 4, DQM1 = 10

 6498 16:52:01.203738  DQ Delay:

 6499 16:52:01.206687  DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0

 6500 16:52:01.206768  DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16

 6501 16:52:01.209970  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6502 16:52:01.213675  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6503 16:52:01.213755  

 6504 16:52:01.213819  

 6505 16:52:01.216731  ==

 6506 16:52:01.220333  Dram Type= 6, Freq= 0, CH_0, rank 1

 6507 16:52:01.223623  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6508 16:52:01.223705  ==

 6509 16:52:01.223770  

 6510 16:52:01.223829  

 6511 16:52:01.226557  	TX Vref Scan disable

 6512 16:52:01.226637   == TX Byte 0 ==

 6513 16:52:01.230104  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6514 16:52:01.236647  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6515 16:52:01.236736   == TX Byte 1 ==

 6516 16:52:01.239939  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6517 16:52:01.246378  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6518 16:52:01.246460  ==

 6519 16:52:01.249983  Dram Type= 6, Freq= 0, CH_0, rank 1

 6520 16:52:01.253192  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6521 16:52:01.253273  ==

 6522 16:52:01.253337  

 6523 16:52:01.253395  

 6524 16:52:01.256955  	TX Vref Scan disable

 6525 16:52:01.257047   == TX Byte 0 ==

 6526 16:52:01.259662  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6527 16:52:01.266845  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6528 16:52:01.266927   == TX Byte 1 ==

 6529 16:52:01.270078  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6530 16:52:01.276311  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6531 16:52:01.276393  

 6532 16:52:01.276460  [DATLAT]

 6533 16:52:01.276520  Freq=400, CH0 RK1

 6534 16:52:01.276578  

 6535 16:52:01.280565  DATLAT Default: 0xe

 6536 16:52:01.280646  0, 0xFFFF, sum = 0

 6537 16:52:01.283372  1, 0xFFFF, sum = 0

 6538 16:52:01.283454  2, 0xFFFF, sum = 0

 6539 16:52:01.286438  3, 0xFFFF, sum = 0

 6540 16:52:01.289893  4, 0xFFFF, sum = 0

 6541 16:52:01.289975  5, 0xFFFF, sum = 0

 6542 16:52:01.293316  6, 0xFFFF, sum = 0

 6543 16:52:01.293398  7, 0xFFFF, sum = 0

 6544 16:52:01.296753  8, 0xFFFF, sum = 0

 6545 16:52:01.296835  9, 0xFFFF, sum = 0

 6546 16:52:01.300186  10, 0xFFFF, sum = 0

 6547 16:52:01.300268  11, 0xFFFF, sum = 0

 6548 16:52:01.303741  12, 0xFFFF, sum = 0

 6549 16:52:01.303849  13, 0x0, sum = 1

 6550 16:52:01.306790  14, 0x0, sum = 2

 6551 16:52:01.306872  15, 0x0, sum = 3

 6552 16:52:01.309910  16, 0x0, sum = 4

 6553 16:52:01.309991  best_step = 14

 6554 16:52:01.310055  

 6555 16:52:01.310113  ==

 6556 16:52:01.313182  Dram Type= 6, Freq= 0, CH_0, rank 1

 6557 16:52:01.316878  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6558 16:52:01.316959  ==

 6559 16:52:01.319819  RX Vref Scan: 0

 6560 16:52:01.319923  

 6561 16:52:01.323365  RX Vref 0 -> 0, step: 1

 6562 16:52:01.323445  

 6563 16:52:01.323508  RX Delay -343 -> 252, step: 8

 6564 16:52:01.332411  iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488

 6565 16:52:01.335306  iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488

 6566 16:52:01.338931  iDelay=217, Bit 2, Center -36 (-279 ~ 208) 488

 6567 16:52:01.342027  iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488

 6568 16:52:01.348563  iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488

 6569 16:52:01.351831  iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480

 6570 16:52:01.355495  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6571 16:52:01.358672  iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488

 6572 16:52:01.365130  iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488

 6573 16:52:01.369028  iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488

 6574 16:52:01.371766  iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488

 6575 16:52:01.378313  iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480

 6576 16:52:01.381973  iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488

 6577 16:52:01.385218  iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480

 6578 16:52:01.388385  iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488

 6579 16:52:01.395301  iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488

 6580 16:52:01.395384  ==

 6581 16:52:01.398663  Dram Type= 6, Freq= 0, CH_0, rank 1

 6582 16:52:01.401639  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6583 16:52:01.401722  ==

 6584 16:52:01.401787  DQS Delay:

 6585 16:52:01.405054  DQS0 = 48, DQS1 = 60

 6586 16:52:01.405135  DQM Delay:

 6587 16:52:01.408552  DQM0 = 12, DQM1 = 13

 6588 16:52:01.408633  DQ Delay:

 6589 16:52:01.411648  DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =12

 6590 16:52:01.414844  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20

 6591 16:52:01.418085  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4

 6592 16:52:01.421646  DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24

 6593 16:52:01.421727  

 6594 16:52:01.421790  

 6595 16:52:01.428149  [DQSOSCAuto] RK1, (LSB)MR18= 0x996b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps

 6596 16:52:01.431661  CH0 RK1: MR19=C0C, MR18=996B

 6597 16:52:01.438110  CH0_RK1: MR19=0xC0C, MR18=0x996B, DQSOSC=390, MR23=63, INC=388, DEC=258

 6598 16:52:01.441586  [RxdqsGatingPostProcess] freq 400

 6599 16:52:01.448074  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6600 16:52:01.451164  best DQS0 dly(2T, 0.5T) = (0, 10)

 6601 16:52:01.454372  best DQS1 dly(2T, 0.5T) = (0, 10)

 6602 16:52:01.457920  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6603 16:52:01.461304  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6604 16:52:01.461386  best DQS0 dly(2T, 0.5T) = (0, 10)

 6605 16:52:01.464480  best DQS1 dly(2T, 0.5T) = (0, 10)

 6606 16:52:01.468124  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6607 16:52:01.471664  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6608 16:52:01.474507  Pre-setting of DQS Precalculation

 6609 16:52:01.481036  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6610 16:52:01.481119  ==

 6611 16:52:01.484367  Dram Type= 6, Freq= 0, CH_1, rank 0

 6612 16:52:01.487873  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6613 16:52:01.487986  ==

 6614 16:52:01.494634  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6615 16:52:01.501199  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6616 16:52:01.501286  [CA 0] Center 36 (8~64) winsize 57

 6617 16:52:01.504742  [CA 1] Center 36 (8~64) winsize 57

 6618 16:52:01.507664  [CA 2] Center 36 (8~64) winsize 57

 6619 16:52:01.511071  [CA 3] Center 36 (8~64) winsize 57

 6620 16:52:01.514371  [CA 4] Center 36 (8~64) winsize 57

 6621 16:52:01.517803  [CA 5] Center 36 (8~64) winsize 57

 6622 16:52:01.517886  

 6623 16:52:01.521144  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6624 16:52:01.521226  

 6625 16:52:01.523994  [CATrainingPosCal] consider 1 rank data

 6626 16:52:01.527463  u2DelayCellTimex100 = 270/100 ps

 6627 16:52:01.530750  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6628 16:52:01.537754  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6629 16:52:01.540594  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6630 16:52:01.544105  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6631 16:52:01.547623  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6632 16:52:01.551132  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6633 16:52:01.551213  

 6634 16:52:01.553767  CA PerBit enable=1, Macro0, CA PI delay=36

 6635 16:52:01.553850  

 6636 16:52:01.557497  [CBTSetCACLKResult] CA Dly = 36

 6637 16:52:01.557579  CS Dly: 1 (0~32)

 6638 16:52:01.560493  ==

 6639 16:52:01.563695  Dram Type= 6, Freq= 0, CH_1, rank 1

 6640 16:52:01.567421  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6641 16:52:01.567503  ==

 6642 16:52:01.570621  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6643 16:52:01.577092  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6644 16:52:01.580603  [CA 0] Center 36 (8~64) winsize 57

 6645 16:52:01.584103  [CA 1] Center 36 (8~64) winsize 57

 6646 16:52:01.587255  [CA 2] Center 36 (8~64) winsize 57

 6647 16:52:01.590340  [CA 3] Center 36 (8~64) winsize 57

 6648 16:52:01.593882  [CA 4] Center 36 (8~64) winsize 57

 6649 16:52:01.597326  [CA 5] Center 36 (8~64) winsize 57

 6650 16:52:01.597409  

 6651 16:52:01.600439  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6652 16:52:01.600521  

 6653 16:52:01.603622  [CATrainingPosCal] consider 2 rank data

 6654 16:52:01.607044  u2DelayCellTimex100 = 270/100 ps

 6655 16:52:01.610551  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6656 16:52:01.614051  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6657 16:52:01.616754  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6658 16:52:01.620485  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6659 16:52:01.627294  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6660 16:52:01.630121  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6661 16:52:01.630202  

 6662 16:52:01.633490  CA PerBit enable=1, Macro0, CA PI delay=36

 6663 16:52:01.633570  

 6664 16:52:01.637011  [CBTSetCACLKResult] CA Dly = 36

 6665 16:52:01.637091  CS Dly: 1 (0~32)

 6666 16:52:01.637154  

 6667 16:52:01.640833  ----->DramcWriteLeveling(PI) begin...

 6668 16:52:01.640915  ==

 6669 16:52:01.643725  Dram Type= 6, Freq= 0, CH_1, rank 0

 6670 16:52:01.650068  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6671 16:52:01.650149  ==

 6672 16:52:01.653438  Write leveling (Byte 0): 40 => 8

 6673 16:52:01.653524  Write leveling (Byte 1): 40 => 8

 6674 16:52:01.656666  DramcWriteLeveling(PI) end<-----

 6675 16:52:01.656746  

 6676 16:52:01.656809  ==

 6677 16:52:01.660161  Dram Type= 6, Freq= 0, CH_1, rank 0

 6678 16:52:01.667320  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6679 16:52:01.667402  ==

 6680 16:52:01.670445  [Gating] SW mode calibration

 6681 16:52:01.676894  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6682 16:52:01.680298  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6683 16:52:01.686918   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6684 16:52:01.690454   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6685 16:52:01.693644   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6686 16:52:01.700297   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6687 16:52:01.703588   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6688 16:52:01.706795   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6689 16:52:01.710002   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6690 16:52:01.717017   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6691 16:52:01.720402   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6692 16:52:01.723267  Total UI for P1: 0, mck2ui 16

 6693 16:52:01.726747  best dqsien dly found for B0: ( 0, 14, 24)

 6694 16:52:01.729970  Total UI for P1: 0, mck2ui 16

 6695 16:52:01.733485  best dqsien dly found for B1: ( 0, 14, 24)

 6696 16:52:01.736951  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6697 16:52:01.739895  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6698 16:52:01.740023  

 6699 16:52:01.743337  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6700 16:52:01.750132  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6701 16:52:01.750215  [Gating] SW calibration Done

 6702 16:52:01.750279  ==

 6703 16:52:01.752944  Dram Type= 6, Freq= 0, CH_1, rank 0

 6704 16:52:01.759589  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6705 16:52:01.759701  ==

 6706 16:52:01.759769  RX Vref Scan: 0

 6707 16:52:01.759829  

 6708 16:52:01.762894  RX Vref 0 -> 0, step: 1

 6709 16:52:01.762975  

 6710 16:52:01.766307  RX Delay -410 -> 252, step: 16

 6711 16:52:01.769749  iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480

 6712 16:52:01.773118  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6713 16:52:01.779538  iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496

 6714 16:52:01.783185  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6715 16:52:01.786417  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6716 16:52:01.789701  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6717 16:52:01.796292  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6718 16:52:01.799362  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6719 16:52:01.802849  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6720 16:52:01.806031  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6721 16:52:01.812978  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6722 16:52:01.816300  iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512

 6723 16:52:01.819130  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6724 16:52:01.822539  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6725 16:52:01.829808  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6726 16:52:01.832631  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6727 16:52:01.832716  ==

 6728 16:52:01.835971  Dram Type= 6, Freq= 0, CH_1, rank 0

 6729 16:52:01.839442  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6730 16:52:01.839529  ==

 6731 16:52:01.842946  DQS Delay:

 6732 16:52:01.843020  DQS0 = 51, DQS1 = 59

 6733 16:52:01.845978  DQM Delay:

 6734 16:52:01.846050  DQM0 = 19, DQM1 = 16

 6735 16:52:01.846112  DQ Delay:

 6736 16:52:01.849075  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6737 16:52:01.852538  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6738 16:52:01.855872  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16

 6739 16:52:01.859303  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6740 16:52:01.859374  

 6741 16:52:01.859434  

 6742 16:52:01.862721  ==

 6743 16:52:01.862802  Dram Type= 6, Freq= 0, CH_1, rank 0

 6744 16:52:01.869394  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6745 16:52:01.869474  ==

 6746 16:52:01.869538  

 6747 16:52:01.869596  

 6748 16:52:01.872689  	TX Vref Scan disable

 6749 16:52:01.872770   == TX Byte 0 ==

 6750 16:52:01.876124  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6751 16:52:01.882202  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6752 16:52:01.882282   == TX Byte 1 ==

 6753 16:52:01.886044  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6754 16:52:01.892453  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6755 16:52:01.892558  ==

 6756 16:52:01.895704  Dram Type= 6, Freq= 0, CH_1, rank 0

 6757 16:52:01.899115  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6758 16:52:01.899216  ==

 6759 16:52:01.899305  

 6760 16:52:01.899391  

 6761 16:52:01.901846  	TX Vref Scan disable

 6762 16:52:01.901944   == TX Byte 0 ==

 6763 16:52:01.905726  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6764 16:52:01.912359  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6765 16:52:01.912440   == TX Byte 1 ==

 6766 16:52:01.915473  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6767 16:52:01.921950  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6768 16:52:01.922056  

 6769 16:52:01.922147  [DATLAT]

 6770 16:52:01.922243  Freq=400, CH1 RK0

 6771 16:52:01.922331  

 6772 16:52:01.925390  DATLAT Default: 0xf

 6773 16:52:01.928998  0, 0xFFFF, sum = 0

 6774 16:52:01.929106  1, 0xFFFF, sum = 0

 6775 16:52:01.932323  2, 0xFFFF, sum = 0

 6776 16:52:01.932404  3, 0xFFFF, sum = 0

 6777 16:52:01.935771  4, 0xFFFF, sum = 0

 6778 16:52:01.935879  5, 0xFFFF, sum = 0

 6779 16:52:01.938686  6, 0xFFFF, sum = 0

 6780 16:52:01.938773  7, 0xFFFF, sum = 0

 6781 16:52:01.942293  8, 0xFFFF, sum = 0

 6782 16:52:01.942649  9, 0xFFFF, sum = 0

 6783 16:52:01.945848  10, 0xFFFF, sum = 0

 6784 16:52:01.946203  11, 0xFFFF, sum = 0

 6785 16:52:01.948995  12, 0xFFFF, sum = 0

 6786 16:52:01.949350  13, 0x0, sum = 1

 6787 16:52:01.952562  14, 0x0, sum = 2

 6788 16:52:01.952922  15, 0x0, sum = 3

 6789 16:52:01.958755  16, 0x0, sum = 4

 6790 16:52:01.958837  best_step = 14

 6791 16:52:01.958901  

 6792 16:52:01.958959  ==

 6793 16:52:01.959015  Dram Type= 6, Freq= 0, CH_1, rank 0

 6794 16:52:01.962319  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6795 16:52:01.965763  ==

 6796 16:52:01.965850  RX Vref Scan: 1

 6797 16:52:01.965919  

 6798 16:52:01.969066  RX Vref 0 -> 0, step: 1

 6799 16:52:01.969158  

 6800 16:52:01.971947  RX Delay -359 -> 252, step: 8

 6801 16:52:01.972053  

 6802 16:52:01.975430  Set Vref, RX VrefLevel [Byte0]: 56

 6803 16:52:01.975531                           [Byte1]: 50

 6804 16:52:01.981064  

 6805 16:52:01.981163  Final RX Vref Byte 0 = 56 to rank0

 6806 16:52:01.984957  Final RX Vref Byte 1 = 50 to rank0

 6807 16:52:01.988310  Final RX Vref Byte 0 = 56 to rank1

 6808 16:52:01.991053  Final RX Vref Byte 1 = 50 to rank1==

 6809 16:52:01.994416  Dram Type= 6, Freq= 0, CH_1, rank 0

 6810 16:52:02.000802  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6811 16:52:02.000886  ==

 6812 16:52:02.000961  DQS Delay:

 6813 16:52:02.004557  DQS0 = 48, DQS1 = 60

 6814 16:52:02.004638  DQM Delay:

 6815 16:52:02.004702  DQM0 = 12, DQM1 = 13

 6816 16:52:02.007610  DQ Delay:

 6817 16:52:02.010860  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12

 6818 16:52:02.010941  DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8

 6819 16:52:02.014196  DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8

 6820 16:52:02.017984  DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20

 6821 16:52:02.018064  

 6822 16:52:02.020882  

 6823 16:52:02.027574  [DQSOSCAuto] RK0, (LSB)MR18= 0x8830, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps

 6824 16:52:02.030785  CH1 RK0: MR19=C0C, MR18=8830

 6825 16:52:02.037678  CH1_RK0: MR19=0xC0C, MR18=0x8830, DQSOSC=392, MR23=63, INC=384, DEC=256

 6826 16:52:02.037759  ==

 6827 16:52:02.041017  Dram Type= 6, Freq= 0, CH_1, rank 1

 6828 16:52:02.044522  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6829 16:52:02.044603  ==

 6830 16:52:02.047592  [Gating] SW mode calibration

 6831 16:52:02.054120  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6832 16:52:02.060480  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6833 16:52:02.063820   0 11  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 6834 16:52:02.067721   0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 6835 16:52:02.073927   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6836 16:52:02.077277   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6837 16:52:02.080273   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6838 16:52:02.087681   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6839 16:52:02.090794   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6840 16:52:02.093534   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6841 16:52:02.100690   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6842 16:52:02.100800  Total UI for P1: 0, mck2ui 16

 6843 16:52:02.103590  best dqsien dly found for B0: ( 0, 14, 24)

 6844 16:52:02.106804  Total UI for P1: 0, mck2ui 16

 6845 16:52:02.110536  best dqsien dly found for B1: ( 0, 14, 24)

 6846 16:52:02.117159  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6847 16:52:02.120317  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6848 16:52:02.120399  

 6849 16:52:02.123324  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6850 16:52:02.126919  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6851 16:52:02.130309  [Gating] SW calibration Done

 6852 16:52:02.130390  ==

 6853 16:52:02.133560  Dram Type= 6, Freq= 0, CH_1, rank 1

 6854 16:52:02.137164  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6855 16:52:02.137245  ==

 6856 16:52:02.140177  RX Vref Scan: 0

 6857 16:52:02.140257  

 6858 16:52:02.140321  RX Vref 0 -> 0, step: 1

 6859 16:52:02.140379  

 6860 16:52:02.143441  RX Delay -410 -> 252, step: 16

 6861 16:52:02.150286  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6862 16:52:02.153167  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6863 16:52:02.156422  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6864 16:52:02.160103  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6865 16:52:02.166874  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6866 16:52:02.170416  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6867 16:52:02.173308  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6868 16:52:02.176888  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6869 16:52:02.179833  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6870 16:52:02.186594  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6871 16:52:02.189914  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6872 16:52:02.193116  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6873 16:52:02.199909  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6874 16:52:02.203263  iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512

 6875 16:52:02.206105  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6876 16:52:02.210237  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6877 16:52:02.213016  ==

 6878 16:52:02.216227  Dram Type= 6, Freq= 0, CH_1, rank 1

 6879 16:52:02.219791  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6880 16:52:02.219898  ==

 6881 16:52:02.220019  DQS Delay:

 6882 16:52:02.222674  DQS0 = 43, DQS1 = 59

 6883 16:52:02.222754  DQM Delay:

 6884 16:52:02.226271  DQM0 = 10, DQM1 = 17

 6885 16:52:02.226366  DQ Delay:

 6886 16:52:02.229478  DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8

 6887 16:52:02.232682  DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8

 6888 16:52:02.235892  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8

 6889 16:52:02.239304  DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24

 6890 16:52:02.239385  

 6891 16:52:02.239449  

 6892 16:52:02.239508  ==

 6893 16:52:02.242640  Dram Type= 6, Freq= 0, CH_1, rank 1

 6894 16:52:02.246099  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6895 16:52:02.246181  ==

 6896 16:52:02.246244  

 6897 16:52:02.246302  

 6898 16:52:02.249645  	TX Vref Scan disable

 6899 16:52:02.249726   == TX Byte 0 ==

 6900 16:52:02.256356  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6901 16:52:02.259219  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6902 16:52:02.259299   == TX Byte 1 ==

 6903 16:52:02.265983  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6904 16:52:02.269329  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6905 16:52:02.269410  ==

 6906 16:52:02.272931  Dram Type= 6, Freq= 0, CH_1, rank 1

 6907 16:52:02.275911  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6908 16:52:02.276039  ==

 6909 16:52:02.276104  

 6910 16:52:02.276163  

 6911 16:52:02.279459  	TX Vref Scan disable

 6912 16:52:02.279542   == TX Byte 0 ==

 6913 16:52:02.286245  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6914 16:52:02.289342  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6915 16:52:02.289423   == TX Byte 1 ==

 6916 16:52:02.295912  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6917 16:52:02.298833  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6918 16:52:02.298914  

 6919 16:52:02.298977  [DATLAT]

 6920 16:52:02.302057  Freq=400, CH1 RK1

 6921 16:52:02.302138  

 6922 16:52:02.302201  DATLAT Default: 0xe

 6923 16:52:02.305594  0, 0xFFFF, sum = 0

 6924 16:52:02.305677  1, 0xFFFF, sum = 0

 6925 16:52:02.309023  2, 0xFFFF, sum = 0

 6926 16:52:02.309105  3, 0xFFFF, sum = 0

 6927 16:52:02.312427  4, 0xFFFF, sum = 0

 6928 16:52:02.312508  5, 0xFFFF, sum = 0

 6929 16:52:02.315411  6, 0xFFFF, sum = 0

 6930 16:52:02.315492  7, 0xFFFF, sum = 0

 6931 16:52:02.318637  8, 0xFFFF, sum = 0

 6932 16:52:02.318719  9, 0xFFFF, sum = 0

 6933 16:52:02.322040  10, 0xFFFF, sum = 0

 6934 16:52:02.325612  11, 0xFFFF, sum = 0

 6935 16:52:02.325693  12, 0xFFFF, sum = 0

 6936 16:52:02.328941  13, 0x0, sum = 1

 6937 16:52:02.329023  14, 0x0, sum = 2

 6938 16:52:02.329088  15, 0x0, sum = 3

 6939 16:52:02.332189  16, 0x0, sum = 4

 6940 16:52:02.332271  best_step = 14

 6941 16:52:02.332333  

 6942 16:52:02.335269  ==

 6943 16:52:02.335350  Dram Type= 6, Freq= 0, CH_1, rank 1

 6944 16:52:02.342146  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6945 16:52:02.342227  ==

 6946 16:52:02.342291  RX Vref Scan: 0

 6947 16:52:02.342354  

 6948 16:52:02.345331  RX Vref 0 -> 0, step: 1

 6949 16:52:02.345412  

 6950 16:52:02.348699  RX Delay -359 -> 252, step: 8

 6951 16:52:02.355924  iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488

 6952 16:52:02.358692  iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488

 6953 16:52:02.361824  iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496

 6954 16:52:02.368484  iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480

 6955 16:52:02.371936  iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488

 6956 16:52:02.375100  iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488

 6957 16:52:02.378275  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6958 16:52:02.385244  iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480

 6959 16:52:02.388564  iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496

 6960 16:52:02.391992  iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488

 6961 16:52:02.395248  iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488

 6962 16:52:02.401520  iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488

 6963 16:52:02.404749  iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480

 6964 16:52:02.407994  iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496

 6965 16:52:02.411362  iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496

 6966 16:52:02.418050  iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496

 6967 16:52:02.418132  ==

 6968 16:52:02.421355  Dram Type= 6, Freq= 0, CH_1, rank 1

 6969 16:52:02.425212  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6970 16:52:02.425294  ==

 6971 16:52:02.425359  DQS Delay:

 6972 16:52:02.427895  DQS0 = 48, DQS1 = 60

 6973 16:52:02.428009  DQM Delay:

 6974 16:52:02.431530  DQM0 = 10, DQM1 = 13

 6975 16:52:02.431611  DQ Delay:

 6976 16:52:02.435159  DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8

 6977 16:52:02.438507  DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8

 6978 16:52:02.441417  DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8

 6979 16:52:02.444679  DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20

 6980 16:52:02.444761  

 6981 16:52:02.444829  

 6982 16:52:02.451732  [DQSOSCAuto] RK1, (LSB)MR18= 0x758c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps

 6983 16:52:02.454974  CH1 RK1: MR19=C0C, MR18=758C

 6984 16:52:02.461588  CH1_RK1: MR19=0xC0C, MR18=0x758C, DQSOSC=392, MR23=63, INC=384, DEC=256

 6985 16:52:02.464553  [RxdqsGatingPostProcess] freq 400

 6986 16:52:02.471311  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6987 16:52:02.474733  best DQS0 dly(2T, 0.5T) = (0, 10)

 6988 16:52:02.477970  best DQS1 dly(2T, 0.5T) = (0, 10)

 6989 16:52:02.478056  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6990 16:52:02.481601  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6991 16:52:02.484850  best DQS0 dly(2T, 0.5T) = (0, 10)

 6992 16:52:02.488200  best DQS1 dly(2T, 0.5T) = (0, 10)

 6993 16:52:02.491714  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6994 16:52:02.494487  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6995 16:52:02.497903  Pre-setting of DQS Precalculation

 6996 16:52:02.504809  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6997 16:52:02.511137  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 6998 16:52:02.517765  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6999 16:52:02.517847  

 7000 16:52:02.517911  

 7001 16:52:02.521309  [Calibration Summary] 800 Mbps

 7002 16:52:02.521391  CH 0, Rank 0

 7003 16:52:02.524661  SW Impedance     : PASS

 7004 16:52:02.527667  DUTY Scan        : NO K

 7005 16:52:02.527749  ZQ Calibration   : PASS

 7006 16:52:02.531062  Jitter Meter     : NO K

 7007 16:52:02.534441  CBT Training     : PASS

 7008 16:52:02.534539  Write leveling   : PASS

 7009 16:52:02.537737  RX DQS gating    : PASS

 7010 16:52:02.540977  RX DQ/DQS(RDDQC) : PASS

 7011 16:52:02.541058  TX DQ/DQS        : PASS

 7012 16:52:02.544321  RX DATLAT        : PASS

 7013 16:52:02.544403  RX DQ/DQS(Engine): PASS

 7014 16:52:02.547423  TX OE            : NO K

 7015 16:52:02.547505  All Pass.

 7016 16:52:02.547570  

 7017 16:52:02.550865  CH 0, Rank 1

 7018 16:52:02.550955  SW Impedance     : PASS

 7019 16:52:02.554373  DUTY Scan        : NO K

 7020 16:52:02.557636  ZQ Calibration   : PASS

 7021 16:52:02.557717  Jitter Meter     : NO K

 7022 16:52:02.561172  CBT Training     : PASS

 7023 16:52:02.564171  Write leveling   : NO K

 7024 16:52:02.564253  RX DQS gating    : PASS

 7025 16:52:02.567339  RX DQ/DQS(RDDQC) : PASS

 7026 16:52:02.571032  TX DQ/DQS        : PASS

 7027 16:52:02.571113  RX DATLAT        : PASS

 7028 16:52:02.573899  RX DQ/DQS(Engine): PASS

 7029 16:52:02.577843  TX OE            : NO K

 7030 16:52:02.577925  All Pass.

 7031 16:52:02.577989  

 7032 16:52:02.578049  CH 1, Rank 0

 7033 16:52:02.580747  SW Impedance     : PASS

 7034 16:52:02.583896  DUTY Scan        : NO K

 7035 16:52:02.584001  ZQ Calibration   : PASS

 7036 16:52:02.587369  Jitter Meter     : NO K

 7037 16:52:02.590857  CBT Training     : PASS

 7038 16:52:02.590939  Write leveling   : PASS

 7039 16:52:02.594075  RX DQS gating    : PASS

 7040 16:52:02.597046  RX DQ/DQS(RDDQC) : PASS

 7041 16:52:02.597127  TX DQ/DQS        : PASS

 7042 16:52:02.600682  RX DATLAT        : PASS

 7043 16:52:02.604104  RX DQ/DQS(Engine): PASS

 7044 16:52:02.604186  TX OE            : NO K

 7045 16:52:02.604251  All Pass.

 7046 16:52:02.604311  

 7047 16:52:02.607054  CH 1, Rank 1

 7048 16:52:02.607136  SW Impedance     : PASS

 7049 16:52:02.610439  DUTY Scan        : NO K

 7050 16:52:02.613722  ZQ Calibration   : PASS

 7051 16:52:02.613803  Jitter Meter     : NO K

 7052 16:52:02.617108  CBT Training     : PASS

 7053 16:52:02.620665  Write leveling   : NO K

 7054 16:52:02.620747  RX DQS gating    : PASS

 7055 16:52:02.623429  RX DQ/DQS(RDDQC) : PASS

 7056 16:52:02.627197  TX DQ/DQS        : PASS

 7057 16:52:02.627305  RX DATLAT        : PASS

 7058 16:52:02.630363  RX DQ/DQS(Engine): PASS

 7059 16:52:02.633905  TX OE            : NO K

 7060 16:52:02.633988  All Pass.

 7061 16:52:02.634054  

 7062 16:52:02.637009  DramC Write-DBI off

 7063 16:52:02.637091  	PER_BANK_REFRESH: Hybrid Mode

 7064 16:52:02.640331  TX_TRACKING: ON

 7065 16:52:02.647113  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7066 16:52:02.653771  [FAST_K] Save calibration result to emmc

 7067 16:52:02.657406  dramc_set_vcore_voltage set vcore to 725000

 7068 16:52:02.657488  Read voltage for 1600, 0

 7069 16:52:02.660168  Vio18 = 0

 7070 16:52:02.660250  Vcore = 725000

 7071 16:52:02.660315  Vdram = 0

 7072 16:52:02.663719  Vddq = 0

 7073 16:52:02.663800  Vmddr = 0

 7074 16:52:02.666786  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7075 16:52:02.673527  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7076 16:52:02.676683  MEM_TYPE=3, freq_sel=13

 7077 16:52:02.679914  sv_algorithm_assistance_LP4_3733 

 7078 16:52:02.683371  ============ PULL DRAM RESETB DOWN ============

 7079 16:52:02.686663  ========== PULL DRAM RESETB DOWN end =========

 7080 16:52:02.693379  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7081 16:52:02.693461  =================================== 

 7082 16:52:02.696848  LPDDR4 DRAM CONFIGURATION

 7083 16:52:02.699940  =================================== 

 7084 16:52:02.703378  EX_ROW_EN[0]    = 0x0

 7085 16:52:02.703460  EX_ROW_EN[1]    = 0x0

 7086 16:52:02.706719  LP4Y_EN      = 0x0

 7087 16:52:02.706826  WORK_FSP     = 0x1

 7088 16:52:02.710056  WL           = 0x5

 7089 16:52:02.710137  RL           = 0x5

 7090 16:52:02.713628  BL           = 0x2

 7091 16:52:02.713710  RPST         = 0x0

 7092 16:52:02.716909  RD_PRE       = 0x0

 7093 16:52:02.719903  WR_PRE       = 0x1

 7094 16:52:02.720035  WR_PST       = 0x1

 7095 16:52:02.723610  DBI_WR       = 0x0

 7096 16:52:02.723717  DBI_RD       = 0x0

 7097 16:52:02.726980  OTF          = 0x1

 7098 16:52:02.729985  =================================== 

 7099 16:52:02.733347  =================================== 

 7100 16:52:02.733434  ANA top config

 7101 16:52:02.736369  =================================== 

 7102 16:52:02.739843  DLL_ASYNC_EN            =  0

 7103 16:52:02.743854  ALL_SLAVE_EN            =  0

 7104 16:52:02.743935  NEW_RANK_MODE           =  1

 7105 16:52:02.747048  DLL_IDLE_MODE           =  1

 7106 16:52:02.749997  LP45_APHY_COMB_EN       =  1

 7107 16:52:02.753530  TX_ODT_DIS              =  0

 7108 16:52:02.753612  NEW_8X_MODE             =  1

 7109 16:52:02.756430  =================================== 

 7110 16:52:02.760258  =================================== 

 7111 16:52:02.763106  data_rate                  = 3200

 7112 16:52:02.766664  CKR                        = 1

 7113 16:52:02.770276  DQ_P2S_RATIO               = 8

 7114 16:52:02.773225  =================================== 

 7115 16:52:02.776474  CA_P2S_RATIO               = 8

 7116 16:52:02.779686  DQ_CA_OPEN                 = 0

 7117 16:52:02.779767  DQ_SEMI_OPEN               = 0

 7118 16:52:02.783414  CA_SEMI_OPEN               = 0

 7119 16:52:02.786391  CA_FULL_RATE               = 0

 7120 16:52:02.789908  DQ_CKDIV4_EN               = 0

 7121 16:52:02.793071  CA_CKDIV4_EN               = 0

 7122 16:52:02.796319  CA_PREDIV_EN               = 0

 7123 16:52:02.796427  PH8_DLY                    = 12

 7124 16:52:02.799734  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7125 16:52:02.803053  DQ_AAMCK_DIV               = 4

 7126 16:52:02.806432  CA_AAMCK_DIV               = 4

 7127 16:52:02.809790  CA_ADMCK_DIV               = 4

 7128 16:52:02.813241  DQ_TRACK_CA_EN             = 0

 7129 16:52:02.813323  CA_PICK                    = 1600

 7130 16:52:02.816146  CA_MCKIO                   = 1600

 7131 16:52:02.819494  MCKIO_SEMI                 = 0

 7132 16:52:02.822990  PLL_FREQ                   = 3068

 7133 16:52:02.826702  DQ_UI_PI_RATIO             = 32

 7134 16:52:02.829569  CA_UI_PI_RATIO             = 0

 7135 16:52:02.833206  =================================== 

 7136 16:52:02.836441  =================================== 

 7137 16:52:02.839542  memory_type:LPDDR4         

 7138 16:52:02.839624  GP_NUM     : 10       

 7139 16:52:02.842888  SRAM_EN    : 1       

 7140 16:52:02.842970  MD32_EN    : 0       

 7141 16:52:02.846245  =================================== 

 7142 16:52:02.849856  [ANA_INIT] >>>>>>>>>>>>>> 

 7143 16:52:02.853136  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7144 16:52:02.856569  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7145 16:52:02.859501  =================================== 

 7146 16:52:02.863327  data_rate = 3200,PCW = 0X7600

 7147 16:52:02.866489  =================================== 

 7148 16:52:02.869899  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7149 16:52:02.872801  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7150 16:52:02.879737  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7151 16:52:02.882979  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7152 16:52:02.886210  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7153 16:52:02.892866  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7154 16:52:02.892948  [ANA_INIT] flow start 

 7155 16:52:02.896539  [ANA_INIT] PLL >>>>>>>> 

 7156 16:52:02.899386  [ANA_INIT] PLL <<<<<<<< 

 7157 16:52:02.899467  [ANA_INIT] MIDPI >>>>>>>> 

 7158 16:52:02.902918  [ANA_INIT] MIDPI <<<<<<<< 

 7159 16:52:02.906149  [ANA_INIT] DLL >>>>>>>> 

 7160 16:52:02.906231  [ANA_INIT] DLL <<<<<<<< 

 7161 16:52:02.909488  [ANA_INIT] flow end 

 7162 16:52:02.912895  ============ LP4 DIFF to SE enter ============

 7163 16:52:02.916061  ============ LP4 DIFF to SE exit  ============

 7164 16:52:02.919622  [ANA_INIT] <<<<<<<<<<<<< 

 7165 16:52:02.922931  [Flow] Enable top DCM control >>>>> 

 7166 16:52:02.925967  [Flow] Enable top DCM control <<<<< 

 7167 16:52:02.929337  Enable DLL master slave shuffle 

 7168 16:52:02.936199  ============================================================== 

 7169 16:52:02.936307  Gating Mode config

 7170 16:52:02.942672  ============================================================== 

 7171 16:52:02.942754  Config description: 

 7172 16:52:02.952270  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7173 16:52:02.959025  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7174 16:52:02.965441  SELPH_MODE            0: By rank         1: By Phase 

 7175 16:52:02.972118  ============================================================== 

 7176 16:52:02.972200  GAT_TRACK_EN                 =  1

 7177 16:52:02.975509  RX_GATING_MODE               =  2

 7178 16:52:02.978918  RX_GATING_TRACK_MODE         =  2

 7179 16:52:02.982035  SELPH_MODE                   =  1

 7180 16:52:02.985397  PICG_EARLY_EN                =  1

 7181 16:52:02.988961  VALID_LAT_VALUE              =  1

 7182 16:52:02.995334  ============================================================== 

 7183 16:52:02.998702  Enter into Gating configuration >>>> 

 7184 16:52:03.001763  Exit from Gating configuration <<<< 

 7185 16:52:03.005403  Enter into  DVFS_PRE_config >>>>> 

 7186 16:52:03.015403  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7187 16:52:03.018768  Exit from  DVFS_PRE_config <<<<< 

 7188 16:52:03.022248  Enter into PICG configuration >>>> 

 7189 16:52:03.025067  Exit from PICG configuration <<<< 

 7190 16:52:03.028438  [RX_INPUT] configuration >>>>> 

 7191 16:52:03.028519  [RX_INPUT] configuration <<<<< 

 7192 16:52:03.035248  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7193 16:52:03.042092  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7194 16:52:03.045058  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7195 16:52:03.051798  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7196 16:52:03.058149  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7197 16:52:03.064938  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7198 16:52:03.068362  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7199 16:52:03.071651  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7200 16:52:03.078529  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7201 16:52:03.081990  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7202 16:52:03.084984  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7203 16:52:03.091304  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7204 16:52:03.094679  =================================== 

 7205 16:52:03.094761  LPDDR4 DRAM CONFIGURATION

 7206 16:52:03.097872  =================================== 

 7207 16:52:03.101538  EX_ROW_EN[0]    = 0x0

 7208 16:52:03.101620  EX_ROW_EN[1]    = 0x0

 7209 16:52:03.104709  LP4Y_EN      = 0x0

 7210 16:52:03.108051  WORK_FSP     = 0x1

 7211 16:52:03.108132  WL           = 0x5

 7212 16:52:03.111301  RL           = 0x5

 7213 16:52:03.111382  BL           = 0x2

 7214 16:52:03.115172  RPST         = 0x0

 7215 16:52:03.115255  RD_PRE       = 0x0

 7216 16:52:03.118511  WR_PRE       = 0x1

 7217 16:52:03.118593  WR_PST       = 0x1

 7218 16:52:03.121364  DBI_WR       = 0x0

 7219 16:52:03.121445  DBI_RD       = 0x0

 7220 16:52:03.124581  OTF          = 0x1

 7221 16:52:03.128194  =================================== 

 7222 16:52:03.131624  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7223 16:52:03.134521  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7224 16:52:03.141376  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7225 16:52:03.144876  =================================== 

 7226 16:52:03.144958  LPDDR4 DRAM CONFIGURATION

 7227 16:52:03.147733  =================================== 

 7228 16:52:03.151294  EX_ROW_EN[0]    = 0x10

 7229 16:52:03.151376  EX_ROW_EN[1]    = 0x0

 7230 16:52:03.154341  LP4Y_EN      = 0x0

 7231 16:52:03.154423  WORK_FSP     = 0x1

 7232 16:52:03.157659  WL           = 0x5

 7233 16:52:03.157740  RL           = 0x5

 7234 16:52:03.161269  BL           = 0x2

 7235 16:52:03.164500  RPST         = 0x0

 7236 16:52:03.164581  RD_PRE       = 0x0

 7237 16:52:03.167893  WR_PRE       = 0x1

 7238 16:52:03.167980  WR_PST       = 0x1

 7239 16:52:03.171254  DBI_WR       = 0x0

 7240 16:52:03.171336  DBI_RD       = 0x0

 7241 16:52:03.174580  OTF          = 0x1

 7242 16:52:03.177924  =================================== 

 7243 16:52:03.181503  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7244 16:52:03.184344  ==

 7245 16:52:03.187746  Dram Type= 6, Freq= 0, CH_0, rank 0

 7246 16:52:03.191134  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7247 16:52:03.191216  ==

 7248 16:52:03.194338  [Duty_Offset_Calibration]

 7249 16:52:03.194420  	B0:2	B1:-1	CA:1

 7250 16:52:03.194485  

 7251 16:52:03.197993  [DutyScan_Calibration_Flow] k_type=0

 7252 16:52:03.207316  

 7253 16:52:03.207409  ==CLK 0==

 7254 16:52:03.210002  Final CLK duty delay cell = -4

 7255 16:52:03.213352  [-4] MAX Duty = 5031%(X100), DQS PI = 6

 7256 16:52:03.217107  [-4] MIN Duty = 4844%(X100), DQS PI = 32

 7257 16:52:03.220314  [-4] AVG Duty = 4937%(X100)

 7258 16:52:03.220395  

 7259 16:52:03.223335  CH0 CLK Duty spec in!! Max-Min= 187%

 7260 16:52:03.226914  [DutyScan_Calibration_Flow] ====Done====

 7261 16:52:03.226995  

 7262 16:52:03.230277  [DutyScan_Calibration_Flow] k_type=1

 7263 16:52:03.246250  

 7264 16:52:03.246331  ==DQS 0 ==

 7265 16:52:03.249693  Final DQS duty delay cell = 0

 7266 16:52:03.253081  [0] MAX Duty = 5125%(X100), DQS PI = 22

 7267 16:52:03.256227  [0] MIN Duty = 5000%(X100), DQS PI = 14

 7268 16:52:03.260012  [0] AVG Duty = 5062%(X100)

 7269 16:52:03.260094  

 7270 16:52:03.260158  ==DQS 1 ==

 7271 16:52:03.262710  Final DQS duty delay cell = -4

 7272 16:52:03.266632  [-4] MAX Duty = 5093%(X100), DQS PI = 0

 7273 16:52:03.269845  [-4] MIN Duty = 5031%(X100), DQS PI = 8

 7274 16:52:03.273293  [-4] AVG Duty = 5062%(X100)

 7275 16:52:03.273375  

 7276 16:52:03.276108  CH0 DQS 0 Duty spec in!! Max-Min= 125%

 7277 16:52:03.276191  

 7278 16:52:03.279943  CH0 DQS 1 Duty spec in!! Max-Min= 62%

 7279 16:52:03.283046  [DutyScan_Calibration_Flow] ====Done====

 7280 16:52:03.283127  

 7281 16:52:03.285970  [DutyScan_Calibration_Flow] k_type=3

 7282 16:52:03.303902  

 7283 16:52:03.304038  ==DQM 0 ==

 7284 16:52:03.307017  Final DQM duty delay cell = 0

 7285 16:52:03.310462  [0] MAX Duty = 5000%(X100), DQS PI = 20

 7286 16:52:03.313432  [0] MIN Duty = 4844%(X100), DQS PI = 8

 7287 16:52:03.317218  [0] AVG Duty = 4922%(X100)

 7288 16:52:03.317299  

 7289 16:52:03.317364  ==DQM 1 ==

 7290 16:52:03.320472  Final DQM duty delay cell = 0

 7291 16:52:03.323475  [0] MAX Duty = 5218%(X100), DQS PI = 58

 7292 16:52:03.326852  [0] MIN Duty = 4969%(X100), DQS PI = 18

 7293 16:52:03.330224  [0] AVG Duty = 5093%(X100)

 7294 16:52:03.330304  

 7295 16:52:03.333505  CH0 DQM 0 Duty spec in!! Max-Min= 156%

 7296 16:52:03.333584  

 7297 16:52:03.336773  CH0 DQM 1 Duty spec in!! Max-Min= 249%

 7298 16:52:03.339859  [DutyScan_Calibration_Flow] ====Done====

 7299 16:52:03.339937  

 7300 16:52:03.343341  [DutyScan_Calibration_Flow] k_type=2

 7301 16:52:03.360893  

 7302 16:52:03.360972  ==DQ 0 ==

 7303 16:52:03.364260  Final DQ duty delay cell = 0

 7304 16:52:03.367354  [0] MAX Duty = 5156%(X100), DQS PI = 0

 7305 16:52:03.370538  [0] MIN Duty = 5031%(X100), DQS PI = 12

 7306 16:52:03.370617  [0] AVG Duty = 5093%(X100)

 7307 16:52:03.373783  

 7308 16:52:03.373861  ==DQ 1 ==

 7309 16:52:03.377346  Final DQ duty delay cell = 0

 7310 16:52:03.380691  [0] MAX Duty = 5000%(X100), DQS PI = 0

 7311 16:52:03.384133  [0] MIN Duty = 4907%(X100), DQS PI = 26

 7312 16:52:03.384212  [0] AVG Duty = 4953%(X100)

 7313 16:52:03.384274  

 7314 16:52:03.387327  CH0 DQ 0 Duty spec in!! Max-Min= 125%

 7315 16:52:03.390295  

 7316 16:52:03.393648  CH0 DQ 1 Duty spec in!! Max-Min= 93%

 7317 16:52:03.397084  [DutyScan_Calibration_Flow] ====Done====

 7318 16:52:03.397163  ==

 7319 16:52:03.400261  Dram Type= 6, Freq= 0, CH_1, rank 0

 7320 16:52:03.403894  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7321 16:52:03.404010  ==

 7322 16:52:03.407322  [Duty_Offset_Calibration]

 7323 16:52:03.407401  	B0:1	B1:1	CA:2

 7324 16:52:03.407464  

 7325 16:52:03.410097  [DutyScan_Calibration_Flow] k_type=0

 7326 16:52:03.420842  

 7327 16:52:03.420920  ==CLK 0==

 7328 16:52:03.423891  Final CLK duty delay cell = 0

 7329 16:52:03.427655  [0] MAX Duty = 5187%(X100), DQS PI = 24

 7330 16:52:03.430963  [0] MIN Duty = 4938%(X100), DQS PI = 50

 7331 16:52:03.433930  [0] AVG Duty = 5062%(X100)

 7332 16:52:03.434010  

 7333 16:52:03.437488  CH1 CLK Duty spec in!! Max-Min= 249%

 7334 16:52:03.440797  [DutyScan_Calibration_Flow] ====Done====

 7335 16:52:03.440876  

 7336 16:52:03.443943  [DutyScan_Calibration_Flow] k_type=1

 7337 16:52:03.460706  

 7338 16:52:03.460785  ==DQS 0 ==

 7339 16:52:03.464127  Final DQS duty delay cell = 0

 7340 16:52:03.467483  [0] MAX Duty = 5062%(X100), DQS PI = 20

 7341 16:52:03.470953  [0] MIN Duty = 4813%(X100), DQS PI = 54

 7342 16:52:03.471033  [0] AVG Duty = 4937%(X100)

 7343 16:52:03.473915  

 7344 16:52:03.473995  ==DQS 1 ==

 7345 16:52:03.476983  Final DQS duty delay cell = 0

 7346 16:52:03.480584  [0] MAX Duty = 5062%(X100), DQS PI = 56

 7347 16:52:03.483966  [0] MIN Duty = 4938%(X100), DQS PI = 14

 7348 16:52:03.486973  [0] AVG Duty = 5000%(X100)

 7349 16:52:03.487053  

 7350 16:52:03.491175  CH1 DQS 0 Duty spec in!! Max-Min= 249%

 7351 16:52:03.491256  

 7352 16:52:03.493671  CH1 DQS 1 Duty spec in!! Max-Min= 124%

 7353 16:52:03.497306  [DutyScan_Calibration_Flow] ====Done====

 7354 16:52:03.497387  

 7355 16:52:03.500072  [DutyScan_Calibration_Flow] k_type=3

 7356 16:52:03.517641  

 7357 16:52:03.517723  ==DQM 0 ==

 7358 16:52:03.520987  Final DQM duty delay cell = 0

 7359 16:52:03.524007  [0] MAX Duty = 5124%(X100), DQS PI = 18

 7360 16:52:03.527561  [0] MIN Duty = 4813%(X100), DQS PI = 50

 7361 16:52:03.530867  [0] AVG Duty = 4968%(X100)

 7362 16:52:03.530947  

 7363 16:52:03.531012  ==DQM 1 ==

 7364 16:52:03.534481  Final DQM duty delay cell = 0

 7365 16:52:03.537833  [0] MAX Duty = 5125%(X100), DQS PI = 8

 7366 16:52:03.540904  [0] MIN Duty = 4875%(X100), DQS PI = 20

 7367 16:52:03.543975  [0] AVG Duty = 5000%(X100)

 7368 16:52:03.544055  

 7369 16:52:03.547254  CH1 DQM 0 Duty spec in!! Max-Min= 311%

 7370 16:52:03.547335  

 7371 16:52:03.550748  CH1 DQM 1 Duty spec in!! Max-Min= 250%

 7372 16:52:03.554073  [DutyScan_Calibration_Flow] ====Done====

 7373 16:52:03.554154  

 7374 16:52:03.557435  [DutyScan_Calibration_Flow] k_type=2

 7375 16:52:03.574225  

 7376 16:52:03.574306  ==DQ 0 ==

 7377 16:52:03.577344  Final DQ duty delay cell = 0

 7378 16:52:03.581088  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7379 16:52:03.584385  [0] MIN Duty = 4938%(X100), DQS PI = 52

 7380 16:52:03.584466  [0] AVG Duty = 5047%(X100)

 7381 16:52:03.587798  

 7382 16:52:03.587878  ==DQ 1 ==

 7383 16:52:03.590838  Final DQ duty delay cell = 0

 7384 16:52:03.594241  [0] MAX Duty = 5093%(X100), DQS PI = 6

 7385 16:52:03.597801  [0] MIN Duty = 5031%(X100), DQS PI = 2

 7386 16:52:03.597882  [0] AVG Duty = 5062%(X100)

 7387 16:52:03.597982  

 7388 16:52:03.600917  CH1 DQ 0 Duty spec in!! Max-Min= 218%

 7389 16:52:03.604281  

 7390 16:52:03.604362  CH1 DQ 1 Duty spec in!! Max-Min= 62%

 7391 16:52:03.610608  [DutyScan_Calibration_Flow] ====Done====

 7392 16:52:03.614044  nWR fixed to 30

 7393 16:52:03.614126  [ModeRegInit_LP4] CH0 RK0

 7394 16:52:03.617234  [ModeRegInit_LP4] CH0 RK1

 7395 16:52:03.620810  [ModeRegInit_LP4] CH1 RK0

 7396 16:52:03.620890  [ModeRegInit_LP4] CH1 RK1

 7397 16:52:03.624122  match AC timing 5

 7398 16:52:03.627333  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7399 16:52:03.634146  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7400 16:52:03.637829  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7401 16:52:03.643937  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7402 16:52:03.646899  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7403 16:52:03.646980  [MiockJmeterHQA]

 7404 16:52:03.647045  

 7405 16:52:03.650830  [DramcMiockJmeter] u1RxGatingPI = 0

 7406 16:52:03.653868  0 : 4255, 4029

 7407 16:52:03.653950  4 : 4252, 4027

 7408 16:52:03.654016  8 : 4253, 4026

 7409 16:52:03.657218  12 : 4253, 4027

 7410 16:52:03.657301  16 : 4252, 4027

 7411 16:52:03.660571  20 : 4363, 4137

 7412 16:52:03.660654  24 : 4252, 4027

 7413 16:52:03.663662  28 : 4363, 4138

 7414 16:52:03.663744  32 : 4253, 4026

 7415 16:52:03.666805  36 : 4252, 4027

 7416 16:52:03.666887  40 : 4253, 4027

 7417 16:52:03.666954  44 : 4363, 4137

 7418 16:52:03.670273  48 : 4252, 4027

 7419 16:52:03.670355  52 : 4363, 4137

 7420 16:52:03.673487  56 : 4250, 4027

 7421 16:52:03.673570  60 : 4250, 4027

 7422 16:52:03.676985  64 : 4250, 4027

 7423 16:52:03.677068  68 : 4253, 4029

 7424 16:52:03.680357  72 : 4361, 4138

 7425 16:52:03.680440  76 : 4250, 4027

 7426 16:52:03.680506  80 : 4361, 4137

 7427 16:52:03.683458  84 : 4250, 4027

 7428 16:52:03.683540  88 : 4250, 4027

 7429 16:52:03.686688  92 : 4250, 4027

 7430 16:52:03.686770  96 : 4361, 3348

 7431 16:52:03.690238  100 : 4250, 0

 7432 16:52:03.690321  104 : 4360, 0

 7433 16:52:03.690388  108 : 4361, 0

 7434 16:52:03.693805  112 : 4360, 0

 7435 16:52:03.693887  116 : 4250, 0

 7436 16:52:03.696491  120 : 4361, 0

 7437 16:52:03.696574  124 : 4249, 0

 7438 16:52:03.696639  128 : 4250, 0

 7439 16:52:03.699899  132 : 4250, 0

 7440 16:52:03.700035  136 : 4250, 0

 7441 16:52:03.703208  140 : 4253, 0

 7442 16:52:03.703291  144 : 4361, 0

 7443 16:52:03.703367  148 : 4250, 0

 7444 16:52:03.706573  152 : 4250, 0

 7445 16:52:03.706657  156 : 4250, 0

 7446 16:52:03.706723  160 : 4361, 0

 7447 16:52:03.710094  164 : 4361, 0

 7448 16:52:03.710176  168 : 4252, 0

 7449 16:52:03.713494  172 : 4250, 0

 7450 16:52:03.713577  176 : 4249, 0

 7451 16:52:03.713643  180 : 4250, 0

 7452 16:52:03.716991  184 : 4250, 0

 7453 16:52:03.717074  188 : 4250, 0

 7454 16:52:03.719793  192 : 4252, 0

 7455 16:52:03.719875  196 : 4250, 0

 7456 16:52:03.719941  200 : 4249, 0

 7457 16:52:03.723692  204 : 4252, 0

 7458 16:52:03.723775  208 : 4360, 0

 7459 16:52:03.726915  212 : 4361, 123

 7460 16:52:03.726997  216 : 4250, 3701

 7461 16:52:03.729885  220 : 4250, 4027

 7462 16:52:03.729967  224 : 4250, 4027

 7463 16:52:03.730033  228 : 4250, 4027

 7464 16:52:03.733228  232 : 4250, 4027

 7465 16:52:03.733310  236 : 4252, 4029

 7466 16:52:03.736830  240 : 4249, 4027

 7467 16:52:03.736913  244 : 4361, 4137

 7468 16:52:03.740300  248 : 4361, 4138

 7469 16:52:03.740381  252 : 4250, 4027

 7470 16:52:03.743298  256 : 4363, 4140

 7471 16:52:03.743380  260 : 4361, 4138

 7472 16:52:03.746646  264 : 4250, 4026

 7473 16:52:03.746729  268 : 4250, 4027

 7474 16:52:03.749957  272 : 4252, 4029

 7475 16:52:03.750040  276 : 4250, 4027

 7476 16:52:03.752911  280 : 4250, 4027

 7477 16:52:03.752994  284 : 4250, 4027

 7478 16:52:03.753060  288 : 4252, 4029

 7479 16:52:03.756133  292 : 4250, 4027

 7480 16:52:03.756218  296 : 4361, 4138

 7481 16:52:03.759507  300 : 4361, 4138

 7482 16:52:03.759590  304 : 4250, 4027

 7483 16:52:03.763118  308 : 4363, 4140

 7484 16:52:03.763201  312 : 4361, 4137

 7485 16:52:03.766589  316 : 4250, 4026

 7486 16:52:03.766671  320 : 4250, 4027

 7487 16:52:03.769388  324 : 4252, 4030

 7488 16:52:03.769470  328 : 4250, 4027

 7489 16:52:03.772999  332 : 4250, 2484

 7490 16:52:03.773081  336 : 4250, 34

 7491 16:52:03.773147  

 7492 16:52:03.776300  	MIOCK jitter meter	ch=0

 7493 16:52:03.776381  

 7494 16:52:03.779218  1T = (336-100) = 236 dly cells

 7495 16:52:03.783194  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps

 7496 16:52:03.783276  ==

 7497 16:52:03.786515  Dram Type= 6, Freq= 0, CH_0, rank 0

 7498 16:52:03.793039  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7499 16:52:03.793122  ==

 7500 16:52:03.796180  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7501 16:52:03.803206  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7502 16:52:03.806022  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7503 16:52:03.812589  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7504 16:52:03.821035  [CA 0] Center 44 (14~75) winsize 62

 7505 16:52:03.823835  [CA 1] Center 44 (14~74) winsize 61

 7506 16:52:03.827480  [CA 2] Center 39 (10~68) winsize 59

 7507 16:52:03.830754  [CA 3] Center 39 (10~68) winsize 59

 7508 16:52:03.833833  [CA 4] Center 37 (7~67) winsize 61

 7509 16:52:03.837649  [CA 5] Center 37 (7~67) winsize 61

 7510 16:52:03.837732  

 7511 16:52:03.840962  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7512 16:52:03.841045  

 7513 16:52:03.847322  [CATrainingPosCal] consider 1 rank data

 7514 16:52:03.847404  u2DelayCellTimex100 = 275/100 ps

 7515 16:52:03.853878  CA0 delay=44 (14~75),Diff = 7 PI (24 cell)

 7516 16:52:03.857663  CA1 delay=44 (14~74),Diff = 7 PI (24 cell)

 7517 16:52:03.860775  CA2 delay=39 (10~68),Diff = 2 PI (7 cell)

 7518 16:52:03.863842  CA3 delay=39 (10~68),Diff = 2 PI (7 cell)

 7519 16:52:03.867257  CA4 delay=37 (7~67),Diff = 0 PI (0 cell)

 7520 16:52:03.870222  CA5 delay=37 (7~67),Diff = 0 PI (0 cell)

 7521 16:52:03.870304  

 7522 16:52:03.873708  CA PerBit enable=1, Macro0, CA PI delay=37

 7523 16:52:03.873791  

 7524 16:52:03.876860  [CBTSetCACLKResult] CA Dly = 37

 7525 16:52:03.880357  CS Dly: 10 (0~41)

 7526 16:52:03.883827  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7527 16:52:03.887271  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7528 16:52:03.887353  ==

 7529 16:52:03.890454  Dram Type= 6, Freq= 0, CH_0, rank 1

 7530 16:52:03.897204  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7531 16:52:03.897288  ==

 7532 16:52:03.900730  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7533 16:52:03.907200  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7534 16:52:03.910317  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7535 16:52:03.917050  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7536 16:52:03.924821  [CA 0] Center 43 (13~74) winsize 62

 7537 16:52:03.927866  [CA 1] Center 43 (13~74) winsize 62

 7538 16:52:03.931091  [CA 2] Center 39 (10~69) winsize 60

 7539 16:52:03.934553  [CA 3] Center 38 (9~68) winsize 60

 7540 16:52:03.937938  [CA 4] Center 37 (7~67) winsize 61

 7541 16:52:03.941286  [CA 5] Center 37 (7~67) winsize 61

 7542 16:52:03.941367  

 7543 16:52:03.944367  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7544 16:52:03.944456  

 7545 16:52:03.947709  [CATrainingPosCal] consider 2 rank data

 7546 16:52:03.951124  u2DelayCellTimex100 = 275/100 ps

 7547 16:52:03.957810  CA0 delay=44 (14~74),Diff = 7 PI (24 cell)

 7548 16:52:03.960828  CA1 delay=44 (14~74),Diff = 7 PI (24 cell)

 7549 16:52:03.964497  CA2 delay=39 (10~68),Diff = 2 PI (7 cell)

 7550 16:52:03.967739  CA3 delay=39 (10~68),Diff = 2 PI (7 cell)

 7551 16:52:03.971329  CA4 delay=37 (7~67),Diff = 0 PI (0 cell)

 7552 16:52:03.974431  CA5 delay=37 (7~67),Diff = 0 PI (0 cell)

 7553 16:52:03.974512  

 7554 16:52:03.977693  CA PerBit enable=1, Macro0, CA PI delay=37

 7555 16:52:03.977773  

 7556 16:52:03.981175  [CBTSetCACLKResult] CA Dly = 37

 7557 16:52:03.984043  CS Dly: 11 (0~44)

 7558 16:52:03.987364  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7559 16:52:03.990913  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7560 16:52:03.990994  

 7561 16:52:03.994249  ----->DramcWriteLeveling(PI) begin...

 7562 16:52:03.994342  ==

 7563 16:52:03.997562  Dram Type= 6, Freq= 0, CH_0, rank 0

 7564 16:52:04.003869  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7565 16:52:04.003993  ==

 7566 16:52:04.007699  Write leveling (Byte 0): 32 => 32

 7567 16:52:04.010477  Write leveling (Byte 1): 27 => 27

 7568 16:52:04.010557  DramcWriteLeveling(PI) end<-----

 7569 16:52:04.010622  

 7570 16:52:04.013686  ==

 7571 16:52:04.017475  Dram Type= 6, Freq= 0, CH_0, rank 0

 7572 16:52:04.020557  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7573 16:52:04.020638  ==

 7574 16:52:04.023511  [Gating] SW mode calibration

 7575 16:52:04.030776  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7576 16:52:04.033637  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7577 16:52:04.040376   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7578 16:52:04.044271   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7579 16:52:04.047253   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7580 16:52:04.053828   1  4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7581 16:52:04.057037   1  4 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)

 7582 16:52:04.060389   1  4 20 | B1->B0 | 2323 3232 | 1 0 | (1 1) (0 0)

 7583 16:52:04.067152   1  4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 7584 16:52:04.070453   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7585 16:52:04.073680   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7586 16:52:04.080413   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7587 16:52:04.083407   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7588 16:52:04.086749   1  5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 7589 16:52:04.093524   1  5 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 7590 16:52:04.096791   1  5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)

 7591 16:52:04.100142   1  5 24 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)

 7592 16:52:04.107064   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7593 16:52:04.110319   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7594 16:52:04.113772   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7595 16:52:04.120083   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7596 16:52:04.123233   1  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7597 16:52:04.127291   1  6 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)

 7598 16:52:04.133313   1  6 20 | B1->B0 | 2727 4545 | 0 0 | (1 1) (0 0)

 7599 16:52:04.136493   1  6 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)

 7600 16:52:04.139843   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7601 16:52:04.143304   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7602 16:52:04.150003   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7603 16:52:04.153272   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7604 16:52:04.156408   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7605 16:52:04.163273   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7606 16:52:04.166672   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7607 16:52:04.170005   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7608 16:52:04.176646   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7609 16:52:04.179894   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7610 16:52:04.182881   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7611 16:52:04.190071   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7612 16:52:04.192761   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7613 16:52:04.196159   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7614 16:52:04.202912   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7615 16:52:04.206158   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7616 16:52:04.209840   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7617 16:52:04.216012   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7618 16:52:04.219315   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7619 16:52:04.222767   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7620 16:52:04.229329   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7621 16:52:04.232549   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7622 16:52:04.236046   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7623 16:52:04.239417  Total UI for P1: 0, mck2ui 16

 7624 16:52:04.242838  best dqsien dly found for B0: ( 1,  9, 16)

 7625 16:52:04.249315   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7626 16:52:04.252805   1  9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7627 16:52:04.255745  Total UI for P1: 0, mck2ui 16

 7628 16:52:04.259099  best dqsien dly found for B1: ( 1,  9, 22)

 7629 16:52:04.262636  best DQS0 dly(MCK, UI, PI) = (1, 9, 16)

 7630 16:52:04.266270  best DQS1 dly(MCK, UI, PI) = (1, 9, 22)

 7631 16:52:04.266352  

 7632 16:52:04.268925  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)

 7633 16:52:04.272453  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)

 7634 16:52:04.275910  [Gating] SW calibration Done

 7635 16:52:04.276027  ==

 7636 16:52:04.279408  Dram Type= 6, Freq= 0, CH_0, rank 0

 7637 16:52:04.282847  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7638 16:52:04.285746  ==

 7639 16:52:04.285827  RX Vref Scan: 0

 7640 16:52:04.285890  

 7641 16:52:04.289302  RX Vref 0 -> 0, step: 1

 7642 16:52:04.289383  

 7643 16:52:04.292560  RX Delay 0 -> 252, step: 8

 7644 16:52:04.295678  iDelay=200, Bit 0, Center 131 (80 ~ 183) 104

 7645 16:52:04.299141  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 7646 16:52:04.302167  iDelay=200, Bit 2, Center 127 (72 ~ 183) 112

 7647 16:52:04.305521  iDelay=200, Bit 3, Center 127 (72 ~ 183) 112

 7648 16:52:04.312945  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 7649 16:52:04.315729  iDelay=200, Bit 5, Center 119 (64 ~ 175) 112

 7650 16:52:04.318944  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 7651 16:52:04.322012  iDelay=200, Bit 7, Center 139 (88 ~ 191) 104

 7652 16:52:04.325576  iDelay=200, Bit 8, Center 111 (56 ~ 167) 112

 7653 16:52:04.332485  iDelay=200, Bit 9, Center 111 (56 ~ 167) 112

 7654 16:52:04.335713  iDelay=200, Bit 10, Center 119 (64 ~ 175) 112

 7655 16:52:04.338719  iDelay=200, Bit 11, Center 115 (64 ~ 167) 104

 7656 16:52:04.342154  iDelay=200, Bit 12, Center 131 (72 ~ 191) 120

 7657 16:52:04.345403  iDelay=200, Bit 13, Center 131 (80 ~ 183) 104

 7658 16:52:04.352507  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 7659 16:52:04.355902  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7660 16:52:04.356029  ==

 7661 16:52:04.359179  Dram Type= 6, Freq= 0, CH_0, rank 0

 7662 16:52:04.362108  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7663 16:52:04.362190  ==

 7664 16:52:04.365350  DQS Delay:

 7665 16:52:04.365430  DQS0 = 0, DQS1 = 0

 7666 16:52:04.365495  DQM Delay:

 7667 16:52:04.369051  DQM0 = 131, DQM1 = 123

 7668 16:52:04.369132  DQ Delay:

 7669 16:52:04.371994  DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127

 7670 16:52:04.375222  DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139

 7671 16:52:04.378786  DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115

 7672 16:52:04.385741  DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135

 7673 16:52:04.385823  

 7674 16:52:04.385887  

 7675 16:52:04.385948  ==

 7676 16:52:04.388899  Dram Type= 6, Freq= 0, CH_0, rank 0

 7677 16:52:04.392299  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7678 16:52:04.392380  ==

 7679 16:52:04.392444  

 7680 16:52:04.392503  

 7681 16:52:04.395501  	TX Vref Scan disable

 7682 16:52:04.395580   == TX Byte 0 ==

 7683 16:52:04.402132  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 7684 16:52:04.405403  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 7685 16:52:04.405484   == TX Byte 1 ==

 7686 16:52:04.412107  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 7687 16:52:04.415285  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7688 16:52:04.415366  ==

 7689 16:52:04.418445  Dram Type= 6, Freq= 0, CH_0, rank 0

 7690 16:52:04.421981  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7691 16:52:04.422062  ==

 7692 16:52:04.436416  

 7693 16:52:04.439598  TX Vref early break, caculate TX vref

 7694 16:52:04.443027  TX Vref=16, minBit 0, minWin=22, winSum=357

 7695 16:52:04.446483  TX Vref=18, minBit 1, minWin=22, winSum=370

 7696 16:52:04.450065  TX Vref=20, minBit 1, minWin=23, winSum=378

 7697 16:52:04.453384  TX Vref=22, minBit 4, minWin=23, winSum=392

 7698 16:52:04.456737  TX Vref=24, minBit 2, minWin=24, winSum=400

 7699 16:52:04.462892  TX Vref=26, minBit 12, minWin=24, winSum=410

 7700 16:52:04.466264  TX Vref=28, minBit 1, minWin=25, winSum=416

 7701 16:52:04.469599  TX Vref=30, minBit 0, minWin=25, winSum=419

 7702 16:52:04.473208  TX Vref=32, minBit 4, minWin=24, winSum=411

 7703 16:52:04.476707  TX Vref=34, minBit 4, minWin=23, winSum=397

 7704 16:52:04.482875  [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 30

 7705 16:52:04.482956  

 7706 16:52:04.486391  Final TX Range 0 Vref 30

 7707 16:52:04.486471  

 7708 16:52:04.486534  ==

 7709 16:52:04.489804  Dram Type= 6, Freq= 0, CH_0, rank 0

 7710 16:52:04.493185  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7711 16:52:04.493266  ==

 7712 16:52:04.493330  

 7713 16:52:04.493389  

 7714 16:52:04.496400  	TX Vref Scan disable

 7715 16:52:04.503061  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 7716 16:52:04.503157   == TX Byte 0 ==

 7717 16:52:04.506462  u2DelayCellOfst[0]=17 cells (5 PI)

 7718 16:52:04.509792  u2DelayCellOfst[1]=21 cells (6 PI)

 7719 16:52:04.512869  u2DelayCellOfst[2]=14 cells (4 PI)

 7720 16:52:04.516088  u2DelayCellOfst[3]=17 cells (5 PI)

 7721 16:52:04.519263  u2DelayCellOfst[4]=14 cells (4 PI)

 7722 16:52:04.522583  u2DelayCellOfst[5]=0 cells (0 PI)

 7723 16:52:04.525884  u2DelayCellOfst[6]=21 cells (6 PI)

 7724 16:52:04.529360  u2DelayCellOfst[7]=21 cells (6 PI)

 7725 16:52:04.532721  Update DQ  dly =987 (3 ,6, 27)  DQ  OEN =(3 ,3)

 7726 16:52:04.535839  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 7727 16:52:04.539697   == TX Byte 1 ==

 7728 16:52:04.542752  u2DelayCellOfst[8]=0 cells (0 PI)

 7729 16:52:04.542852  u2DelayCellOfst[9]=0 cells (0 PI)

 7730 16:52:04.546210  u2DelayCellOfst[10]=7 cells (2 PI)

 7731 16:52:04.549343  u2DelayCellOfst[11]=0 cells (0 PI)

 7732 16:52:04.552796  u2DelayCellOfst[12]=14 cells (4 PI)

 7733 16:52:04.556447  u2DelayCellOfst[13]=10 cells (3 PI)

 7734 16:52:04.559679  u2DelayCellOfst[14]=17 cells (5 PI)

 7735 16:52:04.562421  u2DelayCellOfst[15]=14 cells (4 PI)

 7736 16:52:04.566441  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 7737 16:52:04.572516  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7738 16:52:04.572590  DramC Write-DBI on

 7739 16:52:04.572653  ==

 7740 16:52:04.576062  Dram Type= 6, Freq= 0, CH_0, rank 0

 7741 16:52:04.582392  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7742 16:52:04.582475  ==

 7743 16:52:04.582540  

 7744 16:52:04.582603  

 7745 16:52:04.582665  	TX Vref Scan disable

 7746 16:52:04.586451   == TX Byte 0 ==

 7747 16:52:04.589291  Update DQM dly =733 (2 ,6, 29)  DQM OEN =(3 ,3)

 7748 16:52:04.592886   == TX Byte 1 ==

 7749 16:52:04.596132  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 7750 16:52:04.599339  DramC Write-DBI off

 7751 16:52:04.599421  

 7752 16:52:04.599487  [DATLAT]

 7753 16:52:04.599548  Freq=1600, CH0 RK0

 7754 16:52:04.599606  

 7755 16:52:04.602974  DATLAT Default: 0xf

 7756 16:52:04.603058  0, 0xFFFF, sum = 0

 7757 16:52:04.606395  1, 0xFFFF, sum = 0

 7758 16:52:04.609349  2, 0xFFFF, sum = 0

 7759 16:52:04.609432  3, 0xFFFF, sum = 0

 7760 16:52:04.612638  4, 0xFFFF, sum = 0

 7761 16:52:04.612749  5, 0xFFFF, sum = 0

 7762 16:52:04.615931  6, 0xFFFF, sum = 0

 7763 16:52:04.616051  7, 0xFFFF, sum = 0

 7764 16:52:04.619435  8, 0xFFFF, sum = 0

 7765 16:52:04.619507  9, 0xFFFF, sum = 0

 7766 16:52:04.622701  10, 0xFFFF, sum = 0

 7767 16:52:04.622775  11, 0xFFFF, sum = 0

 7768 16:52:04.625999  12, 0xFFFF, sum = 0

 7769 16:52:04.626069  13, 0xFFFF, sum = 0

 7770 16:52:04.629093  14, 0x0, sum = 1

 7771 16:52:04.629163  15, 0x0, sum = 2

 7772 16:52:04.632582  16, 0x0, sum = 3

 7773 16:52:04.632665  17, 0x0, sum = 4

 7774 16:52:04.635992  best_step = 15

 7775 16:52:04.636088  

 7776 16:52:04.636153  ==

 7777 16:52:04.639478  Dram Type= 6, Freq= 0, CH_0, rank 0

 7778 16:52:04.642724  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7779 16:52:04.642807  ==

 7780 16:52:04.646106  RX Vref Scan: 1

 7781 16:52:04.646188  

 7782 16:52:04.646253  Set Vref Range= 24 -> 127

 7783 16:52:04.646314  

 7784 16:52:04.649434  RX Vref 24 -> 127, step: 1

 7785 16:52:04.649516  

 7786 16:52:04.652692  RX Delay 11 -> 252, step: 4

 7787 16:52:04.652775  

 7788 16:52:04.655705  Set Vref, RX VrefLevel [Byte0]: 24

 7789 16:52:04.659364                           [Byte1]: 24

 7790 16:52:04.659446  

 7791 16:52:04.662611  Set Vref, RX VrefLevel [Byte0]: 25

 7792 16:52:04.665954                           [Byte1]: 25

 7793 16:52:04.666036  

 7794 16:52:04.669272  Set Vref, RX VrefLevel [Byte0]: 26

 7795 16:52:04.672651                           [Byte1]: 26

 7796 16:52:04.676584  

 7797 16:52:04.676665  Set Vref, RX VrefLevel [Byte0]: 27

 7798 16:52:04.679944                           [Byte1]: 27

 7799 16:52:04.684038  

 7800 16:52:04.684119  Set Vref, RX VrefLevel [Byte0]: 28

 7801 16:52:04.687500                           [Byte1]: 28

 7802 16:52:04.692152  

 7803 16:52:04.692232  Set Vref, RX VrefLevel [Byte0]: 29

 7804 16:52:04.694891                           [Byte1]: 29

 7805 16:52:04.699314  

 7806 16:52:04.699395  Set Vref, RX VrefLevel [Byte0]: 30

 7807 16:52:04.702633                           [Byte1]: 30

 7808 16:52:04.706938  

 7809 16:52:04.707020  Set Vref, RX VrefLevel [Byte0]: 31

 7810 16:52:04.710463                           [Byte1]: 31

 7811 16:52:04.714889  

 7812 16:52:04.714970  Set Vref, RX VrefLevel [Byte0]: 32

 7813 16:52:04.718053                           [Byte1]: 32

 7814 16:52:04.722356  

 7815 16:52:04.722438  Set Vref, RX VrefLevel [Byte0]: 33

 7816 16:52:04.725308                           [Byte1]: 33

 7817 16:52:04.730106  

 7818 16:52:04.730187  Set Vref, RX VrefLevel [Byte0]: 34

 7819 16:52:04.733733                           [Byte1]: 34

 7820 16:52:04.737515  

 7821 16:52:04.737596  Set Vref, RX VrefLevel [Byte0]: 35

 7822 16:52:04.740558                           [Byte1]: 35

 7823 16:52:04.744853  

 7824 16:52:04.744961  Set Vref, RX VrefLevel [Byte0]: 36

 7825 16:52:04.748131                           [Byte1]: 36

 7826 16:52:04.752551  

 7827 16:52:04.752632  Set Vref, RX VrefLevel [Byte0]: 37

 7828 16:52:04.756236                           [Byte1]: 37

 7829 16:52:04.760352  

 7830 16:52:04.760433  Set Vref, RX VrefLevel [Byte0]: 38

 7831 16:52:04.763917                           [Byte1]: 38

 7832 16:52:04.768064  

 7833 16:52:04.768145  Set Vref, RX VrefLevel [Byte0]: 39

 7834 16:52:04.771303                           [Byte1]: 39

 7835 16:52:04.775501  

 7836 16:52:04.775582  Set Vref, RX VrefLevel [Byte0]: 40

 7837 16:52:04.778885                           [Byte1]: 40

 7838 16:52:04.783005  

 7839 16:52:04.783086  Set Vref, RX VrefLevel [Byte0]: 41

 7840 16:52:04.786185                           [Byte1]: 41

 7841 16:52:04.790894  

 7842 16:52:04.790975  Set Vref, RX VrefLevel [Byte0]: 42

 7843 16:52:04.793923                           [Byte1]: 42

 7844 16:52:04.798745  

 7845 16:52:04.798828  Set Vref, RX VrefLevel [Byte0]: 43

 7846 16:52:04.802158                           [Byte1]: 43

 7847 16:52:04.805958  

 7848 16:52:04.806066  Set Vref, RX VrefLevel [Byte0]: 44

 7849 16:52:04.809417                           [Byte1]: 44

 7850 16:52:04.813697  

 7851 16:52:04.813771  Set Vref, RX VrefLevel [Byte0]: 45

 7852 16:52:04.816676                           [Byte1]: 45

 7853 16:52:04.821134  

 7854 16:52:04.821232  Set Vref, RX VrefLevel [Byte0]: 46

 7855 16:52:04.824792                           [Byte1]: 46

 7856 16:52:04.829377  

 7857 16:52:04.829478  Set Vref, RX VrefLevel [Byte0]: 47

 7858 16:52:04.831905                           [Byte1]: 47

 7859 16:52:04.836514  

 7860 16:52:04.836615  Set Vref, RX VrefLevel [Byte0]: 48

 7861 16:52:04.839924                           [Byte1]: 48

 7862 16:52:04.844300  

 7863 16:52:04.844409  Set Vref, RX VrefLevel [Byte0]: 49

 7864 16:52:04.847477                           [Byte1]: 49

 7865 16:52:04.851792  

 7866 16:52:04.851895  Set Vref, RX VrefLevel [Byte0]: 50

 7867 16:52:04.854993                           [Byte1]: 50

 7868 16:52:04.859236  

 7869 16:52:04.859318  Set Vref, RX VrefLevel [Byte0]: 51

 7870 16:52:04.863047                           [Byte1]: 51

 7871 16:52:04.866889  

 7872 16:52:04.866965  Set Vref, RX VrefLevel [Byte0]: 52

 7873 16:52:04.870521                           [Byte1]: 52

 7874 16:52:04.874277  

 7875 16:52:04.874347  Set Vref, RX VrefLevel [Byte0]: 53

 7876 16:52:04.877830                           [Byte1]: 53

 7877 16:52:04.881878  

 7878 16:52:04.881947  Set Vref, RX VrefLevel [Byte0]: 54

 7879 16:52:04.885150                           [Byte1]: 54

 7880 16:52:04.889831  

 7881 16:52:04.889901  Set Vref, RX VrefLevel [Byte0]: 55

 7882 16:52:04.893180                           [Byte1]: 55

 7883 16:52:04.897094  

 7884 16:52:04.897162  Set Vref, RX VrefLevel [Byte0]: 56

 7885 16:52:04.900530                           [Byte1]: 56

 7886 16:52:04.904986  

 7887 16:52:04.905124  Set Vref, RX VrefLevel [Byte0]: 57

 7888 16:52:04.908446                           [Byte1]: 57

 7889 16:52:04.912398  

 7890 16:52:04.912479  Set Vref, RX VrefLevel [Byte0]: 58

 7891 16:52:04.915921                           [Byte1]: 58

 7892 16:52:04.920430  

 7893 16:52:04.920514  Set Vref, RX VrefLevel [Byte0]: 59

 7894 16:52:04.923735                           [Byte1]: 59

 7895 16:52:04.927834  

 7896 16:52:04.927942  Set Vref, RX VrefLevel [Byte0]: 60

 7897 16:52:04.931009                           [Byte1]: 60

 7898 16:52:04.935407  

 7899 16:52:04.935515  Set Vref, RX VrefLevel [Byte0]: 61

 7900 16:52:04.938769                           [Byte1]: 61

 7901 16:52:04.943008  

 7902 16:52:04.943083  Set Vref, RX VrefLevel [Byte0]: 62

 7903 16:52:04.946202                           [Byte1]: 62

 7904 16:52:04.950769  

 7905 16:52:04.950844  Set Vref, RX VrefLevel [Byte0]: 63

 7906 16:52:04.954313                           [Byte1]: 63

 7907 16:52:04.958103  

 7908 16:52:04.958185  Set Vref, RX VrefLevel [Byte0]: 64

 7909 16:52:04.961489                           [Byte1]: 64

 7910 16:52:04.965698  

 7911 16:52:04.965805  Set Vref, RX VrefLevel [Byte0]: 65

 7912 16:52:04.969349                           [Byte1]: 65

 7913 16:52:04.973535  

 7914 16:52:04.973616  Set Vref, RX VrefLevel [Byte0]: 66

 7915 16:52:04.976736                           [Byte1]: 66

 7916 16:52:04.981063  

 7917 16:52:04.981145  Set Vref, RX VrefLevel [Byte0]: 67

 7918 16:52:04.984170                           [Byte1]: 67

 7919 16:52:04.988858  

 7920 16:52:04.988939  Set Vref, RX VrefLevel [Byte0]: 68

 7921 16:52:04.992351                           [Byte1]: 68

 7922 16:52:04.996257  

 7923 16:52:04.996338  Set Vref, RX VrefLevel [Byte0]: 69

 7924 16:52:04.999676                           [Byte1]: 69

 7925 16:52:05.003750  

 7926 16:52:05.003832  Set Vref, RX VrefLevel [Byte0]: 70

 7927 16:52:05.007250                           [Byte1]: 70

 7928 16:52:05.012164  

 7929 16:52:05.012246  Set Vref, RX VrefLevel [Byte0]: 71

 7930 16:52:05.014562                           [Byte1]: 71

 7931 16:52:05.018992  

 7932 16:52:05.019077  Set Vref, RX VrefLevel [Byte0]: 72

 7933 16:52:05.022136                           [Byte1]: 72

 7934 16:52:05.026935  

 7935 16:52:05.027036  Set Vref, RX VrefLevel [Byte0]: 73

 7936 16:52:05.029827                           [Byte1]: 73

 7937 16:52:05.034827  

 7938 16:52:05.034908  Set Vref, RX VrefLevel [Byte0]: 74

 7939 16:52:05.037835                           [Byte1]: 74

 7940 16:52:05.042105  

 7941 16:52:05.042189  Set Vref, RX VrefLevel [Byte0]: 75

 7942 16:52:05.045043                           [Byte1]: 75

 7943 16:52:05.049495  

 7944 16:52:05.049577  Set Vref, RX VrefLevel [Byte0]: 76

 7945 16:52:05.053679                           [Byte1]: 76

 7946 16:52:05.056926  

 7947 16:52:05.057007  Set Vref, RX VrefLevel [Byte0]: 77

 7948 16:52:05.060185                           [Byte1]: 77

 7949 16:52:05.064848  

 7950 16:52:05.064930  Final RX Vref Byte 0 = 58 to rank0

 7951 16:52:05.067888  Final RX Vref Byte 1 = 63 to rank0

 7952 16:52:05.071368  Final RX Vref Byte 0 = 58 to rank1

 7953 16:52:05.075188  Final RX Vref Byte 1 = 63 to rank1==

 7954 16:52:05.078307  Dram Type= 6, Freq= 0, CH_0, rank 0

 7955 16:52:05.085213  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7956 16:52:05.085296  ==

 7957 16:52:05.085362  DQS Delay:

 7958 16:52:05.085422  DQS0 = 0, DQS1 = 0

 7959 16:52:05.088049  DQM Delay:

 7960 16:52:05.088131  DQM0 = 129, DQM1 = 121

 7961 16:52:05.091465  DQ Delay:

 7962 16:52:05.094831  DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126

 7963 16:52:05.098300  DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138

 7964 16:52:05.101628  DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116

 7965 16:52:05.104577  DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132

 7966 16:52:05.104660  

 7967 16:52:05.104726  

 7968 16:52:05.104785  

 7969 16:52:05.107946  [DramC_TX_OE_Calibration] TA2

 7970 16:52:05.111153  Original DQ_B0 (3 6) =30, OEN = 27

 7971 16:52:05.114675  Original DQ_B1 (3 6) =30, OEN = 27

 7972 16:52:05.118024  24, 0x0, End_B0=24 End_B1=24

 7973 16:52:05.118108  25, 0x0, End_B0=25 End_B1=25

 7974 16:52:05.121252  26, 0x0, End_B0=26 End_B1=26

 7975 16:52:05.124532  27, 0x0, End_B0=27 End_B1=27

 7976 16:52:05.127930  28, 0x0, End_B0=28 End_B1=28

 7977 16:52:05.128049  29, 0x0, End_B0=29 End_B1=29

 7978 16:52:05.131362  30, 0x0, End_B0=30 End_B1=30

 7979 16:52:05.135173  31, 0x4141, End_B0=30 End_B1=30

 7980 16:52:05.138176  Byte0 end_step=30  best_step=27

 7981 16:52:05.140982  Byte1 end_step=30  best_step=27

 7982 16:52:05.144530  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7983 16:52:05.144612  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7984 16:52:05.147651  

 7985 16:52:05.147733  

 7986 16:52:05.154745  [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps

 7987 16:52:05.158042  CH0 RK0: MR19=303, MR18=1509

 7988 16:52:05.164619  CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15

 7989 16:52:05.164703  

 7990 16:52:05.167752  ----->DramcWriteLeveling(PI) begin...

 7991 16:52:05.167859  ==

 7992 16:52:05.170911  Dram Type= 6, Freq= 0, CH_0, rank 1

 7993 16:52:05.174434  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7994 16:52:05.174517  ==

 7995 16:52:05.177928  Write leveling (Byte 0): 35 => 35

 7996 16:52:05.181035  Write leveling (Byte 1): 24 => 24

 7997 16:52:05.183924  DramcWriteLeveling(PI) end<-----

 7998 16:52:05.184052  

 7999 16:52:05.184119  ==

 8000 16:52:05.187908  Dram Type= 6, Freq= 0, CH_0, rank 1

 8001 16:52:05.190904  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8002 16:52:05.190987  ==

 8003 16:52:05.194179  [Gating] SW mode calibration

 8004 16:52:05.201330  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8005 16:52:05.207611  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8006 16:52:05.211037   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8007 16:52:05.213950   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8008 16:52:05.220797   1  4  8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)

 8009 16:52:05.224076   1  4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)

 8010 16:52:05.227377   1  4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 8011 16:52:05.234466   1  4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)

 8012 16:52:05.237915   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8013 16:52:05.240886   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8014 16:52:05.247416   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8015 16:52:05.250675   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8016 16:52:05.253843   1  5  8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)

 8017 16:52:05.260389   1  5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)

 8018 16:52:05.263699   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)

 8019 16:52:05.267401   1  5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)

 8020 16:52:05.273825   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8021 16:52:05.276930   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8022 16:52:05.280881   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8023 16:52:05.286882   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8024 16:52:05.290481   1  6  8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)

 8025 16:52:05.294056   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 8026 16:52:05.300305   1  6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 8027 16:52:05.303757   1  6 20 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)

 8028 16:52:05.307322   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8029 16:52:05.313876   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8030 16:52:05.316782   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8031 16:52:05.320124   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8032 16:52:05.327089   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8033 16:52:05.330261   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8034 16:52:05.333446   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8035 16:52:05.340179   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8036 16:52:05.343745   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8037 16:52:05.346853   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8038 16:52:05.354150   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8039 16:52:05.357035   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8040 16:52:05.360361   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8041 16:52:05.363876   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8042 16:52:05.370116   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8043 16:52:05.374010   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8044 16:52:05.377129   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8045 16:52:05.383964   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8046 16:52:05.386925   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8047 16:52:05.389867   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8048 16:52:05.396729   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8049 16:52:05.400119   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 8050 16:52:05.403617  Total UI for P1: 0, mck2ui 16

 8051 16:52:05.406927  best dqsien dly found for B0: ( 1,  9,  6)

 8052 16:52:05.410468   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8053 16:52:05.416601   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8054 16:52:05.419945   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8055 16:52:05.423340   1  9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8056 16:52:05.426402  Total UI for P1: 0, mck2ui 16

 8057 16:52:05.430031  best dqsien dly found for B1: ( 1,  9, 20)

 8058 16:52:05.433021  best DQS0 dly(MCK, UI, PI) = (1, 9, 6)

 8059 16:52:05.436480  best DQS1 dly(MCK, UI, PI) = (1, 9, 20)

 8060 16:52:05.436561  

 8061 16:52:05.443433  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8062 16:52:05.446776  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)

 8063 16:52:05.446858  [Gating] SW calibration Done

 8064 16:52:05.449660  ==

 8065 16:52:05.452956  Dram Type= 6, Freq= 0, CH_0, rank 1

 8066 16:52:05.456521  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8067 16:52:05.456603  ==

 8068 16:52:05.456668  RX Vref Scan: 0

 8069 16:52:05.456729  

 8070 16:52:05.459870  RX Vref 0 -> 0, step: 1

 8071 16:52:05.460012  

 8072 16:52:05.463291  RX Delay 0 -> 252, step: 8

 8073 16:52:05.466588  iDelay=200, Bit 0, Center 131 (72 ~ 191) 120

 8074 16:52:05.470730  iDelay=200, Bit 1, Center 135 (80 ~ 191) 112

 8075 16:52:05.473556  iDelay=200, Bit 2, Center 131 (72 ~ 191) 120

 8076 16:52:05.480001  iDelay=200, Bit 3, Center 131 (72 ~ 191) 120

 8077 16:52:05.482892  iDelay=200, Bit 4, Center 131 (72 ~ 191) 120

 8078 16:52:05.486393  iDelay=200, Bit 5, Center 119 (64 ~ 175) 112

 8079 16:52:05.490052  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8080 16:52:05.493558  iDelay=200, Bit 7, Center 139 (80 ~ 199) 120

 8081 16:52:05.499717  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 8082 16:52:05.502851  iDelay=200, Bit 9, Center 115 (56 ~ 175) 120

 8083 16:52:05.506363  iDelay=200, Bit 10, Center 123 (64 ~ 183) 120

 8084 16:52:05.509627  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8085 16:52:05.512707  iDelay=200, Bit 12, Center 127 (72 ~ 183) 112

 8086 16:52:05.519993  iDelay=200, Bit 13, Center 131 (72 ~ 191) 120

 8087 16:52:05.522916  iDelay=200, Bit 14, Center 131 (72 ~ 191) 120

 8088 16:52:05.526275  iDelay=200, Bit 15, Center 131 (72 ~ 191) 120

 8089 16:52:05.526356  ==

 8090 16:52:05.529762  Dram Type= 6, Freq= 0, CH_0, rank 1

 8091 16:52:05.533109  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8092 16:52:05.536464  ==

 8093 16:52:05.536545  DQS Delay:

 8094 16:52:05.536609  DQS0 = 0, DQS1 = 0

 8095 16:52:05.539274  DQM Delay:

 8096 16:52:05.539355  DQM0 = 132, DQM1 = 124

 8097 16:52:05.543407  DQ Delay:

 8098 16:52:05.545940  DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =131

 8099 16:52:05.549242  DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139

 8100 16:52:05.552656  DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119

 8101 16:52:05.556142  DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131

 8102 16:52:05.556223  

 8103 16:52:05.556292  

 8104 16:52:05.556352  ==

 8105 16:52:05.559386  Dram Type= 6, Freq= 0, CH_0, rank 1

 8106 16:52:05.562680  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8107 16:52:05.562762  ==

 8108 16:52:05.562827  

 8109 16:52:05.566224  

 8110 16:52:05.566304  	TX Vref Scan disable

 8111 16:52:05.569248   == TX Byte 0 ==

 8112 16:52:05.572907  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 8113 16:52:05.575791  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8114 16:52:05.579427   == TX Byte 1 ==

 8115 16:52:05.583003  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8116 16:52:05.586437  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8117 16:52:05.586519  ==

 8118 16:52:05.589580  Dram Type= 6, Freq= 0, CH_0, rank 1

 8119 16:52:05.596132  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8120 16:52:05.596214  ==

 8121 16:52:05.610303  

 8122 16:52:05.613699  TX Vref early break, caculate TX vref

 8123 16:52:05.616509  TX Vref=16, minBit 8, minWin=22, winSum=377

 8124 16:52:05.619837  TX Vref=18, minBit 9, minWin=22, winSum=387

 8125 16:52:05.623816  TX Vref=20, minBit 5, minWin=24, winSum=395

 8126 16:52:05.626697  TX Vref=22, minBit 8, minWin=24, winSum=406

 8127 16:52:05.629960  TX Vref=24, minBit 9, minWin=24, winSum=409

 8128 16:52:05.636990  TX Vref=26, minBit 9, minWin=25, winSum=416

 8129 16:52:05.639877  TX Vref=28, minBit 10, minWin=25, winSum=424

 8130 16:52:05.643367  TX Vref=30, minBit 13, minWin=25, winSum=422

 8131 16:52:05.646662  TX Vref=32, minBit 4, minWin=25, winSum=414

 8132 16:52:05.649871  TX Vref=34, minBit 0, minWin=25, winSum=407

 8133 16:52:05.653262  TX Vref=36, minBit 4, minWin=24, winSum=399

 8134 16:52:05.659773  [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 28

 8135 16:52:05.659855  

 8136 16:52:05.663533  Final TX Range 0 Vref 28

 8137 16:52:05.663615  

 8138 16:52:05.663679  ==

 8139 16:52:05.666678  Dram Type= 6, Freq= 0, CH_0, rank 1

 8140 16:52:05.670041  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8141 16:52:05.670123  ==

 8142 16:52:05.672978  

 8143 16:52:05.673059  

 8144 16:52:05.673123  	TX Vref Scan disable

 8145 16:52:05.680244  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8146 16:52:05.680326   == TX Byte 0 ==

 8147 16:52:05.682851  u2DelayCellOfst[0]=14 cells (4 PI)

 8148 16:52:05.686415  u2DelayCellOfst[1]=21 cells (6 PI)

 8149 16:52:05.690132  u2DelayCellOfst[2]=10 cells (3 PI)

 8150 16:52:05.693391  u2DelayCellOfst[3]=14 cells (4 PI)

 8151 16:52:05.696457  u2DelayCellOfst[4]=10 cells (3 PI)

 8152 16:52:05.699845  u2DelayCellOfst[5]=0 cells (0 PI)

 8153 16:52:05.703111  u2DelayCellOfst[6]=21 cells (6 PI)

 8154 16:52:05.706240  u2DelayCellOfst[7]=21 cells (6 PI)

 8155 16:52:05.709617  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 8156 16:52:05.712708  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8157 16:52:05.716200   == TX Byte 1 ==

 8158 16:52:05.719682  u2DelayCellOfst[8]=0 cells (0 PI)

 8159 16:52:05.723105  u2DelayCellOfst[9]=0 cells (0 PI)

 8160 16:52:05.726017  u2DelayCellOfst[10]=10 cells (3 PI)

 8161 16:52:05.729405  u2DelayCellOfst[11]=7 cells (2 PI)

 8162 16:52:05.732876  u2DelayCellOfst[12]=14 cells (4 PI)

 8163 16:52:05.736360  u2DelayCellOfst[13]=14 cells (4 PI)

 8164 16:52:05.736441  u2DelayCellOfst[14]=17 cells (5 PI)

 8165 16:52:05.739625  u2DelayCellOfst[15]=14 cells (4 PI)

 8166 16:52:05.746304  Update DQ  dly =977 (3 ,6, 17)  DQ  OEN =(3 ,3)

 8167 16:52:05.749326  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8168 16:52:05.752906  DramC Write-DBI on

 8169 16:52:05.752987  ==

 8170 16:52:05.755819  Dram Type= 6, Freq= 0, CH_0, rank 1

 8171 16:52:05.759113  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8172 16:52:05.759195  ==

 8173 16:52:05.759260  

 8174 16:52:05.759319  

 8175 16:52:05.762567  	TX Vref Scan disable

 8176 16:52:05.762648   == TX Byte 0 ==

 8177 16:52:05.769096  Update DQM dly =736 (2 ,6, 32)  DQM OEN =(3 ,3)

 8178 16:52:05.769177   == TX Byte 1 ==

 8179 16:52:05.772411  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8180 16:52:05.776362  DramC Write-DBI off

 8181 16:52:05.776443  

 8182 16:52:05.776507  [DATLAT]

 8183 16:52:05.779309  Freq=1600, CH0 RK1

 8184 16:52:05.779390  

 8185 16:52:05.779455  DATLAT Default: 0xf

 8186 16:52:05.782919  0, 0xFFFF, sum = 0

 8187 16:52:05.783002  1, 0xFFFF, sum = 0

 8188 16:52:05.786315  2, 0xFFFF, sum = 0

 8189 16:52:05.786397  3, 0xFFFF, sum = 0

 8190 16:52:05.789032  4, 0xFFFF, sum = 0

 8191 16:52:05.789115  5, 0xFFFF, sum = 0

 8192 16:52:05.792512  6, 0xFFFF, sum = 0

 8193 16:52:05.796178  7, 0xFFFF, sum = 0

 8194 16:52:05.796260  8, 0xFFFF, sum = 0

 8195 16:52:05.799085  9, 0xFFFF, sum = 0

 8196 16:52:05.799168  10, 0xFFFF, sum = 0

 8197 16:52:05.802685  11, 0xFFFF, sum = 0

 8198 16:52:05.802773  12, 0xFFFF, sum = 0

 8199 16:52:05.805788  13, 0xFFFF, sum = 0

 8200 16:52:05.805871  14, 0x0, sum = 1

 8201 16:52:05.809347  15, 0x0, sum = 2

 8202 16:52:05.809429  16, 0x0, sum = 3

 8203 16:52:05.812512  17, 0x0, sum = 4

 8204 16:52:05.812595  best_step = 15

 8205 16:52:05.812660  

 8206 16:52:05.812719  ==

 8207 16:52:05.815773  Dram Type= 6, Freq= 0, CH_0, rank 1

 8208 16:52:05.818971  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8209 16:52:05.822557  ==

 8210 16:52:05.822638  RX Vref Scan: 0

 8211 16:52:05.822701  

 8212 16:52:05.825595  RX Vref 0 -> 0, step: 1

 8213 16:52:05.825676  

 8214 16:52:05.825740  RX Delay 11 -> 252, step: 4

 8215 16:52:05.833185  iDelay=191, Bit 0, Center 126 (71 ~ 182) 112

 8216 16:52:05.836594  iDelay=191, Bit 1, Center 130 (75 ~ 186) 112

 8217 16:52:05.839365  iDelay=191, Bit 2, Center 122 (67 ~ 178) 112

 8218 16:52:05.842800  iDelay=191, Bit 3, Center 126 (71 ~ 182) 112

 8219 16:52:05.849255  iDelay=191, Bit 4, Center 126 (71 ~ 182) 112

 8220 16:52:05.852959  iDelay=191, Bit 5, Center 116 (63 ~ 170) 108

 8221 16:52:05.856121  iDelay=191, Bit 6, Center 134 (79 ~ 190) 112

 8222 16:52:05.859308  iDelay=191, Bit 7, Center 136 (83 ~ 190) 108

 8223 16:52:05.862821  iDelay=191, Bit 8, Center 112 (59 ~ 166) 108

 8224 16:52:05.869568  iDelay=191, Bit 9, Center 110 (55 ~ 166) 112

 8225 16:52:05.872656  iDelay=191, Bit 10, Center 122 (67 ~ 178) 112

 8226 16:52:05.875712  iDelay=191, Bit 11, Center 116 (63 ~ 170) 108

 8227 16:52:05.878908  iDelay=191, Bit 12, Center 126 (75 ~ 178) 104

 8228 16:52:05.882594  iDelay=191, Bit 13, Center 126 (71 ~ 182) 112

 8229 16:52:05.888965  iDelay=191, Bit 14, Center 134 (79 ~ 190) 112

 8230 16:52:05.892154  iDelay=191, Bit 15, Center 130 (75 ~ 186) 112

 8231 16:52:05.892235  ==

 8232 16:52:05.895576  Dram Type= 6, Freq= 0, CH_0, rank 1

 8233 16:52:05.898572  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8234 16:52:05.898654  ==

 8235 16:52:05.901936  DQS Delay:

 8236 16:52:05.902017  DQS0 = 0, DQS1 = 0

 8237 16:52:05.902082  DQM Delay:

 8238 16:52:05.905684  DQM0 = 127, DQM1 = 122

 8239 16:52:05.905766  DQ Delay:

 8240 16:52:05.908895  DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126

 8241 16:52:05.915175  DQ4 =126, DQ5 =116, DQ6 =134, DQ7 =136

 8242 16:52:05.918707  DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116

 8243 16:52:05.922000  DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130

 8244 16:52:05.922081  

 8245 16:52:05.922145  

 8246 16:52:05.922203  

 8247 16:52:05.925074  [DramC_TX_OE_Calibration] TA2

 8248 16:52:05.928570  Original DQ_B0 (3 6) =30, OEN = 27

 8249 16:52:05.931936  Original DQ_B1 (3 6) =30, OEN = 27

 8250 16:52:05.932055  24, 0x0, End_B0=24 End_B1=24

 8251 16:52:05.935292  25, 0x0, End_B0=25 End_B1=25

 8252 16:52:05.938881  26, 0x0, End_B0=26 End_B1=26

 8253 16:52:05.942193  27, 0x0, End_B0=27 End_B1=27

 8254 16:52:05.942275  28, 0x0, End_B0=28 End_B1=28

 8255 16:52:05.945024  29, 0x0, End_B0=29 End_B1=29

 8256 16:52:05.948317  30, 0x0, End_B0=30 End_B1=30

 8257 16:52:05.951927  31, 0x4141, End_B0=30 End_B1=30

 8258 16:52:05.955400  Byte0 end_step=30  best_step=27

 8259 16:52:05.958924  Byte1 end_step=30  best_step=27

 8260 16:52:05.959004  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8261 16:52:05.961509  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8262 16:52:05.961590  

 8263 16:52:05.961652  

 8264 16:52:05.971576  [DQSOSCAuto] RK1, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps

 8265 16:52:05.975135  CH0 RK1: MR19=303, MR18=1509

 8266 16:52:05.978071  CH0_RK1: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15

 8267 16:52:05.981914  [RxdqsGatingPostProcess] freq 1600

 8268 16:52:05.988528  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8269 16:52:05.991400  best DQS0 dly(2T, 0.5T) = (1, 1)

 8270 16:52:05.994892  best DQS1 dly(2T, 0.5T) = (1, 1)

 8271 16:52:05.998380  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8272 16:52:06.001971  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8273 16:52:06.005340  best DQS0 dly(2T, 0.5T) = (1, 1)

 8274 16:52:06.005421  best DQS1 dly(2T, 0.5T) = (1, 1)

 8275 16:52:06.007947  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8276 16:52:06.012015  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8277 16:52:06.014897  Pre-setting of DQS Precalculation

 8278 16:52:06.021261  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8279 16:52:06.021343  ==

 8280 16:52:06.025010  Dram Type= 6, Freq= 0, CH_1, rank 0

 8281 16:52:06.028318  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8282 16:52:06.028400  ==

 8283 16:52:06.034894  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8284 16:52:06.038442  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8285 16:52:06.041275  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8286 16:52:06.047449  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8287 16:52:06.057512  [CA 0] Center 43 (15~72) winsize 58

 8288 16:52:06.060357  [CA 1] Center 43 (14~72) winsize 59

 8289 16:52:06.063699  [CA 2] Center 38 (10~67) winsize 58

 8290 16:52:06.067557  [CA 3] Center 37 (8~67) winsize 60

 8291 16:52:06.070597  [CA 4] Center 38 (9~68) winsize 60

 8292 16:52:06.074017  [CA 5] Center 37 (8~66) winsize 59

 8293 16:52:06.074096  

 8294 16:52:06.077553  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8295 16:52:06.077633  

 8296 16:52:06.080236  [CATrainingPosCal] consider 1 rank data

 8297 16:52:06.084120  u2DelayCellTimex100 = 275/100 ps

 8298 16:52:06.090394  CA0 delay=43 (15~72),Diff = 6 PI (21 cell)

 8299 16:52:06.093812  CA1 delay=43 (14~72),Diff = 6 PI (21 cell)

 8300 16:52:06.097106  CA2 delay=38 (10~67),Diff = 1 PI (3 cell)

 8301 16:52:06.100472  CA3 delay=37 (8~67),Diff = 0 PI (0 cell)

 8302 16:52:06.104271  CA4 delay=38 (9~68),Diff = 1 PI (3 cell)

 8303 16:52:06.107024  CA5 delay=37 (8~66),Diff = 0 PI (0 cell)

 8304 16:52:06.107104  

 8305 16:52:06.110574  CA PerBit enable=1, Macro0, CA PI delay=37

 8306 16:52:06.110653  

 8307 16:52:06.113829  [CBTSetCACLKResult] CA Dly = 37

 8308 16:52:06.116748  CS Dly: 8 (0~39)

 8309 16:52:06.120027  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8310 16:52:06.123418  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8311 16:52:06.123497  ==

 8312 16:52:06.126837  Dram Type= 6, Freq= 0, CH_1, rank 1

 8313 16:52:06.130202  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8314 16:52:06.133230  ==

 8315 16:52:06.137025  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8316 16:52:06.140279  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8317 16:52:06.146352  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8318 16:52:06.152991  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8319 16:52:06.160483  [CA 0] Center 43 (14~72) winsize 59

 8320 16:52:06.163691  [CA 1] Center 43 (14~72) winsize 59

 8321 16:52:06.167299  [CA 2] Center 38 (10~67) winsize 58

 8322 16:52:06.170257  [CA 3] Center 37 (8~67) winsize 60

 8323 16:52:06.173974  [CA 4] Center 38 (9~68) winsize 60

 8324 16:52:06.177305  [CA 5] Center 36 (7~66) winsize 60

 8325 16:52:06.177384  

 8326 16:52:06.180239  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8327 16:52:06.180318  

 8328 16:52:06.183592  [CATrainingPosCal] consider 2 rank data

 8329 16:52:06.186998  u2DelayCellTimex100 = 275/100 ps

 8330 16:52:06.190246  CA0 delay=43 (15~72),Diff = 6 PI (21 cell)

 8331 16:52:06.196940  CA1 delay=43 (14~72),Diff = 6 PI (21 cell)

 8332 16:52:06.200394  CA2 delay=38 (10~67),Diff = 1 PI (3 cell)

 8333 16:52:06.203588  CA3 delay=37 (8~67),Diff = 0 PI (0 cell)

 8334 16:52:06.207207  CA4 delay=38 (9~68),Diff = 1 PI (3 cell)

 8335 16:52:06.210302  CA5 delay=37 (8~66),Diff = 0 PI (0 cell)

 8336 16:52:06.210383  

 8337 16:52:06.214048  CA PerBit enable=1, Macro0, CA PI delay=37

 8338 16:52:06.214130  

 8339 16:52:06.217056  [CBTSetCACLKResult] CA Dly = 37

 8340 16:52:06.220422  CS Dly: 10 (0~44)

 8341 16:52:06.223439  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8342 16:52:06.226795  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8343 16:52:06.226877  

 8344 16:52:06.229966  ----->DramcWriteLeveling(PI) begin...

 8345 16:52:06.230049  ==

 8346 16:52:06.233983  Dram Type= 6, Freq= 0, CH_1, rank 0

 8347 16:52:06.239839  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8348 16:52:06.239959  ==

 8349 16:52:06.243288  Write leveling (Byte 0): 24 => 24

 8350 16:52:06.243366  Write leveling (Byte 1): 28 => 28

 8351 16:52:06.246614  DramcWriteLeveling(PI) end<-----

 8352 16:52:06.246689  

 8353 16:52:06.246750  ==

 8354 16:52:06.250016  Dram Type= 6, Freq= 0, CH_1, rank 0

 8355 16:52:06.257082  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8356 16:52:06.257164  ==

 8357 16:52:06.259770  [Gating] SW mode calibration

 8358 16:52:06.266654  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8359 16:52:06.269990  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8360 16:52:06.276403   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8361 16:52:06.280293   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8362 16:52:06.283076   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8363 16:52:06.290080   1  4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8364 16:52:06.293052   1  4 16 | B1->B0 | 2b2b 2626 | 1 0 | (1 1) (0 0)

 8365 16:52:06.296623   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8366 16:52:06.302993   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8367 16:52:06.306380   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8368 16:52:06.310021   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8369 16:52:06.316390   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8370 16:52:06.319523   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8371 16:52:06.323082   1  5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8372 16:52:06.329340   1  5 16 | B1->B0 | 3232 3434 | 0 0 | (0 1) (0 1)

 8373 16:52:06.332658   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8374 16:52:06.336164   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8375 16:52:06.342537   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8376 16:52:06.346262   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8377 16:52:06.349606   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8378 16:52:06.356124   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8379 16:52:06.359164   1  6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 8380 16:52:06.362796   1  6 16 | B1->B0 | 4040 3636 | 0 0 | (0 0) (0 0)

 8381 16:52:06.369640   1  6 20 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)

 8382 16:52:06.372472   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8383 16:52:06.375733   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8384 16:52:06.379444   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8385 16:52:06.385952   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8386 16:52:06.389245   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8387 16:52:06.392573   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8388 16:52:06.399282   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8389 16:52:06.402492   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8390 16:52:06.406199   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8391 16:52:06.412331   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8392 16:52:06.415700   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8393 16:52:06.418961   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8394 16:52:06.425902   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8395 16:52:06.429172   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8396 16:52:06.432741   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8397 16:52:06.439072   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8398 16:52:06.442812   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8399 16:52:06.445786   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8400 16:52:06.452306   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8401 16:52:06.455610   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8402 16:52:06.458829   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8403 16:52:06.466239   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8404 16:52:06.469277   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8405 16:52:06.472162   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8406 16:52:06.475400  Total UI for P1: 0, mck2ui 16

 8407 16:52:06.478869  best dqsien dly found for B0: ( 1,  9, 16)

 8408 16:52:06.482529  Total UI for P1: 0, mck2ui 16

 8409 16:52:06.485355  best dqsien dly found for B1: ( 1,  9, 16)

 8410 16:52:06.488645  best DQS0 dly(MCK, UI, PI) = (1, 9, 16)

 8411 16:52:06.492300  best DQS1 dly(MCK, UI, PI) = (1, 9, 16)

 8412 16:52:06.492382  

 8413 16:52:06.499307  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)

 8414 16:52:06.502055  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)

 8415 16:52:06.502136  [Gating] SW calibration Done

 8416 16:52:06.505374  ==

 8417 16:52:06.508879  Dram Type= 6, Freq= 0, CH_1, rank 0

 8418 16:52:06.512146  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8419 16:52:06.512228  ==

 8420 16:52:06.512293  RX Vref Scan: 0

 8421 16:52:06.512352  

 8422 16:52:06.515483  RX Vref 0 -> 0, step: 1

 8423 16:52:06.515564  

 8424 16:52:06.519045  RX Delay 0 -> 252, step: 8

 8425 16:52:06.522154  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8426 16:52:06.525460  iDelay=208, Bit 1, Center 131 (80 ~ 183) 104

 8427 16:52:06.528455  iDelay=208, Bit 2, Center 123 (72 ~ 175) 104

 8428 16:52:06.535374  iDelay=208, Bit 3, Center 135 (80 ~ 191) 112

 8429 16:52:06.538864  iDelay=208, Bit 4, Center 135 (80 ~ 191) 112

 8430 16:52:06.541842  iDelay=208, Bit 5, Center 147 (88 ~ 207) 120

 8431 16:52:06.545027  iDelay=208, Bit 6, Center 143 (96 ~ 191) 96

 8432 16:52:06.548644  iDelay=208, Bit 7, Center 131 (80 ~ 183) 104

 8433 16:52:06.555464  iDelay=208, Bit 8, Center 111 (56 ~ 167) 112

 8434 16:52:06.558776  iDelay=208, Bit 9, Center 115 (64 ~ 167) 104

 8435 16:52:06.561720  iDelay=208, Bit 10, Center 127 (72 ~ 183) 112

 8436 16:52:06.565025  iDelay=208, Bit 11, Center 123 (72 ~ 175) 104

 8437 16:52:06.568358  iDelay=208, Bit 12, Center 135 (80 ~ 191) 112

 8438 16:52:06.575195  iDelay=208, Bit 13, Center 131 (72 ~ 191) 120

 8439 16:52:06.578713  iDelay=208, Bit 14, Center 135 (80 ~ 191) 112

 8440 16:52:06.581505  iDelay=208, Bit 15, Center 131 (80 ~ 183) 104

 8441 16:52:06.581587  ==

 8442 16:52:06.585009  Dram Type= 6, Freq= 0, CH_1, rank 0

 8443 16:52:06.588256  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8444 16:52:06.591202  ==

 8445 16:52:06.591283  DQS Delay:

 8446 16:52:06.591347  DQS0 = 0, DQS1 = 0

 8447 16:52:06.594610  DQM Delay:

 8448 16:52:06.594691  DQM0 = 135, DQM1 = 126

 8449 16:52:06.598746  DQ Delay:

 8450 16:52:06.601680  DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135

 8451 16:52:06.605080  DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131

 8452 16:52:06.608435  DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123

 8453 16:52:06.611378  DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131

 8454 16:52:06.611459  

 8455 16:52:06.611523  

 8456 16:52:06.611582  ==

 8457 16:52:06.615027  Dram Type= 6, Freq= 0, CH_1, rank 0

 8458 16:52:06.618381  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8459 16:52:06.618463  ==

 8460 16:52:06.618528  

 8461 16:52:06.621092  

 8462 16:52:06.621173  	TX Vref Scan disable

 8463 16:52:06.624477   == TX Byte 0 ==

 8464 16:52:06.627824  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8465 16:52:06.631262  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8466 16:52:06.634652   == TX Byte 1 ==

 8467 16:52:06.637671  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8468 16:52:06.641105  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8469 16:52:06.641186  ==

 8470 16:52:06.644913  Dram Type= 6, Freq= 0, CH_1, rank 0

 8471 16:52:06.651334  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8472 16:52:06.651415  ==

 8473 16:52:06.663973  

 8474 16:52:06.667326  TX Vref early break, caculate TX vref

 8475 16:52:06.670777  TX Vref=16, minBit 9, minWin=20, winSum=364

 8476 16:52:06.674228  TX Vref=18, minBit 8, minWin=21, winSum=372

 8477 16:52:06.677125  TX Vref=20, minBit 8, minWin=21, winSum=380

 8478 16:52:06.680768  TX Vref=22, minBit 8, minWin=23, winSum=396

 8479 16:52:06.684168  TX Vref=24, minBit 8, minWin=23, winSum=403

 8480 16:52:06.690351  TX Vref=26, minBit 8, minWin=24, winSum=413

 8481 16:52:06.694212  TX Vref=28, minBit 0, minWin=25, winSum=415

 8482 16:52:06.697236  TX Vref=30, minBit 0, minWin=25, winSum=415

 8483 16:52:06.700267  TX Vref=32, minBit 1, minWin=25, winSum=413

 8484 16:52:06.703975  TX Vref=34, minBit 8, minWin=23, winSum=398

 8485 16:52:06.706966  TX Vref=36, minBit 15, minWin=22, winSum=388

 8486 16:52:06.713556  [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28

 8487 16:52:06.713637  

 8488 16:52:06.716978  Final TX Range 0 Vref 28

 8489 16:52:06.717058  

 8490 16:52:06.717122  ==

 8491 16:52:06.720119  Dram Type= 6, Freq= 0, CH_1, rank 0

 8492 16:52:06.723916  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8493 16:52:06.724076  ==

 8494 16:52:06.724169  

 8495 16:52:06.726813  

 8496 16:52:06.726909  	TX Vref Scan disable

 8497 16:52:06.733772  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8498 16:52:06.733853   == TX Byte 0 ==

 8499 16:52:06.737000  u2DelayCellOfst[0]=17 cells (5 PI)

 8500 16:52:06.740384  u2DelayCellOfst[1]=10 cells (3 PI)

 8501 16:52:06.743883  u2DelayCellOfst[2]=0 cells (0 PI)

 8502 16:52:06.746926  u2DelayCellOfst[3]=7 cells (2 PI)

 8503 16:52:06.750439  u2DelayCellOfst[4]=7 cells (2 PI)

 8504 16:52:06.753713  u2DelayCellOfst[5]=17 cells (5 PI)

 8505 16:52:06.756730  u2DelayCellOfst[6]=17 cells (5 PI)

 8506 16:52:06.759915  u2DelayCellOfst[7]=7 cells (2 PI)

 8507 16:52:06.763547  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8508 16:52:06.766516  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8509 16:52:06.769816   == TX Byte 1 ==

 8510 16:52:06.773114  u2DelayCellOfst[8]=0 cells (0 PI)

 8511 16:52:06.776564  u2DelayCellOfst[9]=3 cells (1 PI)

 8512 16:52:06.779681  u2DelayCellOfst[10]=10 cells (3 PI)

 8513 16:52:06.779761  u2DelayCellOfst[11]=7 cells (2 PI)

 8514 16:52:06.783386  u2DelayCellOfst[12]=14 cells (4 PI)

 8515 16:52:06.786468  u2DelayCellOfst[13]=17 cells (5 PI)

 8516 16:52:06.790289  u2DelayCellOfst[14]=17 cells (5 PI)

 8517 16:52:06.793482  u2DelayCellOfst[15]=14 cells (4 PI)

 8518 16:52:06.799892  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8519 16:52:06.802996  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8520 16:52:06.803099  DramC Write-DBI on

 8521 16:52:06.806639  ==

 8522 16:52:06.806720  Dram Type= 6, Freq= 0, CH_1, rank 0

 8523 16:52:06.812996  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8524 16:52:06.813078  ==

 8525 16:52:06.813142  

 8526 16:52:06.813200  

 8527 16:52:06.816439  	TX Vref Scan disable

 8528 16:52:06.816520   == TX Byte 0 ==

 8529 16:52:06.822702  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8530 16:52:06.822783   == TX Byte 1 ==

 8531 16:52:06.826232  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8532 16:52:06.829744  DramC Write-DBI off

 8533 16:52:06.829824  

 8534 16:52:06.829887  [DATLAT]

 8535 16:52:06.832690  Freq=1600, CH1 RK0

 8536 16:52:06.832771  

 8537 16:52:06.832835  DATLAT Default: 0xf

 8538 16:52:06.836167  0, 0xFFFF, sum = 0

 8539 16:52:06.836257  1, 0xFFFF, sum = 0

 8540 16:52:06.839472  2, 0xFFFF, sum = 0

 8541 16:52:06.839554  3, 0xFFFF, sum = 0

 8542 16:52:06.842949  4, 0xFFFF, sum = 0

 8543 16:52:06.843031  5, 0xFFFF, sum = 0

 8544 16:52:06.846372  6, 0xFFFF, sum = 0

 8545 16:52:06.846453  7, 0xFFFF, sum = 0

 8546 16:52:06.849704  8, 0xFFFF, sum = 0

 8547 16:52:06.849786  9, 0xFFFF, sum = 0

 8548 16:52:06.852975  10, 0xFFFF, sum = 0

 8549 16:52:06.856103  11, 0xFFFF, sum = 0

 8550 16:52:06.856186  12, 0xFFFF, sum = 0

 8551 16:52:06.859263  13, 0xFFFF, sum = 0

 8552 16:52:06.859344  14, 0x0, sum = 1

 8553 16:52:06.862652  15, 0x0, sum = 2

 8554 16:52:06.862734  16, 0x0, sum = 3

 8555 16:52:06.866144  17, 0x0, sum = 4

 8556 16:52:06.866226  best_step = 15

 8557 16:52:06.866291  

 8558 16:52:06.866348  ==

 8559 16:52:06.869962  Dram Type= 6, Freq= 0, CH_1, rank 0

 8560 16:52:06.873329  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8561 16:52:06.873410  ==

 8562 16:52:06.875832  RX Vref Scan: 1

 8563 16:52:06.875937  

 8564 16:52:06.879298  Set Vref Range= 24 -> 127

 8565 16:52:06.879378  

 8566 16:52:06.879442  RX Vref 24 -> 127, step: 1

 8567 16:52:06.879502  

 8568 16:52:06.882326  RX Delay 11 -> 252, step: 4

 8569 16:52:06.882406  

 8570 16:52:06.886148  Set Vref, RX VrefLevel [Byte0]: 24

 8571 16:52:06.889279                           [Byte1]: 24

 8572 16:52:06.892335  

 8573 16:52:06.892416  Set Vref, RX VrefLevel [Byte0]: 25

 8574 16:52:06.895431                           [Byte1]: 25

 8575 16:52:06.899882  

 8576 16:52:06.899989  Set Vref, RX VrefLevel [Byte0]: 26

 8577 16:52:06.903183                           [Byte1]: 26

 8578 16:52:06.907873  

 8579 16:52:06.907960  Set Vref, RX VrefLevel [Byte0]: 27

 8580 16:52:06.910982                           [Byte1]: 27

 8581 16:52:06.915695  

 8582 16:52:06.915776  Set Vref, RX VrefLevel [Byte0]: 28

 8583 16:52:06.918446                           [Byte1]: 28

 8584 16:52:06.922902  

 8585 16:52:06.922983  Set Vref, RX VrefLevel [Byte0]: 29

 8586 16:52:06.926308                           [Byte1]: 29

 8587 16:52:06.930296  

 8588 16:52:06.930377  Set Vref, RX VrefLevel [Byte0]: 30

 8589 16:52:06.933545                           [Byte1]: 30

 8590 16:52:06.938218  

 8591 16:52:06.938299  Set Vref, RX VrefLevel [Byte0]: 31

 8592 16:52:06.941592                           [Byte1]: 31

 8593 16:52:06.945706  

 8594 16:52:06.945787  Set Vref, RX VrefLevel [Byte0]: 32

 8595 16:52:06.948877                           [Byte1]: 32

 8596 16:52:06.953484  

 8597 16:52:06.953565  Set Vref, RX VrefLevel [Byte0]: 33

 8598 16:52:06.957001                           [Byte1]: 33

 8599 16:52:06.961022  

 8600 16:52:06.961103  Set Vref, RX VrefLevel [Byte0]: 34

 8601 16:52:06.963934                           [Byte1]: 34

 8602 16:52:06.968467  

 8603 16:52:06.968549  Set Vref, RX VrefLevel [Byte0]: 35

 8604 16:52:06.971824                           [Byte1]: 35

 8605 16:52:06.976147  

 8606 16:52:06.976250  Set Vref, RX VrefLevel [Byte0]: 36

 8607 16:52:06.979547                           [Byte1]: 36

 8608 16:52:06.983867  

 8609 16:52:06.983949  Set Vref, RX VrefLevel [Byte0]: 37

 8610 16:52:06.987228                           [Byte1]: 37

 8611 16:52:06.991287  

 8612 16:52:06.991368  Set Vref, RX VrefLevel [Byte0]: 38

 8613 16:52:06.994819                           [Byte1]: 38

 8614 16:52:06.998754  

 8615 16:52:06.998836  Set Vref, RX VrefLevel [Byte0]: 39

 8616 16:52:07.002095                           [Byte1]: 39

 8617 16:52:07.006512  

 8618 16:52:07.006598  Set Vref, RX VrefLevel [Byte0]: 40

 8619 16:52:07.010061                           [Byte1]: 40

 8620 16:52:07.014116  

 8621 16:52:07.014201  Set Vref, RX VrefLevel [Byte0]: 41

 8622 16:52:07.017564                           [Byte1]: 41

 8623 16:52:07.021920  

 8624 16:52:07.022002  Set Vref, RX VrefLevel [Byte0]: 42

 8625 16:52:07.025051                           [Byte1]: 42

 8626 16:52:07.029405  

 8627 16:52:07.029487  Set Vref, RX VrefLevel [Byte0]: 43

 8628 16:52:07.032957                           [Byte1]: 43

 8629 16:52:07.036834  

 8630 16:52:07.036916  Set Vref, RX VrefLevel [Byte0]: 44

 8631 16:52:07.040292                           [Byte1]: 44

 8632 16:52:07.044559  

 8633 16:52:07.044641  Set Vref, RX VrefLevel [Byte0]: 45

 8634 16:52:07.048200                           [Byte1]: 45

 8635 16:52:07.052672  

 8636 16:52:07.052757  Set Vref, RX VrefLevel [Byte0]: 46

 8637 16:52:07.055524                           [Byte1]: 46

 8638 16:52:07.059610  

 8639 16:52:07.059691  Set Vref, RX VrefLevel [Byte0]: 47

 8640 16:52:07.062988                           [Byte1]: 47

 8641 16:52:07.067327  

 8642 16:52:07.067411  Set Vref, RX VrefLevel [Byte0]: 48

 8643 16:52:07.070614                           [Byte1]: 48

 8644 16:52:07.075145  

 8645 16:52:07.075226  Set Vref, RX VrefLevel [Byte0]: 49

 8646 16:52:07.078643                           [Byte1]: 49

 8647 16:52:07.082655  

 8648 16:52:07.082736  Set Vref, RX VrefLevel [Byte0]: 50

 8649 16:52:07.085791                           [Byte1]: 50

 8650 16:52:07.090173  

 8651 16:52:07.090254  Set Vref, RX VrefLevel [Byte0]: 51

 8652 16:52:07.094041                           [Byte1]: 51

 8653 16:52:07.097902  

 8654 16:52:07.097983  Set Vref, RX VrefLevel [Byte0]: 52

 8655 16:52:07.101159                           [Byte1]: 52

 8656 16:52:07.105500  

 8657 16:52:07.105581  Set Vref, RX VrefLevel [Byte0]: 53

 8658 16:52:07.108917                           [Byte1]: 53

 8659 16:52:07.113197  

 8660 16:52:07.113278  Set Vref, RX VrefLevel [Byte0]: 54

 8661 16:52:07.116559                           [Byte1]: 54

 8662 16:52:07.120628  

 8663 16:52:07.120709  Set Vref, RX VrefLevel [Byte0]: 55

 8664 16:52:07.124438                           [Byte1]: 55

 8665 16:52:07.128226  

 8666 16:52:07.128307  Set Vref, RX VrefLevel [Byte0]: 56

 8667 16:52:07.131854                           [Byte1]: 56

 8668 16:52:07.135904  

 8669 16:52:07.139343  Set Vref, RX VrefLevel [Byte0]: 57

 8670 16:52:07.142400                           [Byte1]: 57

 8671 16:52:07.142482  

 8672 16:52:07.145788  Set Vref, RX VrefLevel [Byte0]: 58

 8673 16:52:07.149150                           [Byte1]: 58

 8674 16:52:07.149232  

 8675 16:52:07.152534  Set Vref, RX VrefLevel [Byte0]: 59

 8676 16:52:07.155879                           [Byte1]: 59

 8677 16:52:07.155967  

 8678 16:52:07.158928  Set Vref, RX VrefLevel [Byte0]: 60

 8679 16:52:07.162700                           [Byte1]: 60

 8680 16:52:07.166420  

 8681 16:52:07.166501  Set Vref, RX VrefLevel [Byte0]: 61

 8682 16:52:07.169840                           [Byte1]: 61

 8683 16:52:07.174001  

 8684 16:52:07.174084  Set Vref, RX VrefLevel [Byte0]: 62

 8685 16:52:07.177318                           [Byte1]: 62

 8686 16:52:07.181683  

 8687 16:52:07.181764  Set Vref, RX VrefLevel [Byte0]: 63

 8688 16:52:07.184679                           [Byte1]: 63

 8689 16:52:07.189395  

 8690 16:52:07.189476  Set Vref, RX VrefLevel [Byte0]: 64

 8691 16:52:07.192566                           [Byte1]: 64

 8692 16:52:07.196896  

 8693 16:52:07.196977  Set Vref, RX VrefLevel [Byte0]: 65

 8694 16:52:07.200241                           [Byte1]: 65

 8695 16:52:07.204507  

 8696 16:52:07.204601  Set Vref, RX VrefLevel [Byte0]: 66

 8697 16:52:07.207876                           [Byte1]: 66

 8698 16:52:07.212539  

 8699 16:52:07.212621  Set Vref, RX VrefLevel [Byte0]: 67

 8700 16:52:07.215475                           [Byte1]: 67

 8701 16:52:07.219376  

 8702 16:52:07.219458  Set Vref, RX VrefLevel [Byte0]: 68

 8703 16:52:07.223249                           [Byte1]: 68

 8704 16:52:07.227462  

 8705 16:52:07.227543  Set Vref, RX VrefLevel [Byte0]: 69

 8706 16:52:07.230777                           [Byte1]: 69

 8707 16:52:07.235172  

 8708 16:52:07.235255  Set Vref, RX VrefLevel [Byte0]: 70

 8709 16:52:07.238505                           [Byte1]: 70

 8710 16:52:07.242463  

 8711 16:52:07.242544  Set Vref, RX VrefLevel [Byte0]: 71

 8712 16:52:07.245843                           [Byte1]: 71

 8713 16:52:07.250422  

 8714 16:52:07.250503  Set Vref, RX VrefLevel [Byte0]: 72

 8715 16:52:07.253349                           [Byte1]: 72

 8716 16:52:07.257926  

 8717 16:52:07.258007  Set Vref, RX VrefLevel [Byte0]: 73

 8718 16:52:07.260863                           [Byte1]: 73

 8719 16:52:07.265467  

 8720 16:52:07.265548  Set Vref, RX VrefLevel [Byte0]: 74

 8721 16:52:07.269113                           [Byte1]: 74

 8722 16:52:07.273212  

 8723 16:52:07.273293  Set Vref, RX VrefLevel [Byte0]: 75

 8724 16:52:07.276635                           [Byte1]: 75

 8725 16:52:07.280540  

 8726 16:52:07.280656  Final RX Vref Byte 0 = 59 to rank0

 8727 16:52:07.284097  Final RX Vref Byte 1 = 58 to rank0

 8728 16:52:07.287463  Final RX Vref Byte 0 = 59 to rank1

 8729 16:52:07.290726  Final RX Vref Byte 1 = 58 to rank1==

 8730 16:52:07.293905  Dram Type= 6, Freq= 0, CH_1, rank 0

 8731 16:52:07.300746  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8732 16:52:07.300829  ==

 8733 16:52:07.300894  DQS Delay:

 8734 16:52:07.300954  DQS0 = 0, DQS1 = 0

 8735 16:52:07.303720  DQM Delay:

 8736 16:52:07.303802  DQM0 = 131, DQM1 = 124

 8737 16:52:07.307623  DQ Delay:

 8738 16:52:07.311065  DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128

 8739 16:52:07.314037  DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128

 8740 16:52:07.316830  DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118

 8741 16:52:07.320166  DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =132

 8742 16:52:07.320248  

 8743 16:52:07.320312  

 8744 16:52:07.320372  

 8745 16:52:07.323822  [DramC_TX_OE_Calibration] TA2

 8746 16:52:07.327182  Original DQ_B0 (3 6) =30, OEN = 27

 8747 16:52:07.330224  Original DQ_B1 (3 6) =30, OEN = 27

 8748 16:52:07.333879  24, 0x0, End_B0=24 End_B1=24

 8749 16:52:07.333962  25, 0x0, End_B0=25 End_B1=25

 8750 16:52:07.336875  26, 0x0, End_B0=26 End_B1=26

 8751 16:52:07.340445  27, 0x0, End_B0=27 End_B1=27

 8752 16:52:07.343805  28, 0x0, End_B0=28 End_B1=28

 8753 16:52:07.347141  29, 0x0, End_B0=29 End_B1=29

 8754 16:52:07.347225  30, 0x0, End_B0=30 End_B1=30

 8755 16:52:07.350447  31, 0x4141, End_B0=30 End_B1=30

 8756 16:52:07.353954  Byte0 end_step=30  best_step=27

 8757 16:52:07.356872  Byte1 end_step=30  best_step=27

 8758 16:52:07.360162  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8759 16:52:07.363497  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8760 16:52:07.363579  

 8761 16:52:07.363642  

 8762 16:52:07.369983  [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps

 8763 16:52:07.373952  CH1 RK0: MR19=302, MR18=13FE

 8764 16:52:07.380064  CH1_RK0: MR19=0x302, MR18=0x13FE, DQSOSC=400, MR23=63, INC=23, DEC=15

 8765 16:52:07.380147  

 8766 16:52:07.383468  ----->DramcWriteLeveling(PI) begin...

 8767 16:52:07.383551  ==

 8768 16:52:07.386987  Dram Type= 6, Freq= 0, CH_1, rank 1

 8769 16:52:07.390470  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8770 16:52:07.390553  ==

 8771 16:52:07.393156  Write leveling (Byte 0): 25 => 25

 8772 16:52:07.396545  Write leveling (Byte 1): 27 => 27

 8773 16:52:07.399910  DramcWriteLeveling(PI) end<-----

 8774 16:52:07.400032  

 8775 16:52:07.400097  ==

 8776 16:52:07.403407  Dram Type= 6, Freq= 0, CH_1, rank 1

 8777 16:52:07.406398  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8778 16:52:07.406480  ==

 8779 16:52:07.410376  [Gating] SW mode calibration

 8780 16:52:07.416553  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8781 16:52:07.423167  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8782 16:52:07.426512   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8783 16:52:07.433263   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8784 16:52:07.436725   1  4  8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)

 8785 16:52:07.439823   1  4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)

 8786 16:52:07.443540   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8787 16:52:07.449694   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8788 16:52:07.452980   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8789 16:52:07.456512   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8790 16:52:07.462895   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8791 16:52:07.466281   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8792 16:52:07.469925   1  5  8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)

 8793 16:52:07.476096   1  5 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)

 8794 16:52:07.479476   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8795 16:52:07.482925   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8796 16:52:07.489612   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8797 16:52:07.492653   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8798 16:52:07.496134   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8799 16:52:07.502891   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8800 16:52:07.506417   1  6  8 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)

 8801 16:52:07.509713   1  6 12 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)

 8802 16:52:07.516096   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8803 16:52:07.519636   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8804 16:52:07.522831   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8805 16:52:07.529639   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8806 16:52:07.532635   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8807 16:52:07.535923   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8808 16:52:07.542583   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8809 16:52:07.546273   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8810 16:52:07.549186   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8811 16:52:07.556352   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8812 16:52:07.559465   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8813 16:52:07.562421   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8814 16:52:07.569510   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8815 16:52:07.572887   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8816 16:52:07.575964   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8817 16:52:07.582380   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8818 16:52:07.585886   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8819 16:52:07.589147   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8820 16:52:07.592773   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8821 16:52:07.598921   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8822 16:52:07.602293   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8823 16:52:07.606026   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8824 16:52:07.612807   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8825 16:52:07.615450   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8826 16:52:07.618853  Total UI for P1: 0, mck2ui 16

 8827 16:52:07.622374  best dqsien dly found for B0: ( 1,  9,  6)

 8828 16:52:07.625855   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8829 16:52:07.632298   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8830 16:52:07.635708  Total UI for P1: 0, mck2ui 16

 8831 16:52:07.638541  best dqsien dly found for B1: ( 1,  9, 14)

 8832 16:52:07.641878  best DQS0 dly(MCK, UI, PI) = (1, 9, 6)

 8833 16:52:07.645422  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8834 16:52:07.645503  

 8835 16:52:07.648524  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8836 16:52:07.652597  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8837 16:52:07.655261  [Gating] SW calibration Done

 8838 16:52:07.655342  ==

 8839 16:52:07.658691  Dram Type= 6, Freq= 0, CH_1, rank 1

 8840 16:52:07.661792  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8841 16:52:07.661904  ==

 8842 16:52:07.665153  RX Vref Scan: 0

 8843 16:52:07.665234  

 8844 16:52:07.665299  RX Vref 0 -> 0, step: 1

 8845 16:52:07.668432  

 8846 16:52:07.668512  RX Delay 0 -> 252, step: 8

 8847 16:52:07.674998  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8848 16:52:07.678669  iDelay=200, Bit 1, Center 127 (72 ~ 183) 112

 8849 16:52:07.682156  iDelay=200, Bit 2, Center 119 (64 ~ 175) 112

 8850 16:52:07.684948  iDelay=200, Bit 3, Center 131 (72 ~ 191) 120

 8851 16:52:07.688590  iDelay=200, Bit 4, Center 131 (72 ~ 191) 120

 8852 16:52:07.691781  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8853 16:52:07.698644  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8854 16:52:07.701886  iDelay=200, Bit 7, Center 127 (72 ~ 183) 112

 8855 16:52:07.705493  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 8856 16:52:07.708613  iDelay=200, Bit 9, Center 115 (56 ~ 175) 120

 8857 16:52:07.711834  iDelay=200, Bit 10, Center 131 (72 ~ 191) 120

 8858 16:52:07.718545  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8859 16:52:07.721884  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8860 16:52:07.725616  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 8861 16:52:07.728305  iDelay=200, Bit 14, Center 139 (80 ~ 199) 120

 8862 16:52:07.734793  iDelay=200, Bit 15, Center 139 (80 ~ 199) 120

 8863 16:52:07.734905  ==

 8864 16:52:07.738162  Dram Type= 6, Freq= 0, CH_1, rank 1

 8865 16:52:07.741650  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8866 16:52:07.741738  ==

 8867 16:52:07.741804  DQS Delay:

 8868 16:52:07.744892  DQS0 = 0, DQS1 = 0

 8869 16:52:07.744974  DQM Delay:

 8870 16:52:07.748417  DQM0 = 132, DQM1 = 129

 8871 16:52:07.748499  DQ Delay:

 8872 16:52:07.751454  DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131

 8873 16:52:07.754997  DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127

 8874 16:52:07.758197  DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119

 8875 16:52:07.761935  DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139

 8876 16:52:07.762017  

 8877 16:52:07.762081  

 8878 16:52:07.765344  ==

 8879 16:52:07.769046  Dram Type= 6, Freq= 0, CH_1, rank 1

 8880 16:52:07.771432  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8881 16:52:07.771515  ==

 8882 16:52:07.771579  

 8883 16:52:07.771639  

 8884 16:52:07.775061  	TX Vref Scan disable

 8885 16:52:07.775143   == TX Byte 0 ==

 8886 16:52:07.778214  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8887 16:52:07.784691  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8888 16:52:07.784775   == TX Byte 1 ==

 8889 16:52:07.788087  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8890 16:52:07.794464  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8891 16:52:07.794547  ==

 8892 16:52:07.797920  Dram Type= 6, Freq= 0, CH_1, rank 1

 8893 16:52:07.801523  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8894 16:52:07.801606  ==

 8895 16:52:07.815236  

 8896 16:52:07.818648  TX Vref early break, caculate TX vref

 8897 16:52:07.821924  TX Vref=16, minBit 8, minWin=22, winSum=374

 8898 16:52:07.825342  TX Vref=18, minBit 9, minWin=22, winSum=384

 8899 16:52:07.828754  TX Vref=20, minBit 8, minWin=23, winSum=394

 8900 16:52:07.832143  TX Vref=22, minBit 8, minWin=24, winSum=404

 8901 16:52:07.835188  TX Vref=24, minBit 15, minWin=24, winSum=409

 8902 16:52:07.841865  TX Vref=26, minBit 0, minWin=25, winSum=415

 8903 16:52:07.845263  TX Vref=28, minBit 0, minWin=26, winSum=424

 8904 16:52:07.848544  TX Vref=30, minBit 5, minWin=25, winSum=424

 8905 16:52:07.851555  TX Vref=32, minBit 0, minWin=25, winSum=420

 8906 16:52:07.855048  TX Vref=34, minBit 0, minWin=24, winSum=407

 8907 16:52:07.858234  TX Vref=36, minBit 0, minWin=23, winSum=395

 8908 16:52:07.864809  [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28

 8909 16:52:07.864898  

 8910 16:52:07.868545  Final TX Range 0 Vref 28

 8911 16:52:07.868629  

 8912 16:52:07.868694  ==

 8913 16:52:07.871856  Dram Type= 6, Freq= 0, CH_1, rank 1

 8914 16:52:07.875101  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8915 16:52:07.875189  ==

 8916 16:52:07.878259  

 8917 16:52:07.878343  

 8918 16:52:07.878408  	TX Vref Scan disable

 8919 16:52:07.885031  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8920 16:52:07.885120   == TX Byte 0 ==

 8921 16:52:07.888222  u2DelayCellOfst[0]=14 cells (4 PI)

 8922 16:52:07.891371  u2DelayCellOfst[1]=10 cells (3 PI)

 8923 16:52:07.894705  u2DelayCellOfst[2]=0 cells (0 PI)

 8924 16:52:07.898664  u2DelayCellOfst[3]=7 cells (2 PI)

 8925 16:52:07.901444  u2DelayCellOfst[4]=7 cells (2 PI)

 8926 16:52:07.904827  u2DelayCellOfst[5]=17 cells (5 PI)

 8927 16:52:07.908525  u2DelayCellOfst[6]=17 cells (5 PI)

 8928 16:52:07.911709  u2DelayCellOfst[7]=7 cells (2 PI)

 8929 16:52:07.914684  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8930 16:52:07.917941  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8931 16:52:07.921453   == TX Byte 1 ==

 8932 16:52:07.924535  u2DelayCellOfst[8]=0 cells (0 PI)

 8933 16:52:07.928072  u2DelayCellOfst[9]=3 cells (1 PI)

 8934 16:52:07.931413  u2DelayCellOfst[10]=10 cells (3 PI)

 8935 16:52:07.931500  u2DelayCellOfst[11]=7 cells (2 PI)

 8936 16:52:07.934704  u2DelayCellOfst[12]=14 cells (4 PI)

 8937 16:52:07.937672  u2DelayCellOfst[13]=17 cells (5 PI)

 8938 16:52:07.941768  u2DelayCellOfst[14]=17 cells (5 PI)

 8939 16:52:07.944452  u2DelayCellOfst[15]=14 cells (4 PI)

 8940 16:52:07.951758  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8941 16:52:07.954745  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8942 16:52:07.954831  DramC Write-DBI on

 8943 16:52:07.954898  ==

 8944 16:52:07.957846  Dram Type= 6, Freq= 0, CH_1, rank 1

 8945 16:52:07.963998  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8946 16:52:07.964088  ==

 8947 16:52:07.964154  

 8948 16:52:07.964214  

 8949 16:52:07.967242  	TX Vref Scan disable

 8950 16:52:07.967326   == TX Byte 0 ==

 8951 16:52:07.974271  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8952 16:52:07.974363   == TX Byte 1 ==

 8953 16:52:07.977512  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8954 16:52:07.981138  DramC Write-DBI off

 8955 16:52:07.981222  

 8956 16:52:07.981288  [DATLAT]

 8957 16:52:07.983783  Freq=1600, CH1 RK1

 8958 16:52:07.983866  

 8959 16:52:07.983933  DATLAT Default: 0xf

 8960 16:52:07.987428  0, 0xFFFF, sum = 0

 8961 16:52:07.987513  1, 0xFFFF, sum = 0

 8962 16:52:07.990873  2, 0xFFFF, sum = 0

 8963 16:52:07.990957  3, 0xFFFF, sum = 0

 8964 16:52:07.994096  4, 0xFFFF, sum = 0

 8965 16:52:07.994181  5, 0xFFFF, sum = 0

 8966 16:52:07.997251  6, 0xFFFF, sum = 0

 8967 16:52:08.000514  7, 0xFFFF, sum = 0

 8968 16:52:08.000599  8, 0xFFFF, sum = 0

 8969 16:52:08.003856  9, 0xFFFF, sum = 0

 8970 16:52:08.003940  10, 0xFFFF, sum = 0

 8971 16:52:08.007364  11, 0xFFFF, sum = 0

 8972 16:52:08.007459  12, 0xFFFF, sum = 0

 8973 16:52:08.010758  13, 0xFFFF, sum = 0

 8974 16:52:08.010845  14, 0x0, sum = 1

 8975 16:52:08.014157  15, 0x0, sum = 2

 8976 16:52:08.014244  16, 0x0, sum = 3

 8977 16:52:08.017037  17, 0x0, sum = 4

 8978 16:52:08.017121  best_step = 15

 8979 16:52:08.017187  

 8980 16:52:08.017247  ==

 8981 16:52:08.020421  Dram Type= 6, Freq= 0, CH_1, rank 1

 8982 16:52:08.024204  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8983 16:52:08.024290  ==

 8984 16:52:08.026926  RX Vref Scan: 0

 8985 16:52:08.027009  

 8986 16:52:08.030482  RX Vref 0 -> 0, step: 1

 8987 16:52:08.030566  

 8988 16:52:08.030631  RX Delay 11 -> 252, step: 4

 8989 16:52:08.037636  iDelay=195, Bit 0, Center 132 (83 ~ 182) 100

 8990 16:52:08.041031  iDelay=195, Bit 1, Center 126 (75 ~ 178) 104

 8991 16:52:08.043714  iDelay=195, Bit 2, Center 118 (67 ~ 170) 104

 8992 16:52:08.047156  iDelay=195, Bit 3, Center 126 (75 ~ 178) 104

 8993 16:52:08.050643  iDelay=195, Bit 4, Center 130 (79 ~ 182) 104

 8994 16:52:08.057233  iDelay=195, Bit 5, Center 144 (95 ~ 194) 100

 8995 16:52:08.060542  iDelay=195, Bit 6, Center 138 (87 ~ 190) 104

 8996 16:52:08.063884  iDelay=195, Bit 7, Center 126 (75 ~ 178) 104

 8997 16:52:08.067370  iDelay=195, Bit 8, Center 114 (59 ~ 170) 112

 8998 16:52:08.073715  iDelay=195, Bit 9, Center 112 (59 ~ 166) 108

 8999 16:52:08.077181  iDelay=195, Bit 10, Center 128 (75 ~ 182) 108

 9000 16:52:08.080662  iDelay=195, Bit 11, Center 120 (67 ~ 174) 108

 9001 16:52:08.083470  iDelay=195, Bit 12, Center 132 (79 ~ 186) 108

 9002 16:52:08.087177  iDelay=195, Bit 13, Center 134 (83 ~ 186) 104

 9003 16:52:08.093707  iDelay=195, Bit 14, Center 134 (79 ~ 190) 112

 9004 16:52:08.096811  iDelay=195, Bit 15, Center 136 (83 ~ 190) 108

 9005 16:52:08.096900  ==

 9006 16:52:08.100548  Dram Type= 6, Freq= 0, CH_1, rank 1

 9007 16:52:08.103605  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9008 16:52:08.103691  ==

 9009 16:52:08.106668  DQS Delay:

 9010 16:52:08.106793  DQS0 = 0, DQS1 = 0

 9011 16:52:08.106872  DQM Delay:

 9012 16:52:08.110115  DQM0 = 130, DQM1 = 126

 9013 16:52:08.110205  DQ Delay:

 9014 16:52:08.113824  DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126

 9015 16:52:08.116868  DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126

 9016 16:52:08.120164  DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120

 9017 16:52:08.127038  DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =136

 9018 16:52:08.127134  

 9019 16:52:08.127201  

 9020 16:52:08.127261  

 9021 16:52:08.130226  [DramC_TX_OE_Calibration] TA2

 9022 16:52:08.133637  Original DQ_B0 (3 6) =30, OEN = 27

 9023 16:52:08.133723  Original DQ_B1 (3 6) =30, OEN = 27

 9024 16:52:08.136560  24, 0x0, End_B0=24 End_B1=24

 9025 16:52:08.139934  25, 0x0, End_B0=25 End_B1=25

 9026 16:52:08.143206  26, 0x0, End_B0=26 End_B1=26

 9027 16:52:08.146659  27, 0x0, End_B0=27 End_B1=27

 9028 16:52:08.146749  28, 0x0, End_B0=28 End_B1=28

 9029 16:52:08.150087  29, 0x0, End_B0=29 End_B1=29

 9030 16:52:08.153245  30, 0x0, End_B0=30 End_B1=30

 9031 16:52:08.156841  31, 0x4141, End_B0=30 End_B1=30

 9032 16:52:08.160519  Byte0 end_step=30  best_step=27

 9033 16:52:08.160605  Byte1 end_step=30  best_step=27

 9034 16:52:08.163577  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9035 16:52:08.166938  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9036 16:52:08.167023  

 9037 16:52:08.167089  

 9038 16:52:08.176273  [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps

 9039 16:52:08.176391  CH1 RK1: MR19=303, MR18=1016

 9040 16:52:08.183079  CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15

 9041 16:52:08.186934  [RxdqsGatingPostProcess] freq 1600

 9042 16:52:08.193825  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9043 16:52:08.196347  best DQS0 dly(2T, 0.5T) = (1, 1)

 9044 16:52:08.199829  best DQS1 dly(2T, 0.5T) = (1, 1)

 9045 16:52:08.202889  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9046 16:52:08.206453  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9047 16:52:08.209748  best DQS0 dly(2T, 0.5T) = (1, 1)

 9048 16:52:08.209843  best DQS1 dly(2T, 0.5T) = (1, 1)

 9049 16:52:08.212852  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9050 16:52:08.216701  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9051 16:52:08.219795  Pre-setting of DQS Precalculation

 9052 16:52:08.226164  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9053 16:52:08.232836  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9054 16:52:08.239434  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9055 16:52:08.239537  

 9056 16:52:08.239600  

 9057 16:52:08.242380  [Calibration Summary] 3200 Mbps

 9058 16:52:08.242464  CH 0, Rank 0

 9059 16:52:08.245938  SW Impedance     : PASS

 9060 16:52:08.249243  DUTY Scan        : NO K

 9061 16:52:08.249331  ZQ Calibration   : PASS

 9062 16:52:08.252867  Jitter Meter     : NO K

 9063 16:52:08.256146  CBT Training     : PASS

 9064 16:52:08.256231  Write leveling   : PASS

 9065 16:52:08.259630  RX DQS gating    : PASS

 9066 16:52:08.262772  RX DQ/DQS(RDDQC) : PASS

 9067 16:52:08.262855  TX DQ/DQS        : PASS

 9068 16:52:08.265634  RX DATLAT        : PASS

 9069 16:52:08.269059  RX DQ/DQS(Engine): PASS

 9070 16:52:08.269143  TX OE            : PASS

 9071 16:52:08.272733  All Pass.

 9072 16:52:08.272816  

 9073 16:52:08.272882  CH 0, Rank 1

 9074 16:52:08.275895  SW Impedance     : PASS

 9075 16:52:08.276015  DUTY Scan        : NO K

 9076 16:52:08.279060  ZQ Calibration   : PASS

 9077 16:52:08.282452  Jitter Meter     : NO K

 9078 16:52:08.282541  CBT Training     : PASS

 9079 16:52:08.285836  Write leveling   : PASS

 9080 16:52:08.288908  RX DQS gating    : PASS

 9081 16:52:08.288992  RX DQ/DQS(RDDQC) : PASS

 9082 16:52:08.292259  TX DQ/DQS        : PASS

 9083 16:52:08.292343  RX DATLAT        : PASS

 9084 16:52:08.295640  RX DQ/DQS(Engine): PASS

 9085 16:52:08.299290  TX OE            : PASS

 9086 16:52:08.299375  All Pass.

 9087 16:52:08.299439  

 9088 16:52:08.299499  CH 1, Rank 0

 9089 16:52:08.302694  SW Impedance     : PASS

 9090 16:52:08.305782  DUTY Scan        : NO K

 9091 16:52:08.305867  ZQ Calibration   : PASS

 9092 16:52:08.308797  Jitter Meter     : NO K

 9093 16:52:08.312514  CBT Training     : PASS

 9094 16:52:08.312607  Write leveling   : PASS

 9095 16:52:08.315650  RX DQS gating    : PASS

 9096 16:52:08.319296  RX DQ/DQS(RDDQC) : PASS

 9097 16:52:08.319383  TX DQ/DQS        : PASS

 9098 16:52:08.322300  RX DATLAT        : PASS

 9099 16:52:08.325695  RX DQ/DQS(Engine): PASS

 9100 16:52:08.325780  TX OE            : PASS

 9101 16:52:08.329378  All Pass.

 9102 16:52:08.329463  

 9103 16:52:08.329527  CH 1, Rank 1

 9104 16:52:08.332242  SW Impedance     : PASS

 9105 16:52:08.332325  DUTY Scan        : NO K

 9106 16:52:08.335573  ZQ Calibration   : PASS

 9107 16:52:08.339011  Jitter Meter     : NO K

 9108 16:52:08.339094  CBT Training     : PASS

 9109 16:52:08.342361  Write leveling   : PASS

 9110 16:52:08.342447  RX DQS gating    : PASS

 9111 16:52:08.345457  RX DQ/DQS(RDDQC) : PASS

 9112 16:52:08.349030  TX DQ/DQS        : PASS

 9113 16:52:08.349116  RX DATLAT        : PASS

 9114 16:52:08.352338  RX DQ/DQS(Engine): PASS

 9115 16:52:08.355801  TX OE            : PASS

 9116 16:52:08.355888  All Pass.

 9117 16:52:08.356010  

 9118 16:52:08.359104  DramC Write-DBI on

 9119 16:52:08.359192  	PER_BANK_REFRESH: Hybrid Mode

 9120 16:52:08.361990  TX_TRACKING: ON

 9121 16:52:08.372132  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9122 16:52:08.379157  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9123 16:52:08.385824  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9124 16:52:08.388857  [FAST_K] Save calibration result to emmc

 9125 16:52:08.392167  sync common calibartion params.

 9126 16:52:08.395624  sync cbt_mode0:1, 1:1

 9127 16:52:08.395713  dram_init: ddr_geometry: 2

 9128 16:52:08.399135  dram_init: ddr_geometry: 2

 9129 16:52:08.402502  dram_init: ddr_geometry: 2

 9130 16:52:08.405197  0:dram_rank_size:100000000

 9131 16:52:08.405284  1:dram_rank_size:100000000

 9132 16:52:08.412528  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9133 16:52:08.415577  DFS_SHUFFLE_HW_MODE: ON

 9134 16:52:08.419040  dramc_set_vcore_voltage set vcore to 725000

 9135 16:52:08.419132  Read voltage for 1600, 0

 9136 16:52:08.422025  Vio18 = 0

 9137 16:52:08.422109  Vcore = 725000

 9138 16:52:08.422191  Vdram = 0

 9139 16:52:08.425522  Vddq = 0

 9140 16:52:08.425606  Vmddr = 0

 9141 16:52:08.429042  switch to 3200 Mbps bootup

 9142 16:52:08.429126  [DramcRunTimeConfig]

 9143 16:52:08.429191  PHYPLL

 9144 16:52:08.431851  DPM_CONTROL_AFTERK: ON

 9145 16:52:08.435246  PER_BANK_REFRESH: ON

 9146 16:52:08.438773  REFRESH_OVERHEAD_REDUCTION: ON

 9147 16:52:08.438857  CMD_PICG_NEW_MODE: OFF

 9148 16:52:08.441704  XRTWTW_NEW_MODE: ON

 9149 16:52:08.441786  XRTRTR_NEW_MODE: ON

 9150 16:52:08.444916  TX_TRACKING: ON

 9151 16:52:08.444999  RDSEL_TRACKING: OFF

 9152 16:52:08.448237  DQS Precalculation for DVFS: ON

 9153 16:52:08.451824  RX_TRACKING: OFF

 9154 16:52:08.451934  HW_GATING DBG: ON

 9155 16:52:08.455068  ZQCS_ENABLE_LP4: ON

 9156 16:52:08.455151  RX_PICG_NEW_MODE: ON

 9157 16:52:08.458644  TX_PICG_NEW_MODE: ON

 9158 16:52:08.458727  ENABLE_RX_DCM_DPHY: ON

 9159 16:52:08.462151  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9160 16:52:08.464994  DUMMY_READ_FOR_TRACKING: OFF

 9161 16:52:08.468277  !!! SPM_CONTROL_AFTERK: OFF

 9162 16:52:08.471682  !!! SPM could not control APHY

 9163 16:52:08.471772  IMPEDANCE_TRACKING: ON

 9164 16:52:08.475125  TEMP_SENSOR: ON

 9165 16:52:08.475210  HW_SAVE_FOR_SR: OFF

 9166 16:52:08.478565  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9167 16:52:08.481399  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9168 16:52:08.485284  Read ODT Tracking: ON

 9169 16:52:08.488045  Refresh Rate DeBounce: ON

 9170 16:52:08.488130  DFS_NO_QUEUE_FLUSH: ON

 9171 16:52:08.491424  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9172 16:52:08.495113  ENABLE_DFS_RUNTIME_MRW: OFF

 9173 16:52:08.497936  DDR_RESERVE_NEW_MODE: ON

 9174 16:52:08.498020  MR_CBT_SWITCH_FREQ: ON

 9175 16:52:08.501326  =========================

 9176 16:52:08.520684  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9177 16:52:08.523571  dram_init: ddr_geometry: 2

 9178 16:52:08.541430  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9179 16:52:08.544991  dram_init: dram init end (result: 0)

 9180 16:52:08.551737  DRAM-K: Full calibration passed in 24602 msecs

 9181 16:52:08.555065  MRC: failed to locate region type 0.

 9182 16:52:08.555164  DRAM rank0 size:0x100000000,

 9183 16:52:08.558265  DRAM rank1 size=0x100000000

 9184 16:52:08.568151  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9185 16:52:08.574645  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9186 16:52:08.581451  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9187 16:52:08.591230  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9188 16:52:08.591371  DRAM rank0 size:0x100000000,

 9189 16:52:08.594464  DRAM rank1 size=0x100000000

 9190 16:52:08.594551  CBMEM:

 9191 16:52:08.597783  IMD: root @ 0xfffff000 254 entries.

 9192 16:52:08.600880  IMD: root @ 0xffffec00 62 entries.

 9193 16:52:08.604702  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9194 16:52:08.611258  WARNING: RO_VPD is uninitialized or empty.

 9195 16:52:08.614194  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9196 16:52:08.622108  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9197 16:52:08.634348  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9198 16:52:08.646137  BS: romstage times (exec / console): total (unknown) / 24104 ms

 9199 16:52:08.646281  

 9200 16:52:08.646347  

 9201 16:52:08.656076  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9202 16:52:08.658977  ARM64: Exception handlers installed.

 9203 16:52:08.662279  ARM64: Testing exception

 9204 16:52:08.665835  ARM64: Done test exception

 9205 16:52:08.665927  Enumerating buses...

 9206 16:52:08.669037  Show all devs... Before device enumeration.

 9207 16:52:08.672434  Root Device: enabled 1

 9208 16:52:08.676027  CPU_CLUSTER: 0: enabled 1

 9209 16:52:08.676116  CPU: 00: enabled 1

 9210 16:52:08.678871  Compare with tree...

 9211 16:52:08.678955  Root Device: enabled 1

 9212 16:52:08.682325   CPU_CLUSTER: 0: enabled 1

 9213 16:52:08.685762    CPU: 00: enabled 1

 9214 16:52:08.685849  Root Device scanning...

 9215 16:52:08.689167  scan_static_bus for Root Device

 9216 16:52:08.692448  CPU_CLUSTER: 0 enabled

 9217 16:52:08.695910  scan_static_bus for Root Device done

 9218 16:52:08.699292  scan_bus: bus Root Device finished in 8 msecs

 9219 16:52:08.699381  done

 9220 16:52:08.705906  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9221 16:52:08.709038  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9222 16:52:08.715901  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9223 16:52:08.718720  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9224 16:52:08.722410  Allocating resources...

 9225 16:52:08.725716  Reading resources...

 9226 16:52:08.729016  Root Device read_resources bus 0 link: 0

 9227 16:52:08.729110  DRAM rank0 size:0x100000000,

 9228 16:52:08.732376  DRAM rank1 size=0x100000000

 9229 16:52:08.735606  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9230 16:52:08.738860  CPU: 00 missing read_resources

 9231 16:52:08.742565  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9232 16:52:08.748722  Root Device read_resources bus 0 link: 0 done

 9233 16:52:08.748830  Done reading resources.

 9234 16:52:08.755736  Show resources in subtree (Root Device)...After reading.

 9235 16:52:08.758420   Root Device child on link 0 CPU_CLUSTER: 0

 9236 16:52:08.762678    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9237 16:52:08.771802    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9238 16:52:08.771921     CPU: 00

 9239 16:52:08.775184  Root Device assign_resources, bus 0 link: 0

 9240 16:52:08.778651  CPU_CLUSTER: 0 missing set_resources

 9241 16:52:08.785363  Root Device assign_resources, bus 0 link: 0 done

 9242 16:52:08.785478  Done setting resources.

 9243 16:52:08.791814  Show resources in subtree (Root Device)...After assigning values.

 9244 16:52:08.795252   Root Device child on link 0 CPU_CLUSTER: 0

 9245 16:52:08.798443    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9246 16:52:08.808593    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9247 16:52:08.808718     CPU: 00

 9248 16:52:08.811922  Done allocating resources.

 9249 16:52:08.815243  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9250 16:52:08.818121  Enabling resources...

 9251 16:52:08.818209  done.

 9252 16:52:08.824807  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9253 16:52:08.824906  Initializing devices...

 9254 16:52:08.828244  Root Device init

 9255 16:52:08.828330  init hardware done!

 9256 16:52:08.831716  0x00000018: ctrlr->caps

 9257 16:52:08.834967  52.000 MHz: ctrlr->f_max

 9258 16:52:08.835056  0.400 MHz: ctrlr->f_min

 9259 16:52:08.838180  0x40ff8080: ctrlr->voltages

 9260 16:52:08.838266  sclk: 390625

 9261 16:52:08.841464  Bus Width = 1

 9262 16:52:08.841549  sclk: 390625

 9263 16:52:08.844722  Bus Width = 1

 9264 16:52:08.844805  Early init status = 3

 9265 16:52:08.851432  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9266 16:52:08.854742  in-header: 03 fc 00 00 01 00 00 00 

 9267 16:52:08.854835  in-data: 00 

 9268 16:52:08.861203  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9269 16:52:08.864796  in-header: 03 fd 00 00 00 00 00 00 

 9270 16:52:08.868334  in-data: 

 9271 16:52:08.871149  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9272 16:52:08.874859  in-header: 03 fc 00 00 01 00 00 00 

 9273 16:52:08.878133  in-data: 00 

 9274 16:52:08.881599  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9275 16:52:08.886726  in-header: 03 fd 00 00 00 00 00 00 

 9276 16:52:08.890239  in-data: 

 9277 16:52:08.892997  [SSUSB] Setting up USB HOST controller...

 9278 16:52:08.896477  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9279 16:52:08.899892  [SSUSB] phy power-on done.

 9280 16:52:08.903174  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9281 16:52:08.909682  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9282 16:52:08.913141  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9283 16:52:08.919425  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9284 16:52:08.926529  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9285 16:52:08.932831  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9286 16:52:08.939608  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9287 16:52:08.946237  read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps

 9288 16:52:08.949798  SPM: binary array size = 0x9dc

 9289 16:52:08.953187  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9290 16:52:08.959394  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9291 16:52:08.965999  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9292 16:52:08.972479  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9293 16:52:08.975904  configure_display: Starting display init

 9294 16:52:09.010063  anx7625_power_on_init: Init interface.

 9295 16:52:09.013389  anx7625_disable_pd_protocol: Disabled PD feature.

 9296 16:52:09.016194  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9297 16:52:09.044785  anx7625_start_dp_work: Secure OCM version=00

 9298 16:52:09.047637  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9299 16:52:09.062437  sp_tx_get_edid_block: EDID Block = 1

 9300 16:52:09.164657  Extracted contents:

 9301 16:52:09.167971  header:          00 ff ff ff ff ff ff 00

 9302 16:52:09.171605  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9303 16:52:09.174944  version:         01 04

 9304 16:52:09.178109  basic params:    95 1f 11 78 0a

 9305 16:52:09.181223  chroma info:     76 90 94 55 54 90 27 21 50 54

 9306 16:52:09.184400  established:     00 00 00

 9307 16:52:09.191040  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9308 16:52:09.197509  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9309 16:52:09.200893  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9310 16:52:09.207660  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9311 16:52:09.214401  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9312 16:52:09.217954  extensions:      00

 9313 16:52:09.218056  checksum:        fb

 9314 16:52:09.218120  

 9315 16:52:09.220643  Manufacturer: IVO Model 57d Serial Number 0

 9316 16:52:09.223820  Made week 0 of 2020

 9317 16:52:09.227411  EDID version: 1.4

 9318 16:52:09.227498  Digital display

 9319 16:52:09.230927  6 bits per primary color channel

 9320 16:52:09.231016  DisplayPort interface

 9321 16:52:09.233847  Maximum image size: 31 cm x 17 cm

 9322 16:52:09.237438  Gamma: 220%

 9323 16:52:09.237525  Check DPMS levels

 9324 16:52:09.240897  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9325 16:52:09.247503  First detailed timing is preferred timing

 9326 16:52:09.247612  Established timings supported:

 9327 16:52:09.251152  Standard timings supported:

 9328 16:52:09.253801  Detailed timings

 9329 16:52:09.257132  Hex of detail: 383680a07038204018303c0035ae10000019

 9330 16:52:09.263741  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9331 16:52:09.267323                 0780 0798 07c8 0820 hborder 0

 9332 16:52:09.270650                 0438 043b 0447 0458 vborder 0

 9333 16:52:09.273830                 -hsync -vsync

 9334 16:52:09.273921  Did detailed timing

 9335 16:52:09.280501  Hex of detail: 000000000000000000000000000000000000

 9336 16:52:09.283637  Manufacturer-specified data, tag 0

 9337 16:52:09.286998  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9338 16:52:09.290426  ASCII string: InfoVision

 9339 16:52:09.294019  Hex of detail: 000000fe00523134304e574635205248200a

 9340 16:52:09.297118  ASCII string: R140NWF5 RH 

 9341 16:52:09.297206  Checksum

 9342 16:52:09.300109  Checksum: 0xfb (valid)

 9343 16:52:09.303752  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9344 16:52:09.307469  DSI data_rate: 832800000 bps

 9345 16:52:09.313614  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9346 16:52:09.317190  anx7625_parse_edid: pixelclock(138800).

 9347 16:52:09.320352   hactive(1920), hsync(48), hfp(24), hbp(88)

 9348 16:52:09.323339   vactive(1080), vsync(12), vfp(3), vbp(17)

 9349 16:52:09.326877  anx7625_dsi_config: config dsi.

 9350 16:52:09.333320  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9351 16:52:09.346927  anx7625_dsi_config: success to config DSI

 9352 16:52:09.350762  anx7625_dp_start: MIPI phy setup OK.

 9353 16:52:09.353686  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9354 16:52:09.356909  mtk_ddp_mode_set invalid vrefresh 60

 9355 16:52:09.359769  main_disp_path_setup

 9356 16:52:09.359859  ovl_layer_smi_id_en

 9357 16:52:09.363450  ovl_layer_smi_id_en

 9358 16:52:09.363539  ccorr_config

 9359 16:52:09.363605  aal_config

 9360 16:52:09.366742  gamma_config

 9361 16:52:09.366830  postmask_config

 9362 16:52:09.369647  dither_config

 9363 16:52:09.373173  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9364 16:52:09.379894                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9365 16:52:09.383114  Root Device init finished in 552 msecs

 9366 16:52:09.386329  CPU_CLUSTER: 0 init

 9367 16:52:09.393244  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9368 16:52:09.399419  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9369 16:52:09.399528  APU_MBOX 0x190000b0 = 0x10001

 9370 16:52:09.403080  APU_MBOX 0x190001b0 = 0x10001

 9371 16:52:09.406059  APU_MBOX 0x190005b0 = 0x10001

 9372 16:52:09.409920  APU_MBOX 0x190006b0 = 0x10001

 9373 16:52:09.415912  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9374 16:52:09.425754  read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps

 9375 16:52:09.438050  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9376 16:52:09.445042  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9377 16:52:09.456261  read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps

 9378 16:52:09.465704  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9379 16:52:09.469086  CPU_CLUSTER: 0 init finished in 81 msecs

 9380 16:52:09.472096  Devices initialized

 9381 16:52:09.475467  Show all devs... After init.

 9382 16:52:09.475558  Root Device: enabled 1

 9383 16:52:09.479253  CPU_CLUSTER: 0: enabled 1

 9384 16:52:09.482541  CPU: 00: enabled 1

 9385 16:52:09.485902  BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms

 9386 16:52:09.488657  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9387 16:52:09.492679  ELOG: NV offset 0x57f000 size 0x1000

 9388 16:52:09.498746  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9389 16:52:09.505586  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9390 16:52:09.508864  ELOG: Event(17) added with size 13 at 2023-06-03 16:52:09 UTC

 9391 16:52:09.512210  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9392 16:52:09.516477  in-header: 03 b8 00 00 2c 00 00 00 

 9393 16:52:09.530026  in-data: a7 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9394 16:52:09.536571  ELOG: Event(A1) added with size 10 at 2023-06-03 16:52:09 UTC

 9395 16:52:09.543150  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9396 16:52:09.549549  ELOG: Event(A0) added with size 9 at 2023-06-03 16:52:09 UTC

 9397 16:52:09.553357  elog_add_boot_reason: Logged dev mode boot

 9398 16:52:09.556478  BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms

 9399 16:52:09.559665  Finalize devices...

 9400 16:52:09.559751  Devices finalized

 9401 16:52:09.566063  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9402 16:52:09.569345  Writing coreboot table at 0xffe64000

 9403 16:52:09.572624   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9404 16:52:09.576144   1. 0000000040000000-00000000400fffff: RAM

 9405 16:52:09.583297   2. 0000000040100000-000000004032afff: RAMSTAGE

 9406 16:52:09.586481   3. 000000004032b000-00000000545fffff: RAM

 9407 16:52:09.589941   4. 0000000054600000-000000005465ffff: BL31

 9408 16:52:09.592771   5. 0000000054660000-00000000ffe63fff: RAM

 9409 16:52:09.599545   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9410 16:52:09.602727   7. 0000000100000000-000000023fffffff: RAM

 9411 16:52:09.605929  Passing 5 GPIOs to payload:

 9412 16:52:09.609185              NAME |       PORT | POLARITY |     VALUE

 9413 16:52:09.612860          EC in RW | 0x000000aa |      low | undefined

 9414 16:52:09.619137      EC interrupt | 0x00000005 |      low | undefined

 9415 16:52:09.622679     TPM interrupt | 0x000000ab |     high | undefined

 9416 16:52:09.629345    SD card detect | 0x00000011 |     high | undefined

 9417 16:52:09.632611    speaker enable | 0x00000093 |     high | undefined

 9418 16:52:09.636220  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9419 16:52:09.638797  in-header: 03 f9 00 00 02 00 00 00 

 9420 16:52:09.642312  in-data: 02 00 

 9421 16:52:09.642436  ADC[4]: Raw value=900221 ID=7

 9422 16:52:09.645562  ADC[3]: Raw value=213336 ID=1

 9423 16:52:09.648919  RAM Code: 0x71

 9424 16:52:09.649040  ADC[6]: Raw value=74926 ID=0

 9425 16:52:09.652191  ADC[5]: Raw value=211860 ID=1

 9426 16:52:09.655706  SKU Code: 0x1

 9427 16:52:09.658542  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1

 9428 16:52:09.662214  coreboot table: 964 bytes.

 9429 16:52:09.665397  IMD ROOT    0. 0xfffff000 0x00001000

 9430 16:52:09.668884  IMD SMALL   1. 0xffffe000 0x00001000

 9431 16:52:09.672075  RO MCACHE   2. 0xffffc000 0x00001104

 9432 16:52:09.675396  CONSOLE     3. 0xfff7c000 0x00080000

 9433 16:52:09.678951  FMAP        4. 0xfff7b000 0x00000452

 9434 16:52:09.681900  TIME STAMP  5. 0xfff7a000 0x00000910

 9435 16:52:09.685531  VBOOT WORK  6. 0xfff66000 0x00014000

 9436 16:52:09.688422  RAMOOPS     7. 0xffe66000 0x00100000

 9437 16:52:09.691816  COREBOOT    8. 0xffe64000 0x00002000

 9438 16:52:09.691937  IMD small region:

 9439 16:52:09.695228    IMD ROOT    0. 0xffffec00 0x00000400

 9440 16:52:09.701982    VPD         1. 0xffffeba0 0x0000004c

 9441 16:52:09.705218    MMC STATUS  2. 0xffffeb80 0x00000004

 9442 16:52:09.708516  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9443 16:52:09.711821  Probing TPM:  done!

 9444 16:52:09.715495  Connected to device vid:did:rid of 1ae0:0028:00

 9445 16:52:09.725164  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

 9446 16:52:09.728575  Initialized TPM device CR50 revision 0

 9447 16:52:09.731848  Checking cr50 for pending updates

 9448 16:52:09.735925  Reading cr50 TPM mode

 9449 16:52:09.745045  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9450 16:52:09.751399  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9451 16:52:09.791609  read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps

 9452 16:52:09.795006  Checking segment from ROM address 0x40100000

 9453 16:52:09.797846  Checking segment from ROM address 0x4010001c

 9454 16:52:09.804672  Loading segment from ROM address 0x40100000

 9455 16:52:09.804781    code (compression=0)

 9456 16:52:09.814823    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9457 16:52:09.821428  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9458 16:52:09.821548  it's not compressed!

 9459 16:52:09.828193  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9460 16:52:09.831091  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9461 16:52:09.851628  Loading segment from ROM address 0x4010001c

 9462 16:52:09.851778    Entry Point 0x80000000

 9463 16:52:09.855486  Loaded segments

 9464 16:52:09.858654  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9465 16:52:09.865092  Jumping to boot code at 0x80000000(0xffe64000)

 9466 16:52:09.871745  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9467 16:52:09.878061  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9468 16:52:09.886457  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9469 16:52:09.889687  Checking segment from ROM address 0x40100000

 9470 16:52:09.892722  Checking segment from ROM address 0x4010001c

 9471 16:52:09.899500  Loading segment from ROM address 0x40100000

 9472 16:52:09.899611    code (compression=1)

 9473 16:52:09.906337    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9474 16:52:09.916304  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9475 16:52:09.916449  using LZMA

 9476 16:52:09.924537  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9477 16:52:09.931020  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9478 16:52:09.934863  Loading segment from ROM address 0x4010001c

 9479 16:52:09.934964    Entry Point 0x54601000

 9480 16:52:09.937810  Loaded segments

 9481 16:52:09.941053  NOTICE:  MT8192 bl31_setup

 9482 16:52:09.948481  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9483 16:52:09.951389  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9484 16:52:09.954794  WARNING: region 0:

 9485 16:52:09.958036  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9486 16:52:09.958130  WARNING: region 1:

 9487 16:52:09.965232  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9488 16:52:09.968124  WARNING: region 2:

 9489 16:52:09.971508  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9490 16:52:09.975072  WARNING: region 3:

 9491 16:52:09.978495  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9492 16:52:09.981981  WARNING: region 4:

 9493 16:52:09.988018  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9494 16:52:09.988145  WARNING: region 5:

 9495 16:52:09.991404  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9496 16:52:09.994877  WARNING: region 6:

 9497 16:52:09.998722  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9498 16:52:09.998812  WARNING: region 7:

 9499 16:52:10.005008  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9500 16:52:10.011749  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9501 16:52:10.014933  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9502 16:52:10.018091  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9503 16:52:10.024939  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9504 16:52:10.028337  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9505 16:52:10.032211  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9506 16:52:10.038634  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9507 16:52:10.041757  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9508 16:52:10.048619  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9509 16:52:10.051549  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9510 16:52:10.055145  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9511 16:52:10.061831  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9512 16:52:10.064931  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9513 16:52:10.068199  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9514 16:52:10.075172  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9515 16:52:10.078564  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9516 16:52:10.081982  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9517 16:52:10.088287  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9518 16:52:10.091472  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9519 16:52:10.098125  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9520 16:52:10.101654  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9521 16:52:10.105034  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9522 16:52:10.111749  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9523 16:52:10.114809  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9524 16:52:10.121925  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9525 16:52:10.124834  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9526 16:52:10.128152  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9527 16:52:10.135053  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9528 16:52:10.138149  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9529 16:52:10.145289  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9530 16:52:10.148503  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9531 16:52:10.151514  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9532 16:52:10.158081  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9533 16:52:10.161612  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9534 16:52:10.165030  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9535 16:52:10.168375  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9536 16:52:10.174628  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9537 16:52:10.178103  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9538 16:52:10.181731  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9539 16:52:10.184599  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9540 16:52:10.187950  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9541 16:52:10.194749  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9542 16:52:10.198087  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9543 16:52:10.201338  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9544 16:52:10.208496  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9545 16:52:10.211318  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9546 16:52:10.214546  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9547 16:52:10.218057  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9548 16:52:10.224880  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9549 16:52:10.228237  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9550 16:52:10.235028  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9551 16:52:10.238296  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9552 16:52:10.241717  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9553 16:52:10.247789  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9554 16:52:10.251721  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9555 16:52:10.258070  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9556 16:52:10.261350  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9557 16:52:10.267753  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9558 16:52:10.271299  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9559 16:52:10.274461  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9560 16:52:10.281070  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9561 16:52:10.284767  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9562 16:52:10.291485  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9563 16:52:10.294553  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9564 16:52:10.301331  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9565 16:52:10.304445  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9566 16:52:10.311174  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9567 16:52:10.314617  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9568 16:52:10.317813  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9569 16:52:10.324481  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9570 16:52:10.327756  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9571 16:52:10.334092  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9572 16:52:10.337788  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9573 16:52:10.344164  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9574 16:52:10.347429  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9575 16:52:10.351319  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9576 16:52:10.357533  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9577 16:52:10.361022  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9578 16:52:10.367884  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9579 16:52:10.371015  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9580 16:52:10.378533  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9581 16:52:10.381641  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9582 16:52:10.388086  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9583 16:52:10.390991  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9584 16:52:10.394197  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9585 16:52:10.401029  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9586 16:52:10.404189  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9587 16:52:10.411373  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9588 16:52:10.414288  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9589 16:52:10.417559  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9590 16:52:10.424421  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9591 16:52:10.427869  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9592 16:52:10.434823  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9593 16:52:10.438147  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9594 16:52:10.444828  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9595 16:52:10.448270  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9596 16:52:10.450904  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9597 16:52:10.457732  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9598 16:52:10.461264  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9599 16:52:10.464406  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9600 16:52:10.468165  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9601 16:52:10.474598  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9602 16:52:10.477853  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9603 16:52:10.484582  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9604 16:52:10.487372  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9605 16:52:10.490886  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9606 16:52:10.497271  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9607 16:52:10.500579  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9608 16:52:10.508153  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9609 16:52:10.511002  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9610 16:52:10.514336  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9611 16:52:10.520793  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9612 16:52:10.524516  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9613 16:52:10.530787  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9614 16:52:10.534032  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9615 16:52:10.537388  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9616 16:52:10.544225  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9617 16:52:10.547415  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9618 16:52:10.550598  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9619 16:52:10.557441  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9620 16:52:10.560642  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9621 16:52:10.564144  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9622 16:52:10.567064  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9623 16:52:10.573644  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9624 16:52:10.577307  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9625 16:52:10.580325  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9626 16:52:10.586883  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9627 16:52:10.590602  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9628 16:52:10.597332  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9629 16:52:10.600489  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9630 16:52:10.603926  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9631 16:52:10.610721  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9632 16:52:10.614249  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9633 16:52:10.620625  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9634 16:52:10.623949  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9635 16:52:10.626759  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9636 16:52:10.634009  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9637 16:52:10.636796  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9638 16:52:10.640245  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9639 16:52:10.647060  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9640 16:52:10.650047  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9641 16:52:10.656826  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9642 16:52:10.660422  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9643 16:52:10.663905  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9644 16:52:10.670337  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9645 16:52:10.673865  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9646 16:52:10.680314  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9647 16:52:10.683380  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9648 16:52:10.686798  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9649 16:52:10.693370  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9650 16:52:10.696885  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9651 16:52:10.700581  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9652 16:52:10.706551  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9653 16:52:10.709987  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9654 16:52:10.716645  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9655 16:52:10.719872  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9656 16:52:10.723370  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9657 16:52:10.730126  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9658 16:52:10.733450  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9659 16:52:10.740320  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9660 16:52:10.742993  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9661 16:52:10.746473  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9662 16:52:10.753181  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9663 16:52:10.756404  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9664 16:52:10.763135  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9665 16:52:10.766243  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9666 16:52:10.769808  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9667 16:52:10.776128  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9668 16:52:10.779676  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9669 16:52:10.786450  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9670 16:52:10.789048  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9671 16:52:10.792919  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9672 16:52:10.798968  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9673 16:52:10.802319  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9674 16:52:10.809449  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9675 16:52:10.812429  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9676 16:52:10.815578  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9677 16:52:10.822305  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9678 16:52:10.825852  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9679 16:52:10.832466  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9680 16:52:10.835500  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9681 16:52:10.839381  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9682 16:52:10.846280  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9683 16:52:10.849278  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9684 16:52:10.855929  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9685 16:52:10.858985  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9686 16:52:10.862330  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9687 16:52:10.869313  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9688 16:52:10.872600  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9689 16:52:10.878927  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9690 16:52:10.882257  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9691 16:52:10.885365  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9692 16:52:10.892402  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9693 16:52:10.896088  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9694 16:52:10.902011  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9695 16:52:10.905876  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9696 16:52:10.908550  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9697 16:52:10.915599  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9698 16:52:10.918470  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9699 16:52:10.924968  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9700 16:52:10.928863  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9701 16:52:10.935241  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9702 16:52:10.938518  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9703 16:52:10.942004  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9704 16:52:10.948209  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9705 16:52:10.951933  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9706 16:52:10.958306  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9707 16:52:10.961774  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9708 16:52:10.968221  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9709 16:52:10.971944  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9710 16:52:10.975092  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9711 16:52:10.981909  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9712 16:52:10.984717  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9713 16:52:10.991771  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9714 16:52:10.995168  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9715 16:52:10.997996  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9716 16:52:11.005006  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9717 16:52:11.008160  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9718 16:52:11.015226  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9719 16:52:11.018462  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9720 16:52:11.025801  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9721 16:52:11.028169  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9722 16:52:11.031400  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9723 16:52:11.038296  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9724 16:52:11.041483  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9725 16:52:11.048236  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9726 16:52:11.051318  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9727 16:52:11.054634  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9728 16:52:11.061200  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9729 16:52:11.064701  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9730 16:52:11.067963  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9731 16:52:11.071701  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9732 16:52:11.077798  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9733 16:52:11.081186  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9734 16:52:11.084544  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9735 16:52:11.091106  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9736 16:52:11.094578  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9737 16:52:11.098014  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9738 16:52:11.104533  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9739 16:52:11.107928  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9740 16:52:11.111370  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9741 16:52:11.117676  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9742 16:52:11.121332  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9743 16:52:11.128447  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9744 16:52:11.131504  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9745 16:52:11.134525  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9746 16:52:11.140939  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9747 16:52:11.144302  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9748 16:52:11.148008  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9749 16:52:11.154611  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9750 16:52:11.157903  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9751 16:52:11.164431  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9752 16:52:11.167781  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9753 16:52:11.170833  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9754 16:52:11.177578  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9755 16:52:11.180895  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9756 16:52:11.184487  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9757 16:52:11.190944  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9758 16:52:11.194281  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9759 16:52:11.197710  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9760 16:52:11.204236  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9761 16:52:11.207616  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9762 16:52:11.213994  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9763 16:52:11.217503  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9764 16:52:11.220811  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9765 16:52:11.227355  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9766 16:52:11.230486  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9767 16:52:11.234109  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9768 16:52:11.241131  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9769 16:52:11.243986  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9770 16:52:11.247261  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9771 16:52:11.250875  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9772 16:52:11.257579  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9773 16:52:11.260590  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9774 16:52:11.263772  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9775 16:52:11.267182  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9776 16:52:11.273865  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9777 16:52:11.277367  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9778 16:52:11.280700  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9779 16:52:11.283523  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9780 16:52:11.290489  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9781 16:52:11.293405  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9782 16:52:11.297035  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9783 16:52:11.303557  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9784 16:52:11.307068  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9785 16:52:11.313132  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9786 16:52:11.316559  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9787 16:52:11.323471  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9788 16:52:11.326488  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9789 16:52:11.329882  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9790 16:52:11.336825  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9791 16:52:11.340114  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9792 16:52:11.346758  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9793 16:52:11.349936  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9794 16:52:11.353720  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9795 16:52:11.359774  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9796 16:52:11.363044  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9797 16:52:11.369587  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9798 16:52:11.373226  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9799 16:52:11.376676  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9800 16:52:11.382688  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9801 16:52:11.386079  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9802 16:52:11.392998  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9803 16:52:11.396489  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9804 16:52:11.402951  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9805 16:52:11.406364  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9806 16:52:11.409652  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9807 16:52:11.416541  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9808 16:52:11.419915  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9809 16:52:11.423425  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9810 16:52:11.429711  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9811 16:52:11.433036  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9812 16:52:11.439596  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9813 16:52:11.443080  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9814 16:52:11.446038  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9815 16:52:11.453295  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9816 16:52:11.455907  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9817 16:52:11.463178  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9818 16:52:11.466148  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9819 16:52:11.473126  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9820 16:52:11.476140  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9821 16:52:11.479344  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9822 16:52:11.486119  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9823 16:52:11.489389  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9824 16:52:11.495785  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9825 16:52:11.499629  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9826 16:52:11.503095  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9827 16:52:11.509132  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9828 16:52:11.512635  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9829 16:52:11.519458  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9830 16:52:11.522816  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9831 16:52:11.525792  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9832 16:52:11.532692  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9833 16:52:11.535936  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9834 16:52:11.542538  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9835 16:52:11.545790  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9836 16:52:11.552336  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9837 16:52:11.555635  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9838 16:52:11.559304  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9839 16:52:11.566321  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9840 16:52:11.569239  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9841 16:52:11.575600  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9842 16:52:11.579215  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9843 16:52:11.582785  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9844 16:52:11.589373  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9845 16:52:11.591997  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9846 16:52:11.598954  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9847 16:52:11.602464  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9848 16:52:11.605365  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9849 16:52:11.612232  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9850 16:52:11.615583  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9851 16:52:11.622054  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9852 16:52:11.625492  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9853 16:52:11.628708  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9854 16:52:11.635209  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9855 16:52:11.639097  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9856 16:52:11.645715  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9857 16:52:11.648601  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9858 16:52:11.655535  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9859 16:52:11.658888  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9860 16:52:11.665025  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9861 16:52:11.668935  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9862 16:52:11.671821  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9863 16:52:11.678551  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9864 16:52:11.681794  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9865 16:52:11.688353  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9866 16:52:11.692218  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9867 16:52:11.698431  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9868 16:52:11.701615  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9869 16:52:11.705543  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9870 16:52:11.711940  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9871 16:52:11.715299  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9872 16:52:11.722085  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9873 16:52:11.724961  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9874 16:52:11.731921  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9875 16:52:11.735116  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9876 16:52:11.738357  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9877 16:52:11.744848  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9878 16:52:11.748266  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9879 16:52:11.754622  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9880 16:52:11.758224  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9881 16:52:11.764694  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9882 16:52:11.767967  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9883 16:52:11.774963  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9884 16:52:11.777889  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9885 16:52:11.781420  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9886 16:52:11.788045  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9887 16:52:11.791413  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9888 16:52:11.797851  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9889 16:52:11.801243  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9890 16:52:11.807811  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9891 16:52:11.811217  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9892 16:52:11.814206  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9893 16:52:11.821691  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9894 16:52:11.824533  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9895 16:52:11.831480  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9896 16:52:11.834693  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9897 16:52:11.840877  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9898 16:52:11.844218  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9899 16:52:11.847494  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9900 16:52:11.854496  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9901 16:52:11.857835  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9902 16:52:11.864367  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9903 16:52:11.867678  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9904 16:52:11.870962  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9905 16:52:11.877872  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9906 16:52:11.881116  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9907 16:52:11.887437  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9908 16:52:11.891127  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9909 16:52:11.897413  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9910 16:52:11.901423  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9911 16:52:11.907634  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9912 16:52:11.911195  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9913 16:52:11.917563  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9914 16:52:11.920851  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9915 16:52:11.927469  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9916 16:52:11.931013  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9917 16:52:11.937337  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9918 16:52:11.940898  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9919 16:52:11.947247  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9920 16:52:11.950602  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9921 16:52:11.957299  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9922 16:52:11.960368  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9923 16:52:11.967048  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9924 16:52:11.970594  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9925 16:52:11.977381  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9926 16:52:11.980347  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9927 16:52:11.987231  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9928 16:52:11.990653  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9929 16:52:11.996860  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9930 16:52:12.000162  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9931 16:52:12.006720  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9932 16:52:12.010244  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9933 16:52:12.017072  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9934 16:52:12.020435  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9935 16:52:12.023169  INFO:    [APUAPC] vio 0

 9936 16:52:12.026660  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9937 16:52:12.033327  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9938 16:52:12.036501  INFO:    [APUAPC] D0_APC_0: 0x400510

 9939 16:52:12.036594  INFO:    [APUAPC] D0_APC_1: 0x0

 9940 16:52:12.039831  INFO:    [APUAPC] D0_APC_2: 0x1540

 9941 16:52:12.043158  INFO:    [APUAPC] D0_APC_3: 0x0

 9942 16:52:12.046784  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9943 16:52:12.050271  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9944 16:52:12.053215  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9945 16:52:12.056334  INFO:    [APUAPC] D1_APC_3: 0x0

 9946 16:52:12.059771  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9947 16:52:12.063261  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9948 16:52:12.066408  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9949 16:52:12.069746  INFO:    [APUAPC] D2_APC_3: 0x0

 9950 16:52:12.073298  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9951 16:52:12.076285  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9952 16:52:12.079769  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9953 16:52:12.082958  INFO:    [APUAPC] D3_APC_3: 0x0

 9954 16:52:12.086462  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9955 16:52:12.089427  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9956 16:52:12.093369  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9957 16:52:12.096121  INFO:    [APUAPC] D4_APC_3: 0x0

 9958 16:52:12.099719  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9959 16:52:12.102737  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9960 16:52:12.106051  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9961 16:52:12.109510  INFO:    [APUAPC] D5_APC_3: 0x0

 9962 16:52:12.113108  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9963 16:52:12.116077  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9964 16:52:12.119698  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9965 16:52:12.123323  INFO:    [APUAPC] D6_APC_3: 0x0

 9966 16:52:12.126226  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9967 16:52:12.129259  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9968 16:52:12.132815  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9969 16:52:12.135914  INFO:    [APUAPC] D7_APC_3: 0x0

 9970 16:52:12.139448  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9971 16:52:12.142553  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9972 16:52:12.146059  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9973 16:52:12.149901  INFO:    [APUAPC] D8_APC_3: 0x0

 9974 16:52:12.153074  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9975 16:52:12.155761  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9976 16:52:12.159279  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9977 16:52:12.162164  INFO:    [APUAPC] D9_APC_3: 0x0

 9978 16:52:12.165695  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9979 16:52:12.169294  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9980 16:52:12.172310  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9981 16:52:12.175583  INFO:    [APUAPC] D10_APC_3: 0x0

 9982 16:52:12.178927  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9983 16:52:12.182463  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9984 16:52:12.185373  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9985 16:52:12.188793  INFO:    [APUAPC] D11_APC_3: 0x0

 9986 16:52:12.192619  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9987 16:52:12.195470  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9988 16:52:12.198669  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9989 16:52:12.202790  INFO:    [APUAPC] D12_APC_3: 0x0

 9990 16:52:12.205644  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9991 16:52:12.208985  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9992 16:52:12.212188  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9993 16:52:12.215854  INFO:    [APUAPC] D13_APC_3: 0x0

 9994 16:52:12.219327  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9995 16:52:12.222262  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9996 16:52:12.225170  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9997 16:52:12.229089  INFO:    [APUAPC] D14_APC_3: 0x0

 9998 16:52:12.232209  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9999 16:52:12.235433  INFO:    [APUAPC] D15_APC_1: 0xffffffff

10000 16:52:12.238558  INFO:    [APUAPC] D15_APC_2: 0x3fffff

10001 16:52:12.242350  INFO:    [APUAPC] D15_APC_3: 0x0

10002 16:52:12.245116  INFO:    [APUAPC] APC_CON: 0x4

10003 16:52:12.245206  INFO:    [NOCDAPC] D0_APC_0: 0x0

10004 16:52:12.248499  INFO:    [NOCDAPC] D0_APC_1: 0x0

10005 16:52:12.251719  INFO:    [NOCDAPC] D1_APC_0: 0x0

10006 16:52:12.255500  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10007 16:52:12.258342  INFO:    [NOCDAPC] D2_APC_0: 0x0

10008 16:52:12.261770  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10009 16:52:12.265153  INFO:    [NOCDAPC] D3_APC_0: 0x0

10010 16:52:12.268642  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10011 16:52:12.271991  INFO:    [NOCDAPC] D4_APC_0: 0x0

10012 16:52:12.274974  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10013 16:52:12.278179  INFO:    [NOCDAPC] D5_APC_0: 0x0

10014 16:52:12.278265  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10015 16:52:12.281695  INFO:    [NOCDAPC] D6_APC_0: 0x0

10016 16:52:12.285285  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10017 16:52:12.288229  INFO:    [NOCDAPC] D7_APC_0: 0x0

10018 16:52:12.291637  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10019 16:52:12.295286  INFO:    [NOCDAPC] D8_APC_0: 0x0

10020 16:52:12.298446  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10021 16:52:12.301610  INFO:    [NOCDAPC] D9_APC_0: 0x0

10022 16:52:12.305068  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10023 16:52:12.308184  INFO:    [NOCDAPC] D10_APC_0: 0x0

10024 16:52:12.311588  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10025 16:52:12.311676  INFO:    [NOCDAPC] D11_APC_0: 0x0

10026 16:52:12.314937  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10027 16:52:12.318259  INFO:    [NOCDAPC] D12_APC_0: 0x0

10028 16:52:12.321520  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10029 16:52:12.324984  INFO:    [NOCDAPC] D13_APC_0: 0x0

10030 16:52:12.328420  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10031 16:52:12.331287  INFO:    [NOCDAPC] D14_APC_0: 0x0

10032 16:52:12.334775  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10033 16:52:12.337998  INFO:    [NOCDAPC] D15_APC_0: 0x0

10034 16:52:12.341330  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10035 16:52:12.344820  INFO:    [NOCDAPC] APC_CON: 0x4

10036 16:52:12.347875  INFO:    [APUAPC] set_apusys_apc done

10037 16:52:12.351770  INFO:    [DEVAPC] devapc_init done

10038 16:52:12.354487  INFO:    GICv3 without legacy support detected.

10039 16:52:12.357825  INFO:    ARM GICv3 driver initialized in EL3

10040 16:52:12.361336  INFO:    Maximum SPI INTID supported: 639

10041 16:52:12.368081  INFO:    BL31: Initializing runtime services

10042 16:52:12.371044  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10043 16:52:12.374773  INFO:    SPM: enable CPC mode

10044 16:52:12.381821  INFO:    mcdi ready for mcusys-off-idle and system suspend

10045 16:52:12.384790  INFO:    BL31: Preparing for EL3 exit to normal world

10046 16:52:12.387610  INFO:    Entry point address = 0x80000000

10047 16:52:12.391087  INFO:    SPSR = 0x8

10048 16:52:12.396298  

10049 16:52:12.396392  

10050 16:52:12.396458  

10051 16:52:12.399688  Starting depthcharge on Spherion...

10052 16:52:12.399773  

10053 16:52:12.399839  Wipe memory regions:

10054 16:52:12.399899  

10055 16:52:12.400545  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10056 16:52:12.400644  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10057 16:52:12.400729  Setting prompt string to ['asurada:']
10058 16:52:12.400812  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10059 16:52:12.402983  	[0x00000040000000, 0x00000054600000)

10060 16:52:12.525230  

10061 16:52:12.525385  	[0x00000054660000, 0x00000080000000)

10062 16:52:12.785495  

10063 16:52:12.785648  	[0x000000821a7280, 0x000000ffe64000)

10064 16:52:13.530396  

10065 16:52:13.530555  	[0x00000100000000, 0x00000240000000)

10066 16:52:15.421012  

10067 16:52:15.423788  Initializing XHCI USB controller at 0x11200000.

10068 16:52:16.461755  

10069 16:52:16.465147  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10070 16:52:16.465253  

10071 16:52:16.465320  

10072 16:52:16.465380  

10073 16:52:16.465658  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 16:52:16.566057  asurada: tftpboot 192.168.201.1 10576311/tftp-deploy-n2rwzs5_/kernel/image.itb 10576311/tftp-deploy-n2rwzs5_/kernel/cmdline 

10076 16:52:16.566243  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 16:52:16.566359  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10078 16:52:16.571020  tftpboot 192.168.201.1 10576311/tftp-deploy-n2rwzs5_/kernel/image.itp-deploy-n2rwzs5_/kernel/cmdline 

10079 16:52:16.571106  

10080 16:52:16.571172  Waiting for link

10081 16:52:16.731380  

10082 16:52:16.731536  R8152: Initializing

10083 16:52:16.731605  

10084 16:52:16.734813  Version 6 (ocp_data = 5c30)

10085 16:52:16.734897  

10086 16:52:16.738092  R8152: Done initializing

10087 16:52:16.738176  

10088 16:52:16.738242  Adding net device

10089 16:52:18.718940  

10090 16:52:18.719078  done.

10091 16:52:18.719145  

10092 16:52:18.719207  MAC: 00:24:32:30:78:52

10093 16:52:18.719267  

10094 16:52:18.722295  Sending DHCP discover... done.

10095 16:52:18.722379  

10096 16:52:23.586760  Waiting for reply... done.

10097 16:52:23.586922  

10098 16:52:23.586988  Sending DHCP request... done.

10099 16:52:23.589740  

10100 16:52:23.589821  Waiting for reply... done.

10101 16:52:23.589886  

10102 16:52:23.593216  My ip is 192.168.201.14

10103 16:52:23.593297  

10104 16:52:23.596176  The DHCP server ip is 192.168.201.1

10105 16:52:23.596257  

10106 16:52:23.599901  TFTP server IP predefined by user: 192.168.201.1

10107 16:52:23.600021  

10108 16:52:23.606038  Bootfile predefined by user: 10576311/tftp-deploy-n2rwzs5_/kernel/image.itb

10109 16:52:23.606122  

10110 16:52:23.609575  Sending tftp read request... done.

10111 16:52:23.609654  

10112 16:52:23.612756  Waiting for the transfer... 

10113 16:52:23.612843  

10114 16:52:24.180261  00000000 ################################################################

10115 16:52:24.180410  

10116 16:52:24.735858  00080000 ################################################################

10117 16:52:24.736062  

10118 16:52:25.300724  00100000 ################################################################

10119 16:52:25.300861  

10120 16:52:25.866874  00180000 ################################################################

10121 16:52:25.867023  

10122 16:52:26.435672  00200000 ################################################################

10123 16:52:26.435830  

10124 16:52:26.990193  00280000 ################################################################

10125 16:52:26.990327  

10126 16:52:27.547425  00300000 ################################################################

10127 16:52:27.547586  

10128 16:52:28.086579  00380000 ################################################################

10129 16:52:28.086718  

10130 16:52:28.619204  00400000 ################################################################

10131 16:52:28.619339  

10132 16:52:29.182047  00480000 ################################################################

10133 16:52:29.182212  

10134 16:52:29.726255  00500000 ################################################################

10135 16:52:29.726406  

10136 16:52:30.277291  00580000 ################################################################

10137 16:52:30.277454  

10138 16:52:30.817949  00600000 ################################################################

10139 16:52:30.818104  

10140 16:52:31.360174  00680000 ################################################################

10141 16:52:31.360346  

10142 16:52:31.895129  00700000 ################################################################

10143 16:52:31.895281  

10144 16:52:32.430995  00780000 ################################################################

10145 16:52:32.431155  

10146 16:52:32.975727  00800000 ################################################################

10147 16:52:32.975880  

10148 16:52:33.513994  00880000 ################################################################

10149 16:52:33.514133  

10150 16:52:34.063729  00900000 ################################################################

10151 16:52:34.063905  

10152 16:52:34.604529  00980000 ################################################################

10153 16:52:34.604669  

10154 16:52:35.161624  00a00000 ################################################################

10155 16:52:35.161764  

10156 16:52:35.698697  00a80000 ################################################################

10157 16:52:35.698834  

10158 16:52:36.262692  00b00000 ################################################################

10159 16:52:36.262843  

10160 16:52:36.806026  00b80000 ################################################################

10161 16:52:36.806170  

10162 16:52:37.354105  00c00000 ################################################################

10163 16:52:37.354246  

10164 16:52:37.900181  00c80000 ################################################################

10165 16:52:37.900331  

10166 16:52:38.447919  00d00000 ################################################################

10167 16:52:38.448103  

10168 16:52:38.989054  00d80000 ################################################################

10169 16:52:38.989192  

10170 16:52:39.514343  00e00000 ################################################################

10171 16:52:39.514502  

10172 16:52:40.045329  00e80000 ################################################################

10173 16:52:40.045467  

10174 16:52:40.577522  00f00000 ################################################################

10175 16:52:40.577697  

10176 16:52:41.124898  00f80000 ################################################################

10177 16:52:41.125045  

10178 16:52:41.669781  01000000 ################################################################

10179 16:52:41.669933  

10180 16:52:42.224581  01080000 ################################################################

10181 16:52:42.224747  

10182 16:52:42.763574  01100000 ################################################################

10183 16:52:42.763742  

10184 16:52:43.313138  01180000 ################################################################

10185 16:52:43.313283  

10186 16:52:43.874899  01200000 ################################################################

10187 16:52:43.875073  

10188 16:52:44.406993  01280000 ################################################################

10189 16:52:44.407143  

10190 16:52:44.936773  01300000 ################################################################

10191 16:52:44.936925  

10192 16:52:45.455305  01380000 ################################################################

10193 16:52:45.455457  

10194 16:52:45.977885  01400000 ################################################################

10195 16:52:45.978060  

10196 16:52:46.504939  01480000 ################################################################

10197 16:52:46.505119  

10198 16:52:47.033256  01500000 ################################################################

10199 16:52:47.033431  

10200 16:52:47.572185  01580000 ################################################################

10201 16:52:47.572352  

10202 16:52:48.099114  01600000 ################################################################

10203 16:52:48.099265  

10204 16:52:48.627513  01680000 ################################################################

10205 16:52:48.627701  

10206 16:52:49.161575  01700000 ################################################################

10207 16:52:49.161759  

10208 16:52:49.700914  01780000 ################################################################

10209 16:52:49.701072  

10210 16:52:50.226109  01800000 ################################################################

10211 16:52:50.226268  

10212 16:52:50.768568  01880000 ################################################################

10213 16:52:50.768726  

10214 16:52:51.308518  01900000 ################################################################

10215 16:52:51.308664  

10216 16:52:51.861731  01980000 ################################################################

10217 16:52:51.861932  

10218 16:52:52.408777  01a00000 ################################################################

10219 16:52:52.408947  

10220 16:52:52.936975  01a80000 ################################################################

10221 16:52:52.937128  

10222 16:52:53.477924  01b00000 ################################################################

10223 16:52:53.478087  

10224 16:52:54.019849  01b80000 ################################################################

10225 16:52:54.020035  

10226 16:52:54.551255  01c00000 ################################################################

10227 16:52:54.551415  

10228 16:52:55.081880  01c80000 ################################################################

10229 16:52:55.082043  

10230 16:52:55.604492  01d00000 ################################################################

10231 16:52:55.604644  

10232 16:52:56.143015  01d80000 ################################################################

10233 16:52:56.143180  

10234 16:52:56.686331  01e00000 ################################################################

10235 16:52:56.686487  

10236 16:52:57.228082  01e80000 ################################################################

10237 16:52:57.228238  

10238 16:52:57.763271  01f00000 ################################################################

10239 16:52:57.763492  

10240 16:52:58.304847  01f80000 ################################################################

10241 16:52:58.305022  

10242 16:52:58.850817  02000000 ################################################################

10243 16:52:58.850969  

10244 16:52:59.379353  02080000 ################################################################

10245 16:52:59.379511  

10246 16:52:59.922171  02100000 ################################################################

10247 16:52:59.922360  

10248 16:53:00.475147  02180000 ################################################################

10249 16:53:00.475303  

10250 16:53:01.032670  02200000 ################################################################

10251 16:53:01.032850  

10252 16:53:01.567121  02280000 ################################################################

10253 16:53:01.567303  

10254 16:53:02.101718  02300000 ################################################################

10255 16:53:02.101894  

10256 16:53:02.651594  02380000 ################################################################

10257 16:53:02.651757  

10258 16:53:03.180093  02400000 ################################################################

10259 16:53:03.180234  

10260 16:53:03.701560  02480000 ################################################################

10261 16:53:03.701722  

10262 16:53:04.243386  02500000 ################################################################

10263 16:53:04.243518  

10264 16:53:04.809505  02580000 ################################################################

10265 16:53:04.809674  

10266 16:53:05.378825  02600000 ################################################################

10267 16:53:05.378970  

10268 16:53:05.954164  02680000 ################################################################

10269 16:53:05.954383  

10270 16:53:06.497296  02700000 ################################################################

10271 16:53:06.497461  

10272 16:53:07.035682  02780000 ################################################################

10273 16:53:07.035847  

10274 16:53:07.571485  02800000 ################################################################

10275 16:53:07.571637  

10276 16:53:08.151023  02880000 ################################################################

10277 16:53:08.151170  

10278 16:53:08.703270  02900000 ################################################################

10279 16:53:08.703423  

10280 16:53:09.266528  02980000 ################################################################

10281 16:53:09.266689  

10282 16:53:09.813841  02a00000 ################################################################

10283 16:53:09.814012  

10284 16:53:10.339899  02a80000 ################################################################

10285 16:53:10.340044  

10286 16:53:10.884788  02b00000 ################################################################

10287 16:53:10.884963  

10288 16:53:11.429905  02b80000 ################################################################

10289 16:53:11.430065  

10290 16:53:11.983615  02c00000 ################################################################

10291 16:53:11.983757  

10292 16:53:12.532079  02c80000 ################################################################

10293 16:53:12.532227  

10294 16:53:13.078612  02d00000 ################################################################

10295 16:53:13.078743  

10296 16:53:13.641765  02d80000 ################################################################

10297 16:53:13.641896  

10298 16:53:14.164667  02e00000 ################################################################

10299 16:53:14.164832  

10300 16:53:14.722241  02e80000 ################################################################

10301 16:53:14.722404  

10302 16:53:15.259655  02f00000 ################################################################

10303 16:53:15.259820  

10304 16:53:15.722561  02f80000 ######################################################### done.

10305 16:53:15.722696  

10306 16:53:15.725949  The bootfile was 50270022 bytes long.

10307 16:53:15.726050  

10308 16:53:15.729361  Sending tftp read request... done.

10309 16:53:15.729468  

10310 16:53:15.729561  Waiting for the transfer... 

10311 16:53:15.729651  

10312 16:53:15.732476  00000000 # done.

10313 16:53:15.732577  

10314 16:53:15.738934  Command line loaded dynamically from TFTP file: 10576311/tftp-deploy-n2rwzs5_/kernel/cmdline

10315 16:53:15.739023  

10316 16:53:15.752133  The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10317 16:53:15.752229  

10318 16:53:15.752295  Loading FIT.

10319 16:53:15.752357  

10320 16:53:15.755506  Image ramdisk-1 has 40137592 bytes.

10321 16:53:15.755585  

10322 16:53:15.758852  Image fdt-1 has 46924 bytes.

10323 16:53:15.758959  

10324 16:53:15.762406  Image kernel-1 has 10083474 bytes.

10325 16:53:15.762502  

10326 16:53:15.768764  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10327 16:53:15.772259  

10328 16:53:15.788552  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10329 16:53:15.788633  

10330 16:53:15.791862  Choosing best match conf-1 for compat google,spherion-rev2.

10331 16:53:15.797101  

10332 16:53:15.801725  Connected to device vid:did:rid of 1ae0:0028:00

10333 16:53:15.808919  

10334 16:53:15.812328  tpm_get_response: command 0x17b, return code 0x0

10335 16:53:15.812426  

10336 16:53:15.818588  ec_init: CrosEC protocol v3 supported (256, 248)

10337 16:53:15.818694  

10338 16:53:15.821792  tpm_cleanup: add release locality here.

10339 16:53:15.821863  

10340 16:53:15.824951  Shutting down all USB controllers.

10341 16:53:15.825022  

10342 16:53:15.828319  Removing current net device

10343 16:53:15.828396  

10344 16:53:15.831947  Exiting depthcharge with code 4 at timestamp: 92864616

10345 16:53:15.835347  

10346 16:53:15.838391  LZMA decompressing kernel-1 to 0x821a6718

10347 16:53:15.838472  

10348 16:53:15.841914  LZMA decompressing kernel-1 to 0x40000000

10349 16:53:17.106810  

10350 16:53:17.106952  jumping to kernel

10351 16:53:17.107368  end: 2.2.4 bootloader-commands (duration 00:01:05) [common]
10352 16:53:17.107470  start: 2.2.5 auto-login-action (timeout 00:03:20) [common]
10353 16:53:17.107545  Setting prompt string to ['Linux version [0-9]']
10354 16:53:17.107610  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10355 16:53:17.107675  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10356 16:53:17.189633  

10357 16:53:17.193030  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10358 16:53:17.196642  start: 2.2.5.1 login-action (timeout 00:03:20) [common]
10359 16:53:17.196730  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10360 16:53:17.196835  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10361 16:53:17.196914  Using line separator: #'\n'#
10362 16:53:17.196974  No login prompt set.
10363 16:53:17.197037  Parsing kernel messages
10364 16:53:17.197092  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10365 16:53:17.197190  [login-action] Waiting for messages, (timeout 00:03:20)
10366 16:53:17.215595  [    0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun  3 16:27:28 UTC 2023

10367 16:53:17.219143  [    0.000000] random: crng init done

10368 16:53:17.222524  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10369 16:53:17.226151  [    0.000000] efi: UEFI not found.

10370 16:53:17.235807  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10371 16:53:17.242774  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10372 16:53:17.252680  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10373 16:53:17.262724  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10374 16:53:17.269318  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10375 16:53:17.272302  [    0.000000] printk: bootconsole [mtk8250] enabled

10376 16:53:17.281183  [    0.000000] NUMA: No NUMA configuration found

10377 16:53:17.287232  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10378 16:53:17.294190  [    0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]

10379 16:53:17.294274  [    0.000000] Zone ranges:

10380 16:53:17.301343  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10381 16:53:17.304176  [    0.000000]   DMA32    empty

10382 16:53:17.310847  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10383 16:53:17.314049  [    0.000000] Movable zone start for each node

10384 16:53:17.317465  [    0.000000] Early memory node ranges

10385 16:53:17.323809  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10386 16:53:17.330610  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10387 16:53:17.337462  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10388 16:53:17.343633  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10389 16:53:17.350765  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10390 16:53:17.357523  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10391 16:53:17.412611  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10392 16:53:17.419619  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10393 16:53:17.426529  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10394 16:53:17.429610  [    0.000000] psci: probing for conduit method from DT.

10395 16:53:17.436098  [    0.000000] psci: PSCIv1.1 detected in firmware.

10396 16:53:17.439480  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10397 16:53:17.445890  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10398 16:53:17.449507  [    0.000000] psci: SMC Calling Convention v1.2

10399 16:53:17.455838  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10400 16:53:17.459567  [    0.000000] Detected VIPT I-cache on CPU0

10401 16:53:17.466422  [    0.000000] CPU features: detected: GIC system register CPU interface

10402 16:53:17.472707  [    0.000000] CPU features: detected: Virtualization Host Extensions

10403 16:53:17.479201  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10404 16:53:17.486194  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10405 16:53:17.492784  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10406 16:53:17.502238  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10407 16:53:17.505599  [    0.000000] alternatives: applying boot alternatives

10408 16:53:17.512470  [    0.000000] Fallback order for Node 0: 0 

10409 16:53:17.518831  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10410 16:53:17.522266  [    0.000000] Policy zone: Normal

10411 16:53:17.532133  [    0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10412 16:53:17.542034  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10413 16:53:17.554606  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10414 16:53:17.565227  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10415 16:53:17.571192  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10416 16:53:17.574399  <6>[    0.000000] software IO TLB: area num 8.

10417 16:53:17.632541  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10418 16:53:17.781508  <6>[    0.000000] Memory: 7933744K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419024K reserved, 32768K cma-reserved)

10419 16:53:17.788091  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10420 16:53:17.794813  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10421 16:53:17.798058  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10422 16:53:17.804875  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10423 16:53:17.811369  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10424 16:53:17.814952  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10425 16:53:17.824843  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10426 16:53:17.831300  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10427 16:53:17.838229  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10428 16:53:17.844877  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10429 16:53:17.847950  <6>[    0.000000] GICv3: 608 SPIs implemented

10430 16:53:17.851751  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10431 16:53:17.857593  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10432 16:53:17.861292  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10433 16:53:17.867668  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10434 16:53:17.881516  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10435 16:53:17.891074  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10436 16:53:17.900616  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10437 16:53:17.908188  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10438 16:53:17.921167  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10439 16:53:17.927872  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10440 16:53:17.934445  <6>[    0.009180] Console: colour dummy device 80x25

10441 16:53:17.944521  <6>[    0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10442 16:53:17.950831  <6>[    0.024351] pid_max: default: 32768 minimum: 301

10443 16:53:17.954393  <6>[    0.029224] LSM: Security Framework initializing

10444 16:53:17.961094  <6>[    0.034162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10445 16:53:17.970818  <6>[    0.041976] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10446 16:53:17.977712  <6>[    0.051406] cblist_init_generic: Setting adjustable number of callback queues.

10447 16:53:17.984240  <6>[    0.058859] cblist_init_generic: Setting shift to 3 and lim to 1.

10448 16:53:17.990560  <6>[    0.065196] cblist_init_generic: Setting shift to 3 and lim to 1.

10449 16:53:17.997294  <6>[    0.071641] rcu: Hierarchical SRCU implementation.

10450 16:53:18.004038  <6>[    0.076655] rcu: 	Max phase no-delay instances is 1000.

10451 16:53:18.007373  <6>[    0.083673] EFI services will not be available.

10452 16:53:18.014292  <6>[    0.088647] smp: Bringing up secondary CPUs ...

10453 16:53:18.021768  <6>[    0.093731] Detected VIPT I-cache on CPU1

10454 16:53:18.028312  <6>[    0.093803] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10455 16:53:18.034645  <6>[    0.093833] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10456 16:53:18.038148  <6>[    0.094172] Detected VIPT I-cache on CPU2

10457 16:53:18.044517  <6>[    0.094221] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10458 16:53:18.054299  <6>[    0.094237] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10459 16:53:18.057853  <6>[    0.094493] Detected VIPT I-cache on CPU3

10460 16:53:18.064192  <6>[    0.094539] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10461 16:53:18.070738  <6>[    0.094552] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10462 16:53:18.074363  <6>[    0.094856] CPU features: detected: Spectre-v4

10463 16:53:18.080995  <6>[    0.094862] CPU features: detected: Spectre-BHB

10464 16:53:18.084657  <6>[    0.094868] Detected PIPT I-cache on CPU4

10465 16:53:18.090816  <6>[    0.094925] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10466 16:53:18.097701  <6>[    0.094942] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10467 16:53:18.104464  <6>[    0.095241] Detected PIPT I-cache on CPU5

10468 16:53:18.110798  <6>[    0.095304] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10469 16:53:18.117693  <6>[    0.095320] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10470 16:53:18.120578  <6>[    0.095605] Detected PIPT I-cache on CPU6

10471 16:53:18.127587  <6>[    0.095672] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10472 16:53:18.133838  <6>[    0.095688] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10473 16:53:18.140821  <6>[    0.095984] Detected PIPT I-cache on CPU7

10474 16:53:18.147624  <6>[    0.096048] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10475 16:53:18.153986  <6>[    0.096064] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10476 16:53:18.157506  <6>[    0.096112] smp: Brought up 1 node, 8 CPUs

10477 16:53:18.163820  <6>[    0.237348] SMP: Total of 8 processors activated.

10478 16:53:18.167603  <6>[    0.242300] CPU features: detected: 32-bit EL0 Support

10479 16:53:18.177037  <6>[    0.247662] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10480 16:53:18.183848  <6>[    0.256462] CPU features: detected: Common not Private translations

10481 16:53:18.187630  <6>[    0.262937] CPU features: detected: CRC32 instructions

10482 16:53:18.194091  <6>[    0.268322] CPU features: detected: RCpc load-acquire (LDAPR)

10483 16:53:18.200336  <6>[    0.274281] CPU features: detected: LSE atomic instructions

10484 16:53:18.206855  <6>[    0.280098] CPU features: detected: Privileged Access Never

10485 16:53:18.210547  <6>[    0.285878] CPU features: detected: RAS Extension Support

10486 16:53:18.219935  <6>[    0.291486] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10487 16:53:18.223244  <6>[    0.298704] CPU: All CPU(s) started at EL2

10488 16:53:18.229887  <6>[    0.303021] alternatives: applying system-wide alternatives

10489 16:53:18.239202  <6>[    0.313768] devtmpfs: initialized

10490 16:53:18.254393  <6>[    0.322623] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10491 16:53:18.260857  <6>[    0.332588] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10492 16:53:18.267432  <6>[    0.340611] pinctrl core: initialized pinctrl subsystem

10493 16:53:18.270969  <6>[    0.347268] DMI not present or invalid.

10494 16:53:18.277414  <6>[    0.351677] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10495 16:53:18.287732  <6>[    0.358452] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10496 16:53:18.293993  <6>[    0.366032] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10497 16:53:18.303831  <6>[    0.374245] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10498 16:53:18.307415  <6>[    0.382490] audit: initializing netlink subsys (disabled)

10499 16:53:18.317242  <5>[    0.388185] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1

10500 16:53:18.323886  <6>[    0.388882] thermal_sys: Registered thermal governor 'step_wise'

10501 16:53:18.330379  <6>[    0.396152] thermal_sys: Registered thermal governor 'power_allocator'

10502 16:53:18.333794  <6>[    0.402407] cpuidle: using governor menu

10503 16:53:18.340310  <6>[    0.413369] NET: Registered PF_QIPCRTR protocol family

10504 16:53:18.347327  <6>[    0.418849] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10505 16:53:18.350277  <6>[    0.425952] ASID allocator initialised with 32768 entries

10506 16:53:18.357681  <6>[    0.432515] Serial: AMBA PL011 UART driver

10507 16:53:18.366341  <4>[    0.441093] Trying to register duplicate clock ID: 134

10508 16:53:18.419659  <6>[    0.498151] KASLR enabled

10509 16:53:18.434527  <6>[    0.506033] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10510 16:53:18.440906  <6>[    0.513050] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10511 16:53:18.447861  <6>[    0.519540] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10512 16:53:18.454380  <6>[    0.526547] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10513 16:53:18.460960  <6>[    0.533036] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10514 16:53:18.467701  <6>[    0.540041] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10515 16:53:18.473948  <6>[    0.546529] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10516 16:53:18.480580  <6>[    0.553535] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10517 16:53:18.484004  <6>[    0.561060] ACPI: Interpreter disabled.

10518 16:53:18.492433  <6>[    0.567435] iommu: Default domain type: Translated 

10519 16:53:18.499306  <6>[    0.572546] iommu: DMA domain TLB invalidation policy: strict mode 

10520 16:53:18.502694  <5>[    0.579200] SCSI subsystem initialized

10521 16:53:18.509259  <6>[    0.583365] usbcore: registered new interface driver usbfs

10522 16:53:18.515717  <6>[    0.589098] usbcore: registered new interface driver hub

10523 16:53:18.519647  <6>[    0.594650] usbcore: registered new device driver usb

10524 16:53:18.526338  <6>[    0.600727] pps_core: LinuxPPS API ver. 1 registered

10525 16:53:18.535870  <6>[    0.605919] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10526 16:53:18.539075  <6>[    0.615266] PTP clock support registered

10527 16:53:18.542408  <6>[    0.619509] EDAC MC: Ver: 3.0.0

10528 16:53:18.550037  <6>[    0.624643] FPGA manager framework

10529 16:53:18.556323  <6>[    0.628321] Advanced Linux Sound Architecture Driver Initialized.

10530 16:53:18.559539  <6>[    0.635092] vgaarb: loaded

10531 16:53:18.566009  <6>[    0.638259] clocksource: Switched to clocksource arch_sys_counter

10532 16:53:18.569609  <5>[    0.644698] VFS: Disk quotas dquot_6.6.0

10533 16:53:18.576532  <6>[    0.648884] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10534 16:53:18.579558  <6>[    0.656076] pnp: PnP ACPI: disabled

10535 16:53:18.587836  <6>[    0.662743] NET: Registered PF_INET protocol family

10536 16:53:18.597663  <6>[    0.668328] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10537 16:53:18.609547  <6>[    0.680688] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10538 16:53:18.619379  <6>[    0.689503] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10539 16:53:18.625784  <6>[    0.697472] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10540 16:53:18.632199  <6>[    0.706177] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10541 16:53:18.644747  <6>[    0.715932] TCP: Hash tables configured (established 65536 bind 65536)

10542 16:53:18.651005  <6>[    0.722789] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10543 16:53:18.657743  <6>[    0.729988] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10544 16:53:18.663907  <6>[    0.737690] NET: Registered PF_UNIX/PF_LOCAL protocol family

10545 16:53:18.671086  <6>[    0.743837] RPC: Registered named UNIX socket transport module.

10546 16:53:18.673960  <6>[    0.749992] RPC: Registered udp transport module.

10547 16:53:18.680894  <6>[    0.754926] RPC: Registered tcp transport module.

10548 16:53:18.687713  <6>[    0.759858] RPC: Registered tcp NFSv4.1 backchannel transport module.

10549 16:53:18.691094  <6>[    0.766529] PCI: CLS 0 bytes, default 64

10550 16:53:18.693912  <6>[    0.770885] Unpacking initramfs...

10551 16:53:18.711516  <6>[    0.782908] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10552 16:53:18.721383  <6>[    0.791549] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10553 16:53:18.724347  <6>[    0.800385] kvm [1]: IPA Size Limit: 40 bits

10554 16:53:18.730993  <6>[    0.804912] kvm [1]: GICv3: no GICV resource entry

10555 16:53:18.734536  <6>[    0.809934] kvm [1]: disabling GICv2 emulation

10556 16:53:18.741252  <6>[    0.814622] kvm [1]: GIC system register CPU interface enabled

10557 16:53:18.744450  <6>[    0.820785] kvm [1]: vgic interrupt IRQ18

10558 16:53:18.751467  <6>[    0.825156] kvm [1]: VHE mode initialized successfully

10559 16:53:18.757749  <5>[    0.831580] Initialise system trusted keyrings

10560 16:53:18.764323  <6>[    0.836345] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10561 16:53:18.772115  <6>[    0.846538] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10562 16:53:18.778092  <5>[    0.852910] NFS: Registering the id_resolver key type

10563 16:53:18.781598  <5>[    0.858214] Key type id_resolver registered

10564 16:53:18.788387  <5>[    0.862630] Key type id_legacy registered

10565 16:53:18.795065  <6>[    0.866910] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10566 16:53:18.801527  <6>[    0.873833] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10567 16:53:18.808167  <6>[    0.881565] 9p: Installing v9fs 9p2000 file system support

10568 16:53:18.844497  <5>[    0.919332] Key type asymmetric registered

10569 16:53:18.848103  <5>[    0.923667] Asymmetric key parser 'x509' registered

10570 16:53:18.858274  <6>[    0.928808] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10571 16:53:18.861160  <6>[    0.936424] io scheduler mq-deadline registered

10572 16:53:18.864098  <6>[    0.941186] io scheduler kyber registered

10573 16:53:18.883001  <6>[    0.958023] EINJ: ACPI disabled.

10574 16:53:18.915166  <4>[    0.983353] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10575 16:53:18.925193  <4>[    0.993990] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10576 16:53:18.939727  <6>[    1.014783] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10577 16:53:18.948262  <6>[    1.022781] printk: console [ttyS0] disabled

10578 16:53:18.975944  <6>[    1.047434] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10579 16:53:18.982441  <6>[    1.056909] printk: console [ttyS0] enabled

10580 16:53:18.985745  <6>[    1.056909] printk: console [ttyS0] enabled

10581 16:53:18.992274  <6>[    1.065803] printk: bootconsole [mtk8250] disabled

10582 16:53:18.995860  <6>[    1.065803] printk: bootconsole [mtk8250] disabled

10583 16:53:19.002672  <6>[    1.077074] SuperH (H)SCI(F) driver initialized

10584 16:53:19.005608  <6>[    1.082376] msm_serial: driver initialized

10585 16:53:19.019584  <6>[    1.091365] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10586 16:53:19.029852  <6>[    1.099925] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10587 16:53:19.036187  <6>[    1.108468] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10588 16:53:19.046226  <6>[    1.117097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10589 16:53:19.056363  <6>[    1.125802] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10590 16:53:19.062589  <6>[    1.134515] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10591 16:53:19.072487  <6>[    1.143056] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10592 16:53:19.079224  <6>[    1.151859] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10593 16:53:19.089408  <6>[    1.160401] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10594 16:53:19.101283  <6>[    1.176160] loop: module loaded

10595 16:53:19.108013  <6>[    1.182230] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10596 16:53:19.130783  <4>[    1.205497] mtk-pmic-keys: Failed to locate of_node [id: -1]

10597 16:53:19.137459  <6>[    1.212303] megasas: 07.719.03.00-rc1

10598 16:53:19.146625  <6>[    1.221818] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10599 16:53:19.159026  <6>[    1.233639] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10600 16:53:19.175665  <6>[    1.250362] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10601 16:53:19.237321  <6>[    1.304735] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7

10602 16:53:20.312825  <6>[    2.387276] Freeing initrd memory: 39192K

10603 16:53:20.322865  <6>[    2.397509] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10604 16:53:20.334553  <6>[    2.408468] tun: Universal TUN/TAP device driver, 1.6

10605 16:53:20.337486  <6>[    2.414529] thunder_xcv, ver 1.0

10606 16:53:20.340811  <6>[    2.418026] thunder_bgx, ver 1.0

10607 16:53:20.343802  <6>[    2.421523] nicpf, ver 1.0

10608 16:53:20.354314  <6>[    2.425512] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10609 16:53:20.358288  <6>[    2.432989] hns3: Copyright (c) 2017 Huawei Corporation.

10610 16:53:20.364283  <6>[    2.438577] hclge is initializing

10611 16:53:20.367878  <6>[    2.442154] e1000: Intel(R) PRO/1000 Network Driver

10612 16:53:20.374488  <6>[    2.447284] e1000: Copyright (c) 1999-2006 Intel Corporation.

10613 16:53:20.377951  <6>[    2.453297] e1000e: Intel(R) PRO/1000 Network Driver

10614 16:53:20.384411  <6>[    2.458513] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10615 16:53:20.390767  <6>[    2.464697] igb: Intel(R) Gigabit Ethernet Network Driver

10616 16:53:20.397463  <6>[    2.470347] igb: Copyright (c) 2007-2014 Intel Corporation.

10617 16:53:20.404151  <6>[    2.476183] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10618 16:53:20.411027  <6>[    2.482701] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10619 16:53:20.414056  <6>[    2.489160] sky2: driver version 1.30

10620 16:53:20.420297  <6>[    2.494142] VFIO - User Level meta-driver version: 0.3

10621 16:53:20.427540  <6>[    2.502292] usbcore: registered new interface driver usb-storage

10622 16:53:20.434740  <6>[    2.508735] usbcore: registered new device driver onboard-usb-hub

10623 16:53:20.443037  <6>[    2.517754] mt6397-rtc mt6359-rtc: registered as rtc0

10624 16:53:20.453320  <6>[    2.523221] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:53:20 UTC (1685811200)

10625 16:53:20.456647  <6>[    2.532776] i2c_dev: i2c /dev entries driver

10626 16:53:20.473188  <6>[    2.544434] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10627 16:53:20.480148  <6>[    2.554613] sdhci: Secure Digital Host Controller Interface driver

10628 16:53:20.486871  <6>[    2.561050] sdhci: Copyright(c) Pierre Ossman

10629 16:53:20.493355  <6>[    2.566454] Synopsys Designware Multimedia Card Interface Driver

10630 16:53:20.497111  <6>[    2.573051] mmc0: CQHCI version 5.10

10631 16:53:20.503606  <6>[    2.573603] sdhci-pltfm: SDHCI platform and OF driver helper

10632 16:53:20.510540  <6>[    2.584901] ledtrig-cpu: registered to indicate activity on CPUs

10633 16:53:20.521021  <6>[    2.592261] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10634 16:53:20.527906  <6>[    2.599662] usbcore: registered new interface driver usbhid

10635 16:53:20.530976  <6>[    2.605488] usbhid: USB HID core driver

10636 16:53:20.538017  <6>[    2.609730] spi_master spi0: will run message pump with realtime priority

10637 16:53:20.582475  <6>[    2.650050] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10638 16:53:20.601555  <6>[    2.665535] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10639 16:53:20.604600  <6>[    2.679123] mmc0: Command Queue Engine enabled

10640 16:53:20.611833  <6>[    2.680632] cros-ec-spi spi0.0: Chrome EC device registered

10641 16:53:20.618254  <6>[    2.683870] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10642 16:53:20.621933  <6>[    2.696891] mmcblk0: mmc0:0001 DA4128 116 GiB 

10643 16:53:20.631406  <6>[    2.705862]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10644 16:53:20.641319  <6>[    2.706335] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10645 16:53:20.648176  <6>[    2.713245] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10646 16:53:20.651395  <6>[    2.723221] NET: Registered PF_PACKET protocol family

10647 16:53:20.657993  <6>[    2.726990] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10648 16:53:20.661157  <6>[    2.731738] 9pnet: Installing 9P2000 support

10649 16:53:20.668518  <6>[    2.737530] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10650 16:53:20.674574  <5>[    2.741420] Key type dns_resolver registered

10651 16:53:20.677984  <6>[    2.753008] registered taskstats version 1

10652 16:53:20.684327  <5>[    2.757394] Loading compiled-in X.509 certificates

10653 16:53:20.717535  <4>[    2.785693] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10654 16:53:20.728039  <4>[    2.796394] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10655 16:53:20.738700  <3>[    2.809133] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10656 16:53:20.750614  <6>[    2.824644] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10657 16:53:20.756945  <6>[    2.831550] xhci-mtk 11200000.usb: xHCI Host Controller

10658 16:53:20.764158  <6>[    2.837057] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10659 16:53:20.774222  <6>[    2.844904] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10660 16:53:20.780206  <6>[    2.854342] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10661 16:53:20.786861  <6>[    2.860459] xhci-mtk 11200000.usb: xHCI Host Controller

10662 16:53:20.793628  <6>[    2.865947] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10663 16:53:20.800159  <6>[    2.873598] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10664 16:53:20.806505  <6>[    2.881340] hub 1-0:1.0: USB hub found

10665 16:53:20.810031  <6>[    2.885380] hub 1-0:1.0: 1 port detected

10666 16:53:20.819724  <6>[    2.889712] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10667 16:53:20.823510  <6>[    2.898313] hub 2-0:1.0: USB hub found

10668 16:53:20.826741  <6>[    2.902327] hub 2-0:1.0: 1 port detected

10669 16:53:20.834872  <6>[    2.909503] mtk-msdc 11f70000.mmc: Got CD GPIO

10670 16:53:20.852889  <6>[    2.924007] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10671 16:53:20.859446  <6>[    2.932039] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10672 16:53:20.868936  <4>[    2.940014] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10673 16:53:20.879053  <6>[    2.949688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10674 16:53:20.885870  <6>[    2.957769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10675 16:53:20.895395  <6>[    2.965802] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10676 16:53:20.902383  <6>[    2.973724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10677 16:53:20.908859  <6>[    2.981547] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10678 16:53:20.918934  <6>[    2.989370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10679 16:53:20.928963  <6>[    3.000149] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10680 16:53:20.938641  <6>[    3.008517] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10681 16:53:20.945290  <6>[    3.016869] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10682 16:53:20.955084  <6>[    3.025211] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10683 16:53:20.962044  <6>[    3.033554] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10684 16:53:20.971640  <6>[    3.041897] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10685 16:53:20.978057  <6>[    3.050239] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10686 16:53:20.988530  <6>[    3.058582] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10687 16:53:20.994681  <6>[    3.066926] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10688 16:53:21.004622  <6>[    3.075269] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10689 16:53:21.011106  <6>[    3.083612] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10690 16:53:21.021579  <6>[    3.091958] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10691 16:53:21.028024  <6>[    3.100301] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10692 16:53:21.038238  <6>[    3.108644] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10693 16:53:21.044399  <6>[    3.116987] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10694 16:53:21.051641  <6>[    3.125888] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10695 16:53:21.058491  <6>[    3.133304] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10696 16:53:21.065533  <6>[    3.140337] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10697 16:53:21.076110  <6>[    3.147484] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10698 16:53:21.082468  <6>[    3.154777] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10699 16:53:21.092381  <6>[    3.161680] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10700 16:53:21.099367  <6>[    3.170821] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10701 16:53:21.109478  <6>[    3.179947] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10702 16:53:21.119275  <6>[    3.189249] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10703 16:53:21.128887  <6>[    3.198724] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10704 16:53:21.138143  <6>[    3.208198] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10705 16:53:21.148120  <6>[    3.217325] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10706 16:53:21.154873  <6>[    3.226805] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10707 16:53:21.164784  <6>[    3.235932] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10708 16:53:21.174710  <6>[    3.245234] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10709 16:53:21.184933  <6>[    3.255402] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10710 16:53:21.195319  <6>[    3.267325] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10711 16:53:21.234395  <6>[    3.306503] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10712 16:53:21.388311  <6>[    3.462461] hub 1-1:1.0: USB hub found

10713 16:53:21.390905  <6>[    3.466820] hub 1-1:1.0: 4 ports detected

10714 16:53:21.515384  <6>[    3.586879] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10715 16:53:21.542568  <6>[    3.616706] hub 2-1:1.0: USB hub found

10716 16:53:21.545352  <6>[    3.621205] hub 2-1:1.0: 3 ports detected

10717 16:53:21.711078  <6>[    3.782531] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10718 16:53:21.843986  <6>[    3.918493] hub 1-1.4:1.0: USB hub found

10719 16:53:21.847294  <6>[    3.923145] hub 1-1.4:1.0: 2 ports detected

10720 16:53:21.927212  <6>[    3.998772] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10721 16:53:22.142892  <6>[    4.214532] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10722 16:53:22.334883  <6>[    4.406534] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10723 16:53:33.483352  <6>[   15.563103] ALSA device list:

10724 16:53:33.489816  <6>[   15.566358]   No soundcards found.

10725 16:53:33.502364  <6>[   15.578755] Freeing unused kernel memory: 8384K

10726 16:53:33.505274  <6>[   15.583662] Run /init as init process

10727 16:53:33.535107  <6>[   15.611852] NET: Registered PF_INET6 protocol family

10728 16:53:33.542168  <6>[   15.618385] Segment Routing with IPv6

10729 16:53:33.545026  <6>[   15.622340] In-situ OAM (IOAM) with IPv6

10730 16:53:33.580401  <30>[   15.636940] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10731 16:53:33.583492  <30>[   15.660663] systemd[1]: Detected architecture arm64.

10732 16:53:33.583576  

10733 16:53:33.590117  Welcome to Debian GNU/Linux 11 (bullseye)!

10734 16:53:33.590200  

10735 16:53:33.606152  <30>[   15.682697] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10736 16:53:33.745589  <30>[   15.819018] systemd[1]: Queued start job for default target Graphical Interface.

10737 16:53:33.787064  <30>[   15.863841] systemd[1]: Created slice system-getty.slice.

10738 16:53:33.793739  [  OK  ] Created slice system-getty.slice.

10739 16:53:33.810649  <30>[   15.887124] systemd[1]: Created slice system-modprobe.slice.

10740 16:53:33.817259  [  OK  ] Created slice system-modprobe.slice.

10741 16:53:33.834412  <30>[   15.911037] systemd[1]: Created slice system-serial\x2dgetty.slice.

10742 16:53:33.844661  [  OK  ] Created slice system-serial\x2dgetty.slice.

10743 16:53:33.859060  <30>[   15.935553] systemd[1]: Created slice User and Session Slice.

10744 16:53:33.865464  [  OK  ] Created slice User and Session Slice.

10745 16:53:33.885548  <30>[   15.959062] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10746 16:53:33.895286  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10747 16:53:33.913943  <30>[   15.987055] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10748 16:53:33.920449  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10749 16:53:33.940760  <30>[   16.010628] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10750 16:53:33.947239  <30>[   16.022666] systemd[1]: Reached target Local Encrypted Volumes.

10751 16:53:33.954132  [  OK  ] Reached target Local Encrypted Volumes.

10752 16:53:33.970659  <30>[   16.046909] systemd[1]: Reached target Paths.

10753 16:53:33.973796  [  OK  ] Reached target Paths.

10754 16:53:33.989758  <30>[   16.066573] systemd[1]: Reached target Remote File Systems.

10755 16:53:33.996653  [  OK  ] Reached target Remote File Systems.

10756 16:53:34.009945  <30>[   16.086560] systemd[1]: Reached target Slices.

10757 16:53:34.013120  [  OK  ] Reached target Slices.

10758 16:53:34.030374  <30>[   16.106574] systemd[1]: Reached target Swap.

10759 16:53:34.033283  [  OK  ] Reached target Swap.

10760 16:53:34.054109  <30>[   16.126872] systemd[1]: Listening on initctl Compatibility Named Pipe.

10761 16:53:34.060356  [  OK  ] Listening on initctl Compatibility Named Pipe.

10762 16:53:34.066825  <30>[   16.141564] systemd[1]: Listening on Journal Audit Socket.

10763 16:53:34.073445  [  OK  ] Listening on Journal Audit Socket.

10764 16:53:34.086433  <30>[   16.162837] systemd[1]: Listening on Journal Socket (/dev/log).

10765 16:53:34.092559  [  OK  ] Listening on Journal Socket (/dev/log).

10766 16:53:34.110137  <30>[   16.186853] systemd[1]: Listening on Journal Socket.

10767 16:53:34.117035  [  OK  ] Listening on Journal Socket.

10768 16:53:34.133667  <30>[   16.206873] systemd[1]: Listening on Network Service Netlink Socket.

10769 16:53:34.140037  [  OK  ] Listening on Network Service Netlink Socket.

10770 16:53:34.154955  <30>[   16.231322] systemd[1]: Listening on udev Control Socket.

10771 16:53:34.161106  [  OK  ] Listening on udev Control Socket.

10772 16:53:34.178723  <30>[   16.255245] systemd[1]: Listening on udev Kernel Socket.

10773 16:53:34.185345  [  OK  ] Listening on udev Kernel Socket.

10774 16:53:34.218067  <30>[   16.294681] systemd[1]: Mounting Huge Pages File System...

10775 16:53:34.224854           Mounting Huge Pages File System...

10776 16:53:34.240311  <30>[   16.316677] systemd[1]: Mounting POSIX Message Queue File System...

10777 16:53:34.246614           Mounting POSIX Message Queue File System...

10778 16:53:34.264250  <30>[   16.340672] systemd[1]: Mounting Kernel Debug File System...

10779 16:53:34.270892           Mounting Kernel Debug File System...

10780 16:53:34.289408  <30>[   16.362867] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10781 16:53:34.321635  <30>[   16.395042] systemd[1]: Starting Create list of static device nodes for the current kernel...

10782 16:53:34.327958           Starting Create list of st…odes for the current kernel...

10783 16:53:34.348103  <30>[   16.424930] systemd[1]: Starting Load Kernel Module configfs...

10784 16:53:34.354535           Starting Load Kernel Module configfs...

10785 16:53:34.372403  <30>[   16.448865] systemd[1]: Starting Load Kernel Module drm...

10786 16:53:34.378826           Starting Load Kernel Module drm...

10787 16:53:34.397392  <30>[   16.470715] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10788 16:53:34.408059  <30>[   16.484490] systemd[1]: Starting Journal Service...

10789 16:53:34.411354           Starting Journal Service...

10790 16:53:34.428757  <30>[   16.505083] systemd[1]: Starting Load Kernel Modules...

10791 16:53:34.434938           Starting Load Kernel Modules...

10792 16:53:34.455875  <30>[   16.529174] systemd[1]: Starting Remount Root and Kernel File Systems...

10793 16:53:34.462478           Starting Remount Root and Kernel File Systems...

10794 16:53:34.476078  <30>[   16.552960] systemd[1]: Starting Coldplug All udev Devices...

10795 16:53:34.482770           Starting Coldplug All udev Devices...

10796 16:53:34.500181  <30>[   16.577053] systemd[1]: Mounted Huge Pages File System.

10797 16:53:34.506870  [  OK  ] Mounted Huge Pages File System.

10798 16:53:34.522392  <30>[   16.598971] systemd[1]: Started Journal Service.

10799 16:53:34.528647  [  OK  ] Started Journal Service.

10800 16:53:34.543594  [  OK  ] Mounted POSIX Message Queue File System.

10801 16:53:34.558764  [  OK  ] Mounted Kernel Debug File System.

10802 16:53:34.578056  [  OK  ] Finished Create list of st… nodes for the current kernel.

10803 16:53:34.599484  [  OK  ] Finished Load Kernel Module configfs.

10804 16:53:34.619554  [  OK  ] Finished Load Kernel Module drm.

10805 16:53:34.634968  [  OK  ] Finished Load Kernel Modules.

10806 16:53:34.655045  [FAILED] Failed to start Remount Root and Kernel File Systems.

10807 16:53:34.669788  See 'systemctl status systemd-remount-fs.service' for details.

10808 16:53:34.722780           Mounting Kernel Configuration File System...

10809 16:53:34.740564           Starting Flush Journal to Persistent Storage...

10810 16:53:34.758699  <46>[   16.831793] systemd-journald[175]: Received client request to flush runtime journal.

10811 16:53:34.766424           Starting Load/Save Random Seed...

10812 16:53:34.785270           Starting Apply Kernel Variables...

10813 16:53:34.801522           Starting Create System Users...

10814 16:53:34.816275  [  OK  ] Mounted Kernel Configuration File System.

10815 16:53:34.838822  [  OK  ] Finished Flush Journal to Persistent Storage.

10816 16:53:34.854978  [  OK  ] Finished Load/Save Random Seed.

10817 16:53:34.870828  [  OK  ] Finished Apply Kernel Variables.

10818 16:53:34.886904  [  OK  ] Finished Coldplug All udev Devices.

10819 16:53:34.903390  [  OK  ] Finished Create System Users.

10820 16:53:34.946439           Starting Create Static Device Nodes in /dev...

10821 16:53:34.968785  [  OK  ] Finished Create Static Device Nodes in /dev.

10822 16:53:34.982096  [  OK  ] Reached target Local File Systems (Pre).

10823 16:53:34.997980  [  OK  ] Reached target Local File Systems.

10824 16:53:35.042104           Starting Create Volatile Files and Directories...

10825 16:53:35.065672           Starting Rule-based Manage…for Device Events and Files...

10826 16:53:35.083173  [  OK  ] Finished Create Volatile Files and Directories.

10827 16:53:35.103129  [  OK  ] Started Rule-based Manager for Device Events and Files.

10828 16:53:35.160405           Starting Network Service...

10829 16:53:35.180940           Starting Network Time Synchronization...

10830 16:53:35.201836           Starting Update UTMP about System Boot/Shutdown...

10831 16:53:35.250223  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10832 16:53:35.262724  [  OK  ] Started Network Service.

10833 16:53:35.293562  [  OK  ] Found device /dev/ttyS0.

10834 16:53:35.311589  [  OK  ] Started Network Time Synchronization.

10835 16:53:35.341889  [  OK  ] Created slice system-systemd\x2dbacklight.slice<3>[   17.414835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10836 16:53:35.348950  <6>[   17.422873] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10837 16:53:35.349030  .

10838 16:53:35.358201  <3>[   17.423866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10839 16:53:35.364957  <3>[   17.439483] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10840 16:53:35.375294  <6>[   17.443408] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10841 16:53:35.378280  <6>[   17.450067] remoteproc remoteproc0: scp is available

10842 16:53:35.388452  <6>[   17.455350] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10843 16:53:35.394794  <3>[   17.460910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10844 16:53:35.401378  <6>[   17.461493] remoteproc remoteproc0: powering up scp

10845 16:53:35.408104  <6>[   17.461505] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10846 16:53:35.414857  <6>[   17.461530] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10847 16:53:35.425365  <6>[   17.469422] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10848 16:53:35.431214  <3>[   17.477474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10849 16:53:35.437697  <4>[   17.483447] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10850 16:53:35.447561  <3>[   17.490967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10851 16:53:35.454388  <3>[   17.490977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10852 16:53:35.464622  <3>[   17.490985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10853 16:53:35.470791  <3>[   17.496644] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10854 16:53:35.477402  <4>[   17.534564] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10855 16:53:35.487419  <3>[   17.551960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10856 16:53:35.494354  <3>[   17.568813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10857 16:53:35.503804  <3>[   17.576929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10858 16:53:35.514175  [  OK  [<6>[   17.585159] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10859 16:53:35.520381  0m] Reached targ<6>[   17.585159] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10860 16:53:35.530368  et Syst<3>[   17.585182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10861 16:53:35.536897  em Time Set.<6>[   17.588148] usbcore: registered new interface driver r8152

10862 16:53:35.536975  

10863 16:53:35.543738  <6>[   17.588205] mc: Linux media interface: v0.10

10864 16:53:35.550166  <6>[   17.595070] remoteproc remoteproc0: remote processor scp is now up

10865 16:53:35.557095  <3>[   17.603386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10866 16:53:35.563806  <6>[   17.605588] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10867 16:53:35.570924  <6>[   17.617361] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10868 16:53:35.580745  <3>[   17.619986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10869 16:53:35.587015  <3>[   17.620007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10870 16:53:35.597057  <3>[   17.620019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10871 16:53:35.603306  <6>[   17.624710] pci_bus 0000:00: root bus resource [bus 00-ff]

10872 16:53:35.610418  <3>[   17.631355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10873 16:53:35.620172  <4>[   17.631626] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10874 16:53:35.623771  <4>[   17.631626] Fallback method does not support PEC.

10875 16:53:35.630429  <6>[   17.639355] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10876 16:53:35.636813  <6>[   17.640845] videodev: Linux video capture interface: v2.00

10877 16:53:35.646893  <3>[   17.649678] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10878 16:53:35.657771  <6>[   17.654009] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10879 16:53:35.664470  <6>[   17.666799] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10880 16:53:35.671067  <6>[   17.670548] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10881 16:53:35.680888  <6>[   17.686980] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10882 16:53:35.690678  <6>[   17.692260] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10883 16:53:35.694347  <6>[   17.692513] pci 0000:00:00.0: supports D1 D2

10884 16:53:35.700648  <6>[   17.698590] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10885 16:53:35.710685  <6>[   17.706632] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10886 16:53:35.717657  <6>[   17.713286] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10887 16:53:35.727202  <3>[   17.735421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10888 16:53:35.733732  <3>[   17.736177] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6

10889 16:53:35.743587  <6>[   17.741439] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10890 16:53:35.750217  <4>[   17.741968] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2

10891 16:53:35.761012  <4>[   17.741980] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)

10892 16:53:35.767268  <6>[   17.752534] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10893 16:53:35.774365  <6>[   17.759714] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10894 16:53:35.781280  <6>[   17.764129] usbcore: registered new interface driver cdc_ether

10895 16:53:35.788426  <6>[   17.766830] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10896 16:53:35.798119  <6>[   17.770948] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10897 16:53:35.804562  <6>[   17.770978] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10898 16:53:35.808711  <6>[   17.772827] Bluetooth: Core ver 2.22

10899 16:53:35.811863  <6>[   17.772892] NET: Registered PF_BLUETOOTH protocol family

10900 16:53:35.818759  <6>[   17.772895] Bluetooth: HCI device and connection manager initialized

10901 16:53:35.825383  <6>[   17.772908] Bluetooth: HCI socket layer initialized

10902 16:53:35.832286  <6>[   17.772931] Bluetooth: L2CAP socket layer initialized

10903 16:53:35.835216  <6>[   17.772943] Bluetooth: SCO socket layer initialized

10904 16:53:35.841691  <6>[   17.783176] usbcore: registered new interface driver r8153_ecm

10905 16:53:35.845313  <6>[   17.786464] r8152 2-1.3:1.0 eth0: v1.12.13

10906 16:53:35.852529  <6>[   17.791876] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10907 16:53:35.858845  <6>[   17.799612] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10908 16:53:35.865487  <6>[   17.807515] pci 0000:01:00.0: supports D1 D2

10909 16:53:35.872438  <6>[   17.812534] r8152 2-1.3:1.0 enx002432307852: renamed from eth0

10910 16:53:35.876159  <6>[   17.817799] usbcore: registered new interface driver btusb

10911 16:53:35.889429  <6>[   17.818102] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10912 16:53:35.898930  <4>[   17.818375] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10913 16:53:35.905968  <3>[   17.818388] Bluetooth: hci0: Failed to load firmware file (-2)

10914 16:53:35.912230  <3>[   17.818395] Bluetooth: hci0: Failed to set up firmware (-2)

10915 16:53:35.922975  <4>[   17.818401] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10916 16:53:35.929311  <6>[   17.818882] usbcore: registered new interface driver uvcvideo

10917 16:53:35.936099  <6>[   17.824804] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10918 16:53:35.942790  <6>[   17.838357] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10919 16:53:35.949864  <6>[   17.851243] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10920 16:53:35.956288  <6>[   17.856540] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10921 16:53:35.966626  <3>[   17.858035] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6

10922 16:53:35.973388  <3>[   17.864395] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10923 16:53:35.983511  <3>[   17.865148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6

10924 16:53:35.990521  <6>[   17.870852] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10925 16:53:35.997688  <6>[   17.870866] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10926 16:53:36.007220  <3>[   17.899413] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10927 16:53:36.014426  <6>[   17.901827] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10928 16:53:36.024240  <3>[   17.934954] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10929 16:53:36.030838  <6>[   17.935268] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10930 16:53:36.040490  <3>[   17.963632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10931 16:53:36.046938  <6>[   17.971068] pci 0000:00:00.0: PCI bridge to [bus 01]

10932 16:53:36.053740  <6>[   17.971077] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10933 16:53:36.063886  <3>[   18.001637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10934 16:53:36.070670  <6>[   18.004141] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10935 16:53:36.077290  [  OK  [<6>[   18.152071] pcieport 0000:00:00.0: PME: Signaling with IRQ 283

10936 16:53:36.083675  0m] Reached targ<6>[   18.159624] pcieport 0000:00:00.0: AER: enabled with IRQ 283

10937 16:53:36.086799  et System Time Synchronized.

10938 16:53:36.105087  <5>[   18.178183] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10939 16:53:36.125377  <5>[   18.198384] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10940 16:53:36.131160  <4>[   18.205364] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10941 16:53:36.138151  <6>[   18.214281] cfg80211: failed to load regulatory.db

10942 16:53:36.144386           Starting Load/Save Screen …of leds:white:kbd_backlight...

10943 16:53:36.169239           Starting Network Name Resolution...

10944 16:53:36.188494  [  OK  [<6>[   18.262973] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10945 16:53:36.194754  0m] Finished [0<6>[   18.270684] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10946 16:53:36.201776  ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight.

10947 16:53:36.221933  <6>[   18.298713] mt7921e 0000:01:00.0: ASIC revision: 79610010

10948 16:53:36.283838  [  OK  ] Started Network Name Resolution.

10949 16:53:36.331565  <4>[   18.402093] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10950 16:53:36.390197  [  OK  ] Reached target Bluetooth.

10951 16:53:36.405818  [  OK  ] Reached target Network.

10952 16:53:36.424768  [  OK  ] Reached target Host and Network Name Lookups.

10953 16:53:36.455470  [  OK  ] Reached targ<4>[   18.525230] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10954 16:53:36.459054  et System Initialization.

10955 16:53:36.478617  [  OK  ] Started Discard unused blocks once a week.

10956 16:53:36.493092  [  OK  ] Started Daily Cleanup of Temporary Directories.

10957 16:53:36.505646  [  OK  ] Reached target Timers.

10958 16:53:36.525741  [  OK  ] Listening on D-Bus System Message Bus Socket.

10959 16:53:36.537463  [  OK  ] Reached target Sockets.

10960 16:53:36.560330  [  OK  ] Reached target Basic System.

10961 16:53:36.575440  <4>[   18.645668] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10962 16:53:36.585641  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10963 16:53:36.646340  [  OK  ] Started D-Bus System Message Bus.

10964 16:53:36.672906           Starting User Login Management...

10965 16:53:36.695603  <4>[   18.765602] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10966 16:53:36.707855           Starting Permit User Sessions...

10967 16:53:36.726022           Starting Load/Save RF Kill Switch Status...

10968 16:53:36.742171  [  OK  ] Started Load/Save RF Kill Switch Status.

10969 16:53:36.763452  [  OK  ] Finished Permit User Sessions.

10970 16:53:36.783476  [  OK  ] Started User Login Management.

10971 16:53:36.824251  <4>[   18.894367] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10972 16:53:36.834781  [  OK  ] Started Getty on tty1.

10973 16:53:36.853529  [  OK  ] Started Serial Getty on ttyS0.

10974 16:53:36.870536  [  OK  ] Reached target Login Prompts.

10975 16:53:36.886076  [  OK  ] Reached target Multi-User System.

10976 16:53:36.901619  [  OK  ] Reached target Graphical Interface.

10977 16:53:36.942430  <4>[   19.012691] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10978 16:53:36.949030           Starting Update UTMP about System Runlevel Changes...

10979 16:53:36.982633  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10980 16:53:37.026326  

10981 16:53:37.026452  

10982 16:53:37.029721  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10983 16:53:37.029820  

10984 16:53:37.032632  debian-bullseye-arm64 login: root (automatic login)

10985 16:53:37.032705  

10986 16:53:37.032765  

10987 16:53:37.063566  Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMP<4>[   19.134532] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10988 16:53:37.067158  T Sat Jun  3 16:27:28 UTC 2023 aarch64

10989 16:53:37.067246  

10990 16:53:37.073648  The programs included with the Debian GNU/Linux system are free software;

10991 16:53:37.080045  the exact distribution terms for each program are described in the

10992 16:53:37.084021  individual files in /usr/share/doc/*/copyright.

10993 16:53:37.084131  

10994 16:53:37.090390  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

10995 16:53:37.093378  permitted by applicable law.

10996 16:53:37.093926  Matched prompt #10: / #
10998 16:53:37.094264  Setting prompt string to ['/ #']
10999 16:53:37.094393  end: 2.2.5.1 login-action (duration 00:00:20) [common]
11001 16:53:37.094716  end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11002 16:53:37.094848  start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11003 16:53:37.094957  Setting prompt string to ['/ #']
11004 16:53:37.095039  Forcing a shell prompt, looking for ['/ #']
11006 16:53:37.145241  / # 

11007 16:53:37.145378  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11008 16:53:37.145515  Waiting using forced prompt support (timeout 00:02:30)
11009 16:53:37.150799  

11010 16:53:37.151106  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11011 16:53:37.151226  start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11012 16:53:37.151323  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11013 16:53:37.151413  end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11014 16:53:37.151497  end: 2 depthcharge-action (duration 00:02:00) [common]
11015 16:53:37.151616  start: 3 lava-test-retry (timeout 00:07:41) [common]
11016 16:53:37.151773  start: 3.1 lava-test-shell (timeout 00:07:41) [common]
11017 16:53:37.151880  Using namespace: common
11019 16:53:37.252225  / # #

11020 16:53:37.252383  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11021 16:53:37.252505  <4>[   19.257180] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11022 16:53:37.257407  #

11023 16:53:37.257684  Using /lava-10576311
11025 16:53:37.357946  / # export SHELL=/bin/sh

11026 16:53:37.358150  <4>[   19.381053] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11027 16:53:37.362908  export SHELL=/bin/sh

11029 16:53:37.463392  / # . /lava-10576311/environment

11030 16:53:37.463631  . /lava-10576311/environment<4>[   19.501009] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11031 16:53:37.463759  <6>[   19.508025] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready

11032 16:53:37.463865  <6>[   19.520534] r8152 2-1.3:1.0 enx002432307852: carrier on

11033 16:53:37.468962  

11035 16:53:37.569449  / # /lava-10576311/bin/lava-test-runner /lava-10576311/0

11036 16:53:37.569602  Test shell timeout: 10s (minimum of the action and connection timeout)
11037 16:53:37.570139  /lava-10576311/bin/lava-test-runner /lava-10576311/0<3>[   19.626769] mt7921e 0000:01:00.0: hardware init failed

11038 16:53:37.574487  

11039 16:53:37.616087  + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc

11040 16:53:37.616189  + cd /lava-10576311/0/tests/0_v4l2-compliance-mtk-vcodec-enc

11041 16:53:37.616278  + cat uuid

11042 16:53:37.616359  + UUID=10576311_1.5.2.3.1

11043 16:53:37.616440  + set +x

11044 16:53:37.616519  <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10576311_1.5.2.3.1>

11045 16:53:37.616794  Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10576311_1.5.2.3.1
11046 16:53:37.616898  Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10576311_1.5.2.3.1)
11047 16:53:37.617025  Skipping test definition patterns.
11048 16:53:37.617198  + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc

11049 16:53:37.623401  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>

11050 16:53:37.623649  Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11052 16:53:37.629944  device: /dev/vide<4>[   19.704593] use of bytesused == 0 is deprecated and will be removed in the future,

11053 16:53:37.633588  o2

11054 16:53:37.636868  <4>[   19.713794] use the actual size instead.

11055 16:53:37.643845  <4>[   19.720603] ------------[ cut here ]------------

11056 16:53:37.650184  <4>[   19.725487] get_vaddr_frames() cannot follow VM_IO mapping

11057 16:53:37.663201  <4>[   19.725642] WARNING: CPU: 6 PID: 305 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]

11058 16:53:37.709640  <4>[   19.743746] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 mtk_vcodec_enc mtk_vcodec_common btusb btintel mtk_vpu btmtk v4l2_mem2mem uvcvideo btrtl videobuf2_vmalloc videobuf2_dma_contig r8153_ecm btbcm videobuf2_memops cdc_ether videobuf2_v4l2 bluetooth cros_ec_rpmsg videobuf2_common usbnet ecdh_generic ecc videodev rfkill r8152 crct10dif_ce mc sbs_battery elan_i2c elants_i2c cros_ec_chardev pcie_mediatek_gen3 mtk_scp hid_google_hammer hid_vivaldi_common cros_ec_typec mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6

11059 16:53:37.719283  <4>[   19.793133] CPU: 6 PID: 305 Comm: v4l2-compliance Not tainted 6.1.31 #1

11060 16:53:37.722803  <4>[   19.799999] Hardware name: Google Spherion (rev0 - 3) (DT)

11061 16:53:37.729786  <4>[   19.805733] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)

11062 16:53:37.736114  <4>[   19.812946] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]

11063 16:53:37.742770  <4>[   19.819044] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]

11064 16:53:37.746146  <4>[   19.825140] sp : ffff8000091c3850

11065 16:53:37.752639  <4>[   19.828703] x29: ffff8000091c3850 x28: ffffccc0bec2a000 x27: ffffccc0bec26238

11066 16:53:37.762406  <4>[   19.836092] x26: 0000000000000000 x25: ffffccc0c58dacb8 x24: ffff6ed7cf001298

11067 16:53:37.768993  <4>[   19.843479] x23: ffff6ed7cc44dc00 x22: ffff6ed7c0d48010 x21: 0000000000000000

11068 16:53:37.775527  <4>[   19.850867] x20: 00000000fffffff2 x19: ffff6ed7c03a0b80 x18: fffffffffffe95b8

11069 16:53:37.782009  <4>[   19.858254] x17: 0000000000000000 x16: ffffccc0c546d150 x15: 0000000000000038

11070 16:53:37.791847  <4>[   19.865642] x14: ffffccc0c61c34a8 x13: 000000000000063c x12: 0000000000000214

11071 16:53:37.798699  <4>[   19.873029] x11: fffffffffffe95b8 x10: fffffffffffe9580 x9 : 00000000fffff214

11072 16:53:37.805554  <4>[   19.880415] x8 : ffffccc0c61c34a8 x7 : ffffccc0c621b4a8 x6 : 00000000000018f0

11073 16:53:37.811733  <4>[   19.887802] x5 : ffff6ed8fef90a18 x4 : 00000000fffff214 x3 : ffffa2183948e000

11074 16:53:37.822235  <4>[   19.895189] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff6ed7ce123b00

11075 16:53:37.822310  <4>[   19.902577] Call trace:

11076 16:53:37.828890  <4>[   19.905273]  get_vaddr_frames+0xa8/0xb0 [videobuf2_common]

11077 16:53:37.835654  <4>[   19.911023]  vb2_create_framevec+0x50/0xac [videobuf2_memops]

11078 16:53:37.841699  <4>[   19.917032]  vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]

11079 16:53:37.848068  <4>[   19.923386]  __prepare_userptr+0x280/0x410 [videobuf2_common]

11080 16:53:37.851620  <4>[   19.929397]  __buf_prepare+0x1a0/0x244 [videobuf2_common]

11081 16:53:37.858660  <4>[   19.935059]  vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]

11082 16:53:37.865268  <4>[   19.941243]  vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]

11083 16:53:37.871675  <4>[   19.946739]  v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]

11084 16:53:37.878560  <4>[   19.952500]  v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]

11085 16:53:37.881523  <4>[   19.958770]  v4l_prepare_buf+0x48/0x60 [videodev]

11086 16:53:37.888144  <4>[   19.963801]  __video_do_ioctl+0x184/0x3d0 [videodev]

11087 16:53:37.891449  <4>[   19.969052]  video_usercopy+0x358/0x680 [videodev]

11088 16:53:37.898672  <4>[   19.974130]  video_ioctl2+0x18/0x30 [videodev]

11089 16:53:37.901286  <4>[   19.978861]  v4l2_ioctl+0x40/0x60 [videodev]

11090 16:53:37.904941  <4>[   19.983418]  __arm64_sys_ioctl+0xa8/0xf0

11091 16:53:37.908380  <4>[   19.987600]  invoke_syscall+0x48/0x114

11092 16:53:37.915091  <4>[   19.991608]  el0_svc_common.constprop.0+0x44/0xec

11093 16:53:37.918176  <4>[   19.996566]  do_el0_svc+0x2c/0xd0

11094 16:53:37.921701  <4>[   20.000135]  el0_svc+0x2c/0x84

11095 16:53:37.925157  <4>[   20.003449]  el0t_64_sync_handler+0xb8/0xc0

11096 16:53:37.928224  <4>[   20.007887]  el0t_64_sync+0x18c/0x190

11097 16:53:37.934807  <4>[   20.011802] ---[ end trace 0000000000000000 ]---

11098 16:53:37.947877  v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t

11099 16:53:37.957043  v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39

11100 16:53:37.962455  

11101 16:53:37.975292  Compliance test for mtk-vcodec-enc device /dev/video2:

11102 16:53:37.981218  

11103 16:53:37.990938  Driver Info:

11104 16:53:38.000582  	Driver name      : mtk-vcodec-enc

11105 16:53:38.013782  	Card type        : MT8192 video encoder

11106 16:53:38.023428  	Bus info         : platform:17020000.vcodec

11107 16:53:38.029573  	Driver version   : 6.1.31

11108 16:53:38.039729  	Capabilities     : 0x84204000

11109 16:53:38.049205  		Video Memory-to-Memory Multiplanar

11110 16:53:38.059010  		Streaming

11111 16:53:38.068751  		Extended Pix Format

11112 16:53:38.078651  		Device Capabilities

11113 16:53:38.088707  	Device Caps      : 0x04204000

11114 16:53:38.098318  		Video Memory-to-Memory Multiplanar

11115 16:53:38.107948  		Streaming

11116 16:53:38.117283  		Extended Pix Format

11117 16:53:38.127765  	Detected Stateful Encoder

11118 16:53:38.137435  

11119 16:53:38.147421  Required ioctls:

11120 16:53:38.160416  <LAVA_SIGNAL_TESTSET START Required-ioctls>

11121 16:53:38.160499  	test VIDIOC_QUERYCAP: OK

11122 16:53:38.160747  Received signal: <TESTSET> START Required-ioctls
11123 16:53:38.160822  Starting test_set Required-ioctls
11124 16:53:38.184177  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>

11125 16:53:38.184433  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11127 16:53:38.187220  	test invalid ioctls: OK

11128 16:53:38.207992  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>

11129 16:53:38.208092  

11130 16:53:38.208325  Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11132 16:53:38.217864  Allow for multiple opens:

11133 16:53:38.222984  <LAVA_SIGNAL_TESTSET STOP>

11134 16:53:38.223233  Received signal: <TESTSET> STOP
11135 16:53:38.223304  Closing test_set Required-ioctls
11136 16:53:38.232667  <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>

11137 16:53:38.232919  Received signal: <TESTSET> START Allow-for-multiple-opens
11138 16:53:38.232990  Starting test_set Allow-for-multiple-opens
11139 16:53:38.235691  	test second /dev/video2 open: OK

11140 16:53:38.256286  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>

11141 16:53:38.256537  Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11143 16:53:38.260129  	test VIDIOC_QUERYCAP: OK

11144 16:53:38.279893  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>

11145 16:53:38.280182  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11147 16:53:38.282916  	test VIDIOC_G/S_PRIORITY: OK

11148 16:53:38.303578  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>

11149 16:53:38.303859  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11151 16:53:38.306758  	test for unlimited opens: OK

11152 16:53:38.327586  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>

11153 16:53:38.327669  

11154 16:53:38.327902  Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11156 16:53:38.337760  Debug ioctls:

11157 16:53:38.344344  <LAVA_SIGNAL_TESTSET STOP>

11158 16:53:38.344594  Received signal: <TESTSET> STOP
11159 16:53:38.344662  Closing test_set Allow-for-multiple-opens
11160 16:53:38.353987  <LAVA_SIGNAL_TESTSET START Debug-ioctls>

11161 16:53:38.354236  Received signal: <TESTSET> START Debug-ioctls
11162 16:53:38.354304  Starting test_set Debug-ioctls
11163 16:53:38.357416  	test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)

11164 16:53:38.376924  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>

11165 16:53:38.377207  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11167 16:53:38.383149  	test VIDIOC_LOG_STATUS: OK (Not Supported)

11168 16:53:38.401803  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>

11169 16:53:38.401889  

11170 16:53:38.402123  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11172 16:53:38.411801  Input ioctls:

11173 16:53:38.418343  <LAVA_SIGNAL_TESTSET STOP>

11174 16:53:38.418654  Received signal: <TESTSET> STOP
11175 16:53:38.418751  Closing test_set Debug-ioctls
11176 16:53:38.428051  <LAVA_SIGNAL_TESTSET START Input-ioctls>

11177 16:53:38.428303  Received signal: <TESTSET> START Input-ioctls
11178 16:53:38.428374  Starting test_set Input-ioctls
11179 16:53:38.431550  	test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)

11180 16:53:38.456848  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>

11181 16:53:38.457099  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11183 16:53:38.459965  	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)

11184 16:53:38.478751  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>

11185 16:53:38.479001  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11187 16:53:38.485466  	test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)

11188 16:53:38.504217  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>

11189 16:53:38.504479  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11191 16:53:38.510363  	test VIDIOC_ENUMAUDIO: OK (Not Supported)

11192 16:53:38.527877  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>

11193 16:53:38.528155  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11195 16:53:38.531570  	test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)

11196 16:53:38.553342  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>

11197 16:53:38.553591  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11199 16:53:38.556135  	test VIDIOC_G/S_AUDIO: OK (Not Supported)

11200 16:53:38.576305  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>

11201 16:53:38.576556  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11203 16:53:38.579761  	Inputs: 0 Audio Inputs: 0 Tuners: 0

11204 16:53:38.585635  

11205 16:53:38.602478  	test VIDIOC_G/S_MODULATOR: OK (Not Supported)

11206 16:53:38.623861  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>

11207 16:53:38.624160  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11209 16:53:38.630220  	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)

11210 16:53:38.647893  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>

11211 16:53:38.648164  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11213 16:53:38.654775  	test VIDIOC_ENUMAUDOUT: OK (Not Supported)

11214 16:53:38.673312  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>

11215 16:53:38.673563  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11217 16:53:38.679386  	test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)

11218 16:53:38.696175  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>

11219 16:53:38.696438  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11221 16:53:38.702463  	test VIDIOC_G/S_AUDOUT: OK (Not Supported)

11222 16:53:38.725893  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>

11223 16:53:38.725978  

11224 16:53:38.726212  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11226 16:53:38.743471  	test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)

11227 16:53:38.763594  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>

11228 16:53:38.763847  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11230 16:53:38.769891  	test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)

11231 16:53:38.791279  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>

11232 16:53:38.791537  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11234 16:53:38.793847  	test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)

11235 16:53:38.811102  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>

11236 16:53:38.811352  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11238 16:53:38.814554  	test VIDIOC_G/S_EDID: OK (Not Supported)

11239 16:53:38.834673  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>

11240 16:53:38.834756  

11241 16:53:38.834989  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11243 16:53:38.845693  Control ioctls:

11244 16:53:38.852506  <LAVA_SIGNAL_TESTSET STOP>

11245 16:53:38.852786  Received signal: <TESTSET> STOP
11246 16:53:38.852884  Closing test_set Input-ioctls
11247 16:53:38.862913  <LAVA_SIGNAL_TESTSET START Control-ioctls>

11248 16:53:38.863186  Received signal: <TESTSET> START Control-ioctls
11249 16:53:38.863256  Starting test_set Control-ioctls
11250 16:53:38.865471  	test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK

11251 16:53:38.890070  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>

11252 16:53:38.890183  	test VIDIOC_QUERYCTRL: OK

11253 16:53:38.890449  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11255 16:53:38.911517  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>

11256 16:53:38.911799  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11258 16:53:38.914534  	test VIDIOC_G/S_CTRL: OK

11259 16:53:38.935538  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>

11260 16:53:38.935812  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11262 16:53:38.938812  	test VIDIOC_G/S/TRY_EXT_CTRLS: OK

11263 16:53:38.959495  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>

11264 16:53:38.959771  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11266 16:53:38.969286  		fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER

11267 16:53:38.972289  	test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL

11268 16:53:38.998678  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>

11269 16:53:38.998980  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11271 16:53:39.002200  	test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)

11272 16:53:39.023825  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>

11273 16:53:39.024100  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11275 16:53:39.027336  	Standard Controls: 16 Private Controls: 0

11276 16:53:39.032950  

11277 16:53:39.042543  Format ioctls:

11278 16:53:39.048312  <LAVA_SIGNAL_TESTSET STOP>

11279 16:53:39.048554  Received signal: <TESTSET> STOP
11280 16:53:39.048623  Closing test_set Control-ioctls
11281 16:53:39.056830  <LAVA_SIGNAL_TESTSET START Format-ioctls>

11282 16:53:39.057075  Received signal: <TESTSET> START Format-ioctls
11283 16:53:39.057142  Starting test_set Format-ioctls
11284 16:53:39.060150  	test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK

11285 16:53:39.086664  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>

11286 16:53:39.086948  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11288 16:53:39.089862  	test VIDIOC_G/S_PARM: OK

11289 16:53:39.107237  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>

11290 16:53:39.107488  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11292 16:53:39.110263  	test VIDIOC_G_FBUF: OK (Not Supported)

11293 16:53:39.131087  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>

11294 16:53:39.131332  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11296 16:53:39.134662  	test VIDIOC_G_FMT: OK

11297 16:53:39.156665  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>

11298 16:53:39.156912  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11300 16:53:39.159843  	test VIDIOC_TRY_FMT: OK

11301 16:53:39.183228  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>

11302 16:53:39.183506  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11304 16:53:39.192885  		fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()

11305 16:53:39.192997  	test VIDIOC_S_FMT: FAIL

11306 16:53:39.215986  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>

11307 16:53:39.216239  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11309 16:53:39.219482  	test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)

11310 16:53:39.239721  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>

11311 16:53:39.239974  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11313 16:53:39.242823  	test Cropping: OK

11314 16:53:39.263744  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>

11315 16:53:39.264047  Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11317 16:53:39.267204  	test Composing: OK (Not Supported)

11318 16:53:39.287567  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>

11319 16:53:39.287864  Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11321 16:53:39.290342  	test Scaling: OK (Not Supported)

11322 16:53:39.311411  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>

11323 16:53:39.311519  

11324 16:53:39.311784  Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11326 16:53:39.321477  Codec ioctls:

11327 16:53:39.328711  <LAVA_SIGNAL_TESTSET STOP>

11328 16:53:39.328955  Received signal: <TESTSET> STOP
11329 16:53:39.329023  Closing test_set Format-ioctls
11330 16:53:39.338135  <LAVA_SIGNAL_TESTSET START Codec-ioctls>

11331 16:53:39.338381  Received signal: <TESTSET> START Codec-ioctls
11332 16:53:39.338451  Starting test_set Codec-ioctls
11333 16:53:39.342042  	test VIDIOC_(TRY_)ENCODER_CMD: OK

11334 16:53:39.362698  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>

11335 16:53:39.362978  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11337 16:53:39.369311  	test VIDIOC_G_ENC_INDEX: OK (Not Supported)

11338 16:53:39.387454  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>

11339 16:53:39.387731  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11341 16:53:39.394146  	test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)

11342 16:53:39.411345  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>

11343 16:53:39.411432  

11344 16:53:39.411698  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11346 16:53:39.420336  Buffer ioctls:

11347 16:53:39.426382  <LAVA_SIGNAL_TESTSET STOP>

11348 16:53:39.426651  Received signal: <TESTSET> STOP
11349 16:53:39.426745  Closing test_set Codec-ioctls
11350 16:53:39.436325  <LAVA_SIGNAL_TESTSET START Buffer-ioctls>

11351 16:53:39.436570  Received signal: <TESTSET> START Buffer-ioctls
11352 16:53:39.436639  Starting test_set Buffer-ioctls
11353 16:53:39.439046  	test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK

11354 16:53:39.462138  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>

11355 16:53:39.462244  	test VIDIOC_EXPBUF: OK

11356 16:53:39.462507  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11358 16:53:39.480325  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>

11359 16:53:39.480601  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11361 16:53:39.483208  	test Requests: OK (Not Supported)

11362 16:53:39.504375  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>

11363 16:53:39.504485  

11364 16:53:39.504723  Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11366 16:53:39.514695  Test input 0:

11367 16:53:39.524343  

11368 16:53:39.534116  Streaming ioctls:

11369 16:53:39.540148  <LAVA_SIGNAL_TESTSET STOP>

11370 16:53:39.540390  Received signal: <TESTSET> STOP
11371 16:53:39.540457  Closing test_set Buffer-ioctls
11372 16:53:39.549740  <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>

11373 16:53:39.549987  Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11374 16:53:39.550058  Starting test_set Streaming-ioctls_Test-input-0
11375 16:53:39.552679  	test read/write: OK (Not Supported)

11376 16:53:39.574914  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>

11377 16:53:39.575170  Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11379 16:53:39.581322  		fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())

11380 16:53:39.591919  		fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)

11381 16:53:39.595838  	test blocking wait: FAIL

11382 16:53:39.620621  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>

11383 16:53:39.620873  Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11385 16:53:39.630301  		fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())

11386 16:53:39.630380  	test MMAP (select): FAIL

11387 16:53:39.655333  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>

11388 16:53:39.655581  Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11390 16:53:39.662084  		fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())

11391 16:53:39.665740  	test MMAP (epoll): FAIL

11392 16:53:39.690089  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>

11393 16:53:39.690346  Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11395 16:53:39.696852  		fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)

11396 16:53:39.707459  		fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)

11397 16:53:39.710787  	test USERPTR (select): FAIL

11398 16:53:39.735542  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>

11399 16:53:39.735793  Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11401 16:53:39.742168  	test DMABUF: Cannot test, specify --expbuf-device

11402 16:53:39.746285  

11403 16:53:39.762807  Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0

11404 16:53:39.766569  <LAVA_TEST_RUNNER EXIT>

11405 16:53:39.766816  ok: lava_test_shell seems to have completed
11406 16:53:39.766893  Marking unfinished test run as failed
11408 16:53:39.767838  Composing:
  result: pass
  set: Format-ioctls
Cropping:
  result: pass
  set: Format-ioctls
MMAP-epoll:
  result: fail
  set: Streaming-ioctls_Test-input-0
MMAP-select:
  result: fail
  set: Streaming-ioctls_Test-input-0
Requests:
  result: pass
  set: Buffer-ioctls
Scaling:
  result: pass
  set: Format-ioctls
USERPTR-select:
  result: fail
  set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
  result: pass
  set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
  result: pass
  set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
  result: pass
  set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
  result: pass
  set: Input-ioctls
VIDIOC_ENUMAUDIO:
  result: pass
  set: Input-ioctls
VIDIOC_ENUMAUDOUT:
  result: pass
  set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
  result: pass
  set: Format-ioctls
VIDIOC_EXPBUF:
  result: pass
  set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
  result: pass
  set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
  result: pass
  set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
  result: pass
  set: Control-ioctls
VIDIOC_G/S_AUDIO:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_AUDOUT:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_CTRL:
  result: pass
  set: Control-ioctls
VIDIOC_G/S_EDID:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
  result: pass
  set: Control-ioctls
VIDIOC_G/S_MODULATOR:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_PARM:
  result: pass
  set: Format-ioctls
VIDIOC_G/S_PRIORITY:
  result: pass
  set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
  result: pass
  set: Input-ioctls
VIDIOC_G_ENC_INDEX:
  result: pass
  set: Codec-ioctls
VIDIOC_G_FBUF:
  result: pass
  set: Format-ioctls
VIDIOC_G_FMT:
  result: pass
  set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
  result: pass
  set: Format-ioctls
VIDIOC_LOG_STATUS:
  result: pass
  set: Debug-ioctls
VIDIOC_QUERYCAP:
  result: pass
  set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
  result: pass
  set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
  result: pass
  set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
  result: pass
  set: Buffer-ioctls
VIDIOC_S_FMT:
  result: fail
  set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
  result: pass
  set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
  result: pass
  set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
  result: pass
  set: Codec-ioctls
VIDIOC_TRY_FMT:
  result: pass
  set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
  result: fail
  set: Control-ioctls
blocking-wait:
  result: fail
  set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
  result: pass
  set: Allow-for-multiple-opens
invalid-ioctls:
  result: pass
  set: Required-ioctls
read/write:
  result: pass
  set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
  result: pass
  set: Allow-for-multiple-opens

11409 16:53:39.767978  end: 3.1 lava-test-shell (duration 00:00:03) [common]
11410 16:53:39.768119  end: 3 lava-test-retry (duration 00:00:03) [common]
11411 16:53:39.768227  start: 4 finalize (timeout 00:07:38) [common]
11412 16:53:39.768332  start: 4.1 power-off (timeout 00:00:30) [common]
11413 16:53:39.768602  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11414 16:53:39.843813  >> Command sent successfully.

11415 16:53:39.846307  Returned 0 in 0 seconds
11416 16:53:39.946679  end: 4.1 power-off (duration 00:00:00) [common]
11418 16:53:39.947129  start: 4.2 read-feedback (timeout 00:07:38) [common]
11419 16:53:39.947411  Listened to connection for namespace 'common' for up to 1s
11420 16:53:40.948048  Finalising connection for namespace 'common'
11421 16:53:40.948223  Disconnecting from shell: Finalise
11422 16:53:40.948312  / # 
11423 16:53:41.048607  end: 4.2 read-feedback (duration 00:00:01) [common]
11424 16:53:41.048801  end: 4 finalize (duration 00:00:01) [common]
11425 16:53:41.048917  Cleaning after the job
11426 16:53:41.049020  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/ramdisk
11427 16:53:41.053643  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/kernel
11428 16:53:41.059754  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/dtb
11429 16:53:41.059947  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576311/tftp-deploy-n2rwzs5_/modules
11430 16:53:41.065461  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576311
11431 16:53:41.123462  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576311
11432 16:53:41.123666  Job finished correctly