Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 63
1 16:47:08.788552 lava-dispatcher, installed at version: 2023.03
2 16:47:08.788743 start: 0 validate
3 16:47:08.788866 Start time: 2023-06-03 16:47:08.788859+00:00 (UTC)
4 16:47:08.788990 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:47:08.789119 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 16:47:09.078810 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:47:09.079611 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:47:09.372743 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:47:09.373549 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:47:09.663650 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:47:09.664443 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:47:09.958282 validate duration: 1.17
14 16:47:09.958598 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:47:09.958696 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:47:09.958783 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:47:09.958909 Not decompressing ramdisk as can be used compressed.
18 16:47:09.958992 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 16:47:09.959061 saving as /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/ramdisk/rootfs.cpio.gz
20 16:47:09.959122 total size: 27151647 (25MB)
21 16:47:09.961950 progress 0% (0MB)
22 16:47:09.968848 progress 5% (1MB)
23 16:47:09.975858 progress 10% (2MB)
24 16:47:09.982995 progress 15% (3MB)
25 16:47:09.990015 progress 20% (5MB)
26 16:47:09.996739 progress 25% (6MB)
27 16:47:10.003307 progress 30% (7MB)
28 16:47:10.010124 progress 35% (9MB)
29 16:47:10.016768 progress 40% (10MB)
30 16:47:10.023473 progress 45% (11MB)
31 16:47:10.030396 progress 50% (12MB)
32 16:47:10.037069 progress 55% (14MB)
33 16:47:10.043874 progress 60% (15MB)
34 16:47:10.050733 progress 65% (16MB)
35 16:47:10.057555 progress 70% (18MB)
36 16:47:10.064259 progress 75% (19MB)
37 16:47:10.070939 progress 80% (20MB)
38 16:47:10.077673 progress 85% (22MB)
39 16:47:10.084177 progress 90% (23MB)
40 16:47:10.090955 progress 95% (24MB)
41 16:47:10.097477 progress 100% (25MB)
42 16:47:10.097662 25MB downloaded in 0.14s (186.91MB/s)
43 16:47:10.097816 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:47:10.098051 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:47:10.098137 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:47:10.098220 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:47:10.098356 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:47:10.098429 saving as /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/kernel/Image
50 16:47:10.098490 total size: 45746688 (43MB)
51 16:47:10.098549 No compression specified
52 16:47:10.099638 progress 0% (0MB)
53 16:47:10.110732 progress 5% (2MB)
54 16:47:10.122091 progress 10% (4MB)
55 16:47:10.133516 progress 15% (6MB)
56 16:47:10.144893 progress 20% (8MB)
57 16:47:10.156357 progress 25% (10MB)
58 16:47:10.167487 progress 30% (13MB)
59 16:47:10.178745 progress 35% (15MB)
60 16:47:10.190018 progress 40% (17MB)
61 16:47:10.201195 progress 45% (19MB)
62 16:47:10.212314 progress 50% (21MB)
63 16:47:10.223424 progress 55% (24MB)
64 16:47:10.234686 progress 60% (26MB)
65 16:47:10.246064 progress 65% (28MB)
66 16:47:10.257591 progress 70% (30MB)
67 16:47:10.268918 progress 75% (32MB)
68 16:47:10.279968 progress 80% (34MB)
69 16:47:10.291280 progress 85% (37MB)
70 16:47:10.302563 progress 90% (39MB)
71 16:47:10.313605 progress 95% (41MB)
72 16:47:10.324644 progress 100% (43MB)
73 16:47:10.324758 43MB downloaded in 0.23s (192.82MB/s)
74 16:47:10.324909 end: 1.2.1 http-download (duration 00:00:00) [common]
76 16:47:10.325135 end: 1.2 download-retry (duration 00:00:00) [common]
77 16:47:10.325222 start: 1.3 download-retry (timeout 00:10:00) [common]
78 16:47:10.325306 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 16:47:10.325445 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:47:10.325519 saving as /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/dtb/mt8192-asurada-spherion-r0.dtb
81 16:47:10.325581 total size: 46924 (0MB)
82 16:47:10.325640 No compression specified
83 16:47:10.326776 progress 69% (0MB)
84 16:47:10.327044 progress 100% (0MB)
85 16:47:10.327193 0MB downloaded in 0.00s (27.80MB/s)
86 16:47:10.327311 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:47:10.327546 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:47:10.327660 start: 1.4 download-retry (timeout 00:10:00) [common]
90 16:47:10.327785 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 16:47:10.327891 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:47:10.327960 saving as /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/modules/modules.tar
93 16:47:10.328020 total size: 8545664 (8MB)
94 16:47:10.328080 Using unxz to decompress xz
95 16:47:10.331698 progress 0% (0MB)
96 16:47:10.353236 progress 5% (0MB)
97 16:47:10.377685 progress 10% (0MB)
98 16:47:10.402858 progress 15% (1MB)
99 16:47:10.426507 progress 20% (1MB)
100 16:47:10.451669 progress 25% (2MB)
101 16:47:10.476156 progress 30% (2MB)
102 16:47:10.500768 progress 35% (2MB)
103 16:47:10.524761 progress 40% (3MB)
104 16:47:10.549204 progress 45% (3MB)
105 16:47:10.572709 progress 50% (4MB)
106 16:47:10.595144 progress 55% (4MB)
107 16:47:10.618809 progress 60% (4MB)
108 16:47:10.643168 progress 65% (5MB)
109 16:47:10.667953 progress 70% (5MB)
110 16:47:10.694181 progress 75% (6MB)
111 16:47:10.722629 progress 80% (6MB)
112 16:47:10.744223 progress 85% (6MB)
113 16:47:10.768717 progress 90% (7MB)
114 16:47:10.791668 progress 95% (7MB)
115 16:47:10.814266 progress 100% (8MB)
116 16:47:10.819925 8MB downloaded in 0.49s (16.57MB/s)
117 16:47:10.820211 end: 1.4.1 http-download (duration 00:00:00) [common]
119 16:47:10.820503 end: 1.4 download-retry (duration 00:00:00) [common]
120 16:47:10.820610 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 16:47:10.820722 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 16:47:10.820818 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:47:10.820923 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 16:47:10.821175 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8
125 16:47:10.821345 makedir: /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin
126 16:47:10.821491 makedir: /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/tests
127 16:47:10.821628 makedir: /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/results
128 16:47:10.821757 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-add-keys
129 16:47:10.821918 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-add-sources
130 16:47:10.822064 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-background-process-start
131 16:47:10.822212 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-background-process-stop
132 16:47:10.822404 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-common-functions
133 16:47:10.822561 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-echo-ipv4
134 16:47:10.822727 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-install-packages
135 16:47:10.822865 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-installed-packages
136 16:47:10.823001 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-os-build
137 16:47:10.823139 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-probe-channel
138 16:47:10.823276 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-probe-ip
139 16:47:10.823416 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-target-ip
140 16:47:10.823584 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-target-mac
141 16:47:10.823747 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-target-storage
142 16:47:10.823893 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-test-case
143 16:47:10.824056 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-test-event
144 16:47:10.824193 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-test-feedback
145 16:47:10.824331 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-test-raise
146 16:47:10.824472 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-test-reference
147 16:47:10.824610 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-test-runner
148 16:47:10.824752 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-test-set
149 16:47:10.824920 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-test-shell
150 16:47:10.825086 Updating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-install-packages (oe)
151 16:47:10.825260 Updating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/bin/lava-installed-packages (oe)
152 16:47:10.825419 Creating /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/environment
153 16:47:10.825530 LAVA metadata
154 16:47:10.825638 - LAVA_JOB_ID=10576304
155 16:47:10.825745 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:47:10.825898 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 16:47:10.825997 skipped lava-vland-overlay
158 16:47:10.826120 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:47:10.826254 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 16:47:10.826357 skipped lava-multinode-overlay
161 16:47:10.826508 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:47:10.826634 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 16:47:10.826752 Loading test definitions
164 16:47:10.826892 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 16:47:10.827004 Using /lava-10576304 at stage 0
166 16:47:10.827412 uuid=10576304_1.5.2.3.1 testdef=None
167 16:47:10.827537 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:47:10.827664 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 16:47:10.828370 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:47:10.828735 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 16:47:10.829356 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:47:10.829614 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 16:47:10.830205 runner path: /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/0/tests/0_v4l2-compliance-uvc test_uuid 10576304_1.5.2.3.1
176 16:47:10.830397 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:47:10.830635 Creating lava-test-runner.conf files
179 16:47:10.830716 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576304/lava-overlay-7c644fu8/lava-10576304/0 for stage 0
180 16:47:10.830827 - 0_v4l2-compliance-uvc
181 16:47:10.830964 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 16:47:10.831062 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 16:47:10.839005 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 16:47:10.839145 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 16:47:10.839244 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 16:47:10.839344 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 16:47:10.839446 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 16:47:11.518292 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 16:47:11.518713 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 16:47:11.518851 extracting modules file /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576304/extract-overlay-ramdisk-h_cfnjrj/ramdisk
191 16:47:11.723251 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 16:47:11.723434 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 16:47:11.723550 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576304/compress-overlay-sgwoxsqh/overlay-1.5.2.4.tar.gz to ramdisk
194 16:47:11.723636 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576304/compress-overlay-sgwoxsqh/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576304/extract-overlay-ramdisk-h_cfnjrj/ramdisk
195 16:47:11.730016 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 16:47:11.730139 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 16:47:11.730244 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 16:47:11.730384 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 16:47:11.730480 Building ramdisk /var/lib/lava/dispatcher/tmp/10576304/extract-overlay-ramdisk-h_cfnjrj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576304/extract-overlay-ramdisk-h_cfnjrj/ramdisk
200 16:47:12.307494 >> 230334 blocks
201 16:47:16.156975 rename /var/lib/lava/dispatcher/tmp/10576304/extract-overlay-ramdisk-h_cfnjrj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/ramdisk/ramdisk.cpio.gz
202 16:47:16.157436 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 16:47:16.157627 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 16:47:16.157793 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 16:47:16.157957 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/kernel/Image'
206 16:47:27.292444 Returned 0 in 11 seconds
207 16:47:27.393506 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/kernel/image.itb
208 16:47:27.999859 output: FIT description: Kernel Image image with one or more FDT blobs
209 16:47:28.000215 output: Created: Sat Jun 3 17:47:27 2023
210 16:47:28.000323 output: Image 0 (kernel-1)
211 16:47:28.000412 output: Description:
212 16:47:28.000497 output: Created: Sat Jun 3 17:47:27 2023
213 16:47:28.000579 output: Type: Kernel Image
214 16:47:28.000658 output: Compression: lzma compressed
215 16:47:28.000740 output: Data Size: 10083474 Bytes = 9847.14 KiB = 9.62 MiB
216 16:47:28.000839 output: Architecture: AArch64
217 16:47:28.000939 output: OS: Linux
218 16:47:28.001038 output: Load Address: 0x00000000
219 16:47:28.001132 output: Entry Point: 0x00000000
220 16:47:28.001228 output: Hash algo: crc32
221 16:47:28.001321 output: Hash value: b48eba69
222 16:47:28.001420 output: Image 1 (fdt-1)
223 16:47:28.001514 output: Description: mt8192-asurada-spherion-r0
224 16:47:28.001607 output: Created: Sat Jun 3 17:47:27 2023
225 16:47:28.001701 output: Type: Flat Device Tree
226 16:47:28.001794 output: Compression: uncompressed
227 16:47:28.001886 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 16:47:28.001979 output: Architecture: AArch64
229 16:47:28.002072 output: Hash algo: crc32
230 16:47:28.002164 output: Hash value: 1df858fa
231 16:47:28.002257 output: Image 2 (ramdisk-1)
232 16:47:28.002356 output: Description: unavailable
233 16:47:28.002498 output: Created: Sat Jun 3 17:47:27 2023
234 16:47:28.002592 output: Type: RAMDisk Image
235 16:47:28.002685 output: Compression: Unknown Compression
236 16:47:28.002778 output: Data Size: 40134375 Bytes = 39193.73 KiB = 38.28 MiB
237 16:47:28.002871 output: Architecture: AArch64
238 16:47:28.002964 output: OS: Linux
239 16:47:28.003056 output: Load Address: unavailable
240 16:47:28.003148 output: Entry Point: unavailable
241 16:47:28.003240 output: Hash algo: crc32
242 16:47:28.003332 output: Hash value: baff8f2c
243 16:47:28.003423 output: Default Configuration: 'conf-1'
244 16:47:28.003539 output: Configuration 0 (conf-1)
245 16:47:28.003644 output: Description: mt8192-asurada-spherion-r0
246 16:47:28.003736 output: Kernel: kernel-1
247 16:47:28.003828 output: Init Ramdisk: ramdisk-1
248 16:47:28.003919 output: FDT: fdt-1
249 16:47:28.004011 output: Loadables: kernel-1
250 16:47:28.004102 output:
251 16:47:28.004343 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 16:47:28.004489 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 16:47:28.004639 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
254 16:47:28.004774 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
255 16:47:28.004891 No LXC device requested
256 16:47:28.005012 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 16:47:28.005144 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
258 16:47:28.005265 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 16:47:28.005371 Checking files for TFTP limit of 4294967296 bytes.
260 16:47:28.006051 end: 1 tftp-deploy (duration 00:00:18) [common]
261 16:47:28.006196 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 16:47:28.006327 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 16:47:28.006562 substitutions:
264 16:47:28.006662 - {DTB}: 10576304/tftp-deploy-sksb23zw/dtb/mt8192-asurada-spherion-r0.dtb
265 16:47:28.006765 - {INITRD}: 10576304/tftp-deploy-sksb23zw/ramdisk/ramdisk.cpio.gz
266 16:47:28.006864 - {KERNEL}: 10576304/tftp-deploy-sksb23zw/kernel/Image
267 16:47:28.006962 - {LAVA_MAC}: None
268 16:47:28.007059 - {PRESEED_CONFIG}: None
269 16:47:28.007157 - {PRESEED_LOCAL}: None
270 16:47:28.007252 - {RAMDISK}: 10576304/tftp-deploy-sksb23zw/ramdisk/ramdisk.cpio.gz
271 16:47:28.007348 - {ROOT_PART}: None
272 16:47:28.007443 - {ROOT}: None
273 16:47:28.007579 - {SERVER_IP}: 192.168.201.1
274 16:47:28.007673 - {TEE}: None
275 16:47:28.007767 Parsed boot commands:
276 16:47:28.007860 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 16:47:28.008089 Parsed boot commands: tftpboot 192.168.201.1 10576304/tftp-deploy-sksb23zw/kernel/image.itb 10576304/tftp-deploy-sksb23zw/kernel/cmdline
278 16:47:28.008214 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 16:47:28.008352 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 16:47:28.008489 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 16:47:28.008619 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 16:47:28.008729 Not connected, no need to disconnect.
283 16:47:28.008846 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 16:47:28.008969 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 16:47:28.009074 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
286 16:47:28.012658 Setting prompt string to ['lava-test: # ']
287 16:47:28.012987 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 16:47:28.013110 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 16:47:28.013222 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 16:47:28.013357 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 16:47:28.013727 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 16:47:33.163996 >> Command sent successfully.
293 16:47:33.169927 Returned 0 in 5 seconds
294 16:47:33.270764 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 16:47:33.273588 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 16:47:33.274240 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 16:47:33.274903 Setting prompt string to 'Starting depthcharge on Spherion...'
299 16:47:33.275368 Changing prompt to 'Starting depthcharge on Spherion...'
300 16:47:33.275881 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 16:47:33.277423 [Enter `^Ec?' for help]
302 16:47:33.442899
303 16:47:33.443498
304 16:47:33.443876 F0: 102B 0000
305 16:47:33.444229
306 16:47:33.446765 F3: 1001 0000 [0200]
307 16:47:33.447364
308 16:47:33.447750 F3: 1001 0000
309 16:47:33.448102
310 16:47:33.448432 F7: 102D 0000
311 16:47:33.448765
312 16:47:33.449619 F1: 0000 0000
313 16:47:33.450096
314 16:47:33.450508 V0: 0000 0000 [0001]
315 16:47:33.450865
316 16:47:33.451200 00: 0007 8000
317 16:47:33.453939
318 16:47:33.454569 01: 0000 0000
319 16:47:33.454967
320 16:47:33.455320 BP: 0C00 0209 [0000]
321 16:47:33.455661
322 16:47:33.457451 G0: 1182 0000
323 16:47:33.458046
324 16:47:33.458487 EC: 0000 0021 [4000]
325 16:47:33.458855
326 16:47:33.461539 S7: 0000 0000 [0000]
327 16:47:33.462122
328 16:47:33.462548 CC: 0000 0000 [0001]
329 16:47:33.462930
330 16:47:33.465169 T0: 0000 0040 [010F]
331 16:47:33.465745
332 16:47:33.466124 Jump to BL
333 16:47:33.466514
334 16:47:33.489857
335 16:47:33.490461
336 16:47:33.490848
337 16:47:33.496397 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 16:47:33.499715 ARM64: Exception handlers installed.
339 16:47:33.503152 ARM64: Testing exception
340 16:47:33.506683 ARM64: Done test exception
341 16:47:33.514734 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 16:47:33.524845 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 16:47:33.531942 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 16:47:33.541722 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 16:47:33.548358 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 16:47:33.554936 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 16:47:33.566263 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 16:47:33.573608 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 16:47:33.592521 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 16:47:33.596186 WDT: Last reset was cold boot
351 16:47:33.598920 SPI1(PAD0) initialized at 2873684 Hz
352 16:47:33.602602 SPI5(PAD0) initialized at 992727 Hz
353 16:47:33.605573 VBOOT: Loading verstage.
354 16:47:33.612441 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 16:47:33.615897 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 16:47:33.618868 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 16:47:33.622149 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 16:47:33.629798 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 16:47:33.636777 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 16:47:33.648198 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 16:47:33.648780
362 16:47:33.649155
363 16:47:33.657778 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 16:47:33.660794 ARM64: Exception handlers installed.
365 16:47:33.664543 ARM64: Testing exception
366 16:47:33.665019 ARM64: Done test exception
367 16:47:33.670578 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 16:47:33.674143 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 16:47:33.688387 Probing TPM: . done!
370 16:47:33.688835 TPM ready after 0 ms
371 16:47:33.694846 Connected to device vid:did:rid of 1ae0:0028:00
372 16:47:33.704851 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 16:47:33.760984 Initialized TPM device CR50 revision 0
374 16:47:33.772362 tlcl_send_startup: Startup return code is 0
375 16:47:33.772854 TPM: setup succeeded
376 16:47:33.783751 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 16:47:33.792948 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 16:47:33.802841 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 16:47:33.812336 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 16:47:33.815397 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 16:47:33.821219 in-header: 03 07 00 00 08 00 00 00
382 16:47:33.824850 in-data: aa e4 47 04 13 02 00 00
383 16:47:33.828623 Chrome EC: UHEPI supported
384 16:47:33.835583 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 16:47:33.839441 in-header: 03 ad 00 00 08 00 00 00
386 16:47:33.843015 in-data: 00 20 20 08 00 00 00 00
387 16:47:33.843449 Phase 1
388 16:47:33.847102 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 16:47:33.853916 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 16:47:33.860920 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 16:47:33.861505 Recovery requested (1009000e)
392 16:47:33.871410 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 16:47:33.877291 tlcl_extend: response is 0
394 16:47:33.888792 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 16:47:33.892703 tlcl_extend: response is 0
396 16:47:33.899358 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 16:47:33.919453 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 16:47:33.926412 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 16:47:33.926978
400 16:47:33.927360
401 16:47:33.937115 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 16:47:33.940234 ARM64: Exception handlers installed.
403 16:47:33.940716 ARM64: Testing exception
404 16:47:33.943238 ARM64: Done test exception
405 16:47:33.965252 pmic_efuse_setting: Set efuses in 11 msecs
406 16:47:33.968315 pmwrap_interface_init: Select PMIF_VLD_RDY
407 16:47:33.975395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 16:47:33.978823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 16:47:33.985338 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 16:47:33.988579 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 16:47:33.995372 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 16:47:33.999267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 16:47:34.002565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 16:47:34.009684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 16:47:34.013481 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 16:47:34.016912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 16:47:34.020497 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 16:47:34.027608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 16:47:34.030906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 16:47:34.037825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 16:47:34.044135 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 16:47:34.047976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 16:47:34.054278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 16:47:34.061539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 16:47:34.065353 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 16:47:34.071947 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 16:47:34.075265 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 16:47:34.082204 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 16:47:34.088893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 16:47:34.092038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 16:47:34.098830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 16:47:34.105739 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 16:47:34.108912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 16:47:34.115937 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 16:47:34.119223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 16:47:34.122857 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 16:47:34.128936 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 16:47:34.135678 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 16:47:34.138949 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 16:47:34.145843 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 16:47:34.149056 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 16:47:34.155314 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 16:47:34.158617 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 16:47:34.165572 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 16:47:34.168492 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 16:47:34.171949 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 16:47:34.178667 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 16:47:34.182234 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 16:47:34.185597 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 16:47:34.188979 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 16:47:34.196553 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 16:47:34.198789 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 16:47:34.202282 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 16:47:34.209592 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 16:47:34.212566 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 16:47:34.216082 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 16:47:34.219247 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 16:47:34.229205 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 16:47:34.235646 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 16:47:34.242962 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 16:47:34.249837 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 16:47:34.256904 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 16:47:34.260603 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 16:47:34.267597 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 16:47:34.271273 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 16:47:34.278544 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xa
467 16:47:34.282020 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 16:47:34.289919 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 16:47:34.292683 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 16:47:34.302626 [RTC]rtc_get_frequency_meter,154: input=15, output=771
471 16:47:34.312655 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 16:47:34.321310 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 16:47:34.331000 [RTC]rtc_get_frequency_meter,154: input=17, output=817
474 16:47:34.340429 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 16:47:34.343732 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 16:47:34.350162 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 16:47:34.353423 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 16:47:34.357294 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 16:47:34.360570 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 16:47:34.363748 ADC[4]: Raw value=903245 ID=7
481 16:47:34.367245 ADC[3]: Raw value=213179 ID=1
482 16:47:34.367748 RAM Code: 0x71
483 16:47:34.375013 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 16:47:34.378997 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 16:47:34.386347 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 16:47:34.392805 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 16:47:34.396395 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 16:47:34.399392 in-header: 03 07 00 00 08 00 00 00
489 16:47:34.403112 in-data: aa e4 47 04 13 02 00 00
490 16:47:34.405934 Chrome EC: UHEPI supported
491 16:47:34.412924 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 16:47:34.416510 in-header: 03 ed 00 00 08 00 00 00
493 16:47:34.419608 in-data: 80 20 60 08 00 00 00 00
494 16:47:34.422708 MRC: failed to locate region type 0.
495 16:47:34.429736 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 16:47:34.433337 DRAM-K: Running full calibration
497 16:47:34.439668 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 16:47:34.440267 header.status = 0x0
499 16:47:34.442487 header.version = 0x6 (expected: 0x6)
500 16:47:34.445824 header.size = 0xd00 (expected: 0xd00)
501 16:47:34.449300 header.flags = 0x0
502 16:47:34.455790 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 16:47:34.471905 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
504 16:47:34.478703 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 16:47:34.482230 dram_init: ddr_geometry: 2
506 16:47:34.485646 [EMI] MDL number = 2
507 16:47:34.486255 [EMI] Get MDL freq = 0
508 16:47:34.488501 dram_init: ddr_type: 0
509 16:47:34.489096 is_discrete_lpddr4: 1
510 16:47:34.492249 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 16:47:34.492853
512 16:47:34.493351
513 16:47:34.495434 [Bian_co] ETT version 0.0.0.1
514 16:47:34.502154 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 16:47:34.502788
516 16:47:34.505348 dramc_set_vcore_voltage set vcore to 650000
517 16:47:34.508804 Read voltage for 800, 4
518 16:47:34.509401 Vio18 = 0
519 16:47:34.509901 Vcore = 650000
520 16:47:34.511942 Vdram = 0
521 16:47:34.512538 Vddq = 0
522 16:47:34.513035 Vmddr = 0
523 16:47:34.515096 dram_init: config_dvfs: 1
524 16:47:34.518617 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 16:47:34.525133 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 16:47:34.528724 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 16:47:34.532387 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 16:47:34.535879 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 16:47:34.538917 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 16:47:34.542134 MEM_TYPE=3, freq_sel=18
531 16:47:34.546843 sv_algorithm_assistance_LP4_1600
532 16:47:34.548370 ============ PULL DRAM RESETB DOWN ============
533 16:47:34.555185 ========== PULL DRAM RESETB DOWN end =========
534 16:47:34.558856 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 16:47:34.561384 ===================================
536 16:47:34.565055 LPDDR4 DRAM CONFIGURATION
537 16:47:34.568102 ===================================
538 16:47:34.568586 EX_ROW_EN[0] = 0x0
539 16:47:34.571626 EX_ROW_EN[1] = 0x0
540 16:47:34.572206 LP4Y_EN = 0x0
541 16:47:34.574861 WORK_FSP = 0x0
542 16:47:34.575345 WL = 0x2
543 16:47:34.578767 RL = 0x2
544 16:47:34.579349 BL = 0x2
545 16:47:34.582187 RPST = 0x0
546 16:47:34.582724 RD_PRE = 0x0
547 16:47:34.585158 WR_PRE = 0x1
548 16:47:34.585742 WR_PST = 0x0
549 16:47:34.588624 DBI_WR = 0x0
550 16:47:34.591521 DBI_RD = 0x0
551 16:47:34.592105 OTF = 0x1
552 16:47:34.594916 ===================================
553 16:47:34.598170 ===================================
554 16:47:34.598700 ANA top config
555 16:47:34.601539 ===================================
556 16:47:34.605072 DLL_ASYNC_EN = 0
557 16:47:34.608040 ALL_SLAVE_EN = 1
558 16:47:34.611574 NEW_RANK_MODE = 1
559 16:47:34.615038 DLL_IDLE_MODE = 1
560 16:47:34.615571 LP45_APHY_COMB_EN = 1
561 16:47:34.618225 TX_ODT_DIS = 1
562 16:47:34.621756 NEW_8X_MODE = 1
563 16:47:34.624723 ===================================
564 16:47:34.627841 ===================================
565 16:47:34.631422 data_rate = 1600
566 16:47:34.635317 CKR = 1
567 16:47:34.635851 DQ_P2S_RATIO = 8
568 16:47:34.638046 ===================================
569 16:47:34.641492 CA_P2S_RATIO = 8
570 16:47:34.644888 DQ_CA_OPEN = 0
571 16:47:34.648375 DQ_SEMI_OPEN = 0
572 16:47:34.652937 CA_SEMI_OPEN = 0
573 16:47:34.654739 CA_FULL_RATE = 0
574 16:47:34.655176 DQ_CKDIV4_EN = 1
575 16:47:34.658711 CA_CKDIV4_EN = 1
576 16:47:34.662020 CA_PREDIV_EN = 0
577 16:47:34.664829 PH8_DLY = 0
578 16:47:34.667530 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 16:47:34.671498 DQ_AAMCK_DIV = 4
580 16:47:34.672034 CA_AAMCK_DIV = 4
581 16:47:34.674752 CA_ADMCK_DIV = 4
582 16:47:34.677909 DQ_TRACK_CA_EN = 0
583 16:47:34.681220 CA_PICK = 800
584 16:47:34.684694 CA_MCKIO = 800
585 16:47:34.687719 MCKIO_SEMI = 0
586 16:47:34.690913 PLL_FREQ = 3068
587 16:47:34.691448 DQ_UI_PI_RATIO = 32
588 16:47:34.694171 CA_UI_PI_RATIO = 0
589 16:47:34.697679 ===================================
590 16:47:34.700837 ===================================
591 16:47:34.704199 memory_type:LPDDR4
592 16:47:34.707761 GP_NUM : 10
593 16:47:34.708239 SRAM_EN : 1
594 16:47:34.711147 MD32_EN : 0
595 16:47:34.714638 ===================================
596 16:47:34.715111 [ANA_INIT] >>>>>>>>>>>>>>
597 16:47:34.718154 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 16:47:34.722019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 16:47:34.724864 ===================================
600 16:47:34.728702 data_rate = 1600,PCW = 0X7600
601 16:47:34.732640 ===================================
602 16:47:34.736366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 16:47:34.739782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 16:47:34.746774 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 16:47:34.750757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 16:47:34.754255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 16:47:34.757442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 16:47:34.760386 [ANA_INIT] flow start
609 16:47:34.760962 [ANA_INIT] PLL >>>>>>>>
610 16:47:34.764045 [ANA_INIT] PLL <<<<<<<<
611 16:47:34.766873 [ANA_INIT] MIDPI >>>>>>>>
612 16:47:34.770747 [ANA_INIT] MIDPI <<<<<<<<
613 16:47:34.771322 [ANA_INIT] DLL >>>>>>>>
614 16:47:34.774176 [ANA_INIT] flow end
615 16:47:34.777373 ============ LP4 DIFF to SE enter ============
616 16:47:34.780517 ============ LP4 DIFF to SE exit ============
617 16:47:34.783901 [ANA_INIT] <<<<<<<<<<<<<
618 16:47:34.787175 [Flow] Enable top DCM control >>>>>
619 16:47:34.791184 [Flow] Enable top DCM control <<<<<
620 16:47:34.794496 Enable DLL master slave shuffle
621 16:47:34.797792 ==============================================================
622 16:47:34.801027 Gating Mode config
623 16:47:34.804766 ==============================================================
624 16:47:34.808837 Config description:
625 16:47:34.819310 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 16:47:34.822847 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 16:47:34.830885 SELPH_MODE 0: By rank 1: By Phase
628 16:47:34.834745 ==============================================================
629 16:47:34.838216 GAT_TRACK_EN = 1
630 16:47:34.841605 RX_GATING_MODE = 2
631 16:47:34.845245 RX_GATING_TRACK_MODE = 2
632 16:47:34.845836 SELPH_MODE = 1
633 16:47:34.849218 PICG_EARLY_EN = 1
634 16:47:34.852403 VALID_LAT_VALUE = 1
635 16:47:34.859683 ==============================================================
636 16:47:34.863858 Enter into Gating configuration >>>>
637 16:47:34.864540 Exit from Gating configuration <<<<
638 16:47:34.867589 Enter into DVFS_PRE_config >>>>>
639 16:47:34.878537 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 16:47:34.882112 Exit from DVFS_PRE_config <<<<<
641 16:47:34.885944 Enter into PICG configuration >>>>
642 16:47:34.889385 Exit from PICG configuration <<<<
643 16:47:34.893115 [RX_INPUT] configuration >>>>>
644 16:47:34.893743 [RX_INPUT] configuration <<<<<
645 16:47:34.900314 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 16:47:34.904146 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 16:47:34.911208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 16:47:34.918597 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 16:47:34.921944 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 16:47:34.929190 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 16:47:34.933207 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 16:47:34.937372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 16:47:34.941256 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 16:47:34.944786 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 16:47:34.948252 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 16:47:34.955882 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 16:47:34.958595 ===================================
658 16:47:34.959195 LPDDR4 DRAM CONFIGURATION
659 16:47:34.962455 ===================================
660 16:47:34.966100 EX_ROW_EN[0] = 0x0
661 16:47:34.966731 EX_ROW_EN[1] = 0x0
662 16:47:34.969188 LP4Y_EN = 0x0
663 16:47:34.969683 WORK_FSP = 0x0
664 16:47:34.973169 WL = 0x2
665 16:47:34.973644 RL = 0x2
666 16:47:34.977587 BL = 0x2
667 16:47:34.978174 RPST = 0x0
668 16:47:34.980901 RD_PRE = 0x0
669 16:47:34.981509 WR_PRE = 0x1
670 16:47:34.985217 WR_PST = 0x0
671 16:47:34.985783 DBI_WR = 0x0
672 16:47:34.987866 DBI_RD = 0x0
673 16:47:34.988448 OTF = 0x1
674 16:47:34.991873 ===================================
675 16:47:34.995264 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 16:47:34.998769 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 16:47:35.002955 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 16:47:35.006293 ===================================
679 16:47:35.009902 LPDDR4 DRAM CONFIGURATION
680 16:47:35.014116 ===================================
681 16:47:35.014805 EX_ROW_EN[0] = 0x10
682 16:47:35.017532 EX_ROW_EN[1] = 0x0
683 16:47:35.018106 LP4Y_EN = 0x0
684 16:47:35.021425 WORK_FSP = 0x0
685 16:47:35.022079 WL = 0x2
686 16:47:35.025449 RL = 0x2
687 16:47:35.026204 BL = 0x2
688 16:47:35.028380 RPST = 0x0
689 16:47:35.028856 RD_PRE = 0x0
690 16:47:35.029237 WR_PRE = 0x1
691 16:47:35.032737 WR_PST = 0x0
692 16:47:35.033214 DBI_WR = 0x0
693 16:47:35.036246 DBI_RD = 0x0
694 16:47:35.036935 OTF = 0x1
695 16:47:35.039885 ===================================
696 16:47:35.047093 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 16:47:35.051215 nWR fixed to 40
698 16:47:35.054791 [ModeRegInit_LP4] CH0 RK0
699 16:47:35.055393 [ModeRegInit_LP4] CH0 RK1
700 16:47:35.058458 [ModeRegInit_LP4] CH1 RK0
701 16:47:35.059066 [ModeRegInit_LP4] CH1 RK1
702 16:47:35.062525 match AC timing 13
703 16:47:35.065963 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 16:47:35.069543 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 16:47:35.072920 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 16:47:35.080768 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 16:47:35.084282 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 16:47:35.084884 [EMI DOE] emi_dcm 0
709 16:47:35.092304 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 16:47:35.092902 ==
711 16:47:35.093294 Dram Type= 6, Freq= 0, CH_0, rank 0
712 16:47:35.099290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 16:47:35.099893 ==
714 16:47:35.103284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 16:47:35.108801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 16:47:35.118401 [CA 0] Center 38 (7~69) winsize 63
717 16:47:35.121433 [CA 1] Center 38 (7~69) winsize 63
718 16:47:35.125174 [CA 2] Center 35 (5~66) winsize 62
719 16:47:35.128515 [CA 3] Center 35 (4~66) winsize 63
720 16:47:35.131385 [CA 4] Center 34 (4~65) winsize 62
721 16:47:35.134572 [CA 5] Center 33 (3~64) winsize 62
722 16:47:35.135044
723 16:47:35.138254 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 16:47:35.138854
725 16:47:35.141376 [CATrainingPosCal] consider 1 rank data
726 16:47:35.144597 u2DelayCellTimex100 = 270/100 ps
727 16:47:35.148349 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 16:47:35.151095 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 16:47:35.158101 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 16:47:35.161826 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
731 16:47:35.165188 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 16:47:35.168143 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 16:47:35.168721
734 16:47:35.171264 CA PerBit enable=1, Macro0, CA PI delay=33
735 16:47:35.171844
736 16:47:35.174690 [CBTSetCACLKResult] CA Dly = 33
737 16:47:35.175262 CS Dly: 6 (0~37)
738 16:47:35.178203 ==
739 16:47:35.182043 Dram Type= 6, Freq= 0, CH_0, rank 1
740 16:47:35.184738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 16:47:35.185317 ==
742 16:47:35.191568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 16:47:35.194626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 16:47:35.204617 [CA 0] Center 38 (7~69) winsize 63
745 16:47:35.207799 [CA 1] Center 38 (7~69) winsize 63
746 16:47:35.211269 [CA 2] Center 36 (6~67) winsize 62
747 16:47:35.214522 [CA 3] Center 36 (5~67) winsize 63
748 16:47:35.218321 [CA 4] Center 35 (4~66) winsize 63
749 16:47:35.221385 [CA 5] Center 34 (4~65) winsize 62
750 16:47:35.221953
751 16:47:35.225034 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 16:47:35.225509
753 16:47:35.227991 [CATrainingPosCal] consider 2 rank data
754 16:47:35.231782 u2DelayCellTimex100 = 270/100 ps
755 16:47:35.234543 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 16:47:35.238155 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 16:47:35.244552 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 16:47:35.248142 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 16:47:35.251155 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 16:47:35.255089 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 16:47:35.255667
762 16:47:35.258308 CA PerBit enable=1, Macro0, CA PI delay=34
763 16:47:35.258943
764 16:47:35.261471 [CBTSetCACLKResult] CA Dly = 34
765 16:47:35.262054 CS Dly: 6 (0~38)
766 16:47:35.262525
767 16:47:35.264873 ----->DramcWriteLeveling(PI) begin...
768 16:47:35.267987 ==
769 16:47:35.271455 Dram Type= 6, Freq= 0, CH_0, rank 0
770 16:47:35.274567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 16:47:35.275158 ==
772 16:47:35.278201 Write leveling (Byte 0): 32 => 32
773 16:47:35.281511 Write leveling (Byte 1): 32 => 32
774 16:47:35.284378 DramcWriteLeveling(PI) end<-----
775 16:47:35.284951
776 16:47:35.285330 ==
777 16:47:35.288350 Dram Type= 6, Freq= 0, CH_0, rank 0
778 16:47:35.291224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 16:47:35.291806 ==
780 16:47:35.294973 [Gating] SW mode calibration
781 16:47:35.302528 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 16:47:35.306080 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 16:47:35.309600 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 16:47:35.316710 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 16:47:35.320424 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 16:47:35.322890 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 16:47:35.326449 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 16:47:35.333659 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 16:47:35.337452 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 16:47:35.340375 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 16:47:35.347589 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 16:47:35.350291 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 16:47:35.353917 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 16:47:35.360841 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 16:47:35.363297 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 16:47:35.366910 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 16:47:35.373772 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 16:47:35.377291 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 16:47:35.380441 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 16:47:35.386798 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
801 16:47:35.390073 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
802 16:47:35.393403 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 16:47:35.400175 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 16:47:35.403259 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 16:47:35.407010 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 16:47:35.410375 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 16:47:35.416651 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 16:47:35.420233 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
809 16:47:35.423421 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 16:47:35.429661 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
811 16:47:35.433352 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 16:47:35.436561 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 16:47:35.443150 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 16:47:35.447643 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 16:47:35.449913 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 16:47:35.456645 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
817 16:47:35.459976 0 10 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
818 16:47:35.463040 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
819 16:47:35.470398 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 16:47:35.473181 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 16:47:35.476414 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 16:47:35.483767 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 16:47:35.486688 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 16:47:35.489583 0 11 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
825 16:47:35.496893 0 11 8 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
826 16:47:35.499894 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
827 16:47:35.503283 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 16:47:35.509727 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 16:47:35.513669 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 16:47:35.516520 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 16:47:35.523267 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 16:47:35.526062 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 16:47:35.529839 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 16:47:35.533312 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 16:47:35.540040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 16:47:35.542996 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 16:47:35.546709 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 16:47:35.553255 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 16:47:35.556451 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 16:47:35.559879 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 16:47:35.566436 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 16:47:35.569221 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 16:47:35.572962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 16:47:35.579730 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 16:47:35.582904 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 16:47:35.586493 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 16:47:35.593112 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 16:47:35.596007 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 16:47:35.599478 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 16:47:35.602645 Total UI for P1: 0, mck2ui 16
851 16:47:35.606036 best dqsien dly found for B0: ( 0, 14, 4)
852 16:47:35.613263 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 16:47:35.613847 Total UI for P1: 0, mck2ui 16
854 16:47:35.619384 best dqsien dly found for B1: ( 0, 14, 8)
855 16:47:35.622930 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
856 16:47:35.626390 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 16:47:35.626959
858 16:47:35.628980 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 16:47:35.633092 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 16:47:35.635600 [Gating] SW calibration Done
861 16:47:35.636087 ==
862 16:47:35.639872 Dram Type= 6, Freq= 0, CH_0, rank 0
863 16:47:35.642410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 16:47:35.642900 ==
865 16:47:35.645585 RX Vref Scan: 0
866 16:47:35.646270
867 16:47:35.646726 RX Vref 0 -> 0, step: 1
868 16:47:35.647097
869 16:47:35.648959 RX Delay -130 -> 252, step: 16
870 16:47:35.652719 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
871 16:47:35.658937 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 16:47:35.662241 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 16:47:35.666002 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
874 16:47:35.669031 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
875 16:47:35.672951 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 16:47:35.679310 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 16:47:35.682072 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 16:47:35.685435 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 16:47:35.688852 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 16:47:35.695328 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 16:47:35.698658 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 16:47:35.702450 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
883 16:47:35.705195 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 16:47:35.708255 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 16:47:35.715011 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 16:47:35.715591 ==
887 16:47:35.719128 Dram Type= 6, Freq= 0, CH_0, rank 0
888 16:47:35.722383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 16:47:35.722978 ==
890 16:47:35.723407 DQS Delay:
891 16:47:35.724948 DQS0 = 0, DQS1 = 0
892 16:47:35.725431 DQM Delay:
893 16:47:35.728067 DQM0 = 92, DQM1 = 80
894 16:47:35.728554 DQ Delay:
895 16:47:35.731678 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
896 16:47:35.735266 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
897 16:47:35.738748 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 16:47:35.741839 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
899 16:47:35.742409
900 16:47:35.742773
901 16:47:35.743100 ==
902 16:47:35.745086 Dram Type= 6, Freq= 0, CH_0, rank 0
903 16:47:35.748521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 16:47:35.749058 ==
905 16:47:35.751627
906 16:47:35.752065
907 16:47:35.752412 TX Vref Scan disable
908 16:47:35.754909 == TX Byte 0 ==
909 16:47:35.758447 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
910 16:47:35.761788 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
911 16:47:35.764872 == TX Byte 1 ==
912 16:47:35.768367 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 16:47:35.772062 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 16:47:35.772605 ==
915 16:47:35.774911 Dram Type= 6, Freq= 0, CH_0, rank 0
916 16:47:35.781433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 16:47:35.781863 ==
918 16:47:35.793529 TX Vref=22, minBit 6, minWin=27, winSum=440
919 16:47:35.797243 TX Vref=24, minBit 6, minWin=27, winSum=444
920 16:47:35.800701 TX Vref=26, minBit 8, minWin=27, winSum=452
921 16:47:35.803727 TX Vref=28, minBit 8, minWin=27, winSum=453
922 16:47:35.807471 TX Vref=30, minBit 3, minWin=28, winSum=457
923 16:47:35.810186 TX Vref=32, minBit 9, minWin=27, winSum=455
924 16:47:35.817013 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 30
925 16:47:35.817597
926 16:47:35.820052 Final TX Range 1 Vref 30
927 16:47:35.820634
928 16:47:35.821013 ==
929 16:47:35.823139 Dram Type= 6, Freq= 0, CH_0, rank 0
930 16:47:35.827001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 16:47:35.827544 ==
932 16:47:35.829661
933 16:47:35.830155
934 16:47:35.830574 TX Vref Scan disable
935 16:47:35.833285 == TX Byte 0 ==
936 16:47:35.836789 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 16:47:35.840375 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 16:47:35.843095 == TX Byte 1 ==
939 16:47:35.846314 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 16:47:35.853495 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 16:47:35.854084
942 16:47:35.854504 [DATLAT]
943 16:47:35.854870 Freq=800, CH0 RK0
944 16:47:35.855217
945 16:47:35.856806 DATLAT Default: 0xa
946 16:47:35.857393 0, 0xFFFF, sum = 0
947 16:47:35.860043 1, 0xFFFF, sum = 0
948 16:47:35.860638 2, 0xFFFF, sum = 0
949 16:47:35.863285 3, 0xFFFF, sum = 0
950 16:47:35.866491 4, 0xFFFF, sum = 0
951 16:47:35.867120 5, 0xFFFF, sum = 0
952 16:47:35.870337 6, 0xFFFF, sum = 0
953 16:47:35.870961 7, 0xFFFF, sum = 0
954 16:47:35.874210 8, 0xFFFF, sum = 0
955 16:47:35.874851 9, 0x0, sum = 1
956 16:47:35.875246 10, 0x0, sum = 2
957 16:47:35.876399 11, 0x0, sum = 3
958 16:47:35.876882 12, 0x0, sum = 4
959 16:47:35.879615 best_step = 10
960 16:47:35.880051
961 16:47:35.880398 ==
962 16:47:35.883562 Dram Type= 6, Freq= 0, CH_0, rank 0
963 16:47:35.886167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 16:47:35.886649 ==
965 16:47:35.889780 RX Vref Scan: 1
966 16:47:35.890322
967 16:47:35.890714 Set Vref Range= 32 -> 127
968 16:47:35.893381
969 16:47:35.893930 RX Vref 32 -> 127, step: 1
970 16:47:35.894286
971 16:47:35.896180 RX Delay -95 -> 252, step: 8
972 16:47:35.896660
973 16:47:35.899691 Set Vref, RX VrefLevel [Byte0]: 32
974 16:47:35.903241 [Byte1]: 32
975 16:47:35.903830
976 16:47:35.906303 Set Vref, RX VrefLevel [Byte0]: 33
977 16:47:35.909725 [Byte1]: 33
978 16:47:35.913711
979 16:47:35.914301 Set Vref, RX VrefLevel [Byte0]: 34
980 16:47:35.917017 [Byte1]: 34
981 16:47:35.921962
982 16:47:35.922578 Set Vref, RX VrefLevel [Byte0]: 35
983 16:47:35.924435 [Byte1]: 35
984 16:47:35.929036
985 16:47:35.929704 Set Vref, RX VrefLevel [Byte0]: 36
986 16:47:35.932235 [Byte1]: 36
987 16:47:35.936987
988 16:47:35.937568 Set Vref, RX VrefLevel [Byte0]: 37
989 16:47:35.939823 [Byte1]: 37
990 16:47:35.944733
991 16:47:35.945324 Set Vref, RX VrefLevel [Byte0]: 38
992 16:47:35.948460 [Byte1]: 38
993 16:47:35.951752
994 16:47:35.952337 Set Vref, RX VrefLevel [Byte0]: 39
995 16:47:35.954930 [Byte1]: 39
996 16:47:35.959716
997 16:47:35.960301 Set Vref, RX VrefLevel [Byte0]: 40
998 16:47:35.962419 [Byte1]: 40
999 16:47:35.967083
1000 16:47:35.967662 Set Vref, RX VrefLevel [Byte0]: 41
1001 16:47:35.970495 [Byte1]: 41
1002 16:47:35.975091
1003 16:47:35.975678 Set Vref, RX VrefLevel [Byte0]: 42
1004 16:47:35.978690 [Byte1]: 42
1005 16:47:35.982318
1006 16:47:35.982836 Set Vref, RX VrefLevel [Byte0]: 43
1007 16:47:35.985330 [Byte1]: 43
1008 16:47:35.990189
1009 16:47:35.991001 Set Vref, RX VrefLevel [Byte0]: 44
1010 16:47:35.993457 [Byte1]: 44
1011 16:47:35.997189
1012 16:47:35.997852 Set Vref, RX VrefLevel [Byte0]: 45
1013 16:47:36.000900 [Byte1]: 45
1014 16:47:36.004759
1015 16:47:36.005238 Set Vref, RX VrefLevel [Byte0]: 46
1016 16:47:36.007868 [Byte1]: 46
1017 16:47:36.012566
1018 16:47:36.013159 Set Vref, RX VrefLevel [Byte0]: 47
1019 16:47:36.016006 [Byte1]: 47
1020 16:47:36.020172
1021 16:47:36.023674 Set Vref, RX VrefLevel [Byte0]: 48
1022 16:47:36.026152 [Byte1]: 48
1023 16:47:36.026688
1024 16:47:36.030570 Set Vref, RX VrefLevel [Byte0]: 49
1025 16:47:36.033345 [Byte1]: 49
1026 16:47:36.033823
1027 16:47:36.036750 Set Vref, RX VrefLevel [Byte0]: 50
1028 16:47:36.040774 [Byte1]: 50
1029 16:47:36.041352
1030 16:47:36.043000 Set Vref, RX VrefLevel [Byte0]: 51
1031 16:47:36.046237 [Byte1]: 51
1032 16:47:36.050304
1033 16:47:36.050924 Set Vref, RX VrefLevel [Byte0]: 52
1034 16:47:36.056874 [Byte1]: 52
1035 16:47:36.057449
1036 16:47:36.060276 Set Vref, RX VrefLevel [Byte0]: 53
1037 16:47:36.063951 [Byte1]: 53
1038 16:47:36.064425
1039 16:47:36.067435 Set Vref, RX VrefLevel [Byte0]: 54
1040 16:47:36.070086 [Byte1]: 54
1041 16:47:36.070718
1042 16:47:36.073822 Set Vref, RX VrefLevel [Byte0]: 55
1043 16:47:36.076828 [Byte1]: 55
1044 16:47:36.080884
1045 16:47:36.081452 Set Vref, RX VrefLevel [Byte0]: 56
1046 16:47:36.084230 [Byte1]: 56
1047 16:47:36.088793
1048 16:47:36.089371 Set Vref, RX VrefLevel [Byte0]: 57
1049 16:47:36.091500 [Byte1]: 57
1050 16:47:36.096020
1051 16:47:36.096603 Set Vref, RX VrefLevel [Byte0]: 58
1052 16:47:36.099456 [Byte1]: 58
1053 16:47:36.103742
1054 16:47:36.104345 Set Vref, RX VrefLevel [Byte0]: 59
1055 16:47:36.106972 [Byte1]: 59
1056 16:47:36.111198
1057 16:47:36.111685 Set Vref, RX VrefLevel [Byte0]: 60
1058 16:47:36.114451 [Byte1]: 60
1059 16:47:36.118950
1060 16:47:36.119485 Set Vref, RX VrefLevel [Byte0]: 61
1061 16:47:36.122037 [Byte1]: 61
1062 16:47:36.126710
1063 16:47:36.127279 Set Vref, RX VrefLevel [Byte0]: 62
1064 16:47:36.129710 [Byte1]: 62
1065 16:47:36.133904
1066 16:47:36.134487 Set Vref, RX VrefLevel [Byte0]: 63
1067 16:47:36.137506 [Byte1]: 63
1068 16:47:36.141891
1069 16:47:36.142486 Set Vref, RX VrefLevel [Byte0]: 64
1070 16:47:36.145202 [Byte1]: 64
1071 16:47:36.149316
1072 16:47:36.149850 Set Vref, RX VrefLevel [Byte0]: 65
1073 16:47:36.152465 [Byte1]: 65
1074 16:47:36.157718
1075 16:47:36.158248 Set Vref, RX VrefLevel [Byte0]: 66
1076 16:47:36.160737 [Byte1]: 66
1077 16:47:36.164855
1078 16:47:36.165392 Set Vref, RX VrefLevel [Byte0]: 67
1079 16:47:36.167819 [Byte1]: 67
1080 16:47:36.171893
1081 16:47:36.172434 Set Vref, RX VrefLevel [Byte0]: 68
1082 16:47:36.175556 [Byte1]: 68
1083 16:47:36.179547
1084 16:47:36.180084 Set Vref, RX VrefLevel [Byte0]: 69
1085 16:47:36.182892 [Byte1]: 69
1086 16:47:36.187076
1087 16:47:36.187609 Set Vref, RX VrefLevel [Byte0]: 70
1088 16:47:36.190558 [Byte1]: 70
1089 16:47:36.194739
1090 16:47:36.195273 Set Vref, RX VrefLevel [Byte0]: 71
1091 16:47:36.197893 [Byte1]: 71
1092 16:47:36.202185
1093 16:47:36.202753 Set Vref, RX VrefLevel [Byte0]: 72
1094 16:47:36.205632 [Byte1]: 72
1095 16:47:36.209742
1096 16:47:36.210172 Set Vref, RX VrefLevel [Byte0]: 73
1097 16:47:36.213211 [Byte1]: 73
1098 16:47:36.217599
1099 16:47:36.218120 Set Vref, RX VrefLevel [Byte0]: 74
1100 16:47:36.220915 [Byte1]: 74
1101 16:47:36.225835
1102 16:47:36.226439 Set Vref, RX VrefLevel [Byte0]: 75
1103 16:47:36.228293 [Byte1]: 75
1104 16:47:36.232760
1105 16:47:36.233241 Set Vref, RX VrefLevel [Byte0]: 76
1106 16:47:36.236436 [Byte1]: 76
1107 16:47:36.240289
1108 16:47:36.240857 Final RX Vref Byte 0 = 63 to rank0
1109 16:47:36.243934 Final RX Vref Byte 1 = 52 to rank0
1110 16:47:36.246706 Final RX Vref Byte 0 = 63 to rank1
1111 16:47:36.251364 Final RX Vref Byte 1 = 52 to rank1==
1112 16:47:36.253952 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 16:47:36.260474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 16:47:36.261045 ==
1115 16:47:36.261422 DQS Delay:
1116 16:47:36.261776 DQS0 = 0, DQS1 = 0
1117 16:47:36.263336 DQM Delay:
1118 16:47:36.263810 DQM0 = 93, DQM1 = 81
1119 16:47:36.266539 DQ Delay:
1120 16:47:36.270096 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1121 16:47:36.273731 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1122 16:47:36.277221 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1123 16:47:36.280195 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1124 16:47:36.280892
1125 16:47:36.281277
1126 16:47:36.286991 [DQSOSCAuto] RK0, (LSB)MR18= 0x3934, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1127 16:47:36.290736 CH0 RK0: MR19=606, MR18=3934
1128 16:47:36.297310 CH0_RK0: MR19=0x606, MR18=0x3934, DQSOSC=395, MR23=63, INC=94, DEC=63
1129 16:47:36.297885
1130 16:47:36.300530 ----->DramcWriteLeveling(PI) begin...
1131 16:47:36.301011 ==
1132 16:47:36.303351 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 16:47:36.306672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 16:47:36.307248 ==
1135 16:47:36.309777 Write leveling (Byte 0): 29 => 29
1136 16:47:36.313531 Write leveling (Byte 1): 30 => 30
1137 16:47:36.316731 DramcWriteLeveling(PI) end<-----
1138 16:47:36.317326
1139 16:47:36.317740 ==
1140 16:47:36.320092 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 16:47:36.323581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 16:47:36.324215 ==
1143 16:47:36.326867 [Gating] SW mode calibration
1144 16:47:36.333351 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 16:47:36.340155 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 16:47:36.343037 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1147 16:47:36.347303 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1148 16:47:36.354247 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1149 16:47:36.356696 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 16:47:36.360483 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 16:47:36.367193 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 16:47:36.410728 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 16:47:36.411377 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 16:47:36.411994 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 16:47:36.412559 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 16:47:36.413279 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 16:47:36.413655 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 16:47:36.414026 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 16:47:36.414424 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 16:47:36.414760 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 16:47:36.415085 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 16:47:36.415479 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 16:47:36.418179 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1164 16:47:36.422139 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 16:47:36.429036 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 16:47:36.431599 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 16:47:36.434966 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 16:47:36.441536 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 16:47:36.445056 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 16:47:36.448201 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 16:47:36.454787 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1172 16:47:36.458562 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1173 16:47:36.461551 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 16:47:36.468086 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 16:47:36.472771 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 16:47:36.474670 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 16:47:36.481612 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 16:47:36.485097 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 16:47:36.488267 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
1180 16:47:36.494534 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1181 16:47:36.497731 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 16:47:36.500993 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 16:47:36.507992 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 16:47:36.511290 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 16:47:36.514386 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 16:47:36.521349 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 16:47:36.524894 0 11 4 | B1->B0 | 2525 3333 | 0 1 | (1 1) (0 0)
1188 16:47:36.527500 0 11 8 | B1->B0 | 3e3e 4545 | 1 0 | (0 0) (0 0)
1189 16:47:36.534194 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 16:47:36.537845 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 16:47:36.541023 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 16:47:36.548176 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 16:47:36.552036 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 16:47:36.555488 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 16:47:36.559521 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 16:47:36.562980 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 16:47:36.569224 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 16:47:36.572339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 16:47:36.577449 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 16:47:36.579865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 16:47:36.586679 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 16:47:36.590024 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 16:47:36.593073 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 16:47:36.599892 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 16:47:36.603190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 16:47:36.606201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 16:47:36.613589 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 16:47:36.617036 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 16:47:36.620007 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 16:47:36.626802 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 16:47:36.629466 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1212 16:47:36.632497 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 16:47:36.636021 Total UI for P1: 0, mck2ui 16
1214 16:47:36.639436 best dqsien dly found for B0: ( 0, 14, 4)
1215 16:47:36.642795 Total UI for P1: 0, mck2ui 16
1216 16:47:36.646234 best dqsien dly found for B1: ( 0, 14, 4)
1217 16:47:36.649276 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1218 16:47:36.652307 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1219 16:47:36.652743
1220 16:47:36.658997 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1221 16:47:36.662283 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1222 16:47:36.662811 [Gating] SW calibration Done
1223 16:47:36.665703 ==
1224 16:47:36.669304 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 16:47:36.672254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 16:47:36.672728 ==
1227 16:47:36.673101 RX Vref Scan: 0
1228 16:47:36.673446
1229 16:47:36.675700 RX Vref 0 -> 0, step: 1
1230 16:47:36.676170
1231 16:47:36.678762 RX Delay -130 -> 252, step: 16
1232 16:47:36.682726 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1233 16:47:36.685926 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1234 16:47:36.692580 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1235 16:47:36.695832 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1236 16:47:36.699413 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1237 16:47:36.702411 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1238 16:47:36.706077 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1239 16:47:36.709105 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1240 16:47:36.715805 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1241 16:47:36.718971 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1242 16:47:36.722567 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1243 16:47:36.725941 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1244 16:47:36.730302 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1245 16:47:36.735400 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1246 16:47:36.738821 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1247 16:47:36.742246 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1248 16:47:36.742874 ==
1249 16:47:36.745513 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 16:47:36.748667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 16:47:36.752199 ==
1252 16:47:36.752889 DQS Delay:
1253 16:47:36.753419 DQS0 = 0, DQS1 = 0
1254 16:47:36.755394 DQM Delay:
1255 16:47:36.755862 DQM0 = 87, DQM1 = 80
1256 16:47:36.758643 DQ Delay:
1257 16:47:36.759113 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1258 16:47:36.762410 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1259 16:47:36.766046 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1260 16:47:36.768813 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1261 16:47:36.772187
1262 16:47:36.772654
1263 16:47:36.773024 ==
1264 16:47:36.775498 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 16:47:36.778898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 16:47:36.779374 ==
1267 16:47:36.779748
1268 16:47:36.780095
1269 16:47:36.782282 TX Vref Scan disable
1270 16:47:36.782772 == TX Byte 0 ==
1271 16:47:36.788778 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1272 16:47:36.792039 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1273 16:47:36.792610 == TX Byte 1 ==
1274 16:47:36.798786 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1275 16:47:36.802118 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1276 16:47:36.802723 ==
1277 16:47:36.805698 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 16:47:36.809116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 16:47:36.809690 ==
1280 16:47:36.821837 TX Vref=22, minBit 8, minWin=27, winSum=446
1281 16:47:36.825633 TX Vref=24, minBit 8, minWin=27, winSum=445
1282 16:47:36.828338 TX Vref=26, minBit 8, minWin=27, winSum=449
1283 16:47:36.832118 TX Vref=28, minBit 8, minWin=27, winSum=451
1284 16:47:36.835243 TX Vref=30, minBit 8, minWin=27, winSum=454
1285 16:47:36.842146 TX Vref=32, minBit 8, minWin=27, winSum=455
1286 16:47:36.845581 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 32
1287 16:47:36.846154
1288 16:47:36.848579 Final TX Range 1 Vref 32
1289 16:47:36.849046
1290 16:47:36.849417 ==
1291 16:47:36.852188 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 16:47:36.855092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 16:47:36.855553 ==
1294 16:47:36.859229
1295 16:47:36.859679
1296 16:47:36.860036 TX Vref Scan disable
1297 16:47:36.861601 == TX Byte 0 ==
1298 16:47:36.864905 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1299 16:47:36.871732 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1300 16:47:36.872187 == TX Byte 1 ==
1301 16:47:36.874903 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1302 16:47:36.881581 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1303 16:47:36.881874
1304 16:47:36.882106 [DATLAT]
1305 16:47:36.882323 Freq=800, CH0 RK1
1306 16:47:36.882583
1307 16:47:36.884999 DATLAT Default: 0xa
1308 16:47:36.885308 0, 0xFFFF, sum = 0
1309 16:47:36.888561 1, 0xFFFF, sum = 0
1310 16:47:36.891904 2, 0xFFFF, sum = 0
1311 16:47:36.892223 3, 0xFFFF, sum = 0
1312 16:47:36.895030 4, 0xFFFF, sum = 0
1313 16:47:36.895348 5, 0xFFFF, sum = 0
1314 16:47:36.898060 6, 0xFFFF, sum = 0
1315 16:47:36.898284 7, 0xFFFF, sum = 0
1316 16:47:36.901640 8, 0xFFFF, sum = 0
1317 16:47:36.901950 9, 0x0, sum = 1
1318 16:47:36.905332 10, 0x0, sum = 2
1319 16:47:36.905651 11, 0x0, sum = 3
1320 16:47:36.905840 12, 0x0, sum = 4
1321 16:47:36.907804 best_step = 10
1322 16:47:36.908118
1323 16:47:36.908303 ==
1324 16:47:36.912181 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 16:47:36.915239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 16:47:36.915556 ==
1327 16:47:36.918235 RX Vref Scan: 0
1328 16:47:36.918567
1329 16:47:36.921288 RX Vref 0 -> 0, step: 1
1330 16:47:36.921602
1331 16:47:36.921790 RX Delay -95 -> 252, step: 8
1332 16:47:36.928234 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1333 16:47:36.931479 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1334 16:47:36.935507 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1335 16:47:36.939262 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1336 16:47:36.944877 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1337 16:47:36.948339 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1338 16:47:36.951381 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1339 16:47:36.955002 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1340 16:47:36.958587 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1341 16:47:36.964625 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1342 16:47:36.968041 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1343 16:47:36.972009 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1344 16:47:36.975443 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1345 16:47:36.978473 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1346 16:47:36.984582 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1347 16:47:36.988135 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1348 16:47:36.988592 ==
1349 16:47:36.991656 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 16:47:36.995713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 16:47:36.996269 ==
1352 16:47:36.998289 DQS Delay:
1353 16:47:36.998878 DQS0 = 0, DQS1 = 0
1354 16:47:36.999249 DQM Delay:
1355 16:47:37.001436 DQM0 = 91, DQM1 = 82
1356 16:47:37.001989 DQ Delay:
1357 16:47:37.004904 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1358 16:47:37.008536 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1359 16:47:37.010902 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1360 16:47:37.014235 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1361 16:47:37.014818
1362 16:47:37.015187
1363 16:47:37.024707 [DQSOSCAuto] RK1, (LSB)MR18= 0x401a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1364 16:47:37.027752 CH0 RK1: MR19=606, MR18=401A
1365 16:47:37.030960 CH0_RK1: MR19=0x606, MR18=0x401A, DQSOSC=393, MR23=63, INC=95, DEC=63
1366 16:47:37.034386 [RxdqsGatingPostProcess] freq 800
1367 16:47:37.041035 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1368 16:47:37.044397 Pre-setting of DQS Precalculation
1369 16:47:37.047833 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1370 16:47:37.048412 ==
1371 16:47:37.050684 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 16:47:37.057594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 16:47:37.058175 ==
1374 16:47:37.061186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1375 16:47:37.067709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1376 16:47:37.077165 [CA 0] Center 36 (6~67) winsize 62
1377 16:47:37.080416 [CA 1] Center 36 (6~67) winsize 62
1378 16:47:37.083758 [CA 2] Center 34 (4~65) winsize 62
1379 16:47:37.087314 [CA 3] Center 34 (4~65) winsize 62
1380 16:47:37.090184 [CA 4] Center 34 (4~65) winsize 62
1381 16:47:37.093491 [CA 5] Center 33 (3~64) winsize 62
1382 16:47:37.094067
1383 16:47:37.097356 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1384 16:47:37.097933
1385 16:47:37.100230 [CATrainingPosCal] consider 1 rank data
1386 16:47:37.103884 u2DelayCellTimex100 = 270/100 ps
1387 16:47:37.107088 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1388 16:47:37.113703 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 16:47:37.116995 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 16:47:37.120353 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1391 16:47:37.124018 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1392 16:47:37.126861 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1393 16:47:37.127434
1394 16:47:37.130144 CA PerBit enable=1, Macro0, CA PI delay=33
1395 16:47:37.130662
1396 16:47:37.133537 [CBTSetCACLKResult] CA Dly = 33
1397 16:47:37.134132 CS Dly: 5 (0~36)
1398 16:47:37.136800 ==
1399 16:47:37.137287 Dram Type= 6, Freq= 0, CH_1, rank 1
1400 16:47:37.143299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 16:47:37.143890 ==
1402 16:47:37.147051 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1403 16:47:37.153527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1404 16:47:37.163295 [CA 0] Center 37 (6~68) winsize 63
1405 16:47:37.166886 [CA 1] Center 37 (6~68) winsize 63
1406 16:47:37.170026 [CA 2] Center 35 (5~66) winsize 62
1407 16:47:37.173055 [CA 3] Center 34 (4~65) winsize 62
1408 16:47:37.176762 [CA 4] Center 34 (4~65) winsize 62
1409 16:47:37.179891 [CA 5] Center 34 (4~64) winsize 61
1410 16:47:37.180380
1411 16:47:37.183421 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1412 16:47:37.183994
1413 16:47:37.187043 [CATrainingPosCal] consider 2 rank data
1414 16:47:37.189490 u2DelayCellTimex100 = 270/100 ps
1415 16:47:37.193113 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1416 16:47:37.199693 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1417 16:47:37.202860 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1418 16:47:37.206278 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1419 16:47:37.210050 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 16:47:37.213838 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1421 16:47:37.214613
1422 16:47:37.217299 CA PerBit enable=1, Macro0, CA PI delay=34
1423 16:47:37.217890
1424 16:47:37.221078 [CBTSetCACLKResult] CA Dly = 34
1425 16:47:37.221787 CS Dly: 6 (0~38)
1426 16:47:37.222187
1427 16:47:37.224176 ----->DramcWriteLeveling(PI) begin...
1428 16:47:37.224737 ==
1429 16:47:37.227981 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 16:47:37.232575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 16:47:37.233145 ==
1432 16:47:37.235434 Write leveling (Byte 0): 26 => 26
1433 16:47:37.239260 Write leveling (Byte 1): 28 => 28
1434 16:47:37.242716 DramcWriteLeveling(PI) end<-----
1435 16:47:37.243191
1436 16:47:37.243567 ==
1437 16:47:37.246276 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 16:47:37.249517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 16:47:37.249995 ==
1440 16:47:37.253315 [Gating] SW mode calibration
1441 16:47:37.259721 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1442 16:47:37.263181 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1443 16:47:37.270731 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1444 16:47:37.273081 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 16:47:37.276518 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1446 16:47:37.283263 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 16:47:37.286542 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 16:47:37.289834 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 16:47:37.296565 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 16:47:37.299566 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 16:47:37.303179 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 16:47:37.309624 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 16:47:37.313012 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 16:47:37.316093 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 16:47:37.323234 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 16:47:37.326341 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 16:47:37.329486 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 16:47:37.336997 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 16:47:37.339345 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1460 16:47:37.343245 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1461 16:47:37.350160 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1462 16:47:37.353011 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 16:47:37.356315 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 16:47:37.363261 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 16:47:37.366330 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 16:47:37.369609 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 16:47:37.373223 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 16:47:37.379502 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1469 16:47:37.383233 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
1470 16:47:37.386132 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 16:47:37.392714 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 16:47:37.396375 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 16:47:37.399825 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 16:47:37.406146 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 16:47:37.409772 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1476 16:47:37.412791 0 10 4 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
1477 16:47:37.419697 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1478 16:47:37.422601 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 16:47:37.426137 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 16:47:37.432521 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 16:47:37.436193 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 16:47:37.439431 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 16:47:37.446588 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 16:47:37.449161 0 11 4 | B1->B0 | 2f2f 3737 | 0 0 | (0 0) (0 0)
1485 16:47:37.453228 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1486 16:47:37.459316 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 16:47:37.462878 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 16:47:37.466270 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 16:47:37.472643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 16:47:37.476177 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 16:47:37.479408 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 16:47:37.485910 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1493 16:47:37.489540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 16:47:37.492684 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 16:47:37.499264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 16:47:37.502514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 16:47:37.505971 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 16:47:37.509212 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 16:47:37.515722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 16:47:37.519165 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 16:47:37.522927 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 16:47:37.529538 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 16:47:37.532467 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 16:47:37.536202 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 16:47:37.542595 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 16:47:37.546437 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 16:47:37.548974 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 16:47:37.555708 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 16:47:37.556182 Total UI for P1: 0, mck2ui 16
1510 16:47:37.562479 best dqsien dly found for B0: ( 0, 14, 2)
1511 16:47:37.563044 Total UI for P1: 0, mck2ui 16
1512 16:47:37.569439 best dqsien dly found for B1: ( 0, 14, 2)
1513 16:47:37.572263 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1514 16:47:37.575521 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1515 16:47:37.576092
1516 16:47:37.578918 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1517 16:47:37.582198 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1518 16:47:37.585770 [Gating] SW calibration Done
1519 16:47:37.586335 ==
1520 16:47:37.588872 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 16:47:37.592296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1522 16:47:37.592865 ==
1523 16:47:37.595277 RX Vref Scan: 0
1524 16:47:37.595839
1525 16:47:37.596212 RX Vref 0 -> 0, step: 1
1526 16:47:37.596557
1527 16:47:37.598604 RX Delay -130 -> 252, step: 16
1528 16:47:37.602616 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1529 16:47:37.609035 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1530 16:47:37.612149 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1531 16:47:37.615136 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1532 16:47:37.618626 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1533 16:47:37.622087 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1534 16:47:37.628321 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1535 16:47:37.631579 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1536 16:47:37.635025 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1537 16:47:37.638207 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1538 16:47:37.641471 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1539 16:47:37.648268 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1540 16:47:37.652165 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1541 16:47:37.654898 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1542 16:47:37.659472 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1543 16:47:37.665216 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1544 16:47:37.665787 ==
1545 16:47:37.668257 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 16:47:37.671893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1547 16:47:37.672463 ==
1548 16:47:37.672839 DQS Delay:
1549 16:47:37.675474 DQS0 = 0, DQS1 = 0
1550 16:47:37.676037 DQM Delay:
1551 16:47:37.679029 DQM0 = 89, DQM1 = 80
1552 16:47:37.679594 DQ Delay:
1553 16:47:37.681471 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1554 16:47:37.684753 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1555 16:47:37.688522 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1556 16:47:37.691733 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1557 16:47:37.692304
1558 16:47:37.692679
1559 16:47:37.693027 ==
1560 16:47:37.694960 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 16:47:37.698611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 16:47:37.699181 ==
1563 16:47:37.701276
1564 16:47:37.701742
1565 16:47:37.702113 TX Vref Scan disable
1566 16:47:37.705405 == TX Byte 0 ==
1567 16:47:37.708210 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1568 16:47:37.711997 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1569 16:47:37.714534 == TX Byte 1 ==
1570 16:47:37.718219 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1571 16:47:37.722468 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1572 16:47:37.723032 ==
1573 16:47:37.724839 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 16:47:37.731256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 16:47:37.731729 ==
1576 16:47:37.743803 TX Vref=22, minBit 8, minWin=27, winSum=450
1577 16:47:37.747098 TX Vref=24, minBit 13, minWin=27, winSum=451
1578 16:47:37.750257 TX Vref=26, minBit 15, minWin=27, winSum=455
1579 16:47:37.753381 TX Vref=28, minBit 15, minWin=27, winSum=457
1580 16:47:37.757170 TX Vref=30, minBit 8, minWin=28, winSum=459
1581 16:47:37.763143 TX Vref=32, minBit 9, minWin=27, winSum=458
1582 16:47:37.766715 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1583 16:47:37.767284
1584 16:47:37.769914 Final TX Range 1 Vref 30
1585 16:47:37.770515
1586 16:47:37.770889 ==
1587 16:47:37.773171 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 16:47:37.776797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 16:47:37.780224 ==
1590 16:47:37.780836
1591 16:47:37.781211
1592 16:47:37.781559 TX Vref Scan disable
1593 16:47:37.783445 == TX Byte 0 ==
1594 16:47:37.786784 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1595 16:47:37.790930 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1596 16:47:37.794226 == TX Byte 1 ==
1597 16:47:37.797370 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1598 16:47:37.800639 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1599 16:47:37.801221
1600 16:47:37.804689 [DATLAT]
1601 16:47:37.805257 Freq=800, CH1 RK0
1602 16:47:37.805640
1603 16:47:37.807169 DATLAT Default: 0xa
1604 16:47:37.807704 0, 0xFFFF, sum = 0
1605 16:47:37.810229 1, 0xFFFF, sum = 0
1606 16:47:37.810845 2, 0xFFFF, sum = 0
1607 16:47:37.813649 3, 0xFFFF, sum = 0
1608 16:47:37.814221 4, 0xFFFF, sum = 0
1609 16:47:37.816972 5, 0xFFFF, sum = 0
1610 16:47:37.817541 6, 0xFFFF, sum = 0
1611 16:47:37.820911 7, 0xFFFF, sum = 0
1612 16:47:37.821485 8, 0xFFFF, sum = 0
1613 16:47:37.824097 9, 0x0, sum = 1
1614 16:47:37.824672 10, 0x0, sum = 2
1615 16:47:37.827174 11, 0x0, sum = 3
1616 16:47:37.827751 12, 0x0, sum = 4
1617 16:47:37.830461 best_step = 10
1618 16:47:37.830973
1619 16:47:37.831444 ==
1620 16:47:37.833881 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 16:47:37.837012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 16:47:37.837494 ==
1623 16:47:37.840297 RX Vref Scan: 1
1624 16:47:37.841022
1625 16:47:37.841422 Set Vref Range= 32 -> 127
1626 16:47:37.841778
1627 16:47:37.843805 RX Vref 32 -> 127, step: 1
1628 16:47:37.844371
1629 16:47:37.846931 RX Delay -95 -> 252, step: 8
1630 16:47:37.847405
1631 16:47:37.850141 Set Vref, RX VrefLevel [Byte0]: 32
1632 16:47:37.853583 [Byte1]: 32
1633 16:47:37.854161
1634 16:47:37.857953 Set Vref, RX VrefLevel [Byte0]: 33
1635 16:47:37.860712 [Byte1]: 33
1636 16:47:37.863875
1637 16:47:37.864441 Set Vref, RX VrefLevel [Byte0]: 34
1638 16:47:37.866981 [Byte1]: 34
1639 16:47:37.871472
1640 16:47:37.872040 Set Vref, RX VrefLevel [Byte0]: 35
1641 16:47:37.874720 [Byte1]: 35
1642 16:47:37.879200
1643 16:47:37.879774 Set Vref, RX VrefLevel [Byte0]: 36
1644 16:47:37.882020 [Byte1]: 36
1645 16:47:37.886654
1646 16:47:37.887219 Set Vref, RX VrefLevel [Byte0]: 37
1647 16:47:37.889964 [Byte1]: 37
1648 16:47:37.894481
1649 16:47:37.895056 Set Vref, RX VrefLevel [Byte0]: 38
1650 16:47:37.897387 [Byte1]: 38
1651 16:47:37.901815
1652 16:47:37.904912 Set Vref, RX VrefLevel [Byte0]: 39
1653 16:47:37.905483 [Byte1]: 39
1654 16:47:37.909885
1655 16:47:37.910489 Set Vref, RX VrefLevel [Byte0]: 40
1656 16:47:37.912590 [Byte1]: 40
1657 16:47:37.917216
1658 16:47:37.917789 Set Vref, RX VrefLevel [Byte0]: 41
1659 16:47:37.920586 [Byte1]: 41
1660 16:47:37.925003
1661 16:47:37.925571 Set Vref, RX VrefLevel [Byte0]: 42
1662 16:47:37.927981 [Byte1]: 42
1663 16:47:37.931941
1664 16:47:37.932502 Set Vref, RX VrefLevel [Byte0]: 43
1665 16:47:37.935427 [Byte1]: 43
1666 16:47:37.939537
1667 16:47:37.940106 Set Vref, RX VrefLevel [Byte0]: 44
1668 16:47:37.942736 [Byte1]: 44
1669 16:47:37.947696
1670 16:47:37.948164 Set Vref, RX VrefLevel [Byte0]: 45
1671 16:47:37.950844 [Byte1]: 45
1672 16:47:37.954885
1673 16:47:37.955356 Set Vref, RX VrefLevel [Byte0]: 46
1674 16:47:37.958182 [Byte1]: 46
1675 16:47:37.963164
1676 16:47:37.963729 Set Vref, RX VrefLevel [Byte0]: 47
1677 16:47:37.965522 [Byte1]: 47
1678 16:47:37.969761
1679 16:47:37.970231 Set Vref, RX VrefLevel [Byte0]: 48
1680 16:47:37.973347 [Byte1]: 48
1681 16:47:37.977827
1682 16:47:37.978462 Set Vref, RX VrefLevel [Byte0]: 49
1683 16:47:37.981042 [Byte1]: 49
1684 16:47:37.985540
1685 16:47:37.986111 Set Vref, RX VrefLevel [Byte0]: 50
1686 16:47:37.988679 [Byte1]: 50
1687 16:47:37.992983
1688 16:47:37.993548 Set Vref, RX VrefLevel [Byte0]: 51
1689 16:47:37.996235 [Byte1]: 51
1690 16:47:38.000782
1691 16:47:38.004355 Set Vref, RX VrefLevel [Byte0]: 52
1692 16:47:38.004929 [Byte1]: 52
1693 16:47:38.007837
1694 16:47:38.008399 Set Vref, RX VrefLevel [Byte0]: 53
1695 16:47:38.011356 [Byte1]: 53
1696 16:47:38.015503
1697 16:47:38.016072 Set Vref, RX VrefLevel [Byte0]: 54
1698 16:47:38.019284 [Byte1]: 54
1699 16:47:38.023757
1700 16:47:38.024323 Set Vref, RX VrefLevel [Byte0]: 55
1701 16:47:38.026834 [Byte1]: 55
1702 16:47:38.030632
1703 16:47:38.031148 Set Vref, RX VrefLevel [Byte0]: 56
1704 16:47:38.035213 [Byte1]: 56
1705 16:47:38.038914
1706 16:47:38.039481 Set Vref, RX VrefLevel [Byte0]: 57
1707 16:47:38.041671 [Byte1]: 57
1708 16:47:38.046513
1709 16:47:38.047070 Set Vref, RX VrefLevel [Byte0]: 58
1710 16:47:38.049673 [Byte1]: 58
1711 16:47:38.053924
1712 16:47:38.054533 Set Vref, RX VrefLevel [Byte0]: 59
1713 16:47:38.056771 [Byte1]: 59
1714 16:47:38.061131
1715 16:47:38.061592 Set Vref, RX VrefLevel [Byte0]: 60
1716 16:47:38.064439 [Byte1]: 60
1717 16:47:38.069024
1718 16:47:38.069484 Set Vref, RX VrefLevel [Byte0]: 61
1719 16:47:38.072430 [Byte1]: 61
1720 16:47:38.076252
1721 16:47:38.076763 Set Vref, RX VrefLevel [Byte0]: 62
1722 16:47:38.079736 [Byte1]: 62
1723 16:47:38.083691
1724 16:47:38.084157 Set Vref, RX VrefLevel [Byte0]: 63
1725 16:47:38.087187 [Byte1]: 63
1726 16:47:38.092165
1727 16:47:38.092722 Set Vref, RX VrefLevel [Byte0]: 64
1728 16:47:38.095122 [Byte1]: 64
1729 16:47:38.099372
1730 16:47:38.099837 Set Vref, RX VrefLevel [Byte0]: 65
1731 16:47:38.102283 [Byte1]: 65
1732 16:47:38.107083
1733 16:47:38.107653 Set Vref, RX VrefLevel [Byte0]: 66
1734 16:47:38.110720 [Byte1]: 66
1735 16:47:38.114831
1736 16:47:38.115397 Set Vref, RX VrefLevel [Byte0]: 67
1737 16:47:38.117510 [Byte1]: 67
1738 16:47:38.123001
1739 16:47:38.123568 Set Vref, RX VrefLevel [Byte0]: 68
1740 16:47:38.125866 [Byte1]: 68
1741 16:47:38.130254
1742 16:47:38.130891 Set Vref, RX VrefLevel [Byte0]: 69
1743 16:47:38.135957 [Byte1]: 69
1744 16:47:38.136526
1745 16:47:38.139478 Set Vref, RX VrefLevel [Byte0]: 70
1746 16:47:38.142531 [Byte1]: 70
1747 16:47:38.143014
1748 16:47:38.145999 Set Vref, RX VrefLevel [Byte0]: 71
1749 16:47:38.149378 [Byte1]: 71
1750 16:47:38.149946
1751 16:47:38.152805 Set Vref, RX VrefLevel [Byte0]: 72
1752 16:47:38.156371 [Byte1]: 72
1753 16:47:38.160202
1754 16:47:38.160771 Set Vref, RX VrefLevel [Byte0]: 73
1755 16:47:38.163008 [Byte1]: 73
1756 16:47:38.167489
1757 16:47:38.168073 Set Vref, RX VrefLevel [Byte0]: 74
1758 16:47:38.171530 [Byte1]: 74
1759 16:47:38.175230
1760 16:47:38.175867 Set Vref, RX VrefLevel [Byte0]: 75
1761 16:47:38.179006 [Byte1]: 75
1762 16:47:38.182468
1763 16:47:38.182938 Set Vref, RX VrefLevel [Byte0]: 76
1764 16:47:38.185993 [Byte1]: 76
1765 16:47:38.190440
1766 16:47:38.190870 Set Vref, RX VrefLevel [Byte0]: 77
1767 16:47:38.193491 [Byte1]: 77
1768 16:47:38.198217
1769 16:47:38.198882 Final RX Vref Byte 0 = 53 to rank0
1770 16:47:38.201464 Final RX Vref Byte 1 = 63 to rank0
1771 16:47:38.204958 Final RX Vref Byte 0 = 53 to rank1
1772 16:47:38.207702 Final RX Vref Byte 1 = 63 to rank1==
1773 16:47:38.210986 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 16:47:38.217973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 16:47:38.218585 ==
1776 16:47:38.218962 DQS Delay:
1777 16:47:38.219306 DQS0 = 0, DQS1 = 0
1778 16:47:38.221513 DQM Delay:
1779 16:47:38.221977 DQM0 = 93, DQM1 = 82
1780 16:47:38.224570 DQ Delay:
1781 16:47:38.228252 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1782 16:47:38.231401 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1783 16:47:38.234464 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1784 16:47:38.238865 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1785 16:47:38.239467
1786 16:47:38.239843
1787 16:47:38.244472 [DQSOSCAuto] RK0, (LSB)MR18= 0x3350, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1788 16:47:38.247724 CH1 RK0: MR19=606, MR18=3350
1789 16:47:38.255255 CH1_RK0: MR19=0x606, MR18=0x3350, DQSOSC=389, MR23=63, INC=97, DEC=65
1790 16:47:38.255827
1791 16:47:38.257926 ----->DramcWriteLeveling(PI) begin...
1792 16:47:38.258535 ==
1793 16:47:38.261055 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 16:47:38.264833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 16:47:38.265324 ==
1796 16:47:38.267821 Write leveling (Byte 0): 27 => 27
1797 16:47:38.270963 Write leveling (Byte 1): 29 => 29
1798 16:47:38.274474 DramcWriteLeveling(PI) end<-----
1799 16:47:38.274938
1800 16:47:38.275306 ==
1801 16:47:38.277369 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 16:47:38.281055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 16:47:38.281618 ==
1804 16:47:38.284242 [Gating] SW mode calibration
1805 16:47:38.291020 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 16:47:38.297683 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 16:47:38.301035 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 16:47:38.307410 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1809 16:47:38.310480 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 16:47:38.314320 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 16:47:38.320809 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 16:47:38.323971 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 16:47:38.327148 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 16:47:38.330670 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 16:47:38.337820 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 16:47:38.340407 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 16:47:38.343844 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 16:47:38.350855 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 16:47:38.353912 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 16:47:38.357215 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 16:47:38.364412 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 16:47:38.366971 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 16:47:38.370685 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 16:47:38.377648 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1825 16:47:38.380322 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 16:47:38.383333 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 16:47:38.391165 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 16:47:38.393757 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 16:47:38.397000 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 16:47:38.403446 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 16:47:38.407230 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 16:47:38.410329 0 9 4 | B1->B0 | 2626 2626 | 1 0 | (1 1) (0 0)
1833 16:47:38.416940 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 16:47:38.420787 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 16:47:38.423640 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 16:47:38.430442 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 16:47:38.433653 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 16:47:38.437025 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 16:47:38.443485 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 16:47:38.446429 0 10 4 | B1->B0 | 2b2b 3030 | 0 0 | (0 1) (0 1)
1841 16:47:38.450625 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 16:47:38.457203 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 16:47:38.459888 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 16:47:38.463493 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 16:47:38.470072 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 16:47:38.472842 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 16:47:38.476495 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 16:47:38.482955 0 11 4 | B1->B0 | 3131 2e2e | 1 0 | (0 0) (0 0)
1849 16:47:38.486328 0 11 8 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
1850 16:47:38.490003 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 16:47:38.496460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 16:47:38.499600 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 16:47:38.503009 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 16:47:38.509390 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 16:47:38.513194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 16:47:38.516505 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1857 16:47:38.523071 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 16:47:38.526504 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 16:47:38.530003 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 16:47:38.532794 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 16:47:38.539154 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 16:47:38.543140 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 16:47:38.546097 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 16:47:38.552863 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 16:47:38.556063 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 16:47:38.559818 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 16:47:38.565934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 16:47:38.569425 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 16:47:38.572561 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 16:47:38.579367 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 16:47:38.582460 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 16:47:38.586149 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1873 16:47:38.592753 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1874 16:47:38.596294 Total UI for P1: 0, mck2ui 16
1875 16:47:38.598971 best dqsien dly found for B0: ( 0, 14, 4)
1876 16:47:38.602530 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 16:47:38.605401 Total UI for P1: 0, mck2ui 16
1878 16:47:38.609001 best dqsien dly found for B1: ( 0, 14, 6)
1879 16:47:38.612692 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1880 16:47:38.615472 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1881 16:47:38.615938
1882 16:47:38.618618 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1883 16:47:38.622425 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 16:47:38.625322 [Gating] SW calibration Done
1885 16:47:38.625787 ==
1886 16:47:38.629139 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 16:47:38.632338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 16:47:38.635230 ==
1889 16:47:38.635694 RX Vref Scan: 0
1890 16:47:38.636074
1891 16:47:38.638669 RX Vref 0 -> 0, step: 1
1892 16:47:38.639133
1893 16:47:38.642643 RX Delay -130 -> 252, step: 16
1894 16:47:38.645571 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1895 16:47:38.648763 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1896 16:47:38.652466 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1897 16:47:38.655523 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1898 16:47:38.663100 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1899 16:47:38.665572 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1900 16:47:38.669472 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1901 16:47:38.672757 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1902 16:47:38.675957 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1903 16:47:38.682324 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1904 16:47:38.685689 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1905 16:47:38.689380 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1906 16:47:38.692032 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1907 16:47:38.695278 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1908 16:47:38.702121 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1909 16:47:38.705324 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1910 16:47:38.705894 ==
1911 16:47:38.708685 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 16:47:38.711927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 16:47:38.712397 ==
1914 16:47:38.715273 DQS Delay:
1915 16:47:38.715838 DQS0 = 0, DQS1 = 0
1916 16:47:38.716215 DQM Delay:
1917 16:47:38.718269 DQM0 = 88, DQM1 = 81
1918 16:47:38.718766 DQ Delay:
1919 16:47:38.721948 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1920 16:47:38.725466 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1921 16:47:38.728568 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1922 16:47:38.731773 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1923 16:47:38.732240
1924 16:47:38.732612
1925 16:47:38.733125 ==
1926 16:47:38.735113 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 16:47:38.741391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 16:47:38.741858 ==
1929 16:47:38.742233
1930 16:47:38.742624
1931 16:47:38.743073 TX Vref Scan disable
1932 16:47:38.744987 == TX Byte 0 ==
1933 16:47:38.748676 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1934 16:47:38.755591 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1935 16:47:38.756174 == TX Byte 1 ==
1936 16:47:38.758231 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1937 16:47:38.765475 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1938 16:47:38.766048 ==
1939 16:47:38.768665 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 16:47:38.771968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 16:47:38.772539 ==
1942 16:47:38.784265 TX Vref=22, minBit 13, minWin=27, winSum=454
1943 16:47:38.787585 TX Vref=24, minBit 13, minWin=27, winSum=454
1944 16:47:38.791438 TX Vref=26, minBit 13, minWin=27, winSum=455
1945 16:47:38.794828 TX Vref=28, minBit 8, minWin=28, winSum=460
1946 16:47:38.798026 TX Vref=30, minBit 9, minWin=27, winSum=457
1947 16:47:38.804195 TX Vref=32, minBit 9, minWin=27, winSum=457
1948 16:47:38.808045 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
1949 16:47:38.808620
1950 16:47:38.810835 Final TX Range 1 Vref 28
1951 16:47:38.811304
1952 16:47:38.811709 ==
1953 16:47:38.814194 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 16:47:38.818319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 16:47:38.821065 ==
1956 16:47:38.821638
1957 16:47:38.822010
1958 16:47:38.822377 TX Vref Scan disable
1959 16:47:38.824115 == TX Byte 0 ==
1960 16:47:38.827847 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1961 16:47:38.830933 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1962 16:47:38.834133 == TX Byte 1 ==
1963 16:47:38.838739 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1964 16:47:38.841022 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1965 16:47:38.844342
1966 16:47:38.844808 [DATLAT]
1967 16:47:38.845343 Freq=800, CH1 RK1
1968 16:47:38.845835
1969 16:47:38.847656 DATLAT Default: 0xa
1970 16:47:38.848122 0, 0xFFFF, sum = 0
1971 16:47:38.851775 1, 0xFFFF, sum = 0
1972 16:47:38.852370 2, 0xFFFF, sum = 0
1973 16:47:38.854138 3, 0xFFFF, sum = 0
1974 16:47:38.854645 4, 0xFFFF, sum = 0
1975 16:47:38.857876 5, 0xFFFF, sum = 0
1976 16:47:38.861522 6, 0xFFFF, sum = 0
1977 16:47:38.862104 7, 0xFFFF, sum = 0
1978 16:47:38.864582 8, 0xFFFF, sum = 0
1979 16:47:38.865158 9, 0x0, sum = 1
1980 16:47:38.865541 10, 0x0, sum = 2
1981 16:47:38.867588 11, 0x0, sum = 3
1982 16:47:38.868166 12, 0x0, sum = 4
1983 16:47:38.870895 best_step = 10
1984 16:47:38.871465
1985 16:47:38.871845 ==
1986 16:47:38.874457 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 16:47:38.877511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 16:47:38.878116 ==
1989 16:47:38.881319 RX Vref Scan: 0
1990 16:47:38.881888
1991 16:47:38.884367 RX Vref 0 -> 0, step: 1
1992 16:47:38.884838
1993 16:47:38.885213 RX Delay -95 -> 252, step: 8
1994 16:47:38.891093 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1995 16:47:38.894730 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1996 16:47:38.898052 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1997 16:47:38.900932 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1998 16:47:38.904458 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
1999 16:47:38.911249 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2000 16:47:38.914792 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2001 16:47:38.917893 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2002 16:47:38.921073 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2003 16:47:38.924055 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2004 16:47:38.930950 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2005 16:47:38.934123 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2006 16:47:38.937327 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2007 16:47:38.941113 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2008 16:47:38.944451 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2009 16:47:38.950523 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2010 16:47:38.951116 ==
2011 16:47:38.954015 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 16:47:38.957340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 16:47:38.957956 ==
2014 16:47:38.958342 DQS Delay:
2015 16:47:38.960665 DQS0 = 0, DQS1 = 0
2016 16:47:38.961235 DQM Delay:
2017 16:47:38.963612 DQM0 = 92, DQM1 = 84
2018 16:47:38.964081 DQ Delay:
2019 16:47:38.967208 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2020 16:47:38.971274 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2021 16:47:38.973635 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2022 16:47:38.977090 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2023 16:47:38.977668
2024 16:47:38.978046
2025 16:47:38.987259 [DQSOSCAuto] RK1, (LSB)MR18= 0x370b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 395 ps
2026 16:47:38.987843 CH1 RK1: MR19=606, MR18=370B
2027 16:47:38.994309 CH1_RK1: MR19=0x606, MR18=0x370B, DQSOSC=395, MR23=63, INC=94, DEC=63
2028 16:47:38.996988 [RxdqsGatingPostProcess] freq 800
2029 16:47:39.003564 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2030 16:47:39.007221 Pre-setting of DQS Precalculation
2031 16:47:39.010534 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2032 16:47:39.016985 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2033 16:47:39.026941 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2034 16:47:39.027517
2035 16:47:39.027895
2036 16:47:39.030316 [Calibration Summary] 1600 Mbps
2037 16:47:39.030938 CH 0, Rank 0
2038 16:47:39.033803 SW Impedance : PASS
2039 16:47:39.034277 DUTY Scan : NO K
2040 16:47:39.037506 ZQ Calibration : PASS
2041 16:47:39.039762 Jitter Meter : NO K
2042 16:47:39.040239 CBT Training : PASS
2043 16:47:39.043306 Write leveling : PASS
2044 16:47:39.043780 RX DQS gating : PASS
2045 16:47:39.046566 RX DQ/DQS(RDDQC) : PASS
2046 16:47:39.050272 TX DQ/DQS : PASS
2047 16:47:39.050877 RX DATLAT : PASS
2048 16:47:39.053524 RX DQ/DQS(Engine): PASS
2049 16:47:39.056652 TX OE : NO K
2050 16:47:39.057222 All Pass.
2051 16:47:39.057607
2052 16:47:39.057958 CH 0, Rank 1
2053 16:47:39.059665 SW Impedance : PASS
2054 16:47:39.063017 DUTY Scan : NO K
2055 16:47:39.063495 ZQ Calibration : PASS
2056 16:47:39.066102 Jitter Meter : NO K
2057 16:47:39.069790 CBT Training : PASS
2058 16:47:39.070403 Write leveling : PASS
2059 16:47:39.073188 RX DQS gating : PASS
2060 16:47:39.076510 RX DQ/DQS(RDDQC) : PASS
2061 16:47:39.077080 TX DQ/DQS : PASS
2062 16:47:39.079691 RX DATLAT : PASS
2063 16:47:39.082824 RX DQ/DQS(Engine): PASS
2064 16:47:39.083299 TX OE : NO K
2065 16:47:39.086502 All Pass.
2066 16:47:39.087074
2067 16:47:39.087455 CH 1, Rank 0
2068 16:47:39.089906 SW Impedance : PASS
2069 16:47:39.090506 DUTY Scan : NO K
2070 16:47:39.092728 ZQ Calibration : PASS
2071 16:47:39.096215 Jitter Meter : NO K
2072 16:47:39.096780 CBT Training : PASS
2073 16:47:39.099430 Write leveling : PASS
2074 16:47:39.102859 RX DQS gating : PASS
2075 16:47:39.103428 RX DQ/DQS(RDDQC) : PASS
2076 16:47:39.106063 TX DQ/DQS : PASS
2077 16:47:39.106679 RX DATLAT : PASS
2078 16:47:39.110477 RX DQ/DQS(Engine): PASS
2079 16:47:39.112871 TX OE : NO K
2080 16:47:39.113350 All Pass.
2081 16:47:39.113726
2082 16:47:39.114078 CH 1, Rank 1
2083 16:47:39.116103 SW Impedance : PASS
2084 16:47:39.119519 DUTY Scan : NO K
2085 16:47:39.120095 ZQ Calibration : PASS
2086 16:47:39.122850 Jitter Meter : NO K
2087 16:47:39.126529 CBT Training : PASS
2088 16:47:39.127098 Write leveling : PASS
2089 16:47:39.129470 RX DQS gating : PASS
2090 16:47:39.132580 RX DQ/DQS(RDDQC) : PASS
2091 16:47:39.133052 TX DQ/DQS : PASS
2092 16:47:39.136073 RX DATLAT : PASS
2093 16:47:39.139382 RX DQ/DQS(Engine): PASS
2094 16:47:39.139953 TX OE : NO K
2095 16:47:39.142392 All Pass.
2096 16:47:39.142863
2097 16:47:39.143237 DramC Write-DBI off
2098 16:47:39.145849 PER_BANK_REFRESH: Hybrid Mode
2099 16:47:39.146466 TX_TRACKING: ON
2100 16:47:39.149130 [GetDramInforAfterCalByMRR] Vendor 6.
2101 16:47:39.156088 [GetDramInforAfterCalByMRR] Revision 606.
2102 16:47:39.158625 [GetDramInforAfterCalByMRR] Revision 2 0.
2103 16:47:39.159100 MR0 0x3b3b
2104 16:47:39.159479 MR8 0x5151
2105 16:47:39.162263 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 16:47:39.165493
2107 16:47:39.166052 MR0 0x3b3b
2108 16:47:39.166651 MR8 0x5151
2109 16:47:39.168790 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 16:47:39.169356
2111 16:47:39.179118 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2112 16:47:39.182271 [FAST_K] Save calibration result to emmc
2113 16:47:39.185960 [FAST_K] Save calibration result to emmc
2114 16:47:39.188882 dram_init: config_dvfs: 1
2115 16:47:39.192098 dramc_set_vcore_voltage set vcore to 662500
2116 16:47:39.196136 Read voltage for 1200, 2
2117 16:47:39.196703 Vio18 = 0
2118 16:47:39.197081 Vcore = 662500
2119 16:47:39.198580 Vdram = 0
2120 16:47:39.199049 Vddq = 0
2121 16:47:39.199426 Vmddr = 0
2122 16:47:39.205607 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2123 16:47:39.209257 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2124 16:47:39.212475 MEM_TYPE=3, freq_sel=15
2125 16:47:39.215603 sv_algorithm_assistance_LP4_1600
2126 16:47:39.219159 ============ PULL DRAM RESETB DOWN ============
2127 16:47:39.222596 ========== PULL DRAM RESETB DOWN end =========
2128 16:47:39.228660 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2129 16:47:39.232340 ===================================
2130 16:47:39.232850 LPDDR4 DRAM CONFIGURATION
2131 16:47:39.235892 ===================================
2132 16:47:39.238953 EX_ROW_EN[0] = 0x0
2133 16:47:39.242394 EX_ROW_EN[1] = 0x0
2134 16:47:39.243187 LP4Y_EN = 0x0
2135 16:47:39.245653 WORK_FSP = 0x0
2136 16:47:39.246217 WL = 0x4
2137 16:47:39.248651 RL = 0x4
2138 16:47:39.249126 BL = 0x2
2139 16:47:39.252104 RPST = 0x0
2140 16:47:39.252670 RD_PRE = 0x0
2141 16:47:39.255516 WR_PRE = 0x1
2142 16:47:39.255983 WR_PST = 0x0
2143 16:47:39.258300 DBI_WR = 0x0
2144 16:47:39.258914 DBI_RD = 0x0
2145 16:47:39.261807 OTF = 0x1
2146 16:47:39.265034 ===================================
2147 16:47:39.268596 ===================================
2148 16:47:39.269216 ANA top config
2149 16:47:39.272712 ===================================
2150 16:47:39.275067 DLL_ASYNC_EN = 0
2151 16:47:39.278520 ALL_SLAVE_EN = 0
2152 16:47:39.281610 NEW_RANK_MODE = 1
2153 16:47:39.282088 DLL_IDLE_MODE = 1
2154 16:47:39.284990 LP45_APHY_COMB_EN = 1
2155 16:47:39.288855 TX_ODT_DIS = 1
2156 16:47:39.291787 NEW_8X_MODE = 1
2157 16:47:39.295208 ===================================
2158 16:47:39.298327 ===================================
2159 16:47:39.301532 data_rate = 2400
2160 16:47:39.305005 CKR = 1
2161 16:47:39.305573 DQ_P2S_RATIO = 8
2162 16:47:39.308263 ===================================
2163 16:47:39.311306 CA_P2S_RATIO = 8
2164 16:47:39.315033 DQ_CA_OPEN = 0
2165 16:47:39.318181 DQ_SEMI_OPEN = 0
2166 16:47:39.322098 CA_SEMI_OPEN = 0
2167 16:47:39.322698 CA_FULL_RATE = 0
2168 16:47:39.324832 DQ_CKDIV4_EN = 0
2169 16:47:39.328031 CA_CKDIV4_EN = 0
2170 16:47:39.331397 CA_PREDIV_EN = 0
2171 16:47:39.334592 PH8_DLY = 17
2172 16:47:39.338663 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2173 16:47:39.339235 DQ_AAMCK_DIV = 4
2174 16:47:39.341571 CA_AAMCK_DIV = 4
2175 16:47:39.344736 CA_ADMCK_DIV = 4
2176 16:47:39.347809 DQ_TRACK_CA_EN = 0
2177 16:47:39.351634 CA_PICK = 1200
2178 16:47:39.354537 CA_MCKIO = 1200
2179 16:47:39.358145 MCKIO_SEMI = 0
2180 16:47:39.361514 PLL_FREQ = 2366
2181 16:47:39.362079 DQ_UI_PI_RATIO = 32
2182 16:47:39.364478 CA_UI_PI_RATIO = 0
2183 16:47:39.368643 ===================================
2184 16:47:39.371160 ===================================
2185 16:47:39.374461 memory_type:LPDDR4
2186 16:47:39.378118 GP_NUM : 10
2187 16:47:39.378739 SRAM_EN : 1
2188 16:47:39.381192 MD32_EN : 0
2189 16:47:39.384311 ===================================
2190 16:47:39.384783 [ANA_INIT] >>>>>>>>>>>>>>
2191 16:47:39.387751 <<<<<< [CONFIGURE PHASE]: ANA_TX
2192 16:47:39.391390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2193 16:47:39.394548 ===================================
2194 16:47:39.398210 data_rate = 2400,PCW = 0X5b00
2195 16:47:39.401544 ===================================
2196 16:47:39.404717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2197 16:47:39.411530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 16:47:39.418373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 16:47:39.421644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2200 16:47:39.425090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2201 16:47:39.427925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2202 16:47:39.431104 [ANA_INIT] flow start
2203 16:47:39.431673 [ANA_INIT] PLL >>>>>>>>
2204 16:47:39.434658 [ANA_INIT] PLL <<<<<<<<
2205 16:47:39.438389 [ANA_INIT] MIDPI >>>>>>>>
2206 16:47:39.438955 [ANA_INIT] MIDPI <<<<<<<<
2207 16:47:39.441072 [ANA_INIT] DLL >>>>>>>>
2208 16:47:39.444724 [ANA_INIT] DLL <<<<<<<<
2209 16:47:39.445290 [ANA_INIT] flow end
2210 16:47:39.451262 ============ LP4 DIFF to SE enter ============
2211 16:47:39.454344 ============ LP4 DIFF to SE exit ============
2212 16:47:39.454865 [ANA_INIT] <<<<<<<<<<<<<
2213 16:47:39.457948 [Flow] Enable top DCM control >>>>>
2214 16:47:39.461008 [Flow] Enable top DCM control <<<<<
2215 16:47:39.464339 Enable DLL master slave shuffle
2216 16:47:39.471194 ==============================================================
2217 16:47:39.474452 Gating Mode config
2218 16:47:39.477477 ==============================================================
2219 16:47:39.481120 Config description:
2220 16:47:39.491158 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2221 16:47:39.497680 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2222 16:47:39.500899 SELPH_MODE 0: By rank 1: By Phase
2223 16:47:39.507639 ==============================================================
2224 16:47:39.511120 GAT_TRACK_EN = 1
2225 16:47:39.514936 RX_GATING_MODE = 2
2226 16:47:39.517679 RX_GATING_TRACK_MODE = 2
2227 16:47:39.518247 SELPH_MODE = 1
2228 16:47:39.520612 PICG_EARLY_EN = 1
2229 16:47:39.524247 VALID_LAT_VALUE = 1
2230 16:47:39.530844 ==============================================================
2231 16:47:39.533802 Enter into Gating configuration >>>>
2232 16:47:39.537696 Exit from Gating configuration <<<<
2233 16:47:39.540511 Enter into DVFS_PRE_config >>>>>
2234 16:47:39.551035 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2235 16:47:39.554028 Exit from DVFS_PRE_config <<<<<
2236 16:47:39.557466 Enter into PICG configuration >>>>
2237 16:47:39.560900 Exit from PICG configuration <<<<
2238 16:47:39.564239 [RX_INPUT] configuration >>>>>
2239 16:47:39.566992 [RX_INPUT] configuration <<<<<
2240 16:47:39.570795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2241 16:47:39.577201 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2242 16:47:39.583912 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 16:47:39.590883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 16:47:39.593612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 16:47:39.600686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 16:47:39.603764 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2247 16:47:39.610227 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2248 16:47:39.614099 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2249 16:47:39.617719 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2250 16:47:39.620552 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2251 16:47:39.627547 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2252 16:47:39.630477 ===================================
2253 16:47:39.630949 LPDDR4 DRAM CONFIGURATION
2254 16:47:39.634038 ===================================
2255 16:47:39.637039 EX_ROW_EN[0] = 0x0
2256 16:47:39.640321 EX_ROW_EN[1] = 0x0
2257 16:47:39.640892 LP4Y_EN = 0x0
2258 16:47:39.643565 WORK_FSP = 0x0
2259 16:47:39.644033 WL = 0x4
2260 16:47:39.647291 RL = 0x4
2261 16:47:39.647860 BL = 0x2
2262 16:47:39.650231 RPST = 0x0
2263 16:47:39.650765 RD_PRE = 0x0
2264 16:47:39.653897 WR_PRE = 0x1
2265 16:47:39.654394 WR_PST = 0x0
2266 16:47:39.657237 DBI_WR = 0x0
2267 16:47:39.657700 DBI_RD = 0x0
2268 16:47:39.660366 OTF = 0x1
2269 16:47:39.663697 ===================================
2270 16:47:39.667062 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2271 16:47:39.670746 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2272 16:47:39.677268 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2273 16:47:39.680639 ===================================
2274 16:47:39.681209 LPDDR4 DRAM CONFIGURATION
2275 16:47:39.683532 ===================================
2276 16:47:39.687740 EX_ROW_EN[0] = 0x10
2277 16:47:39.690447 EX_ROW_EN[1] = 0x0
2278 16:47:39.691029 LP4Y_EN = 0x0
2279 16:47:39.693869 WORK_FSP = 0x0
2280 16:47:39.694475 WL = 0x4
2281 16:47:39.696860 RL = 0x4
2282 16:47:39.697325 BL = 0x2
2283 16:47:39.700432 RPST = 0x0
2284 16:47:39.701037 RD_PRE = 0x0
2285 16:47:39.703590 WR_PRE = 0x1
2286 16:47:39.704055 WR_PST = 0x0
2287 16:47:39.706847 DBI_WR = 0x0
2288 16:47:39.707310 DBI_RD = 0x0
2289 16:47:39.710033 OTF = 0x1
2290 16:47:39.713388 ===================================
2291 16:47:39.720030 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2292 16:47:39.720606 ==
2293 16:47:39.723562 Dram Type= 6, Freq= 0, CH_0, rank 0
2294 16:47:39.726852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2295 16:47:39.727313 ==
2296 16:47:39.729698 [Duty_Offset_Calibration]
2297 16:47:39.730150 B0:2 B1:0 CA:1
2298 16:47:39.730575
2299 16:47:39.732908 [DutyScan_Calibration_Flow] k_type=0
2300 16:47:39.742539
2301 16:47:39.743013 ==CLK 0==
2302 16:47:39.745732 Final CLK duty delay cell = -4
2303 16:47:39.749731 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2304 16:47:39.753078 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2305 16:47:39.756221 [-4] AVG Duty = 4953%(X100)
2306 16:47:39.756546
2307 16:47:39.758988 CH0 CLK Duty spec in!! Max-Min= 156%
2308 16:47:39.762434 [DutyScan_Calibration_Flow] ====Done====
2309 16:47:39.762754
2310 16:47:39.766218 [DutyScan_Calibration_Flow] k_type=1
2311 16:47:39.781442
2312 16:47:39.781955 ==DQS 0 ==
2313 16:47:39.784564 Final DQS duty delay cell = 0
2314 16:47:39.788454 [0] MAX Duty = 5187%(X100), DQS PI = 32
2315 16:47:39.791487 [0] MIN Duty = 4938%(X100), DQS PI = 0
2316 16:47:39.794472 [0] AVG Duty = 5062%(X100)
2317 16:47:39.794929
2318 16:47:39.795314 ==DQS 1 ==
2319 16:47:39.798155 Final DQS duty delay cell = -4
2320 16:47:39.801223 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2321 16:47:39.805158 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2322 16:47:39.808201 [-4] AVG Duty = 5031%(X100)
2323 16:47:39.808660
2324 16:47:39.811591 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2325 16:47:39.812151
2326 16:47:39.814597 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2327 16:47:39.818618 [DutyScan_Calibration_Flow] ====Done====
2328 16:47:39.819180
2329 16:47:39.821440 [DutyScan_Calibration_Flow] k_type=3
2330 16:47:39.837735
2331 16:47:39.838289 ==DQM 0 ==
2332 16:47:39.841044 Final DQM duty delay cell = 0
2333 16:47:39.844403 [0] MAX Duty = 5062%(X100), DQS PI = 24
2334 16:47:39.847605 [0] MIN Duty = 4813%(X100), DQS PI = 2
2335 16:47:39.848170 [0] AVG Duty = 4937%(X100)
2336 16:47:39.851001
2337 16:47:39.851593 ==DQM 1 ==
2338 16:47:39.854665 Final DQM duty delay cell = -4
2339 16:47:39.857354 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2340 16:47:39.860939 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2341 16:47:39.865027 [-4] AVG Duty = 4906%(X100)
2342 16:47:39.865580
2343 16:47:39.867655 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2344 16:47:39.868210
2345 16:47:39.871246 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2346 16:47:39.873802 [DutyScan_Calibration_Flow] ====Done====
2347 16:47:39.874265
2348 16:47:39.877550 [DutyScan_Calibration_Flow] k_type=2
2349 16:47:39.894426
2350 16:47:39.894989 ==DQ 0 ==
2351 16:47:39.897241 Final DQ duty delay cell = -4
2352 16:47:39.900565 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2353 16:47:39.903449 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2354 16:47:39.906798 [-4] AVG Duty = 4953%(X100)
2355 16:47:39.907325
2356 16:47:39.907708 ==DQ 1 ==
2357 16:47:39.910006 Final DQ duty delay cell = 0
2358 16:47:39.913659 [0] MAX Duty = 4938%(X100), DQS PI = 4
2359 16:47:39.916600 [0] MIN Duty = 4907%(X100), DQS PI = 0
2360 16:47:39.920071 [0] AVG Duty = 4922%(X100)
2361 16:47:39.920550
2362 16:47:39.923198 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2363 16:47:39.923672
2364 16:47:39.926626 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2365 16:47:39.930167 [DutyScan_Calibration_Flow] ====Done====
2366 16:47:39.930783 ==
2367 16:47:39.933707 Dram Type= 6, Freq= 0, CH_1, rank 0
2368 16:47:39.936726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 16:47:39.937223 ==
2370 16:47:39.940105 [Duty_Offset_Calibration]
2371 16:47:39.940675 B0:0 B1:-1 CA:2
2372 16:47:39.941052
2373 16:47:39.943335 [DutyScan_Calibration_Flow] k_type=0
2374 16:47:39.954466
2375 16:47:39.955031 ==CLK 0==
2376 16:47:39.957292 Final CLK duty delay cell = 0
2377 16:47:39.960665 [0] MAX Duty = 5156%(X100), DQS PI = 16
2378 16:47:39.964017 [0] MIN Duty = 4938%(X100), DQS PI = 44
2379 16:47:39.966905 [0] AVG Duty = 5047%(X100)
2380 16:47:39.967380
2381 16:47:39.970594 CH1 CLK Duty spec in!! Max-Min= 218%
2382 16:47:39.973903 [DutyScan_Calibration_Flow] ====Done====
2383 16:47:39.974500
2384 16:47:39.976846 [DutyScan_Calibration_Flow] k_type=1
2385 16:47:39.993448
2386 16:47:39.994013 ==DQS 0 ==
2387 16:47:39.996455 Final DQS duty delay cell = 0
2388 16:47:40.000338 [0] MAX Duty = 5093%(X100), DQS PI = 24
2389 16:47:40.003497 [0] MIN Duty = 4969%(X100), DQS PI = 0
2390 16:47:40.006314 [0] AVG Duty = 5031%(X100)
2391 16:47:40.006918
2392 16:47:40.007346 ==DQS 1 ==
2393 16:47:40.010300 Final DQS duty delay cell = 0
2394 16:47:40.012835 [0] MAX Duty = 5156%(X100), DQS PI = 0
2395 16:47:40.016769 [0] MIN Duty = 4844%(X100), DQS PI = 36
2396 16:47:40.020415 [0] AVG Duty = 5000%(X100)
2397 16:47:40.020916
2398 16:47:40.023073 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2399 16:47:40.023550
2400 16:47:40.026292 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2401 16:47:40.029509 [DutyScan_Calibration_Flow] ====Done====
2402 16:47:40.029983
2403 16:47:40.033204 [DutyScan_Calibration_Flow] k_type=3
2404 16:47:40.050103
2405 16:47:40.050723 ==DQM 0 ==
2406 16:47:40.052738 Final DQM duty delay cell = 4
2407 16:47:40.056524 [4] MAX Duty = 5093%(X100), DQS PI = 6
2408 16:47:40.059748 [4] MIN Duty = 4969%(X100), DQS PI = 28
2409 16:47:40.062909 [4] AVG Duty = 5031%(X100)
2410 16:47:40.063474
2411 16:47:40.063855 ==DQM 1 ==
2412 16:47:40.066483 Final DQM duty delay cell = -4
2413 16:47:40.069667 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2414 16:47:40.073296 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2415 16:47:40.075922 [-4] AVG Duty = 4891%(X100)
2416 16:47:40.076396
2417 16:47:40.079640 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2418 16:47:40.080210
2419 16:47:40.083289 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2420 16:47:40.086180 [DutyScan_Calibration_Flow] ====Done====
2421 16:47:40.086770
2422 16:47:40.089496 [DutyScan_Calibration_Flow] k_type=2
2423 16:47:40.106506
2424 16:47:40.107065 ==DQ 0 ==
2425 16:47:40.110507 Final DQ duty delay cell = 0
2426 16:47:40.113075 [0] MAX Duty = 5062%(X100), DQS PI = 20
2427 16:47:40.116324 [0] MIN Duty = 4938%(X100), DQS PI = 44
2428 16:47:40.116800 [0] AVG Duty = 5000%(X100)
2429 16:47:40.119830
2430 16:47:40.120456 ==DQ 1 ==
2431 16:47:40.123040 Final DQ duty delay cell = 0
2432 16:47:40.126107 [0] MAX Duty = 5031%(X100), DQS PI = 2
2433 16:47:40.129671 [0] MIN Duty = 4813%(X100), DQS PI = 34
2434 16:47:40.130156 [0] AVG Duty = 4922%(X100)
2435 16:47:40.130591
2436 16:47:40.136017 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2437 16:47:40.136574
2438 16:47:40.139308 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2439 16:47:40.142971 [DutyScan_Calibration_Flow] ====Done====
2440 16:47:40.147724 nWR fixed to 30
2441 16:47:40.148299 [ModeRegInit_LP4] CH0 RK0
2442 16:47:40.149476 [ModeRegInit_LP4] CH0 RK1
2443 16:47:40.153555 [ModeRegInit_LP4] CH1 RK0
2444 16:47:40.155876 [ModeRegInit_LP4] CH1 RK1
2445 16:47:40.156349 match AC timing 7
2446 16:47:40.159571 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2447 16:47:40.166562 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2448 16:47:40.169901 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2449 16:47:40.176252 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2450 16:47:40.179090 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2451 16:47:40.179571 ==
2452 16:47:40.182530 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 16:47:40.185831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2454 16:47:40.186421 ==
2455 16:47:40.193232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2456 16:47:40.199399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2457 16:47:40.206518 [CA 0] Center 38 (7~69) winsize 63
2458 16:47:40.210103 [CA 1] Center 38 (8~69) winsize 62
2459 16:47:40.213042 [CA 2] Center 35 (5~66) winsize 62
2460 16:47:40.216321 [CA 3] Center 35 (4~66) winsize 63
2461 16:47:40.219917 [CA 4] Center 34 (4~65) winsize 62
2462 16:47:40.222900 [CA 5] Center 33 (3~63) winsize 61
2463 16:47:40.223417
2464 16:47:40.226122 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2465 16:47:40.226721
2466 16:47:40.229306 [CATrainingPosCal] consider 1 rank data
2467 16:47:40.232921 u2DelayCellTimex100 = 270/100 ps
2468 16:47:40.236091 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2469 16:47:40.243051 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2470 16:47:40.246288 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2471 16:47:40.249101 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2472 16:47:40.253080 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2473 16:47:40.255920 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2474 16:47:40.256389
2475 16:47:40.259604 CA PerBit enable=1, Macro0, CA PI delay=33
2476 16:47:40.260176
2477 16:47:40.262873 [CBTSetCACLKResult] CA Dly = 33
2478 16:47:40.263338 CS Dly: 6 (0~37)
2479 16:47:40.265900 ==
2480 16:47:40.269798 Dram Type= 6, Freq= 0, CH_0, rank 1
2481 16:47:40.272627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2482 16:47:40.273203 ==
2483 16:47:40.279474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2484 16:47:40.282408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2485 16:47:40.292524 [CA 0] Center 39 (8~70) winsize 63
2486 16:47:40.295468 [CA 1] Center 38 (8~69) winsize 62
2487 16:47:40.299253 [CA 2] Center 35 (5~66) winsize 62
2488 16:47:40.302013 [CA 3] Center 35 (5~66) winsize 62
2489 16:47:40.305751 [CA 4] Center 34 (4~65) winsize 62
2490 16:47:40.308866 [CA 5] Center 34 (4~64) winsize 61
2491 16:47:40.309441
2492 16:47:40.312411 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2493 16:47:40.312988
2494 16:47:40.315755 [CATrainingPosCal] consider 2 rank data
2495 16:47:40.318780 u2DelayCellTimex100 = 270/100 ps
2496 16:47:40.322000 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2497 16:47:40.328564 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2498 16:47:40.331952 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 16:47:40.335096 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2500 16:47:40.339090 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2501 16:47:40.341527 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2502 16:47:40.341994
2503 16:47:40.345108 CA PerBit enable=1, Macro0, CA PI delay=33
2504 16:47:40.345576
2505 16:47:40.348239 [CBTSetCACLKResult] CA Dly = 33
2506 16:47:40.348707 CS Dly: 7 (0~39)
2507 16:47:40.351707
2508 16:47:40.354862 ----->DramcWriteLeveling(PI) begin...
2509 16:47:40.355340 ==
2510 16:47:40.358311 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 16:47:40.361639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 16:47:40.362110 ==
2513 16:47:40.364990 Write leveling (Byte 0): 33 => 33
2514 16:47:40.368605 Write leveling (Byte 1): 30 => 30
2515 16:47:40.371646 DramcWriteLeveling(PI) end<-----
2516 16:47:40.372217
2517 16:47:40.372591 ==
2518 16:47:40.375052 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 16:47:40.378467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 16:47:40.378937 ==
2521 16:47:40.381813 [Gating] SW mode calibration
2522 16:47:40.388608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2523 16:47:40.395033 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2524 16:47:40.398913 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2525 16:47:40.401899 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2526 16:47:40.408615 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 16:47:40.412066 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 16:47:40.415004 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 16:47:40.421939 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 16:47:40.424902 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2531 16:47:40.428330 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2532 16:47:40.435011 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
2533 16:47:40.437875 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 16:47:40.441615 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 16:47:40.448072 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 16:47:40.451217 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 16:47:40.454466 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 16:47:40.457665 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2539 16:47:40.464547 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2540 16:47:40.468267 1 1 0 | B1->B0 | 3938 4646 | 1 0 | (0 0) (0 0)
2541 16:47:40.471487 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 16:47:40.478392 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 16:47:40.481350 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 16:47:40.484671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 16:47:40.491241 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 16:47:40.494799 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2547 16:47:40.497940 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2548 16:47:40.504729 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2549 16:47:40.507730 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 16:47:40.511760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 16:47:40.518265 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 16:47:40.521121 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 16:47:40.524279 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 16:47:40.531231 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 16:47:40.534456 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 16:47:40.537747 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 16:47:40.544873 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 16:47:40.547412 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 16:47:40.550766 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 16:47:40.557436 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 16:47:40.560970 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 16:47:40.564382 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 16:47:40.570700 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 16:47:40.574405 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 16:47:40.577554 Total UI for P1: 0, mck2ui 16
2566 16:47:40.580954 best dqsien dly found for B0: ( 1, 3, 28)
2567 16:47:40.584014 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 16:47:40.587484 Total UI for P1: 0, mck2ui 16
2569 16:47:40.590797 best dqsien dly found for B1: ( 1, 4, 0)
2570 16:47:40.594072 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2571 16:47:40.597594 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2572 16:47:40.598175
2573 16:47:40.600820 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2574 16:47:40.607261 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2575 16:47:40.607825 [Gating] SW calibration Done
2576 16:47:40.608207 ==
2577 16:47:40.610962 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 16:47:40.617610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 16:47:40.618195 ==
2580 16:47:40.618621 RX Vref Scan: 0
2581 16:47:40.618979
2582 16:47:40.620546 RX Vref 0 -> 0, step: 1
2583 16:47:40.621069
2584 16:47:40.623913 RX Delay -40 -> 252, step: 8
2585 16:47:40.627276 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2586 16:47:40.630485 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2587 16:47:40.633964 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2588 16:47:40.640909 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2589 16:47:40.643515 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2590 16:47:40.647171 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2591 16:47:40.650028 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2592 16:47:40.654186 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2593 16:47:40.656917 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2594 16:47:40.663646 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2595 16:47:40.667111 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2596 16:47:40.670600 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2597 16:47:40.673382 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2598 16:47:40.680640 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2599 16:47:40.683424 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2600 16:47:40.686937 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2601 16:47:40.687504 ==
2602 16:47:40.689991 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 16:47:40.694387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 16:47:40.694975 ==
2605 16:47:40.697036 DQS Delay:
2606 16:47:40.697503 DQS0 = 0, DQS1 = 0
2607 16:47:40.700010 DQM Delay:
2608 16:47:40.700572 DQM0 = 122, DQM1 = 110
2609 16:47:40.700951 DQ Delay:
2610 16:47:40.706730 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2611 16:47:40.709915 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2612 16:47:40.713245 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2613 16:47:40.716920 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2614 16:47:40.717483
2615 16:47:40.717858
2616 16:47:40.718197 ==
2617 16:47:40.720059 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 16:47:40.723606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 16:47:40.724170 ==
2620 16:47:40.724548
2621 16:47:40.724917
2622 16:47:40.726742 TX Vref Scan disable
2623 16:47:40.729662 == TX Byte 0 ==
2624 16:47:40.733878 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2625 16:47:40.736447 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2626 16:47:40.740101 == TX Byte 1 ==
2627 16:47:40.743842 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2628 16:47:40.746774 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2629 16:47:40.747246 ==
2630 16:47:40.749926 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 16:47:40.754209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 16:47:40.756411 ==
2633 16:47:40.766838 TX Vref=22, minBit 4, minWin=23, winSum=402
2634 16:47:40.770117 TX Vref=24, minBit 6, minWin=24, winSum=406
2635 16:47:40.773315 TX Vref=26, minBit 0, minWin=25, winSum=412
2636 16:47:40.776852 TX Vref=28, minBit 3, minWin=25, winSum=418
2637 16:47:40.780677 TX Vref=30, minBit 3, minWin=25, winSum=421
2638 16:47:40.783153 TX Vref=32, minBit 3, minWin=25, winSum=421
2639 16:47:40.789827 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 30
2640 16:47:40.790306
2641 16:47:40.793533 Final TX Range 1 Vref 30
2642 16:47:40.794113
2643 16:47:40.794667 ==
2644 16:47:40.796944 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 16:47:40.799525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 16:47:40.800010 ==
2647 16:47:40.803381
2648 16:47:40.804000
2649 16:47:40.804488 TX Vref Scan disable
2650 16:47:40.806711 == TX Byte 0 ==
2651 16:47:40.810063 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2652 16:47:40.813142 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2653 16:47:40.816629 == TX Byte 1 ==
2654 16:47:40.819540 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2655 16:47:40.823308 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2656 16:47:40.826570
2657 16:47:40.827141 [DATLAT]
2658 16:47:40.827625 Freq=1200, CH0 RK0
2659 16:47:40.828078
2660 16:47:40.829297 DATLAT Default: 0xd
2661 16:47:40.829777 0, 0xFFFF, sum = 0
2662 16:47:40.833478 1, 0xFFFF, sum = 0
2663 16:47:40.834062 2, 0xFFFF, sum = 0
2664 16:47:40.836483 3, 0xFFFF, sum = 0
2665 16:47:40.839485 4, 0xFFFF, sum = 0
2666 16:47:40.840067 5, 0xFFFF, sum = 0
2667 16:47:40.842540 6, 0xFFFF, sum = 0
2668 16:47:40.843027 7, 0xFFFF, sum = 0
2669 16:47:40.846453 8, 0xFFFF, sum = 0
2670 16:47:40.847040 9, 0xFFFF, sum = 0
2671 16:47:40.849501 10, 0xFFFF, sum = 0
2672 16:47:40.850091 11, 0xFFFF, sum = 0
2673 16:47:40.853118 12, 0x0, sum = 1
2674 16:47:40.853702 13, 0x0, sum = 2
2675 16:47:40.855897 14, 0x0, sum = 3
2676 16:47:40.856535 15, 0x0, sum = 4
2677 16:47:40.857043 best_step = 13
2678 16:47:40.859410
2679 16:47:40.859871 ==
2680 16:47:40.863220 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 16:47:40.866235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 16:47:40.866868 ==
2683 16:47:40.867243 RX Vref Scan: 1
2684 16:47:40.867588
2685 16:47:40.869354 Set Vref Range= 32 -> 127
2686 16:47:40.869816
2687 16:47:40.873084 RX Vref 32 -> 127, step: 1
2688 16:47:40.873661
2689 16:47:40.876283 RX Delay -13 -> 252, step: 4
2690 16:47:40.876777
2691 16:47:40.879346 Set Vref, RX VrefLevel [Byte0]: 32
2692 16:47:40.883155 [Byte1]: 32
2693 16:47:40.883725
2694 16:47:40.886557 Set Vref, RX VrefLevel [Byte0]: 33
2695 16:47:40.889704 [Byte1]: 33
2696 16:47:40.893313
2697 16:47:40.893873 Set Vref, RX VrefLevel [Byte0]: 34
2698 16:47:40.895872 [Byte1]: 34
2699 16:47:40.900520
2700 16:47:40.900983 Set Vref, RX VrefLevel [Byte0]: 35
2701 16:47:40.904400 [Byte1]: 35
2702 16:47:40.908518
2703 16:47:40.909093 Set Vref, RX VrefLevel [Byte0]: 36
2704 16:47:40.911753 [Byte1]: 36
2705 16:47:40.916377
2706 16:47:40.916940 Set Vref, RX VrefLevel [Byte0]: 37
2707 16:47:40.919426 [Byte1]: 37
2708 16:47:40.924753
2709 16:47:40.925317 Set Vref, RX VrefLevel [Byte0]: 38
2710 16:47:40.927443 [Byte1]: 38
2711 16:47:40.932634
2712 16:47:40.933197 Set Vref, RX VrefLevel [Byte0]: 39
2713 16:47:40.935274 [Byte1]: 39
2714 16:47:40.940030
2715 16:47:40.940598 Set Vref, RX VrefLevel [Byte0]: 40
2716 16:47:40.943326 [Byte1]: 40
2717 16:47:40.948572
2718 16:47:40.949134 Set Vref, RX VrefLevel [Byte0]: 41
2719 16:47:40.951138 [Byte1]: 41
2720 16:47:40.955793
2721 16:47:40.956386 Set Vref, RX VrefLevel [Byte0]: 42
2722 16:47:40.959313 [Byte1]: 42
2723 16:47:40.963731
2724 16:47:40.964293 Set Vref, RX VrefLevel [Byte0]: 43
2725 16:47:40.966799 [Byte1]: 43
2726 16:47:40.971486
2727 16:47:40.972050 Set Vref, RX VrefLevel [Byte0]: 44
2728 16:47:40.974669 [Byte1]: 44
2729 16:47:40.979085
2730 16:47:40.982789 Set Vref, RX VrefLevel [Byte0]: 45
2731 16:47:40.985895 [Byte1]: 45
2732 16:47:40.986507
2733 16:47:40.989007 Set Vref, RX VrefLevel [Byte0]: 46
2734 16:47:40.992443 [Byte1]: 46
2735 16:47:40.992910
2736 16:47:40.996074 Set Vref, RX VrefLevel [Byte0]: 47
2737 16:47:40.999353 [Byte1]: 47
2738 16:47:41.003100
2739 16:47:41.003666 Set Vref, RX VrefLevel [Byte0]: 48
2740 16:47:41.006644 [Byte1]: 48
2741 16:47:41.010988
2742 16:47:41.011574 Set Vref, RX VrefLevel [Byte0]: 49
2743 16:47:41.014136 [Byte1]: 49
2744 16:47:41.019567
2745 16:47:41.020128 Set Vref, RX VrefLevel [Byte0]: 50
2746 16:47:41.022081 [Byte1]: 50
2747 16:47:41.026556
2748 16:47:41.027121 Set Vref, RX VrefLevel [Byte0]: 51
2749 16:47:41.030220 [Byte1]: 51
2750 16:47:41.035271
2751 16:47:41.035837 Set Vref, RX VrefLevel [Byte0]: 52
2752 16:47:41.037589 [Byte1]: 52
2753 16:47:41.042658
2754 16:47:41.043229 Set Vref, RX VrefLevel [Byte0]: 53
2755 16:47:41.045916 [Byte1]: 53
2756 16:47:41.050538
2757 16:47:41.051112 Set Vref, RX VrefLevel [Byte0]: 54
2758 16:47:41.053949 [Byte1]: 54
2759 16:47:41.058272
2760 16:47:41.058958 Set Vref, RX VrefLevel [Byte0]: 55
2761 16:47:41.061523 [Byte1]: 55
2762 16:47:41.066824
2763 16:47:41.067393 Set Vref, RX VrefLevel [Byte0]: 56
2764 16:47:41.069261 [Byte1]: 56
2765 16:47:41.074190
2766 16:47:41.074836 Set Vref, RX VrefLevel [Byte0]: 57
2767 16:47:41.077630 [Byte1]: 57
2768 16:47:41.081870
2769 16:47:41.082484 Set Vref, RX VrefLevel [Byte0]: 58
2770 16:47:41.085301 [Byte1]: 58
2771 16:47:41.089858
2772 16:47:41.090481 Set Vref, RX VrefLevel [Byte0]: 59
2773 16:47:41.092858 [Byte1]: 59
2774 16:47:41.097739
2775 16:47:41.098332 Set Vref, RX VrefLevel [Byte0]: 60
2776 16:47:41.100939 [Byte1]: 60
2777 16:47:41.105635
2778 16:47:41.106222 Set Vref, RX VrefLevel [Byte0]: 61
2779 16:47:41.108850 [Byte1]: 61
2780 16:47:41.113503
2781 16:47:41.114099 Set Vref, RX VrefLevel [Byte0]: 62
2782 16:47:41.116699 [Byte1]: 62
2783 16:47:41.121630
2784 16:47:41.122198 Set Vref, RX VrefLevel [Byte0]: 63
2785 16:47:41.124648 [Byte1]: 63
2786 16:47:41.129255
2787 16:47:41.129824 Set Vref, RX VrefLevel [Byte0]: 64
2788 16:47:41.132699 [Byte1]: 64
2789 16:47:41.136948
2790 16:47:41.137476 Set Vref, RX VrefLevel [Byte0]: 65
2791 16:47:41.140872 [Byte1]: 65
2792 16:47:41.145472
2793 16:47:41.146043 Set Vref, RX VrefLevel [Byte0]: 66
2794 16:47:41.149363 [Byte1]: 66
2795 16:47:41.153173
2796 16:47:41.153745 Set Vref, RX VrefLevel [Byte0]: 67
2797 16:47:41.156238 [Byte1]: 67
2798 16:47:41.160850
2799 16:47:41.161421 Set Vref, RX VrefLevel [Byte0]: 68
2800 16:47:41.164514 [Byte1]: 68
2801 16:47:41.168877
2802 16:47:41.169442 Set Vref, RX VrefLevel [Byte0]: 69
2803 16:47:41.172291 [Byte1]: 69
2804 16:47:41.176623
2805 16:47:41.177197 Set Vref, RX VrefLevel [Byte0]: 70
2806 16:47:41.179802 [Byte1]: 70
2807 16:47:41.184630
2808 16:47:41.185209 Set Vref, RX VrefLevel [Byte0]: 71
2809 16:47:41.187781 [Byte1]: 71
2810 16:47:41.192392
2811 16:47:41.192974 Set Vref, RX VrefLevel [Byte0]: 72
2812 16:47:41.195653 [Byte1]: 72
2813 16:47:41.200231
2814 16:47:41.200815 Final RX Vref Byte 0 = 63 to rank0
2815 16:47:41.203607 Final RX Vref Byte 1 = 50 to rank0
2816 16:47:41.207166 Final RX Vref Byte 0 = 63 to rank1
2817 16:47:41.210468 Final RX Vref Byte 1 = 50 to rank1==
2818 16:47:41.213624 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 16:47:41.219911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 16:47:41.220476 ==
2821 16:47:41.220969 DQS Delay:
2822 16:47:41.223176 DQS0 = 0, DQS1 = 0
2823 16:47:41.223663 DQM Delay:
2824 16:47:41.224148 DQM0 = 123, DQM1 = 109
2825 16:47:41.228308 DQ Delay:
2826 16:47:41.229922 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2827 16:47:41.233599 DQ4 =126, DQ5 =116, DQ6 =132, DQ7 =128
2828 16:47:41.236269 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2829 16:47:41.240060 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2830 16:47:41.240633
2831 16:47:41.241126
2832 16:47:41.249825 [DQSOSCAuto] RK0, (LSB)MR18= 0xa07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2833 16:47:41.250435 CH0 RK0: MR19=404, MR18=A07
2834 16:47:41.257008 CH0_RK0: MR19=0x404, MR18=0xA07, DQSOSC=406, MR23=63, INC=39, DEC=26
2835 16:47:41.257585
2836 16:47:41.260050 ----->DramcWriteLeveling(PI) begin...
2837 16:47:41.260527 ==
2838 16:47:41.263476 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 16:47:41.270217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 16:47:41.270837 ==
2841 16:47:41.273363 Write leveling (Byte 0): 34 => 34
2842 16:47:41.273930 Write leveling (Byte 1): 31 => 31
2843 16:47:41.276600 DramcWriteLeveling(PI) end<-----
2844 16:47:41.277072
2845 16:47:41.277445 ==
2846 16:47:41.280040 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 16:47:41.286683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 16:47:41.287255 ==
2849 16:47:41.289769 [Gating] SW mode calibration
2850 16:47:41.296811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 16:47:41.299378 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 16:47:41.306381 0 15 0 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
2853 16:47:41.309589 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 16:47:41.312697 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 16:47:41.319288 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 16:47:41.323195 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 16:47:41.326040 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 16:47:41.332819 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 16:47:41.336382 0 15 28 | B1->B0 | 3131 3131 | 1 0 | (1 0) (0 0)
2860 16:47:41.339327 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 16:47:41.346727 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 16:47:41.349427 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 16:47:41.352719 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 16:47:41.356183 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 16:47:41.363055 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 16:47:41.366227 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 16:47:41.369635 1 0 28 | B1->B0 | 3232 3f3f | 0 0 | (0 0) (0 0)
2868 16:47:41.376234 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 16:47:41.379278 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 16:47:41.382699 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 16:47:41.389095 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 16:47:41.392536 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 16:47:41.395948 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 16:47:41.402611 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 16:47:41.406000 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2876 16:47:41.409310 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 16:47:41.415608 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 16:47:41.418834 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 16:47:41.422656 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 16:47:41.429184 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 16:47:41.432562 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 16:47:41.435385 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 16:47:41.442577 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 16:47:41.445838 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 16:47:41.449390 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 16:47:41.455700 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 16:47:41.459265 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 16:47:41.462418 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 16:47:41.469447 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 16:47:41.472254 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 16:47:41.475435 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2892 16:47:41.479487 Total UI for P1: 0, mck2ui 16
2893 16:47:41.482052 best dqsien dly found for B0: ( 1, 3, 26)
2894 16:47:41.488399 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2895 16:47:41.488955 Total UI for P1: 0, mck2ui 16
2896 16:47:41.491985 best dqsien dly found for B1: ( 1, 3, 28)
2897 16:47:41.498859 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2898 16:47:41.501941 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2899 16:47:41.502554
2900 16:47:41.505668 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2901 16:47:41.509344 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2902 16:47:41.511655 [Gating] SW calibration Done
2903 16:47:41.512121 ==
2904 16:47:41.515332 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 16:47:41.518511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 16:47:41.519074 ==
2907 16:47:41.522268 RX Vref Scan: 0
2908 16:47:41.522869
2909 16:47:41.523241 RX Vref 0 -> 0, step: 1
2910 16:47:41.523588
2911 16:47:41.524870 RX Delay -40 -> 252, step: 8
2912 16:47:41.528766 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2913 16:47:41.534985 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2914 16:47:41.538320 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2915 16:47:41.542029 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2916 16:47:41.545421 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2917 16:47:41.548542 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2918 16:47:41.555186 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2919 16:47:41.558344 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2920 16:47:41.561319 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2921 16:47:41.565001 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2922 16:47:41.568217 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2923 16:47:41.574822 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2924 16:47:41.578507 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2925 16:47:41.581509 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2926 16:47:41.585055 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2927 16:47:41.588430 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2928 16:47:41.591435 ==
2929 16:47:41.591911 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 16:47:41.598464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 16:47:41.599033 ==
2932 16:47:41.599417 DQS Delay:
2933 16:47:41.601400 DQS0 = 0, DQS1 = 0
2934 16:47:41.601971 DQM Delay:
2935 16:47:41.604683 DQM0 = 120, DQM1 = 108
2936 16:47:41.605246 DQ Delay:
2937 16:47:41.608065 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2938 16:47:41.611620 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2939 16:47:41.614980 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2940 16:47:41.618191 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2941 16:47:41.618796
2942 16:47:41.619174
2943 16:47:41.619529 ==
2944 16:47:41.621319 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 16:47:41.627916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 16:47:41.628487 ==
2947 16:47:41.628868
2948 16:47:41.629218
2949 16:47:41.629554 TX Vref Scan disable
2950 16:47:41.631012 == TX Byte 0 ==
2951 16:47:41.634796 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2952 16:47:41.638381 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2953 16:47:41.641442 == TX Byte 1 ==
2954 16:47:41.644983 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2955 16:47:41.647736 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2956 16:47:41.651763 ==
2957 16:47:41.654856 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 16:47:41.658252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 16:47:41.658757 ==
2960 16:47:41.669557 TX Vref=22, minBit 0, minWin=24, winSum=406
2961 16:47:41.672600 TX Vref=24, minBit 0, minWin=24, winSum=409
2962 16:47:41.676489 TX Vref=26, minBit 3, minWin=24, winSum=413
2963 16:47:41.679104 TX Vref=28, minBit 1, minWin=25, winSum=418
2964 16:47:41.682694 TX Vref=30, minBit 1, minWin=25, winSum=422
2965 16:47:41.689018 TX Vref=32, minBit 5, minWin=25, winSum=420
2966 16:47:41.692578 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 30
2967 16:47:41.693149
2968 16:47:41.696165 Final TX Range 1 Vref 30
2969 16:47:41.696735
2970 16:47:41.697112 ==
2971 16:47:41.699341 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 16:47:41.702867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 16:47:41.703440 ==
2974 16:47:41.705714
2975 16:47:41.706278
2976 16:47:41.706710 TX Vref Scan disable
2977 16:47:41.709899 == TX Byte 0 ==
2978 16:47:41.712314 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2979 16:47:41.715775 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2980 16:47:41.719051 == TX Byte 1 ==
2981 16:47:41.722646 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2982 16:47:41.725791 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2983 16:47:41.729360
2984 16:47:41.729925 [DATLAT]
2985 16:47:41.730329 Freq=1200, CH0 RK1
2986 16:47:41.730767
2987 16:47:41.732108 DATLAT Default: 0xd
2988 16:47:41.732600 0, 0xFFFF, sum = 0
2989 16:47:41.735957 1, 0xFFFF, sum = 0
2990 16:47:41.736531 2, 0xFFFF, sum = 0
2991 16:47:41.738912 3, 0xFFFF, sum = 0
2992 16:47:41.742712 4, 0xFFFF, sum = 0
2993 16:47:41.743306 5, 0xFFFF, sum = 0
2994 16:47:41.746157 6, 0xFFFF, sum = 0
2995 16:47:41.746772 7, 0xFFFF, sum = 0
2996 16:47:41.748834 8, 0xFFFF, sum = 0
2997 16:47:41.749324 9, 0xFFFF, sum = 0
2998 16:47:41.752224 10, 0xFFFF, sum = 0
2999 16:47:41.752714 11, 0xFFFF, sum = 0
3000 16:47:41.755836 12, 0x0, sum = 1
3001 16:47:41.756426 13, 0x0, sum = 2
3002 16:47:41.759239 14, 0x0, sum = 3
3003 16:47:41.759830 15, 0x0, sum = 4
3004 16:47:41.760327 best_step = 13
3005 16:47:41.762182
3006 16:47:41.762753 ==
3007 16:47:41.765619 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 16:47:41.769591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 16:47:41.770168 ==
3010 16:47:41.770647 RX Vref Scan: 0
3011 16:47:41.771007
3012 16:47:41.772012 RX Vref 0 -> 0, step: 1
3013 16:47:41.772477
3014 16:47:41.775915 RX Delay -21 -> 252, step: 4
3015 16:47:41.779045 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3016 16:47:41.785866 iDelay=199, Bit 1, Center 122 (55 ~ 190) 136
3017 16:47:41.789181 iDelay=199, Bit 2, Center 118 (51 ~ 186) 136
3018 16:47:41.792556 iDelay=199, Bit 3, Center 114 (47 ~ 182) 136
3019 16:47:41.795399 iDelay=199, Bit 4, Center 120 (51 ~ 190) 140
3020 16:47:41.799411 iDelay=199, Bit 5, Center 114 (51 ~ 178) 128
3021 16:47:41.805481 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3022 16:47:41.808907 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3023 16:47:41.812146 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3024 16:47:41.815867 iDelay=199, Bit 9, Center 94 (31 ~ 158) 128
3025 16:47:41.818903 iDelay=199, Bit 10, Center 110 (47 ~ 174) 128
3026 16:47:41.825763 iDelay=199, Bit 11, Center 104 (43 ~ 166) 124
3027 16:47:41.828793 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
3028 16:47:41.832725 iDelay=199, Bit 13, Center 110 (47 ~ 174) 128
3029 16:47:41.835440 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3030 16:47:41.838769 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
3031 16:47:41.841797 ==
3032 16:47:41.842262 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 16:47:41.849041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 16:47:41.849646 ==
3035 16:47:41.850021 DQS Delay:
3036 16:47:41.852060 DQS0 = 0, DQS1 = 0
3037 16:47:41.852624 DQM Delay:
3038 16:47:41.855401 DQM0 = 119, DQM1 = 107
3039 16:47:41.855865 DQ Delay:
3040 16:47:41.858911 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3041 16:47:41.861977 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =124
3042 16:47:41.865395 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3043 16:47:41.869026 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3044 16:47:41.869664
3045 16:47:41.870046
3046 16:47:41.878568 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3047 16:47:41.879117 CH0 RK1: MR19=403, MR18=CF5
3048 16:47:41.885236 CH0_RK1: MR19=0x403, MR18=0xCF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3049 16:47:41.888852 [RxdqsGatingPostProcess] freq 1200
3050 16:47:41.895223 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3051 16:47:41.898668 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 16:47:41.902207 best DQS1 dly(2T, 0.5T) = (0, 12)
3053 16:47:41.905214 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 16:47:41.908887 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3055 16:47:41.909449 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 16:47:41.911912 best DQS1 dly(2T, 0.5T) = (0, 11)
3057 16:47:41.915372 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 16:47:41.918775 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3059 16:47:41.921830 Pre-setting of DQS Precalculation
3060 16:47:41.928955 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3061 16:47:41.929520 ==
3062 16:47:41.932264 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 16:47:41.935297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 16:47:41.935857 ==
3065 16:47:41.941850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 16:47:41.948494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3067 16:47:41.955112 [CA 0] Center 37 (7~68) winsize 62
3068 16:47:41.958340 [CA 1] Center 37 (7~68) winsize 62
3069 16:47:41.961891 [CA 2] Center 35 (5~65) winsize 61
3070 16:47:41.964981 [CA 3] Center 34 (4~65) winsize 62
3071 16:47:41.968705 [CA 4] Center 34 (4~64) winsize 61
3072 16:47:41.971601 [CA 5] Center 33 (3~64) winsize 62
3073 16:47:41.972190
3074 16:47:41.975229 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3075 16:47:41.975695
3076 16:47:41.978178 [CATrainingPosCal] consider 1 rank data
3077 16:47:41.981553 u2DelayCellTimex100 = 270/100 ps
3078 16:47:41.985207 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3079 16:47:41.988707 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3080 16:47:41.995093 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3081 16:47:41.998552 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3082 16:47:42.001928 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3083 16:47:42.004965 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3084 16:47:42.005528
3085 16:47:42.008506 CA PerBit enable=1, Macro0, CA PI delay=33
3086 16:47:42.009071
3087 16:47:42.011905 [CBTSetCACLKResult] CA Dly = 33
3088 16:47:42.012473 CS Dly: 5 (0~36)
3089 16:47:42.014969 ==
3090 16:47:42.015536 Dram Type= 6, Freq= 0, CH_1, rank 1
3091 16:47:42.021556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 16:47:42.022129 ==
3093 16:47:42.025509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 16:47:42.031684 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3095 16:47:42.040977 [CA 0] Center 38 (8~68) winsize 61
3096 16:47:42.044247 [CA 1] Center 38 (7~69) winsize 63
3097 16:47:42.047561 [CA 2] Center 35 (5~66) winsize 62
3098 16:47:42.050875 [CA 3] Center 35 (5~65) winsize 61
3099 16:47:42.054102 [CA 4] Center 34 (4~64) winsize 61
3100 16:47:42.057646 [CA 5] Center 34 (4~64) winsize 61
3101 16:47:42.058215
3102 16:47:42.061186 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3103 16:47:42.061778
3104 16:47:42.065280 [CATrainingPosCal] consider 2 rank data
3105 16:47:42.067155 u2DelayCellTimex100 = 270/100 ps
3106 16:47:42.070525 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3107 16:47:42.077270 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3108 16:47:42.080766 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3109 16:47:42.083824 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3110 16:47:42.087577 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3111 16:47:42.090417 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3112 16:47:42.090905
3113 16:47:42.094148 CA PerBit enable=1, Macro0, CA PI delay=34
3114 16:47:42.094659
3115 16:47:42.098483 [CBTSetCACLKResult] CA Dly = 34
3116 16:47:42.099061 CS Dly: 6 (0~39)
3117 16:47:42.099441
3118 16:47:42.100592 ----->DramcWriteLeveling(PI) begin...
3119 16:47:42.104145 ==
3120 16:47:42.107209 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 16:47:42.110867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 16:47:42.111438 ==
3123 16:47:42.113773 Write leveling (Byte 0): 25 => 25
3124 16:47:42.117226 Write leveling (Byte 1): 28 => 28
3125 16:47:42.120586 DramcWriteLeveling(PI) end<-----
3126 16:47:42.121150
3127 16:47:42.121518 ==
3128 16:47:42.123528 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 16:47:42.127100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 16:47:42.127672 ==
3131 16:47:42.130684 [Gating] SW mode calibration
3132 16:47:42.137110 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3133 16:47:42.143668 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3134 16:47:42.147484 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 16:47:42.150025 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 16:47:42.157461 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 16:47:42.161127 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 16:47:42.163536 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 16:47:42.166873 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3140 16:47:42.173892 0 15 24 | B1->B0 | 2d2d 2626 | 0 0 | (0 1) (0 1)
3141 16:47:42.178045 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3142 16:47:42.180400 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 16:47:42.187108 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 16:47:42.190102 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 16:47:42.193948 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 16:47:42.200418 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 16:47:42.204061 1 0 20 | B1->B0 | 2525 2727 | 0 1 | (0 0) (0 0)
3148 16:47:42.207691 1 0 24 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
3149 16:47:42.213781 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 16:47:42.217482 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 16:47:42.220390 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 16:47:42.227438 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 16:47:42.230315 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 16:47:42.233871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 16:47:42.239949 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 16:47:42.243767 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 16:47:42.247049 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3158 16:47:42.253526 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 16:47:42.257051 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 16:47:42.260140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 16:47:42.266758 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 16:47:42.270004 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 16:47:42.273801 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 16:47:42.280344 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 16:47:42.284672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 16:47:42.286630 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 16:47:42.290036 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 16:47:42.296835 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 16:47:42.300155 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 16:47:42.303461 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 16:47:42.310731 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3172 16:47:42.313613 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3173 16:47:42.316518 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3174 16:47:42.319994 Total UI for P1: 0, mck2ui 16
3175 16:47:42.322916 best dqsien dly found for B0: ( 1, 3, 22)
3176 16:47:42.330584 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 16:47:42.331160 Total UI for P1: 0, mck2ui 16
3178 16:47:42.336553 best dqsien dly found for B1: ( 1, 3, 26)
3179 16:47:42.339814 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3180 16:47:42.343366 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3181 16:47:42.343938
3182 16:47:42.346518 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3183 16:47:42.349615 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3184 16:47:42.353402 [Gating] SW calibration Done
3185 16:47:42.353970 ==
3186 16:47:42.356823 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 16:47:42.359676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 16:47:42.360245 ==
3189 16:47:42.363204 RX Vref Scan: 0
3190 16:47:42.363769
3191 16:47:42.364161 RX Vref 0 -> 0, step: 1
3192 16:47:42.364764
3193 16:47:42.366422 RX Delay -40 -> 252, step: 8
3194 16:47:42.373061 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3195 16:47:42.376375 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3196 16:47:42.379665 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3197 16:47:42.383106 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3198 16:47:42.386575 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3199 16:47:42.389472 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3200 16:47:42.396237 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3201 16:47:42.399343 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3202 16:47:42.402986 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3203 16:47:42.407241 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3204 16:47:42.409710 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3205 16:47:42.416012 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3206 16:47:42.419312 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3207 16:47:42.422514 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3208 16:47:42.426307 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3209 16:47:42.433649 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3210 16:47:42.434227 ==
3211 16:47:42.436038 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 16:47:42.438927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 16:47:42.439403 ==
3214 16:47:42.439917 DQS Delay:
3215 16:47:42.442890 DQS0 = 0, DQS1 = 0
3216 16:47:42.443367 DQM Delay:
3217 16:47:42.445820 DQM0 = 120, DQM1 = 112
3218 16:47:42.446425 DQ Delay:
3219 16:47:42.449552 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3220 16:47:42.452907 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3221 16:47:42.455946 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3222 16:47:42.459147 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3223 16:47:42.459727
3224 16:47:42.460106
3225 16:47:42.462573 ==
3226 16:47:42.463244 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 16:47:42.469969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 16:47:42.470571 ==
3229 16:47:42.470960
3230 16:47:42.471309
3231 16:47:42.472223 TX Vref Scan disable
3232 16:47:42.472692 == TX Byte 0 ==
3233 16:47:42.475691 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3234 16:47:42.482991 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3235 16:47:42.483566 == TX Byte 1 ==
3236 16:47:42.486090 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3237 16:47:42.492399 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3238 16:47:42.492967 ==
3239 16:47:42.495573 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 16:47:42.499010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 16:47:42.499590 ==
3242 16:47:42.511141 TX Vref=22, minBit 1, minWin=24, winSum=404
3243 16:47:42.514407 TX Vref=24, minBit 11, minWin=24, winSum=410
3244 16:47:42.517695 TX Vref=26, minBit 3, minWin=25, winSum=416
3245 16:47:42.520911 TX Vref=28, minBit 10, minWin=25, winSum=418
3246 16:47:42.524397 TX Vref=30, minBit 1, minWin=26, winSum=423
3247 16:47:42.530903 TX Vref=32, minBit 9, minWin=25, winSum=423
3248 16:47:42.534602 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 30
3249 16:47:42.535169
3250 16:47:42.537409 Final TX Range 1 Vref 30
3251 16:47:42.537977
3252 16:47:42.538394 ==
3253 16:47:42.540305 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 16:47:42.543899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 16:47:42.547290 ==
3256 16:47:42.547856
3257 16:47:42.548238
3258 16:47:42.548586 TX Vref Scan disable
3259 16:47:42.550607 == TX Byte 0 ==
3260 16:47:42.553966 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3261 16:47:42.560599 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3262 16:47:42.561166 == TX Byte 1 ==
3263 16:47:42.564571 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3264 16:47:42.570408 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3265 16:47:42.570974
3266 16:47:42.571351 [DATLAT]
3267 16:47:42.571698 Freq=1200, CH1 RK0
3268 16:47:42.572032
3269 16:47:42.573936 DATLAT Default: 0xd
3270 16:47:42.574440 0, 0xFFFF, sum = 0
3271 16:47:42.577303 1, 0xFFFF, sum = 0
3272 16:47:42.580847 2, 0xFFFF, sum = 0
3273 16:47:42.581418 3, 0xFFFF, sum = 0
3274 16:47:42.583829 4, 0xFFFF, sum = 0
3275 16:47:42.584404 5, 0xFFFF, sum = 0
3276 16:47:42.586970 6, 0xFFFF, sum = 0
3277 16:47:42.587445 7, 0xFFFF, sum = 0
3278 16:47:42.590120 8, 0xFFFF, sum = 0
3279 16:47:42.590630 9, 0xFFFF, sum = 0
3280 16:47:42.593786 10, 0xFFFF, sum = 0
3281 16:47:42.594388 11, 0xFFFF, sum = 0
3282 16:47:42.596965 12, 0x0, sum = 1
3283 16:47:42.597542 13, 0x0, sum = 2
3284 16:47:42.600544 14, 0x0, sum = 3
3285 16:47:42.601120 15, 0x0, sum = 4
3286 16:47:42.603842 best_step = 13
3287 16:47:42.604477
3288 16:47:42.604860 ==
3289 16:47:42.607173 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 16:47:42.611253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 16:47:42.611823 ==
3292 16:47:42.612201 RX Vref Scan: 1
3293 16:47:42.612548
3294 16:47:42.613451 Set Vref Range= 32 -> 127
3295 16:47:42.613910
3296 16:47:42.618347 RX Vref 32 -> 127, step: 1
3297 16:47:42.618843
3298 16:47:42.620123 RX Delay -13 -> 252, step: 4
3299 16:47:42.620580
3300 16:47:42.623553 Set Vref, RX VrefLevel [Byte0]: 32
3301 16:47:42.627080 [Byte1]: 32
3302 16:47:42.627538
3303 16:47:42.630028 Set Vref, RX VrefLevel [Byte0]: 33
3304 16:47:42.633538 [Byte1]: 33
3305 16:47:42.636753
3306 16:47:42.637208 Set Vref, RX VrefLevel [Byte0]: 34
3307 16:47:42.640964 [Byte1]: 34
3308 16:47:42.645069
3309 16:47:42.645619 Set Vref, RX VrefLevel [Byte0]: 35
3310 16:47:42.648274 [Byte1]: 35
3311 16:47:42.652958
3312 16:47:42.653506 Set Vref, RX VrefLevel [Byte0]: 36
3313 16:47:42.656356 [Byte1]: 36
3314 16:47:42.660977
3315 16:47:42.661528 Set Vref, RX VrefLevel [Byte0]: 37
3316 16:47:42.663880 [Byte1]: 37
3317 16:47:42.668495
3318 16:47:42.668948 Set Vref, RX VrefLevel [Byte0]: 38
3319 16:47:42.672186 [Byte1]: 38
3320 16:47:42.676196
3321 16:47:42.676652 Set Vref, RX VrefLevel [Byte0]: 39
3322 16:47:42.679852 [Byte1]: 39
3323 16:47:42.684700
3324 16:47:42.685250 Set Vref, RX VrefLevel [Byte0]: 40
3325 16:47:42.687807 [Byte1]: 40
3326 16:47:42.692489
3327 16:47:42.693037 Set Vref, RX VrefLevel [Byte0]: 41
3328 16:47:42.695727 [Byte1]: 41
3329 16:47:42.700438
3330 16:47:42.700988 Set Vref, RX VrefLevel [Byte0]: 42
3331 16:47:42.703236 [Byte1]: 42
3332 16:47:42.708141
3333 16:47:42.708690 Set Vref, RX VrefLevel [Byte0]: 43
3334 16:47:42.711472 [Byte1]: 43
3335 16:47:42.716239
3336 16:47:42.716789 Set Vref, RX VrefLevel [Byte0]: 44
3337 16:47:42.719465 [Byte1]: 44
3338 16:47:42.723757
3339 16:47:42.724308 Set Vref, RX VrefLevel [Byte0]: 45
3340 16:47:42.726967 [Byte1]: 45
3341 16:47:42.731561
3342 16:47:42.732103 Set Vref, RX VrefLevel [Byte0]: 46
3343 16:47:42.735351 [Byte1]: 46
3344 16:47:42.739535
3345 16:47:42.739992 Set Vref, RX VrefLevel [Byte0]: 47
3346 16:47:42.743100 [Byte1]: 47
3347 16:47:42.747613
3348 16:47:42.748158 Set Vref, RX VrefLevel [Byte0]: 48
3349 16:47:42.751129 [Byte1]: 48
3350 16:47:42.755294
3351 16:47:42.755836 Set Vref, RX VrefLevel [Byte0]: 49
3352 16:47:42.758420 [Byte1]: 49
3353 16:47:42.763286
3354 16:47:42.763876 Set Vref, RX VrefLevel [Byte0]: 50
3355 16:47:42.766610 [Byte1]: 50
3356 16:47:42.770989
3357 16:47:42.771454 Set Vref, RX VrefLevel [Byte0]: 51
3358 16:47:42.774182 [Byte1]: 51
3359 16:47:42.779676
3360 16:47:42.780238 Set Vref, RX VrefLevel [Byte0]: 52
3361 16:47:42.782087 [Byte1]: 52
3362 16:47:42.787208
3363 16:47:42.787772 Set Vref, RX VrefLevel [Byte0]: 53
3364 16:47:42.790142 [Byte1]: 53
3365 16:47:42.794827
3366 16:47:42.795390 Set Vref, RX VrefLevel [Byte0]: 54
3367 16:47:42.798198 [Byte1]: 54
3368 16:47:42.803039
3369 16:47:42.803603 Set Vref, RX VrefLevel [Byte0]: 55
3370 16:47:42.806962 [Byte1]: 55
3371 16:47:42.810896
3372 16:47:42.811457 Set Vref, RX VrefLevel [Byte0]: 56
3373 16:47:42.813895 [Byte1]: 56
3374 16:47:42.819156
3375 16:47:42.819721 Set Vref, RX VrefLevel [Byte0]: 57
3376 16:47:42.821738 [Byte1]: 57
3377 16:47:42.826311
3378 16:47:42.826911 Set Vref, RX VrefLevel [Byte0]: 58
3379 16:47:42.829570 [Byte1]: 58
3380 16:47:42.834342
3381 16:47:42.834947 Set Vref, RX VrefLevel [Byte0]: 59
3382 16:47:42.837320 [Byte1]: 59
3383 16:47:42.841913
3384 16:47:42.842422 Set Vref, RX VrefLevel [Byte0]: 60
3385 16:47:42.845310 [Byte1]: 60
3386 16:47:42.850026
3387 16:47:42.850627 Set Vref, RX VrefLevel [Byte0]: 61
3388 16:47:42.853405 [Byte1]: 61
3389 16:47:42.858062
3390 16:47:42.858665 Set Vref, RX VrefLevel [Byte0]: 62
3391 16:47:42.861491 [Byte1]: 62
3392 16:47:42.865947
3393 16:47:42.866552 Set Vref, RX VrefLevel [Byte0]: 63
3394 16:47:42.869574 [Byte1]: 63
3395 16:47:42.873911
3396 16:47:42.874517 Set Vref, RX VrefLevel [Byte0]: 64
3397 16:47:42.877083 [Byte1]: 64
3398 16:47:42.881801
3399 16:47:42.882415 Set Vref, RX VrefLevel [Byte0]: 65
3400 16:47:42.885102 [Byte1]: 65
3401 16:47:42.890079
3402 16:47:42.890687 Set Vref, RX VrefLevel [Byte0]: 66
3403 16:47:42.893173 [Byte1]: 66
3404 16:47:42.897690
3405 16:47:42.898254 Set Vref, RX VrefLevel [Byte0]: 67
3406 16:47:42.900736 [Byte1]: 67
3407 16:47:42.905880
3408 16:47:42.906486 Final RX Vref Byte 0 = 54 to rank0
3409 16:47:42.908489 Final RX Vref Byte 1 = 57 to rank0
3410 16:47:42.912134 Final RX Vref Byte 0 = 54 to rank1
3411 16:47:42.915229 Final RX Vref Byte 1 = 57 to rank1==
3412 16:47:42.918480 Dram Type= 6, Freq= 0, CH_1, rank 0
3413 16:47:42.925575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 16:47:42.926147 ==
3415 16:47:42.926599 DQS Delay:
3416 16:47:42.926958 DQS0 = 0, DQS1 = 0
3417 16:47:42.928791 DQM Delay:
3418 16:47:42.929355 DQM0 = 119, DQM1 = 113
3419 16:47:42.931804 DQ Delay:
3420 16:47:42.934925 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3421 16:47:42.938990 DQ4 =118, DQ5 =126, DQ6 =128, DQ7 =118
3422 16:47:42.941828 DQ8 =102, DQ9 =100, DQ10 =116, DQ11 =106
3423 16:47:42.945137 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =120
3424 16:47:42.945609
3425 16:47:42.945980
3426 16:47:42.954802 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3427 16:47:42.955362 CH1 RK0: MR19=404, MR18=114
3428 16:47:42.961463 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3429 16:47:42.962030
3430 16:47:42.964878 ----->DramcWriteLeveling(PI) begin...
3431 16:47:42.965351 ==
3432 16:47:42.968100 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 16:47:42.971961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 16:47:42.974925 ==
3435 16:47:42.978490 Write leveling (Byte 0): 26 => 26
3436 16:47:42.979047 Write leveling (Byte 1): 30 => 30
3437 16:47:42.982002 DramcWriteLeveling(PI) end<-----
3438 16:47:42.982612
3439 16:47:42.983001 ==
3440 16:47:42.984830 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 16:47:42.991667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 16:47:42.992237 ==
3443 16:47:42.995080 [Gating] SW mode calibration
3444 16:47:43.001620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3445 16:47:43.005449 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3446 16:47:43.011204 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 16:47:43.015267 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 16:47:43.018098 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 16:47:43.024980 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 16:47:43.027932 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 16:47:43.031256 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 16:47:43.037838 0 15 24 | B1->B0 | 2626 3434 | 0 0 | (0 1) (0 1)
3453 16:47:43.041315 0 15 28 | B1->B0 | 2323 2a2a | 0 1 | (1 0) (1 0)
3454 16:47:43.044309 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 16:47:43.051055 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 16:47:43.054797 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 16:47:43.057962 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 16:47:43.060931 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 16:47:43.067903 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3460 16:47:43.071239 1 0 24 | B1->B0 | 3d3d 2f2f | 1 0 | (0 0) (0 0)
3461 16:47:43.074801 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3462 16:47:43.081225 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 16:47:43.084638 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 16:47:43.087635 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 16:47:43.094698 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 16:47:43.097893 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 16:47:43.100903 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 16:47:43.107076 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3469 16:47:43.110711 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 16:47:43.114048 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 16:47:43.120629 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 16:47:43.124296 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 16:47:43.127249 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 16:47:43.134049 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 16:47:43.137762 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 16:47:43.140412 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 16:47:43.146955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 16:47:43.150523 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 16:47:43.153761 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 16:47:43.160597 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 16:47:43.163733 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 16:47:43.166771 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 16:47:43.173566 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3484 16:47:43.176936 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3485 16:47:43.180067 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3486 16:47:43.186874 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 16:47:43.187443 Total UI for P1: 0, mck2ui 16
3488 16:47:43.194127 best dqsien dly found for B0: ( 1, 3, 24)
3489 16:47:43.194739 Total UI for P1: 0, mck2ui 16
3490 16:47:43.199961 best dqsien dly found for B1: ( 1, 3, 26)
3491 16:47:43.203812 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3492 16:47:43.206688 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3493 16:47:43.207253
3494 16:47:43.210162 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3495 16:47:43.213598 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3496 16:47:43.216628 [Gating] SW calibration Done
3497 16:47:43.217191 ==
3498 16:47:43.219878 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 16:47:43.223438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 16:47:43.224000 ==
3501 16:47:43.226745 RX Vref Scan: 0
3502 16:47:43.227309
3503 16:47:43.227684 RX Vref 0 -> 0, step: 1
3504 16:47:43.228033
3505 16:47:43.229956 RX Delay -40 -> 252, step: 8
3506 16:47:43.236347 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3507 16:47:43.239780 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3508 16:47:43.243041 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3509 16:47:43.246320 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3510 16:47:43.249931 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3511 16:47:43.256417 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3512 16:47:43.259843 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3513 16:47:43.262600 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3514 16:47:43.266253 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3515 16:47:43.269263 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3516 16:47:43.276107 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3517 16:47:43.279596 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3518 16:47:43.282392 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3519 16:47:43.285826 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3520 16:47:43.289556 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3521 16:47:43.295677 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3522 16:47:43.296149 ==
3523 16:47:43.299234 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 16:47:43.302689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 16:47:43.303257 ==
3526 16:47:43.303636 DQS Delay:
3527 16:47:43.306122 DQS0 = 0, DQS1 = 0
3528 16:47:43.306735 DQM Delay:
3529 16:47:43.309852 DQM0 = 121, DQM1 = 112
3530 16:47:43.310450 DQ Delay:
3531 16:47:43.312780 DQ0 =127, DQ1 =115, DQ2 =111, DQ3 =123
3532 16:47:43.315762 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3533 16:47:43.319251 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3534 16:47:43.322466 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3535 16:47:43.323037
3536 16:47:43.323412
3537 16:47:43.325996 ==
3538 16:47:43.328875 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 16:47:43.332580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 16:47:43.333156 ==
3541 16:47:43.333538
3542 16:47:43.333884
3543 16:47:43.335365 TX Vref Scan disable
3544 16:47:43.335830 == TX Byte 0 ==
3545 16:47:43.338796 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3546 16:47:43.345552 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3547 16:47:43.346124 == TX Byte 1 ==
3548 16:47:43.351810 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3549 16:47:43.355387 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3550 16:47:43.355954 ==
3551 16:47:43.358566 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 16:47:43.362070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 16:47:43.362689 ==
3554 16:47:43.375117 TX Vref=22, minBit 1, minWin=25, winSum=419
3555 16:47:43.377687 TX Vref=24, minBit 3, minWin=25, winSum=423
3556 16:47:43.380613 TX Vref=26, minBit 1, minWin=26, winSum=427
3557 16:47:43.384746 TX Vref=28, minBit 9, minWin=25, winSum=429
3558 16:47:43.387475 TX Vref=30, minBit 9, minWin=26, winSum=435
3559 16:47:43.394127 TX Vref=32, minBit 1, minWin=26, winSum=428
3560 16:47:43.397933 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3561 16:47:43.398458
3562 16:47:43.400800 Final TX Range 1 Vref 30
3563 16:47:43.401370
3564 16:47:43.401746 ==
3565 16:47:43.404143 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 16:47:43.407284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 16:47:43.407853 ==
3568 16:47:43.410995
3569 16:47:43.411559
3570 16:47:43.411929 TX Vref Scan disable
3571 16:47:43.413948 == TX Byte 0 ==
3572 16:47:43.417274 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3573 16:47:43.424216 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3574 16:47:43.424784 == TX Byte 1 ==
3575 16:47:43.427067 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3576 16:47:43.433861 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3577 16:47:43.434462
3578 16:47:43.434840 [DATLAT]
3579 16:47:43.435192 Freq=1200, CH1 RK1
3580 16:47:43.435529
3581 16:47:43.436818 DATLAT Default: 0xd
3582 16:47:43.440679 0, 0xFFFF, sum = 0
3583 16:47:43.441250 1, 0xFFFF, sum = 0
3584 16:47:43.443725 2, 0xFFFF, sum = 0
3585 16:47:43.444203 3, 0xFFFF, sum = 0
3586 16:47:43.447995 4, 0xFFFF, sum = 0
3587 16:47:43.448569 5, 0xFFFF, sum = 0
3588 16:47:43.450659 6, 0xFFFF, sum = 0
3589 16:47:43.451135 7, 0xFFFF, sum = 0
3590 16:47:43.454150 8, 0xFFFF, sum = 0
3591 16:47:43.454767 9, 0xFFFF, sum = 0
3592 16:47:43.457174 10, 0xFFFF, sum = 0
3593 16:47:43.457750 11, 0xFFFF, sum = 0
3594 16:47:43.460431 12, 0x0, sum = 1
3595 16:47:43.461003 13, 0x0, sum = 2
3596 16:47:43.463899 14, 0x0, sum = 3
3597 16:47:43.464474 15, 0x0, sum = 4
3598 16:47:43.466813 best_step = 13
3599 16:47:43.467281
3600 16:47:43.467653 ==
3601 16:47:43.470040 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 16:47:43.473765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 16:47:43.474238 ==
3604 16:47:43.476620 RX Vref Scan: 0
3605 16:47:43.477183
3606 16:47:43.477559 RX Vref 0 -> 0, step: 1
3607 16:47:43.477909
3608 16:47:43.479763 RX Delay -13 -> 252, step: 4
3609 16:47:43.486862 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3610 16:47:43.489876 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3611 16:47:43.493461 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3612 16:47:43.496404 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3613 16:47:43.500602 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3614 16:47:43.507368 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3615 16:47:43.509788 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3616 16:47:43.513293 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3617 16:47:43.516042 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3618 16:47:43.519948 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3619 16:47:43.526482 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3620 16:47:43.529823 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3621 16:47:43.532910 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3622 16:47:43.536401 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3623 16:47:43.542554 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3624 16:47:43.546081 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3625 16:47:43.546582 ==
3626 16:47:43.549295 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 16:47:43.552475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 16:47:43.552951 ==
3629 16:47:43.553428 DQS Delay:
3630 16:47:43.556167 DQS0 = 0, DQS1 = 0
3631 16:47:43.556734 DQM Delay:
3632 16:47:43.559248 DQM0 = 119, DQM1 = 113
3633 16:47:43.559810 DQ Delay:
3634 16:47:43.562637 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3635 16:47:43.566394 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3636 16:47:43.569651 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3637 16:47:43.575783 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3638 16:47:43.576398
3639 16:47:43.576779
3640 16:47:43.582659 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3641 16:47:43.585740 CH1 RK1: MR19=403, MR18=8ED
3642 16:47:43.592338 CH1_RK1: MR19=0x403, MR18=0x8ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3643 16:47:43.595390 [RxdqsGatingPostProcess] freq 1200
3644 16:47:43.598719 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3645 16:47:43.603412 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 16:47:43.605238 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 16:47:43.608992 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 16:47:43.612521 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 16:47:43.615245 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 16:47:43.618607 best DQS1 dly(2T, 0.5T) = (0, 11)
3651 16:47:43.622175 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 16:47:43.625255 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3653 16:47:43.628676 Pre-setting of DQS Precalculation
3654 16:47:43.631886 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3655 16:47:43.642088 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3656 16:47:43.648554 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3657 16:47:43.649124
3658 16:47:43.649499
3659 16:47:43.652064 [Calibration Summary] 2400 Mbps
3660 16:47:43.652640 CH 0, Rank 0
3661 16:47:43.654790 SW Impedance : PASS
3662 16:47:43.655261 DUTY Scan : NO K
3663 16:47:43.658387 ZQ Calibration : PASS
3664 16:47:43.661891 Jitter Meter : NO K
3665 16:47:43.662491 CBT Training : PASS
3666 16:47:43.664886 Write leveling : PASS
3667 16:47:43.668475 RX DQS gating : PASS
3668 16:47:43.669039 RX DQ/DQS(RDDQC) : PASS
3669 16:47:43.671348 TX DQ/DQS : PASS
3670 16:47:43.674632 RX DATLAT : PASS
3671 16:47:43.675097 RX DQ/DQS(Engine): PASS
3672 16:47:43.678701 TX OE : NO K
3673 16:47:43.679271 All Pass.
3674 16:47:43.679648
3675 16:47:43.681056 CH 0, Rank 1
3676 16:47:43.681561 SW Impedance : PASS
3677 16:47:43.684326 DUTY Scan : NO K
3678 16:47:43.688105 ZQ Calibration : PASS
3679 16:47:43.688675 Jitter Meter : NO K
3680 16:47:43.691012 CBT Training : PASS
3681 16:47:43.694460 Write leveling : PASS
3682 16:47:43.694929 RX DQS gating : PASS
3683 16:47:43.698158 RX DQ/DQS(RDDQC) : PASS
3684 16:47:43.698771 TX DQ/DQS : PASS
3685 16:47:43.701441 RX DATLAT : PASS
3686 16:47:43.704506 RX DQ/DQS(Engine): PASS
3687 16:47:43.705072 TX OE : NO K
3688 16:47:43.707805 All Pass.
3689 16:47:43.708369
3690 16:47:43.708743 CH 1, Rank 0
3691 16:47:43.710829 SW Impedance : PASS
3692 16:47:43.711299 DUTY Scan : NO K
3693 16:47:43.714281 ZQ Calibration : PASS
3694 16:47:43.717844 Jitter Meter : NO K
3695 16:47:43.718455 CBT Training : PASS
3696 16:47:43.720985 Write leveling : PASS
3697 16:47:43.724849 RX DQS gating : PASS
3698 16:47:43.725418 RX DQ/DQS(RDDQC) : PASS
3699 16:47:43.727704 TX DQ/DQS : PASS
3700 16:47:43.730992 RX DATLAT : PASS
3701 16:47:43.731566 RX DQ/DQS(Engine): PASS
3702 16:47:43.734590 TX OE : NO K
3703 16:47:43.735158 All Pass.
3704 16:47:43.735536
3705 16:47:43.737680 CH 1, Rank 1
3706 16:47:43.738240 SW Impedance : PASS
3707 16:47:43.740891 DUTY Scan : NO K
3708 16:47:43.745298 ZQ Calibration : PASS
3709 16:47:43.745862 Jitter Meter : NO K
3710 16:47:43.747354 CBT Training : PASS
3711 16:47:43.750905 Write leveling : PASS
3712 16:47:43.751474 RX DQS gating : PASS
3713 16:47:43.754424 RX DQ/DQS(RDDQC) : PASS
3714 16:47:43.757157 TX DQ/DQS : PASS
3715 16:47:43.757723 RX DATLAT : PASS
3716 16:47:43.760790 RX DQ/DQS(Engine): PASS
3717 16:47:43.763839 TX OE : NO K
3718 16:47:43.764406 All Pass.
3719 16:47:43.764785
3720 16:47:43.765133 DramC Write-DBI off
3721 16:47:43.766787 PER_BANK_REFRESH: Hybrid Mode
3722 16:47:43.770564 TX_TRACKING: ON
3723 16:47:43.776972 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3724 16:47:43.780455 [FAST_K] Save calibration result to emmc
3725 16:47:43.786859 dramc_set_vcore_voltage set vcore to 650000
3726 16:47:43.787428 Read voltage for 600, 5
3727 16:47:43.790115 Vio18 = 0
3728 16:47:43.790620 Vcore = 650000
3729 16:47:43.790996 Vdram = 0
3730 16:47:43.793371 Vddq = 0
3731 16:47:43.793839 Vmddr = 0
3732 16:47:43.796452 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3733 16:47:43.803675 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3734 16:47:43.806907 MEM_TYPE=3, freq_sel=19
3735 16:47:43.809897 sv_algorithm_assistance_LP4_1600
3736 16:47:43.813822 ============ PULL DRAM RESETB DOWN ============
3737 16:47:43.816847 ========== PULL DRAM RESETB DOWN end =========
3738 16:47:43.823291 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3739 16:47:43.826191 ===================================
3740 16:47:43.826697 LPDDR4 DRAM CONFIGURATION
3741 16:47:43.829713 ===================================
3742 16:47:43.833114 EX_ROW_EN[0] = 0x0
3743 16:47:43.833684 EX_ROW_EN[1] = 0x0
3744 16:47:43.836305 LP4Y_EN = 0x0
3745 16:47:43.836873 WORK_FSP = 0x0
3746 16:47:43.839452 WL = 0x2
3747 16:47:43.843047 RL = 0x2
3748 16:47:43.843524 BL = 0x2
3749 16:47:43.846487 RPST = 0x0
3750 16:47:43.847111 RD_PRE = 0x0
3751 16:47:43.849273 WR_PRE = 0x1
3752 16:47:43.849747 WR_PST = 0x0
3753 16:47:43.853021 DBI_WR = 0x0
3754 16:47:43.853634 DBI_RD = 0x0
3755 16:47:43.856399 OTF = 0x1
3756 16:47:43.859833 ===================================
3757 16:47:43.863141 ===================================
3758 16:47:43.863740 ANA top config
3759 16:47:43.866112 ===================================
3760 16:47:43.869482 DLL_ASYNC_EN = 0
3761 16:47:43.872645 ALL_SLAVE_EN = 1
3762 16:47:43.873242 NEW_RANK_MODE = 1
3763 16:47:43.876255 DLL_IDLE_MODE = 1
3764 16:47:43.879094 LP45_APHY_COMB_EN = 1
3765 16:47:43.882512 TX_ODT_DIS = 1
3766 16:47:43.885952 NEW_8X_MODE = 1
3767 16:47:43.889167 ===================================
3768 16:47:43.892210 ===================================
3769 16:47:43.892682 data_rate = 1200
3770 16:47:43.896701 CKR = 1
3771 16:47:43.898933 DQ_P2S_RATIO = 8
3772 16:47:43.902458 ===================================
3773 16:47:43.905650 CA_P2S_RATIO = 8
3774 16:47:43.909524 DQ_CA_OPEN = 0
3775 16:47:43.912669 DQ_SEMI_OPEN = 0
3776 16:47:43.913239 CA_SEMI_OPEN = 0
3777 16:47:43.916167 CA_FULL_RATE = 0
3778 16:47:43.918867 DQ_CKDIV4_EN = 1
3779 16:47:43.922250 CA_CKDIV4_EN = 1
3780 16:47:43.926091 CA_PREDIV_EN = 0
3781 16:47:43.929037 PH8_DLY = 0
3782 16:47:43.929604 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3783 16:47:43.932320 DQ_AAMCK_DIV = 4
3784 16:47:43.935253 CA_AAMCK_DIV = 4
3785 16:47:43.938718 CA_ADMCK_DIV = 4
3786 16:47:43.942133 DQ_TRACK_CA_EN = 0
3787 16:47:43.944983 CA_PICK = 600
3788 16:47:43.949052 CA_MCKIO = 600
3789 16:47:43.949658 MCKIO_SEMI = 0
3790 16:47:43.952337 PLL_FREQ = 2288
3791 16:47:43.954907 DQ_UI_PI_RATIO = 32
3792 16:47:43.958659 CA_UI_PI_RATIO = 0
3793 16:47:43.961638 ===================================
3794 16:47:43.965452 ===================================
3795 16:47:43.968987 memory_type:LPDDR4
3796 16:47:43.969565 GP_NUM : 10
3797 16:47:43.971707 SRAM_EN : 1
3798 16:47:43.974831 MD32_EN : 0
3799 16:47:43.978112 ===================================
3800 16:47:43.978746 [ANA_INIT] >>>>>>>>>>>>>>
3801 16:47:43.982213 <<<<<< [CONFIGURE PHASE]: ANA_TX
3802 16:47:43.985530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3803 16:47:43.987992 ===================================
3804 16:47:43.991243 data_rate = 1200,PCW = 0X5800
3805 16:47:43.994888 ===================================
3806 16:47:43.997601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3807 16:47:44.004632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 16:47:44.007363 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 16:47:44.014473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3810 16:47:44.018317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3811 16:47:44.021422 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3812 16:47:44.024034 [ANA_INIT] flow start
3813 16:47:44.024552 [ANA_INIT] PLL >>>>>>>>
3814 16:47:44.027272 [ANA_INIT] PLL <<<<<<<<
3815 16:47:44.030860 [ANA_INIT] MIDPI >>>>>>>>
3816 16:47:44.031326 [ANA_INIT] MIDPI <<<<<<<<
3817 16:47:44.034010 [ANA_INIT] DLL >>>>>>>>
3818 16:47:44.037260 [ANA_INIT] flow end
3819 16:47:44.040615 ============ LP4 DIFF to SE enter ============
3820 16:47:44.044388 ============ LP4 DIFF to SE exit ============
3821 16:47:44.047533 [ANA_INIT] <<<<<<<<<<<<<
3822 16:47:44.050592 [Flow] Enable top DCM control >>>>>
3823 16:47:44.053600 [Flow] Enable top DCM control <<<<<
3824 16:47:44.057047 Enable DLL master slave shuffle
3825 16:47:44.060955 ==============================================================
3826 16:47:44.063744 Gating Mode config
3827 16:47:44.070624 ==============================================================
3828 16:47:44.070959 Config description:
3829 16:47:44.080117 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3830 16:47:44.086822 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3831 16:47:44.093119 SELPH_MODE 0: By rank 1: By Phase
3832 16:47:44.096645 ==============================================================
3833 16:47:44.099725 GAT_TRACK_EN = 1
3834 16:47:44.103180 RX_GATING_MODE = 2
3835 16:47:44.106469 RX_GATING_TRACK_MODE = 2
3836 16:47:44.109898 SELPH_MODE = 1
3837 16:47:44.113114 PICG_EARLY_EN = 1
3838 16:47:44.116605 VALID_LAT_VALUE = 1
3839 16:47:44.119910 ==============================================================
3840 16:47:44.123221 Enter into Gating configuration >>>>
3841 16:47:44.125999 Exit from Gating configuration <<<<
3842 16:47:44.129372 Enter into DVFS_PRE_config >>>>>
3843 16:47:44.143237 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3844 16:47:44.146655 Exit from DVFS_PRE_config <<<<<
3845 16:47:44.149357 Enter into PICG configuration >>>>
3846 16:47:44.153080 Exit from PICG configuration <<<<
3847 16:47:44.153414 [RX_INPUT] configuration >>>>>
3848 16:47:44.155888 [RX_INPUT] configuration <<<<<
3849 16:47:44.162510 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3850 16:47:44.166177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3851 16:47:44.172132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 16:47:44.178640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 16:47:44.185737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3854 16:47:44.192600 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3855 16:47:44.195340 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3856 16:47:44.198704 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3857 16:47:44.205565 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3858 16:47:44.208864 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3859 16:47:44.211868 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3860 16:47:44.219412 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3861 16:47:44.222724 ===================================
3862 16:47:44.222961 LPDDR4 DRAM CONFIGURATION
3863 16:47:44.225210 ===================================
3864 16:47:44.228149 EX_ROW_EN[0] = 0x0
3865 16:47:44.228432 EX_ROW_EN[1] = 0x0
3866 16:47:44.231693 LP4Y_EN = 0x0
3867 16:47:44.234850 WORK_FSP = 0x0
3868 16:47:44.235131 WL = 0x2
3869 16:47:44.238146 RL = 0x2
3870 16:47:44.238489 BL = 0x2
3871 16:47:44.241533 RPST = 0x0
3872 16:47:44.241915 RD_PRE = 0x0
3873 16:47:44.245046 WR_PRE = 0x1
3874 16:47:44.245345 WR_PST = 0x0
3875 16:47:44.247901 DBI_WR = 0x0
3876 16:47:44.248265 DBI_RD = 0x0
3877 16:47:44.252358 OTF = 0x1
3878 16:47:44.254783 ===================================
3879 16:47:44.258249 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3880 16:47:44.261584 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3881 16:47:44.268139 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 16:47:44.271282 ===================================
3883 16:47:44.271873 LPDDR4 DRAM CONFIGURATION
3884 16:47:44.275103 ===================================
3885 16:47:44.277912 EX_ROW_EN[0] = 0x10
3886 16:47:44.281536 EX_ROW_EN[1] = 0x0
3887 16:47:44.282122 LP4Y_EN = 0x0
3888 16:47:44.284620 WORK_FSP = 0x0
3889 16:47:44.285199 WL = 0x2
3890 16:47:44.287910 RL = 0x2
3891 16:47:44.288493 BL = 0x2
3892 16:47:44.291113 RPST = 0x0
3893 16:47:44.291690 RD_PRE = 0x0
3894 16:47:44.294647 WR_PRE = 0x1
3895 16:47:44.295123 WR_PST = 0x0
3896 16:47:44.298210 DBI_WR = 0x0
3897 16:47:44.298831 DBI_RD = 0x0
3898 16:47:44.300944 OTF = 0x1
3899 16:47:44.304544 ===================================
3900 16:47:44.311274 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3901 16:47:44.315019 nWR fixed to 30
3902 16:47:44.317433 [ModeRegInit_LP4] CH0 RK0
3903 16:47:44.318008 [ModeRegInit_LP4] CH0 RK1
3904 16:47:44.320948 [ModeRegInit_LP4] CH1 RK0
3905 16:47:44.324434 [ModeRegInit_LP4] CH1 RK1
3906 16:47:44.325010 match AC timing 17
3907 16:47:44.331112 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3908 16:47:44.333838 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3909 16:47:44.337168 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3910 16:47:44.343946 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3911 16:47:44.346925 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3912 16:47:44.347396 ==
3913 16:47:44.350757 Dram Type= 6, Freq= 0, CH_0, rank 0
3914 16:47:44.353252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3915 16:47:44.353819 ==
3916 16:47:44.360055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3917 16:47:44.366722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3918 16:47:44.369931 [CA 0] Center 36 (6~67) winsize 62
3919 16:47:44.373673 [CA 1] Center 36 (6~67) winsize 62
3920 16:47:44.376401 [CA 2] Center 34 (4~65) winsize 62
3921 16:47:44.380204 [CA 3] Center 34 (3~65) winsize 63
3922 16:47:44.383037 [CA 4] Center 33 (3~64) winsize 62
3923 16:47:44.386624 [CA 5] Center 33 (2~64) winsize 63
3924 16:47:44.387197
3925 16:47:44.389914 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3926 16:47:44.390526
3927 16:47:44.393271 [CATrainingPosCal] consider 1 rank data
3928 16:47:44.396478 u2DelayCellTimex100 = 270/100 ps
3929 16:47:44.399924 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3930 16:47:44.403263 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3931 16:47:44.406131 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3932 16:47:44.413238 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3933 16:47:44.416114 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3934 16:47:44.419633 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3935 16:47:44.420201
3936 16:47:44.422564 CA PerBit enable=1, Macro0, CA PI delay=33
3937 16:47:44.423033
3938 16:47:44.426266 [CBTSetCACLKResult] CA Dly = 33
3939 16:47:44.426930 CS Dly: 5 (0~36)
3940 16:47:44.427310 ==
3941 16:47:44.428922 Dram Type= 6, Freq= 0, CH_0, rank 1
3942 16:47:44.435810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 16:47:44.436376 ==
3944 16:47:44.439488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 16:47:44.445521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3946 16:47:44.449082 [CA 0] Center 36 (6~67) winsize 62
3947 16:47:44.452183 [CA 1] Center 36 (6~67) winsize 62
3948 16:47:44.455555 [CA 2] Center 35 (4~66) winsize 63
3949 16:47:44.459179 [CA 3] Center 35 (4~66) winsize 63
3950 16:47:44.462916 [CA 4] Center 34 (3~65) winsize 63
3951 16:47:44.465880 [CA 5] Center 33 (3~64) winsize 62
3952 16:47:44.466492
3953 16:47:44.468943 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3954 16:47:44.469406
3955 16:47:44.472692 [CATrainingPosCal] consider 2 rank data
3956 16:47:44.475382 u2DelayCellTimex100 = 270/100 ps
3957 16:47:44.478978 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3958 16:47:44.485478 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3959 16:47:44.489188 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 16:47:44.492031 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 16:47:44.495015 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 16:47:44.499036 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 16:47:44.499602
3964 16:47:44.502095 CA PerBit enable=1, Macro0, CA PI delay=33
3965 16:47:44.502719
3966 16:47:44.505355 [CBTSetCACLKResult] CA Dly = 33
3967 16:47:44.508393 CS Dly: 5 (0~37)
3968 16:47:44.508953
3969 16:47:44.511848 ----->DramcWriteLeveling(PI) begin...
3970 16:47:44.512418 ==
3971 16:47:44.515002 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 16:47:44.518487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 16:47:44.519060 ==
3974 16:47:44.521530 Write leveling (Byte 0): 35 => 35
3975 16:47:44.525284 Write leveling (Byte 1): 31 => 31
3976 16:47:44.528766 DramcWriteLeveling(PI) end<-----
3977 16:47:44.529333
3978 16:47:44.529705 ==
3979 16:47:44.531430 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 16:47:44.534741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 16:47:44.535356 ==
3982 16:47:44.538479 [Gating] SW mode calibration
3983 16:47:44.544584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3984 16:47:44.551378 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3985 16:47:44.554819 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 16:47:44.558419 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 16:47:44.564642 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 16:47:44.567965 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
3989 16:47:44.571447 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
3990 16:47:44.577943 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 16:47:44.581220 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 16:47:44.584588 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 16:47:44.591225 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 16:47:44.594763 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 16:47:44.597819 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3996 16:47:44.604509 0 10 12 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
3997 16:47:44.607882 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3998 16:47:44.611461 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 16:47:44.618047 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 16:47:44.621122 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 16:47:44.624232 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 16:47:44.630958 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 16:47:44.634423 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 16:47:44.637979 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4005 16:47:44.644515 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4006 16:47:44.647814 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 16:47:44.650493 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 16:47:44.657371 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 16:47:44.660740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 16:47:44.663947 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 16:47:44.670526 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 16:47:44.674291 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 16:47:44.677018 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 16:47:44.683784 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 16:47:44.687086 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 16:47:44.690428 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 16:47:44.697028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 16:47:44.700832 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 16:47:44.703725 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 16:47:44.710296 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4021 16:47:44.713514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4022 16:47:44.716986 Total UI for P1: 0, mck2ui 16
4023 16:47:44.719922 best dqsien dly found for B0: ( 0, 13, 12)
4024 16:47:44.723642 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 16:47:44.726833 Total UI for P1: 0, mck2ui 16
4026 16:47:44.731220 best dqsien dly found for B1: ( 0, 13, 18)
4027 16:47:44.733336 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4028 16:47:44.736802 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4029 16:47:44.737379
4030 16:47:44.743382 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4031 16:47:44.746659 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4032 16:47:44.747241 [Gating] SW calibration Done
4033 16:47:44.750192 ==
4034 16:47:44.753281 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 16:47:44.756361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 16:47:44.756839 ==
4037 16:47:44.757213 RX Vref Scan: 0
4038 16:47:44.757562
4039 16:47:44.759906 RX Vref 0 -> 0, step: 1
4040 16:47:44.760480
4041 16:47:44.763454 RX Delay -230 -> 252, step: 16
4042 16:47:44.766065 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4043 16:47:44.769657 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4044 16:47:44.776882 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4045 16:47:44.779536 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4046 16:47:44.783128 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4047 16:47:44.785818 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4048 16:47:44.792817 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4049 16:47:44.795839 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4050 16:47:44.799468 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4051 16:47:44.802730 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4052 16:47:44.809275 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4053 16:47:44.812424 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4054 16:47:44.815776 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4055 16:47:44.819205 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4056 16:47:44.826733 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4057 16:47:44.828590 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4058 16:47:44.829063 ==
4059 16:47:44.832322 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 16:47:44.835619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 16:47:44.836198 ==
4062 16:47:44.839233 DQS Delay:
4063 16:47:44.839804 DQS0 = 0, DQS1 = 0
4064 16:47:44.840184 DQM Delay:
4065 16:47:44.842241 DQM0 = 53, DQM1 = 43
4066 16:47:44.842740 DQ Delay:
4067 16:47:44.845912 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4068 16:47:44.849193 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4069 16:47:44.852428 DQ8 =25, DQ9 =25, DQ10 =49, DQ11 =41
4070 16:47:44.855437 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4071 16:47:44.855921
4072 16:47:44.856298
4073 16:47:44.856643 ==
4074 16:47:44.859059 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 16:47:44.865446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 16:47:44.866027 ==
4077 16:47:44.866437
4078 16:47:44.866793
4079 16:47:44.867128 TX Vref Scan disable
4080 16:47:44.869003 == TX Byte 0 ==
4081 16:47:44.871940 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4082 16:47:44.878716 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4083 16:47:44.879549 == TX Byte 1 ==
4084 16:47:44.882251 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4085 16:47:44.888787 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4086 16:47:44.889355 ==
4087 16:47:44.892089 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 16:47:44.895039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 16:47:44.895521 ==
4090 16:47:44.895895
4091 16:47:44.896245
4092 16:47:44.898628 TX Vref Scan disable
4093 16:47:44.901612 == TX Byte 0 ==
4094 16:47:44.905380 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4095 16:47:44.908654 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4096 16:47:44.911731 == TX Byte 1 ==
4097 16:47:44.915178 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4098 16:47:44.918545 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4099 16:47:44.919116
4100 16:47:44.919491 [DATLAT]
4101 16:47:44.921715 Freq=600, CH0 RK0
4102 16:47:44.922283
4103 16:47:44.925079 DATLAT Default: 0x9
4104 16:47:44.925648 0, 0xFFFF, sum = 0
4105 16:47:44.928246 1, 0xFFFF, sum = 0
4106 16:47:44.928825 2, 0xFFFF, sum = 0
4107 16:47:44.931779 3, 0xFFFF, sum = 0
4108 16:47:44.932357 4, 0xFFFF, sum = 0
4109 16:47:44.935522 5, 0xFFFF, sum = 0
4110 16:47:44.936098 6, 0xFFFF, sum = 0
4111 16:47:44.938447 7, 0xFFFF, sum = 0
4112 16:47:44.939026 8, 0x0, sum = 1
4113 16:47:44.941984 9, 0x0, sum = 2
4114 16:47:44.942607 10, 0x0, sum = 3
4115 16:47:44.944665 11, 0x0, sum = 4
4116 16:47:44.945197 best_step = 9
4117 16:47:44.945571
4118 16:47:44.945914 ==
4119 16:47:44.947862 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 16:47:44.951472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 16:47:44.952050 ==
4122 16:47:44.954925 RX Vref Scan: 1
4123 16:47:44.955497
4124 16:47:44.958115 RX Vref 0 -> 0, step: 1
4125 16:47:44.958728
4126 16:47:44.959108 RX Delay -179 -> 252, step: 8
4127 16:47:44.961198
4128 16:47:44.961760 Set Vref, RX VrefLevel [Byte0]: 63
4129 16:47:44.964587 [Byte1]: 50
4130 16:47:44.969395
4131 16:47:44.970038 Final RX Vref Byte 0 = 63 to rank0
4132 16:47:44.972797 Final RX Vref Byte 1 = 50 to rank0
4133 16:47:44.975701 Final RX Vref Byte 0 = 63 to rank1
4134 16:47:44.979439 Final RX Vref Byte 1 = 50 to rank1==
4135 16:47:44.982329 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 16:47:44.989855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 16:47:44.990478 ==
4138 16:47:44.990865 DQS Delay:
4139 16:47:44.992257 DQS0 = 0, DQS1 = 0
4140 16:47:44.992728 DQM Delay:
4141 16:47:44.993103 DQM0 = 47, DQM1 = 39
4142 16:47:44.995743 DQ Delay:
4143 16:47:44.998880 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4144 16:47:45.002464 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4145 16:47:45.005876 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =32
4146 16:47:45.009716 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4147 16:47:45.010297
4148 16:47:45.010718
4149 16:47:45.015629 [DQSOSCAuto] RK0, (LSB)MR18= 0x554e, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 393 ps
4150 16:47:45.019060 CH0 RK0: MR19=808, MR18=554E
4151 16:47:45.025494 CH0_RK0: MR19=0x808, MR18=0x554E, DQSOSC=393, MR23=63, INC=169, DEC=113
4152 16:47:45.026073
4153 16:47:45.028889 ----->DramcWriteLeveling(PI) begin...
4154 16:47:45.029472 ==
4155 16:47:45.033090 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 16:47:45.035873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 16:47:45.036456 ==
4158 16:47:45.039102 Write leveling (Byte 0): 31 => 31
4159 16:47:45.042319 Write leveling (Byte 1): 30 => 30
4160 16:47:45.045221 DramcWriteLeveling(PI) end<-----
4161 16:47:45.045696
4162 16:47:45.046069 ==
4163 16:47:45.048268 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 16:47:45.051902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 16:47:45.055247 ==
4166 16:47:45.055823 [Gating] SW mode calibration
4167 16:47:45.065298 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4168 16:47:45.068082 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4169 16:47:45.071115 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 16:47:45.077861 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 16:47:45.081103 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 16:47:45.084671 0 9 12 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 1)
4173 16:47:45.091284 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4174 16:47:45.094769 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 16:47:45.097929 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 16:47:45.105052 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 16:47:45.108166 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 16:47:45.111340 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 16:47:45.118280 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4180 16:47:45.121622 0 10 12 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (0 0)
4181 16:47:45.124635 0 10 16 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
4182 16:47:45.131550 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 16:47:45.134601 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 16:47:45.137739 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 16:47:45.144060 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 16:47:45.147540 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 16:47:45.150803 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 16:47:45.157391 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 16:47:45.161091 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 16:47:45.164153 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 16:47:45.170833 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 16:47:45.174233 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 16:47:45.177164 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 16:47:45.183738 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 16:47:45.187008 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 16:47:45.191116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 16:47:45.197717 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 16:47:45.200190 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 16:47:45.204081 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 16:47:45.210608 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 16:47:45.213797 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 16:47:45.217047 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 16:47:45.223393 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 16:47:45.227004 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4205 16:47:45.230176 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 16:47:45.233704 Total UI for P1: 0, mck2ui 16
4207 16:47:45.237008 best dqsien dly found for B0: ( 0, 13, 12)
4208 16:47:45.240265 Total UI for P1: 0, mck2ui 16
4209 16:47:45.243770 best dqsien dly found for B1: ( 0, 13, 12)
4210 16:47:45.246581 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4211 16:47:45.250083 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4212 16:47:45.250581
4213 16:47:45.257119 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 16:47:45.260152 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4215 16:47:45.263229 [Gating] SW calibration Done
4216 16:47:45.263793 ==
4217 16:47:45.266420 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 16:47:45.269988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 16:47:45.270641 ==
4220 16:47:45.271026 RX Vref Scan: 0
4221 16:47:45.271379
4222 16:47:45.273134 RX Vref 0 -> 0, step: 1
4223 16:47:45.273627
4224 16:47:45.276414 RX Delay -230 -> 252, step: 16
4225 16:47:45.279369 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4226 16:47:45.286574 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4227 16:47:45.289408 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4228 16:47:45.292935 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4229 16:47:45.295902 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4230 16:47:45.299665 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4231 16:47:45.305679 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4232 16:47:45.309132 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4233 16:47:45.312259 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4234 16:47:45.315763 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4235 16:47:45.322485 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4236 16:47:45.325582 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4237 16:47:45.329356 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4238 16:47:45.332424 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4239 16:47:45.339450 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4240 16:47:45.342428 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4241 16:47:45.343001 ==
4242 16:47:45.345673 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 16:47:45.348962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 16:47:45.349567 ==
4245 16:47:45.352508 DQS Delay:
4246 16:47:45.353081 DQS0 = 0, DQS1 = 0
4247 16:47:45.353460 DQM Delay:
4248 16:47:45.355807 DQM0 = 47, DQM1 = 41
4249 16:47:45.356281 DQ Delay:
4250 16:47:45.359232 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4251 16:47:45.362388 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4252 16:47:45.365948 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4253 16:47:45.369006 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4254 16:47:45.369580
4255 16:47:45.369953
4256 16:47:45.370295 ==
4257 16:47:45.372558 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 16:47:45.378944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 16:47:45.379526 ==
4260 16:47:45.379908
4261 16:47:45.380257
4262 16:47:45.380596 TX Vref Scan disable
4263 16:47:45.381964 == TX Byte 0 ==
4264 16:47:45.385303 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4265 16:47:45.392272 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4266 16:47:45.392851 == TX Byte 1 ==
4267 16:47:45.395609 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4268 16:47:45.402681 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4269 16:47:45.403152 ==
4270 16:47:45.405601 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 16:47:45.408660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 16:47:45.409256 ==
4273 16:47:45.409646
4274 16:47:45.409997
4275 16:47:45.411958 TX Vref Scan disable
4276 16:47:45.415211 == TX Byte 0 ==
4277 16:47:45.418945 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4278 16:47:45.422068 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4279 16:47:45.425258 == TX Byte 1 ==
4280 16:47:45.428299 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4281 16:47:45.431637 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4282 16:47:45.432116
4283 16:47:45.432491 [DATLAT]
4284 16:47:45.435128 Freq=600, CH0 RK1
4285 16:47:45.435741
4286 16:47:45.439245 DATLAT Default: 0x9
4287 16:47:45.439814 0, 0xFFFF, sum = 0
4288 16:47:45.441970 1, 0xFFFF, sum = 0
4289 16:47:45.442573 2, 0xFFFF, sum = 0
4290 16:47:45.445278 3, 0xFFFF, sum = 0
4291 16:47:45.445926 4, 0xFFFF, sum = 0
4292 16:47:45.448491 5, 0xFFFF, sum = 0
4293 16:47:45.448958 6, 0xFFFF, sum = 0
4294 16:47:45.451359 7, 0xFFFF, sum = 0
4295 16:47:45.451827 8, 0x0, sum = 1
4296 16:47:45.454926 9, 0x0, sum = 2
4297 16:47:45.455393 10, 0x0, sum = 3
4298 16:47:45.457898 11, 0x0, sum = 4
4299 16:47:45.458389 best_step = 9
4300 16:47:45.458761
4301 16:47:45.459103 ==
4302 16:47:45.461219 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 16:47:45.464631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 16:47:45.465094 ==
4305 16:47:45.468559 RX Vref Scan: 0
4306 16:47:45.469015
4307 16:47:45.471061 RX Vref 0 -> 0, step: 1
4308 16:47:45.471521
4309 16:47:45.471886 RX Delay -179 -> 252, step: 8
4310 16:47:45.479317 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4311 16:47:45.483766 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4312 16:47:45.486159 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4313 16:47:45.489315 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4314 16:47:45.496455 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4315 16:47:45.499210 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4316 16:47:45.503041 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4317 16:47:45.506193 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4318 16:47:45.509006 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4319 16:47:45.515952 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4320 16:47:45.518828 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4321 16:47:45.522497 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4322 16:47:45.525604 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4323 16:47:45.531940 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4324 16:47:45.535470 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4325 16:47:45.538965 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4326 16:47:45.539520 ==
4327 16:47:45.542195 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 16:47:45.545877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 16:47:45.546416 ==
4330 16:47:45.548653 DQS Delay:
4331 16:47:45.549212 DQS0 = 0, DQS1 = 0
4332 16:47:45.551787 DQM Delay:
4333 16:47:45.552247 DQM0 = 48, DQM1 = 40
4334 16:47:45.552620 DQ Delay:
4335 16:47:45.555579 DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44
4336 16:47:45.558771 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4337 16:47:45.561917 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4338 16:47:45.565402 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =52
4339 16:47:45.565953
4340 16:47:45.566321
4341 16:47:45.575274 [DQSOSCAuto] RK1, (LSB)MR18= 0x6431, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4342 16:47:45.578534 CH0 RK1: MR19=808, MR18=6431
4343 16:47:45.585001 CH0_RK1: MR19=0x808, MR18=0x6431, DQSOSC=391, MR23=63, INC=171, DEC=114
4344 16:47:45.588376 [RxdqsGatingPostProcess] freq 600
4345 16:47:45.591770 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 16:47:45.594993 Pre-setting of DQS Precalculation
4347 16:47:45.601852 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 16:47:45.602535 ==
4349 16:47:45.604726 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 16:47:45.608288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 16:47:45.608869 ==
4352 16:47:45.615301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 16:47:45.617991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4354 16:47:45.622185 [CA 0] Center 35 (5~66) winsize 62
4355 16:47:45.625479 [CA 1] Center 35 (5~66) winsize 62
4356 16:47:45.628836 [CA 2] Center 34 (4~65) winsize 62
4357 16:47:45.631709 [CA 3] Center 33 (3~64) winsize 62
4358 16:47:45.635152 [CA 4] Center 34 (3~65) winsize 63
4359 16:47:45.638962 [CA 5] Center 33 (3~64) winsize 62
4360 16:47:45.639519
4361 16:47:45.641640 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4362 16:47:45.642098
4363 16:47:45.645034 [CATrainingPosCal] consider 1 rank data
4364 16:47:45.648734 u2DelayCellTimex100 = 270/100 ps
4365 16:47:45.651691 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 16:47:45.658475 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4367 16:47:45.661936 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4368 16:47:45.664893 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4369 16:47:45.668118 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4370 16:47:45.671844 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4371 16:47:45.672412
4372 16:47:45.674653 CA PerBit enable=1, Macro0, CA PI delay=33
4373 16:47:45.675120
4374 16:47:45.678678 [CBTSetCACLKResult] CA Dly = 33
4375 16:47:45.681605 CS Dly: 4 (0~35)
4376 16:47:45.682166 ==
4377 16:47:45.684728 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 16:47:45.688148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 16:47:45.688715 ==
4380 16:47:45.694773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 16:47:45.697810 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4382 16:47:45.702421 [CA 0] Center 35 (5~66) winsize 62
4383 16:47:45.705453 [CA 1] Center 35 (5~66) winsize 62
4384 16:47:45.709156 [CA 2] Center 34 (4~65) winsize 62
4385 16:47:45.712458 [CA 3] Center 34 (4~64) winsize 61
4386 16:47:45.715831 [CA 4] Center 34 (4~65) winsize 62
4387 16:47:45.718951 [CA 5] Center 34 (4~64) winsize 61
4388 16:47:45.719531
4389 16:47:45.722091 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4390 16:47:45.722704
4391 16:47:45.725069 [CATrainingPosCal] consider 2 rank data
4392 16:47:45.728670 u2DelayCellTimex100 = 270/100 ps
4393 16:47:45.731893 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4394 16:47:45.735386 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4395 16:47:45.741980 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4396 16:47:45.745480 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4397 16:47:45.748366 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4398 16:47:45.751655 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4399 16:47:45.752125
4400 16:47:45.754812 CA PerBit enable=1, Macro0, CA PI delay=34
4401 16:47:45.755283
4402 16:47:45.758224 [CBTSetCACLKResult] CA Dly = 34
4403 16:47:45.758727 CS Dly: 5 (0~38)
4404 16:47:45.759099
4405 16:47:45.765328 ----->DramcWriteLeveling(PI) begin...
4406 16:47:45.765898 ==
4407 16:47:45.768229 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 16:47:45.771837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 16:47:45.772511 ==
4410 16:47:45.775042 Write leveling (Byte 0): 32 => 32
4411 16:47:45.778929 Write leveling (Byte 1): 31 => 31
4412 16:47:45.781711 DramcWriteLeveling(PI) end<-----
4413 16:47:45.782272
4414 16:47:45.782707 ==
4415 16:47:45.784711 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 16:47:45.788459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 16:47:45.788931 ==
4418 16:47:45.791869 [Gating] SW mode calibration
4419 16:47:45.798111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 16:47:45.804926 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 16:47:45.808377 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 16:47:45.811639 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 16:47:45.818794 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 16:47:45.821284 0 9 12 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (1 0)
4425 16:47:45.825120 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 16:47:45.828292 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 16:47:45.834568 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 16:47:45.837863 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 16:47:45.841337 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 16:47:45.848057 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 16:47:45.851503 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4432 16:47:45.854639 0 10 12 | B1->B0 | 3737 3c3c | 1 1 | (0 0) (0 0)
4433 16:47:45.861230 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 16:47:45.864480 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 16:47:45.867906 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 16:47:45.874379 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 16:47:45.877880 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 16:47:45.881037 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 16:47:45.887763 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 16:47:45.890720 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4441 16:47:45.894535 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 16:47:45.900948 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 16:47:45.904156 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 16:47:45.907983 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 16:47:45.914498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 16:47:45.917811 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 16:47:45.920788 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 16:47:45.927687 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 16:47:45.930820 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 16:47:45.934021 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 16:47:45.940502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 16:47:45.944150 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 16:47:45.946968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 16:47:45.953789 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 16:47:45.957154 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4456 16:47:45.960370 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4457 16:47:45.967090 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 16:47:45.970306 Total UI for P1: 0, mck2ui 16
4459 16:47:45.973471 best dqsien dly found for B0: ( 0, 13, 10)
4460 16:47:45.973945 Total UI for P1: 0, mck2ui 16
4461 16:47:45.980366 best dqsien dly found for B1: ( 0, 13, 10)
4462 16:47:45.983673 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4463 16:47:45.986569 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4464 16:47:45.987045
4465 16:47:45.990154 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4466 16:47:45.993680 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4467 16:47:45.996950 [Gating] SW calibration Done
4468 16:47:45.997517 ==
4469 16:47:46.000497 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 16:47:46.003248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 16:47:46.003723 ==
4472 16:47:46.007152 RX Vref Scan: 0
4473 16:47:46.007718
4474 16:47:46.008090 RX Vref 0 -> 0, step: 1
4475 16:47:46.009779
4476 16:47:46.010344 RX Delay -230 -> 252, step: 16
4477 16:47:46.017146 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4478 16:47:46.019770 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4479 16:47:46.023110 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4480 16:47:46.026237 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4481 16:47:46.033017 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4482 16:47:46.036568 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4483 16:47:46.039473 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4484 16:47:46.043111 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4485 16:47:46.046334 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4486 16:47:46.052525 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4487 16:47:46.055995 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4488 16:47:46.059286 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4489 16:47:46.062693 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4490 16:47:46.069269 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4491 16:47:46.072269 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4492 16:47:46.076207 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4493 16:47:46.076676 ==
4494 16:47:46.078884 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 16:47:46.085777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 16:47:46.086341 ==
4497 16:47:46.086784 DQS Delay:
4498 16:47:46.087136 DQS0 = 0, DQS1 = 0
4499 16:47:46.088831 DQM Delay:
4500 16:47:46.089297 DQM0 = 52, DQM1 = 46
4501 16:47:46.092372 DQ Delay:
4502 16:47:46.096004 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4503 16:47:46.098726 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4504 16:47:46.102470 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4505 16:47:46.105765 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4506 16:47:46.106326
4507 16:47:46.106765
4508 16:47:46.107116 ==
4509 16:47:46.108979 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 16:47:46.112291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 16:47:46.112862 ==
4512 16:47:46.113239
4513 16:47:46.113587
4514 16:47:46.115115 TX Vref Scan disable
4515 16:47:46.115584 == TX Byte 0 ==
4516 16:47:46.122168 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4517 16:47:46.125466 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4518 16:47:46.128851 == TX Byte 1 ==
4519 16:47:46.133041 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4520 16:47:46.135637 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4521 16:47:46.136204 ==
4522 16:47:46.138715 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 16:47:46.142412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 16:47:46.142987 ==
4525 16:47:46.145079
4526 16:47:46.145639
4527 16:47:46.146012 TX Vref Scan disable
4528 16:47:46.148832 == TX Byte 0 ==
4529 16:47:46.152632 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4530 16:47:46.158704 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4531 16:47:46.159286 == TX Byte 1 ==
4532 16:47:46.162384 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 16:47:46.168657 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 16:47:46.169232
4535 16:47:46.169612 [DATLAT]
4536 16:47:46.169962 Freq=600, CH1 RK0
4537 16:47:46.170298
4538 16:47:46.171531 DATLAT Default: 0x9
4539 16:47:46.172002 0, 0xFFFF, sum = 0
4540 16:47:46.175331 1, 0xFFFF, sum = 0
4541 16:47:46.178181 2, 0xFFFF, sum = 0
4542 16:47:46.178692 3, 0xFFFF, sum = 0
4543 16:47:46.182046 4, 0xFFFF, sum = 0
4544 16:47:46.182689 5, 0xFFFF, sum = 0
4545 16:47:46.185354 6, 0xFFFF, sum = 0
4546 16:47:46.186042 7, 0xFFFF, sum = 0
4547 16:47:46.188222 8, 0x0, sum = 1
4548 16:47:46.188698 9, 0x0, sum = 2
4549 16:47:46.189080 10, 0x0, sum = 3
4550 16:47:46.191782 11, 0x0, sum = 4
4551 16:47:46.192356 best_step = 9
4552 16:47:46.192734
4553 16:47:46.193078 ==
4554 16:47:46.194949 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 16:47:46.202088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 16:47:46.202696 ==
4557 16:47:46.203080 RX Vref Scan: 1
4558 16:47:46.203429
4559 16:47:46.204670 RX Vref 0 -> 0, step: 1
4560 16:47:46.205136
4561 16:47:46.208244 RX Delay -163 -> 252, step: 8
4562 16:47:46.208811
4563 16:47:46.211549 Set Vref, RX VrefLevel [Byte0]: 54
4564 16:47:46.215097 [Byte1]: 57
4565 16:47:46.215665
4566 16:47:46.218204 Final RX Vref Byte 0 = 54 to rank0
4567 16:47:46.221694 Final RX Vref Byte 1 = 57 to rank0
4568 16:47:46.224680 Final RX Vref Byte 0 = 54 to rank1
4569 16:47:46.227959 Final RX Vref Byte 1 = 57 to rank1==
4570 16:47:46.231304 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 16:47:46.234991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 16:47:46.235559 ==
4573 16:47:46.237907 DQS Delay:
4574 16:47:46.238487 DQS0 = 0, DQS1 = 0
4575 16:47:46.241443 DQM Delay:
4576 16:47:46.242002 DQM0 = 48, DQM1 = 41
4577 16:47:46.242413 DQ Delay:
4578 16:47:46.245065 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4579 16:47:46.247708 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4580 16:47:46.251329 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4581 16:47:46.254504 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4582 16:47:46.255067
4583 16:47:46.255442
4584 16:47:46.264941 [DQSOSCAuto] RK0, (LSB)MR18= 0x486f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4585 16:47:46.267510 CH1 RK0: MR19=808, MR18=486F
4586 16:47:46.274027 CH1_RK0: MR19=0x808, MR18=0x486F, DQSOSC=389, MR23=63, INC=173, DEC=115
4587 16:47:46.274527
4588 16:47:46.277506 ----->DramcWriteLeveling(PI) begin...
4589 16:47:46.277980 ==
4590 16:47:46.280989 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 16:47:46.284685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 16:47:46.285263 ==
4593 16:47:46.287837 Write leveling (Byte 0): 30 => 30
4594 16:47:46.291815 Write leveling (Byte 1): 30 => 30
4595 16:47:46.294091 DramcWriteLeveling(PI) end<-----
4596 16:47:46.294594
4597 16:47:46.294968 ==
4598 16:47:46.297194 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 16:47:46.300548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 16:47:46.301111 ==
4601 16:47:46.304022 [Gating] SW mode calibration
4602 16:47:46.311274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4603 16:47:46.317574 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4604 16:47:46.321262 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 16:47:46.324533 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 16:47:46.330374 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
4607 16:47:46.333954 0 9 12 | B1->B0 | 2525 3232 | 0 1 | (0 0) (1 0)
4608 16:47:46.337210 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 16:47:46.343639 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 16:47:46.346875 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 16:47:46.350131 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 16:47:46.356998 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 16:47:46.360154 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 16:47:46.363378 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 16:47:46.370057 0 10 12 | B1->B0 | 3e3e 2f2f | 0 1 | (0 0) (1 1)
4616 16:47:46.373840 0 10 16 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
4617 16:47:46.376753 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 16:47:46.383231 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 16:47:46.386225 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 16:47:46.390283 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 16:47:46.396740 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 16:47:46.399754 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 16:47:46.402994 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4624 16:47:46.409635 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 16:47:46.412875 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 16:47:46.416418 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 16:47:46.423246 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 16:47:46.426475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 16:47:46.429833 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 16:47:46.436291 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 16:47:46.439452 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 16:47:46.443052 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 16:47:46.449387 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 16:47:46.452295 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 16:47:46.455866 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 16:47:46.462455 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 16:47:46.466065 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 16:47:46.469450 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 16:47:46.475711 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4640 16:47:46.479389 Total UI for P1: 0, mck2ui 16
4641 16:47:46.482091 best dqsien dly found for B1: ( 0, 13, 10)
4642 16:47:46.485486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 16:47:46.488403 Total UI for P1: 0, mck2ui 16
4644 16:47:46.491882 best dqsien dly found for B0: ( 0, 13, 12)
4645 16:47:46.495528 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4646 16:47:46.498484 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4647 16:47:46.498953
4648 16:47:46.501818 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4649 16:47:46.508534 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4650 16:47:46.509104 [Gating] SW calibration Done
4651 16:47:46.509484 ==
4652 16:47:46.511744 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 16:47:46.518493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 16:47:46.519076 ==
4655 16:47:46.519455 RX Vref Scan: 0
4656 16:47:46.519803
4657 16:47:46.521541 RX Vref 0 -> 0, step: 1
4658 16:47:46.522006
4659 16:47:46.525174 RX Delay -230 -> 252, step: 16
4660 16:47:46.528558 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4661 16:47:46.531695 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4662 16:47:46.538716 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4663 16:47:46.541788 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4664 16:47:46.544964 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4665 16:47:46.548145 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4666 16:47:46.551309 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4667 16:47:46.558117 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4668 16:47:46.561662 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4669 16:47:46.564801 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4670 16:47:46.568038 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4671 16:47:46.574616 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4672 16:47:46.579314 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4673 16:47:46.581237 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4674 16:47:46.585474 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4675 16:47:46.591507 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4676 16:47:46.591983 ==
4677 16:47:46.594273 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 16:47:46.597658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 16:47:46.598153 ==
4680 16:47:46.598606 DQS Delay:
4681 16:47:46.600934 DQS0 = 0, DQS1 = 0
4682 16:47:46.601522 DQM Delay:
4683 16:47:46.604499 DQM0 = 50, DQM1 = 47
4684 16:47:46.604971 DQ Delay:
4685 16:47:46.608207 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4686 16:47:46.610623 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4687 16:47:46.614405 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4688 16:47:46.617573 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4689 16:47:46.618045
4690 16:47:46.618457
4691 16:47:46.618813 ==
4692 16:47:46.621014 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 16:47:46.623846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 16:47:46.627842 ==
4695 16:47:46.628419
4696 16:47:46.628799
4697 16:47:46.629149 TX Vref Scan disable
4698 16:47:46.630272 == TX Byte 0 ==
4699 16:47:46.634564 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4700 16:47:46.637744 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4701 16:47:46.640520 == TX Byte 1 ==
4702 16:47:46.643973 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 16:47:46.647257 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 16:47:46.650565 ==
4705 16:47:46.653914 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 16:47:46.657585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 16:47:46.658157 ==
4708 16:47:46.658572
4709 16:47:46.658923
4710 16:47:46.660057 TX Vref Scan disable
4711 16:47:46.663608 == TX Byte 0 ==
4712 16:47:46.667096 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4713 16:47:46.670638 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4714 16:47:46.675130 == TX Byte 1 ==
4715 16:47:46.676768 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 16:47:46.680155 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 16:47:46.680727
4718 16:47:46.681104 [DATLAT]
4719 16:47:46.683681 Freq=600, CH1 RK1
4720 16:47:46.684252
4721 16:47:46.684632 DATLAT Default: 0x9
4722 16:47:46.686665 0, 0xFFFF, sum = 0
4723 16:47:46.690007 1, 0xFFFF, sum = 0
4724 16:47:46.690535 2, 0xFFFF, sum = 0
4725 16:47:46.693532 3, 0xFFFF, sum = 0
4726 16:47:46.694105 4, 0xFFFF, sum = 0
4727 16:47:46.696651 5, 0xFFFF, sum = 0
4728 16:47:46.697218 6, 0xFFFF, sum = 0
4729 16:47:46.699813 7, 0xFFFF, sum = 0
4730 16:47:46.700389 8, 0x0, sum = 1
4731 16:47:46.702993 9, 0x0, sum = 2
4732 16:47:46.703471 10, 0x0, sum = 3
4733 16:47:46.703859 11, 0x0, sum = 4
4734 16:47:46.706534 best_step = 9
4735 16:47:46.707005
4736 16:47:46.707378 ==
4737 16:47:46.709999 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 16:47:46.713026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 16:47:46.713502 ==
4740 16:47:46.716819 RX Vref Scan: 0
4741 16:47:46.717386
4742 16:47:46.717768 RX Vref 0 -> 0, step: 1
4743 16:47:46.719553
4744 16:47:46.720018 RX Delay -163 -> 252, step: 8
4745 16:47:46.727126 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4746 16:47:46.730312 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4747 16:47:46.733513 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4748 16:47:46.737370 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4749 16:47:46.743712 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4750 16:47:46.747243 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4751 16:47:46.750573 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4752 16:47:46.753731 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4753 16:47:46.756918 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4754 16:47:46.763340 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4755 16:47:46.766542 iDelay=205, Bit 10, Center 44 (-107 ~ 196) 304
4756 16:47:46.769798 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4757 16:47:46.773290 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4758 16:47:46.780440 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4759 16:47:46.782931 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4760 16:47:46.786946 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4761 16:47:46.787520 ==
4762 16:47:46.789770 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 16:47:46.793339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 16:47:46.796766 ==
4765 16:47:46.797332 DQS Delay:
4766 16:47:46.797714 DQS0 = 0, DQS1 = 0
4767 16:47:46.799415 DQM Delay:
4768 16:47:46.799885 DQM0 = 49, DQM1 = 43
4769 16:47:46.802721 DQ Delay:
4770 16:47:46.806444 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =48
4771 16:47:46.806918 DQ4 =52, DQ5 =60, DQ6 =56, DQ7 =48
4772 16:47:46.809052 DQ8 =28, DQ9 =32, DQ10 =44, DQ11 =40
4773 16:47:46.815944 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4774 16:47:46.816515
4775 16:47:46.816980
4776 16:47:46.822571 [DQSOSCAuto] RK1, (LSB)MR18= 0x561c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4777 16:47:46.826060 CH1 RK1: MR19=808, MR18=561C
4778 16:47:46.832226 CH1_RK1: MR19=0x808, MR18=0x561C, DQSOSC=393, MR23=63, INC=169, DEC=113
4779 16:47:46.835634 [RxdqsGatingPostProcess] freq 600
4780 16:47:46.839016 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4781 16:47:46.841944 Pre-setting of DQS Precalculation
4782 16:47:46.848848 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4783 16:47:46.855319 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4784 16:47:46.862221 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4785 16:47:46.862836
4786 16:47:46.863208
4787 16:47:46.865366 [Calibration Summary] 1200 Mbps
4788 16:47:46.865932 CH 0, Rank 0
4789 16:47:46.869011 SW Impedance : PASS
4790 16:47:46.872022 DUTY Scan : NO K
4791 16:47:46.872586 ZQ Calibration : PASS
4792 16:47:46.875795 Jitter Meter : NO K
4793 16:47:46.878902 CBT Training : PASS
4794 16:47:46.879470 Write leveling : PASS
4795 16:47:46.881951 RX DQS gating : PASS
4796 16:47:46.885167 RX DQ/DQS(RDDQC) : PASS
4797 16:47:46.885734 TX DQ/DQS : PASS
4798 16:47:46.888813 RX DATLAT : PASS
4799 16:47:46.891837 RX DQ/DQS(Engine): PASS
4800 16:47:46.892302 TX OE : NO K
4801 16:47:46.895919 All Pass.
4802 16:47:46.896481
4803 16:47:46.896856 CH 0, Rank 1
4804 16:47:46.898194 SW Impedance : PASS
4805 16:47:46.898715 DUTY Scan : NO K
4806 16:47:46.901623 ZQ Calibration : PASS
4807 16:47:46.905204 Jitter Meter : NO K
4808 16:47:46.905810 CBT Training : PASS
4809 16:47:46.908623 Write leveling : PASS
4810 16:47:46.909185 RX DQS gating : PASS
4811 16:47:46.911367 RX DQ/DQS(RDDQC) : PASS
4812 16:47:46.914734 TX DQ/DQS : PASS
4813 16:47:46.915300 RX DATLAT : PASS
4814 16:47:46.918095 RX DQ/DQS(Engine): PASS
4815 16:47:46.922543 TX OE : NO K
4816 16:47:46.923100 All Pass.
4817 16:47:46.923476
4818 16:47:46.923823 CH 1, Rank 0
4819 16:47:46.924591 SW Impedance : PASS
4820 16:47:46.928015 DUTY Scan : NO K
4821 16:47:46.928485 ZQ Calibration : PASS
4822 16:47:46.931017 Jitter Meter : NO K
4823 16:47:46.934297 CBT Training : PASS
4824 16:47:46.934797 Write leveling : PASS
4825 16:47:46.937638 RX DQS gating : PASS
4826 16:47:46.941333 RX DQ/DQS(RDDQC) : PASS
4827 16:47:46.941907 TX DQ/DQS : PASS
4828 16:47:46.945185 RX DATLAT : PASS
4829 16:47:46.947803 RX DQ/DQS(Engine): PASS
4830 16:47:46.948269 TX OE : NO K
4831 16:47:46.950952 All Pass.
4832 16:47:46.951513
4833 16:47:46.951886 CH 1, Rank 1
4834 16:47:46.954245 SW Impedance : PASS
4835 16:47:46.954758 DUTY Scan : NO K
4836 16:47:46.957958 ZQ Calibration : PASS
4837 16:47:46.961903 Jitter Meter : NO K
4838 16:47:46.962497 CBT Training : PASS
4839 16:47:46.964674 Write leveling : PASS
4840 16:47:46.967551 RX DQS gating : PASS
4841 16:47:46.968120 RX DQ/DQS(RDDQC) : PASS
4842 16:47:46.970851 TX DQ/DQS : PASS
4843 16:47:46.974640 RX DATLAT : PASS
4844 16:47:46.975223 RX DQ/DQS(Engine): PASS
4845 16:47:46.977481 TX OE : NO K
4846 16:47:46.978049 All Pass.
4847 16:47:46.978467
4848 16:47:46.981596 DramC Write-DBI off
4849 16:47:46.984182 PER_BANK_REFRESH: Hybrid Mode
4850 16:47:46.984744 TX_TRACKING: ON
4851 16:47:46.994218 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4852 16:47:46.997114 [FAST_K] Save calibration result to emmc
4853 16:47:47.000216 dramc_set_vcore_voltage set vcore to 662500
4854 16:47:47.003743 Read voltage for 933, 3
4855 16:47:47.004307 Vio18 = 0
4856 16:47:47.004681 Vcore = 662500
4857 16:47:47.007162 Vdram = 0
4858 16:47:47.007628 Vddq = 0
4859 16:47:47.007999 Vmddr = 0
4860 16:47:47.013987 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4861 16:47:47.017125 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4862 16:47:47.020312 MEM_TYPE=3, freq_sel=17
4863 16:47:47.024276 sv_algorithm_assistance_LP4_1600
4864 16:47:47.026774 ============ PULL DRAM RESETB DOWN ============
4865 16:47:47.030489 ========== PULL DRAM RESETB DOWN end =========
4866 16:47:47.037234 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4867 16:47:47.040388 ===================================
4868 16:47:47.043064 LPDDR4 DRAM CONFIGURATION
4869 16:47:47.046428 ===================================
4870 16:47:47.046900 EX_ROW_EN[0] = 0x0
4871 16:47:47.049924 EX_ROW_EN[1] = 0x0
4872 16:47:47.050431 LP4Y_EN = 0x0
4873 16:47:47.053886 WORK_FSP = 0x0
4874 16:47:47.054379 WL = 0x3
4875 16:47:47.056445 RL = 0x3
4876 16:47:47.057013 BL = 0x2
4877 16:47:47.059745 RPST = 0x0
4878 16:47:47.060210 RD_PRE = 0x0
4879 16:47:47.062870 WR_PRE = 0x1
4880 16:47:47.063337 WR_PST = 0x0
4881 16:47:47.066215 DBI_WR = 0x0
4882 16:47:47.069793 DBI_RD = 0x0
4883 16:47:47.070386 OTF = 0x1
4884 16:47:47.073117 ===================================
4885 16:47:47.075740 ===================================
4886 16:47:47.076211 ANA top config
4887 16:47:47.079491 ===================================
4888 16:47:47.083026 DLL_ASYNC_EN = 0
4889 16:47:47.086265 ALL_SLAVE_EN = 1
4890 16:47:47.089366 NEW_RANK_MODE = 1
4891 16:47:47.092656 DLL_IDLE_MODE = 1
4892 16:47:47.093121 LP45_APHY_COMB_EN = 1
4893 16:47:47.096642 TX_ODT_DIS = 1
4894 16:47:47.099454 NEW_8X_MODE = 1
4895 16:47:47.102789 ===================================
4896 16:47:47.106446 ===================================
4897 16:47:47.109433 data_rate = 1866
4898 16:47:47.112588 CKR = 1
4899 16:47:47.113151 DQ_P2S_RATIO = 8
4900 16:47:47.116168 ===================================
4901 16:47:47.119106 CA_P2S_RATIO = 8
4902 16:47:47.122826 DQ_CA_OPEN = 0
4903 16:47:47.125427 DQ_SEMI_OPEN = 0
4904 16:47:47.129207 CA_SEMI_OPEN = 0
4905 16:47:47.132378 CA_FULL_RATE = 0
4906 16:47:47.132944 DQ_CKDIV4_EN = 1
4907 16:47:47.135913 CA_CKDIV4_EN = 1
4908 16:47:47.139002 CA_PREDIV_EN = 0
4909 16:47:47.142264 PH8_DLY = 0
4910 16:47:47.145788 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4911 16:47:47.148412 DQ_AAMCK_DIV = 4
4912 16:47:47.152435 CA_AAMCK_DIV = 4
4913 16:47:47.152897 CA_ADMCK_DIV = 4
4914 16:47:47.155144 DQ_TRACK_CA_EN = 0
4915 16:47:47.158783 CA_PICK = 933
4916 16:47:47.162411 CA_MCKIO = 933
4917 16:47:47.165354 MCKIO_SEMI = 0
4918 16:47:47.168852 PLL_FREQ = 3732
4919 16:47:47.172029 DQ_UI_PI_RATIO = 32
4920 16:47:47.172624 CA_UI_PI_RATIO = 0
4921 16:47:47.174924 ===================================
4922 16:47:47.178970 ===================================
4923 16:47:47.182038 memory_type:LPDDR4
4924 16:47:47.185069 GP_NUM : 10
4925 16:47:47.185644 SRAM_EN : 1
4926 16:47:47.188218 MD32_EN : 0
4927 16:47:47.191450 ===================================
4928 16:47:47.194537 [ANA_INIT] >>>>>>>>>>>>>>
4929 16:47:47.198874 <<<<<< [CONFIGURE PHASE]: ANA_TX
4930 16:47:47.201808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4931 16:47:47.204697 ===================================
4932 16:47:47.205273 data_rate = 1866,PCW = 0X8f00
4933 16:47:47.208069 ===================================
4934 16:47:47.212121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4935 16:47:47.218076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 16:47:47.224966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 16:47:47.227786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4938 16:47:47.231508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4939 16:47:47.234556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4940 16:47:47.237668 [ANA_INIT] flow start
4941 16:47:47.240953 [ANA_INIT] PLL >>>>>>>>
4942 16:47:47.241424 [ANA_INIT] PLL <<<<<<<<
4943 16:47:47.244594 [ANA_INIT] MIDPI >>>>>>>>
4944 16:47:47.247649 [ANA_INIT] MIDPI <<<<<<<<
4945 16:47:47.248124 [ANA_INIT] DLL >>>>>>>>
4946 16:47:47.251185 [ANA_INIT] flow end
4947 16:47:47.254663 ============ LP4 DIFF to SE enter ============
4948 16:47:47.257817 ============ LP4 DIFF to SE exit ============
4949 16:47:47.260893 [ANA_INIT] <<<<<<<<<<<<<
4950 16:47:47.264246 [Flow] Enable top DCM control >>>>>
4951 16:47:47.267978 [Flow] Enable top DCM control <<<<<
4952 16:47:47.270959 Enable DLL master slave shuffle
4953 16:47:47.277423 ==============================================================
4954 16:47:47.277902 Gating Mode config
4955 16:47:47.284524 ==============================================================
4956 16:47:47.287509 Config description:
4957 16:47:47.293898 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4958 16:47:47.301339 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4959 16:47:47.307167 SELPH_MODE 0: By rank 1: By Phase
4960 16:47:47.314232 ==============================================================
4961 16:47:47.314874 GAT_TRACK_EN = 1
4962 16:47:47.317598 RX_GATING_MODE = 2
4963 16:47:47.320908 RX_GATING_TRACK_MODE = 2
4964 16:47:47.324030 SELPH_MODE = 1
4965 16:47:47.326872 PICG_EARLY_EN = 1
4966 16:47:47.330935 VALID_LAT_VALUE = 1
4967 16:47:47.337476 ==============================================================
4968 16:47:47.340093 Enter into Gating configuration >>>>
4969 16:47:47.345189 Exit from Gating configuration <<<<
4970 16:47:47.346595 Enter into DVFS_PRE_config >>>>>
4971 16:47:47.356778 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4972 16:47:47.360071 Exit from DVFS_PRE_config <<<<<
4973 16:47:47.363516 Enter into PICG configuration >>>>
4974 16:47:47.366750 Exit from PICG configuration <<<<
4975 16:47:47.370091 [RX_INPUT] configuration >>>>>
4976 16:47:47.373078 [RX_INPUT] configuration <<<<<
4977 16:47:47.376193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4978 16:47:47.382822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4979 16:47:47.389666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 16:47:47.396581 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 16:47:47.399789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 16:47:47.406595 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 16:47:47.409394 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4984 16:47:47.416131 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4985 16:47:47.419086 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4986 16:47:47.422583 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4987 16:47:47.426247 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4988 16:47:47.433010 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 16:47:47.435772 ===================================
4990 16:47:47.438955 LPDDR4 DRAM CONFIGURATION
4991 16:47:47.442472 ===================================
4992 16:47:47.443040 EX_ROW_EN[0] = 0x0
4993 16:47:47.446024 EX_ROW_EN[1] = 0x0
4994 16:47:47.446618 LP4Y_EN = 0x0
4995 16:47:47.449194 WORK_FSP = 0x0
4996 16:47:47.449830 WL = 0x3
4997 16:47:47.452664 RL = 0x3
4998 16:47:47.453234 BL = 0x2
4999 16:47:47.455760 RPST = 0x0
5000 16:47:47.456228 RD_PRE = 0x0
5001 16:47:47.459023 WR_PRE = 0x1
5002 16:47:47.459593 WR_PST = 0x0
5003 16:47:47.462160 DBI_WR = 0x0
5004 16:47:47.465748 DBI_RD = 0x0
5005 16:47:47.466313 OTF = 0x1
5006 16:47:47.469277 ===================================
5007 16:47:47.471835 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5008 16:47:47.475252 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5009 16:47:47.481780 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 16:47:47.485176 ===================================
5011 16:47:47.488116 LPDDR4 DRAM CONFIGURATION
5012 16:47:47.491958 ===================================
5013 16:47:47.492532 EX_ROW_EN[0] = 0x10
5014 16:47:47.494964 EX_ROW_EN[1] = 0x0
5015 16:47:47.495431 LP4Y_EN = 0x0
5016 16:47:47.498601 WORK_FSP = 0x0
5017 16:47:47.499163 WL = 0x3
5018 16:47:47.501750 RL = 0x3
5019 16:47:47.502218 BL = 0x2
5020 16:47:47.505250 RPST = 0x0
5021 16:47:47.505812 RD_PRE = 0x0
5022 16:47:47.508502 WR_PRE = 0x1
5023 16:47:47.508968 WR_PST = 0x0
5024 16:47:47.511714 DBI_WR = 0x0
5025 16:47:47.514972 DBI_RD = 0x0
5026 16:47:47.515534 OTF = 0x1
5027 16:47:47.517911 ===================================
5028 16:47:47.525173 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5029 16:47:47.528246 nWR fixed to 30
5030 16:47:47.532051 [ModeRegInit_LP4] CH0 RK0
5031 16:47:47.532617 [ModeRegInit_LP4] CH0 RK1
5032 16:47:47.535457 [ModeRegInit_LP4] CH1 RK0
5033 16:47:47.538516 [ModeRegInit_LP4] CH1 RK1
5034 16:47:47.539082 match AC timing 9
5035 16:47:47.545322 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5036 16:47:47.548196 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5037 16:47:47.551252 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5038 16:47:47.558754 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5039 16:47:47.561812 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5040 16:47:47.562439 ==
5041 16:47:47.565251 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 16:47:47.568117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5043 16:47:47.568595 ==
5044 16:47:47.574889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5045 16:47:47.581124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5046 16:47:47.584713 [CA 0] Center 38 (7~69) winsize 63
5047 16:47:47.588441 [CA 1] Center 38 (7~69) winsize 63
5048 16:47:47.591086 [CA 2] Center 35 (5~66) winsize 62
5049 16:47:47.594591 [CA 3] Center 35 (5~65) winsize 61
5050 16:47:47.597939 [CA 4] Center 34 (4~64) winsize 61
5051 16:47:47.600997 [CA 5] Center 33 (3~64) winsize 62
5052 16:47:47.601466
5053 16:47:47.605118 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5054 16:47:47.605683
5055 16:47:47.607846 [CATrainingPosCal] consider 1 rank data
5056 16:47:47.611291 u2DelayCellTimex100 = 270/100 ps
5057 16:47:47.614612 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5058 16:47:47.618085 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5059 16:47:47.621485 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5060 16:47:47.624500 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5061 16:47:47.631415 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5062 16:47:47.634255 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5063 16:47:47.634766
5064 16:47:47.637981 CA PerBit enable=1, Macro0, CA PI delay=33
5065 16:47:47.638587
5066 16:47:47.641095 [CBTSetCACLKResult] CA Dly = 33
5067 16:47:47.641562 CS Dly: 7 (0~38)
5068 16:47:47.641929 ==
5069 16:47:47.644449 Dram Type= 6, Freq= 0, CH_0, rank 1
5070 16:47:47.647629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 16:47:47.650621 ==
5072 16:47:47.654652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 16:47:47.661063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5074 16:47:47.663930 [CA 0] Center 38 (8~69) winsize 62
5075 16:47:47.667102 [CA 1] Center 38 (8~69) winsize 62
5076 16:47:47.670747 [CA 2] Center 36 (6~66) winsize 61
5077 16:47:47.673653 [CA 3] Center 35 (5~66) winsize 62
5078 16:47:47.676904 [CA 4] Center 34 (4~65) winsize 62
5079 16:47:47.680940 [CA 5] Center 34 (4~65) winsize 62
5080 16:47:47.681503
5081 16:47:47.683832 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5082 16:47:47.684401
5083 16:47:47.686889 [CATrainingPosCal] consider 2 rank data
5084 16:47:47.690442 u2DelayCellTimex100 = 270/100 ps
5085 16:47:47.693576 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5086 16:47:47.697245 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5087 16:47:47.703644 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5088 16:47:47.707058 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5089 16:47:47.710954 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5090 16:47:47.714073 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5091 16:47:47.714693
5092 16:47:47.717173 CA PerBit enable=1, Macro0, CA PI delay=34
5093 16:47:47.717731
5094 16:47:47.720467 [CBTSetCACLKResult] CA Dly = 34
5095 16:47:47.721027 CS Dly: 7 (0~39)
5096 16:47:47.723119
5097 16:47:47.726783 ----->DramcWriteLeveling(PI) begin...
5098 16:47:47.727348 ==
5099 16:47:47.730138 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 16:47:47.733295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 16:47:47.733857 ==
5102 16:47:47.736573 Write leveling (Byte 0): 33 => 33
5103 16:47:47.739960 Write leveling (Byte 1): 28 => 28
5104 16:47:47.743071 DramcWriteLeveling(PI) end<-----
5105 16:47:47.743535
5106 16:47:47.743904 ==
5107 16:47:47.746533 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 16:47:47.749878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 16:47:47.750566 ==
5110 16:47:47.753852 [Gating] SW mode calibration
5111 16:47:47.759783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5112 16:47:47.766460 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5113 16:47:47.769684 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5114 16:47:47.772946 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 16:47:47.779355 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 16:47:47.783057 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 16:47:47.786239 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 16:47:47.792735 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 16:47:47.796291 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5120 16:47:47.799032 0 14 28 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (0 0)
5121 16:47:47.806036 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 16:47:47.809112 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 16:47:47.813223 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 16:47:47.819137 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 16:47:47.822338 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 16:47:47.825933 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 16:47:47.832315 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5128 16:47:47.835557 0 15 28 | B1->B0 | 2a29 4545 | 1 0 | (0 0) (0 0)
5129 16:47:47.838608 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5130 16:47:47.846026 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 16:47:47.849043 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 16:47:47.851851 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 16:47:47.858902 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 16:47:47.862040 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 16:47:47.865683 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 16:47:47.872105 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5137 16:47:47.875839 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5138 16:47:47.878323 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 16:47:47.885218 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 16:47:47.888546 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 16:47:47.891398 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 16:47:47.898534 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 16:47:47.901473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 16:47:47.905056 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 16:47:47.911451 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 16:47:47.915211 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 16:47:47.918914 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 16:47:47.924845 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 16:47:47.928242 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 16:47:47.932434 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 16:47:47.937842 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 16:47:47.941546 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5153 16:47:47.944484 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 16:47:47.947963 Total UI for P1: 0, mck2ui 16
5155 16:47:47.951289 best dqsien dly found for B0: ( 1, 2, 28)
5156 16:47:47.954884 Total UI for P1: 0, mck2ui 16
5157 16:47:47.957904 best dqsien dly found for B1: ( 1, 2, 30)
5158 16:47:47.961145 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5159 16:47:47.964261 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5160 16:47:47.964731
5161 16:47:47.968220 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5162 16:47:47.974690 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5163 16:47:47.975254 [Gating] SW calibration Done
5164 16:47:47.975632 ==
5165 16:47:47.977863 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 16:47:47.984659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 16:47:47.985235 ==
5168 16:47:47.985619 RX Vref Scan: 0
5169 16:47:47.985969
5170 16:47:47.987417 RX Vref 0 -> 0, step: 1
5171 16:47:47.987911
5172 16:47:47.990565 RX Delay -80 -> 252, step: 8
5173 16:47:47.993812 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5174 16:47:47.997244 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5175 16:47:48.000543 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5176 16:47:48.007502 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5177 16:47:48.010727 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5178 16:47:48.014394 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5179 16:47:48.016953 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5180 16:47:48.020343 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5181 16:47:48.026856 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5182 16:47:48.030576 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5183 16:47:48.033542 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5184 16:47:48.037440 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5185 16:47:48.040019 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5186 16:47:48.043470 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5187 16:47:48.050035 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5188 16:47:48.053553 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5189 16:47:48.054120 ==
5190 16:47:48.056946 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 16:47:48.060110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 16:47:48.060683 ==
5193 16:47:48.063277 DQS Delay:
5194 16:47:48.063836 DQS0 = 0, DQS1 = 0
5195 16:47:48.064242 DQM Delay:
5196 16:47:48.066562 DQM0 = 105, DQM1 = 91
5197 16:47:48.067030 DQ Delay:
5198 16:47:48.070014 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5199 16:47:48.073274 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5200 16:47:48.076480 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =87
5201 16:47:48.079970 DQ12 =95, DQ13 =95, DQ14 =103, DQ15 =99
5202 16:47:48.080535
5203 16:47:48.083037
5204 16:47:48.083502 ==
5205 16:47:48.086410 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 16:47:48.089615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 16:47:48.090186 ==
5208 16:47:48.090623
5209 16:47:48.090978
5210 16:47:48.093054 TX Vref Scan disable
5211 16:47:48.093620 == TX Byte 0 ==
5212 16:47:48.099457 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5213 16:47:48.103180 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5214 16:47:48.103651 == TX Byte 1 ==
5215 16:47:48.109741 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5216 16:47:48.112655 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5217 16:47:48.113281 ==
5218 16:47:48.115966 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 16:47:48.119846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 16:47:48.120413 ==
5221 16:47:48.120790
5222 16:47:48.121133
5223 16:47:48.122555 TX Vref Scan disable
5224 16:47:48.125967 == TX Byte 0 ==
5225 16:47:48.129642 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5226 16:47:48.132697 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5227 16:47:48.136405 == TX Byte 1 ==
5228 16:47:48.139930 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5229 16:47:48.142904 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5230 16:47:48.143375
5231 16:47:48.146133 [DATLAT]
5232 16:47:48.146631 Freq=933, CH0 RK0
5233 16:47:48.147007
5234 16:47:48.149274 DATLAT Default: 0xd
5235 16:47:48.149742 0, 0xFFFF, sum = 0
5236 16:47:48.153458 1, 0xFFFF, sum = 0
5237 16:47:48.154032 2, 0xFFFF, sum = 0
5238 16:47:48.155760 3, 0xFFFF, sum = 0
5239 16:47:48.156237 4, 0xFFFF, sum = 0
5240 16:47:48.159373 5, 0xFFFF, sum = 0
5241 16:47:48.159949 6, 0xFFFF, sum = 0
5242 16:47:48.162823 7, 0xFFFF, sum = 0
5243 16:47:48.163301 8, 0xFFFF, sum = 0
5244 16:47:48.166065 9, 0xFFFF, sum = 0
5245 16:47:48.166677 10, 0x0, sum = 1
5246 16:47:48.169451 11, 0x0, sum = 2
5247 16:47:48.170023 12, 0x0, sum = 3
5248 16:47:48.172887 13, 0x0, sum = 4
5249 16:47:48.173457 best_step = 11
5250 16:47:48.173831
5251 16:47:48.174177 ==
5252 16:47:48.175824 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 16:47:48.182299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 16:47:48.182901 ==
5255 16:47:48.183281 RX Vref Scan: 1
5256 16:47:48.183627
5257 16:47:48.185817 RX Vref 0 -> 0, step: 1
5258 16:47:48.186417
5259 16:47:48.189494 RX Delay -61 -> 252, step: 4
5260 16:47:48.190057
5261 16:47:48.192199 Set Vref, RX VrefLevel [Byte0]: 63
5262 16:47:48.195616 [Byte1]: 50
5263 16:47:48.196184
5264 16:47:48.199078 Final RX Vref Byte 0 = 63 to rank0
5265 16:47:48.202544 Final RX Vref Byte 1 = 50 to rank0
5266 16:47:48.206039 Final RX Vref Byte 0 = 63 to rank1
5267 16:47:48.208931 Final RX Vref Byte 1 = 50 to rank1==
5268 16:47:48.212323 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 16:47:48.215318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 16:47:48.215816 ==
5271 16:47:48.219062 DQS Delay:
5272 16:47:48.219533 DQS0 = 0, DQS1 = 0
5273 16:47:48.221760 DQM Delay:
5274 16:47:48.222412 DQM0 = 107, DQM1 = 90
5275 16:47:48.222814 DQ Delay:
5276 16:47:48.225132 DQ0 =106, DQ1 =104, DQ2 =106, DQ3 =106
5277 16:47:48.228924 DQ4 =110, DQ5 =98, DQ6 =116, DQ7 =114
5278 16:47:48.231913 DQ8 =82, DQ9 =76, DQ10 =90, DQ11 =90
5279 16:47:48.238743 DQ12 =94, DQ13 =92, DQ14 =104, DQ15 =98
5280 16:47:48.239302
5281 16:47:48.239677
5282 16:47:48.244931 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5283 16:47:48.248683 CH0 RK0: MR19=505, MR18=2622
5284 16:47:48.255257 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5285 16:47:48.255821
5286 16:47:48.258923 ----->DramcWriteLeveling(PI) begin...
5287 16:47:48.259505 ==
5288 16:47:48.262498 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 16:47:48.265071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 16:47:48.265648 ==
5291 16:47:48.268379 Write leveling (Byte 0): 33 => 33
5292 16:47:48.272104 Write leveling (Byte 1): 30 => 30
5293 16:47:48.274886 DramcWriteLeveling(PI) end<-----
5294 16:47:48.275337
5295 16:47:48.275697 ==
5296 16:47:48.279131 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 16:47:48.282047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 16:47:48.282540 ==
5299 16:47:48.285244 [Gating] SW mode calibration
5300 16:47:48.291419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5301 16:47:48.298376 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5302 16:47:48.302010 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 16:47:48.304922 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 16:47:48.311801 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 16:47:48.314618 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 16:47:48.318335 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 16:47:48.324911 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 16:47:48.327912 0 14 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5309 16:47:48.331114 0 14 28 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
5310 16:47:48.337826 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 16:47:48.341505 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 16:47:48.344714 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 16:47:48.351211 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 16:47:48.355147 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 16:47:48.358159 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 16:47:48.364266 0 15 24 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
5317 16:47:48.367681 0 15 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
5318 16:47:48.374011 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 16:47:48.377501 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 16:47:48.380752 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 16:47:48.387453 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 16:47:48.391136 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 16:47:48.393851 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 16:47:48.400661 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 16:47:48.403486 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5326 16:47:48.406882 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5327 16:47:48.410595 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 16:47:48.417279 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 16:47:48.420262 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 16:47:48.423603 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 16:47:48.430291 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 16:47:48.434282 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 16:47:48.436972 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 16:47:48.443284 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 16:47:48.446759 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 16:47:48.450039 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 16:47:48.456786 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 16:47:48.460417 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 16:47:48.463320 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 16:47:48.469888 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 16:47:48.473447 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5342 16:47:48.476604 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 16:47:48.479797 Total UI for P1: 0, mck2ui 16
5344 16:47:48.484129 best dqsien dly found for B0: ( 1, 2, 28)
5345 16:47:48.487212 Total UI for P1: 0, mck2ui 16
5346 16:47:48.490651 best dqsien dly found for B1: ( 1, 2, 28)
5347 16:47:48.493290 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5348 16:47:48.496491 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5349 16:47:48.499763
5350 16:47:48.502736 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5351 16:47:48.507338 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5352 16:47:48.509628 [Gating] SW calibration Done
5353 16:47:48.510100 ==
5354 16:47:48.513080 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 16:47:48.516171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 16:47:48.516739 ==
5357 16:47:48.517118 RX Vref Scan: 0
5358 16:47:48.519431
5359 16:47:48.519899 RX Vref 0 -> 0, step: 1
5360 16:47:48.520270
5361 16:47:48.522602 RX Delay -80 -> 252, step: 8
5362 16:47:48.526066 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5363 16:47:48.529308 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5364 16:47:48.536145 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5365 16:47:48.539157 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5366 16:47:48.542569 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5367 16:47:48.545805 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5368 16:47:48.549581 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5369 16:47:48.556021 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5370 16:47:48.559008 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5371 16:47:48.563302 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5372 16:47:48.565702 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5373 16:47:48.569424 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5374 16:47:48.572632 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5375 16:47:48.578955 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5376 16:47:48.582593 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5377 16:47:48.585817 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5378 16:47:48.586421 ==
5379 16:47:48.588584 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 16:47:48.592401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 16:47:48.592977 ==
5382 16:47:48.595174 DQS Delay:
5383 16:47:48.595638 DQS0 = 0, DQS1 = 0
5384 16:47:48.596006 DQM Delay:
5385 16:47:48.599151 DQM0 = 105, DQM1 = 91
5386 16:47:48.599814 DQ Delay:
5387 16:47:48.602275 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5388 16:47:48.605516 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5389 16:47:48.608705 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5390 16:47:48.611950 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5391 16:47:48.612516
5392 16:47:48.615259
5393 16:47:48.615822 ==
5394 16:47:48.618540 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 16:47:48.621806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 16:47:48.622408 ==
5397 16:47:48.622788
5398 16:47:48.623130
5399 16:47:48.625749 TX Vref Scan disable
5400 16:47:48.626315 == TX Byte 0 ==
5401 16:47:48.632697 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5402 16:47:48.634738 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5403 16:47:48.635206 == TX Byte 1 ==
5404 16:47:48.641409 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5405 16:47:48.645468 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5406 16:47:48.646096 ==
5407 16:47:48.648583 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 16:47:48.651611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 16:47:48.652201 ==
5410 16:47:48.652684
5411 16:47:48.653135
5412 16:47:48.654697 TX Vref Scan disable
5413 16:47:48.658542 == TX Byte 0 ==
5414 16:47:48.661345 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5415 16:47:48.664890 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5416 16:47:48.668154 == TX Byte 1 ==
5417 16:47:48.671593 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5418 16:47:48.674310 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5419 16:47:48.674835
5420 16:47:48.678455 [DATLAT]
5421 16:47:48.678933 Freq=933, CH0 RK1
5422 16:47:48.679410
5423 16:47:48.681047 DATLAT Default: 0xb
5424 16:47:48.681520 0, 0xFFFF, sum = 0
5425 16:47:48.684484 1, 0xFFFF, sum = 0
5426 16:47:48.685069 2, 0xFFFF, sum = 0
5427 16:47:48.688219 3, 0xFFFF, sum = 0
5428 16:47:48.688801 4, 0xFFFF, sum = 0
5429 16:47:48.690947 5, 0xFFFF, sum = 0
5430 16:47:48.691426 6, 0xFFFF, sum = 0
5431 16:47:48.695054 7, 0xFFFF, sum = 0
5432 16:47:48.697549 8, 0xFFFF, sum = 0
5433 16:47:48.698136 9, 0xFFFF, sum = 0
5434 16:47:48.700724 10, 0x0, sum = 1
5435 16:47:48.701211 11, 0x0, sum = 2
5436 16:47:48.701693 12, 0x0, sum = 3
5437 16:47:48.704514 13, 0x0, sum = 4
5438 16:47:48.704995 best_step = 11
5439 16:47:48.705469
5440 16:47:48.707131 ==
5441 16:47:48.707608 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 16:47:48.714513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 16:47:48.715089 ==
5444 16:47:48.715572 RX Vref Scan: 0
5445 16:47:48.716018
5446 16:47:48.717194 RX Vref 0 -> 0, step: 1
5447 16:47:48.717670
5448 16:47:48.721507 RX Delay -53 -> 252, step: 4
5449 16:47:48.724448 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
5450 16:47:48.730853 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5451 16:47:48.733915 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5452 16:47:48.737458 iDelay=203, Bit 3, Center 100 (15 ~ 186) 172
5453 16:47:48.740941 iDelay=203, Bit 4, Center 106 (19 ~ 194) 176
5454 16:47:48.743935 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5455 16:47:48.750519 iDelay=203, Bit 6, Center 116 (31 ~ 202) 172
5456 16:47:48.753544 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5457 16:47:48.757352 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5458 16:47:48.760215 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5459 16:47:48.764660 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5460 16:47:48.770454 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5461 16:47:48.773493 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5462 16:47:48.776950 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5463 16:47:48.780048 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5464 16:47:48.784032 iDelay=203, Bit 15, Center 100 (19 ~ 182) 164
5465 16:47:48.786784 ==
5466 16:47:48.787361 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 16:47:48.793451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 16:47:48.794033 ==
5469 16:47:48.794606 DQS Delay:
5470 16:47:48.796953 DQS0 = 0, DQS1 = 0
5471 16:47:48.797529 DQM Delay:
5472 16:47:48.799750 DQM0 = 105, DQM1 = 92
5473 16:47:48.800424 DQ Delay:
5474 16:47:48.802980 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =100
5475 16:47:48.807309 DQ4 =106, DQ5 =96, DQ6 =116, DQ7 =110
5476 16:47:48.810584 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5477 16:47:48.813414 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5478 16:47:48.813982
5479 16:47:48.814383
5480 16:47:48.822932 [DQSOSCAuto] RK1, (LSB)MR18= 0x2708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5481 16:47:48.823507 CH0 RK1: MR19=505, MR18=2708
5482 16:47:48.829536 CH0_RK1: MR19=0x505, MR18=0x2708, DQSOSC=409, MR23=63, INC=64, DEC=43
5483 16:47:48.833316 [RxdqsGatingPostProcess] freq 933
5484 16:47:48.839286 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5485 16:47:48.842771 best DQS0 dly(2T, 0.5T) = (0, 10)
5486 16:47:48.846306 best DQS1 dly(2T, 0.5T) = (0, 10)
5487 16:47:48.849432 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5488 16:47:48.853019 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5489 16:47:48.855595 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 16:47:48.859492 best DQS1 dly(2T, 0.5T) = (0, 10)
5491 16:47:48.862543 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 16:47:48.865648 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5493 16:47:48.866216 Pre-setting of DQS Precalculation
5494 16:47:48.872292 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5495 16:47:48.872877 ==
5496 16:47:48.875800 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 16:47:48.879077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 16:47:48.879647 ==
5499 16:47:48.885429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5500 16:47:48.891899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5501 16:47:48.895535 [CA 0] Center 36 (6~67) winsize 62
5502 16:47:48.898892 [CA 1] Center 37 (7~68) winsize 62
5503 16:47:48.902120 [CA 2] Center 35 (5~66) winsize 62
5504 16:47:48.905437 [CA 3] Center 34 (4~65) winsize 62
5505 16:47:48.908917 [CA 4] Center 34 (4~65) winsize 62
5506 16:47:48.911950 [CA 5] Center 34 (4~64) winsize 61
5507 16:47:48.912514
5508 16:47:48.916007 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5509 16:47:48.916574
5510 16:47:48.918549 [CATrainingPosCal] consider 1 rank data
5511 16:47:48.922530 u2DelayCellTimex100 = 270/100 ps
5512 16:47:48.925571 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5513 16:47:48.928896 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5514 16:47:48.931505 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5515 16:47:48.935062 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5516 16:47:48.938177 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5517 16:47:48.945815 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5518 16:47:48.946422
5519 16:47:48.947872 CA PerBit enable=1, Macro0, CA PI delay=34
5520 16:47:48.948336
5521 16:47:48.952081 [CBTSetCACLKResult] CA Dly = 34
5522 16:47:48.952742 CS Dly: 5 (0~36)
5523 16:47:48.953195 ==
5524 16:47:48.954974 Dram Type= 6, Freq= 0, CH_1, rank 1
5525 16:47:48.958460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 16:47:48.961418 ==
5527 16:47:48.965168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5528 16:47:48.971203 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5529 16:47:48.975411 [CA 0] Center 37 (7~68) winsize 62
5530 16:47:48.978136 [CA 1] Center 37 (7~68) winsize 62
5531 16:47:48.981363 [CA 2] Center 35 (5~66) winsize 62
5532 16:47:48.984636 [CA 3] Center 35 (5~65) winsize 61
5533 16:47:48.988133 [CA 4] Center 35 (5~65) winsize 61
5534 16:47:48.991291 [CA 5] Center 34 (4~65) winsize 62
5535 16:47:48.991873
5536 16:47:48.994519 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5537 16:47:48.995073
5538 16:47:48.998195 [CATrainingPosCal] consider 2 rank data
5539 16:47:49.001679 u2DelayCellTimex100 = 270/100 ps
5540 16:47:49.004239 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5541 16:47:49.008489 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5542 16:47:49.011044 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5543 16:47:49.017661 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5544 16:47:49.021001 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5545 16:47:49.024472 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5546 16:47:49.025053
5547 16:47:49.027505 CA PerBit enable=1, Macro0, CA PI delay=34
5548 16:47:49.028080
5549 16:47:49.031688 [CBTSetCACLKResult] CA Dly = 34
5550 16:47:49.032268 CS Dly: 6 (0~38)
5551 16:47:49.032653
5552 16:47:49.034054 ----->DramcWriteLeveling(PI) begin...
5553 16:47:49.038159 ==
5554 16:47:49.038803 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 16:47:49.043962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 16:47:49.044536 ==
5557 16:47:49.047121 Write leveling (Byte 0): 28 => 28
5558 16:47:49.050896 Write leveling (Byte 1): 27 => 27
5559 16:47:49.053666 DramcWriteLeveling(PI) end<-----
5560 16:47:49.054136
5561 16:47:49.054542 ==
5562 16:47:49.057479 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 16:47:49.060754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 16:47:49.061353 ==
5565 16:47:49.063659 [Gating] SW mode calibration
5566 16:47:49.070526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5567 16:47:49.077262 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5568 16:47:49.080267 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 16:47:49.083710 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 16:47:49.090739 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 16:47:49.093375 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 16:47:49.096481 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 16:47:49.103526 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5574 16:47:49.106649 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (0 0) (0 0)
5575 16:47:49.110884 0 14 28 | B1->B0 | 2a2a 2626 | 0 0 | (1 0) (0 0)
5576 16:47:49.116942 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 16:47:49.119996 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 16:47:49.123063 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 16:47:49.129759 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 16:47:49.133489 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 16:47:49.136503 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 16:47:49.143237 0 15 24 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5583 16:47:49.147134 0 15 28 | B1->B0 | 3b3b 4040 | 0 0 | (0 0) (0 0)
5584 16:47:49.149654 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 16:47:49.156410 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 16:47:49.159483 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 16:47:49.162993 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 16:47:49.169656 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 16:47:49.173216 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5590 16:47:49.176911 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5591 16:47:49.179524 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5592 16:47:49.186256 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 16:47:49.189795 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 16:47:49.192696 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 16:47:49.199463 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 16:47:49.203376 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 16:47:49.206477 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 16:47:49.212737 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 16:47:49.215862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 16:47:49.219013 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 16:47:49.226712 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 16:47:49.229398 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 16:47:49.232643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 16:47:49.239312 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 16:47:49.243348 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5606 16:47:49.245668 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5607 16:47:49.252323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 16:47:49.255728 Total UI for P1: 0, mck2ui 16
5609 16:47:49.259285 best dqsien dly found for B0: ( 1, 2, 22)
5610 16:47:49.259914 Total UI for P1: 0, mck2ui 16
5611 16:47:49.265439 best dqsien dly found for B1: ( 1, 2, 24)
5612 16:47:49.269194 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5613 16:47:49.272220 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5614 16:47:49.272786
5615 16:47:49.275535 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5616 16:47:49.279396 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5617 16:47:49.281973 [Gating] SW calibration Done
5618 16:47:49.282491 ==
5619 16:47:49.285356 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 16:47:49.288912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 16:47:49.289481 ==
5622 16:47:49.292475 RX Vref Scan: 0
5623 16:47:49.292943
5624 16:47:49.293314 RX Vref 0 -> 0, step: 1
5625 16:47:49.294972
5626 16:47:49.295434 RX Delay -80 -> 252, step: 8
5627 16:47:49.301860 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5628 16:47:49.304954 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5629 16:47:49.308587 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5630 16:47:49.311779 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5631 16:47:49.315141 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5632 16:47:49.318790 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5633 16:47:49.325051 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5634 16:47:49.328335 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5635 16:47:49.331297 iDelay=200, Bit 8, Center 87 (-8 ~ 183) 192
5636 16:47:49.334901 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5637 16:47:49.338272 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5638 16:47:49.345878 iDelay=200, Bit 11, Center 95 (8 ~ 183) 176
5639 16:47:49.348452 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5640 16:47:49.351765 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5641 16:47:49.354604 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5642 16:47:49.358458 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5643 16:47:49.359020 ==
5644 16:47:49.361070 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 16:47:49.368313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 16:47:49.368886 ==
5647 16:47:49.369265 DQS Delay:
5648 16:47:49.371146 DQS0 = 0, DQS1 = 0
5649 16:47:49.371615 DQM Delay:
5650 16:47:49.371986 DQM0 = 104, DQM1 = 96
5651 16:47:49.374645 DQ Delay:
5652 16:47:49.378080 DQ0 =111, DQ1 =95, DQ2 =95, DQ3 =103
5653 16:47:49.381104 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =99
5654 16:47:49.384379 DQ8 =87, DQ9 =83, DQ10 =99, DQ11 =95
5655 16:47:49.388339 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5656 16:47:49.388911
5657 16:47:49.389288
5658 16:47:49.389635 ==
5659 16:47:49.390970 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 16:47:49.395167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 16:47:49.395638 ==
5662 16:47:49.396013
5663 16:47:49.396358
5664 16:47:49.397668 TX Vref Scan disable
5665 16:47:49.401170 == TX Byte 0 ==
5666 16:47:49.404165 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5667 16:47:49.407507 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5668 16:47:49.410585 == TX Byte 1 ==
5669 16:47:49.414287 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5670 16:47:49.417607 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5671 16:47:49.418174 ==
5672 16:47:49.420684 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 16:47:49.427255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 16:47:49.427823 ==
5675 16:47:49.428198
5676 16:47:49.428542
5677 16:47:49.428869 TX Vref Scan disable
5678 16:47:49.431456 == TX Byte 0 ==
5679 16:47:49.434978 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5680 16:47:49.441428 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5681 16:47:49.442005 == TX Byte 1 ==
5682 16:47:49.444577 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5683 16:47:49.451254 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5684 16:47:49.451816
5685 16:47:49.452183 [DATLAT]
5686 16:47:49.452525 Freq=933, CH1 RK0
5687 16:47:49.452856
5688 16:47:49.454716 DATLAT Default: 0xd
5689 16:47:49.455182 0, 0xFFFF, sum = 0
5690 16:47:49.458203 1, 0xFFFF, sum = 0
5691 16:47:49.461093 2, 0xFFFF, sum = 0
5692 16:47:49.461661 3, 0xFFFF, sum = 0
5693 16:47:49.464608 4, 0xFFFF, sum = 0
5694 16:47:49.465178 5, 0xFFFF, sum = 0
5695 16:47:49.467786 6, 0xFFFF, sum = 0
5696 16:47:49.468255 7, 0xFFFF, sum = 0
5697 16:47:49.471239 8, 0xFFFF, sum = 0
5698 16:47:49.471810 9, 0xFFFF, sum = 0
5699 16:47:49.474432 10, 0x0, sum = 1
5700 16:47:49.474996 11, 0x0, sum = 2
5701 16:47:49.477936 12, 0x0, sum = 3
5702 16:47:49.478551 13, 0x0, sum = 4
5703 16:47:49.478940 best_step = 11
5704 16:47:49.481244
5705 16:47:49.481808 ==
5706 16:47:49.484660 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 16:47:49.487997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 16:47:49.488560 ==
5709 16:47:49.488936 RX Vref Scan: 1
5710 16:47:49.489321
5711 16:47:49.490871 RX Vref 0 -> 0, step: 1
5712 16:47:49.491393
5713 16:47:49.494263 RX Delay -53 -> 252, step: 4
5714 16:47:49.494874
5715 16:47:49.497870 Set Vref, RX VrefLevel [Byte0]: 54
5716 16:47:49.500760 [Byte1]: 57
5717 16:47:49.501225
5718 16:47:49.504348 Final RX Vref Byte 0 = 54 to rank0
5719 16:47:49.507234 Final RX Vref Byte 1 = 57 to rank0
5720 16:47:49.510633 Final RX Vref Byte 0 = 54 to rank1
5721 16:47:49.514152 Final RX Vref Byte 1 = 57 to rank1==
5722 16:47:49.517570 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 16:47:49.521002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 16:47:49.524057 ==
5725 16:47:49.524529 DQS Delay:
5726 16:47:49.524905 DQS0 = 0, DQS1 = 0
5727 16:47:49.527731 DQM Delay:
5728 16:47:49.528315 DQM0 = 108, DQM1 = 102
5729 16:47:49.530910 DQ Delay:
5730 16:47:49.534078 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =106
5731 16:47:49.537892 DQ4 =106, DQ5 =116, DQ6 =118, DQ7 =106
5732 16:47:49.540957 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =98
5733 16:47:49.544323 DQ12 =110, DQ13 =108, DQ14 =108, DQ15 =108
5734 16:47:49.544894
5735 16:47:49.545272
5736 16:47:49.550911 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5737 16:47:49.553882 CH1 RK0: MR19=505, MR18=172F
5738 16:47:49.560293 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5739 16:47:49.560856
5740 16:47:49.563538 ----->DramcWriteLeveling(PI) begin...
5741 16:47:49.564020 ==
5742 16:47:49.567234 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 16:47:49.570535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 16:47:49.573799 ==
5745 16:47:49.574411 Write leveling (Byte 0): 26 => 26
5746 16:47:49.577205 Write leveling (Byte 1): 27 => 27
5747 16:47:49.580312 DramcWriteLeveling(PI) end<-----
5748 16:47:49.580879
5749 16:47:49.581252 ==
5750 16:47:49.583415 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 16:47:49.590465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 16:47:49.591034 ==
5753 16:47:49.593324 [Gating] SW mode calibration
5754 16:47:49.600188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5755 16:47:49.603302 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5756 16:47:49.609729 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5757 16:47:49.613353 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 16:47:49.616719 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 16:47:49.623499 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 16:47:49.626223 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 16:47:49.629476 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 16:47:49.636255 0 14 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5763 16:47:49.639254 0 14 28 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (1 1)
5764 16:47:49.643196 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 16:47:49.649709 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 16:47:49.652695 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 16:47:49.655578 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 16:47:49.662784 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 16:47:49.665611 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 16:47:49.669063 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5771 16:47:49.675648 0 15 28 | B1->B0 | 3c3b 3030 | 1 0 | (0 0) (0 0)
5772 16:47:49.679004 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 16:47:49.682269 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 16:47:49.688756 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 16:47:49.692331 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 16:47:49.695707 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 16:47:49.701897 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 16:47:49.704989 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5779 16:47:49.708444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 16:47:49.714867 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 16:47:49.718461 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 16:47:49.721847 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 16:47:49.728377 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 16:47:49.731795 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 16:47:49.734668 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 16:47:49.741436 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 16:47:49.744766 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 16:47:49.748098 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 16:47:49.755471 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 16:47:49.758432 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 16:47:49.761341 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 16:47:49.768484 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 16:47:49.771239 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 16:47:49.774971 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5795 16:47:49.781743 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 16:47:49.782304 Total UI for P1: 0, mck2ui 16
5797 16:47:49.788010 best dqsien dly found for B0: ( 1, 2, 24)
5798 16:47:49.788573 Total UI for P1: 0, mck2ui 16
5799 16:47:49.794528 best dqsien dly found for B1: ( 1, 2, 24)
5800 16:47:49.798092 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5801 16:47:49.801364 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5802 16:47:49.801927
5803 16:47:49.804307 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5804 16:47:49.807641 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5805 16:47:49.811489 [Gating] SW calibration Done
5806 16:47:49.812054 ==
5807 16:47:49.814547 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 16:47:49.817619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 16:47:49.818195 ==
5810 16:47:49.821028 RX Vref Scan: 0
5811 16:47:49.821591
5812 16:47:49.821965 RX Vref 0 -> 0, step: 1
5813 16:47:49.822318
5814 16:47:49.824000 RX Delay -80 -> 252, step: 8
5815 16:47:49.827457 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5816 16:47:49.833969 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5817 16:47:49.837262 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5818 16:47:49.840952 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5819 16:47:49.843802 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5820 16:47:49.847393 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5821 16:47:49.854509 iDelay=200, Bit 6, Center 115 (32 ~ 199) 168
5822 16:47:49.857347 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5823 16:47:49.860780 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5824 16:47:49.863765 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5825 16:47:49.867747 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5826 16:47:49.870514 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5827 16:47:49.877517 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5828 16:47:49.880677 iDelay=200, Bit 13, Center 107 (16 ~ 199) 184
5829 16:47:49.883741 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5830 16:47:49.888130 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5831 16:47:49.888695 ==
5832 16:47:49.890535 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 16:47:49.896927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 16:47:49.897498 ==
5835 16:47:49.897876 DQS Delay:
5836 16:47:49.900308 DQS0 = 0, DQS1 = 0
5837 16:47:49.900871 DQM Delay:
5838 16:47:49.903796 DQM0 = 105, DQM1 = 98
5839 16:47:49.904362 DQ Delay:
5840 16:47:49.906858 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =103
5841 16:47:49.910147 DQ4 =103, DQ5 =115, DQ6 =115, DQ7 =103
5842 16:47:49.913560 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5843 16:47:49.917632 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5844 16:47:49.918103
5845 16:47:49.918540
5846 16:47:49.918896 ==
5847 16:47:49.919850 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 16:47:49.923190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 16:47:49.923664 ==
5850 16:47:49.926620
5851 16:47:49.927184
5852 16:47:49.927567 TX Vref Scan disable
5853 16:47:49.929845 == TX Byte 0 ==
5854 16:47:49.932981 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5855 16:47:49.936589 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5856 16:47:49.939531 == TX Byte 1 ==
5857 16:47:49.943860 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5858 16:47:49.946438 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5859 16:47:49.946921 ==
5860 16:47:49.950207 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 16:47:49.956225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 16:47:49.956780 ==
5863 16:47:49.957158
5864 16:47:49.957501
5865 16:47:49.957833 TX Vref Scan disable
5866 16:47:49.960970 == TX Byte 0 ==
5867 16:47:49.963888 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5868 16:47:49.970699 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5869 16:47:49.971271 == TX Byte 1 ==
5870 16:47:49.974192 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5871 16:47:49.980753 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5872 16:47:49.981332
5873 16:47:49.981706 [DATLAT]
5874 16:47:49.982050 Freq=933, CH1 RK1
5875 16:47:49.982420
5876 16:47:49.983728 DATLAT Default: 0xb
5877 16:47:49.984193 0, 0xFFFF, sum = 0
5878 16:47:49.987235 1, 0xFFFF, sum = 0
5879 16:47:49.990593 2, 0xFFFF, sum = 0
5880 16:47:49.991167 3, 0xFFFF, sum = 0
5881 16:47:49.994025 4, 0xFFFF, sum = 0
5882 16:47:49.994625 5, 0xFFFF, sum = 0
5883 16:47:49.996942 6, 0xFFFF, sum = 0
5884 16:47:49.997514 7, 0xFFFF, sum = 0
5885 16:47:50.000511 8, 0xFFFF, sum = 0
5886 16:47:50.001081 9, 0xFFFF, sum = 0
5887 16:47:50.003758 10, 0x0, sum = 1
5888 16:47:50.004330 11, 0x0, sum = 2
5889 16:47:50.006966 12, 0x0, sum = 3
5890 16:47:50.007741 13, 0x0, sum = 4
5891 16:47:50.010420 best_step = 11
5892 16:47:50.010985
5893 16:47:50.011358 ==
5894 16:47:50.013382 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 16:47:50.017072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 16:47:50.017641 ==
5897 16:47:50.018012 RX Vref Scan: 0
5898 16:47:50.020034
5899 16:47:50.020599 RX Vref 0 -> 0, step: 1
5900 16:47:50.020978
5901 16:47:50.023106 RX Delay -45 -> 252, step: 4
5902 16:47:50.030619 iDelay=199, Bit 0, Center 112 (39 ~ 186) 148
5903 16:47:50.033480 iDelay=199, Bit 1, Center 102 (27 ~ 178) 152
5904 16:47:50.036588 iDelay=199, Bit 2, Center 98 (23 ~ 174) 152
5905 16:47:50.039493 iDelay=199, Bit 3, Center 108 (31 ~ 186) 156
5906 16:47:50.043309 iDelay=199, Bit 4, Center 110 (31 ~ 190) 160
5907 16:47:50.049632 iDelay=199, Bit 5, Center 118 (39 ~ 198) 160
5908 16:47:50.053110 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5909 16:47:50.056128 iDelay=199, Bit 7, Center 106 (31 ~ 182) 152
5910 16:47:50.059463 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5911 16:47:50.062943 iDelay=199, Bit 9, Center 92 (11 ~ 174) 164
5912 16:47:50.069605 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5913 16:47:50.073279 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5914 16:47:50.076123 iDelay=199, Bit 12, Center 110 (27 ~ 194) 168
5915 16:47:50.079232 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5916 16:47:50.083040 iDelay=199, Bit 14, Center 108 (27 ~ 190) 164
5917 16:47:50.089667 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5918 16:47:50.090242 ==
5919 16:47:50.092755 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 16:47:50.096733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 16:47:50.097312 ==
5922 16:47:50.097693 DQS Delay:
5923 16:47:50.099084 DQS0 = 0, DQS1 = 0
5924 16:47:50.099554 DQM Delay:
5925 16:47:50.102952 DQM0 = 108, DQM1 = 101
5926 16:47:50.103529 DQ Delay:
5927 16:47:50.105959 DQ0 =112, DQ1 =102, DQ2 =98, DQ3 =108
5928 16:47:50.109084 DQ4 =110, DQ5 =118, DQ6 =114, DQ7 =106
5929 16:47:50.113153 DQ8 =88, DQ9 =92, DQ10 =100, DQ11 =94
5930 16:47:50.115475 DQ12 =110, DQ13 =106, DQ14 =108, DQ15 =110
5931 16:47:50.115962
5932 16:47:50.116337
5933 16:47:50.125687 [DQSOSCAuto] RK1, (LSB)MR18= 0x2300, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5934 16:47:50.129224 CH1 RK1: MR19=505, MR18=2300
5935 16:47:50.135613 CH1_RK1: MR19=0x505, MR18=0x2300, DQSOSC=410, MR23=63, INC=64, DEC=42
5936 16:47:50.136194 [RxdqsGatingPostProcess] freq 933
5937 16:47:50.142012 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5938 16:47:50.145100 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 16:47:50.148658 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 16:47:50.152648 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 16:47:50.155275 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 16:47:50.158544 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 16:47:50.161673 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 16:47:50.164980 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 16:47:50.169273 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 16:47:50.172096 Pre-setting of DQS Precalculation
5947 16:47:50.175116 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5948 16:47:50.182251 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5949 16:47:50.191888 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5950 16:47:50.192459
5951 16:47:50.192831
5952 16:47:50.195513 [Calibration Summary] 1866 Mbps
5953 16:47:50.196078 CH 0, Rank 0
5954 16:47:50.198307 SW Impedance : PASS
5955 16:47:50.198914 DUTY Scan : NO K
5956 16:47:50.201658 ZQ Calibration : PASS
5957 16:47:50.204929 Jitter Meter : NO K
5958 16:47:50.205501 CBT Training : PASS
5959 16:47:50.208041 Write leveling : PASS
5960 16:47:50.208535 RX DQS gating : PASS
5961 16:47:50.211621 RX DQ/DQS(RDDQC) : PASS
5962 16:47:50.214804 TX DQ/DQS : PASS
5963 16:47:50.215274 RX DATLAT : PASS
5964 16:47:50.218158 RX DQ/DQS(Engine): PASS
5965 16:47:50.221464 TX OE : NO K
5966 16:47:50.222029 All Pass.
5967 16:47:50.222444
5968 16:47:50.222792 CH 0, Rank 1
5969 16:47:50.224790 SW Impedance : PASS
5970 16:47:50.228170 DUTY Scan : NO K
5971 16:47:50.228740 ZQ Calibration : PASS
5972 16:47:50.231260 Jitter Meter : NO K
5973 16:47:50.234645 CBT Training : PASS
5974 16:47:50.235119 Write leveling : PASS
5975 16:47:50.237783 RX DQS gating : PASS
5976 16:47:50.241272 RX DQ/DQS(RDDQC) : PASS
5977 16:47:50.241954 TX DQ/DQS : PASS
5978 16:47:50.244612 RX DATLAT : PASS
5979 16:47:50.247565 RX DQ/DQS(Engine): PASS
5980 16:47:50.248039 TX OE : NO K
5981 16:47:50.251357 All Pass.
5982 16:47:50.251937
5983 16:47:50.252320 CH 1, Rank 0
5984 16:47:50.254501 SW Impedance : PASS
5985 16:47:50.254975 DUTY Scan : NO K
5986 16:47:50.257836 ZQ Calibration : PASS
5987 16:47:50.261308 Jitter Meter : NO K
5988 16:47:50.261870 CBT Training : PASS
5989 16:47:50.264245 Write leveling : PASS
5990 16:47:50.267905 RX DQS gating : PASS
5991 16:47:50.268468 RX DQ/DQS(RDDQC) : PASS
5992 16:47:50.271143 TX DQ/DQS : PASS
5993 16:47:50.271709 RX DATLAT : PASS
5994 16:47:50.274024 RX DQ/DQS(Engine): PASS
5995 16:47:50.277660 TX OE : NO K
5996 16:47:50.278224 All Pass.
5997 16:47:50.278654
5998 16:47:50.279007 CH 1, Rank 1
5999 16:47:50.281041 SW Impedance : PASS
6000 16:47:50.284420 DUTY Scan : NO K
6001 16:47:50.284998 ZQ Calibration : PASS
6002 16:47:50.287636 Jitter Meter : NO K
6003 16:47:50.290926 CBT Training : PASS
6004 16:47:50.291490 Write leveling : PASS
6005 16:47:50.294023 RX DQS gating : PASS
6006 16:47:50.297210 RX DQ/DQS(RDDQC) : PASS
6007 16:47:50.297679 TX DQ/DQS : PASS
6008 16:47:50.301221 RX DATLAT : PASS
6009 16:47:50.304612 RX DQ/DQS(Engine): PASS
6010 16:47:50.305177 TX OE : NO K
6011 16:47:50.307312 All Pass.
6012 16:47:50.307781
6013 16:47:50.308272 DramC Write-DBI off
6014 16:47:50.310822 PER_BANK_REFRESH: Hybrid Mode
6015 16:47:50.314082 TX_TRACKING: ON
6016 16:47:50.320526 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6017 16:47:50.323534 [FAST_K] Save calibration result to emmc
6018 16:47:50.327299 dramc_set_vcore_voltage set vcore to 650000
6019 16:47:50.330724 Read voltage for 400, 6
6020 16:47:50.331285 Vio18 = 0
6021 16:47:50.333501 Vcore = 650000
6022 16:47:50.334070 Vdram = 0
6023 16:47:50.334514 Vddq = 0
6024 16:47:50.336987 Vmddr = 0
6025 16:47:50.340595 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6026 16:47:50.346467 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6027 16:47:50.350092 MEM_TYPE=3, freq_sel=20
6028 16:47:50.350705 sv_algorithm_assistance_LP4_800
6029 16:47:50.356290 ============ PULL DRAM RESETB DOWN ============
6030 16:47:50.359515 ========== PULL DRAM RESETB DOWN end =========
6031 16:47:50.363624 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6032 16:47:50.366199 ===================================
6033 16:47:50.369905 LPDDR4 DRAM CONFIGURATION
6034 16:47:50.372777 ===================================
6035 16:47:50.376168 EX_ROW_EN[0] = 0x0
6036 16:47:50.376653 EX_ROW_EN[1] = 0x0
6037 16:47:50.379477 LP4Y_EN = 0x0
6038 16:47:50.380053 WORK_FSP = 0x0
6039 16:47:50.382807 WL = 0x2
6040 16:47:50.383274 RL = 0x2
6041 16:47:50.386274 BL = 0x2
6042 16:47:50.386884 RPST = 0x0
6043 16:47:50.389417 RD_PRE = 0x0
6044 16:47:50.389994 WR_PRE = 0x1
6045 16:47:50.392806 WR_PST = 0x0
6046 16:47:50.393372 DBI_WR = 0x0
6047 16:47:50.395688 DBI_RD = 0x0
6048 16:47:50.399602 OTF = 0x1
6049 16:47:50.402733 ===================================
6050 16:47:50.406115 ===================================
6051 16:47:50.406724 ANA top config
6052 16:47:50.409032 ===================================
6053 16:47:50.412571 DLL_ASYNC_EN = 0
6054 16:47:50.416168 ALL_SLAVE_EN = 1
6055 16:47:50.416733 NEW_RANK_MODE = 1
6056 16:47:50.418976 DLL_IDLE_MODE = 1
6057 16:47:50.422613 LP45_APHY_COMB_EN = 1
6058 16:47:50.426227 TX_ODT_DIS = 1
6059 16:47:50.426843 NEW_8X_MODE = 1
6060 16:47:50.428918 ===================================
6061 16:47:50.432418 ===================================
6062 16:47:50.435630 data_rate = 800
6063 16:47:50.439083 CKR = 1
6064 16:47:50.442196 DQ_P2S_RATIO = 4
6065 16:47:50.445752 ===================================
6066 16:47:50.449715 CA_P2S_RATIO = 4
6067 16:47:50.452378 DQ_CA_OPEN = 0
6068 16:47:50.452939 DQ_SEMI_OPEN = 1
6069 16:47:50.455397 CA_SEMI_OPEN = 1
6070 16:47:50.459192 CA_FULL_RATE = 0
6071 16:47:50.462195 DQ_CKDIV4_EN = 0
6072 16:47:50.465527 CA_CKDIV4_EN = 1
6073 16:47:50.469002 CA_PREDIV_EN = 0
6074 16:47:50.469572 PH8_DLY = 0
6075 16:47:50.471728 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6076 16:47:50.474828 DQ_AAMCK_DIV = 0
6077 16:47:50.479451 CA_AAMCK_DIV = 0
6078 16:47:50.481649 CA_ADMCK_DIV = 4
6079 16:47:50.484977 DQ_TRACK_CA_EN = 0
6080 16:47:50.489002 CA_PICK = 800
6081 16:47:50.489569 CA_MCKIO = 400
6082 16:47:50.491490 MCKIO_SEMI = 400
6083 16:47:50.494943 PLL_FREQ = 3016
6084 16:47:50.498524 DQ_UI_PI_RATIO = 32
6085 16:47:50.501476 CA_UI_PI_RATIO = 32
6086 16:47:50.505063 ===================================
6087 16:47:50.508086 ===================================
6088 16:47:50.512490 memory_type:LPDDR4
6089 16:47:50.513054 GP_NUM : 10
6090 16:47:50.514824 SRAM_EN : 1
6091 16:47:50.518239 MD32_EN : 0
6092 16:47:50.522061 ===================================
6093 16:47:50.522679 [ANA_INIT] >>>>>>>>>>>>>>
6094 16:47:50.524748 <<<<<< [CONFIGURE PHASE]: ANA_TX
6095 16:47:50.528472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6096 16:47:50.531473 ===================================
6097 16:47:50.534266 data_rate = 800,PCW = 0X7400
6098 16:47:50.538242 ===================================
6099 16:47:50.541274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6100 16:47:50.547694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 16:47:50.557564 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 16:47:50.561489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6103 16:47:50.567714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6104 16:47:50.571243 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6105 16:47:50.571817 [ANA_INIT] flow start
6106 16:47:50.574177 [ANA_INIT] PLL >>>>>>>>
6107 16:47:50.578541 [ANA_INIT] PLL <<<<<<<<
6108 16:47:50.579014 [ANA_INIT] MIDPI >>>>>>>>
6109 16:47:50.580702 [ANA_INIT] MIDPI <<<<<<<<
6110 16:47:50.584031 [ANA_INIT] DLL >>>>>>>>
6111 16:47:50.584492 [ANA_INIT] flow end
6112 16:47:50.587747 ============ LP4 DIFF to SE enter ============
6113 16:47:50.594213 ============ LP4 DIFF to SE exit ============
6114 16:47:50.594812 [ANA_INIT] <<<<<<<<<<<<<
6115 16:47:50.597599 [Flow] Enable top DCM control >>>>>
6116 16:47:50.600537 [Flow] Enable top DCM control <<<<<
6117 16:47:50.603960 Enable DLL master slave shuffle
6118 16:47:50.610976 ==============================================================
6119 16:47:50.614644 Gating Mode config
6120 16:47:50.617411 ==============================================================
6121 16:47:50.620798 Config description:
6122 16:47:50.631823 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6123 16:47:50.637657 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6124 16:47:50.640723 SELPH_MODE 0: By rank 1: By Phase
6125 16:47:50.647246 ==============================================================
6126 16:47:50.650513 GAT_TRACK_EN = 0
6127 16:47:50.653861 RX_GATING_MODE = 2
6128 16:47:50.656999 RX_GATING_TRACK_MODE = 2
6129 16:47:50.657471 SELPH_MODE = 1
6130 16:47:50.661264 PICG_EARLY_EN = 1
6131 16:47:50.663830 VALID_LAT_VALUE = 1
6132 16:47:50.670420 ==============================================================
6133 16:47:50.674009 Enter into Gating configuration >>>>
6134 16:47:50.677603 Exit from Gating configuration <<<<
6135 16:47:50.680121 Enter into DVFS_PRE_config >>>>>
6136 16:47:50.690546 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6137 16:47:50.694333 Exit from DVFS_PRE_config <<<<<
6138 16:47:50.696995 Enter into PICG configuration >>>>
6139 16:47:50.699909 Exit from PICG configuration <<<<
6140 16:47:50.703912 [RX_INPUT] configuration >>>>>
6141 16:47:50.706815 [RX_INPUT] configuration <<<<<
6142 16:47:50.709856 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6143 16:47:50.716803 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6144 16:47:50.723268 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 16:47:50.729911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 16:47:50.736750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 16:47:50.740080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 16:47:50.746965 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6149 16:47:50.749655 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6150 16:47:50.753103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6151 16:47:50.756393 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6152 16:47:50.762941 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6153 16:47:50.766181 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 16:47:50.770024 ===================================
6155 16:47:50.772838 LPDDR4 DRAM CONFIGURATION
6156 16:47:50.776184 ===================================
6157 16:47:50.776755 EX_ROW_EN[0] = 0x0
6158 16:47:50.779659 EX_ROW_EN[1] = 0x0
6159 16:47:50.780233 LP4Y_EN = 0x0
6160 16:47:50.782922 WORK_FSP = 0x0
6161 16:47:50.783495 WL = 0x2
6162 16:47:50.786031 RL = 0x2
6163 16:47:50.786517 BL = 0x2
6164 16:47:50.789303 RPST = 0x0
6165 16:47:50.792694 RD_PRE = 0x0
6166 16:47:50.793162 WR_PRE = 0x1
6167 16:47:50.795713 WR_PST = 0x0
6168 16:47:50.796178 DBI_WR = 0x0
6169 16:47:50.799602 DBI_RD = 0x0
6170 16:47:50.800166 OTF = 0x1
6171 16:47:50.802785 ===================================
6172 16:47:50.805766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6173 16:47:50.812296 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6174 16:47:50.815812 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 16:47:50.818884 ===================================
6176 16:47:50.822427 LPDDR4 DRAM CONFIGURATION
6177 16:47:50.825689 ===================================
6178 16:47:50.826253 EX_ROW_EN[0] = 0x10
6179 16:47:50.829281 EX_ROW_EN[1] = 0x0
6180 16:47:50.829843 LP4Y_EN = 0x0
6181 16:47:50.832612 WORK_FSP = 0x0
6182 16:47:50.833079 WL = 0x2
6183 16:47:50.836662 RL = 0x2
6184 16:47:50.837227 BL = 0x2
6185 16:47:50.839129 RPST = 0x0
6186 16:47:50.842251 RD_PRE = 0x0
6187 16:47:50.842901 WR_PRE = 0x1
6188 16:47:50.845852 WR_PST = 0x0
6189 16:47:50.846467 DBI_WR = 0x0
6190 16:47:50.848993 DBI_RD = 0x0
6191 16:47:50.849460 OTF = 0x1
6192 16:47:50.852402 ===================================
6193 16:47:50.858728 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6194 16:47:50.862623 nWR fixed to 30
6195 16:47:50.865971 [ModeRegInit_LP4] CH0 RK0
6196 16:47:50.866558 [ModeRegInit_LP4] CH0 RK1
6197 16:47:50.869468 [ModeRegInit_LP4] CH1 RK0
6198 16:47:50.872441 [ModeRegInit_LP4] CH1 RK1
6199 16:47:50.872917 match AC timing 19
6200 16:47:50.879299 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6201 16:47:50.882299 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6202 16:47:50.885285 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6203 16:47:50.892500 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6204 16:47:50.895365 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6205 16:47:50.895943 ==
6206 16:47:50.899013 Dram Type= 6, Freq= 0, CH_0, rank 0
6207 16:47:50.902033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6208 16:47:50.902633 ==
6209 16:47:50.909783 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6210 16:47:50.915146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6211 16:47:50.918472 [CA 0] Center 36 (8~64) winsize 57
6212 16:47:50.922042 [CA 1] Center 36 (8~64) winsize 57
6213 16:47:50.925069 [CA 2] Center 36 (8~64) winsize 57
6214 16:47:50.929218 [CA 3] Center 36 (8~64) winsize 57
6215 16:47:50.931699 [CA 4] Center 36 (8~64) winsize 57
6216 16:47:50.936198 [CA 5] Center 36 (8~64) winsize 57
6217 16:47:50.936823
6218 16:47:50.938091 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6219 16:47:50.938587
6220 16:47:50.942184 [CATrainingPosCal] consider 1 rank data
6221 16:47:50.944820 u2DelayCellTimex100 = 270/100 ps
6222 16:47:50.948461 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 16:47:50.951325 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 16:47:50.955011 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 16:47:50.957861 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 16:47:50.961353 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 16:47:50.964840 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 16:47:50.965407
6229 16:47:50.971269 CA PerBit enable=1, Macro0, CA PI delay=36
6230 16:47:50.971888
6231 16:47:50.972286 [CBTSetCACLKResult] CA Dly = 36
6232 16:47:50.974953 CS Dly: 1 (0~32)
6233 16:47:50.975528 ==
6234 16:47:50.978914 Dram Type= 6, Freq= 0, CH_0, rank 1
6235 16:47:50.981624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6236 16:47:50.982098 ==
6237 16:47:50.988345 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6238 16:47:50.995263 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6239 16:47:50.998097 [CA 0] Center 36 (8~64) winsize 57
6240 16:47:51.001515 [CA 1] Center 36 (8~64) winsize 57
6241 16:47:51.004966 [CA 2] Center 36 (8~64) winsize 57
6242 16:47:51.005532 [CA 3] Center 36 (8~64) winsize 57
6243 16:47:51.007802 [CA 4] Center 36 (8~64) winsize 57
6244 16:47:51.011138 [CA 5] Center 36 (8~64) winsize 57
6245 16:47:51.011707
6246 16:47:51.015231 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6247 16:47:51.017737
6248 16:47:51.021085 [CATrainingPosCal] consider 2 rank data
6249 16:47:51.024391 u2DelayCellTimex100 = 270/100 ps
6250 16:47:51.027692 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 16:47:51.031171 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 16:47:51.034035 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 16:47:51.037301 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 16:47:51.040957 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 16:47:51.044298 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 16:47:51.044863
6257 16:47:51.047797 CA PerBit enable=1, Macro0, CA PI delay=36
6258 16:47:51.048363
6259 16:47:51.050720 [CBTSetCACLKResult] CA Dly = 36
6260 16:47:51.054321 CS Dly: 1 (0~32)
6261 16:47:51.054914
6262 16:47:51.057119 ----->DramcWriteLeveling(PI) begin...
6263 16:47:51.057601 ==
6264 16:47:51.060666 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 16:47:51.064029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 16:47:51.064511 ==
6267 16:47:51.067245 Write leveling (Byte 0): 40 => 8
6268 16:47:51.071274 Write leveling (Byte 1): 32 => 0
6269 16:47:51.073923 DramcWriteLeveling(PI) end<-----
6270 16:47:51.074520
6271 16:47:51.074892 ==
6272 16:47:51.077494 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 16:47:51.080725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 16:47:51.081338 ==
6275 16:47:51.084077 [Gating] SW mode calibration
6276 16:47:51.090526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6277 16:47:51.097024 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6278 16:47:51.100315 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 16:47:51.104501 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 16:47:51.110655 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 16:47:51.113383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 16:47:51.117848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 16:47:51.124074 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 16:47:51.126544 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 16:47:51.130841 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 16:47:51.136564 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 16:47:51.140118 Total UI for P1: 0, mck2ui 16
6288 16:47:51.143318 best dqsien dly found for B0: ( 0, 14, 24)
6289 16:47:51.147356 Total UI for P1: 0, mck2ui 16
6290 16:47:51.150502 best dqsien dly found for B1: ( 0, 14, 24)
6291 16:47:51.153396 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6292 16:47:51.156633 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6293 16:47:51.157134
6294 16:47:51.160007 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 16:47:51.162939 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 16:47:51.166055 [Gating] SW calibration Done
6297 16:47:51.166532 ==
6298 16:47:51.169626 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 16:47:51.172773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 16:47:51.173229 ==
6301 16:47:51.176168 RX Vref Scan: 0
6302 16:47:51.176635
6303 16:47:51.179547 RX Vref 0 -> 0, step: 1
6304 16:47:51.179865
6305 16:47:51.180120 RX Delay -410 -> 252, step: 16
6306 16:47:51.186675 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6307 16:47:51.190313 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6308 16:47:51.193397 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6309 16:47:51.199889 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6310 16:47:51.203095 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6311 16:47:51.205860 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6312 16:47:51.209306 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6313 16:47:51.212670 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6314 16:47:51.219597 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6315 16:47:51.223148 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6316 16:47:51.226337 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6317 16:47:51.232892 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6318 16:47:51.235694 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6319 16:47:51.239168 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6320 16:47:51.242454 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6321 16:47:51.249206 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6322 16:47:51.249767 ==
6323 16:47:51.252376 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 16:47:51.255510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 16:47:51.255968 ==
6326 16:47:51.256328 DQS Delay:
6327 16:47:51.258804 DQS0 = 27, DQS1 = 43
6328 16:47:51.259254 DQM Delay:
6329 16:47:51.262251 DQM0 = 12, DQM1 = 12
6330 16:47:51.262848 DQ Delay:
6331 16:47:51.266042 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6332 16:47:51.269071 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6333 16:47:51.271967 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6334 16:47:51.275899 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6335 16:47:51.276453
6336 16:47:51.276810
6337 16:47:51.277140 ==
6338 16:47:51.278756 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 16:47:51.282044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 16:47:51.282627 ==
6341 16:47:51.282994
6342 16:47:51.285959
6343 16:47:51.286569 TX Vref Scan disable
6344 16:47:51.288850 == TX Byte 0 ==
6345 16:47:51.291950 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 16:47:51.295254 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 16:47:51.298695 == TX Byte 1 ==
6348 16:47:51.301893 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6349 16:47:51.305307 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6350 16:47:51.305853 ==
6351 16:47:51.308395 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 16:47:51.315230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 16:47:51.315777 ==
6354 16:47:51.316140
6355 16:47:51.316473
6356 16:47:51.316818 TX Vref Scan disable
6357 16:47:51.318545 == TX Byte 0 ==
6358 16:47:51.321892 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 16:47:51.325294 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 16:47:51.328594 == TX Byte 1 ==
6361 16:47:51.332306 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6362 16:47:51.334929 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6363 16:47:51.335383
6364 16:47:51.338524 [DATLAT]
6365 16:47:51.339075 Freq=400, CH0 RK0
6366 16:47:51.339438
6367 16:47:51.342239 DATLAT Default: 0xf
6368 16:47:51.342862 0, 0xFFFF, sum = 0
6369 16:47:51.344856 1, 0xFFFF, sum = 0
6370 16:47:51.345416 2, 0xFFFF, sum = 0
6371 16:47:51.348510 3, 0xFFFF, sum = 0
6372 16:47:51.349090 4, 0xFFFF, sum = 0
6373 16:47:51.351310 5, 0xFFFF, sum = 0
6374 16:47:51.351771 6, 0xFFFF, sum = 0
6375 16:47:51.354711 7, 0xFFFF, sum = 0
6376 16:47:51.355174 8, 0xFFFF, sum = 0
6377 16:47:51.357972 9, 0xFFFF, sum = 0
6378 16:47:51.361184 10, 0xFFFF, sum = 0
6379 16:47:51.361760 11, 0xFFFF, sum = 0
6380 16:47:51.364366 12, 0xFFFF, sum = 0
6381 16:47:51.364907 13, 0x0, sum = 1
6382 16:47:51.367682 14, 0x0, sum = 2
6383 16:47:51.368143 15, 0x0, sum = 3
6384 16:47:51.371078 16, 0x0, sum = 4
6385 16:47:51.371642 best_step = 14
6386 16:47:51.372005
6387 16:47:51.372338 ==
6388 16:47:51.374731 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 16:47:51.378005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 16:47:51.378606 ==
6391 16:47:51.381177 RX Vref Scan: 1
6392 16:47:51.381726
6393 16:47:51.385125 RX Vref 0 -> 0, step: 1
6394 16:47:51.385676
6395 16:47:51.386039 RX Delay -327 -> 252, step: 8
6396 16:47:51.386411
6397 16:47:51.387994 Set Vref, RX VrefLevel [Byte0]: 63
6398 16:47:51.392112 [Byte1]: 50
6399 16:47:51.396364
6400 16:47:51.396924 Final RX Vref Byte 0 = 63 to rank0
6401 16:47:51.399750 Final RX Vref Byte 1 = 50 to rank0
6402 16:47:51.403055 Final RX Vref Byte 0 = 63 to rank1
6403 16:47:51.406602 Final RX Vref Byte 1 = 50 to rank1==
6404 16:47:51.410401 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 16:47:51.415987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 16:47:51.416445 ==
6407 16:47:51.416805 DQS Delay:
6408 16:47:51.419906 DQS0 = 28, DQS1 = 48
6409 16:47:51.420359 DQM Delay:
6410 16:47:51.420715 DQM0 = 12, DQM1 = 15
6411 16:47:51.422698 DQ Delay:
6412 16:47:51.426245 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6413 16:47:51.429594 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6414 16:47:51.430159 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6415 16:47:51.432927 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6416 16:47:51.436463
6417 16:47:51.437027
6418 16:47:51.442649 [DQSOSCAuto] RK0, (LSB)MR18= 0xafa5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6419 16:47:51.445956 CH0 RK0: MR19=C0C, MR18=AFA5
6420 16:47:51.452740 CH0_RK0: MR19=0xC0C, MR18=0xAFA5, DQSOSC=388, MR23=63, INC=392, DEC=261
6421 16:47:51.453386 ==
6422 16:47:51.455636 Dram Type= 6, Freq= 0, CH_0, rank 1
6423 16:47:51.459018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 16:47:51.459488 ==
6425 16:47:51.462963 [Gating] SW mode calibration
6426 16:47:51.469710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6427 16:47:51.475820 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6428 16:47:51.479041 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 16:47:51.482972 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 16:47:51.489243 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 16:47:51.492623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 16:47:51.495774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 16:47:51.502017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 16:47:51.505623 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 16:47:51.508501 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 16:47:51.515336 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 16:47:51.515934 Total UI for P1: 0, mck2ui 16
6438 16:47:51.522050 best dqsien dly found for B0: ( 0, 14, 24)
6439 16:47:51.522673 Total UI for P1: 0, mck2ui 16
6440 16:47:51.528836 best dqsien dly found for B1: ( 0, 14, 24)
6441 16:47:51.532003 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6442 16:47:51.535200 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6443 16:47:51.535772
6444 16:47:51.538219 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 16:47:51.542140 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 16:47:51.545397 [Gating] SW calibration Done
6447 16:47:51.545968 ==
6448 16:47:51.548339 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 16:47:51.551758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 16:47:51.552335 ==
6451 16:47:51.554988 RX Vref Scan: 0
6452 16:47:51.555556
6453 16:47:51.555932 RX Vref 0 -> 0, step: 1
6454 16:47:51.557868
6455 16:47:51.558409 RX Delay -410 -> 252, step: 16
6456 16:47:51.564702 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6457 16:47:51.567819 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6458 16:47:51.571336 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6459 16:47:51.575210 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6460 16:47:51.581098 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6461 16:47:51.584593 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6462 16:47:51.587708 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6463 16:47:51.591187 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6464 16:47:51.597883 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6465 16:47:51.601057 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6466 16:47:51.604057 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6467 16:47:51.611000 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6468 16:47:51.614638 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6469 16:47:51.617691 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6470 16:47:51.621427 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6471 16:47:51.627245 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6472 16:47:51.627821 ==
6473 16:47:51.630795 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 16:47:51.634059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 16:47:51.634700 ==
6476 16:47:51.635084 DQS Delay:
6477 16:47:51.637017 DQS0 = 27, DQS1 = 43
6478 16:47:51.637479 DQM Delay:
6479 16:47:51.641144 DQM0 = 10, DQM1 = 16
6480 16:47:51.641719 DQ Delay:
6481 16:47:51.644729 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6482 16:47:51.647205 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6483 16:47:51.650703 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6484 16:47:51.654174 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6485 16:47:51.654799
6486 16:47:51.655175
6487 16:47:51.655520 ==
6488 16:47:51.656856 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 16:47:51.660475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 16:47:51.661050 ==
6491 16:47:51.661426
6492 16:47:51.663650
6493 16:47:51.664216 TX Vref Scan disable
6494 16:47:51.666896 == TX Byte 0 ==
6495 16:47:51.670960 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6496 16:47:51.673460 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6497 16:47:51.677033 == TX Byte 1 ==
6498 16:47:51.680037 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6499 16:47:51.683373 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6500 16:47:51.683941 ==
6501 16:47:51.686561 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 16:47:51.690406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 16:47:51.693519 ==
6504 16:47:51.694087
6505 16:47:51.694503
6506 16:47:51.694854 TX Vref Scan disable
6507 16:47:51.696619 == TX Byte 0 ==
6508 16:47:51.700377 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6509 16:47:51.703452 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6510 16:47:51.706566 == TX Byte 1 ==
6511 16:47:51.710123 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6512 16:47:51.713373 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6513 16:47:51.713946
6514 16:47:51.714318 [DATLAT]
6515 16:47:51.716233 Freq=400, CH0 RK1
6516 16:47:51.716700
6517 16:47:51.720025 DATLAT Default: 0xe
6518 16:47:51.720596 0, 0xFFFF, sum = 0
6519 16:47:51.722993 1, 0xFFFF, sum = 0
6520 16:47:51.723465 2, 0xFFFF, sum = 0
6521 16:47:51.726638 3, 0xFFFF, sum = 0
6522 16:47:51.727214 4, 0xFFFF, sum = 0
6523 16:47:51.729907 5, 0xFFFF, sum = 0
6524 16:47:51.730523 6, 0xFFFF, sum = 0
6525 16:47:51.733277 7, 0xFFFF, sum = 0
6526 16:47:51.733868 8, 0xFFFF, sum = 0
6527 16:47:51.736989 9, 0xFFFF, sum = 0
6528 16:47:51.737571 10, 0xFFFF, sum = 0
6529 16:47:51.739753 11, 0xFFFF, sum = 0
6530 16:47:51.740336 12, 0xFFFF, sum = 0
6531 16:47:51.743128 13, 0x0, sum = 1
6532 16:47:51.743714 14, 0x0, sum = 2
6533 16:47:51.746149 15, 0x0, sum = 3
6534 16:47:51.746773 16, 0x0, sum = 4
6535 16:47:51.749463 best_step = 14
6536 16:47:51.750033
6537 16:47:51.750433 ==
6538 16:47:51.753254 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 16:47:51.756287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 16:47:51.756864 ==
6541 16:47:51.759336 RX Vref Scan: 0
6542 16:47:51.759801
6543 16:47:51.760173 RX Vref 0 -> 0, step: 1
6544 16:47:51.760514
6545 16:47:51.763244 RX Delay -327 -> 252, step: 8
6546 16:47:51.771224 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6547 16:47:51.774711 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6548 16:47:51.777770 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6549 16:47:51.784054 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6550 16:47:51.787091 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6551 16:47:51.790885 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6552 16:47:51.793962 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6553 16:47:51.800093 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6554 16:47:51.803992 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6555 16:47:51.807002 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6556 16:47:51.810175 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6557 16:47:51.816902 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6558 16:47:51.820238 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6559 16:47:51.823148 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6560 16:47:51.826659 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6561 16:47:51.833537 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6562 16:47:51.834111 ==
6563 16:47:51.836786 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 16:47:51.840663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 16:47:51.841239 ==
6566 16:47:51.841618 DQS Delay:
6567 16:47:51.843594 DQS0 = 28, DQS1 = 40
6568 16:47:51.844060 DQM Delay:
6569 16:47:51.847277 DQM0 = 9, DQM1 = 11
6570 16:47:51.847849 DQ Delay:
6571 16:47:51.850264 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6572 16:47:51.853867 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6573 16:47:51.856846 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6574 16:47:51.859790 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6575 16:47:51.860261
6576 16:47:51.860633
6577 16:47:51.867375 [DQSOSCAuto] RK1, (LSB)MR18= 0xb569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6578 16:47:51.870118 CH0 RK1: MR19=C0C, MR18=B569
6579 16:47:51.876800 CH0_RK1: MR19=0xC0C, MR18=0xB569, DQSOSC=387, MR23=63, INC=394, DEC=262
6580 16:47:51.879816 [RxdqsGatingPostProcess] freq 400
6581 16:47:51.886621 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6582 16:47:51.891580 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 16:47:51.892878 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 16:47:51.896568 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 16:47:51.900274 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 16:47:51.900743 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 16:47:51.902643 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 16:47:51.905866 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 16:47:51.909935 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 16:47:51.913516 Pre-setting of DQS Precalculation
6591 16:47:51.919191 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6592 16:47:51.919665 ==
6593 16:47:51.922457 Dram Type= 6, Freq= 0, CH_1, rank 0
6594 16:47:51.926156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 16:47:51.926779 ==
6596 16:47:51.932740 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6597 16:47:51.938844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6598 16:47:51.942311 [CA 0] Center 36 (8~64) winsize 57
6599 16:47:51.945834 [CA 1] Center 36 (8~64) winsize 57
6600 16:47:51.946433 [CA 2] Center 36 (8~64) winsize 57
6601 16:47:51.949000 [CA 3] Center 36 (8~64) winsize 57
6602 16:47:51.952507 [CA 4] Center 36 (8~64) winsize 57
6603 16:47:51.955798 [CA 5] Center 36 (8~64) winsize 57
6604 16:47:51.956363
6605 16:47:51.958526 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6606 16:47:51.962457
6607 16:47:51.965557 [CATrainingPosCal] consider 1 rank data
6608 16:47:51.966129 u2DelayCellTimex100 = 270/100 ps
6609 16:47:51.972044 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 16:47:51.975493 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 16:47:51.978539 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 16:47:51.981862 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 16:47:51.985482 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 16:47:51.988521 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 16:47:51.989085
6616 16:47:51.991692 CA PerBit enable=1, Macro0, CA PI delay=36
6617 16:47:51.992161
6618 16:47:51.995407 [CBTSetCACLKResult] CA Dly = 36
6619 16:47:51.998170 CS Dly: 1 (0~32)
6620 16:47:51.998763 ==
6621 16:47:52.001278 Dram Type= 6, Freq= 0, CH_1, rank 1
6622 16:47:52.005046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 16:47:52.005621 ==
6624 16:47:52.011994 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6625 16:47:52.015249 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6626 16:47:52.018460 [CA 0] Center 36 (8~64) winsize 57
6627 16:47:52.021755 [CA 1] Center 36 (8~64) winsize 57
6628 16:47:52.025256 [CA 2] Center 36 (8~64) winsize 57
6629 16:47:52.028504 [CA 3] Center 36 (8~64) winsize 57
6630 16:47:52.031468 [CA 4] Center 36 (8~64) winsize 57
6631 16:47:52.034424 [CA 5] Center 36 (8~64) winsize 57
6632 16:47:52.034891
6633 16:47:52.037942 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6634 16:47:52.038561
6635 16:47:52.041187 [CATrainingPosCal] consider 2 rank data
6636 16:47:52.044735 u2DelayCellTimex100 = 270/100 ps
6637 16:47:52.047983 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 16:47:52.054976 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 16:47:52.057715 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 16:47:52.061616 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 16:47:52.064402 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 16:47:52.067920 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 16:47:52.068497
6644 16:47:52.070877 CA PerBit enable=1, Macro0, CA PI delay=36
6645 16:47:52.071351
6646 16:47:52.074802 [CBTSetCACLKResult] CA Dly = 36
6647 16:47:52.075380 CS Dly: 1 (0~32)
6648 16:47:52.077770
6649 16:47:52.081488 ----->DramcWriteLeveling(PI) begin...
6650 16:47:52.082074 ==
6651 16:47:52.084359 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 16:47:52.088341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 16:47:52.088944 ==
6654 16:47:52.091054 Write leveling (Byte 0): 40 => 8
6655 16:47:52.094397 Write leveling (Byte 1): 32 => 0
6656 16:47:52.098100 DramcWriteLeveling(PI) end<-----
6657 16:47:52.098737
6658 16:47:52.099117 ==
6659 16:47:52.101594 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 16:47:52.104784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 16:47:52.105366 ==
6662 16:47:52.107796 [Gating] SW mode calibration
6663 16:47:52.114674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6664 16:47:52.120586 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6665 16:47:52.124192 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 16:47:52.127259 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 16:47:52.134106 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 16:47:52.137669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 16:47:52.140253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 16:47:52.147017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 16:47:52.150652 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 16:47:52.154180 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 16:47:52.160084 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 16:47:52.160638 Total UI for P1: 0, mck2ui 16
6675 16:47:52.167224 best dqsien dly found for B0: ( 0, 14, 24)
6676 16:47:52.167789 Total UI for P1: 0, mck2ui 16
6677 16:47:52.173588 best dqsien dly found for B1: ( 0, 14, 24)
6678 16:47:52.176936 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6679 16:47:52.180061 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6680 16:47:52.180529
6681 16:47:52.183558 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 16:47:52.187033 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 16:47:52.190977 [Gating] SW calibration Done
6684 16:47:52.191543 ==
6685 16:47:52.192779 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 16:47:52.196655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 16:47:52.197228 ==
6688 16:47:52.200015 RX Vref Scan: 0
6689 16:47:52.200579
6690 16:47:52.200956 RX Vref 0 -> 0, step: 1
6691 16:47:52.203014
6692 16:47:52.203479 RX Delay -410 -> 252, step: 16
6693 16:47:52.209654 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6694 16:47:52.213438 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6695 16:47:52.216512 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6696 16:47:52.219675 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6697 16:47:52.225718 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6698 16:47:52.229146 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6699 16:47:52.232570 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6700 16:47:52.238944 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6701 16:47:52.242621 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6702 16:47:52.245644 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6703 16:47:52.249250 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6704 16:47:52.255405 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6705 16:47:52.258894 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6706 16:47:52.262286 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6707 16:47:52.265850 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6708 16:47:52.272173 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6709 16:47:52.272738 ==
6710 16:47:52.275839 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 16:47:52.278920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 16:47:52.279487 ==
6713 16:47:52.279867 DQS Delay:
6714 16:47:52.282293 DQS0 = 27, DQS1 = 43
6715 16:47:52.282898 DQM Delay:
6716 16:47:52.285792 DQM0 = 8, DQM1 = 16
6717 16:47:52.286387 DQ Delay:
6718 16:47:52.288620 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6719 16:47:52.292025 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6720 16:47:52.295294 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6721 16:47:52.298765 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6722 16:47:52.299335
6723 16:47:52.299710
6724 16:47:52.300053 ==
6725 16:47:52.301615 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 16:47:52.304944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 16:47:52.305417 ==
6728 16:47:52.305788
6729 16:47:52.308606
6730 16:47:52.309166 TX Vref Scan disable
6731 16:47:52.312044 == TX Byte 0 ==
6732 16:47:52.315915 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 16:47:52.318461 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 16:47:52.321403 == TX Byte 1 ==
6735 16:47:52.324972 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6736 16:47:52.328369 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6737 16:47:52.328939 ==
6738 16:47:52.331774 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 16:47:52.338093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 16:47:52.338667 ==
6741 16:47:52.339085
6742 16:47:52.339436
6743 16:47:52.339776 TX Vref Scan disable
6744 16:47:52.341162 == TX Byte 0 ==
6745 16:47:52.344236 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 16:47:52.347713 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 16:47:52.351720 == TX Byte 1 ==
6748 16:47:52.354602 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6749 16:47:52.357635 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6750 16:47:52.358100
6751 16:47:52.360890 [DATLAT]
6752 16:47:52.361355 Freq=400, CH1 RK0
6753 16:47:52.361728
6754 16:47:52.364788 DATLAT Default: 0xf
6755 16:47:52.365354 0, 0xFFFF, sum = 0
6756 16:47:52.367859 1, 0xFFFF, sum = 0
6757 16:47:52.368333 2, 0xFFFF, sum = 0
6758 16:47:52.370766 3, 0xFFFF, sum = 0
6759 16:47:52.371240 4, 0xFFFF, sum = 0
6760 16:47:52.374288 5, 0xFFFF, sum = 0
6761 16:47:52.374795 6, 0xFFFF, sum = 0
6762 16:47:52.377352 7, 0xFFFF, sum = 0
6763 16:47:52.377827 8, 0xFFFF, sum = 0
6764 16:47:52.381139 9, 0xFFFF, sum = 0
6765 16:47:52.384472 10, 0xFFFF, sum = 0
6766 16:47:52.385041 11, 0xFFFF, sum = 0
6767 16:47:52.387694 12, 0xFFFF, sum = 0
6768 16:47:52.388263 13, 0x0, sum = 1
6769 16:47:52.390833 14, 0x0, sum = 2
6770 16:47:52.391308 15, 0x0, sum = 3
6771 16:47:52.391687 16, 0x0, sum = 4
6772 16:47:52.393890 best_step = 14
6773 16:47:52.394383
6774 16:47:52.394760 ==
6775 16:47:52.397446 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 16:47:52.401106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 16:47:52.401671 ==
6778 16:47:52.404464 RX Vref Scan: 1
6779 16:47:52.405025
6780 16:47:52.407776 RX Vref 0 -> 0, step: 1
6781 16:47:52.408343
6782 16:47:52.408723 RX Delay -327 -> 252, step: 8
6783 16:47:52.409073
6784 16:47:52.410448 Set Vref, RX VrefLevel [Byte0]: 54
6785 16:47:52.413983 [Byte1]: 57
6786 16:47:52.419913
6787 16:47:52.420518 Final RX Vref Byte 0 = 54 to rank0
6788 16:47:52.422468 Final RX Vref Byte 1 = 57 to rank0
6789 16:47:52.426535 Final RX Vref Byte 0 = 54 to rank1
6790 16:47:52.429322 Final RX Vref Byte 1 = 57 to rank1==
6791 16:47:52.432660 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 16:47:52.438918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 16:47:52.439479 ==
6794 16:47:52.439859 DQS Delay:
6795 16:47:52.442213 DQS0 = 28, DQS1 = 40
6796 16:47:52.442716 DQM Delay:
6797 16:47:52.443088 DQM0 = 8, DQM1 = 12
6798 16:47:52.445631 DQ Delay:
6799 16:47:52.448865 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6800 16:47:52.449441 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6801 16:47:52.452183 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6802 16:47:52.455283 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6803 16:47:52.455750
6804 16:47:52.458819
6805 16:47:52.465706 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6806 16:47:52.469344 CH1 RK0: MR19=C0C, MR18=93CD
6807 16:47:52.475258 CH1_RK0: MR19=0xC0C, MR18=0x93CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6808 16:47:52.475876 ==
6809 16:47:52.478279 Dram Type= 6, Freq= 0, CH_1, rank 1
6810 16:47:52.481975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 16:47:52.482584 ==
6812 16:47:52.485355 [Gating] SW mode calibration
6813 16:47:52.491973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6814 16:47:52.498672 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6815 16:47:52.501779 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 16:47:52.505064 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6817 16:47:52.511986 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 16:47:52.515003 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 16:47:52.518635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 16:47:52.525029 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 16:47:52.528408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 16:47:52.531453 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 16:47:52.538803 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 16:47:52.539424 Total UI for P1: 0, mck2ui 16
6825 16:47:52.545121 best dqsien dly found for B0: ( 0, 14, 24)
6826 16:47:52.545685 Total UI for P1: 0, mck2ui 16
6827 16:47:52.548271 best dqsien dly found for B1: ( 0, 14, 24)
6828 16:47:52.555075 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6829 16:47:52.558084 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6830 16:47:52.558687
6831 16:47:52.561354 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 16:47:52.564955 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 16:47:52.568627 [Gating] SW calibration Done
6834 16:47:52.569186 ==
6835 16:47:52.571423 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 16:47:52.575111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 16:47:52.575681 ==
6838 16:47:52.577914 RX Vref Scan: 0
6839 16:47:52.578518
6840 16:47:52.578899 RX Vref 0 -> 0, step: 1
6841 16:47:52.579249
6842 16:47:52.581455 RX Delay -410 -> 252, step: 16
6843 16:47:52.588038 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6844 16:47:52.591611 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6845 16:47:52.595057 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6846 16:47:52.598580 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6847 16:47:52.604972 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6848 16:47:52.608120 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6849 16:47:52.611127 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6850 16:47:52.614753 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6851 16:47:52.617505 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6852 16:47:52.624576 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6853 16:47:52.628000 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6854 16:47:52.630874 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6855 16:47:52.637648 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6856 16:47:52.641101 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6857 16:47:52.644420 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6858 16:47:52.647891 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6859 16:47:52.651445 ==
6860 16:47:52.651915 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 16:47:52.657466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 16:47:52.657940 ==
6863 16:47:52.658317 DQS Delay:
6864 16:47:52.660743 DQS0 = 35, DQS1 = 43
6865 16:47:52.661212 DQM Delay:
6866 16:47:52.664821 DQM0 = 17, DQM1 = 18
6867 16:47:52.665389 DQ Delay:
6868 16:47:52.667403 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6869 16:47:52.670858 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6870 16:47:52.674078 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6871 16:47:52.677020 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6872 16:47:52.677490
6873 16:47:52.677862
6874 16:47:52.678208 ==
6875 16:47:52.680652 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 16:47:52.684352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 16:47:52.684954 ==
6878 16:47:52.685339
6879 16:47:52.685688
6880 16:47:52.687048 TX Vref Scan disable
6881 16:47:52.687518 == TX Byte 0 ==
6882 16:47:52.693751 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6883 16:47:52.697300 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6884 16:47:52.697866 == TX Byte 1 ==
6885 16:47:52.703924 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6886 16:47:52.708690 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6887 16:47:52.709260 ==
6888 16:47:52.709992 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 16:47:52.714246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 16:47:52.714982 ==
6891 16:47:52.715374
6892 16:47:52.715726
6893 16:47:52.717762 TX Vref Scan disable
6894 16:47:52.720045 == TX Byte 0 ==
6895 16:47:52.723667 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6896 16:47:52.726510 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6897 16:47:52.730098 == TX Byte 1 ==
6898 16:47:52.733485 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6899 16:47:52.736943 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6900 16:47:52.737509
6901 16:47:52.737878 [DATLAT]
6902 16:47:52.740111 Freq=400, CH1 RK1
6903 16:47:52.740576
6904 16:47:52.740944 DATLAT Default: 0xe
6905 16:47:52.743189 0, 0xFFFF, sum = 0
6906 16:47:52.743659 1, 0xFFFF, sum = 0
6907 16:47:52.746945 2, 0xFFFF, sum = 0
6908 16:47:52.747514 3, 0xFFFF, sum = 0
6909 16:47:52.749858 4, 0xFFFF, sum = 0
6910 16:47:52.753758 5, 0xFFFF, sum = 0
6911 16:47:52.754333 6, 0xFFFF, sum = 0
6912 16:47:52.757405 7, 0xFFFF, sum = 0
6913 16:47:52.757975 8, 0xFFFF, sum = 0
6914 16:47:52.760069 9, 0xFFFF, sum = 0
6915 16:47:52.760619 10, 0xFFFF, sum = 0
6916 16:47:52.762871 11, 0xFFFF, sum = 0
6917 16:47:52.763364 12, 0xFFFF, sum = 0
6918 16:47:52.766569 13, 0x0, sum = 1
6919 16:47:52.767225 14, 0x0, sum = 2
6920 16:47:52.769480 15, 0x0, sum = 3
6921 16:47:52.769949 16, 0x0, sum = 4
6922 16:47:52.772875 best_step = 14
6923 16:47:52.773365
6924 16:47:52.773733 ==
6925 16:47:52.776092 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 16:47:52.779466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 16:47:52.779933 ==
6928 16:47:52.780303 RX Vref Scan: 0
6929 16:47:52.783084
6930 16:47:52.783645 RX Vref 0 -> 0, step: 1
6931 16:47:52.784022
6932 16:47:52.786048 RX Delay -327 -> 252, step: 8
6933 16:47:52.793383 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6934 16:47:52.796847 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6935 16:47:52.800348 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6936 16:47:52.803502 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6937 16:47:52.810623 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6938 16:47:52.814331 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6939 16:47:52.816865 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6940 16:47:52.823662 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6941 16:47:52.827024 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6942 16:47:52.830579 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6943 16:47:52.833424 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6944 16:47:52.839789 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6945 16:47:52.843126 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
6946 16:47:52.846431 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6947 16:47:52.849668 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6948 16:47:52.856335 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6949 16:47:52.856925 ==
6950 16:47:52.859132 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 16:47:52.862618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 16:47:52.863101 ==
6953 16:47:52.863641 DQS Delay:
6954 16:47:52.866101 DQS0 = 32, DQS1 = 36
6955 16:47:52.866710 DQM Delay:
6956 16:47:52.869054 DQM0 = 13, DQM1 = 11
6957 16:47:52.869530 DQ Delay:
6958 16:47:52.872398 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6959 16:47:52.876059 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6960 16:47:52.879016 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6961 16:47:52.882266 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6962 16:47:52.882863
6963 16:47:52.883242
6964 16:47:52.892108 [DQSOSCAuto] RK1, (LSB)MR18= 0xab54, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6965 16:47:52.892675 CH1 RK1: MR19=C0C, MR18=AB54
6966 16:47:52.899378 CH1_RK1: MR19=0xC0C, MR18=0xAB54, DQSOSC=388, MR23=63, INC=392, DEC=261
6967 16:47:52.902514 [RxdqsGatingPostProcess] freq 400
6968 16:47:52.908893 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6969 16:47:52.912478 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 16:47:52.915783 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 16:47:52.919013 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 16:47:52.922622 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 16:47:52.925245 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 16:47:52.925715 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 16:47:52.928980 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 16:47:52.932305 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 16:47:52.935444 Pre-setting of DQS Precalculation
6978 16:47:52.942328 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6979 16:47:52.948677 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6980 16:47:52.954807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6981 16:47:52.955371
6982 16:47:52.955743
6983 16:47:52.958153 [Calibration Summary] 800 Mbps
6984 16:47:52.961511 CH 0, Rank 0
6985 16:47:52.961983 SW Impedance : PASS
6986 16:47:52.965242 DUTY Scan : NO K
6987 16:47:52.968020 ZQ Calibration : PASS
6988 16:47:52.968486 Jitter Meter : NO K
6989 16:47:52.971217 CBT Training : PASS
6990 16:47:52.974788 Write leveling : PASS
6991 16:47:52.975380 RX DQS gating : PASS
6992 16:47:52.978282 RX DQ/DQS(RDDQC) : PASS
6993 16:47:52.978982 TX DQ/DQS : PASS
6994 16:47:52.981124 RX DATLAT : PASS
6995 16:47:52.984985 RX DQ/DQS(Engine): PASS
6996 16:47:52.985554 TX OE : NO K
6997 16:47:52.988178 All Pass.
6998 16:47:52.988646
6999 16:47:52.989016 CH 0, Rank 1
7000 16:47:52.991183 SW Impedance : PASS
7001 16:47:52.991657 DUTY Scan : NO K
7002 16:47:52.994321 ZQ Calibration : PASS
7003 16:47:52.997775 Jitter Meter : NO K
7004 16:47:52.998344 CBT Training : PASS
7005 16:47:53.000980 Write leveling : NO K
7006 16:47:53.004099 RX DQS gating : PASS
7007 16:47:53.004570 RX DQ/DQS(RDDQC) : PASS
7008 16:47:53.007481 TX DQ/DQS : PASS
7009 16:47:53.011257 RX DATLAT : PASS
7010 16:47:53.011727 RX DQ/DQS(Engine): PASS
7011 16:47:53.014901 TX OE : NO K
7012 16:47:53.015370 All Pass.
7013 16:47:53.015747
7014 16:47:53.017443 CH 1, Rank 0
7015 16:47:53.018017 SW Impedance : PASS
7016 16:47:53.020753 DUTY Scan : NO K
7017 16:47:53.023961 ZQ Calibration : PASS
7018 16:47:53.024636 Jitter Meter : NO K
7019 16:47:53.027170 CBT Training : PASS
7020 16:47:53.031274 Write leveling : PASS
7021 16:47:53.031863 RX DQS gating : PASS
7022 16:47:53.033795 RX DQ/DQS(RDDQC) : PASS
7023 16:47:53.037307 TX DQ/DQS : PASS
7024 16:47:53.037896 RX DATLAT : PASS
7025 16:47:53.040708 RX DQ/DQS(Engine): PASS
7026 16:47:53.044568 TX OE : NO K
7027 16:47:53.045161 All Pass.
7028 16:47:53.045655
7029 16:47:53.046110 CH 1, Rank 1
7030 16:47:53.047133 SW Impedance : PASS
7031 16:47:53.050481 DUTY Scan : NO K
7032 16:47:53.051059 ZQ Calibration : PASS
7033 16:47:53.053875 Jitter Meter : NO K
7034 16:47:53.057225 CBT Training : PASS
7035 16:47:53.057811 Write leveling : NO K
7036 16:47:53.060154 RX DQS gating : PASS
7037 16:47:53.063405 RX DQ/DQS(RDDQC) : PASS
7038 16:47:53.063994 TX DQ/DQS : PASS
7039 16:47:53.067004 RX DATLAT : PASS
7040 16:47:53.067589 RX DQ/DQS(Engine): PASS
7041 16:47:53.070296 TX OE : NO K
7042 16:47:53.070925 All Pass.
7043 16:47:53.071412
7044 16:47:53.073598 DramC Write-DBI off
7045 16:47:53.077980 PER_BANK_REFRESH: Hybrid Mode
7046 16:47:53.078631 TX_TRACKING: ON
7047 16:47:53.086953 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7048 16:47:53.089809 [FAST_K] Save calibration result to emmc
7049 16:47:53.093648 dramc_set_vcore_voltage set vcore to 725000
7050 16:47:53.096576 Read voltage for 1600, 0
7051 16:47:53.097161 Vio18 = 0
7052 16:47:53.099888 Vcore = 725000
7053 16:47:53.100370 Vdram = 0
7054 16:47:53.100854 Vddq = 0
7055 16:47:53.101308 Vmddr = 0
7056 16:47:53.107060 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7057 16:47:53.113644 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7058 16:47:53.114222 MEM_TYPE=3, freq_sel=13
7059 16:47:53.116798 sv_algorithm_assistance_LP4_3733
7060 16:47:53.119759 ============ PULL DRAM RESETB DOWN ============
7061 16:47:53.126161 ========== PULL DRAM RESETB DOWN end =========
7062 16:47:53.129718 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7063 16:47:53.133104 ===================================
7064 16:47:53.136364 LPDDR4 DRAM CONFIGURATION
7065 16:47:53.139767 ===================================
7066 16:47:53.140241 EX_ROW_EN[0] = 0x0
7067 16:47:53.142645 EX_ROW_EN[1] = 0x0
7068 16:47:53.143115 LP4Y_EN = 0x0
7069 16:47:53.146146 WORK_FSP = 0x1
7070 16:47:53.149736 WL = 0x5
7071 16:47:53.150314 RL = 0x5
7072 16:47:53.153205 BL = 0x2
7073 16:47:53.153785 RPST = 0x0
7074 16:47:53.156299 RD_PRE = 0x0
7075 16:47:53.156771 WR_PRE = 0x1
7076 16:47:53.159480 WR_PST = 0x1
7077 16:47:53.160058 DBI_WR = 0x0
7078 16:47:53.162850 DBI_RD = 0x0
7079 16:47:53.163337 OTF = 0x1
7080 16:47:53.166244 ===================================
7081 16:47:53.169667 ===================================
7082 16:47:53.173009 ANA top config
7083 16:47:53.176205 ===================================
7084 16:47:53.176781 DLL_ASYNC_EN = 0
7085 16:47:53.179183 ALL_SLAVE_EN = 0
7086 16:47:53.182713 NEW_RANK_MODE = 1
7087 16:47:53.186082 DLL_IDLE_MODE = 1
7088 16:47:53.189421 LP45_APHY_COMB_EN = 1
7089 16:47:53.189999 TX_ODT_DIS = 0
7090 16:47:53.192160 NEW_8X_MODE = 1
7091 16:47:53.195675 ===================================
7092 16:47:53.199025 ===================================
7093 16:47:53.202295 data_rate = 3200
7094 16:47:53.205884 CKR = 1
7095 16:47:53.209320 DQ_P2S_RATIO = 8
7096 16:47:53.212786 ===================================
7097 16:47:53.215399 CA_P2S_RATIO = 8
7098 16:47:53.215873 DQ_CA_OPEN = 0
7099 16:47:53.218896 DQ_SEMI_OPEN = 0
7100 16:47:53.221807 CA_SEMI_OPEN = 0
7101 16:47:53.225210 CA_FULL_RATE = 0
7102 16:47:53.228629 DQ_CKDIV4_EN = 0
7103 16:47:53.232106 CA_CKDIV4_EN = 0
7104 16:47:53.232679 CA_PREDIV_EN = 0
7105 16:47:53.235174 PH8_DLY = 12
7106 16:47:53.238790 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7107 16:47:53.242405 DQ_AAMCK_DIV = 4
7108 16:47:53.244997 CA_AAMCK_DIV = 4
7109 16:47:53.248993 CA_ADMCK_DIV = 4
7110 16:47:53.249565 DQ_TRACK_CA_EN = 0
7111 16:47:53.252443 CA_PICK = 1600
7112 16:47:53.255397 CA_MCKIO = 1600
7113 16:47:53.258496 MCKIO_SEMI = 0
7114 16:47:53.261712 PLL_FREQ = 3068
7115 16:47:53.265035 DQ_UI_PI_RATIO = 32
7116 16:47:53.268428 CA_UI_PI_RATIO = 0
7117 16:47:53.272163 ===================================
7118 16:47:53.275262 ===================================
7119 16:47:53.275839 memory_type:LPDDR4
7120 16:47:53.277938 GP_NUM : 10
7121 16:47:53.281659 SRAM_EN : 1
7122 16:47:53.282232 MD32_EN : 0
7123 16:47:53.285035 ===================================
7124 16:47:53.288216 [ANA_INIT] >>>>>>>>>>>>>>
7125 16:47:53.291503 <<<<<< [CONFIGURE PHASE]: ANA_TX
7126 16:47:53.294953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7127 16:47:53.298383 ===================================
7128 16:47:53.301129 data_rate = 3200,PCW = 0X7600
7129 16:47:53.304493 ===================================
7130 16:47:53.308284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7131 16:47:53.311355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 16:47:53.318465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 16:47:53.321110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7134 16:47:53.324584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7135 16:47:53.327998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7136 16:47:53.330993 [ANA_INIT] flow start
7137 16:47:53.334471 [ANA_INIT] PLL >>>>>>>>
7138 16:47:53.335039 [ANA_INIT] PLL <<<<<<<<
7139 16:47:53.337834 [ANA_INIT] MIDPI >>>>>>>>
7140 16:47:53.341190 [ANA_INIT] MIDPI <<<<<<<<
7141 16:47:53.344337 [ANA_INIT] DLL >>>>>>>>
7142 16:47:53.344914 [ANA_INIT] DLL <<<<<<<<
7143 16:47:53.348647 [ANA_INIT] flow end
7144 16:47:53.350750 ============ LP4 DIFF to SE enter ============
7145 16:47:53.354348 ============ LP4 DIFF to SE exit ============
7146 16:47:53.357889 [ANA_INIT] <<<<<<<<<<<<<
7147 16:47:53.361492 [Flow] Enable top DCM control >>>>>
7148 16:47:53.364673 [Flow] Enable top DCM control <<<<<
7149 16:47:53.367601 Enable DLL master slave shuffle
7150 16:47:53.373972 ==============================================================
7151 16:47:53.374588 Gating Mode config
7152 16:47:53.381032 ==============================================================
7153 16:47:53.381619 Config description:
7154 16:47:53.390863 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7155 16:47:53.397342 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7156 16:47:53.404513 SELPH_MODE 0: By rank 1: By Phase
7157 16:47:53.407274 ==============================================================
7158 16:47:53.410501 GAT_TRACK_EN = 1
7159 16:47:53.413993 RX_GATING_MODE = 2
7160 16:47:53.417560 RX_GATING_TRACK_MODE = 2
7161 16:47:53.420532 SELPH_MODE = 1
7162 16:47:53.423611 PICG_EARLY_EN = 1
7163 16:47:53.426969 VALID_LAT_VALUE = 1
7164 16:47:53.433442 ==============================================================
7165 16:47:53.436967 Enter into Gating configuration >>>>
7166 16:47:53.440427 Exit from Gating configuration <<<<
7167 16:47:53.444076 Enter into DVFS_PRE_config >>>>>
7168 16:47:53.453974 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7169 16:47:53.456915 Exit from DVFS_PRE_config <<<<<
7170 16:47:53.460364 Enter into PICG configuration >>>>
7171 16:47:53.463563 Exit from PICG configuration <<<<
7172 16:47:53.466515 [RX_INPUT] configuration >>>>>
7173 16:47:53.467094 [RX_INPUT] configuration <<<<<
7174 16:47:53.473493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7175 16:47:53.479969 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7176 16:47:53.486804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 16:47:53.489726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 16:47:53.496835 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 16:47:53.503452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 16:47:53.506739 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7181 16:47:53.509942 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7182 16:47:53.516387 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7183 16:47:53.519324 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7184 16:47:53.522600 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7185 16:47:53.529797 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 16:47:53.532611 ===================================
7187 16:47:53.533076 LPDDR4 DRAM CONFIGURATION
7188 16:47:53.536244 ===================================
7189 16:47:53.539523 EX_ROW_EN[0] = 0x0
7190 16:47:53.542543 EX_ROW_EN[1] = 0x0
7191 16:47:53.543014 LP4Y_EN = 0x0
7192 16:47:53.546524 WORK_FSP = 0x1
7193 16:47:53.547084 WL = 0x5
7194 16:47:53.549178 RL = 0x5
7195 16:47:53.549641 BL = 0x2
7196 16:47:53.552930 RPST = 0x0
7197 16:47:53.553495 RD_PRE = 0x0
7198 16:47:53.556427 WR_PRE = 0x1
7199 16:47:53.557000 WR_PST = 0x1
7200 16:47:53.559197 DBI_WR = 0x0
7201 16:47:53.559660 DBI_RD = 0x0
7202 16:47:53.562342 OTF = 0x1
7203 16:47:53.566506 ===================================
7204 16:47:53.569674 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7205 16:47:53.572565 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7206 16:47:53.578993 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 16:47:53.581964 ===================================
7208 16:47:53.582483 LPDDR4 DRAM CONFIGURATION
7209 16:47:53.585768 ===================================
7210 16:47:53.589440 EX_ROW_EN[0] = 0x10
7211 16:47:53.593230 EX_ROW_EN[1] = 0x0
7212 16:47:53.593835 LP4Y_EN = 0x0
7213 16:47:53.595416 WORK_FSP = 0x1
7214 16:47:53.595898 WL = 0x5
7215 16:47:53.599227 RL = 0x5
7216 16:47:53.599810 BL = 0x2
7217 16:47:53.602483 RPST = 0x0
7218 16:47:53.603065 RD_PRE = 0x0
7219 16:47:53.606027 WR_PRE = 0x1
7220 16:47:53.606649 WR_PST = 0x1
7221 16:47:53.609134 DBI_WR = 0x0
7222 16:47:53.609721 DBI_RD = 0x0
7223 16:47:53.612301 OTF = 0x1
7224 16:47:53.615709 ===================================
7225 16:47:53.622059 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7226 16:47:53.622711 ==
7227 16:47:53.625355 Dram Type= 6, Freq= 0, CH_0, rank 0
7228 16:47:53.628484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7229 16:47:53.628965 ==
7230 16:47:53.631985 [Duty_Offset_Calibration]
7231 16:47:53.632457 B0:2 B1:0 CA:1
7232 16:47:53.632835
7233 16:47:53.635173 [DutyScan_Calibration_Flow] k_type=0
7234 16:47:53.645388
7235 16:47:53.645959 ==CLK 0==
7236 16:47:53.648459 Final CLK duty delay cell = -4
7237 16:47:53.651545 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7238 16:47:53.655082 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7239 16:47:53.658178 [-4] AVG Duty = 4922%(X100)
7240 16:47:53.658831
7241 16:47:53.661619 CH0 CLK Duty spec in!! Max-Min= 156%
7242 16:47:53.664588 [DutyScan_Calibration_Flow] ====Done====
7243 16:47:53.665052
7244 16:47:53.668269 [DutyScan_Calibration_Flow] k_type=1
7245 16:47:53.684657
7246 16:47:53.685228 ==DQS 0 ==
7247 16:47:53.688046 Final DQS duty delay cell = 0
7248 16:47:53.691376 [0] MAX Duty = 5249%(X100), DQS PI = 32
7249 16:47:53.694188 [0] MIN Duty = 4969%(X100), DQS PI = 0
7250 16:47:53.697518 [0] AVG Duty = 5109%(X100)
7251 16:47:53.698085
7252 16:47:53.698517 ==DQS 1 ==
7253 16:47:53.701742 Final DQS duty delay cell = -4
7254 16:47:53.704310 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7255 16:47:53.707517 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7256 16:47:53.711248 [-4] AVG Duty = 5000%(X100)
7257 16:47:53.711814
7258 16:47:53.713991 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7259 16:47:53.714494
7260 16:47:53.717861 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7261 16:47:53.721027 [DutyScan_Calibration_Flow] ====Done====
7262 16:47:53.721643
7263 16:47:53.723809 [DutyScan_Calibration_Flow] k_type=3
7264 16:47:53.741035
7265 16:47:53.741596 ==DQM 0 ==
7266 16:47:53.744064 Final DQM duty delay cell = 0
7267 16:47:53.747210 [0] MAX Duty = 5124%(X100), DQS PI = 26
7268 16:47:53.750896 [0] MIN Duty = 4813%(X100), DQS PI = 50
7269 16:47:53.753870 [0] AVG Duty = 4968%(X100)
7270 16:47:53.754406
7271 16:47:53.754785 ==DQM 1 ==
7272 16:47:53.758069 Final DQM duty delay cell = -4
7273 16:47:53.760585 [-4] MAX Duty = 5031%(X100), DQS PI = 44
7274 16:47:53.763918 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7275 16:47:53.767684 [-4] AVG Duty = 4891%(X100)
7276 16:47:53.768252
7277 16:47:53.770960 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7278 16:47:53.771525
7279 16:47:53.774556 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7280 16:47:53.777626 [DutyScan_Calibration_Flow] ====Done====
7281 16:47:53.778241
7282 16:47:53.780763 [DutyScan_Calibration_Flow] k_type=2
7283 16:47:53.798680
7284 16:47:53.799246 ==DQ 0 ==
7285 16:47:53.801960 Final DQ duty delay cell = 0
7286 16:47:53.805605 [0] MAX Duty = 5156%(X100), DQS PI = 38
7287 16:47:53.808824 [0] MIN Duty = 5000%(X100), DQS PI = 16
7288 16:47:53.809404 [0] AVG Duty = 5078%(X100)
7289 16:47:53.811962
7290 16:47:53.812524 ==DQ 1 ==
7291 16:47:53.815234 Final DQ duty delay cell = 0
7292 16:47:53.818317 [0] MAX Duty = 4969%(X100), DQS PI = 42
7293 16:47:53.821510 [0] MIN Duty = 4875%(X100), DQS PI = 10
7294 16:47:53.821965 [0] AVG Duty = 4922%(X100)
7295 16:47:53.824635
7296 16:47:53.828813 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7297 16:47:53.829269
7298 16:47:53.831721 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7299 16:47:53.835627 [DutyScan_Calibration_Flow] ====Done====
7300 16:47:53.836078 ==
7301 16:47:53.838571 Dram Type= 6, Freq= 0, CH_1, rank 0
7302 16:47:53.841363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 16:47:53.841823 ==
7304 16:47:53.844766 [Duty_Offset_Calibration]
7305 16:47:53.845385 B0:0 B1:-1 CA:2
7306 16:47:53.845778
7307 16:47:53.848037 [DutyScan_Calibration_Flow] k_type=0
7308 16:47:53.858618
7309 16:47:53.859200 ==CLK 0==
7310 16:47:53.862073 Final CLK duty delay cell = 0
7311 16:47:53.865567 [0] MAX Duty = 5156%(X100), DQS PI = 10
7312 16:47:53.868589 [0] MIN Duty = 4938%(X100), DQS PI = 44
7313 16:47:53.871889 [0] AVG Duty = 5047%(X100)
7314 16:47:53.872449
7315 16:47:53.875166 CH1 CLK Duty spec in!! Max-Min= 218%
7316 16:47:53.878867 [DutyScan_Calibration_Flow] ====Done====
7317 16:47:53.879424
7318 16:47:53.881622 [DutyScan_Calibration_Flow] k_type=1
7319 16:47:53.898511
7320 16:47:53.899054 ==DQS 0 ==
7321 16:47:53.901699 Final DQS duty delay cell = 0
7322 16:47:53.905930 [0] MAX Duty = 5124%(X100), DQS PI = 26
7323 16:47:53.908480 [0] MIN Duty = 4969%(X100), DQS PI = 0
7324 16:47:53.909036 [0] AVG Duty = 5046%(X100)
7325 16:47:53.912042
7326 16:47:53.912627 ==DQS 1 ==
7327 16:47:53.915462 Final DQS duty delay cell = 0
7328 16:47:53.918655 [0] MAX Duty = 5187%(X100), DQS PI = 62
7329 16:47:53.921795 [0] MIN Duty = 4844%(X100), DQS PI = 32
7330 16:47:53.925162 [0] AVG Duty = 5015%(X100)
7331 16:47:53.925713
7332 16:47:53.928310 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7333 16:47:53.928772
7334 16:47:53.931439 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7335 16:47:53.934946 [DutyScan_Calibration_Flow] ====Done====
7336 16:47:53.935592
7337 16:47:53.938857 [DutyScan_Calibration_Flow] k_type=3
7338 16:47:53.956110
7339 16:47:53.956659 ==DQM 0 ==
7340 16:47:53.959509 Final DQM duty delay cell = 4
7341 16:47:53.962711 [4] MAX Duty = 5125%(X100), DQS PI = 22
7342 16:47:53.966132 [4] MIN Duty = 4969%(X100), DQS PI = 44
7343 16:47:53.969579 [4] AVG Duty = 5047%(X100)
7344 16:47:53.970049
7345 16:47:53.970469 ==DQM 1 ==
7346 16:47:53.972459 Final DQM duty delay cell = 0
7347 16:47:53.977041 [0] MAX Duty = 5281%(X100), DQS PI = 58
7348 16:47:53.979186 [0] MIN Duty = 4876%(X100), DQS PI = 34
7349 16:47:53.982745 [0] AVG Duty = 5078%(X100)
7350 16:47:53.983323
7351 16:47:53.986136 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7352 16:47:53.986759
7353 16:47:53.989825 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7354 16:47:53.992789 [DutyScan_Calibration_Flow] ====Done====
7355 16:47:53.993368
7356 16:47:53.996024 [DutyScan_Calibration_Flow] k_type=2
7357 16:47:54.014471
7358 16:47:54.015042 ==DQ 0 ==
7359 16:47:54.016070 Final DQ duty delay cell = 0
7360 16:47:54.019651 [0] MAX Duty = 5093%(X100), DQS PI = 20
7361 16:47:54.023011 [0] MIN Duty = 4969%(X100), DQS PI = 46
7362 16:47:54.023616 [0] AVG Duty = 5031%(X100)
7363 16:47:54.026782
7364 16:47:54.027355 ==DQ 1 ==
7365 16:47:54.029504 Final DQ duty delay cell = 0
7366 16:47:54.033879 [0] MAX Duty = 5062%(X100), DQS PI = 2
7367 16:47:54.036213 [0] MIN Duty = 4813%(X100), DQS PI = 34
7368 16:47:54.036793 [0] AVG Duty = 4937%(X100)
7369 16:47:54.037179
7370 16:47:54.042766 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7371 16:47:54.043344
7372 16:47:54.046625 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7373 16:47:54.049401 [DutyScan_Calibration_Flow] ====Done====
7374 16:47:54.052480 nWR fixed to 30
7375 16:47:54.052960 [ModeRegInit_LP4] CH0 RK0
7376 16:47:54.055962 [ModeRegInit_LP4] CH0 RK1
7377 16:47:54.059275 [ModeRegInit_LP4] CH1 RK0
7378 16:47:54.062852 [ModeRegInit_LP4] CH1 RK1
7379 16:47:54.063483 match AC timing 5
7380 16:47:54.069231 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7381 16:47:54.073021 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7382 16:47:54.077010 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7383 16:47:54.082693 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7384 16:47:54.085835 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7385 16:47:54.086458 [MiockJmeterHQA]
7386 16:47:54.086848
7387 16:47:54.089718 [DramcMiockJmeter] u1RxGatingPI = 0
7388 16:47:54.092580 0 : 4255, 4029
7389 16:47:54.093175 4 : 4252, 4027
7390 16:47:54.095691 8 : 4363, 4138
7391 16:47:54.096170 12 : 4363, 4138
7392 16:47:54.096555 16 : 4363, 4137
7393 16:47:54.099490 20 : 4363, 4137
7394 16:47:54.100074 24 : 4252, 4027
7395 16:47:54.102944 28 : 4258, 4029
7396 16:47:54.103524 32 : 4252, 4027
7397 16:47:54.105647 36 : 4255, 4029
7398 16:47:54.106225 40 : 4250, 4026
7399 16:47:54.109309 44 : 4257, 4029
7400 16:47:54.109888 48 : 4258, 4029
7401 16:47:54.110277 52 : 4252, 4027
7402 16:47:54.112611 56 : 4255, 4029
7403 16:47:54.113235 60 : 4250, 4026
7404 16:47:54.116056 64 : 4363, 4138
7405 16:47:54.116640 68 : 4363, 4137
7406 16:47:54.119344 72 : 4250, 4027
7407 16:47:54.119930 76 : 4253, 4030
7408 16:47:54.122434 80 : 4250, 4027
7409 16:47:54.123020 84 : 4250, 4027
7410 16:47:54.123409 88 : 4250, 3511
7411 16:47:54.125730 92 : 4250, 0
7412 16:47:54.126314 96 : 4361, 0
7413 16:47:54.129598 100 : 4252, 0
7414 16:47:54.130186 104 : 4253, 0
7415 16:47:54.130643 108 : 4361, 0
7416 16:47:54.131890 112 : 4250, 0
7417 16:47:54.132371 116 : 4250, 0
7418 16:47:54.132754 120 : 4250, 0
7419 16:47:54.135868 124 : 4250, 0
7420 16:47:54.136454 128 : 4363, 0
7421 16:47:54.139041 132 : 4250, 0
7422 16:47:54.139624 136 : 4250, 0
7423 16:47:54.140012 140 : 4250, 0
7424 16:47:54.142159 144 : 4252, 0
7425 16:47:54.142781 148 : 4250, 0
7426 16:47:54.145329 152 : 4249, 0
7427 16:47:54.145809 156 : 4250, 0
7428 16:47:54.146192 160 : 4363, 0
7429 16:47:54.149028 164 : 4250, 0
7430 16:47:54.149628 168 : 4249, 0
7431 16:47:54.153033 172 : 4250, 0
7432 16:47:54.153649 176 : 4360, 0
7433 16:47:54.154045 180 : 4250, 0
7434 16:47:54.155319 184 : 4250, 0
7435 16:47:54.155897 188 : 4250, 0
7436 16:47:54.158586 192 : 4250, 0
7437 16:47:54.159167 196 : 4360, 0
7438 16:47:54.159551 200 : 4250, 11
7439 16:47:54.161932 204 : 4361, 2612
7440 16:47:54.162548 208 : 4250, 4026
7441 16:47:54.164910 212 : 4250, 4026
7442 16:47:54.165407 216 : 4250, 4027
7443 16:47:54.168290 220 : 4255, 4032
7444 16:47:54.168871 224 : 4360, 4137
7445 16:47:54.172005 228 : 4250, 4026
7446 16:47:54.172594 232 : 4250, 4027
7447 16:47:54.174902 236 : 4255, 4032
7448 16:47:54.175381 240 : 4250, 4027
7449 16:47:54.178517 244 : 4255, 4029
7450 16:47:54.179100 248 : 4361, 4137
7451 16:47:54.179493 252 : 4250, 4027
7452 16:47:54.181259 256 : 4360, 4138
7453 16:47:54.181789 260 : 4250, 4027
7454 16:47:54.184865 264 : 4250, 4026
7455 16:47:54.185449 268 : 4250, 4027
7456 16:47:54.188451 272 : 4250, 4027
7457 16:47:54.189037 276 : 4250, 4027
7458 16:47:54.191389 280 : 4250, 4027
7459 16:47:54.191976 284 : 4250, 4027
7460 16:47:54.195276 288 : 4252, 4030
7461 16:47:54.195863 292 : 4250, 4026
7462 16:47:54.198602 296 : 4250, 4027
7463 16:47:54.199185 300 : 4361, 4137
7464 16:47:54.201314 304 : 4250, 4027
7465 16:47:54.201797 308 : 4360, 4137
7466 16:47:54.205057 312 : 4250, 3845
7467 16:47:54.205646 316 : 4250, 2070
7468 16:47:54.206036
7469 16:47:54.208413 MIOCK jitter meter ch=0
7470 16:47:54.208994
7471 16:47:54.211163 1T = (316-92) = 224 dly cells
7472 16:47:54.214471 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7473 16:47:54.214947 ==
7474 16:47:54.218173 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 16:47:54.224588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7476 16:47:54.225170 ==
7477 16:47:54.228500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7478 16:47:54.234820 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7479 16:47:54.237810 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7480 16:47:54.244941 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7481 16:47:54.252034 [CA 0] Center 43 (13~73) winsize 61
7482 16:47:54.255782 [CA 1] Center 43 (13~73) winsize 61
7483 16:47:54.258526 [CA 2] Center 38 (8~68) winsize 61
7484 16:47:54.262386 [CA 3] Center 37 (8~67) winsize 60
7485 16:47:54.265310 [CA 4] Center 36 (6~66) winsize 61
7486 16:47:54.268790 [CA 5] Center 35 (5~65) winsize 61
7487 16:47:54.269362
7488 16:47:54.271671 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7489 16:47:54.272145
7490 16:47:54.274924 [CATrainingPosCal] consider 1 rank data
7491 16:47:54.278193 u2DelayCellTimex100 = 290/100 ps
7492 16:47:54.285264 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7493 16:47:54.288541 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7494 16:47:54.291921 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7495 16:47:54.295231 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7496 16:47:54.298996 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7497 16:47:54.301918 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7498 16:47:54.302521
7499 16:47:54.304980 CA PerBit enable=1, Macro0, CA PI delay=35
7500 16:47:54.305561
7501 16:47:54.308342 [CBTSetCACLKResult] CA Dly = 35
7502 16:47:54.311961 CS Dly: 9 (0~40)
7503 16:47:54.314730 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7504 16:47:54.318508 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7505 16:47:54.319074 ==
7506 16:47:54.321476 Dram Type= 6, Freq= 0, CH_0, rank 1
7507 16:47:54.328191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7508 16:47:54.328763 ==
7509 16:47:54.331427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7510 16:47:54.338094 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7511 16:47:54.341516 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7512 16:47:54.347931 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7513 16:47:54.355283 [CA 0] Center 43 (13~74) winsize 62
7514 16:47:54.358899 [CA 1] Center 43 (13~73) winsize 61
7515 16:47:54.363103 [CA 2] Center 38 (9~68) winsize 60
7516 16:47:54.365191 [CA 3] Center 38 (9~68) winsize 60
7517 16:47:54.368822 [CA 4] Center 37 (7~67) winsize 61
7518 16:47:54.371734 [CA 5] Center 36 (6~66) winsize 61
7519 16:47:54.372206
7520 16:47:54.375197 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7521 16:47:54.375669
7522 16:47:54.378758 [CATrainingPosCal] consider 2 rank data
7523 16:47:54.381641 u2DelayCellTimex100 = 290/100 ps
7524 16:47:54.388764 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7525 16:47:54.391721 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7526 16:47:54.395444 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7527 16:47:54.398037 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7528 16:47:54.401797 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7529 16:47:54.404978 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7530 16:47:54.405547
7531 16:47:54.408427 CA PerBit enable=1, Macro0, CA PI delay=35
7532 16:47:54.408994
7533 16:47:54.411610 [CBTSetCACLKResult] CA Dly = 35
7534 16:47:54.414801 CS Dly: 10 (0~43)
7535 16:47:54.418598 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7536 16:47:54.421642 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7537 16:47:54.422208
7538 16:47:54.425132 ----->DramcWriteLeveling(PI) begin...
7539 16:47:54.425607 ==
7540 16:47:54.428347 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 16:47:54.434568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 16:47:54.435124 ==
7543 16:47:54.438213 Write leveling (Byte 0): 36 => 36
7544 16:47:54.441554 Write leveling (Byte 1): 31 => 31
7545 16:47:54.442137 DramcWriteLeveling(PI) end<-----
7546 16:47:54.442573
7547 16:47:54.444322 ==
7548 16:47:54.448012 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 16:47:54.451300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 16:47:54.451870 ==
7551 16:47:54.454761 [Gating] SW mode calibration
7552 16:47:54.461193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7553 16:47:54.464404 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7554 16:47:54.471579 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 16:47:54.474308 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 16:47:54.477731 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7557 16:47:54.484386 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7558 16:47:54.487502 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7559 16:47:54.490923 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 16:47:54.497614 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 16:47:54.500478 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 16:47:54.504840 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 16:47:54.511023 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 16:47:54.514425 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
7565 16:47:54.517454 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7566 16:47:54.523819 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7567 16:47:54.527268 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7568 16:47:54.530749 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 16:47:54.537054 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 16:47:54.540356 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 16:47:54.543544 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7572 16:47:54.550754 1 6 8 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
7573 16:47:54.554197 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7574 16:47:54.556648 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7575 16:47:54.563556 1 6 20 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
7576 16:47:54.566624 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 16:47:54.570889 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 16:47:54.577091 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 16:47:54.580609 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 16:47:54.582836 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 16:47:54.589630 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7582 16:47:54.593122 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7583 16:47:54.596312 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7584 16:47:54.603204 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 16:47:54.606779 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 16:47:54.609491 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 16:47:54.616088 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 16:47:54.619405 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 16:47:54.622802 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 16:47:54.629538 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 16:47:54.632563 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 16:47:54.636255 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 16:47:54.642894 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 16:47:54.646181 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 16:47:54.649057 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 16:47:54.656283 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7597 16:47:54.659129 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 16:47:54.662648 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7599 16:47:54.665880 Total UI for P1: 0, mck2ui 16
7600 16:47:54.669740 best dqsien dly found for B0: ( 1, 9, 10)
7601 16:47:54.676049 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7602 16:47:54.679265 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 16:47:54.682753 Total UI for P1: 0, mck2ui 16
7604 16:47:54.685896 best dqsien dly found for B1: ( 1, 9, 20)
7605 16:47:54.689445 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7606 16:47:54.692494 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7607 16:47:54.693101
7608 16:47:54.695731 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7609 16:47:54.699432 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7610 16:47:54.702454 [Gating] SW calibration Done
7611 16:47:54.703017 ==
7612 16:47:54.705906 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 16:47:54.708898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 16:47:54.712229 ==
7615 16:47:54.712796 RX Vref Scan: 0
7616 16:47:54.713172
7617 16:47:54.715628 RX Vref 0 -> 0, step: 1
7618 16:47:54.716094
7619 16:47:54.718829 RX Delay 0 -> 252, step: 8
7620 16:47:54.722620 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7621 16:47:54.725251 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7622 16:47:54.728622 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7623 16:47:54.731904 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7624 16:47:54.736067 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7625 16:47:54.742915 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7626 16:47:54.745572 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7627 16:47:54.748606 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7628 16:47:54.752599 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7629 16:47:54.755020 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7630 16:47:54.762469 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7631 16:47:54.765138 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7632 16:47:54.768566 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7633 16:47:54.772364 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7634 16:47:54.779206 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7635 16:47:54.781930 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7636 16:47:54.782546 ==
7637 16:47:54.785284 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 16:47:54.788439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 16:47:54.789015 ==
7640 16:47:54.792278 DQS Delay:
7641 16:47:54.792858 DQS0 = 0, DQS1 = 0
7642 16:47:54.793241 DQM Delay:
7643 16:47:54.794847 DQM0 = 138, DQM1 = 127
7644 16:47:54.795315 DQ Delay:
7645 16:47:54.798960 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7646 16:47:54.801942 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7647 16:47:54.805740 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7648 16:47:54.811244 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7649 16:47:54.811801
7650 16:47:54.812314
7651 16:47:54.812794 ==
7652 16:47:54.814711 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 16:47:54.818039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 16:47:54.818541 ==
7655 16:47:54.818922
7656 16:47:54.819266
7657 16:47:54.821340 TX Vref Scan disable
7658 16:47:54.821807 == TX Byte 0 ==
7659 16:47:54.827657 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7660 16:47:54.831681 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7661 16:47:54.834806 == TX Byte 1 ==
7662 16:47:54.837957 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7663 16:47:54.841630 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7664 16:47:54.842204 ==
7665 16:47:54.844143 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 16:47:54.847670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 16:47:54.848252 ==
7668 16:47:54.862563
7669 16:47:54.865897 TX Vref early break, caculate TX vref
7670 16:47:54.869185 TX Vref=16, minBit 8, minWin=22, winSum=378
7671 16:47:54.872103 TX Vref=18, minBit 8, minWin=23, winSum=387
7672 16:47:54.875739 TX Vref=20, minBit 7, minWin=23, winSum=398
7673 16:47:54.878626 TX Vref=22, minBit 6, minWin=24, winSum=407
7674 16:47:54.882303 TX Vref=24, minBit 2, minWin=25, winSum=418
7675 16:47:54.888966 TX Vref=26, minBit 0, minWin=26, winSum=426
7676 16:47:54.892349 TX Vref=28, minBit 7, minWin=25, winSum=428
7677 16:47:54.895250 TX Vref=30, minBit 0, minWin=26, winSum=425
7678 16:47:54.898470 TX Vref=32, minBit 1, minWin=24, winSum=415
7679 16:47:54.902496 TX Vref=34, minBit 2, minWin=24, winSum=403
7680 16:47:54.908768 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
7681 16:47:54.909358
7682 16:47:54.911839 Final TX Range 0 Vref 26
7683 16:47:54.912414
7684 16:47:54.912858 ==
7685 16:47:54.915027 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 16:47:54.918441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 16:47:54.919067 ==
7688 16:47:54.919447
7689 16:47:54.919794
7690 16:47:54.921457 TX Vref Scan disable
7691 16:47:54.928922 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7692 16:47:54.929390 == TX Byte 0 ==
7693 16:47:54.931789 u2DelayCellOfst[0]=10 cells (3 PI)
7694 16:47:54.934571 u2DelayCellOfst[1]=13 cells (4 PI)
7695 16:47:54.938047 u2DelayCellOfst[2]=10 cells (3 PI)
7696 16:47:54.941534 u2DelayCellOfst[3]=10 cells (3 PI)
7697 16:47:54.944670 u2DelayCellOfst[4]=6 cells (2 PI)
7698 16:47:54.947739 u2DelayCellOfst[5]=0 cells (0 PI)
7699 16:47:54.951089 u2DelayCellOfst[6]=16 cells (5 PI)
7700 16:47:54.954688 u2DelayCellOfst[7]=16 cells (5 PI)
7701 16:47:54.958688 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7702 16:47:54.960930 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7703 16:47:54.964360 == TX Byte 1 ==
7704 16:47:54.967681 u2DelayCellOfst[8]=0 cells (0 PI)
7705 16:47:54.971079 u2DelayCellOfst[9]=0 cells (0 PI)
7706 16:47:54.971647 u2DelayCellOfst[10]=6 cells (2 PI)
7707 16:47:54.974338 u2DelayCellOfst[11]=3 cells (1 PI)
7708 16:47:54.977871 u2DelayCellOfst[12]=10 cells (3 PI)
7709 16:47:54.980806 u2DelayCellOfst[13]=10 cells (3 PI)
7710 16:47:54.983999 u2DelayCellOfst[14]=13 cells (4 PI)
7711 16:47:54.987321 u2DelayCellOfst[15]=10 cells (3 PI)
7712 16:47:54.994603 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7713 16:47:54.997203 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7714 16:47:54.997840 DramC Write-DBI on
7715 16:47:54.998224 ==
7716 16:47:55.000913 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 16:47:55.007426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 16:47:55.008009 ==
7719 16:47:55.008387
7720 16:47:55.008733
7721 16:47:55.010899 TX Vref Scan disable
7722 16:47:55.011465 == TX Byte 0 ==
7723 16:47:55.016959 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7724 16:47:55.017528 == TX Byte 1 ==
7725 16:47:55.020426 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7726 16:47:55.023820 DramC Write-DBI off
7727 16:47:55.024381
7728 16:47:55.024757 [DATLAT]
7729 16:47:55.026875 Freq=1600, CH0 RK0
7730 16:47:55.027342
7731 16:47:55.027714 DATLAT Default: 0xf
7732 16:47:55.030461 0, 0xFFFF, sum = 0
7733 16:47:55.031031 1, 0xFFFF, sum = 0
7734 16:47:55.033505 2, 0xFFFF, sum = 0
7735 16:47:55.033982 3, 0xFFFF, sum = 0
7736 16:47:55.036942 4, 0xFFFF, sum = 0
7737 16:47:55.037521 5, 0xFFFF, sum = 0
7738 16:47:55.040509 6, 0xFFFF, sum = 0
7739 16:47:55.041085 7, 0xFFFF, sum = 0
7740 16:47:55.043404 8, 0xFFFF, sum = 0
7741 16:47:55.043882 9, 0xFFFF, sum = 0
7742 16:47:55.046503 10, 0xFFFF, sum = 0
7743 16:47:55.050132 11, 0xFFFF, sum = 0
7744 16:47:55.050758 12, 0xFFFF, sum = 0
7745 16:47:55.053624 13, 0xFFFF, sum = 0
7746 16:47:55.054215 14, 0x0, sum = 1
7747 16:47:55.056811 15, 0x0, sum = 2
7748 16:47:55.057441 16, 0x0, sum = 3
7749 16:47:55.060186 17, 0x0, sum = 4
7750 16:47:55.060768 best_step = 15
7751 16:47:55.061145
7752 16:47:55.061494 ==
7753 16:47:55.063754 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 16:47:55.066699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 16:47:55.067172 ==
7756 16:47:55.070487 RX Vref Scan: 1
7757 16:47:55.071060
7758 16:47:55.073414 Set Vref Range= 24 -> 127
7759 16:47:55.073987
7760 16:47:55.074388 RX Vref 24 -> 127, step: 1
7761 16:47:55.076875
7762 16:47:55.077444 RX Delay 19 -> 252, step: 4
7763 16:47:55.077824
7764 16:47:55.080103 Set Vref, RX VrefLevel [Byte0]: 24
7765 16:47:55.083430 [Byte1]: 24
7766 16:47:55.086385
7767 16:47:55.086855 Set Vref, RX VrefLevel [Byte0]: 25
7768 16:47:55.090020 [Byte1]: 25
7769 16:47:55.094775
7770 16:47:55.095345 Set Vref, RX VrefLevel [Byte0]: 26
7771 16:47:55.097372 [Byte1]: 26
7772 16:47:55.101788
7773 16:47:55.102387 Set Vref, RX VrefLevel [Byte0]: 27
7774 16:47:55.105235 [Byte1]: 27
7775 16:47:55.109677
7776 16:47:55.110246 Set Vref, RX VrefLevel [Byte0]: 28
7777 16:47:55.113877 [Byte1]: 28
7778 16:47:55.117862
7779 16:47:55.118467 Set Vref, RX VrefLevel [Byte0]: 29
7780 16:47:55.120376 [Byte1]: 29
7781 16:47:55.125466
7782 16:47:55.126037 Set Vref, RX VrefLevel [Byte0]: 30
7783 16:47:55.128011 [Byte1]: 30
7784 16:47:55.132038
7785 16:47:55.132627 Set Vref, RX VrefLevel [Byte0]: 31
7786 16:47:55.135264 [Byte1]: 31
7787 16:47:55.139578
7788 16:47:55.140145 Set Vref, RX VrefLevel [Byte0]: 32
7789 16:47:55.143065 [Byte1]: 32
7790 16:47:55.147611
7791 16:47:55.148099 Set Vref, RX VrefLevel [Byte0]: 33
7792 16:47:55.150305 [Byte1]: 33
7793 16:47:55.154975
7794 16:47:55.155443 Set Vref, RX VrefLevel [Byte0]: 34
7795 16:47:55.158507 [Byte1]: 34
7796 16:47:55.162324
7797 16:47:55.162932 Set Vref, RX VrefLevel [Byte0]: 35
7798 16:47:55.165569 [Byte1]: 35
7799 16:47:55.170109
7800 16:47:55.170728 Set Vref, RX VrefLevel [Byte0]: 36
7801 16:47:55.173425 [Byte1]: 36
7802 16:47:55.178098
7803 16:47:55.178726 Set Vref, RX VrefLevel [Byte0]: 37
7804 16:47:55.181404 [Byte1]: 37
7805 16:47:55.185215
7806 16:47:55.185683 Set Vref, RX VrefLevel [Byte0]: 38
7807 16:47:55.188944 [Byte1]: 38
7808 16:47:55.193011
7809 16:47:55.193586 Set Vref, RX VrefLevel [Byte0]: 39
7810 16:47:55.196113 [Byte1]: 39
7811 16:47:55.200541
7812 16:47:55.201113 Set Vref, RX VrefLevel [Byte0]: 40
7813 16:47:55.203712 [Byte1]: 40
7814 16:47:55.208032
7815 16:47:55.208603 Set Vref, RX VrefLevel [Byte0]: 41
7816 16:47:55.211250 [Byte1]: 41
7817 16:47:55.215323
7818 16:47:55.215949 Set Vref, RX VrefLevel [Byte0]: 42
7819 16:47:55.219594 [Byte1]: 42
7820 16:47:55.223239
7821 16:47:55.223818 Set Vref, RX VrefLevel [Byte0]: 43
7822 16:47:55.226345 [Byte1]: 43
7823 16:47:55.230634
7824 16:47:55.231206 Set Vref, RX VrefLevel [Byte0]: 44
7825 16:47:55.233736 [Byte1]: 44
7826 16:47:55.237894
7827 16:47:55.238502 Set Vref, RX VrefLevel [Byte0]: 45
7828 16:47:55.241312 [Byte1]: 45
7829 16:47:55.245866
7830 16:47:55.246494 Set Vref, RX VrefLevel [Byte0]: 46
7831 16:47:55.248953 [Byte1]: 46
7832 16:47:55.253084
7833 16:47:55.253562 Set Vref, RX VrefLevel [Byte0]: 47
7834 16:47:55.256649 [Byte1]: 47
7835 16:47:55.260780
7836 16:47:55.261252 Set Vref, RX VrefLevel [Byte0]: 48
7837 16:47:55.263982 [Byte1]: 48
7838 16:47:55.268168
7839 16:47:55.268642 Set Vref, RX VrefLevel [Byte0]: 49
7840 16:47:55.271837 [Byte1]: 49
7841 16:47:55.275684
7842 16:47:55.276238 Set Vref, RX VrefLevel [Byte0]: 50
7843 16:47:55.279321 [Byte1]: 50
7844 16:47:55.283316
7845 16:47:55.283991 Set Vref, RX VrefLevel [Byte0]: 51
7846 16:47:55.287091 [Byte1]: 51
7847 16:47:55.291598
7848 16:47:55.294616 Set Vref, RX VrefLevel [Byte0]: 52
7849 16:47:55.295187 [Byte1]: 52
7850 16:47:55.299028
7851 16:47:55.299602 Set Vref, RX VrefLevel [Byte0]: 53
7852 16:47:55.302251 [Byte1]: 53
7853 16:47:55.306337
7854 16:47:55.306952 Set Vref, RX VrefLevel [Byte0]: 54
7855 16:47:55.309790 [Byte1]: 54
7856 16:47:55.313768
7857 16:47:55.314411 Set Vref, RX VrefLevel [Byte0]: 55
7858 16:47:55.317220 [Byte1]: 55
7859 16:47:55.322003
7860 16:47:55.322616 Set Vref, RX VrefLevel [Byte0]: 56
7861 16:47:55.324723 [Byte1]: 56
7862 16:47:55.329026
7863 16:47:55.329605 Set Vref, RX VrefLevel [Byte0]: 57
7864 16:47:55.332199 [Byte1]: 57
7865 16:47:55.336880
7866 16:47:55.337449 Set Vref, RX VrefLevel [Byte0]: 58
7867 16:47:55.340043 [Byte1]: 58
7868 16:47:55.344380
7869 16:47:55.344958 Set Vref, RX VrefLevel [Byte0]: 59
7870 16:47:55.347361 [Byte1]: 59
7871 16:47:55.351552
7872 16:47:55.352126 Set Vref, RX VrefLevel [Byte0]: 60
7873 16:47:55.354715 [Byte1]: 60
7874 16:47:55.359151
7875 16:47:55.359747 Set Vref, RX VrefLevel [Byte0]: 61
7876 16:47:55.362731 [Byte1]: 61
7877 16:47:55.366538
7878 16:47:55.367029 Set Vref, RX VrefLevel [Byte0]: 62
7879 16:47:55.369894 [Byte1]: 62
7880 16:47:55.374731
7881 16:47:55.375305 Set Vref, RX VrefLevel [Byte0]: 63
7882 16:47:55.377631 [Byte1]: 63
7883 16:47:55.381952
7884 16:47:55.382565 Set Vref, RX VrefLevel [Byte0]: 64
7885 16:47:55.384986 [Byte1]: 64
7886 16:47:55.389609
7887 16:47:55.390179 Set Vref, RX VrefLevel [Byte0]: 65
7888 16:47:55.392788 [Byte1]: 65
7889 16:47:55.397073
7890 16:47:55.397646 Set Vref, RX VrefLevel [Byte0]: 66
7891 16:47:55.400429 [Byte1]: 66
7892 16:47:55.404655
7893 16:47:55.405230 Set Vref, RX VrefLevel [Byte0]: 67
7894 16:47:55.408330 [Byte1]: 67
7895 16:47:55.412222
7896 16:47:55.412794 Set Vref, RX VrefLevel [Byte0]: 68
7897 16:47:55.415635 [Byte1]: 68
7898 16:47:55.419765
7899 16:47:55.420342 Set Vref, RX VrefLevel [Byte0]: 69
7900 16:47:55.423652 [Byte1]: 69
7901 16:47:55.427826
7902 16:47:55.428296 Set Vref, RX VrefLevel [Byte0]: 70
7903 16:47:55.430932 [Byte1]: 70
7904 16:47:55.435114
7905 16:47:55.435688 Set Vref, RX VrefLevel [Byte0]: 71
7906 16:47:55.438178 [Byte1]: 71
7907 16:47:55.442860
7908 16:47:55.443431 Set Vref, RX VrefLevel [Byte0]: 72
7909 16:47:55.445689 [Byte1]: 72
7910 16:47:55.450305
7911 16:47:55.450921 Set Vref, RX VrefLevel [Byte0]: 73
7912 16:47:55.453577 [Byte1]: 73
7913 16:47:55.457757
7914 16:47:55.458332 Set Vref, RX VrefLevel [Byte0]: 74
7915 16:47:55.461218 [Byte1]: 74
7916 16:47:55.465680
7917 16:47:55.466396 Set Vref, RX VrefLevel [Byte0]: 75
7918 16:47:55.468315 [Byte1]: 75
7919 16:47:55.473355
7920 16:47:55.473921 Set Vref, RX VrefLevel [Byte0]: 76
7921 16:47:55.476094 [Byte1]: 76
7922 16:47:55.480264
7923 16:47:55.480827 Set Vref, RX VrefLevel [Byte0]: 77
7924 16:47:55.483938 [Byte1]: 77
7925 16:47:55.488133
7926 16:47:55.488621 Set Vref, RX VrefLevel [Byte0]: 78
7927 16:47:55.491229 [Byte1]: 78
7928 16:47:55.495127
7929 16:47:55.495598 Set Vref, RX VrefLevel [Byte0]: 79
7930 16:47:55.498715 [Byte1]: 79
7931 16:47:55.503270
7932 16:47:55.503834 Set Vref, RX VrefLevel [Byte0]: 80
7933 16:47:55.506439 [Byte1]: 80
7934 16:47:55.510575
7935 16:47:55.511135 Set Vref, RX VrefLevel [Byte0]: 81
7936 16:47:55.514041 [Byte1]: 81
7937 16:47:55.518335
7938 16:47:55.518941 Final RX Vref Byte 0 = 62 to rank0
7939 16:47:55.521586 Final RX Vref Byte 1 = 61 to rank0
7940 16:47:55.525620 Final RX Vref Byte 0 = 62 to rank1
7941 16:47:55.527852 Final RX Vref Byte 1 = 61 to rank1==
7942 16:47:55.531881 Dram Type= 6, Freq= 0, CH_0, rank 0
7943 16:47:55.538136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 16:47:55.538753 ==
7945 16:47:55.539138 DQS Delay:
7946 16:47:55.541541 DQS0 = 0, DQS1 = 0
7947 16:47:55.542111 DQM Delay:
7948 16:47:55.542542 DQM0 = 136, DQM1 = 124
7949 16:47:55.544878 DQ Delay:
7950 16:47:55.547827 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7951 16:47:55.551589 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =144
7952 16:47:55.555032 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7953 16:47:55.558547 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7954 16:47:55.559112
7955 16:47:55.559493
7956 16:47:55.559837
7957 16:47:55.561116 [DramC_TX_OE_Calibration] TA2
7958 16:47:55.564573 Original DQ_B0 (3 6) =30, OEN = 27
7959 16:47:55.567906 Original DQ_B1 (3 6) =30, OEN = 27
7960 16:47:55.571357 24, 0x0, End_B0=24 End_B1=24
7961 16:47:55.571930 25, 0x0, End_B0=25 End_B1=25
7962 16:47:55.574327 26, 0x0, End_B0=26 End_B1=26
7963 16:47:55.577509 27, 0x0, End_B0=27 End_B1=27
7964 16:47:55.581415 28, 0x0, End_B0=28 End_B1=28
7965 16:47:55.584782 29, 0x0, End_B0=29 End_B1=29
7966 16:47:55.585264 30, 0x0, End_B0=30 End_B1=30
7967 16:47:55.587872 31, 0x4141, End_B0=30 End_B1=30
7968 16:47:55.591255 Byte0 end_step=30 best_step=27
7969 16:47:55.594809 Byte1 end_step=30 best_step=27
7970 16:47:55.597728 Byte0 TX OE(2T, 0.5T) = (3, 3)
7971 16:47:55.601128 Byte1 TX OE(2T, 0.5T) = (3, 3)
7972 16:47:55.601691
7973 16:47:55.602067
7974 16:47:55.607942 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7975 16:47:55.611208 CH0 RK0: MR19=303, MR18=1F1D
7976 16:47:55.617612 CH0_RK0: MR19=0x303, MR18=0x1F1D, DQSOSC=394, MR23=63, INC=23, DEC=15
7977 16:47:55.618169
7978 16:47:55.621097 ----->DramcWriteLeveling(PI) begin...
7979 16:47:55.621664 ==
7980 16:47:55.624284 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 16:47:55.627582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 16:47:55.628275 ==
7983 16:47:55.630971 Write leveling (Byte 0): 38 => 38
7984 16:47:55.634174 Write leveling (Byte 1): 29 => 29
7985 16:47:55.637839 DramcWriteLeveling(PI) end<-----
7986 16:47:55.638284
7987 16:47:55.638702 ==
7988 16:47:55.640724 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 16:47:55.644467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 16:47:55.645086 ==
7991 16:47:55.647025 [Gating] SW mode calibration
7992 16:47:55.654151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7993 16:47:55.660329 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7994 16:47:55.663490 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 16:47:55.670581 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 16:47:55.673896 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7997 16:47:55.677392 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7998 16:47:55.683847 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 16:47:55.689461 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 16:47:55.690480 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 16:47:55.696943 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 16:47:55.699990 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 16:47:55.703491 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 16:47:55.710281 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8005 16:47:55.713598 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8006 16:47:55.716838 1 5 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8007 16:47:55.724033 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 16:47:55.726707 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 16:47:55.729958 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 16:47:55.737023 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 16:47:55.739524 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 16:47:55.743262 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8013 16:47:55.749468 1 6 12 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8014 16:47:55.753051 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 16:47:55.756554 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 16:47:55.763208 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 16:47:55.766413 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 16:47:55.769636 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 16:47:55.776130 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 16:47:55.779420 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 16:47:55.783312 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8022 16:47:55.789676 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8023 16:47:55.793224 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 16:47:55.796312 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 16:47:55.799235 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 16:47:55.806453 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 16:47:55.809367 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 16:47:55.812590 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 16:47:55.819928 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 16:47:55.822932 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 16:47:55.825557 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 16:47:55.832724 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 16:47:55.835767 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 16:47:55.838644 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 16:47:55.845489 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 16:47:55.849221 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8037 16:47:55.852023 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8038 16:47:55.855379 Total UI for P1: 0, mck2ui 16
8039 16:47:55.859018 best dqsien dly found for B0: ( 1, 9, 8)
8040 16:47:55.866062 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 16:47:55.868576 Total UI for P1: 0, mck2ui 16
8042 16:47:55.872172 best dqsien dly found for B1: ( 1, 9, 12)
8043 16:47:55.875250 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8044 16:47:55.878468 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8045 16:47:55.879040
8046 16:47:55.882537 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8047 16:47:55.885254 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8048 16:47:55.888695 [Gating] SW calibration Done
8049 16:47:55.889272 ==
8050 16:47:55.891684 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 16:47:55.895336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 16:47:55.895917 ==
8053 16:47:55.898530 RX Vref Scan: 0
8054 16:47:55.899105
8055 16:47:55.901747 RX Vref 0 -> 0, step: 1
8056 16:47:55.902315
8057 16:47:55.902749 RX Delay 0 -> 252, step: 8
8058 16:47:55.908405 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8059 16:47:55.912005 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8060 16:47:55.915042 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8061 16:47:55.917864 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8062 16:47:55.922087 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8063 16:47:55.928522 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8064 16:47:55.932006 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8065 16:47:55.934510 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8066 16:47:55.939067 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8067 16:47:55.941111 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8068 16:47:55.948024 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8069 16:47:55.950955 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8070 16:47:55.954793 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8071 16:47:55.957847 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8072 16:47:55.964015 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8073 16:47:55.967291 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8074 16:47:55.967770 ==
8075 16:47:55.971061 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 16:47:55.974680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 16:47:55.975260 ==
8078 16:47:55.977757 DQS Delay:
8079 16:47:55.978604 DQS0 = 0, DQS1 = 0
8080 16:47:55.979001 DQM Delay:
8081 16:47:55.981254 DQM0 = 136, DQM1 = 125
8082 16:47:55.981726 DQ Delay:
8083 16:47:55.983856 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8084 16:47:55.987545 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8085 16:47:55.990638 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8086 16:47:55.997320 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8087 16:47:55.997899
8088 16:47:55.998276
8089 16:47:55.998690 ==
8090 16:47:56.000225 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 16:47:56.004075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 16:47:56.004662 ==
8093 16:47:56.005154
8094 16:47:56.005605
8095 16:47:56.006967 TX Vref Scan disable
8096 16:47:56.007446 == TX Byte 0 ==
8097 16:47:56.014162 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8098 16:47:56.017436 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8099 16:47:56.018024 == TX Byte 1 ==
8100 16:47:56.023279 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8101 16:47:56.027051 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8102 16:47:56.027537 ==
8103 16:47:56.030571 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 16:47:56.034056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 16:47:56.036699 ==
8106 16:47:56.049197
8107 16:47:56.052108 TX Vref early break, caculate TX vref
8108 16:47:56.055261 TX Vref=16, minBit 0, minWin=23, winSum=392
8109 16:47:56.058925 TX Vref=18, minBit 1, minWin=24, winSum=399
8110 16:47:56.061945 TX Vref=20, minBit 8, minWin=23, winSum=404
8111 16:47:56.064928 TX Vref=22, minBit 0, minWin=25, winSum=413
8112 16:47:56.068238 TX Vref=24, minBit 0, minWin=26, winSum=421
8113 16:47:56.074973 TX Vref=26, minBit 0, minWin=26, winSum=431
8114 16:47:56.079115 TX Vref=28, minBit 0, minWin=26, winSum=430
8115 16:47:56.081391 TX Vref=30, minBit 0, minWin=26, winSum=428
8116 16:47:56.084875 TX Vref=32, minBit 1, minWin=25, winSum=418
8117 16:47:56.088295 TX Vref=34, minBit 11, minWin=24, winSum=408
8118 16:47:56.094855 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 26
8119 16:47:56.095440
8120 16:47:56.098452 Final TX Range 0 Vref 26
8121 16:47:56.099028
8122 16:47:56.099554 ==
8123 16:47:56.101069 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 16:47:56.105229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 16:47:56.105812 ==
8126 16:47:56.106304
8127 16:47:56.107672
8128 16:47:56.108149 TX Vref Scan disable
8129 16:47:56.114688 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8130 16:47:56.115307 == TX Byte 0 ==
8131 16:47:56.117524 u2DelayCellOfst[0]=13 cells (4 PI)
8132 16:47:56.121649 u2DelayCellOfst[1]=16 cells (5 PI)
8133 16:47:56.124367 u2DelayCellOfst[2]=13 cells (4 PI)
8134 16:47:56.127653 u2DelayCellOfst[3]=13 cells (4 PI)
8135 16:47:56.130692 u2DelayCellOfst[4]=10 cells (3 PI)
8136 16:47:56.134206 u2DelayCellOfst[5]=0 cells (0 PI)
8137 16:47:56.137644 u2DelayCellOfst[6]=20 cells (6 PI)
8138 16:47:56.140817 u2DelayCellOfst[7]=16 cells (5 PI)
8139 16:47:56.144879 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8140 16:47:56.147556 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8141 16:47:56.150565 == TX Byte 1 ==
8142 16:47:56.154260 u2DelayCellOfst[8]=0 cells (0 PI)
8143 16:47:56.157324 u2DelayCellOfst[9]=0 cells (0 PI)
8144 16:47:56.160778 u2DelayCellOfst[10]=3 cells (1 PI)
8145 16:47:56.163790 u2DelayCellOfst[11]=0 cells (0 PI)
8146 16:47:56.167278 u2DelayCellOfst[12]=10 cells (3 PI)
8147 16:47:56.170952 u2DelayCellOfst[13]=10 cells (3 PI)
8148 16:47:56.174094 u2DelayCellOfst[14]=10 cells (3 PI)
8149 16:47:56.174721 u2DelayCellOfst[15]=6 cells (2 PI)
8150 16:47:56.180633 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8151 16:47:56.183607 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8152 16:47:56.187154 DramC Write-DBI on
8153 16:47:56.187760 ==
8154 16:47:56.190289 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 16:47:56.193301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 16:47:56.193866 ==
8157 16:47:56.194244
8158 16:47:56.194653
8159 16:47:56.197341 TX Vref Scan disable
8160 16:47:56.197920 == TX Byte 0 ==
8161 16:47:56.203390 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8162 16:47:56.203957 == TX Byte 1 ==
8163 16:47:56.206892 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8164 16:47:56.210408 DramC Write-DBI off
8165 16:47:56.210998
8166 16:47:56.211377 [DATLAT]
8167 16:47:56.213841 Freq=1600, CH0 RK1
8168 16:47:56.214465
8169 16:47:56.214867 DATLAT Default: 0xf
8170 16:47:56.216859 0, 0xFFFF, sum = 0
8171 16:47:56.217340 1, 0xFFFF, sum = 0
8172 16:47:56.219935 2, 0xFFFF, sum = 0
8173 16:47:56.223247 3, 0xFFFF, sum = 0
8174 16:47:56.223814 4, 0xFFFF, sum = 0
8175 16:47:56.226607 5, 0xFFFF, sum = 0
8176 16:47:56.227169 6, 0xFFFF, sum = 0
8177 16:47:56.230253 7, 0xFFFF, sum = 0
8178 16:47:56.230849 8, 0xFFFF, sum = 0
8179 16:47:56.233578 9, 0xFFFF, sum = 0
8180 16:47:56.234166 10, 0xFFFF, sum = 0
8181 16:47:56.236478 11, 0xFFFF, sum = 0
8182 16:47:56.236978 12, 0xFFFF, sum = 0
8183 16:47:56.239708 13, 0xFFFF, sum = 0
8184 16:47:56.240182 14, 0x0, sum = 1
8185 16:47:56.243795 15, 0x0, sum = 2
8186 16:47:56.244287 16, 0x0, sum = 3
8187 16:47:56.246187 17, 0x0, sum = 4
8188 16:47:56.246700 best_step = 15
8189 16:47:56.247078
8190 16:47:56.247426 ==
8191 16:47:56.249821 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 16:47:56.254296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 16:47:56.256397 ==
8194 16:47:56.256867 RX Vref Scan: 0
8195 16:47:56.257241
8196 16:47:56.260050 RX Vref 0 -> 0, step: 1
8197 16:47:56.260778
8198 16:47:56.261169 RX Delay 11 -> 252, step: 4
8199 16:47:56.267081 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8200 16:47:56.270962 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8201 16:47:56.274550 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8202 16:47:56.277876 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8203 16:47:56.280917 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8204 16:47:56.287297 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8205 16:47:56.290322 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8206 16:47:56.293819 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8207 16:47:56.297119 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8208 16:47:56.300239 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8209 16:47:56.307035 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8210 16:47:56.310609 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8211 16:47:56.313554 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8212 16:47:56.317417 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8213 16:47:56.323561 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8214 16:47:56.326789 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8215 16:47:56.327358 ==
8216 16:47:56.329778 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 16:47:56.333645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 16:47:56.334217 ==
8219 16:47:56.337029 DQS Delay:
8220 16:47:56.337594 DQS0 = 0, DQS1 = 0
8221 16:47:56.337973 DQM Delay:
8222 16:47:56.340256 DQM0 = 133, DQM1 = 123
8223 16:47:56.340728 DQ Delay:
8224 16:47:56.343220 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8225 16:47:56.346476 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8226 16:47:56.350442 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8227 16:47:56.356604 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8228 16:47:56.357171
8229 16:47:56.357540
8230 16:47:56.357881
8231 16:47:56.359707 [DramC_TX_OE_Calibration] TA2
8232 16:47:56.363112 Original DQ_B0 (3 6) =30, OEN = 27
8233 16:47:56.363580 Original DQ_B1 (3 6) =30, OEN = 27
8234 16:47:56.366243 24, 0x0, End_B0=24 End_B1=24
8235 16:47:56.369690 25, 0x0, End_B0=25 End_B1=25
8236 16:47:56.373163 26, 0x0, End_B0=26 End_B1=26
8237 16:47:56.376492 27, 0x0, End_B0=27 End_B1=27
8238 16:47:56.377068 28, 0x0, End_B0=28 End_B1=28
8239 16:47:56.379473 29, 0x0, End_B0=29 End_B1=29
8240 16:47:56.383073 30, 0x0, End_B0=30 End_B1=30
8241 16:47:56.386180 31, 0x4141, End_B0=30 End_B1=30
8242 16:47:56.389920 Byte0 end_step=30 best_step=27
8243 16:47:56.392647 Byte1 end_step=30 best_step=27
8244 16:47:56.393211 Byte0 TX OE(2T, 0.5T) = (3, 3)
8245 16:47:56.396117 Byte1 TX OE(2T, 0.5T) = (3, 3)
8246 16:47:56.396683
8247 16:47:56.397055
8248 16:47:56.406252 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8249 16:47:56.409210 CH0 RK1: MR19=303, MR18=200D
8250 16:47:56.412695 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8251 16:47:56.416503 [RxdqsGatingPostProcess] freq 1600
8252 16:47:56.423152 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8253 16:47:56.425682 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 16:47:56.429324 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 16:47:56.432480 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 16:47:56.435628 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 16:47:56.439172 best DQS0 dly(2T, 0.5T) = (1, 1)
8258 16:47:56.441879 best DQS1 dly(2T, 0.5T) = (1, 1)
8259 16:47:56.445876 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8260 16:47:56.446511 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8261 16:47:56.448993 Pre-setting of DQS Precalculation
8262 16:47:56.455573 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8263 16:47:56.456158 ==
8264 16:47:56.459058 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 16:47:56.461877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 16:47:56.462393 ==
8267 16:47:56.468303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 16:47:56.471705 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 16:47:56.475701 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 16:47:56.482061 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 16:47:56.491760 [CA 0] Center 41 (12~71) winsize 60
8272 16:47:56.494842 [CA 1] Center 42 (12~72) winsize 61
8273 16:47:56.498180 [CA 2] Center 38 (9~67) winsize 59
8274 16:47:56.501632 [CA 3] Center 37 (8~67) winsize 60
8275 16:47:56.504845 [CA 4] Center 37 (8~67) winsize 60
8276 16:47:56.508250 [CA 5] Center 37 (7~67) winsize 61
8277 16:47:56.508717
8278 16:47:56.511387 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8279 16:47:56.511960
8280 16:47:56.514763 [CATrainingPosCal] consider 1 rank data
8281 16:47:56.518799 u2DelayCellTimex100 = 290/100 ps
8282 16:47:56.521236 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8283 16:47:56.527889 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8284 16:47:56.531409 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8285 16:47:56.534810 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8286 16:47:56.538062 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8287 16:47:56.541936 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8288 16:47:56.542560
8289 16:47:56.544237 CA PerBit enable=1, Macro0, CA PI delay=37
8290 16:47:56.544700
8291 16:47:56.547415 [CBTSetCACLKResult] CA Dly = 37
8292 16:47:56.550885 CS Dly: 8 (0~39)
8293 16:47:56.554078 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 16:47:56.557882 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 16:47:56.558334 ==
8296 16:47:56.561082 Dram Type= 6, Freq= 0, CH_1, rank 1
8297 16:47:56.564167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 16:47:56.567591 ==
8299 16:47:56.570882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8300 16:47:56.573759 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8301 16:47:56.580259 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8302 16:47:56.587209 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8303 16:47:56.594823 [CA 0] Center 42 (13~71) winsize 59
8304 16:47:56.597835 [CA 1] Center 41 (12~71) winsize 60
8305 16:47:56.601476 [CA 2] Center 37 (8~67) winsize 60
8306 16:47:56.604693 [CA 3] Center 37 (8~67) winsize 60
8307 16:47:56.607885 [CA 4] Center 37 (8~67) winsize 60
8308 16:47:56.611513 [CA 5] Center 37 (7~67) winsize 61
8309 16:47:56.612077
8310 16:47:56.614381 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8311 16:47:56.614934
8312 16:47:56.618453 [CATrainingPosCal] consider 2 rank data
8313 16:47:56.621376 u2DelayCellTimex100 = 290/100 ps
8314 16:47:56.628141 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8315 16:47:56.630724 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8316 16:47:56.634159 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8317 16:47:56.637662 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8318 16:47:56.640992 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8319 16:47:56.644087 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8320 16:47:56.644548
8321 16:47:56.647428 CA PerBit enable=1, Macro0, CA PI delay=37
8322 16:47:56.647891
8323 16:47:56.650610 [CBTSetCACLKResult] CA Dly = 37
8324 16:47:56.654003 CS Dly: 9 (0~42)
8325 16:47:56.657615 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8326 16:47:56.660499 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8327 16:47:56.660961
8328 16:47:56.664170 ----->DramcWriteLeveling(PI) begin...
8329 16:47:56.664739 ==
8330 16:47:56.667422 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 16:47:56.673731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 16:47:56.674295 ==
8333 16:47:56.677599 Write leveling (Byte 0): 25 => 25
8334 16:47:56.680133 Write leveling (Byte 1): 29 => 29
8335 16:47:56.680598 DramcWriteLeveling(PI) end<-----
8336 16:47:56.680963
8337 16:47:56.683585 ==
8338 16:47:56.686793 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 16:47:56.689982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 16:47:56.690486 ==
8341 16:47:56.693683 [Gating] SW mode calibration
8342 16:47:56.700193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8343 16:47:56.703591 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8344 16:47:56.710115 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 16:47:56.713396 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 16:47:56.716551 1 4 8 | B1->B0 | 2525 2929 | 1 1 | (1 1) (1 1)
8347 16:47:56.723828 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8348 16:47:56.726540 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 16:47:56.730595 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 16:47:56.736562 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 16:47:56.739690 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 16:47:56.743285 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 16:47:56.749636 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8354 16:47:56.753217 1 5 8 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 1)
8355 16:47:56.756135 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8356 16:47:56.763081 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 16:47:56.767006 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 16:47:56.769481 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 16:47:56.776730 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 16:47:56.779313 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 16:47:56.782702 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8362 16:47:56.788960 1 6 8 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
8363 16:47:56.792788 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 16:47:56.796556 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 16:47:56.802348 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 16:47:56.806004 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 16:47:56.809222 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 16:47:56.815896 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 16:47:56.819300 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8370 16:47:56.822850 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 16:47:56.829270 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8372 16:47:56.832582 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 16:47:56.835537 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 16:47:56.842236 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 16:47:56.845374 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 16:47:56.848569 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 16:47:56.855154 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 16:47:56.859454 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 16:47:56.862341 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 16:47:56.869574 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 16:47:56.872198 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 16:47:56.875234 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 16:47:56.882045 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 16:47:56.885446 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 16:47:56.888359 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8386 16:47:56.895449 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8387 16:47:56.898717 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8388 16:47:56.901822 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 16:47:56.905743 Total UI for P1: 0, mck2ui 16
8390 16:47:56.908655 best dqsien dly found for B0: ( 1, 9, 8)
8391 16:47:56.911970 Total UI for P1: 0, mck2ui 16
8392 16:47:56.915623 best dqsien dly found for B1: ( 1, 9, 12)
8393 16:47:56.918532 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8394 16:47:56.922413 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8395 16:47:56.922984
8396 16:47:56.925198 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8397 16:47:56.931486 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8398 16:47:56.932049 [Gating] SW calibration Done
8399 16:47:56.932426 ==
8400 16:47:56.934979 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 16:47:56.942031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 16:47:56.942646 ==
8403 16:47:56.943029 RX Vref Scan: 0
8404 16:47:56.943380
8405 16:47:56.945025 RX Vref 0 -> 0, step: 1
8406 16:47:56.945508
8407 16:47:56.948062 RX Delay 0 -> 252, step: 8
8408 16:47:56.951091 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8409 16:47:56.954520 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8410 16:47:56.958815 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8411 16:47:56.964345 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8412 16:47:56.967550 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8413 16:47:56.971382 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8414 16:47:56.974504 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8415 16:47:56.977852 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8416 16:47:56.984273 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8417 16:47:56.987542 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8418 16:47:56.991138 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8419 16:47:56.994245 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8420 16:47:56.997647 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8421 16:47:57.004121 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8422 16:47:57.007054 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8423 16:47:57.010707 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8424 16:47:57.011265 ==
8425 16:47:57.013748 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 16:47:57.017227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 16:47:57.020787 ==
8428 16:47:57.021358 DQS Delay:
8429 16:47:57.021731 DQS0 = 0, DQS1 = 0
8430 16:47:57.024030 DQM Delay:
8431 16:47:57.024597 DQM0 = 138, DQM1 = 129
8432 16:47:57.027001 DQ Delay:
8433 16:47:57.030305 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8434 16:47:57.033784 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8435 16:47:57.037198 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8436 16:47:57.040289 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8437 16:47:57.040853
8438 16:47:57.041221
8439 16:47:57.041565 ==
8440 16:47:57.043430 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 16:47:57.046904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 16:47:57.047377 ==
8443 16:47:57.049939
8444 16:47:57.050428
8445 16:47:57.050806 TX Vref Scan disable
8446 16:47:57.053754 == TX Byte 0 ==
8447 16:47:57.056975 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8448 16:47:57.060136 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8449 16:47:57.063749 == TX Byte 1 ==
8450 16:47:57.067001 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8451 16:47:57.069950 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8452 16:47:57.070464 ==
8453 16:47:57.073281 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 16:47:57.079900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 16:47:57.080477 ==
8456 16:47:57.092018
8457 16:47:57.094826 TX Vref early break, caculate TX vref
8458 16:47:57.099069 TX Vref=16, minBit 15, minWin=21, winSum=371
8459 16:47:57.101672 TX Vref=18, minBit 15, minWin=21, winSum=379
8460 16:47:57.104690 TX Vref=20, minBit 15, minWin=22, winSum=388
8461 16:47:57.107917 TX Vref=22, minBit 9, minWin=24, winSum=402
8462 16:47:57.115208 TX Vref=24, minBit 13, minWin=24, winSum=409
8463 16:47:57.118037 TX Vref=26, minBit 10, minWin=25, winSum=420
8464 16:47:57.121485 TX Vref=28, minBit 9, minWin=25, winSum=423
8465 16:47:57.124734 TX Vref=30, minBit 10, minWin=24, winSum=417
8466 16:47:57.128171 TX Vref=32, minBit 10, minWin=23, winSum=410
8467 16:47:57.131288 TX Vref=34, minBit 10, minWin=23, winSum=400
8468 16:47:57.137785 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
8469 16:47:57.138386
8470 16:47:57.141506 Final TX Range 0 Vref 28
8471 16:47:57.142083
8472 16:47:57.142488 ==
8473 16:47:57.144789 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 16:47:57.148059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 16:47:57.151198 ==
8476 16:47:57.151685
8477 16:47:57.152055
8478 16:47:57.152398 TX Vref Scan disable
8479 16:47:57.157874 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8480 16:47:57.158490 == TX Byte 0 ==
8481 16:47:57.161091 u2DelayCellOfst[0]=16 cells (5 PI)
8482 16:47:57.163917 u2DelayCellOfst[1]=10 cells (3 PI)
8483 16:47:57.167458 u2DelayCellOfst[2]=0 cells (0 PI)
8484 16:47:57.171408 u2DelayCellOfst[3]=3 cells (1 PI)
8485 16:47:57.174333 u2DelayCellOfst[4]=6 cells (2 PI)
8486 16:47:57.177562 u2DelayCellOfst[5]=20 cells (6 PI)
8487 16:47:57.180939 u2DelayCellOfst[6]=16 cells (5 PI)
8488 16:47:57.184609 u2DelayCellOfst[7]=3 cells (1 PI)
8489 16:47:57.187479 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8490 16:47:57.190473 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8491 16:47:57.194017 == TX Byte 1 ==
8492 16:47:57.197992 u2DelayCellOfst[8]=0 cells (0 PI)
8493 16:47:57.201180 u2DelayCellOfst[9]=0 cells (0 PI)
8494 16:47:57.203719 u2DelayCellOfst[10]=10 cells (3 PI)
8495 16:47:57.207014 u2DelayCellOfst[11]=3 cells (1 PI)
8496 16:47:57.210465 u2DelayCellOfst[12]=13 cells (4 PI)
8497 16:47:57.211149 u2DelayCellOfst[13]=13 cells (4 PI)
8498 16:47:57.213553 u2DelayCellOfst[14]=13 cells (4 PI)
8499 16:47:57.216805 u2DelayCellOfst[15]=13 cells (4 PI)
8500 16:47:57.223778 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8501 16:47:57.226957 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8502 16:47:57.230648 DramC Write-DBI on
8503 16:47:57.231222 ==
8504 16:47:57.233728 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 16:47:57.236946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 16:47:57.237522 ==
8507 16:47:57.237902
8508 16:47:57.238251
8509 16:47:57.240394 TX Vref Scan disable
8510 16:47:57.240988 == TX Byte 0 ==
8511 16:47:57.246561 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8512 16:47:57.247122 == TX Byte 1 ==
8513 16:47:57.250241 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8514 16:47:57.253651 DramC Write-DBI off
8515 16:47:57.254228
8516 16:47:57.254668 [DATLAT]
8517 16:47:57.257250 Freq=1600, CH1 RK0
8518 16:47:57.257822
8519 16:47:57.258200 DATLAT Default: 0xf
8520 16:47:57.259968 0, 0xFFFF, sum = 0
8521 16:47:57.260549 1, 0xFFFF, sum = 0
8522 16:47:57.263671 2, 0xFFFF, sum = 0
8523 16:47:57.264261 3, 0xFFFF, sum = 0
8524 16:47:57.266842 4, 0xFFFF, sum = 0
8525 16:47:57.267426 5, 0xFFFF, sum = 0
8526 16:47:57.269989 6, 0xFFFF, sum = 0
8527 16:47:57.273497 7, 0xFFFF, sum = 0
8528 16:47:57.274078 8, 0xFFFF, sum = 0
8529 16:47:57.277178 9, 0xFFFF, sum = 0
8530 16:47:57.277758 10, 0xFFFF, sum = 0
8531 16:47:57.280133 11, 0xFFFF, sum = 0
8532 16:47:57.280735 12, 0xFFFF, sum = 0
8533 16:47:57.283371 13, 0xFFFF, sum = 0
8534 16:47:57.283847 14, 0x0, sum = 1
8535 16:47:57.286504 15, 0x0, sum = 2
8536 16:47:57.287089 16, 0x0, sum = 3
8537 16:47:57.289557 17, 0x0, sum = 4
8538 16:47:57.290036 best_step = 15
8539 16:47:57.290446
8540 16:47:57.290800 ==
8541 16:47:57.293361 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 16:47:57.296536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 16:47:57.300300 ==
8544 16:47:57.300879 RX Vref Scan: 1
8545 16:47:57.301256
8546 16:47:57.303234 Set Vref Range= 24 -> 127
8547 16:47:57.303710
8548 16:47:57.306475 RX Vref 24 -> 127, step: 1
8549 16:47:57.307052
8550 16:47:57.307430 RX Delay 19 -> 252, step: 4
8551 16:47:57.307781
8552 16:47:57.309368 Set Vref, RX VrefLevel [Byte0]: 24
8553 16:47:57.312892 [Byte1]: 24
8554 16:47:57.316795
8555 16:47:57.317468 Set Vref, RX VrefLevel [Byte0]: 25
8556 16:47:57.320318 [Byte1]: 25
8557 16:47:57.324108
8558 16:47:57.324677 Set Vref, RX VrefLevel [Byte0]: 26
8559 16:47:57.327521 [Byte1]: 26
8560 16:47:57.331777
8561 16:47:57.332373 Set Vref, RX VrefLevel [Byte0]: 27
8562 16:47:57.335403 [Byte1]: 27
8563 16:47:57.339667
8564 16:47:57.340241 Set Vref, RX VrefLevel [Byte0]: 28
8565 16:47:57.342512 [Byte1]: 28
8566 16:47:57.347058
8567 16:47:57.347663 Set Vref, RX VrefLevel [Byte0]: 29
8568 16:47:57.350101 [Byte1]: 29
8569 16:47:57.354619
8570 16:47:57.355192 Set Vref, RX VrefLevel [Byte0]: 30
8571 16:47:57.358503 [Byte1]: 30
8572 16:47:57.362251
8573 16:47:57.362892 Set Vref, RX VrefLevel [Byte0]: 31
8574 16:47:57.365646 [Byte1]: 31
8575 16:47:57.370231
8576 16:47:57.370866 Set Vref, RX VrefLevel [Byte0]: 32
8577 16:47:57.373334 [Byte1]: 32
8578 16:47:57.377354
8579 16:47:57.377928 Set Vref, RX VrefLevel [Byte0]: 33
8580 16:47:57.380534 [Byte1]: 33
8581 16:47:57.384816
8582 16:47:57.385441 Set Vref, RX VrefLevel [Byte0]: 34
8583 16:47:57.388181 [Byte1]: 34
8584 16:47:57.392317
8585 16:47:57.392895 Set Vref, RX VrefLevel [Byte0]: 35
8586 16:47:57.395612 [Byte1]: 35
8587 16:47:57.400132
8588 16:47:57.400726 Set Vref, RX VrefLevel [Byte0]: 36
8589 16:47:57.403057 [Byte1]: 36
8590 16:47:57.407835
8591 16:47:57.408411 Set Vref, RX VrefLevel [Byte0]: 37
8592 16:47:57.411014 [Byte1]: 37
8593 16:47:57.415777
8594 16:47:57.416352 Set Vref, RX VrefLevel [Byte0]: 38
8595 16:47:57.418599 [Byte1]: 38
8596 16:47:57.422995
8597 16:47:57.423560 Set Vref, RX VrefLevel [Byte0]: 39
8598 16:47:57.426028 [Byte1]: 39
8599 16:47:57.430474
8600 16:47:57.431044 Set Vref, RX VrefLevel [Byte0]: 40
8601 16:47:57.433489 [Byte1]: 40
8602 16:47:57.438090
8603 16:47:57.438762 Set Vref, RX VrefLevel [Byte0]: 41
8604 16:47:57.441178 [Byte1]: 41
8605 16:47:57.445476
8606 16:47:57.446104 Set Vref, RX VrefLevel [Byte0]: 42
8607 16:47:57.448612 [Byte1]: 42
8608 16:47:57.453496
8609 16:47:57.454056 Set Vref, RX VrefLevel [Byte0]: 43
8610 16:47:57.456344 [Byte1]: 43
8611 16:47:57.460947
8612 16:47:57.461510 Set Vref, RX VrefLevel [Byte0]: 44
8613 16:47:57.464661 [Byte1]: 44
8614 16:47:57.467998
8615 16:47:57.468486 Set Vref, RX VrefLevel [Byte0]: 45
8616 16:47:57.471503 [Byte1]: 45
8617 16:47:57.475760
8618 16:47:57.476324 Set Vref, RX VrefLevel [Byte0]: 46
8619 16:47:57.479274 [Byte1]: 46
8620 16:47:57.483220
8621 16:47:57.483777 Set Vref, RX VrefLevel [Byte0]: 47
8622 16:47:57.486648 [Byte1]: 47
8623 16:47:57.491323
8624 16:47:57.491884 Set Vref, RX VrefLevel [Byte0]: 48
8625 16:47:57.493982 [Byte1]: 48
8626 16:47:57.498902
8627 16:47:57.499470 Set Vref, RX VrefLevel [Byte0]: 49
8628 16:47:57.501974 [Byte1]: 49
8629 16:47:57.506441
8630 16:47:57.507006 Set Vref, RX VrefLevel [Byte0]: 50
8631 16:47:57.509095 [Byte1]: 50
8632 16:47:57.514216
8633 16:47:57.514844 Set Vref, RX VrefLevel [Byte0]: 51
8634 16:47:57.517157 [Byte1]: 51
8635 16:47:57.521022
8636 16:47:57.521488 Set Vref, RX VrefLevel [Byte0]: 52
8637 16:47:57.524875 [Byte1]: 52
8638 16:47:57.528827
8639 16:47:57.529392 Set Vref, RX VrefLevel [Byte0]: 53
8640 16:47:57.532139 [Byte1]: 53
8641 16:47:57.536147
8642 16:47:57.536705 Set Vref, RX VrefLevel [Byte0]: 54
8643 16:47:57.539635 [Byte1]: 54
8644 16:47:57.543815
8645 16:47:57.544378 Set Vref, RX VrefLevel [Byte0]: 55
8646 16:47:57.547290 [Byte1]: 55
8647 16:47:57.551184
8648 16:47:57.551649 Set Vref, RX VrefLevel [Byte0]: 56
8649 16:47:57.554649 [Byte1]: 56
8650 16:47:57.559334
8651 16:47:57.559900 Set Vref, RX VrefLevel [Byte0]: 57
8652 16:47:57.562439 [Byte1]: 57
8653 16:47:57.566612
8654 16:47:57.567169 Set Vref, RX VrefLevel [Byte0]: 58
8655 16:47:57.569584 [Byte1]: 58
8656 16:47:57.574117
8657 16:47:57.574719 Set Vref, RX VrefLevel [Byte0]: 59
8658 16:47:57.577702 [Byte1]: 59
8659 16:47:57.581862
8660 16:47:57.582501 Set Vref, RX VrefLevel [Byte0]: 60
8661 16:47:57.584998 [Byte1]: 60
8662 16:47:57.589444
8663 16:47:57.590083 Set Vref, RX VrefLevel [Byte0]: 61
8664 16:47:57.592651 [Byte1]: 61
8665 16:47:57.596784
8666 16:47:57.597362 Set Vref, RX VrefLevel [Byte0]: 62
8667 16:47:57.600664 [Byte1]: 62
8668 16:47:57.604755
8669 16:47:57.605317 Set Vref, RX VrefLevel [Byte0]: 63
8670 16:47:57.608718 [Byte1]: 63
8671 16:47:57.612481
8672 16:47:57.613043 Set Vref, RX VrefLevel [Byte0]: 64
8673 16:47:57.615151 [Byte1]: 64
8674 16:47:57.619592
8675 16:47:57.620156 Set Vref, RX VrefLevel [Byte0]: 65
8676 16:47:57.622856 [Byte1]: 65
8677 16:47:57.627175
8678 16:47:57.627735 Set Vref, RX VrefLevel [Byte0]: 66
8679 16:47:57.631059 [Byte1]: 66
8680 16:47:57.635054
8681 16:47:57.635620 Set Vref, RX VrefLevel [Byte0]: 67
8682 16:47:57.638218 [Byte1]: 67
8683 16:47:57.642538
8684 16:47:57.643097 Set Vref, RX VrefLevel [Byte0]: 68
8685 16:47:57.645474 [Byte1]: 68
8686 16:47:57.650148
8687 16:47:57.650860 Set Vref, RX VrefLevel [Byte0]: 69
8688 16:47:57.653077 [Byte1]: 69
8689 16:47:57.657662
8690 16:47:57.658181 Set Vref, RX VrefLevel [Byte0]: 70
8691 16:47:57.660611 [Byte1]: 70
8692 16:47:57.665003
8693 16:47:57.665564 Set Vref, RX VrefLevel [Byte0]: 71
8694 16:47:57.668519 [Byte1]: 71
8695 16:47:57.672784
8696 16:47:57.673251 Set Vref, RX VrefLevel [Byte0]: 72
8697 16:47:57.675966 [Byte1]: 72
8698 16:47:57.680884
8699 16:47:57.681448 Set Vref, RX VrefLevel [Byte0]: 73
8700 16:47:57.683227 [Byte1]: 73
8701 16:47:57.688893
8702 16:47:57.689457 Set Vref, RX VrefLevel [Byte0]: 74
8703 16:47:57.690943 [Byte1]: 74
8704 16:47:57.695588
8705 16:47:57.696151 Final RX Vref Byte 0 = 53 to rank0
8706 16:47:57.698873 Final RX Vref Byte 1 = 65 to rank0
8707 16:47:57.702029 Final RX Vref Byte 0 = 53 to rank1
8708 16:47:57.705513 Final RX Vref Byte 1 = 65 to rank1==
8709 16:47:57.708917 Dram Type= 6, Freq= 0, CH_1, rank 0
8710 16:47:57.715167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8711 16:47:57.715736 ==
8712 16:47:57.716111 DQS Delay:
8713 16:47:57.716461 DQS0 = 0, DQS1 = 0
8714 16:47:57.718726 DQM Delay:
8715 16:47:57.719290 DQM0 = 134, DQM1 = 129
8716 16:47:57.722191 DQ Delay:
8717 16:47:57.725461 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =132
8718 16:47:57.728603 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =130
8719 16:47:57.732076 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8720 16:47:57.734878 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8721 16:47:57.735348
8722 16:47:57.735718
8723 16:47:57.736061
8724 16:47:57.738428 [DramC_TX_OE_Calibration] TA2
8725 16:47:57.741676 Original DQ_B0 (3 6) =30, OEN = 27
8726 16:47:57.745187 Original DQ_B1 (3 6) =30, OEN = 27
8727 16:47:57.748469 24, 0x0, End_B0=24 End_B1=24
8728 16:47:57.748956 25, 0x0, End_B0=25 End_B1=25
8729 16:47:57.751503 26, 0x0, End_B0=26 End_B1=26
8730 16:47:57.755562 27, 0x0, End_B0=27 End_B1=27
8731 16:47:57.757993 28, 0x0, End_B0=28 End_B1=28
8732 16:47:57.761803 29, 0x0, End_B0=29 End_B1=29
8733 16:47:57.762439 30, 0x0, End_B0=30 End_B1=30
8734 16:47:57.765284 31, 0x5151, End_B0=30 End_B1=30
8735 16:47:57.768142 Byte0 end_step=30 best_step=27
8736 16:47:57.771412 Byte1 end_step=30 best_step=27
8737 16:47:57.774699 Byte0 TX OE(2T, 0.5T) = (3, 3)
8738 16:47:57.778391 Byte1 TX OE(2T, 0.5T) = (3, 3)
8739 16:47:57.778976
8740 16:47:57.779350
8741 16:47:57.784911 [DQSOSCAuto] RK0, (LSB)MR18= 0x1827, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8742 16:47:57.788045 CH1 RK0: MR19=303, MR18=1827
8743 16:47:57.794743 CH1_RK0: MR19=0x303, MR18=0x1827, DQSOSC=390, MR23=63, INC=24, DEC=16
8744 16:47:57.795311
8745 16:47:57.798024 ----->DramcWriteLeveling(PI) begin...
8746 16:47:57.798626 ==
8747 16:47:57.801411 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 16:47:57.804717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 16:47:57.805350 ==
8750 16:47:57.808363 Write leveling (Byte 0): 26 => 26
8751 16:47:57.810951 Write leveling (Byte 1): 27 => 27
8752 16:47:57.814761 DramcWriteLeveling(PI) end<-----
8753 16:47:57.815332
8754 16:47:57.815707 ==
8755 16:47:57.817675 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 16:47:57.821191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 16:47:57.821762 ==
8758 16:47:57.824620 [Gating] SW mode calibration
8759 16:47:57.831005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8760 16:47:57.837507 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8761 16:47:57.840899 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 16:47:57.847640 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 16:47:57.850544 1 4 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8764 16:47:57.853764 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8765 16:47:57.860366 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 16:47:57.863946 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 16:47:57.867036 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 16:47:57.873977 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 16:47:57.876821 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 16:47:57.880374 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 16:47:57.886993 1 5 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 0) (1 0)
8772 16:47:57.890388 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (1 0) (1 1)
8773 16:47:57.893497 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 16:47:57.900134 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 16:47:57.903678 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 16:47:57.907031 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 16:47:57.913777 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 16:47:57.916936 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 16:47:57.919841 1 6 8 | B1->B0 | 3333 2323 | 0 0 | (1 1) (0 0)
8780 16:47:57.926509 1 6 12 | B1->B0 | 4646 3131 | 0 1 | (0 0) (0 0)
8781 16:47:57.930058 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 16:47:57.933686 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 16:47:57.939921 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 16:47:57.943259 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 16:47:57.946334 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 16:47:57.953230 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 16:47:57.956331 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8788 16:47:57.959724 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8789 16:47:57.966096 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8790 16:47:57.969472 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 16:47:57.972883 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 16:47:57.979179 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 16:47:57.983046 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 16:47:57.985733 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 16:47:57.992242 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 16:47:57.996542 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 16:47:57.999282 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 16:47:58.006190 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 16:47:58.009428 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 16:47:58.012376 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 16:47:58.018918 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 16:47:58.022120 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 16:47:58.025588 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8804 16:47:58.032990 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 16:47:58.033569 Total UI for P1: 0, mck2ui 16
8806 16:47:58.038668 best dqsien dly found for B0: ( 1, 9, 8)
8807 16:47:58.039142 Total UI for P1: 0, mck2ui 16
8808 16:47:58.042040 best dqsien dly found for B1: ( 1, 9, 8)
8809 16:47:58.048779 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8810 16:47:58.051800 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8811 16:47:58.052489
8812 16:47:58.055017 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8813 16:47:58.058757 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8814 16:47:58.062181 [Gating] SW calibration Done
8815 16:47:58.062794 ==
8816 16:47:58.065195 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 16:47:58.068145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 16:47:58.068621 ==
8819 16:47:58.071754 RX Vref Scan: 0
8820 16:47:58.072430
8821 16:47:58.072896 RX Vref 0 -> 0, step: 1
8822 16:47:58.073259
8823 16:47:58.075079 RX Delay 0 -> 252, step: 8
8824 16:47:58.078340 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8825 16:47:58.081920 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8826 16:47:58.088105 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8827 16:47:58.091865 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8828 16:47:58.094948 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8829 16:47:58.098254 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8830 16:47:58.101680 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8831 16:47:58.108884 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8832 16:47:58.111428 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8833 16:47:58.115155 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8834 16:47:58.118496 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8835 16:47:58.121601 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8836 16:47:58.128143 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8837 16:47:58.131561 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8838 16:47:58.134698 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8839 16:47:58.138105 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8840 16:47:58.138727 ==
8841 16:47:58.141316 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 16:47:58.148096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 16:47:58.148679 ==
8844 16:47:58.149058 DQS Delay:
8845 16:47:58.152224 DQS0 = 0, DQS1 = 0
8846 16:47:58.152876 DQM Delay:
8847 16:47:58.153306 DQM0 = 138, DQM1 = 130
8848 16:47:58.154488 DQ Delay:
8849 16:47:58.158380 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8850 16:47:58.161316 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8851 16:47:58.164979 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8852 16:47:58.168622 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8853 16:47:58.169194
8854 16:47:58.169567
8855 16:47:58.169920 ==
8856 16:47:58.170976 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 16:47:58.178086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 16:47:58.178756 ==
8859 16:47:58.179274
8860 16:47:58.179773
8861 16:47:58.180133 TX Vref Scan disable
8862 16:47:58.180850 == TX Byte 0 ==
8863 16:47:58.184206 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8864 16:47:58.191258 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8865 16:47:58.191856 == TX Byte 1 ==
8866 16:47:58.193993 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8867 16:47:58.201275 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8868 16:47:58.201866 ==
8869 16:47:58.204681 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 16:47:58.207603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 16:47:58.208180 ==
8872 16:47:58.219780
8873 16:47:58.223186 TX Vref early break, caculate TX vref
8874 16:47:58.226799 TX Vref=16, minBit 0, minWin=23, winSum=393
8875 16:47:58.229926 TX Vref=18, minBit 13, minWin=23, winSum=397
8876 16:47:58.233232 TX Vref=20, minBit 9, minWin=24, winSum=411
8877 16:47:58.236410 TX Vref=22, minBit 9, minWin=25, winSum=419
8878 16:47:58.239489 TX Vref=24, minBit 5, minWin=25, winSum=420
8879 16:47:58.246275 TX Vref=26, minBit 9, minWin=25, winSum=430
8880 16:47:58.249859 TX Vref=28, minBit 0, minWin=26, winSum=431
8881 16:47:58.252818 TX Vref=30, minBit 9, minWin=25, winSum=425
8882 16:47:58.256024 TX Vref=32, minBit 5, minWin=25, winSum=417
8883 16:47:58.259699 TX Vref=34, minBit 0, minWin=24, winSum=406
8884 16:47:58.266643 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8885 16:47:58.267232
8886 16:47:58.269741 Final TX Range 0 Vref 28
8887 16:47:58.270217
8888 16:47:58.270640 ==
8889 16:47:58.272475 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 16:47:58.276310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 16:47:58.276893 ==
8892 16:47:58.277277
8893 16:47:58.277624
8894 16:47:58.279640 TX Vref Scan disable
8895 16:47:58.285930 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8896 16:47:58.286732 == TX Byte 0 ==
8897 16:47:58.289596 u2DelayCellOfst[0]=16 cells (5 PI)
8898 16:47:58.292209 u2DelayCellOfst[1]=10 cells (3 PI)
8899 16:47:58.295525 u2DelayCellOfst[2]=0 cells (0 PI)
8900 16:47:58.299088 u2DelayCellOfst[3]=6 cells (2 PI)
8901 16:47:58.302524 u2DelayCellOfst[4]=10 cells (3 PI)
8902 16:47:58.305578 u2DelayCellOfst[5]=20 cells (6 PI)
8903 16:47:58.309149 u2DelayCellOfst[6]=20 cells (6 PI)
8904 16:47:58.312426 u2DelayCellOfst[7]=6 cells (2 PI)
8905 16:47:58.315417 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8906 16:47:58.319101 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8907 16:47:58.322315 == TX Byte 1 ==
8908 16:47:58.325418 u2DelayCellOfst[8]=0 cells (0 PI)
8909 16:47:58.329202 u2DelayCellOfst[9]=3 cells (1 PI)
8910 16:47:58.329781 u2DelayCellOfst[10]=6 cells (2 PI)
8911 16:47:58.332212 u2DelayCellOfst[11]=3 cells (1 PI)
8912 16:47:58.335071 u2DelayCellOfst[12]=10 cells (3 PI)
8913 16:47:58.338173 u2DelayCellOfst[13]=10 cells (3 PI)
8914 16:47:58.341786 u2DelayCellOfst[14]=16 cells (5 PI)
8915 16:47:58.345908 u2DelayCellOfst[15]=13 cells (4 PI)
8916 16:47:58.351537 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8917 16:47:58.354753 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8918 16:47:58.355227 DramC Write-DBI on
8919 16:47:58.358305 ==
8920 16:47:58.358922 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 16:47:58.365166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 16:47:58.365749 ==
8923 16:47:58.366130
8924 16:47:58.366517
8925 16:47:58.367838 TX Vref Scan disable
8926 16:47:58.368305 == TX Byte 0 ==
8927 16:47:58.374599 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8928 16:47:58.375072 == TX Byte 1 ==
8929 16:47:58.378526 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8930 16:47:58.381189 DramC Write-DBI off
8931 16:47:58.381764
8932 16:47:58.382139 [DATLAT]
8933 16:47:58.384377 Freq=1600, CH1 RK1
8934 16:47:58.384962
8935 16:47:58.385339 DATLAT Default: 0xf
8936 16:47:58.388356 0, 0xFFFF, sum = 0
8937 16:47:58.388871 1, 0xFFFF, sum = 0
8938 16:47:58.390935 2, 0xFFFF, sum = 0
8939 16:47:58.391415 3, 0xFFFF, sum = 0
8940 16:47:58.394465 4, 0xFFFF, sum = 0
8941 16:47:58.395051 5, 0xFFFF, sum = 0
8942 16:47:58.397576 6, 0xFFFF, sum = 0
8943 16:47:58.400403 7, 0xFFFF, sum = 0
8944 16:47:58.401002 8, 0xFFFF, sum = 0
8945 16:47:58.404373 9, 0xFFFF, sum = 0
8946 16:47:58.404964 10, 0xFFFF, sum = 0
8947 16:47:58.407283 11, 0xFFFF, sum = 0
8948 16:47:58.407763 12, 0xFFFF, sum = 0
8949 16:47:58.410714 13, 0xFFFF, sum = 0
8950 16:47:58.411300 14, 0x0, sum = 1
8951 16:47:58.413969 15, 0x0, sum = 2
8952 16:47:58.414598 16, 0x0, sum = 3
8953 16:47:58.417177 17, 0x0, sum = 4
8954 16:47:58.417656 best_step = 15
8955 16:47:58.418034
8956 16:47:58.418415 ==
8957 16:47:58.421440 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 16:47:58.424530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 16:47:58.427909 ==
8960 16:47:58.428484 RX Vref Scan: 0
8961 16:47:58.428863
8962 16:47:58.430445 RX Vref 0 -> 0, step: 1
8963 16:47:58.430917
8964 16:47:58.434119 RX Delay 19 -> 252, step: 4
8965 16:47:58.437634 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8966 16:47:58.440802 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
8967 16:47:58.444824 iDelay=195, Bit 2, Center 124 (79 ~ 170) 92
8968 16:47:58.447019 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8969 16:47:58.453597 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8970 16:47:58.456994 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8971 16:47:58.461242 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8972 16:47:58.464034 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
8973 16:47:58.467098 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8974 16:47:58.469952 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8975 16:47:58.477104 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8976 16:47:58.480331 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8977 16:47:58.483796 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8978 16:47:58.487275 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8979 16:47:58.494128 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8980 16:47:58.497449 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8981 16:47:58.498023 ==
8982 16:47:58.500057 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 16:47:58.503580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 16:47:58.504156 ==
8985 16:47:58.506665 DQS Delay:
8986 16:47:58.507286 DQS0 = 0, DQS1 = 0
8987 16:47:58.507686 DQM Delay:
8988 16:47:58.509801 DQM0 = 134, DQM1 = 129
8989 16:47:58.510407 DQ Delay:
8990 16:47:58.513336 DQ0 =136, DQ1 =130, DQ2 =124, DQ3 =130
8991 16:47:58.516335 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
8992 16:47:58.520109 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
8993 16:47:58.526144 DQ12 =136, DQ13 =136, DQ14 =138, DQ15 =138
8994 16:47:58.526735
8995 16:47:58.527114
8996 16:47:58.527461
8997 16:47:58.529416 [DramC_TX_OE_Calibration] TA2
8998 16:47:58.533192 Original DQ_B0 (3 6) =30, OEN = 27
8999 16:47:58.536213 Original DQ_B1 (3 6) =30, OEN = 27
9000 16:47:58.536690 24, 0x0, End_B0=24 End_B1=24
9001 16:47:58.539617 25, 0x0, End_B0=25 End_B1=25
9002 16:47:58.542883 26, 0x0, End_B0=26 End_B1=26
9003 16:47:58.546070 27, 0x0, End_B0=27 End_B1=27
9004 16:47:58.546694 28, 0x0, End_B0=28 End_B1=28
9005 16:47:58.549354 29, 0x0, End_B0=29 End_B1=29
9006 16:47:58.553229 30, 0x0, End_B0=30 End_B1=30
9007 16:47:58.556120 31, 0x4141, End_B0=30 End_B1=30
9008 16:47:58.559106 Byte0 end_step=30 best_step=27
9009 16:47:58.562295 Byte1 end_step=30 best_step=27
9010 16:47:58.562807 Byte0 TX OE(2T, 0.5T) = (3, 3)
9011 16:47:58.566284 Byte1 TX OE(2T, 0.5T) = (3, 3)
9012 16:47:58.566914
9013 16:47:58.567292
9014 16:47:58.575833 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9015 16:47:58.579234 CH1 RK1: MR19=303, MR18=1A05
9016 16:47:58.582932 CH1_RK1: MR19=0x303, MR18=0x1A05, DQSOSC=396, MR23=63, INC=23, DEC=15
9017 16:47:58.586484 [RxdqsGatingPostProcess] freq 1600
9018 16:47:58.592397 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9019 16:47:58.595943 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 16:47:58.599192 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 16:47:58.602418 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 16:47:58.606060 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 16:47:58.608673 best DQS0 dly(2T, 0.5T) = (1, 1)
9024 16:47:58.612183 best DQS1 dly(2T, 0.5T) = (1, 1)
9025 16:47:58.615327 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9026 16:47:58.618799 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9027 16:47:58.619269 Pre-setting of DQS Precalculation
9028 16:47:58.626128 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9029 16:47:58.631822 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9030 16:47:58.638741 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9031 16:47:58.639302
9032 16:47:58.639677
9033 16:47:58.641562 [Calibration Summary] 3200 Mbps
9034 16:47:58.645572 CH 0, Rank 0
9035 16:47:58.646150 SW Impedance : PASS
9036 16:47:58.648704 DUTY Scan : NO K
9037 16:47:58.651639 ZQ Calibration : PASS
9038 16:47:58.652106 Jitter Meter : NO K
9039 16:47:58.654772 CBT Training : PASS
9040 16:47:58.658121 Write leveling : PASS
9041 16:47:58.658633 RX DQS gating : PASS
9042 16:47:58.661843 RX DQ/DQS(RDDQC) : PASS
9043 16:47:58.664886 TX DQ/DQS : PASS
9044 16:47:58.665454 RX DATLAT : PASS
9045 16:47:58.667681 RX DQ/DQS(Engine): PASS
9046 16:47:58.671267 TX OE : PASS
9047 16:47:58.671895 All Pass.
9048 16:47:58.672275
9049 16:47:58.672625 CH 0, Rank 1
9050 16:47:58.674308 SW Impedance : PASS
9051 16:47:58.677960 DUTY Scan : NO K
9052 16:47:58.678571 ZQ Calibration : PASS
9053 16:47:58.681396 Jitter Meter : NO K
9054 16:47:58.684205 CBT Training : PASS
9055 16:47:58.684678 Write leveling : PASS
9056 16:47:58.687753 RX DQS gating : PASS
9057 16:47:58.691344 RX DQ/DQS(RDDQC) : PASS
9058 16:47:58.691808 TX DQ/DQS : PASS
9059 16:47:58.694788 RX DATLAT : PASS
9060 16:47:58.695350 RX DQ/DQS(Engine): PASS
9061 16:47:58.697711 TX OE : PASS
9062 16:47:58.698283 All Pass.
9063 16:47:58.698759
9064 16:47:58.701270 CH 1, Rank 0
9065 16:47:58.701833 SW Impedance : PASS
9066 16:47:58.704481 DUTY Scan : NO K
9067 16:47:58.707501 ZQ Calibration : PASS
9068 16:47:58.708077 Jitter Meter : NO K
9069 16:47:58.710683 CBT Training : PASS
9070 16:47:58.714698 Write leveling : PASS
9071 16:47:58.715277 RX DQS gating : PASS
9072 16:47:58.717650 RX DQ/DQS(RDDQC) : PASS
9073 16:47:58.720733 TX DQ/DQS : PASS
9074 16:47:58.721271 RX DATLAT : PASS
9075 16:47:58.723862 RX DQ/DQS(Engine): PASS
9076 16:47:58.727273 TX OE : PASS
9077 16:47:58.727933 All Pass.
9078 16:47:58.728414
9079 16:47:58.728862 CH 1, Rank 1
9080 16:47:58.730741 SW Impedance : PASS
9081 16:47:58.733731 DUTY Scan : NO K
9082 16:47:58.734199 ZQ Calibration : PASS
9083 16:47:58.736834 Jitter Meter : NO K
9084 16:47:58.740706 CBT Training : PASS
9085 16:47:58.741292 Write leveling : PASS
9086 16:47:58.743855 RX DQS gating : PASS
9087 16:47:58.747631 RX DQ/DQS(RDDQC) : PASS
9088 16:47:58.748207 TX DQ/DQS : PASS
9089 16:47:58.750603 RX DATLAT : PASS
9090 16:47:58.753828 RX DQ/DQS(Engine): PASS
9091 16:47:58.754474 TX OE : PASS
9092 16:47:58.754864 All Pass.
9093 16:47:58.757241
9094 16:47:58.757710 DramC Write-DBI on
9095 16:47:58.760339 PER_BANK_REFRESH: Hybrid Mode
9096 16:47:58.760916 TX_TRACKING: ON
9097 16:47:58.770499 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9098 16:47:58.776920 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9099 16:47:58.786822 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9100 16:47:58.790796 [FAST_K] Save calibration result to emmc
9101 16:47:58.793525 sync common calibartion params.
9102 16:47:58.794114 sync cbt_mode0:1, 1:1
9103 16:47:58.797040 dram_init: ddr_geometry: 2
9104 16:47:58.799572 dram_init: ddr_geometry: 2
9105 16:47:58.800048 dram_init: ddr_geometry: 2
9106 16:47:58.803512 0:dram_rank_size:100000000
9107 16:47:58.806744 1:dram_rank_size:100000000
9108 16:47:58.813448 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9109 16:47:58.814025 DFS_SHUFFLE_HW_MODE: ON
9110 16:47:58.816203 dramc_set_vcore_voltage set vcore to 725000
9111 16:47:58.820398 Read voltage for 1600, 0
9112 16:47:58.820969 Vio18 = 0
9113 16:47:58.823038 Vcore = 725000
9114 16:47:58.823563 Vdram = 0
9115 16:47:58.823947 Vddq = 0
9116 16:47:58.826579 Vmddr = 0
9117 16:47:58.827052 switch to 3200 Mbps bootup
9118 16:47:58.829848 [DramcRunTimeConfig]
9119 16:47:58.830462 PHYPLL
9120 16:47:58.832789 DPM_CONTROL_AFTERK: ON
9121 16:47:58.833263 PER_BANK_REFRESH: ON
9122 16:47:58.836421 REFRESH_OVERHEAD_REDUCTION: ON
9123 16:47:58.839356 CMD_PICG_NEW_MODE: OFF
9124 16:47:58.839832 XRTWTW_NEW_MODE: ON
9125 16:47:58.843260 XRTRTR_NEW_MODE: ON
9126 16:47:58.843777 TX_TRACKING: ON
9127 16:47:58.846309 RDSEL_TRACKING: OFF
9128 16:47:58.849433 DQS Precalculation for DVFS: ON
9129 16:47:58.850187 RX_TRACKING: OFF
9130 16:47:58.853156 HW_GATING DBG: ON
9131 16:47:58.853727 ZQCS_ENABLE_LP4: ON
9132 16:47:58.855732 RX_PICG_NEW_MODE: ON
9133 16:47:58.856430 TX_PICG_NEW_MODE: ON
9134 16:47:58.859527 ENABLE_RX_DCM_DPHY: ON
9135 16:47:58.862824 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9136 16:47:58.865838 DUMMY_READ_FOR_TRACKING: OFF
9137 16:47:58.869035 !!! SPM_CONTROL_AFTERK: OFF
9138 16:47:58.869634 !!! SPM could not control APHY
9139 16:47:58.872527 IMPEDANCE_TRACKING: ON
9140 16:47:58.873054 TEMP_SENSOR: ON
9141 16:47:58.875802 HW_SAVE_FOR_SR: OFF
9142 16:47:58.879232 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9143 16:47:58.882260 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9144 16:47:58.885576 Read ODT Tracking: ON
9145 16:47:58.886154 Refresh Rate DeBounce: ON
9146 16:47:58.888772 DFS_NO_QUEUE_FLUSH: ON
9147 16:47:58.892413 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9148 16:47:58.895241 ENABLE_DFS_RUNTIME_MRW: OFF
9149 16:47:58.895790 DDR_RESERVE_NEW_MODE: ON
9150 16:47:58.899269 MR_CBT_SWITCH_FREQ: ON
9151 16:47:58.902291 =========================
9152 16:47:58.920279 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9153 16:47:58.923100 dram_init: ddr_geometry: 2
9154 16:47:58.941171 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9155 16:47:58.945068 dram_init: dram init end (result: 0)
9156 16:47:58.951295 DRAM-K: Full calibration passed in 24507 msecs
9157 16:47:58.954277 MRC: failed to locate region type 0.
9158 16:47:58.954846 DRAM rank0 size:0x100000000,
9159 16:47:58.957647 DRAM rank1 size=0x100000000
9160 16:47:58.967649 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9161 16:47:58.974470 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9162 16:47:58.982018 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9163 16:47:58.987859 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9164 16:47:58.991313 DRAM rank0 size:0x100000000,
9165 16:47:58.994698 DRAM rank1 size=0x100000000
9166 16:47:58.995264 CBMEM:
9167 16:47:58.998445 IMD: root @ 0xfffff000 254 entries.
9168 16:47:59.000983 IMD: root @ 0xffffec00 62 entries.
9169 16:47:59.004870 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9170 16:47:59.007574 WARNING: RO_VPD is uninitialized or empty.
9171 16:47:59.014246 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9172 16:47:59.022153 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9173 16:47:59.034179 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9174 16:47:59.045642 BS: romstage times (exec / console): total (unknown) / 24007 ms
9175 16:47:59.046225
9176 16:47:59.046658
9177 16:47:59.055513 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9178 16:47:59.058680 ARM64: Exception handlers installed.
9179 16:47:59.061679 ARM64: Testing exception
9180 16:47:59.065352 ARM64: Done test exception
9181 16:47:59.065872 Enumerating buses...
9182 16:47:59.068499 Show all devs... Before device enumeration.
9183 16:47:59.071672 Root Device: enabled 1
9184 16:47:59.075024 CPU_CLUSTER: 0: enabled 1
9185 16:47:59.075499 CPU: 00: enabled 1
9186 16:47:59.078433 Compare with tree...
9187 16:47:59.078916 Root Device: enabled 1
9188 16:47:59.081782 CPU_CLUSTER: 0: enabled 1
9189 16:47:59.085832 CPU: 00: enabled 1
9190 16:47:59.086446 Root Device scanning...
9191 16:47:59.088502 scan_static_bus for Root Device
9192 16:47:59.091693 CPU_CLUSTER: 0 enabled
9193 16:47:59.095027 scan_static_bus for Root Device done
9194 16:47:59.098389 scan_bus: bus Root Device finished in 8 msecs
9195 16:47:59.098956 done
9196 16:47:59.104835 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9197 16:47:59.108479 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9198 16:47:59.114549 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9199 16:47:59.118085 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9200 16:47:59.121733 Allocating resources...
9201 16:47:59.124287 Reading resources...
9202 16:47:59.128149 Root Device read_resources bus 0 link: 0
9203 16:47:59.131126 DRAM rank0 size:0x100000000,
9204 16:47:59.131691 DRAM rank1 size=0x100000000
9205 16:47:59.137870 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9206 16:47:59.138476 CPU: 00 missing read_resources
9207 16:47:59.145503 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9208 16:47:59.147941 Root Device read_resources bus 0 link: 0 done
9209 16:47:59.151295 Done reading resources.
9210 16:47:59.154279 Show resources in subtree (Root Device)...After reading.
9211 16:47:59.157311 Root Device child on link 0 CPU_CLUSTER: 0
9212 16:47:59.160615 CPU_CLUSTER: 0 child on link 0 CPU: 00
9213 16:47:59.170526 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9214 16:47:59.171081 CPU: 00
9215 16:47:59.177323 Root Device assign_resources, bus 0 link: 0
9216 16:47:59.180857 CPU_CLUSTER: 0 missing set_resources
9217 16:47:59.184122 Root Device assign_resources, bus 0 link: 0 done
9218 16:47:59.184712 Done setting resources.
9219 16:47:59.190749 Show resources in subtree (Root Device)...After assigning values.
9220 16:47:59.194277 Root Device child on link 0 CPU_CLUSTER: 0
9221 16:47:59.200775 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 16:47:59.207264 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 16:47:59.210397 CPU: 00
9224 16:47:59.210990 Done allocating resources.
9225 16:47:59.217062 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9226 16:47:59.217633 Enabling resources...
9227 16:47:59.220082 done.
9228 16:47:59.223006 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9229 16:47:59.226923 Initializing devices...
9230 16:47:59.227485 Root Device init
9231 16:47:59.230118 init hardware done!
9232 16:47:59.230727 0x00000018: ctrlr->caps
9233 16:47:59.233200 52.000 MHz: ctrlr->f_max
9234 16:47:59.236482 0.400 MHz: ctrlr->f_min
9235 16:47:59.239800 0x40ff8080: ctrlr->voltages
9236 16:47:59.240386 sclk: 390625
9237 16:47:59.240767 Bus Width = 1
9238 16:47:59.243055 sclk: 390625
9239 16:47:59.243623 Bus Width = 1
9240 16:47:59.246994 Early init status = 3
9241 16:47:59.249597 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9242 16:47:59.252847 in-header: 03 fc 00 00 01 00 00 00
9243 16:47:59.256644 in-data: 00
9244 16:47:59.259544 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9245 16:47:59.264595 in-header: 03 fd 00 00 00 00 00 00
9246 16:47:59.267298 in-data:
9247 16:47:59.270729 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9248 16:47:59.274592 in-header: 03 fc 00 00 01 00 00 00
9249 16:47:59.278833 in-data: 00
9250 16:47:59.281505 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9251 16:47:59.286998 in-header: 03 fd 00 00 00 00 00 00
9252 16:47:59.290996 in-data:
9253 16:47:59.293538 [SSUSB] Setting up USB HOST controller...
9254 16:47:59.297143 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9255 16:47:59.300462 [SSUSB] phy power-on done.
9256 16:47:59.303647 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9257 16:47:59.310174 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9258 16:47:59.314288 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9259 16:47:59.320682 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9260 16:47:59.327030 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9261 16:47:59.333557 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9262 16:47:59.340704 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9263 16:47:59.347307 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9264 16:47:59.350110 SPM: binary array size = 0x9dc
9265 16:47:59.352983 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9266 16:47:59.359885 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9267 16:47:59.366502 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9268 16:47:59.373757 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9269 16:47:59.376013 configure_display: Starting display init
9270 16:47:59.410442 anx7625_power_on_init: Init interface.
9271 16:47:59.414083 anx7625_disable_pd_protocol: Disabled PD feature.
9272 16:47:59.417376 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9273 16:47:59.445327 anx7625_start_dp_work: Secure OCM version=00
9274 16:47:59.448131 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9275 16:47:59.462695 sp_tx_get_edid_block: EDID Block = 1
9276 16:47:59.565773 Extracted contents:
9277 16:47:59.568639 header: 00 ff ff ff ff ff ff 00
9278 16:47:59.572044 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9279 16:47:59.575277 version: 01 04
9280 16:47:59.578317 basic params: 95 1f 11 78 0a
9281 16:47:59.581951 chroma info: 76 90 94 55 54 90 27 21 50 54
9282 16:47:59.585395 established: 00 00 00
9283 16:47:59.592133 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9284 16:47:59.595098 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9285 16:47:59.601572 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9286 16:47:59.608721 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9287 16:47:59.614944 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9288 16:47:59.618399 extensions: 00
9289 16:47:59.618980 checksum: fb
9290 16:47:59.619363
9291 16:47:59.621752 Manufacturer: IVO Model 57d Serial Number 0
9292 16:47:59.624727 Made week 0 of 2020
9293 16:47:59.625248 EDID version: 1.4
9294 16:47:59.628020 Digital display
9295 16:47:59.631586 6 bits per primary color channel
9296 16:47:59.632054 DisplayPort interface
9297 16:47:59.634670 Maximum image size: 31 cm x 17 cm
9298 16:47:59.637955 Gamma: 220%
9299 16:47:59.638479 Check DPMS levels
9300 16:47:59.641212 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9301 16:47:59.648487 First detailed timing is preferred timing
9302 16:47:59.648947 Established timings supported:
9303 16:47:59.650918 Standard timings supported:
9304 16:47:59.654176 Detailed timings
9305 16:47:59.658551 Hex of detail: 383680a07038204018303c0035ae10000019
9306 16:47:59.664261 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9307 16:47:59.667335 0780 0798 07c8 0820 hborder 0
9308 16:47:59.670820 0438 043b 0447 0458 vborder 0
9309 16:47:59.674257 -hsync -vsync
9310 16:47:59.674856 Did detailed timing
9311 16:47:59.680593 Hex of detail: 000000000000000000000000000000000000
9312 16:47:59.684132 Manufacturer-specified data, tag 0
9313 16:47:59.687328 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9314 16:47:59.690747 ASCII string: InfoVision
9315 16:47:59.694118 Hex of detail: 000000fe00523134304e574635205248200a
9316 16:47:59.697783 ASCII string: R140NWF5 RH
9317 16:47:59.698338 Checksum
9318 16:47:59.700739 Checksum: 0xfb (valid)
9319 16:47:59.704094 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9320 16:47:59.707404 DSI data_rate: 832800000 bps
9321 16:47:59.714623 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9322 16:47:59.717227 anx7625_parse_edid: pixelclock(138800).
9323 16:47:59.720651 hactive(1920), hsync(48), hfp(24), hbp(88)
9324 16:47:59.723688 vactive(1080), vsync(12), vfp(3), vbp(17)
9325 16:47:59.727002 anx7625_dsi_config: config dsi.
9326 16:47:59.733411 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9327 16:47:59.747286 anx7625_dsi_config: success to config DSI
9328 16:47:59.750764 anx7625_dp_start: MIPI phy setup OK.
9329 16:47:59.754125 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9330 16:47:59.757034 mtk_ddp_mode_set invalid vrefresh 60
9331 16:47:59.760394 main_disp_path_setup
9332 16:47:59.760881 ovl_layer_smi_id_en
9333 16:47:59.763751 ovl_layer_smi_id_en
9334 16:47:59.764205 ccorr_config
9335 16:47:59.764570 aal_config
9336 16:47:59.767871 gamma_config
9337 16:47:59.768420 postmask_config
9338 16:47:59.770635 dither_config
9339 16:47:59.773707 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9340 16:47:59.779983 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9341 16:47:59.784179 Root Device init finished in 553 msecs
9342 16:47:59.786980 CPU_CLUSTER: 0 init
9343 16:47:59.793741 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9344 16:47:59.800473 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9345 16:47:59.801030 APU_MBOX 0x190000b0 = 0x10001
9346 16:47:59.804215 APU_MBOX 0x190001b0 = 0x10001
9347 16:47:59.806635 APU_MBOX 0x190005b0 = 0x10001
9348 16:47:59.810265 APU_MBOX 0x190006b0 = 0x10001
9349 16:47:59.816366 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9350 16:47:59.826158 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9351 16:47:59.838991 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9352 16:47:59.845502 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9353 16:47:59.856985 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9354 16:47:59.866313 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9355 16:47:59.869926 CPU_CLUSTER: 0 init finished in 81 msecs
9356 16:47:59.872933 Devices initialized
9357 16:47:59.876172 Show all devs... After init.
9358 16:47:59.876633 Root Device: enabled 1
9359 16:47:59.880039 CPU_CLUSTER: 0: enabled 1
9360 16:47:59.882330 CPU: 00: enabled 1
9361 16:47:59.886092 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9362 16:47:59.889307 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9363 16:47:59.892395 ELOG: NV offset 0x57f000 size 0x1000
9364 16:47:59.899863 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9365 16:47:59.905995 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9366 16:47:59.909366 ELOG: Event(17) added with size 13 at 2023-06-03 16:47:59 UTC
9367 16:47:59.915827 out: cmd=0x121: 03 db 21 01 00 00 00 00
9368 16:47:59.919061 in-header: 03 2a 00 00 2c 00 00 00
9369 16:47:59.929069 in-data: 35 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 16:47:59.935829 ELOG: Event(A1) added with size 10 at 2023-06-03 16:47:59 UTC
9371 16:47:59.942049 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9372 16:47:59.948716 ELOG: Event(A0) added with size 9 at 2023-06-03 16:47:59 UTC
9373 16:47:59.951881 elog_add_boot_reason: Logged dev mode boot
9374 16:47:59.958943 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9375 16:47:59.959517 Finalize devices...
9376 16:47:59.961881 Devices finalized
9377 16:47:59.965384 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9378 16:47:59.968596 Writing coreboot table at 0xffe64000
9379 16:47:59.972497 0. 000000000010a000-0000000000113fff: RAMSTAGE
9380 16:47:59.978833 1. 0000000040000000-00000000400fffff: RAM
9381 16:47:59.981824 2. 0000000040100000-000000004032afff: RAMSTAGE
9382 16:47:59.984965 3. 000000004032b000-00000000545fffff: RAM
9383 16:47:59.988669 4. 0000000054600000-000000005465ffff: BL31
9384 16:47:59.992137 5. 0000000054660000-00000000ffe63fff: RAM
9385 16:47:59.998795 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9386 16:48:00.001637 7. 0000000100000000-000000023fffffff: RAM
9387 16:48:00.005183 Passing 5 GPIOs to payload:
9388 16:48:00.008641 NAME | PORT | POLARITY | VALUE
9389 16:48:00.014817 EC in RW | 0x000000aa | low | undefined
9390 16:48:00.018302 EC interrupt | 0x00000005 | low | undefined
9391 16:48:00.021653 TPM interrupt | 0x000000ab | high | undefined
9392 16:48:00.028202 SD card detect | 0x00000011 | high | undefined
9393 16:48:00.031239 speaker enable | 0x00000093 | high | undefined
9394 16:48:00.034934 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9395 16:48:00.037955 in-header: 03 f9 00 00 02 00 00 00
9396 16:48:00.041041 in-data: 02 00
9397 16:48:00.044321 ADC[4]: Raw value=901770 ID=7
9398 16:48:00.044787 ADC[3]: Raw value=213179 ID=1
9399 16:48:00.047794 RAM Code: 0x71
9400 16:48:00.051117 ADC[6]: Raw value=74502 ID=0
9401 16:48:00.051755 ADC[5]: Raw value=211703 ID=1
9402 16:48:00.054175 SKU Code: 0x1
9403 16:48:00.061317 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9404 16:48:00.061882 coreboot table: 964 bytes.
9405 16:48:00.064252 IMD ROOT 0. 0xfffff000 0x00001000
9406 16:48:00.068007 IMD SMALL 1. 0xffffe000 0x00001000
9407 16:48:00.070922 RO MCACHE 2. 0xffffc000 0x00001104
9408 16:48:00.074051 CONSOLE 3. 0xfff7c000 0x00080000
9409 16:48:00.077532 FMAP 4. 0xfff7b000 0x00000452
9410 16:48:00.080872 TIME STAMP 5. 0xfff7a000 0x00000910
9411 16:48:00.084480 VBOOT WORK 6. 0xfff66000 0x00014000
9412 16:48:00.087482 RAMOOPS 7. 0xffe66000 0x00100000
9413 16:48:00.090538 COREBOOT 8. 0xffe64000 0x00002000
9414 16:48:00.094123 IMD small region:
9415 16:48:00.097188 IMD ROOT 0. 0xffffec00 0x00000400
9416 16:48:00.100666 VPD 1. 0xffffeba0 0x0000004c
9417 16:48:00.104469 MMC STATUS 2. 0xffffeb80 0x00000004
9418 16:48:00.107170 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9419 16:48:00.110917 Probing TPM: done!
9420 16:48:00.114410 Connected to device vid:did:rid of 1ae0:0028:00
9421 16:48:00.125484 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9422 16:48:00.129010 Initialized TPM device CR50 revision 0
9423 16:48:00.132317 Checking cr50 for pending updates
9424 16:48:00.135688 Reading cr50 TPM mode
9425 16:48:00.143972 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9426 16:48:00.150594 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9427 16:48:00.191642 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9428 16:48:00.194427 Checking segment from ROM address 0x40100000
9429 16:48:00.197792 Checking segment from ROM address 0x4010001c
9430 16:48:00.204803 Loading segment from ROM address 0x40100000
9431 16:48:00.205394 code (compression=0)
9432 16:48:00.214524 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9433 16:48:00.221182 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9434 16:48:00.221780 it's not compressed!
9435 16:48:00.227741 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9436 16:48:00.234265 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9437 16:48:00.251737 Loading segment from ROM address 0x4010001c
9438 16:48:00.252327 Entry Point 0x80000000
9439 16:48:00.254924 Loaded segments
9440 16:48:00.258343 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9441 16:48:00.264757 Jumping to boot code at 0x80000000(0xffe64000)
9442 16:48:00.271321 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9443 16:48:00.277880 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9444 16:48:00.285830 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9445 16:48:00.289991 Checking segment from ROM address 0x40100000
9446 16:48:00.293163 Checking segment from ROM address 0x4010001c
9447 16:48:00.299251 Loading segment from ROM address 0x40100000
9448 16:48:00.299820 code (compression=1)
9449 16:48:00.306546 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9450 16:48:00.315879 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9451 16:48:00.316456 using LZMA
9452 16:48:00.324761 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9453 16:48:00.330974 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9454 16:48:00.334335 Loading segment from ROM address 0x4010001c
9455 16:48:00.334952 Entry Point 0x54601000
9456 16:48:00.337657 Loaded segments
9457 16:48:00.340941 NOTICE: MT8192 bl31_setup
9458 16:48:00.348080 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9459 16:48:00.351256 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9460 16:48:00.355043 WARNING: region 0:
9461 16:48:00.357767 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 16:48:00.358237 WARNING: region 1:
9463 16:48:00.364499 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9464 16:48:00.367742 WARNING: region 2:
9465 16:48:00.371030 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9466 16:48:00.374545 WARNING: region 3:
9467 16:48:00.377616 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 16:48:00.381411 WARNING: region 4:
9469 16:48:00.387911 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 16:48:00.388489 WARNING: region 5:
9471 16:48:00.391021 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 16:48:00.394829 WARNING: region 6:
9473 16:48:00.397400 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 16:48:00.400922 WARNING: region 7:
9475 16:48:00.404491 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 16:48:00.411269 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9477 16:48:00.414265 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9478 16:48:00.417519 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9479 16:48:00.424335 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9480 16:48:00.427945 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9481 16:48:00.434110 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9482 16:48:00.437283 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9483 16:48:00.440662 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9484 16:48:00.447334 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9485 16:48:00.450615 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9486 16:48:00.454171 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9487 16:48:00.460753 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9488 16:48:00.464458 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9489 16:48:00.470417 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9490 16:48:00.473949 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9491 16:48:00.477314 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9492 16:48:00.484215 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9493 16:48:00.486895 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9494 16:48:00.493916 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9495 16:48:00.496832 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9496 16:48:00.500405 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9497 16:48:00.507038 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9498 16:48:00.510408 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9499 16:48:00.513577 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9500 16:48:00.520408 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9501 16:48:00.523939 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9502 16:48:00.530398 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9503 16:48:00.534000 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9504 16:48:00.540163 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9505 16:48:00.543838 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9506 16:48:00.547333 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9507 16:48:00.553245 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9508 16:48:00.556663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9509 16:48:00.560283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9510 16:48:00.562994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9511 16:48:00.569872 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9512 16:48:00.573049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9513 16:48:00.576463 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9514 16:48:00.579654 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9515 16:48:00.586469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9516 16:48:00.590106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9517 16:48:00.593542 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9518 16:48:00.596983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9519 16:48:00.603076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9520 16:48:00.606472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9521 16:48:00.609836 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9522 16:48:00.613071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9523 16:48:00.619444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9524 16:48:00.623616 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9525 16:48:00.629939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9526 16:48:00.633067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9527 16:48:00.636486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9528 16:48:00.642781 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9529 16:48:00.646408 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9530 16:48:00.653027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9531 16:48:00.656348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9532 16:48:00.663299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9533 16:48:00.666180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9534 16:48:00.672846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9535 16:48:00.676132 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9536 16:48:00.679455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9537 16:48:00.686211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9538 16:48:00.689621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9539 16:48:00.696403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9540 16:48:00.699154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9541 16:48:00.706183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9542 16:48:00.709297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9543 16:48:00.712590 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9544 16:48:00.719969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9545 16:48:00.722525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9546 16:48:00.729110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9547 16:48:00.732732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9548 16:48:00.739526 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9549 16:48:00.743225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9550 16:48:00.745768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9551 16:48:00.753512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9552 16:48:00.755864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9553 16:48:00.762330 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9554 16:48:00.766566 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9555 16:48:00.772364 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9556 16:48:00.775731 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9557 16:48:00.782559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9558 16:48:00.785624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9559 16:48:00.789057 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9560 16:48:00.795888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9561 16:48:00.799225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9562 16:48:00.805373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9563 16:48:00.808648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9564 16:48:00.815210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9565 16:48:00.818579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9566 16:48:00.825523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9567 16:48:00.828866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9568 16:48:00.832445 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9569 16:48:00.838454 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9570 16:48:00.842305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9571 16:48:00.849314 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9572 16:48:00.851756 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9573 16:48:00.854895 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9574 16:48:00.861623 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9575 16:48:00.865087 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9576 16:48:00.868094 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9577 16:48:00.872449 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9578 16:48:00.878460 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9579 16:48:00.881998 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9580 16:48:00.888483 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9581 16:48:00.892112 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9582 16:48:00.895326 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9583 16:48:00.901886 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9584 16:48:00.905788 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9585 16:48:00.911545 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9586 16:48:00.915525 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9587 16:48:00.921551 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9588 16:48:00.924671 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9589 16:48:00.928203 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9590 16:48:00.934731 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9591 16:48:00.938247 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9592 16:48:00.941784 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9593 16:48:00.948037 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9594 16:48:00.951230 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9595 16:48:00.954726 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9596 16:48:00.957955 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9597 16:48:00.965108 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9598 16:48:00.967536 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9599 16:48:00.972187 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9600 16:48:00.977730 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9601 16:48:00.981409 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9602 16:48:00.984743 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9603 16:48:00.991309 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9604 16:48:00.994975 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9605 16:48:01.001235 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9606 16:48:01.004879 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9607 16:48:01.008774 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9608 16:48:01.014990 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9609 16:48:01.017945 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9610 16:48:01.024685 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9611 16:48:01.027675 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9612 16:48:01.030983 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9613 16:48:01.038522 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9614 16:48:01.041083 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9615 16:48:01.044139 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9616 16:48:01.051741 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9617 16:48:01.054534 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9618 16:48:01.060945 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9619 16:48:01.064253 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9620 16:48:01.068289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9621 16:48:01.074449 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9622 16:48:01.077681 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9623 16:48:01.083985 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9624 16:48:01.087132 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9625 16:48:01.094223 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9626 16:48:01.097283 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9627 16:48:01.100726 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9628 16:48:01.107192 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9629 16:48:01.110808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9630 16:48:01.114064 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9631 16:48:01.120574 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9632 16:48:01.124053 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9633 16:48:01.130246 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9634 16:48:01.133910 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9635 16:48:01.137109 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9636 16:48:01.143922 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9637 16:48:01.146920 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9638 16:48:01.153407 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9639 16:48:01.156508 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9640 16:48:01.160426 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9641 16:48:01.166524 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9642 16:48:01.169743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9643 16:48:01.176384 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9644 16:48:01.179593 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9645 16:48:01.183571 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9646 16:48:01.189661 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9647 16:48:01.192850 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9648 16:48:01.199460 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9649 16:48:01.203192 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9650 16:48:01.206466 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9651 16:48:01.212822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9652 16:48:01.215735 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9653 16:48:01.222914 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9654 16:48:01.225942 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9655 16:48:01.229301 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9656 16:48:01.235880 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9657 16:48:01.239171 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9658 16:48:01.245821 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9659 16:48:01.249063 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9660 16:48:01.252190 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9661 16:48:01.258790 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9662 16:48:01.262401 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9663 16:48:01.268540 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9664 16:48:01.272324 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9665 16:48:01.275728 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9666 16:48:01.281889 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9667 16:48:01.285574 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9668 16:48:01.291922 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9669 16:48:01.295519 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9670 16:48:01.302332 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9671 16:48:01.305560 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9672 16:48:01.308494 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9673 16:48:01.315180 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9674 16:48:01.319031 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9675 16:48:01.325260 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9676 16:48:01.328079 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9677 16:48:01.334814 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9678 16:48:01.338071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9679 16:48:01.341363 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9680 16:48:01.347994 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9681 16:48:01.351305 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9682 16:48:01.358111 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9683 16:48:01.361110 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9684 16:48:01.367528 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9685 16:48:01.370824 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9686 16:48:01.374571 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9687 16:48:01.380938 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9688 16:48:01.384240 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9689 16:48:01.391077 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9690 16:48:01.394521 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9691 16:48:01.400727 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9692 16:48:01.404357 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9693 16:48:01.407691 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9694 16:48:01.414530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9695 16:48:01.417879 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9696 16:48:01.423842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9697 16:48:01.427286 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9698 16:48:01.434235 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9699 16:48:01.437406 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9700 16:48:01.440498 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9701 16:48:01.447335 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9702 16:48:01.450417 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9703 16:48:01.457215 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9704 16:48:01.460441 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9705 16:48:01.463876 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9706 16:48:01.467041 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9707 16:48:01.473999 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9708 16:48:01.477162 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9709 16:48:01.480118 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9710 16:48:01.486620 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9711 16:48:01.490689 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9712 16:48:01.493213 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9713 16:48:01.500225 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9714 16:48:01.502887 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9715 16:48:01.506723 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9716 16:48:01.514038 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9717 16:48:01.516322 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9718 16:48:01.522933 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9719 16:48:01.526055 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9720 16:48:01.529589 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9721 16:48:01.536603 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9722 16:48:01.539317 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9723 16:48:01.546162 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9724 16:48:01.549295 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9725 16:48:01.552447 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9726 16:48:01.559098 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9727 16:48:01.562067 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9728 16:48:01.566011 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9729 16:48:01.572294 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9730 16:48:01.575405 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9731 16:48:01.582223 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9732 16:48:01.585665 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9733 16:48:01.589358 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9734 16:48:01.595197 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9735 16:48:01.598402 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9736 16:48:01.601683 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9737 16:48:01.608810 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9738 16:48:01.611942 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9739 16:48:01.614936 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9740 16:48:01.621434 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9741 16:48:01.625130 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9742 16:48:01.631795 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9743 16:48:01.635089 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9744 16:48:01.638280 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9745 16:48:01.644431 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9746 16:48:01.648321 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9747 16:48:01.651117 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9748 16:48:01.654891 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9749 16:48:01.657956 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9750 16:48:01.664548 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9751 16:48:01.667739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9752 16:48:01.671127 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9753 16:48:01.677527 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9754 16:48:01.680735 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9755 16:48:01.684015 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9756 16:48:01.687744 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9757 16:48:01.694132 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9758 16:48:01.697404 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9759 16:48:01.703848 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9760 16:48:01.707746 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9761 16:48:01.710723 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9762 16:48:01.716976 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9763 16:48:01.721014 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9764 16:48:01.727220 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9765 16:48:01.730735 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9766 16:48:01.737035 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9767 16:48:01.740358 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9768 16:48:01.743504 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9769 16:48:01.750091 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9770 16:48:01.753185 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9771 16:48:01.760300 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9772 16:48:01.763690 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9773 16:48:01.766800 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9774 16:48:01.773131 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9775 16:48:01.776721 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9776 16:48:01.783071 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9777 16:48:01.786584 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9778 16:48:01.792755 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9779 16:48:01.796106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9780 16:48:01.799830 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9781 16:48:01.806953 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9782 16:48:01.809753 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9783 16:48:01.815640 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9784 16:48:01.819520 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9785 16:48:01.826242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9786 16:48:01.829405 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9787 16:48:01.833004 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9788 16:48:01.839034 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9789 16:48:01.842643 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9790 16:48:01.848916 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9791 16:48:01.852485 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9792 16:48:01.855788 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9793 16:48:01.862443 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9794 16:48:01.865306 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9795 16:48:01.872307 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9796 16:48:01.874991 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9797 16:48:01.878809 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9798 16:48:01.885558 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9799 16:48:01.888927 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9800 16:48:01.895182 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9801 16:48:01.898423 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9802 16:48:01.904989 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9803 16:48:01.908329 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9804 16:48:01.914829 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9805 16:48:01.918471 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9806 16:48:01.921430 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9807 16:48:01.928313 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9808 16:48:01.931169 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9809 16:48:01.938378 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9810 16:48:01.941394 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9811 16:48:01.944520 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9812 16:48:01.951269 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9813 16:48:01.954817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9814 16:48:01.962003 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9815 16:48:01.964131 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9816 16:48:01.968074 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9817 16:48:01.974881 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9818 16:48:01.977677 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9819 16:48:01.984271 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9820 16:48:01.987609 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9821 16:48:01.990778 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9822 16:48:01.997494 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9823 16:48:02.000871 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9824 16:48:02.007879 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9825 16:48:02.010658 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9826 16:48:02.017160 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9827 16:48:02.020361 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9828 16:48:02.023694 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9829 16:48:02.030616 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9830 16:48:02.033768 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9831 16:48:02.040838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9832 16:48:02.043518 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9833 16:48:02.050315 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9834 16:48:02.053691 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9835 16:48:02.060462 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9836 16:48:02.063835 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9837 16:48:02.066880 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9838 16:48:02.073403 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9839 16:48:02.076773 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9840 16:48:02.083180 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9841 16:48:02.087016 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9842 16:48:02.093355 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9843 16:48:02.096528 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9844 16:48:02.102913 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9845 16:48:02.106568 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9846 16:48:02.110266 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9847 16:48:02.116502 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9848 16:48:02.119860 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9849 16:48:02.126505 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9850 16:48:02.129195 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9851 16:48:02.136311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9852 16:48:02.138940 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9853 16:48:02.143151 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9854 16:48:02.149171 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9855 16:48:02.152511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9856 16:48:02.159274 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9857 16:48:02.163017 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9858 16:48:02.169151 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9859 16:48:02.172341 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9860 16:48:02.178901 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9861 16:48:02.182157 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9862 16:48:02.185795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9863 16:48:02.192158 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9864 16:48:02.195156 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9865 16:48:02.202275 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9866 16:48:02.205476 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9867 16:48:02.211892 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9868 16:48:02.215321 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9869 16:48:02.218493 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9870 16:48:02.225063 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9871 16:48:02.228530 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9872 16:48:02.234817 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9873 16:48:02.238327 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9874 16:48:02.245044 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9875 16:48:02.248241 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9876 16:48:02.254954 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9877 16:48:02.258204 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9878 16:48:02.261523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9879 16:48:02.268057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9880 16:48:02.271662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9881 16:48:02.278142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9882 16:48:02.281278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9883 16:48:02.287746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9884 16:48:02.291215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9885 16:48:02.298074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9886 16:48:02.300881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9887 16:48:02.307387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9888 16:48:02.311155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9889 16:48:02.317562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9890 16:48:02.320420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9891 16:48:02.327300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9892 16:48:02.330741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9893 16:48:02.337359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9894 16:48:02.340435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9895 16:48:02.347419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9896 16:48:02.351340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9897 16:48:02.357204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9898 16:48:02.360417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9899 16:48:02.366993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9900 16:48:02.370379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9901 16:48:02.376687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9902 16:48:02.380008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9903 16:48:02.387031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9904 16:48:02.390104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9905 16:48:02.396510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9906 16:48:02.399585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9907 16:48:02.406286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9908 16:48:02.410036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9909 16:48:02.416373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9910 16:48:02.419760 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9911 16:48:02.422950 INFO: [APUAPC] vio 0
9912 16:48:02.426383 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9913 16:48:02.433003 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9914 16:48:02.436125 INFO: [APUAPC] D0_APC_0: 0x400510
9915 16:48:02.436696 INFO: [APUAPC] D0_APC_1: 0x0
9916 16:48:02.439566 INFO: [APUAPC] D0_APC_2: 0x1540
9917 16:48:02.442735 INFO: [APUAPC] D0_APC_3: 0x0
9918 16:48:02.446249 INFO: [APUAPC] D1_APC_0: 0xffffffff
9919 16:48:02.449119 INFO: [APUAPC] D1_APC_1: 0xffffffff
9920 16:48:02.453299 INFO: [APUAPC] D1_APC_2: 0x3fffff
9921 16:48:02.456351 INFO: [APUAPC] D1_APC_3: 0x0
9922 16:48:02.459005 INFO: [APUAPC] D2_APC_0: 0xffffffff
9923 16:48:02.462697 INFO: [APUAPC] D2_APC_1: 0xffffffff
9924 16:48:02.466010 INFO: [APUAPC] D2_APC_2: 0x3fffff
9925 16:48:02.469149 INFO: [APUAPC] D2_APC_3: 0x0
9926 16:48:02.472702 INFO: [APUAPC] D3_APC_0: 0xffffffff
9927 16:48:02.475614 INFO: [APUAPC] D3_APC_1: 0xffffffff
9928 16:48:02.479100 INFO: [APUAPC] D3_APC_2: 0x3fffff
9929 16:48:02.482111 INFO: [APUAPC] D3_APC_3: 0x0
9930 16:48:02.485786 INFO: [APUAPC] D4_APC_0: 0xffffffff
9931 16:48:02.489147 INFO: [APUAPC] D4_APC_1: 0xffffffff
9932 16:48:02.492840 INFO: [APUAPC] D4_APC_2: 0x3fffff
9933 16:48:02.495873 INFO: [APUAPC] D4_APC_3: 0x0
9934 16:48:02.499126 INFO: [APUAPC] D5_APC_0: 0xffffffff
9935 16:48:02.502312 INFO: [APUAPC] D5_APC_1: 0xffffffff
9936 16:48:02.505630 INFO: [APUAPC] D5_APC_2: 0x3fffff
9937 16:48:02.508694 INFO: [APUAPC] D5_APC_3: 0x0
9938 16:48:02.512592 INFO: [APUAPC] D6_APC_0: 0xffffffff
9939 16:48:02.515233 INFO: [APUAPC] D6_APC_1: 0xffffffff
9940 16:48:02.518789 INFO: [APUAPC] D6_APC_2: 0x3fffff
9941 16:48:02.521927 INFO: [APUAPC] D6_APC_3: 0x0
9942 16:48:02.525397 INFO: [APUAPC] D7_APC_0: 0xffffffff
9943 16:48:02.528707 INFO: [APUAPC] D7_APC_1: 0xffffffff
9944 16:48:02.531554 INFO: [APUAPC] D7_APC_2: 0x3fffff
9945 16:48:02.535182 INFO: [APUAPC] D7_APC_3: 0x0
9946 16:48:02.538454 INFO: [APUAPC] D8_APC_0: 0xffffffff
9947 16:48:02.541963 INFO: [APUAPC] D8_APC_1: 0xffffffff
9948 16:48:02.545028 INFO: [APUAPC] D8_APC_2: 0x3fffff
9949 16:48:02.548327 INFO: [APUAPC] D8_APC_3: 0x0
9950 16:48:02.552352 INFO: [APUAPC] D9_APC_0: 0xffffffff
9951 16:48:02.554844 INFO: [APUAPC] D9_APC_1: 0xffffffff
9952 16:48:02.558391 INFO: [APUAPC] D9_APC_2: 0x3fffff
9953 16:48:02.562462 INFO: [APUAPC] D9_APC_3: 0x0
9954 16:48:02.564913 INFO: [APUAPC] D10_APC_0: 0xffffffff
9955 16:48:02.567769 INFO: [APUAPC] D10_APC_1: 0xffffffff
9956 16:48:02.571185 INFO: [APUAPC] D10_APC_2: 0x3fffff
9957 16:48:02.574721 INFO: [APUAPC] D10_APC_3: 0x0
9958 16:48:02.578097 INFO: [APUAPC] D11_APC_0: 0xffffffff
9959 16:48:02.581083 INFO: [APUAPC] D11_APC_1: 0xffffffff
9960 16:48:02.584366 INFO: [APUAPC] D11_APC_2: 0x3fffff
9961 16:48:02.588175 INFO: [APUAPC] D11_APC_3: 0x0
9962 16:48:02.591487 INFO: [APUAPC] D12_APC_0: 0xffffffff
9963 16:48:02.594668 INFO: [APUAPC] D12_APC_1: 0xffffffff
9964 16:48:02.597792 INFO: [APUAPC] D12_APC_2: 0x3fffff
9965 16:48:02.601048 INFO: [APUAPC] D12_APC_3: 0x0
9966 16:48:02.604231 INFO: [APUAPC] D13_APC_0: 0xffffffff
9967 16:48:02.607736 INFO: [APUAPC] D13_APC_1: 0xffffffff
9968 16:48:02.611015 INFO: [APUAPC] D13_APC_2: 0x3fffff
9969 16:48:02.614257 INFO: [APUAPC] D13_APC_3: 0x0
9970 16:48:02.618050 INFO: [APUAPC] D14_APC_0: 0xffffffff
9971 16:48:02.620921 INFO: [APUAPC] D14_APC_1: 0xffffffff
9972 16:48:02.624092 INFO: [APUAPC] D14_APC_2: 0x3fffff
9973 16:48:02.627678 INFO: [APUAPC] D14_APC_3: 0x0
9974 16:48:02.630722 INFO: [APUAPC] D15_APC_0: 0xffffffff
9975 16:48:02.634251 INFO: [APUAPC] D15_APC_1: 0xffffffff
9976 16:48:02.637301 INFO: [APUAPC] D15_APC_2: 0x3fffff
9977 16:48:02.640804 INFO: [APUAPC] D15_APC_3: 0x0
9978 16:48:02.644186 INFO: [APUAPC] APC_CON: 0x4
9979 16:48:02.647214 INFO: [NOCDAPC] D0_APC_0: 0x0
9980 16:48:02.650505 INFO: [NOCDAPC] D0_APC_1: 0x0
9981 16:48:02.653709 INFO: [NOCDAPC] D1_APC_0: 0x0
9982 16:48:02.657067 INFO: [NOCDAPC] D1_APC_1: 0xfff
9983 16:48:02.657644 INFO: [NOCDAPC] D2_APC_0: 0x0
9984 16:48:02.660192 INFO: [NOCDAPC] D2_APC_1: 0xfff
9985 16:48:02.663632 INFO: [NOCDAPC] D3_APC_0: 0x0
9986 16:48:02.667751 INFO: [NOCDAPC] D3_APC_1: 0xfff
9987 16:48:02.670548 INFO: [NOCDAPC] D4_APC_0: 0x0
9988 16:48:02.673735 INFO: [NOCDAPC] D4_APC_1: 0xfff
9989 16:48:02.676740 INFO: [NOCDAPC] D5_APC_0: 0x0
9990 16:48:02.680355 INFO: [NOCDAPC] D5_APC_1: 0xfff
9991 16:48:02.683551 INFO: [NOCDAPC] D6_APC_0: 0x0
9992 16:48:02.686893 INFO: [NOCDAPC] D6_APC_1: 0xfff
9993 16:48:02.690319 INFO: [NOCDAPC] D7_APC_0: 0x0
9994 16:48:02.690929 INFO: [NOCDAPC] D7_APC_1: 0xfff
9995 16:48:02.693618 INFO: [NOCDAPC] D8_APC_0: 0x0
9996 16:48:02.696705 INFO: [NOCDAPC] D8_APC_1: 0xfff
9997 16:48:02.700032 INFO: [NOCDAPC] D9_APC_0: 0x0
9998 16:48:02.703446 INFO: [NOCDAPC] D9_APC_1: 0xfff
9999 16:48:02.706944 INFO: [NOCDAPC] D10_APC_0: 0x0
10000 16:48:02.710553 INFO: [NOCDAPC] D10_APC_1: 0xfff
10001 16:48:02.713412 INFO: [NOCDAPC] D11_APC_0: 0x0
10002 16:48:02.716837 INFO: [NOCDAPC] D11_APC_1: 0xfff
10003 16:48:02.720345 INFO: [NOCDAPC] D12_APC_0: 0x0
10004 16:48:02.723180 INFO: [NOCDAPC] D12_APC_1: 0xfff
10005 16:48:02.726583 INFO: [NOCDAPC] D13_APC_0: 0x0
10006 16:48:02.730022 INFO: [NOCDAPC] D13_APC_1: 0xfff
10007 16:48:02.733188 INFO: [NOCDAPC] D14_APC_0: 0x0
10008 16:48:02.736548 INFO: [NOCDAPC] D14_APC_1: 0xfff
10009 16:48:02.737130 INFO: [NOCDAPC] D15_APC_0: 0x0
10010 16:48:02.739726 INFO: [NOCDAPC] D15_APC_1: 0xfff
10011 16:48:02.743000 INFO: [NOCDAPC] APC_CON: 0x4
10012 16:48:02.746214 INFO: [APUAPC] set_apusys_apc done
10013 16:48:02.749526 INFO: [DEVAPC] devapc_init done
10014 16:48:02.756370 INFO: GICv3 without legacy support detected.
10015 16:48:02.759419 INFO: ARM GICv3 driver initialized in EL3
10016 16:48:02.763906 INFO: Maximum SPI INTID supported: 639
10017 16:48:02.766082 INFO: BL31: Initializing runtime services
10018 16:48:02.772758 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10019 16:48:02.775856 INFO: SPM: enable CPC mode
10020 16:48:02.778881 INFO: mcdi ready for mcusys-off-idle and system suspend
10021 16:48:02.786008 INFO: BL31: Preparing for EL3 exit to normal world
10022 16:48:02.789224 INFO: Entry point address = 0x80000000
10023 16:48:02.789803 INFO: SPSR = 0x8
10024 16:48:02.796260
10025 16:48:02.796837
10026 16:48:02.797212
10027 16:48:02.799250 Starting depthcharge on Spherion...
10028 16:48:02.799725
10029 16:48:02.800309 Wipe memory regions:
10030 16:48:02.800725
10031 16:48:02.803222 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10032 16:48:02.803780 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10033 16:48:02.804247 Setting prompt string to ['asurada:']
10034 16:48:02.804770 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10035 16:48:02.805503 [0x00000040000000, 0x00000054600000)
10036 16:48:02.924842
10037 16:48:02.925438 [0x00000054660000, 0x00000080000000)
10038 16:48:03.185722
10039 16:48:03.186301 [0x000000821a7280, 0x000000ffe64000)
10040 16:48:03.930521
10041 16:48:03.931098 [0x00000100000000, 0x00000240000000)
10042 16:48:05.820868
10043 16:48:05.823831 Initializing XHCI USB controller at 0x11200000.
10044 16:48:06.862324
10045 16:48:06.865701 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10046 16:48:06.866269
10047 16:48:06.866686
10048 16:48:06.867031
10049 16:48:06.867806 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 16:48:06.969015 asurada: tftpboot 192.168.201.1 10576304/tftp-deploy-sksb23zw/kernel/image.itb 10576304/tftp-deploy-sksb23zw/kernel/cmdline
10052 16:48:06.969689 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 16:48:06.970162 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10054 16:48:06.975043 tftpboot 192.168.201.1 10576304/tftp-deploy-sksb23zw/kernel/image.ittp-deploy-sksb23zw/kernel/cmdline
10055 16:48:06.975624
10056 16:48:06.975995 Waiting for link
10057 16:48:07.134984
10058 16:48:07.135545 R8152: Initializing
10059 16:48:07.135920
10060 16:48:07.139097 Version 9 (ocp_data = 6010)
10061 16:48:07.139668
10062 16:48:07.141859 R8152: Done initializing
10063 16:48:07.142453
10064 16:48:07.142827 Adding net device
10065 16:48:09.083520
10066 16:48:09.084077 done.
10067 16:48:09.084446
10068 16:48:09.084790 MAC: 00:e0:4c:72:2d:d6
10069 16:48:09.085125
10070 16:48:09.086754 Sending DHCP discover... done.
10071 16:48:09.087218
10072 16:48:19.521838 Waiting for reply... R8152: Bulk read error 0xffffffbf
10073 16:48:19.522495
10074 16:48:19.524883 Receive failed.
10075 16:48:19.525337
10076 16:48:19.525697 done.
10077 16:48:19.526032
10078 16:48:19.528324 Sending DHCP request... done.
10079 16:48:19.528782
10080 16:48:19.535404 Waiting for reply... done.
10081 16:48:19.535991
10082 16:48:19.536365 My ip is 192.168.201.21
10083 16:48:19.536711
10084 16:48:19.539331 The DHCP server ip is 192.168.201.1
10085 16:48:19.539880
10086 16:48:19.545174 TFTP server IP predefined by user: 192.168.201.1
10087 16:48:19.545715
10088 16:48:19.551658 Bootfile predefined by user: 10576304/tftp-deploy-sksb23zw/kernel/image.itb
10089 16:48:19.552339
10090 16:48:19.554780 Sending tftp read request... done.
10091 16:48:19.555247
10092 16:48:19.559871 Waiting for the transfer...
10093 16:48:19.560438
10094 16:48:19.953317 00000000 ################################################################
10095 16:48:19.953829
10096 16:48:20.321904 00080000 ################################################################
10097 16:48:20.322450
10098 16:48:20.685923 00100000 ################################################################
10099 16:48:20.686512
10100 16:48:21.047808 00180000 ################################################################
10101 16:48:21.048308
10102 16:48:21.427829 00200000 ################################################################
10103 16:48:21.428354
10104 16:48:21.802700 00280000 ################################################################
10105 16:48:21.803198
10106 16:48:22.183490 00300000 ################################################################
10107 16:48:22.183992
10108 16:48:22.563911 00380000 ################################################################
10109 16:48:22.564462
10110 16:48:22.941182 00400000 ################################################################
10111 16:48:22.941712
10112 16:48:23.321970 00480000 ################################################################
10113 16:48:23.322545
10114 16:48:23.719703 00500000 ################################################################
10115 16:48:23.720222
10116 16:48:24.095485 00580000 ################################################################
10117 16:48:24.095633
10118 16:48:24.351906 00600000 ################################################################
10119 16:48:24.352036
10120 16:48:24.636228 00680000 ################################################################
10121 16:48:24.636362
10122 16:48:24.923815 00700000 ################################################################
10123 16:48:24.923957
10124 16:48:25.219067 00780000 ################################################################
10125 16:48:25.219203
10126 16:48:25.508701 00800000 ################################################################
10127 16:48:25.508834
10128 16:48:25.759110 00880000 ################################################################
10129 16:48:25.759238
10130 16:48:26.028205 00900000 ################################################################
10131 16:48:26.028334
10132 16:48:26.316668 00980000 ################################################################
10133 16:48:26.316815
10134 16:48:26.602603 00a00000 ################################################################
10135 16:48:26.602741
10136 16:48:26.898983 00a80000 ################################################################
10137 16:48:26.899117
10138 16:48:27.195198 00b00000 ################################################################
10139 16:48:27.195333
10140 16:48:27.489697 00b80000 ################################################################
10141 16:48:27.489835
10142 16:48:27.748595 00c00000 ################################################################
10143 16:48:27.748724
10144 16:48:28.005670 00c80000 ################################################################
10145 16:48:28.005801
10146 16:48:28.255636 00d00000 ################################################################
10147 16:48:28.255763
10148 16:48:28.523622 00d80000 ################################################################
10149 16:48:28.523758
10150 16:48:28.820069 00e00000 ################################################################
10151 16:48:28.820213
10152 16:48:29.114297 00e80000 ################################################################
10153 16:48:29.114468
10154 16:48:29.480688 00f00000 ################################################################
10155 16:48:29.480830
10156 16:48:29.756491 00f80000 ################################################################
10157 16:48:29.756625
10158 16:48:30.021881 01000000 ################################################################
10159 16:48:30.022023
10160 16:48:30.280965 01080000 ################################################################
10161 16:48:30.281120
10162 16:48:30.542792 01100000 ################################################################
10163 16:48:30.542936
10164 16:48:30.793024 01180000 ################################################################
10165 16:48:30.793178
10166 16:48:31.043275 01200000 ################################################################
10167 16:48:31.043437
10168 16:48:31.293605 01280000 ################################################################
10169 16:48:31.293742
10170 16:48:31.578061 01300000 ################################################################
10171 16:48:31.578239
10172 16:48:31.861188 01380000 ################################################################
10173 16:48:31.861367
10174 16:48:32.111251 01400000 ################################################################
10175 16:48:32.111407
10176 16:48:32.384830 01480000 ################################################################
10177 16:48:32.384973
10178 16:48:32.674836 01500000 ################################################################
10179 16:48:32.674966
10180 16:48:32.972312 01580000 ################################################################
10181 16:48:32.972450
10182 16:48:33.264514 01600000 ################################################################
10183 16:48:33.264655
10184 16:48:33.597877 01680000 ################################################################
10185 16:48:33.598490
10186 16:48:33.977223 01700000 ################################################################
10187 16:48:33.977742
10188 16:48:34.366759 01780000 ################################################################
10189 16:48:34.367311
10190 16:48:34.742584 01800000 ################################################################
10191 16:48:34.743145
10192 16:48:35.088652 01880000 ################################################################
10193 16:48:35.088886
10194 16:48:35.427524 01900000 ################################################################
10195 16:48:35.428090
10196 16:48:35.791665 01980000 ################################################################
10197 16:48:35.792229
10198 16:48:36.179704 01a00000 ################################################################
10199 16:48:36.180265
10200 16:48:36.548204 01a80000 ################################################################
10201 16:48:36.548373
10202 16:48:36.905065 01b00000 ################################################################
10203 16:48:36.905200
10204 16:48:37.162779 01b80000 ################################################################
10205 16:48:37.162910
10206 16:48:37.437377 01c00000 ################################################################
10207 16:48:37.437505
10208 16:48:37.705643 01c80000 ################################################################
10209 16:48:37.705790
10210 16:48:37.984145 01d00000 ################################################################
10211 16:48:37.984280
10212 16:48:38.248809 01d80000 ################################################################
10213 16:48:38.248943
10214 16:48:38.499704 01e00000 ################################################################
10215 16:48:38.499832
10216 16:48:38.780584 01e80000 ################################################################
10217 16:48:38.780714
10218 16:48:39.058259 01f00000 ################################################################
10219 16:48:39.058446
10220 16:48:39.309439 01f80000 ################################################################
10221 16:48:39.309566
10222 16:48:39.573821 02000000 ################################################################
10223 16:48:39.573951
10224 16:48:39.870224 02080000 ################################################################
10225 16:48:39.870417
10226 16:48:40.167753 02100000 ################################################################
10227 16:48:40.167886
10228 16:48:40.464894 02180000 ################################################################
10229 16:48:40.465035
10230 16:48:40.757321 02200000 ################################################################
10231 16:48:40.757459
10232 16:48:41.052712 02280000 ################################################################
10233 16:48:41.052864
10234 16:48:41.350020 02300000 ################################################################
10235 16:48:41.350155
10236 16:48:41.645946 02380000 ################################################################
10237 16:48:41.646077
10238 16:48:41.938024 02400000 ################################################################
10239 16:48:41.938172
10240 16:48:42.234932 02480000 ################################################################
10241 16:48:42.235063
10242 16:48:42.531689 02500000 ################################################################
10243 16:48:42.531823
10244 16:48:42.827735 02580000 ################################################################
10245 16:48:42.827870
10246 16:48:43.124145 02600000 ################################################################
10247 16:48:43.124280
10248 16:48:43.421103 02680000 ################################################################
10249 16:48:43.421240
10250 16:48:43.814487 02700000 ################################################################
10251 16:48:43.815042
10252 16:48:44.193269 02780000 ################################################################
10253 16:48:44.193790
10254 16:48:44.568764 02800000 ################################################################
10255 16:48:44.569309
10256 16:48:44.994222 02880000 ################################################################
10257 16:48:44.994800
10258 16:48:45.373561 02900000 ################################################################
10259 16:48:45.374112
10260 16:48:45.755252 02980000 ################################################################
10261 16:48:45.755763
10262 16:48:46.064715 02a00000 ################################################################
10263 16:48:46.064855
10264 16:48:46.361977 02a80000 ################################################################
10265 16:48:46.362123
10266 16:48:46.657485 02b00000 ################################################################
10267 16:48:46.657620
10268 16:48:46.952997 02b80000 ################################################################
10269 16:48:46.953129
10270 16:48:47.211421 02c00000 ################################################################
10271 16:48:47.211552
10272 16:48:47.479939 02c80000 ################################################################
10273 16:48:47.480073
10274 16:48:47.776900 02d00000 ################################################################
10275 16:48:47.777026
10276 16:48:48.073246 02d80000 ################################################################
10277 16:48:48.073386
10278 16:48:48.371381 02e00000 ################################################################
10279 16:48:48.371525
10280 16:48:48.665892 02e80000 ################################################################
10281 16:48:48.666026
10282 16:48:48.963355 02f00000 ################################################################
10283 16:48:48.963539
10284 16:48:49.197718 02f80000 ######################################################### done.
10285 16:48:49.197850
10286 16:48:49.201405 The bootfile was 50266806 bytes long.
10287 16:48:49.201497
10288 16:48:49.204898 Sending tftp read request... done.
10289 16:48:49.204995
10290 16:48:49.205072 Waiting for the transfer...
10291 16:48:49.207958
10292 16:48:49.208054 00000000 # done.
10293 16:48:49.208150
10294 16:48:49.214641 Command line loaded dynamically from TFTP file: 10576304/tftp-deploy-sksb23zw/kernel/cmdline
10295 16:48:49.214756
10296 16:48:49.227952 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10297 16:48:49.228204
10298 16:48:49.228343 Loading FIT.
10299 16:48:49.228471
10300 16:48:49.231960 Image ramdisk-1 has 40134375 bytes.
10301 16:48:49.232199
10302 16:48:49.234369 Image fdt-1 has 46924 bytes.
10303 16:48:49.234555
10304 16:48:49.237752 Image kernel-1 has 10083474 bytes.
10305 16:48:49.238017
10306 16:48:49.248327 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10307 16:48:49.248647
10308 16:48:49.264518 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10309 16:48:49.265106
10310 16:48:49.271053 Choosing best match conf-1 for compat google,spherion-rev2.
10311 16:48:49.271638
10312 16:48:49.274805 Connected to device vid:did:rid of 1ae0:0028:00
10313 16:48:49.284904
10314 16:48:49.288437 tpm_get_response: command 0x17b, return code 0x0
10315 16:48:49.288998
10316 16:48:49.291553 ec_init: CrosEC protocol v3 supported (256, 248)
10317 16:48:49.295642
10318 16:48:49.298906 tpm_cleanup: add release locality here.
10319 16:48:49.299385
10320 16:48:49.299783 Shutting down all USB controllers.
10321 16:48:49.302403
10322 16:48:49.302881 Removing current net device
10323 16:48:49.303283
10324 16:48:49.308666 Exiting depthcharge with code 4 at timestamp: 75815609
10325 16:48:49.309144
10326 16:48:49.312956 LZMA decompressing kernel-1 to 0x821a6718
10327 16:48:49.313534
10328 16:48:49.315827 LZMA decompressing kernel-1 to 0x40000000
10329 16:48:50.582722
10330 16:48:50.583314 jumping to kernel
10331 16:48:50.585111 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10332 16:48:50.585658 start: 2.2.5 auto-login-action (timeout 00:03:37) [common]
10333 16:48:50.586079 Setting prompt string to ['Linux version [0-9]']
10334 16:48:50.586780 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10335 16:48:50.587213 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10336 16:48:50.664606
10337 16:48:50.667539 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10338 16:48:50.671520 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10339 16:48:50.672139 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10340 16:48:50.672609 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10341 16:48:50.673076 Using line separator: #'\n'#
10342 16:48:50.673431 No login prompt set.
10343 16:48:50.673789 Parsing kernel messages
10344 16:48:50.674110 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10345 16:48:50.674733 [login-action] Waiting for messages, (timeout 00:03:37)
10346 16:48:50.691784 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
10347 16:48:50.694002 [ 0.000000] random: crng init done
10348 16:48:50.697673 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10349 16:48:50.700605 [ 0.000000] efi: UEFI not found.
10350 16:48:50.711256 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10351 16:48:50.717127 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10352 16:48:50.727246 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10353 16:48:50.737140 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10354 16:48:50.743619 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10355 16:48:50.750485 [ 0.000000] printk: bootconsole [mtk8250] enabled
10356 16:48:50.756919 [ 0.000000] NUMA: No NUMA configuration found
10357 16:48:50.763355 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10358 16:48:50.766765 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10359 16:48:50.770450 [ 0.000000] Zone ranges:
10360 16:48:50.777387 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10361 16:48:50.780190 [ 0.000000] DMA32 empty
10362 16:48:50.786959 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10363 16:48:50.790571 [ 0.000000] Movable zone start for each node
10364 16:48:50.792797 [ 0.000000] Early memory node ranges
10365 16:48:50.799667 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10366 16:48:50.806306 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10367 16:48:50.812896 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10368 16:48:50.819510 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10369 16:48:50.825920 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10370 16:48:50.832592 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10371 16:48:50.888201 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10372 16:48:50.895118 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10373 16:48:50.901180 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10374 16:48:50.905081 [ 0.000000] psci: probing for conduit method from DT.
10375 16:48:50.911247 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10376 16:48:50.914257 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10377 16:48:50.921025 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10378 16:48:50.925393 [ 0.000000] psci: SMC Calling Convention v1.2
10379 16:48:50.931257 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10380 16:48:50.934518 [ 0.000000] Detected VIPT I-cache on CPU0
10381 16:48:50.940856 [ 0.000000] CPU features: detected: GIC system register CPU interface
10382 16:48:50.947959 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10383 16:48:50.953824 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10384 16:48:50.960857 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10385 16:48:50.970323 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10386 16:48:50.977033 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10387 16:48:50.980074 [ 0.000000] alternatives: applying boot alternatives
10388 16:48:50.988487 [ 0.000000] Fallback order for Node 0: 0
10389 16:48:50.993989 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10390 16:48:50.997104 [ 0.000000] Policy zone: Normal
10391 16:48:51.007075 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10392 16:48:51.019913 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10393 16:48:51.030293 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10394 16:48:51.040936 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10395 16:48:51.046469 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10396 16:48:51.049950 <6>[ 0.000000] software IO TLB: area num 8.
10397 16:48:51.106966 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10398 16:48:51.255870 <6>[ 0.000000] Memory: 7933748K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419020K reserved, 32768K cma-reserved)
10399 16:48:51.262520 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10400 16:48:51.269106 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10401 16:48:51.272248 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10402 16:48:51.279110 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10403 16:48:51.286228 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10404 16:48:51.288917 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10405 16:48:51.298858 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10406 16:48:51.305350 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10407 16:48:51.312192 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10408 16:48:51.318746 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10409 16:48:51.322460 <6>[ 0.000000] GICv3: 608 SPIs implemented
10410 16:48:51.325069 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10411 16:48:51.331949 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10412 16:48:51.335172 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10413 16:48:51.341809 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10414 16:48:51.354693 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10415 16:48:51.367675 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10416 16:48:51.375283 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10417 16:48:51.382878 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10418 16:48:51.396474 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10419 16:48:51.402553 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10420 16:48:51.409619 <6>[ 0.009182] Console: colour dummy device 80x25
10421 16:48:51.419238 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10422 16:48:51.425857 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10423 16:48:51.428798 <6>[ 0.029303] LSM: Security Framework initializing
10424 16:48:51.435527 <6>[ 0.034271] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 16:48:51.445877 <6>[ 0.042085] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 16:48:51.455552 <6>[ 0.051516] cblist_init_generic: Setting adjustable number of callback queues.
10427 16:48:51.458820 <6>[ 0.058971] cblist_init_generic: Setting shift to 3 and lim to 1.
10428 16:48:51.465345 <6>[ 0.065349] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 16:48:51.471767 <6>[ 0.071759] rcu: Hierarchical SRCU implementation.
10430 16:48:51.479063 <6>[ 0.076773] rcu: Max phase no-delay instances is 1000.
10431 16:48:51.485921 <6>[ 0.083796] EFI services will not be available.
10432 16:48:51.488242 <6>[ 0.088772] smp: Bringing up secondary CPUs ...
10433 16:48:51.496391 <6>[ 0.093857] Detected VIPT I-cache on CPU1
10434 16:48:51.503268 <6>[ 0.093929] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10435 16:48:51.509911 <6>[ 0.093959] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10436 16:48:51.513178 <6>[ 0.094301] Detected VIPT I-cache on CPU2
10437 16:48:51.523202 <6>[ 0.094355] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10438 16:48:51.529431 <6>[ 0.094371] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10439 16:48:51.532667 <6>[ 0.094631] Detected VIPT I-cache on CPU3
10440 16:48:51.539166 <6>[ 0.094679] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10441 16:48:51.545536 <6>[ 0.094694] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10442 16:48:51.552603 <6>[ 0.095001] CPU features: detected: Spectre-v4
10443 16:48:51.555569 <6>[ 0.095007] CPU features: detected: Spectre-BHB
10444 16:48:51.558852 <6>[ 0.095013] Detected PIPT I-cache on CPU4
10445 16:48:51.565393 <6>[ 0.095069] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10446 16:48:51.571884 <6>[ 0.095086] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10447 16:48:51.579306 <6>[ 0.095385] Detected PIPT I-cache on CPU5
10448 16:48:51.585347 <6>[ 0.095447] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10449 16:48:51.591982 <6>[ 0.095464] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10450 16:48:51.595627 <6>[ 0.095747] Detected PIPT I-cache on CPU6
10451 16:48:51.602104 <6>[ 0.095814] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10452 16:48:51.612025 <6>[ 0.095831] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10453 16:48:51.615226 <6>[ 0.096131] Detected PIPT I-cache on CPU7
10454 16:48:51.621920 <6>[ 0.096195] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10455 16:48:51.628281 <6>[ 0.096212] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10456 16:48:51.631767 <6>[ 0.096259] smp: Brought up 1 node, 8 CPUs
10457 16:48:51.638392 <6>[ 0.237652] SMP: Total of 8 processors activated.
10458 16:48:51.641244 <6>[ 0.242604] CPU features: detected: 32-bit EL0 Support
10459 16:48:51.651335 <6>[ 0.247967] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10460 16:48:51.658083 <6>[ 0.256821] CPU features: detected: Common not Private translations
10461 16:48:51.664615 <6>[ 0.263297] CPU features: detected: CRC32 instructions
10462 16:48:51.671780 <6>[ 0.268648] CPU features: detected: RCpc load-acquire (LDAPR)
10463 16:48:51.674334 <6>[ 0.274645] CPU features: detected: LSE atomic instructions
10464 16:48:51.680930 <6>[ 0.280426] CPU features: detected: Privileged Access Never
10465 16:48:51.687837 <6>[ 0.286206] CPU features: detected: RAS Extension Support
10466 16:48:51.694553 <6>[ 0.291814] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10467 16:48:51.697654 <6>[ 0.299034] CPU: All CPU(s) started at EL2
10468 16:48:51.704630 <6>[ 0.303350] alternatives: applying system-wide alternatives
10469 16:48:51.714100 <6>[ 0.314009] devtmpfs: initialized
10470 16:48:51.729914 <6>[ 0.322881] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10471 16:48:51.736500 <6>[ 0.332852] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10472 16:48:51.742693 <6>[ 0.340878] pinctrl core: initialized pinctrl subsystem
10473 16:48:51.746101 <6>[ 0.347525] DMI not present or invalid.
10474 16:48:51.752630 <6>[ 0.351935] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10475 16:48:51.762308 <6>[ 0.358791] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10476 16:48:51.768971 <6>[ 0.366379] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10477 16:48:51.778647 <6>[ 0.374596] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10478 16:48:51.782653 <6>[ 0.382842] audit: initializing netlink subsys (disabled)
10479 16:48:51.792052 <5>[ 0.388542] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10480 16:48:51.798688 <6>[ 0.389247] thermal_sys: Registered thermal governor 'step_wise'
10481 16:48:51.805370 <6>[ 0.396510] thermal_sys: Registered thermal governor 'power_allocator'
10482 16:48:51.808243 <6>[ 0.402768] cpuidle: using governor menu
10483 16:48:51.814958 <6>[ 0.413739] NET: Registered PF_QIPCRTR protocol family
10484 16:48:51.821682 <6>[ 0.419217] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10485 16:48:51.828502 <6>[ 0.426324] ASID allocator initialised with 32768 entries
10486 16:48:51.831055 <6>[ 0.432877] Serial: AMBA PL011 UART driver
10487 16:48:51.841565 <4>[ 0.441490] Trying to register duplicate clock ID: 134
10488 16:48:51.898737 <6>[ 0.500825] KASLR enabled
10489 16:48:51.912189 <6>[ 0.508524] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10490 16:48:51.918960 <6>[ 0.515542] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10491 16:48:51.926052 <6>[ 0.522036] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10492 16:48:51.931710 <6>[ 0.529045] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10493 16:48:51.938327 <6>[ 0.535537] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10494 16:48:51.945649 <6>[ 0.542548] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10495 16:48:51.951395 <6>[ 0.549040] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10496 16:48:51.957877 <6>[ 0.556049] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10497 16:48:51.960946 <6>[ 0.563545] ACPI: Interpreter disabled.
10498 16:48:51.969852 <6>[ 0.569929] iommu: Default domain type: Translated
10499 16:48:51.977012 <6>[ 0.575095] iommu: DMA domain TLB invalidation policy: strict mode
10500 16:48:51.979469 <5>[ 0.581747] SCSI subsystem initialized
10501 16:48:51.986261 <6>[ 0.585987] usbcore: registered new interface driver usbfs
10502 16:48:51.993361 <6>[ 0.591720] usbcore: registered new interface driver hub
10503 16:48:51.996121 <6>[ 0.597275] usbcore: registered new device driver usb
10504 16:48:52.003680 <6>[ 0.603378] pps_core: LinuxPPS API ver. 1 registered
10505 16:48:52.013851 <6>[ 0.608572] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10506 16:48:52.016846 <6>[ 0.617920] PTP clock support registered
10507 16:48:52.019511 <6>[ 0.622164] EDAC MC: Ver: 3.0.0
10508 16:48:52.028472 <6>[ 0.627353] FPGA manager framework
10509 16:48:52.034155 <6>[ 0.631031] Advanced Linux Sound Architecture Driver Initialized.
10510 16:48:52.037211 <6>[ 0.637805] vgaarb: loaded
10511 16:48:52.044263 <6>[ 0.640971] clocksource: Switched to clocksource arch_sys_counter
10512 16:48:52.047128 <5>[ 0.647426] VFS: Disk quotas dquot_6.6.0
10513 16:48:52.053993 <6>[ 0.651611] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10514 16:48:52.057169 <6>[ 0.658806] pnp: PnP ACPI: disabled
10515 16:48:52.065786 <6>[ 0.665483] NET: Registered PF_INET protocol family
10516 16:48:52.075037 <6>[ 0.671063] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10517 16:48:52.086526 <6>[ 0.683345] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10518 16:48:52.096323 <6>[ 0.692164] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10519 16:48:52.102823 <6>[ 0.700137] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10520 16:48:52.113382 <6>[ 0.708839] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10521 16:48:52.119364 <6>[ 0.718590] TCP: Hash tables configured (established 65536 bind 65536)
10522 16:48:52.126149 <6>[ 0.725453] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10523 16:48:52.136279 <6>[ 0.732652] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 16:48:52.142708 <6>[ 0.740356] NET: Registered PF_UNIX/PF_LOCAL protocol family
10525 16:48:52.149906 <6>[ 0.746529] RPC: Registered named UNIX socket transport module.
10526 16:48:52.152817 <6>[ 0.752685] RPC: Registered udp transport module.
10527 16:48:52.160007 <6>[ 0.757620] RPC: Registered tcp transport module.
10528 16:48:52.166157 <6>[ 0.762553] RPC: Registered tcp NFSv4.1 backchannel transport module.
10529 16:48:52.168774 <6>[ 0.769225] PCI: CLS 0 bytes, default 64
10530 16:48:52.172710 <6>[ 0.773624] Unpacking initramfs...
10531 16:48:52.182190 <6>[ 0.777718] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10532 16:48:52.188815 <6>[ 0.786364] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10533 16:48:52.195022 <6>[ 0.795159] kvm [1]: IPA Size Limit: 40 bits
10534 16:48:52.198552 <6>[ 0.799685] kvm [1]: GICv3: no GICV resource entry
10535 16:48:52.205262 <6>[ 0.804707] kvm [1]: disabling GICv2 emulation
10536 16:48:52.211856 <6>[ 0.809396] kvm [1]: GIC system register CPU interface enabled
10537 16:48:52.214973 <6>[ 0.815562] kvm [1]: vgic interrupt IRQ18
10538 16:48:52.221348 <6>[ 0.819921] kvm [1]: VHE mode initialized successfully
10539 16:48:52.225976 <5>[ 0.826358] Initialise system trusted keyrings
10540 16:48:52.231162 <6>[ 0.831158] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10541 16:48:52.241893 <6>[ 0.841381] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10542 16:48:52.248174 <5>[ 0.847752] NFS: Registering the id_resolver key type
10543 16:48:52.251034 <5>[ 0.853057] Key type id_resolver registered
10544 16:48:52.257863 <5>[ 0.857473] Key type id_legacy registered
10545 16:48:52.264699 <6>[ 0.861771] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10546 16:48:52.271376 <6>[ 0.868693] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10547 16:48:52.277528 <6>[ 0.876408] 9p: Installing v9fs 9p2000 file system support
10548 16:48:52.314075 <5>[ 0.914162] Key type asymmetric registered
10549 16:48:52.318086 <5>[ 0.918493] Asymmetric key parser 'x509' registered
10550 16:48:52.327132 <6>[ 0.923634] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10551 16:48:52.330263 <6>[ 0.931252] io scheduler mq-deadline registered
10552 16:48:52.333656 <6>[ 0.936013] io scheduler kyber registered
10553 16:48:52.352856 <6>[ 0.952907] EINJ: ACPI disabled.
10554 16:48:52.385366 <4>[ 0.978402] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10555 16:48:52.394986 <4>[ 0.989068] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 16:48:52.410155 <6>[ 1.009964] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10557 16:48:52.417958 <6>[ 1.017928] printk: console [ttyS0] disabled
10558 16:48:52.445938 <6>[ 1.042572] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10559 16:48:52.452329 <6>[ 1.052050] printk: console [ttyS0] enabled
10560 16:48:52.455442 <6>[ 1.052050] printk: console [ttyS0] enabled
10561 16:48:52.462181 <6>[ 1.060945] printk: bootconsole [mtk8250] disabled
10562 16:48:52.465391 <6>[ 1.060945] printk: bootconsole [mtk8250] disabled
10563 16:48:52.471902 <6>[ 1.072204] SuperH (H)SCI(F) driver initialized
10564 16:48:52.475315 <6>[ 1.077472] msm_serial: driver initialized
10565 16:48:52.490070 <6>[ 1.086447] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10566 16:48:52.499494 <6>[ 1.095004] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10567 16:48:52.506183 <6>[ 1.103545] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10568 16:48:52.516331 <6>[ 1.112175] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10569 16:48:52.526240 <6>[ 1.120880] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10570 16:48:52.532652 <6>[ 1.129600] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10571 16:48:52.542507 <6>[ 1.138141] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10572 16:48:52.549288 <6>[ 1.146947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10573 16:48:52.558890 <6>[ 1.155490] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10574 16:48:52.571112 <6>[ 1.171203] loop: module loaded
10575 16:48:52.577784 <6>[ 1.177267] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10576 16:48:52.600510 <4>[ 1.200712] mtk-pmic-keys: Failed to locate of_node [id: -1]
10577 16:48:52.607575 <6>[ 1.208004] megasas: 07.719.03.00-rc1
10578 16:48:52.617698 <6>[ 1.217733] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10579 16:48:52.624590 <6>[ 1.224382] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10580 16:48:52.640301 <6>[ 1.240333] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10581 16:48:52.700586 <6>[ 1.293776] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10582 16:48:53.835831 <6>[ 2.435839] Freeing initrd memory: 39188K
10583 16:48:53.845970 <6>[ 2.446108] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10584 16:48:53.857212 <6>[ 2.457198] tun: Universal TUN/TAP device driver, 1.6
10585 16:48:53.860462 <6>[ 2.463258] thunder_xcv, ver 1.0
10586 16:48:53.863463 <6>[ 2.466765] thunder_bgx, ver 1.0
10587 16:48:53.866676 <6>[ 2.470259] nicpf, ver 1.0
10588 16:48:53.877245 <6>[ 2.474287] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10589 16:48:53.881051 <6>[ 2.481763] hns3: Copyright (c) 2017 Huawei Corporation.
10590 16:48:53.887449 <6>[ 2.487349] hclge is initializing
10591 16:48:53.890260 <6>[ 2.490936] e1000: Intel(R) PRO/1000 Network Driver
10592 16:48:53.897070 <6>[ 2.496066] e1000: Copyright (c) 1999-2006 Intel Corporation.
10593 16:48:53.900395 <6>[ 2.502080] e1000e: Intel(R) PRO/1000 Network Driver
10594 16:48:53.907113 <6>[ 2.507296] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10595 16:48:53.913395 <6>[ 2.513482] igb: Intel(R) Gigabit Ethernet Network Driver
10596 16:48:53.920106 <6>[ 2.519132] igb: Copyright (c) 2007-2014 Intel Corporation.
10597 16:48:53.927274 <6>[ 2.524971] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10598 16:48:53.933570 <6>[ 2.531490] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10599 16:48:53.936800 <6>[ 2.537950] sky2: driver version 1.30
10600 16:48:53.943727 <6>[ 2.542925] VFIO - User Level meta-driver version: 0.3
10601 16:48:53.950867 <6>[ 2.551101] usbcore: registered new interface driver usb-storage
10602 16:48:53.957630 <6>[ 2.557548] usbcore: registered new device driver onboard-usb-hub
10603 16:48:53.966163 <6>[ 2.566609] mt6397-rtc mt6359-rtc: registered as rtc0
10604 16:48:53.977124 <6>[ 2.572078] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:48:53 UTC (1685810933)
10605 16:48:53.979216 <6>[ 2.581647] i2c_dev: i2c /dev entries driver
10606 16:48:53.996181 <6>[ 2.593368] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10607 16:48:54.003487 <6>[ 2.603620] sdhci: Secure Digital Host Controller Interface driver
10608 16:48:54.010492 <6>[ 2.610059] sdhci: Copyright(c) Pierre Ossman
10609 16:48:54.016947 <6>[ 2.615448] Synopsys Designware Multimedia Card Interface Driver
10610 16:48:54.020198 <6>[ 2.622054] mmc0: CQHCI version 5.10
10611 16:48:54.026533 <6>[ 2.622593] sdhci-pltfm: SDHCI platform and OF driver helper
10612 16:48:54.033587 <6>[ 2.633903] ledtrig-cpu: registered to indicate activity on CPUs
10613 16:48:54.044427 <6>[ 2.641249] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10614 16:48:54.047308 <6>[ 2.648634] usbcore: registered new interface driver usbhid
10615 16:48:54.054512 <6>[ 2.654461] usbhid: USB HID core driver
10616 16:48:54.061376 <6>[ 2.658707] spi_master spi0: will run message pump with realtime priority
10617 16:48:54.110160 <6>[ 2.703893] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10618 16:48:54.129093 <6>[ 2.719203] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10619 16:48:54.132483 <6>[ 2.732786] mmc0: Command Queue Engine enabled
10620 16:48:54.139289 <6>[ 2.734741] cros-ec-spi spi0.0: Chrome EC device registered
10621 16:48:54.146248 <6>[ 2.737518] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10622 16:48:54.149398 <6>[ 2.750619] mmcblk0: mmc0:0001 DA4128 116 GiB
10623 16:48:54.165879 <6>[ 2.762678] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10624 16:48:54.172394 <6>[ 2.762752] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10625 16:48:54.178811 <6>[ 2.774160] NET: Registered PF_PACKET protocol family
10626 16:48:54.182085 <6>[ 2.779343] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10627 16:48:54.188904 <6>[ 2.783340] 9pnet: Installing 9P2000 support
10628 16:48:54.192381 <6>[ 2.789126] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10629 16:48:54.199258 <5>[ 2.793016] Key type dns_resolver registered
10630 16:48:54.205044 <6>[ 2.798887] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10631 16:48:54.208768 <6>[ 2.803332] registered taskstats version 1
10632 16:48:54.212035 <5>[ 2.813617] Loading compiled-in X.509 certificates
10633 16:48:54.247719 <4>[ 2.841412] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10634 16:48:54.257529 <4>[ 2.852131] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 16:48:54.268154 <3>[ 2.865238] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10636 16:48:54.280368 <6>[ 2.880729] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10637 16:48:54.287259 <6>[ 2.887551] xhci-mtk 11200000.usb: xHCI Host Controller
10638 16:48:54.293795 <6>[ 2.893060] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10639 16:48:54.304008 <6>[ 2.900912] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10640 16:48:54.310428 <6>[ 2.910351] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10641 16:48:54.317521 <6>[ 2.916527] xhci-mtk 11200000.usb: xHCI Host Controller
10642 16:48:54.323563 <6>[ 2.922036] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10643 16:48:54.330671 <6>[ 2.929704] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10644 16:48:54.337474 <6>[ 2.937624] hub 1-0:1.0: USB hub found
10645 16:48:54.340660 <6>[ 2.941664] hub 1-0:1.0: 1 port detected
10646 16:48:54.350885 <6>[ 2.946024] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10647 16:48:54.353900 <6>[ 2.954826] hub 2-0:1.0: USB hub found
10648 16:48:54.357468 <6>[ 2.958863] hub 2-0:1.0: 1 port detected
10649 16:48:54.365594 <6>[ 2.966058] mtk-msdc 11f70000.mmc: Got CD GPIO
10650 16:48:54.382778 <6>[ 2.979921] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10651 16:48:54.389725 <6>[ 2.987952] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10652 16:48:54.399263 <4>[ 2.995931] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10653 16:48:54.409471 <6>[ 3.005604] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10654 16:48:54.416134 <6>[ 3.013686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10655 16:48:54.425826 <6>[ 3.021723] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10656 16:48:54.432973 <6>[ 3.029641] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10657 16:48:54.439062 <6>[ 3.037470] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10658 16:48:54.449106 <6>[ 3.045291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10659 16:48:54.459193 <6>[ 3.055997] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10660 16:48:54.468810 <6>[ 3.064366] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10661 16:48:54.475726 <6>[ 3.072727] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10662 16:48:54.486092 <6>[ 3.081072] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10663 16:48:54.492225 <6>[ 3.089414] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10664 16:48:54.502137 <6>[ 3.097757] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10665 16:48:54.508505 <6>[ 3.106100] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10666 16:48:54.518431 <6>[ 3.114443] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10667 16:48:54.525655 <6>[ 3.122786] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10668 16:48:54.535112 <6>[ 3.131130] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10669 16:48:54.541764 <6>[ 3.139472] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10670 16:48:54.551272 <6>[ 3.147816] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10671 16:48:54.557868 <6>[ 3.156159] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10672 16:48:54.567332 <6>[ 3.164503] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10673 16:48:54.577498 <6>[ 3.172848] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10674 16:48:54.583921 <6>[ 3.181750] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10675 16:48:54.590434 <6>[ 3.189192] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10676 16:48:54.597214 <6>[ 3.196229] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10677 16:48:54.603820 <6>[ 3.203329] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10678 16:48:54.610613 <6>[ 3.210623] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10679 16:48:54.620434 <6>[ 3.217530] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10680 16:48:54.630599 <6>[ 3.226668] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10681 16:48:54.640319 <6>[ 3.235795] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10682 16:48:54.650533 <6>[ 3.245120] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10683 16:48:54.660140 <6>[ 3.254597] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10684 16:48:54.666985 <6>[ 3.264071] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10685 16:48:54.676571 <6>[ 3.273198] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10686 16:48:54.686583 <6>[ 3.282674] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10687 16:48:54.696416 <6>[ 3.291812] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10688 16:48:54.706882 <6>[ 3.301114] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10689 16:48:54.716320 <6>[ 3.311280] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10690 16:48:54.726517 <6>[ 3.322785] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10691 16:48:54.772259 <6>[ 3.369251] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10692 16:48:54.926452 <6>[ 3.526592] hub 1-1:1.0: USB hub found
10693 16:48:54.929489 <6>[ 3.531076] hub 1-1:1.0: 4 ports detected
10694 16:48:55.052707 <6>[ 3.649462] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10695 16:48:55.077825 <6>[ 3.677728] hub 2-1:1.0: USB hub found
10696 16:48:55.080887 <6>[ 3.682131] hub 2-1:1.0: 3 ports detected
10697 16:48:55.252706 <6>[ 3.849245] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10698 16:48:55.385165 <6>[ 3.985516] hub 1-1.4:1.0: USB hub found
10699 16:48:55.388419 <6>[ 3.990190] hub 1-1.4:1.0: 2 ports detected
10700 16:48:55.464248 <6>[ 4.061494] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10701 16:48:55.683794 <6>[ 4.281140] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10702 16:48:55.876023 <6>[ 4.473246] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10703 16:49:06.997060 <6>[ 15.601834] ALSA device list:
10704 16:49:07.003289 <6>[ 15.605091] No soundcards found.
10705 16:49:07.015876 <6>[ 15.617462] Freeing unused kernel memory: 8384K
10706 16:49:07.018441 <6>[ 15.622369] Run /init as init process
10707 16:49:07.049478 <6>[ 15.650988] NET: Registered PF_INET6 protocol family
10708 16:49:07.055764 <6>[ 15.657225] Segment Routing with IPv6
10709 16:49:07.058945 <6>[ 15.661180] In-situ OAM (IOAM) with IPv6
10710 16:49:07.093664 <30>[ 15.675576] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10711 16:49:07.097085 <30>[ 15.699386] systemd[1]: Detected architecture arm64.
10712 16:49:07.097663
10713 16:49:07.103145 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10714 16:49:07.103624
10715 16:49:07.119630 <30>[ 15.721345] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10716 16:49:07.259737 <30>[ 15.858132] systemd[1]: Queued start job for default target Graphical Interface.
10717 16:49:07.292833 <30>[ 15.894567] systemd[1]: Created slice system-getty.slice.
10718 16:49:07.299805 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10719 16:49:07.316085 <30>[ 15.917914] systemd[1]: Created slice system-modprobe.slice.
10720 16:49:07.323070 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10721 16:49:07.339949 <30>[ 15.941926] systemd[1]: Created slice system-serial\x2dgetty.slice.
10722 16:49:07.349973 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10723 16:49:07.364927 <30>[ 15.966253] systemd[1]: Created slice User and Session Slice.
10724 16:49:07.371053 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10725 16:49:07.392239 <30>[ 15.989819] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10726 16:49:07.401516 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10727 16:49:07.420067 <30>[ 16.017756] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10728 16:49:07.426005 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10729 16:49:07.446757 <30>[ 16.041347] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10730 16:49:07.453520 <30>[ 16.053382] systemd[1]: Reached target Local Encrypted Volumes.
10731 16:49:07.459160 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10732 16:49:07.475956 <30>[ 16.077612] systemd[1]: Reached target Paths.
10733 16:49:07.479680 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10734 16:49:07.495286 <30>[ 16.097305] systemd[1]: Reached target Remote File Systems.
10735 16:49:07.502188 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10736 16:49:07.515889 <30>[ 16.117274] systemd[1]: Reached target Slices.
10737 16:49:07.522287 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10738 16:49:07.535510 <30>[ 16.137292] systemd[1]: Reached target Swap.
10739 16:49:07.539280 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10740 16:49:07.559065 <30>[ 16.157578] systemd[1]: Listening on initctl Compatibility Named Pipe.
10741 16:49:07.565911 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10742 16:49:07.572319 <30>[ 16.172299] systemd[1]: Listening on Journal Audit Socket.
10743 16:49:07.579030 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10744 16:49:07.591805 <30>[ 16.193549] systemd[1]: Listening on Journal Socket (/dev/log).
10745 16:49:07.599239 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10746 16:49:07.615669 <30>[ 16.217572] systemd[1]: Listening on Journal Socket.
10747 16:49:07.622657 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10748 16:49:07.639213 <30>[ 16.237597] systemd[1]: Listening on Network Service Netlink Socket.
10749 16:49:07.645922 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10750 16:49:07.660278 <30>[ 16.262024] systemd[1]: Listening on udev Control Socket.
10751 16:49:07.666980 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10752 16:49:07.684187 <30>[ 16.285958] systemd[1]: Listening on udev Kernel Socket.
10753 16:49:07.690668 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10754 16:49:07.724034 <30>[ 16.325384] systemd[1]: Mounting Huge Pages File System...
10755 16:49:07.730083 Mounting [0;1;39mHuge Pages File System[0m...
10756 16:49:07.745738 <30>[ 16.347323] systemd[1]: Mounting POSIX Message Queue File System...
10757 16:49:07.752038 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10758 16:49:07.769866 <30>[ 16.371416] systemd[1]: Mounting Kernel Debug File System...
10759 16:49:07.775823 Mounting [0;1;39mKernel Debug File System[0m...
10760 16:49:07.795088 <30>[ 16.393577] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10761 16:49:07.806089 <30>[ 16.404643] systemd[1]: Starting Create list of static device nodes for the current kernel...
10762 16:49:07.813354 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10763 16:49:07.829743 <30>[ 16.431598] systemd[1]: Starting Load Kernel Module configfs...
10764 16:49:07.836504 Starting [0;1;39mLoad Kernel Module configfs[0m...
10765 16:49:07.853855 <30>[ 16.455609] systemd[1]: Starting Load Kernel Module drm...
10766 16:49:07.860153 Starting [0;1;39mLoad Kernel Module drm[0m...
10767 16:49:07.878855 <30>[ 16.477432] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10768 16:49:07.904235 <30>[ 16.505794] systemd[1]: Starting Journal Service...
10769 16:49:07.907001 Starting [0;1;39mJournal Service[0m...
10770 16:49:07.926278 <30>[ 16.528186] systemd[1]: Starting Load Kernel Modules...
10771 16:49:07.933239 Starting [0;1;39mLoad Kernel Modules[0m...
10772 16:49:07.953693 <30>[ 16.552190] systemd[1]: Starting Remount Root and Kernel File Systems...
10773 16:49:07.960398 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10774 16:49:07.978299 <30>[ 16.579724] systemd[1]: Starting Coldplug All udev Devices...
10775 16:49:07.984464 Starting [0;1;39mColdplug All udev Devices[0m...
10776 16:49:08.002458 <30>[ 16.604012] systemd[1]: Mounted Huge Pages File System.
10777 16:49:08.008387 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10778 16:49:08.024340 <30>[ 16.625714] systemd[1]: Started Journal Service.
10779 16:49:08.030293 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10780 16:49:08.045366 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10781 16:49:08.060244 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10782 16:49:08.079868 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10783 16:49:08.097028 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10784 16:49:08.116846 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10785 16:49:08.132587 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10786 16:49:08.152551 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10787 16:49:08.167769 See 'systemctl status systemd-remount-fs.service' for details.
10788 16:49:08.211885 Mounting [0;1;39mKernel Configuration File System[0m...
10789 16:49:08.229767 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10790 16:49:08.248228 <46>[ 16.846763] systemd-journald[175]: Received client request to flush runtime journal.
10791 16:49:08.257164 Starting [0;1;39mLoad/Save Random Seed[0m...
10792 16:49:08.275010 Starting [0;1;39mApply Kernel Variables[0m...
10793 16:49:08.291059 Starting [0;1;39mCreate System Users[0m...
10794 16:49:08.312786 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10795 16:49:08.336003 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10796 16:49:08.352504 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10797 16:49:08.372768 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10798 16:49:08.392816 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10799 16:49:08.408856 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10800 16:49:08.465036 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10801 16:49:08.486986 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10802 16:49:08.500453 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10803 16:49:08.515524 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10804 16:49:08.568341 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10805 16:49:08.591646 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10806 16:49:08.611997 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10807 16:49:08.632229 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10808 16:49:08.685045 Starting [0;1;39mNetwork Service[0m...
10809 16:49:08.707597 Starting [0;1;39mNetwork Time Synchronization[0m...
10810 16:49:08.729135 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10811 16:49:08.773482 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10812 16:49:08.788167 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10813 16:49:08.811917 <6>[ 17.410860] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10814 16:49:08.820300 [[0;32m OK [<6>[ 17.423159] remoteproc remoteproc0: scp is available
10815 16:49:08.827153 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10816 16:49:08.833526 <6>[ 17.434603] remoteproc remoteproc0: powering up scp
10817 16:49:08.840064 <6>[ 17.439786] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10818 16:49:08.847273 <6>[ 17.449586] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10819 16:49:08.866347 <6>[ 17.465197] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10820 16:49:08.873382 <6>[ 17.473061] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10821 16:49:08.883711 <6>[ 17.481965] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10822 16:49:08.893532 Startin<4>[ 17.491824] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10823 16:49:08.900334 g [0;1;39mLoad/<6>[ 17.494520] usbcore: registered new interface driver r8152
10824 16:49:08.909756 Save Screen …of leds:white:kbd<4>[ 17.508541] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10825 16:49:08.913554 _backlight[0m...
10826 16:49:08.953990 <3>[ 17.552911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 16:49:08.960704 <3>[ 17.561057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10828 16:49:08.970325 <3>[ 17.569201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 16:49:08.980745 <3>[ 17.579473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10830 16:49:08.990966 <6>[ 17.581387] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10831 16:49:08.997558 <6>[ 17.581395] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10832 16:49:09.003765 <3>[ 17.587692] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 16:49:09.010804 <6>[ 17.596247] remoteproc remoteproc0: remote processor scp is now up
10834 16:49:09.020463 <3>[ 17.603375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10835 16:49:09.023803 <6>[ 17.612248] mc: Linux media interface: v0.10
10836 16:49:09.030449 <3>[ 17.617783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10837 16:49:09.037479 <3>[ 17.621262] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10838 16:49:09.046932 <6>[ 17.630132] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10839 16:49:09.053673 <3>[ 17.630408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 16:49:09.060035 <6>[ 17.644527] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10841 16:49:09.066934 Starting [0;1;39mNetwork Name Resolution[0m...
10842 16:49:09.076336 <3>[ 17.673748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 16:49:09.086592 <4>[ 17.684375] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10844 16:49:09.089750 <4>[ 17.684375] Fallback method does not support PEC.
10845 16:49:09.099395 <6>[ 17.685238] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10846 16:49:09.105808 <3>[ 17.699045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 16:49:09.112698 <6>[ 17.705365] pci_bus 0000:00: root bus resource [bus 00-ff]
10848 16:49:09.119731 <3>[ 17.713277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 16:49:09.129548 <3>[ 17.713298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10850 16:49:09.136146 <3>[ 17.713480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 16:49:09.145803 <6>[ 17.719301] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10852 16:49:09.155500 <6>[ 17.719310] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10853 16:49:09.159031 <6>[ 17.719383] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10854 16:49:09.168983 <3>[ 17.727837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10855 16:49:09.175292 <3>[ 17.735843] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10856 16:49:09.181951 <6>[ 17.736031] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10857 16:49:09.184982 <6>[ 17.736177] pci 0000:00:00.0: supports D1 D2
10858 16:49:09.192390 <6>[ 17.736183] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10859 16:49:09.202179 <6>[ 17.738782] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10860 16:49:09.208921 <6>[ 17.738945] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10861 16:49:09.215017 <6>[ 17.738985] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10862 16:49:09.222061 <6>[ 17.739008] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10863 16:49:09.231567 <6>[ 17.739027] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10864 16:49:09.235066 <6>[ 17.739165] pci 0000:01:00.0: supports D1 D2
10865 16:49:09.241774 <6>[ 17.739173] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10866 16:49:09.251207 <6>[ 17.739186] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10867 16:49:09.261660 <6>[ 17.740364] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10868 16:49:09.268660 <3>[ 17.743912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 16:49:09.275344 <6>[ 17.753375] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10870 16:49:09.285307 <3>[ 17.760945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 16:49:09.291932 <3>[ 17.760954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 16:49:09.299630 <6>[ 17.767980] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10873 16:49:09.309098 <4>[ 17.768576] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10874 16:49:09.319576 <4>[ 17.768592] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10875 16:49:09.326714 <3>[ 17.775470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 16:49:09.333513 <6>[ 17.781774] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10877 16:49:09.343128 <6>[ 17.781808] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10878 16:49:09.349731 <3>[ 17.837678] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 16:49:09.359853 <6>[ 17.839153] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10880 16:49:09.366498 <6>[ 17.840821] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10881 16:49:09.377358 <6>[ 17.842233] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10882 16:49:09.383104 <3>[ 17.861252] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10883 16:49:09.390647 <6>[ 17.868200] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10884 16:49:09.393631 <6>[ 17.869256] r8152 2-1.3:1.0 eth0: v1.12.13
10885 16:49:09.400318 <3>[ 17.876565] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10886 16:49:09.409877 <3>[ 17.878255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 16:49:09.416830 <3>[ 17.879132] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10888 16:49:09.423561 <6>[ 17.883184] pci 0000:00:00.0: PCI bridge to [bus 01]
10889 16:49:09.433609 <6>[ 17.891356] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10890 16:49:09.439916 <6>[ 17.899347] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10891 16:49:09.446935 <6>[ 17.899529] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10892 16:49:09.456264 <3>[ 17.902418] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 16:49:09.462924 <6>[ 17.932198] videodev: Linux video capture interface: v2.00
10894 16:49:09.469653 <6>[ 17.934117] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10895 16:49:09.472512 <6>[ 17.941494] usbcore: registered new interface driver cdc_ether
10896 16:49:09.482795 <3>[ 17.942700] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 16:49:09.489573 <6>[ 17.950865] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10898 16:49:09.496433 <3>[ 17.955599] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10899 16:49:09.499361 <6>[ 17.967460] Bluetooth: Core ver 2.22
10900 16:49:09.506187 <6>[ 17.975085] usbcore: registered new interface driver r8153_ecm
10901 16:49:09.514128 <6>[ 17.982884] NET: Registered PF_BLUETOOTH protocol family
10902 16:49:09.522916 <3>[ 17.986468] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 16:49:09.530634 <3>[ 17.987288] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10904 16:49:09.537227 <6>[ 17.999642] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10905 16:49:09.544626 <5>[ 18.001230] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10906 16:49:09.551073 <6>[ 18.001434] Bluetooth: HCI device and connection manager initialized
10907 16:49:09.557311 <6>[ 18.004513] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10908 16:49:09.567846 <3>[ 18.009318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 16:49:09.577598 <6>[ 18.010528] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10910 16:49:09.584923 <6>[ 18.010926] usbcore: registered new interface driver uvcvideo
10911 16:49:09.591171 <5>[ 18.016190] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10912 16:49:09.597775 <6>[ 18.017018] Bluetooth: HCI socket layer initialized
10913 16:49:09.601328 <6>[ 18.017031] Bluetooth: L2CAP socket layer initialized
10914 16:49:09.607881 <6>[ 18.017062] Bluetooth: SCO socket layer initialized
10915 16:49:09.615064 <6>[ 18.028298] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10916 16:49:09.617915 <6>[ 18.081969] usbcore: registered new interface driver btusb
10917 16:49:09.630929 <4>[ 18.090339] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10918 16:49:09.637566 <4>[ 18.099063] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10919 16:49:09.644367 <3>[ 18.104336] Bluetooth: hci0: Failed to load firmware file (-2)
10920 16:49:09.651328 <6>[ 18.108153] cfg80211: failed to load regulatory.db
10921 16:49:09.657679 <3>[ 18.113294] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 16:49:09.664139 <3>[ 18.114253] Bluetooth: hci0: Failed to set up firmware (-2)
10923 16:49:09.670983 <6>[ 18.171442] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10924 16:49:09.684453 <4>[ 18.173596] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10925 16:49:09.687099 <6>[ 18.186129] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10926 16:49:09.694336 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10927 16:49:09.712066 <6>[ 18.313233] mt7921e 0000:01:00.0: ASIC revision: 79610010
10928 16:49:09.717946 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10929 16:49:09.739838 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10930 16:49:09.761994 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10931 16:49:09.818310 <4>[ 18.413036] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10932 16:49:09.935512 <4>[ 18.531248] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10933 16:49:09.942186 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10934 16:49:09.956446 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10935 16:49:09.974598 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10936 16:49:09.987878 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10937 16:49:10.010724 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10938 16:49:10.023241 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10939 16:49:10.061154 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchron<4>[ 18.655843] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10940 16:49:10.061738 ized[0m.
10941 16:49:10.080304 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10942 16:49:10.091454 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10943 16:49:10.111492 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10944 16:49:10.123265 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10945 16:49:10.139517 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10946 16:49:10.158543 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10947 16:49:10.180266 <4>[ 18.775568] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10948 16:49:10.208371 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10949 16:49:10.233898 Starting [0;1;39mUser Login Management[0m...
10950 16:49:10.249712 Starting [0;1;39mPermit User Sessions[0m...
10951 16:49:10.267069 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10952 16:49:10.288609 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10953 16:49:10.302001 <4>[ 18.897666] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10954 16:49:10.309139 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10955 16:49:10.332009 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10956 16:49:10.354715 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10957 16:49:10.375519 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10958 16:49:10.396676 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10959 16:49:10.403954 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10960 16:49:10.432408 [[0;32m OK [0m] Reached target [0;1;39mGrap<4>[ 19.028657] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10961 16:49:10.435667 hical Interface[0m.
10962 16:49:10.491744 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10963 16:49:10.515568 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10964 16:49:10.553892 <4>[ 19.148780] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10965 16:49:10.578006
10966 16:49:10.578799
10967 16:49:10.579863 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10968 16:49:10.580271
10969 16:49:10.583531 debian-bullseye-arm64 login: root (automatic login)
10970 16:49:10.584102
10971 16:49:10.584469
10972 16:49:10.600210 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023 aarch64
10973 16:49:10.600784
10974 16:49:10.606269 The programs included with the Debian GNU/Linux system are free software;
10975 16:49:10.612625 the exact distribution terms for each program are described in the
10976 16:49:10.615967 individual files in /usr/share/doc/*/copyright.
10977 16:49:10.616431
10978 16:49:10.623221 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10979 16:49:10.626134 permitted by applicable law.
10980 16:49:10.627466 Matched prompt #10: / #
10982 16:49:10.628561 Setting prompt string to ['/ #']
10983 16:49:10.629037 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10985 16:49:10.630107 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10986 16:49:10.630649 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
10987 16:49:10.631043 Setting prompt string to ['/ #']
10988 16:49:10.631379 Forcing a shell prompt, looking for ['/ #']
10990 16:49:10.682396 / #
10991 16:49:10.683070 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10992 16:49:10.683535 Waiting using forced prompt support (timeout 00:02:30)
10993 16:49:10.684086 <4>[ 19.267754] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10994 16:49:10.689258
10995 16:49:10.690187 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10996 16:49:10.690751 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
10997 16:49:10.691265 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10998 16:49:10.691732 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
10999 16:49:10.692176 end: 2 depthcharge-action (duration 00:01:43) [common]
11000 16:49:10.692638 start: 3 lava-test-retry (timeout 00:07:59) [common]
11001 16:49:10.693102 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
11002 16:49:10.693494 Using namespace: common
11004 16:49:10.794693 / # #
11005 16:49:10.795338 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11006 16:49:10.795916 #<4>[ 19.387362] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11007 16:49:10.801679
11008 16:49:10.843413 Using /lava-10576304
11010 16:49:10.945039 / # export SHELL=/bin/sh
11011 16:49:10.945878 <6>[ 19.503365] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11012 16:49:10.946411 export SHELL=/bi<4>[ 19.511475] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11013 16:49:10.946796 n/sh<6>[ 19.511743] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11014 16:49:10.951242
11016 16:49:11.052987 / # . /lava-10576304/environment
11017 16:49:11.053820 . /lava-10576304/environment<3>[ 19.633488] mt7921e 0000:01:00.0: hardware init failed
11018 16:49:11.059409
11020 16:49:11.161075 / # /lava-10576304/bin/lava-test-runner /lava-10576304/0
11021 16:49:11.161850 Test shell timeout: 10s (minimum of the action and connection timeout)
11022 16:49:11.167665 /lava-10576304/bin/lava-test-runner /lava-10576304/0
11023 16:49:11.188998 + export TESTRUN_ID=0_v4l2-compliance-uvc
11024 16:49:11.192122 + cd /lava-10576304/0/tests/0_v4l2-compliance-uvc
11025 16:49:11.192695 + cat uuid
11026 16:49:11.195181 + UUID=10576304_1.5.2.3.1
11027 16:49:11.195648 + set +x
11028 16:49:11.202050 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10576304_1.5.2.3.1>
11029 16:49:11.202954 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10576304_1.5.2.3.1
11030 16:49:11.203364 Starting test lava.0_v4l2-compliance-uvc (10576304_1.5.2.3.1)
11031 16:49:11.203812 Skipping test definition patterns.
11032 16:49:11.205611 + /usr/bin/v4l2-parser.sh -d uvcvideo
11033 16:49:11.211903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11034 16:49:11.212480 device: /dev/video0
11035 16:49:11.213127 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11037 16:49:15.271262 <4>[ 23.873998] ------------[ cut here ]------------
11038 16:49:15.277473 <4>[ 23.878930] get_vaddr_frames() cannot follow VM_IO mapping
11039 16:49:15.292249 <4>[ 23.879072] WARNING: CPU: 2 PID: 313 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11040 16:49:15.337358 <4>[ 23.897176] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 btusb btintel btmtk btrtl btbcm mac80211 mtk_vcodec_enc libarc4 mtk_vcodec_common mtk_vpu v4l2_mem2mem uvcvideo cfg80211 videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops videobuf2_v4l2 r8153_ecm bluetooth videobuf2_common cdc_ether ecdh_generic videodev usbnet ecc cros_ec_rpmsg rfkill crct10dif_ce cros_ec_chardev mc elan_i2c sbs_battery cros_ec_typec r8152 elants_i2c hid_google_hammer hid_vivaldi_common pcie_mediatek_gen3 mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11041 16:49:15.348341 <4>[ 23.946568] CPU: 2 PID: 313 Comm: v4l2-compliance Not tainted 6.1.31 #1
11042 16:49:15.350421 <4>[ 23.953432] Hardware name: Google Spherion (rev0 - 3) (DT)
11043 16:49:15.357078 <4>[ 23.959167] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11044 16:49:15.363772 <4>[ 23.966378] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11045 16:49:15.370679 <4>[ 23.972471] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11046 16:49:15.373597 <4>[ 23.978561] sp : ffff8000091db810
11047 16:49:15.379898 <4>[ 23.982124] x29: ffff8000091db810 x28: ffffc8660e306000 x27: ffffc8660e302238
11048 16:49:15.390564 <4>[ 23.989511] x26: 0000000000000000 x25: ffffc8660e3064c0 x24: ffff7c73ce2dc538
11049 16:49:15.396812 <4>[ 23.996899] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11050 16:49:15.402997 <4>[ 24.004285] x20: 00000000fffffff2 x19: ffff7c73cd33a000 x18: fffffffffffe9628
11051 16:49:15.410089 <4>[ 24.011672] x17: 0000000000000000 x16: ffffc8666588bb60 x15: 0000000000000038
11052 16:49:15.419784 <4>[ 24.019059] x14: ffffc86667fc34a8 x13: 0000000000000642 x12: 0000000000000216
11053 16:49:15.427076 <4>[ 24.026446] x11: fffffffffffe9628 x10: fffffffffffe95f0 x9 : 00000000fffff216
11054 16:49:15.433292 <4>[ 24.033833] x8 : ffffc86667fc34a8 x7 : ffffc8666801b4a8 x6 : 0000000000001908
11055 16:49:15.439878 <4>[ 24.041220] x5 : ffff7c74fef3ca18 x4 : 00000000fffff216 x3 : ffffb40e9763a000
11056 16:49:15.449604 <4>[ 24.048606] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff7c73cd2be740
11057 16:49:15.450177 <4>[ 24.055993] Call trace:
11058 16:49:15.456476 <4>[ 24.058690] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11059 16:49:15.462716 <4>[ 24.064434] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11060 16:49:15.469440 <4>[ 24.070435] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11061 16:49:15.475906 <4>[ 24.076957] __prepare_userptr+0x280/0x410 [videobuf2_common]
11062 16:49:15.479149 <4>[ 24.082961] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11063 16:49:15.486155 <4>[ 24.088617] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11064 16:49:15.492741 <4>[ 24.094274] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11065 16:49:15.496707 <4>[ 24.099168] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11066 16:49:15.502463 <4>[ 24.104234] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11067 16:49:15.505764 <4>[ 24.109110] v4l_qbuf+0x48/0x60 [videodev]
11068 16:49:15.512360 <4>[ 24.113530] __video_do_ioctl+0x184/0x3d0 [videodev]
11069 16:49:15.515583 <4>[ 24.118773] video_usercopy+0x358/0x680 [videodev]
11070 16:49:15.522192 <4>[ 24.123844] video_ioctl2+0x18/0x30 [videodev]
11071 16:49:15.525709 <4>[ 24.128567] v4l2_ioctl+0x40/0x60 [videodev]
11072 16:49:15.529161 <4>[ 24.133118] __arm64_sys_ioctl+0xa8/0xf0
11073 16:49:15.532180 <4>[ 24.137303] invoke_syscall+0x48/0x114
11074 16:49:15.538912 <4>[ 24.141309] el0_svc_common.constprop.0+0x44/0xec
11075 16:49:15.542669 <4>[ 24.146265] do_el0_svc+0x2c/0xd0
11076 16:49:15.545507 <4>[ 24.149830] el0_svc+0x2c/0x84
11077 16:49:15.548764 <4>[ 24.153140] el0t_64_sync_handler+0xb8/0xc0
11078 16:49:15.552016 <4>[ 24.157575] el0t_64_sync+0x18c/0x190
11079 16:49:15.558813 <4>[ 24.161490] ---[ end trace 0000000000000000 ]---
11080 16:49:17.977403 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11081 16:49:17.987399 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11082 16:49:17.993196
11083 16:49:18.006257 Compliance test for uvcvideo device /dev/video0:
11084 16:49:18.012157
11085 16:49:18.021832 Driver Info:
11086 16:49:18.031967 Driver name : uvcvideo
11087 16:49:18.044195 Card type : HD User Facing: HD User Facing
11088 16:49:18.053335 Bus info : usb-11200000.usb-1.4.1
11089 16:49:18.059813 Driver version : 6.1.31
11090 16:49:18.068915 Capabilities : 0x84a00001
11091 16:49:18.081513 Metadata Capture
11092 16:49:18.090383 Streaming
11093 16:49:18.100248 Extended Pix Format
11094 16:49:18.109943 Device Capabilities
11095 16:49:18.119766 Device Caps : 0x04200001
11096 16:49:18.132288 Streaming
11097 16:49:18.141984 Extended Pix Format
11098 16:49:18.151288 Media Driver Info:
11099 16:49:18.161823 Driver name : uvcvideo
11100 16:49:18.174069 Model : HD User Facing: HD User Facing
11101 16:49:18.181449 Serial : 200901010001
11102 16:49:18.195502 Bus info : usb-11200000.usb-1.4.1
11103 16:49:18.202642 Media version : 6.1.31
11104 16:49:18.215696 Hardware revision: 0x00009758 (38744)
11105 16:49:18.222785 Driver version : 6.1.31
11106 16:49:18.233937 Interface Info:
11107 16:49:18.249192 <LAVA_SIGNAL_TESTSET START Interface-Info>
11108 16:49:18.249764 ID : 0x03000002
11109 16:49:18.250509 Received signal: <TESTSET> START Interface-Info
11110 16:49:18.250921 Starting test_set Interface-Info
11111 16:49:18.259837 Type : V4L Video
11112 16:49:18.270042 Entity Info:
11113 16:49:18.277350 <LAVA_SIGNAL_TESTSET STOP>
11114 16:49:18.278185 Received signal: <TESTSET> STOP
11115 16:49:18.278614 Closing test_set Interface-Info
11116 16:49:18.285962 <LAVA_SIGNAL_TESTSET START Entity-Info>
11117 16:49:18.286827 Received signal: <TESTSET> START Entity-Info
11118 16:49:18.287226 Starting test_set Entity-Info
11119 16:49:18.288811 ID : 0x00000001 (1)
11120 16:49:18.299565 Name : HD User Facing: HD User Facing
11121 16:49:18.306791 Function : V4L2 I/O
11122 16:49:18.317056 Flags : default
11123 16:49:18.327426 Pad 0x01000007 : 0: Sink
11124 16:49:18.348040 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11125 16:49:18.348611
11126 16:49:18.360083 Required ioctls:
11127 16:49:18.366455 <LAVA_SIGNAL_TESTSET STOP>
11128 16:49:18.367292 Received signal: <TESTSET> STOP
11129 16:49:18.367687 Closing test_set Entity-Info
11130 16:49:18.376155 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11131 16:49:18.376993 Received signal: <TESTSET> START Required-ioctls
11132 16:49:18.377393 Starting test_set Required-ioctls
11133 16:49:18.378952 test MC information (see 'Media Driver Info' above): OK
11134 16:49:18.404017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11135 16:49:18.404867 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11137 16:49:18.407386 test VIDIOC_QUERYCAP: OK
11138 16:49:18.424685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11139 16:49:18.425526 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11141 16:49:18.427657 test invalid ioctls: OK
11142 16:49:18.449630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11143 16:49:18.450198
11144 16:49:18.450869 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11146 16:49:18.459947 Allow for multiple opens:
11147 16:49:18.467920 <LAVA_SIGNAL_TESTSET STOP>
11148 16:49:18.468765 Received signal: <TESTSET> STOP
11149 16:49:18.469174 Closing test_set Required-ioctls
11150 16:49:18.477122 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11151 16:49:18.477956 Received signal: <TESTSET> START Allow-for-multiple-opens
11152 16:49:18.478379 Starting test_set Allow-for-multiple-opens
11153 16:49:18.479944 test second /dev/video0 open: OK
11154 16:49:18.501544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11155 16:49:18.502408 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11157 16:49:18.505035 test VIDIOC_QUERYCAP: OK
11158 16:49:18.525792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11159 16:49:18.526657 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11161 16:49:18.528796 test VIDIOC_G/S_PRIORITY: OK
11162 16:49:18.549958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11163 16:49:18.550848 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11165 16:49:18.553076 test for unlimited opens: OK
11166 16:49:18.572846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11167 16:49:18.573417
11168 16:49:18.574055 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11170 16:49:18.581540 Debug ioctls:
11171 16:49:18.587933 <LAVA_SIGNAL_TESTSET STOP>
11172 16:49:18.588779 Received signal: <TESTSET> STOP
11173 16:49:18.589195 Closing test_set Allow-for-multiple-opens
11174 16:49:18.597270 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11175 16:49:18.598104 Received signal: <TESTSET> START Debug-ioctls
11176 16:49:18.598531 Starting test_set Debug-ioctls
11177 16:49:18.600107 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11178 16:49:18.621155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11179 16:49:18.621989 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11181 16:49:18.627619 test VIDIOC_LOG_STATUS: OK (Not Supported)
11182 16:49:18.644248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11183 16:49:18.644806
11184 16:49:18.645440 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11186 16:49:18.653804 Input ioctls:
11187 16:49:18.659157 <LAVA_SIGNAL_TESTSET STOP>
11188 16:49:18.660000 Received signal: <TESTSET> STOP
11189 16:49:18.660395 Closing test_set Debug-ioctls
11190 16:49:18.668612 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11191 16:49:18.669461 Received signal: <TESTSET> START Input-ioctls
11192 16:49:18.669873 Starting test_set Input-ioctls
11193 16:49:18.672152 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11194 16:49:18.695039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11195 16:49:18.695878 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11197 16:49:18.698151 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11198 16:49:18.712556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11199 16:49:18.713395 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11201 16:49:18.719573 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11202 16:49:18.736289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11203 16:49:18.737106 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11205 16:49:18.742830 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11206 16:49:18.760744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11207 16:49:18.761471 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11209 16:49:18.764965 test VIDIOC_G/S/ENUMINPUT: OK
11210 16:49:18.784417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11211 16:49:18.785339 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11213 16:49:18.787934 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11214 16:49:18.808316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11215 16:49:18.809179 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11217 16:49:18.811797 Inputs: 1 Audio Inputs: 0 Tuners: 0
11218 16:49:18.819045
11219 16:49:18.835424 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11220 16:49:18.856496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11221 16:49:18.857338 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11223 16:49:18.863416 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11224 16:49:18.880957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11225 16:49:18.881794 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11227 16:49:18.887757 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11228 16:49:18.905263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11229 16:49:18.906107 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11231 16:49:18.911630 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11232 16:49:18.928498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11233 16:49:18.929340 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11235 16:49:18.934443 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11236 16:49:18.953073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11237 16:49:18.953644
11238 16:49:18.954286 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11240 16:49:18.972702 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11241 16:49:18.994518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11242 16:49:18.995360 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11244 16:49:19.000864 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11245 16:49:19.023428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11246 16:49:19.024267 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11248 16:49:19.026965 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11249 16:49:19.045200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11250 16:49:19.046037 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11252 16:49:19.048132 test VIDIOC_G/S_EDID: OK (Not Supported)
11253 16:49:19.069177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11254 16:49:19.069765
11255 16:49:19.070504 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11257 16:49:19.079944 Control ioctls (Input 0):
11258 16:49:19.086826 <LAVA_SIGNAL_TESTSET STOP>
11259 16:49:19.087665 Received signal: <TESTSET> STOP
11260 16:49:19.088049 Closing test_set Input-ioctls
11261 16:49:19.097061 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11262 16:49:19.097901 Received signal: <TESTSET> START Control-ioctls-Input-0
11263 16:49:19.098294 Starting test_set Control-ioctls-Input-0
11264 16:49:19.100709 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11265 16:49:19.124924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11266 16:49:19.125505 test VIDIOC_QUERYCTRL: OK
11267 16:49:19.126136 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11269 16:49:19.145495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11270 16:49:19.146332 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11272 16:49:19.148271 test VIDIOC_G/S_CTRL: OK
11273 16:49:19.169036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11274 16:49:19.169867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11276 16:49:19.172019 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11277 16:49:19.192646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11278 16:49:19.193476 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11280 16:49:19.199504 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11281 16:49:19.220398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11282 16:49:19.221253 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11284 16:49:19.222834 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11285 16:49:19.242398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11286 16:49:19.243288 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11288 16:49:19.244855 Standard Controls: 16 Private Controls: 0
11289 16:49:19.252499
11290 16:49:19.263607 Format ioctls (Input 0):
11291 16:49:19.270420 <LAVA_SIGNAL_TESTSET STOP>
11292 16:49:19.271293 Received signal: <TESTSET> STOP
11293 16:49:19.271691 Closing test_set Control-ioctls-Input-0
11294 16:49:19.279677 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11295 16:49:19.280517 Received signal: <TESTSET> START Format-ioctls-Input-0
11296 16:49:19.280964 Starting test_set Format-ioctls-Input-0
11297 16:49:19.282973 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11298 16:49:19.307517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11299 16:49:19.308362 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11301 16:49:19.310882 test VIDIOC_G/S_PARM: OK
11302 16:49:19.328177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11303 16:49:19.329020 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11305 16:49:19.331615 test VIDIOC_G_FBUF: OK (Not Supported)
11306 16:49:19.352470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11307 16:49:19.353343 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11309 16:49:19.355381 test VIDIOC_G_FMT: OK
11310 16:49:19.376952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11311 16:49:19.377815 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11313 16:49:19.380448 test VIDIOC_TRY_FMT: OK
11314 16:49:19.401237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11315 16:49:19.402079 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11317 16:49:19.407539 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11318 16:49:19.411716 test VIDIOC_S_FMT: OK
11319 16:49:19.436684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11320 16:49:19.437500 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11322 16:49:19.440176 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11323 16:49:19.461765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11324 16:49:19.462605 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11326 16:49:19.464979 test Cropping: OK (Not Supported)
11327 16:49:19.485462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11328 16:49:19.486314 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11330 16:49:19.488691 test Composing: OK (Not Supported)
11331 16:49:19.510906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11332 16:49:19.511772 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11334 16:49:19.514051 test Scaling: OK (Not Supported)
11335 16:49:19.535595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11336 16:49:19.536191
11337 16:49:19.536974 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11339 16:49:19.546293 Codec ioctls (Input 0):
11340 16:49:19.553744 <LAVA_SIGNAL_TESTSET STOP>
11341 16:49:19.554582 Received signal: <TESTSET> STOP
11342 16:49:19.554982 Closing test_set Format-ioctls-Input-0
11343 16:49:19.563012 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11344 16:49:19.563853 Received signal: <TESTSET> START Codec-ioctls-Input-0
11345 16:49:19.564246 Starting test_set Codec-ioctls-Input-0
11346 16:49:19.566194 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11347 16:49:19.587444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11348 16:49:19.588260 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11350 16:49:19.593629 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11351 16:49:19.613064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11352 16:49:19.613919 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11354 16:49:19.619453 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11355 16:49:19.637039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11356 16:49:19.637647
11357 16:49:19.638287 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11359 16:49:19.647277 Buffer ioctls (Input 0):
11360 16:49:19.653511 <LAVA_SIGNAL_TESTSET STOP>
11361 16:49:19.654343 Received signal: <TESTSET> STOP
11362 16:49:19.654785 Closing test_set Codec-ioctls-Input-0
11363 16:49:19.663272 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11364 16:49:19.664110 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11365 16:49:19.664509 Starting test_set Buffer-ioctls-Input-0
11366 16:49:19.665954 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11367 16:49:19.690992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11368 16:49:19.691576 test VIDIOC_EXPBUF: OK
11369 16:49:19.692226 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11371 16:49:19.712376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11372 16:49:19.713235 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11374 16:49:19.715085 test Requests: OK (Not Supported)
11375 16:49:19.736191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11376 16:49:19.736794
11377 16:49:19.737651 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11379 16:49:19.746049 Test input 0:
11380 16:49:19.755293
11381 16:49:19.764795 Streaming ioctls:
11382 16:49:19.771322 <LAVA_SIGNAL_TESTSET STOP>
11383 16:49:19.772152 Received signal: <TESTSET> STOP
11384 16:49:19.772545 Closing test_set Buffer-ioctls-Input-0
11385 16:49:19.780911 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11386 16:49:19.781751 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11387 16:49:19.782151 Starting test_set Streaming-ioctls_Test-input-0
11388 16:49:19.784619 test read/write: OK (Not Supported)
11389 16:49:19.804108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11390 16:49:19.804962 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11392 16:49:19.806913 test blocking wait: OK
11393 16:49:19.827329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11394 16:49:19.828186 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11396 16:49:19.837147 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11397 16:49:19.840493 test MMAP (no poll): FAIL
11398 16:49:19.862916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11399 16:49:19.863757 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11401 16:49:19.873518 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11402 16:49:19.874093 test MMAP (select): FAIL
11403 16:49:19.897272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11404 16:49:19.898111 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11406 16:49:19.907124 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11407 16:49:19.910456 test MMAP (epoll): FAIL
11408 16:49:19.932875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11409 16:49:19.933444
11410 16:49:19.934087 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11412 16:49:19.949056
11413 16:49:20.103290
11414 16:49:20.109430 test USERPTR (no poll): OK
11415 16:49:20.132535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11416 16:49:20.133104
11417 16:49:20.133744 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11419 16:49:20.143898
11420 16:49:20.295340
11421 16:49:20.301461 test USERPTR (select): OK
11422 16:49:20.326421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11423 16:49:20.327249 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11425 16:49:20.333097 test DMABUF: Cannot test, specify --expbuf-device
11426 16:49:20.333656
11427 16:49:20.352421 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11428 16:49:20.355874 <LAVA_TEST_RUNNER EXIT>
11429 16:49:20.356725 ok: lava_test_shell seems to have completed
11430 16:49:20.357131 Marking unfinished test run as failed
11432 16:49:20.362346 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11433 16:49:20.363037 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11434 16:49:20.363511 end: 3 lava-test-retry (duration 00:00:10) [common]
11435 16:49:20.363999 start: 4 finalize (timeout 00:07:50) [common]
11436 16:49:20.364474 start: 4.1 power-off (timeout 00:00:30) [common]
11437 16:49:20.365283 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11438 16:49:20.482169 >> Command sent successfully.
11439 16:49:20.486000 Returned 0 in 0 seconds
11440 16:49:20.586940 end: 4.1 power-off (duration 00:00:00) [common]
11442 16:49:20.588662 start: 4.2 read-feedback (timeout 00:07:49) [common]
11443 16:49:20.589913 Listened to connection for namespace 'common' for up to 1s
11444 16:49:21.590637 Finalising connection for namespace 'common'
11445 16:49:21.591308 Disconnecting from shell: Finalise
11446 16:49:21.591748 / #
11447 16:49:21.692696 end: 4.2 read-feedback (duration 00:00:01) [common]
11448 16:49:21.693392 end: 4 finalize (duration 00:00:01) [common]
11449 16:49:21.694003 Cleaning after the job
11450 16:49:21.694544 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/ramdisk
11451 16:49:21.715316 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/kernel
11452 16:49:21.745132 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/dtb
11453 16:49:21.745431 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576304/tftp-deploy-sksb23zw/modules
11454 16:49:21.753024 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576304
11455 16:49:21.806739 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576304
11456 16:49:21.806921 Job finished correctly