Boot log: qemu_arm64-virt-gicv3
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
1 16:27:59.545750 lava-dispatcher, installed at version: 2023.01
2 16:27:59.545953 start: 0 validate
3 16:27:59.546062 Start time: 2023-06-03 16:27:59.546056+00:00 (UTC)
4 16:27:59.547133 Validating that http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig/gcc-10/kernel/Image exists
5 16:27:59.946301 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 16:28:00.129787 cmd: ['docker', 'pull', 'kernelci/qemu']
7 16:28:00.129974 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 16:28:00.290007 >> Using default tag: latest
9 16:28:01.497282 >> latest: Pulling from kernelci/qemu
10 16:28:01.536466 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 16:28:01.536691 >> Status: Image is up to date for kernelci/qemu:latest
12 16:28:01.569857 >> docker.io/kernelci/qemu:latest
13 16:28:01.572819 Returned 0 in 1 seconds
14 16:28:01.711857 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 16:28:01.712339 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 16:28:03.638606 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 16:28:03.638905 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 16:28:04.632782 Returned 0 in 2 seconds
19 16:28:04.734069 validate duration: 5.19
21 16:28:04.734622 start: 1 deployimages (timeout 00:03:00) [common]
22 16:28:04.734796 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 16:28:04.735275 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u
24 16:28:04.735527 makedir: /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin
25 16:28:04.735726 makedir: /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/tests
26 16:28:04.735921 makedir: /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/results
27 16:28:04.736124 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-add-keys
28 16:28:04.736390 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-add-sources
29 16:28:04.736631 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-background-process-start
30 16:28:04.736869 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-background-process-stop
31 16:28:04.737101 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-common-functions
32 16:28:04.737327 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-echo-ipv4
33 16:28:04.737558 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-install-packages
34 16:28:04.737801 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-installed-packages
35 16:28:04.738031 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-os-build
36 16:28:04.738261 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-probe-channel
37 16:28:04.738491 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-probe-ip
38 16:28:04.738718 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-target-ip
39 16:28:04.738948 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-target-mac
40 16:28:04.739178 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-target-storage
41 16:28:04.739414 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-test-case
42 16:28:04.739640 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-test-event
43 16:28:04.739869 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-test-feedback
44 16:28:04.740099 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-test-raise
45 16:28:04.740331 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-test-reference
46 16:28:04.740559 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-test-runner
47 16:28:04.740783 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-test-set
48 16:28:04.741006 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-test-shell
49 16:28:04.741240 Updating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-install-packages (oe)
50 16:28:04.741536 Updating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/bin/lava-installed-packages (oe)
51 16:28:04.741793 Creating /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/environment
52 16:28:04.741990 LAVA metadata
53 16:28:04.742132 - LAVA_JOB_ID=556488
54 16:28:04.742259 - LAVA_DISPATCHER_IP=172.27.0.2
55 16:28:04.742454 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 16:28:04.742588 skipped lava-vland-overlay
57 16:28:04.742734 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 16:28:04.742893 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 16:28:04.743020 skipped lava-multinode-overlay
60 16:28:04.743161 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 16:28:04.743317 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 16:28:04.743469 Loading test definitions
63 16:28:04.743650 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 16:28:04.743797 Using /lava-556488 at stage 0
65 16:28:04.744381 uuid=556488_1.1.3.1 testdef=None
66 16:28:04.744560 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 16:28:04.744718 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 16:28:04.745587 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 16:28:04.746059 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 16:28:04.747130 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 16:28:04.747607 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 16:28:04.748632 runner path: /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/0/tests/0_timesync-off test_uuid 556488_1.1.3.1
75 16:28:04.748917 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 16:28:04.749381 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 16:28:04.749518 Using /lava-556488 at stage 0
79 16:28:04.749723 Fetching tests from https://github.com/kernelci/test-definitions.git
80 16:28:04.749875 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/0/tests/1_kselftest-arm64_qemu'
81 16:28:08.220725 Running '/usr/bin/git checkout kernelci.org
82 16:28:08.354742 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 16:28:08.355827 uuid=556488_1.1.3.5 testdef=None
84 16:28:08.356066 end: 1.1.3.5 git-repo-action (duration 00:00:04) [common]
86 16:28:08.356542 start: 1.1.3.6 test-overlay (timeout 00:02:56) [common]
87 16:28:08.358099 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 16:28:08.358577 start: 1.1.3.7 test-install-overlay (timeout 00:02:56) [common]
90 16:28:08.360673 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 16:28:08.361173 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:56) [common]
93 16:28:08.363233 runner path: /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/0/tests/1_kselftest-arm64_qemu test_uuid 556488_1.1.3.5
94 16:28:08.363409 BOARD='qemu_arm64-virt-gicv3'
95 16:28:08.363534 BRANCH='cip-gitlab'
96 16:28:08.363651 SKIPFILE='/dev/null'
97 16:28:08.363767 SKIP_INSTALL='True'
98 16:28:08.363883 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig/gcc-10/kselftest.tar.xz'
99 16:28:08.364001 TST_CASENAME=''
100 16:28:08.364117 TST_CMDFILES='arm64'
101 16:28:08.364380 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 16:28:08.364830 Creating lava-test-runner.conf files
104 16:28:08.364954 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/556488/lava-overlay-gh92su_u/lava-556488/0 for stage 0
105 16:28:08.365127 - 0_timesync-off
106 16:28:08.365262 - 1_kselftest-arm64_qemu
107 16:28:08.365440 end: 1.1.3 test-definition (duration 00:00:04) [common]
108 16:28:08.365604 start: 1.1.4 compress-overlay (timeout 00:02:56) [common]
109 16:28:17.048076 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 16:28:17.048272 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:48) [common]
111 16:28:17.048388 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 16:28:17.048515 end: 1.1 lava-overlay (duration 00:00:12) [common]
113 16:28:17.048615 start: 1.2 apply-overlay-guest (timeout 00:02:48) [common]
114 16:28:17.048700 Overlay: /var/lib/lava/dispatcher/tmp/556488/compress-overlay-uxn2fv9r/overlay-1.1.4.tar.gz
115 16:28:32.060797 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 16:28:32.061642 start: 1.3 deploy-device-env (timeout 00:02:33) [common]
118 16:28:32.061837 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 16:28:32.062007 start: 1.4 download-retry (timeout 00:02:33) [common]
120 16:28:32.062247 start: 1.4.1 http-download (timeout 00:02:33) [common]
121 16:28:32.062592 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig/gcc-10/kernel/Image
122 16:28:32.062737 saving as /var/lib/lava/dispatcher/tmp/556488/deployimages-35vl0guj/kernel/Image
123 16:28:32.062919 total size: 37290496 (35MB)
124 16:28:32.063111 No compression specified
125 16:28:32.428799 progress 0% (0MB)
126 16:28:33.519427 progress 5% (1MB)
127 16:28:33.701485 progress 10% (3MB)
128 16:28:33.720013 progress 15% (5MB)
129 16:28:33.916305 progress 20% (7MB)
130 16:28:34.093906 progress 25% (8MB)
131 16:28:34.295145 progress 30% (10MB)
132 16:28:34.478006 progress 35% (12MB)
133 16:28:34.838425 progress 40% (14MB)
134 16:28:34.853690 progress 45% (16MB)
135 16:28:35.029314 progress 50% (17MB)
136 16:28:35.235326 progress 55% (19MB)
137 16:28:35.409367 progress 60% (21MB)
138 16:28:35.750862 progress 65% (23MB)
139 16:28:35.938075 progress 70% (24MB)
140 16:28:36.123239 progress 75% (26MB)
141 16:28:36.319566 progress 80% (28MB)
142 16:28:36.504484 progress 85% (30MB)
143 16:28:36.844402 progress 90% (32MB)
144 16:28:37.029893 progress 95% (33MB)
145 16:28:37.214451 progress 100% (35MB)
146 16:28:37.214715 35MB downloaded in 5.15s (6.90MB/s)
147 16:28:37.214938 end: 1.4.1 http-download (duration 00:00:05) [common]
149 16:28:37.215314 end: 1.4 download-retry (duration 00:00:05) [common]
150 16:28:37.215435 start: 1.5 download-retry (timeout 00:02:28) [common]
151 16:28:37.215554 start: 1.5.1 http-download (timeout 00:02:28) [common]
152 16:28:37.215736 Not decompressing ramdisk as can be used compressed.
153 16:28:37.215863 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 16:28:37.215966 saving as /var/lib/lava/dispatcher/tmp/556488/deployimages-35vl0guj/ramdisk/rootfs.cpio.gz
155 16:28:37.216059 total size: 88976554 (84MB)
156 16:28:37.216148 No compression specified
157 16:28:37.399426 progress 0% (0MB)
158 16:28:37.948744 progress 5% (4MB)
159 16:28:38.505640 progress 10% (8MB)
160 16:28:39.227480 progress 15% (12MB)
161 16:28:39.949012 progress 20% (17MB)
162 16:28:40.500042 progress 25% (21MB)
163 16:28:41.062933 progress 30% (25MB)
164 16:28:41.771983 progress 35% (29MB)
165 16:28:42.321296 progress 40% (33MB)
166 16:28:42.870332 progress 45% (38MB)
167 16:28:43.471894 progress 50% (42MB)
168 16:28:44.137373 progress 55% (46MB)
169 16:28:44.686594 progress 60% (50MB)
170 16:28:45.235744 progress 65% (55MB)
171 16:28:45.793026 progress 70% (59MB)
172 16:28:46.499988 progress 75% (63MB)
173 16:28:47.050828 progress 80% (67MB)
174 16:28:47.599891 progress 85% (72MB)
175 16:28:48.153867 progress 90% (76MB)
176 16:28:48.861547 progress 95% (80MB)
177 16:28:49.410708 progress 100% (84MB)
178 16:28:49.411109 84MB downloaded in 12.20s (6.96MB/s)
179 16:28:49.411382 end: 1.5.1 http-download (duration 00:00:12) [common]
181 16:28:49.411892 end: 1.5 download-retry (duration 00:00:12) [common]
182 16:28:49.412061 end: 1 deployimages (duration 00:00:45) [common]
183 16:28:49.412228 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 16:28:49.412391 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 16:28:49.412555 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 16:28:49.412926 Extending command line for qcow2 test overlay
187 16:28:49.413562 Pulling docker image
188 16:28:49.413745 cmd: ['docker', 'pull', 'kernelci/qemu']
189 16:28:49.413882 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 16:28:49.582796 >> Using default tag: latest
191 16:28:50.742178 >> latest: Pulling from kernelci/qemu
192 16:28:50.774157 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 16:28:50.774478 >> Status: Image is up to date for kernelci/qemu:latest
194 16:28:50.807515 >> docker.io/kernelci/qemu:latest
195 16:28:50.810894 Returned 0 in 1 seconds
196 16:28:50.950220 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-556488-2.1.1-eyki0152z4 --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/556488/deployimages-35vl0guj/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/556488/deployimages-35vl0guj/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/556488/apply-overlay-guest-__lj33a9/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 16:28:51.085823 started a shell command
198 16:28:51.086358 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 16:28:51.086507 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 16:28:51.086641 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 16:28:51.086778 Setting prompt string to ['Linux version [0-9]']
202 16:28:51.086880 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 16:28:57.287133 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 16:28:57.287747 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605303-arm64-gcc-10-defconfig-s7qmg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:16:15 UTC 2023
205 16:28:57.287989 [ 0.000000] random: crng init done
206 16:28:57.288234 [ 0.000000] Machine model: linux,dummy-virt
207 16:28:57.288391 [ 0.000000] efi: UEFI not found.
208 16:28:57.288524 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
209 16:28:57.288654 [ 0.000000] printk: bootconsole [pl11] enabled
210 16:28:57.289061 start: 2.2.1 login-action (timeout 00:04:52) [common]
211 16:28:57.289230 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
212 16:28:57.289413 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
213 16:28:57.289576 Using line separator: #'\n'#
214 16:28:57.289725 No login prompt set.
215 16:28:57.289868 Parsing kernel messages
216 16:28:57.289996 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
217 16:28:57.290243 [login-action] Waiting for messages, (timeout 00:04:52)
218 16:28:57.291958 [ 0.000000] NUMA: No NUMA configuration found
219 16:28:57.292200 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 16:28:57.292832 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf1a00-0x7fdf3fff]
221 16:28:57.294919 [ 0.000000] Zone ranges:
222 16:28:57.295672 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 16:28:57.295787 [ 0.000000] DMA32 empty
224 16:28:57.295902 [ 0.000000] Normal empty
225 16:28:57.296015 [ 0.000000] Movable zone start for each node
226 16:28:57.296125 [ 0.000000] Early memory node ranges
227 16:28:57.296419 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 16:28:57.296716 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 16:28:57.311371 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 16:28:57.312521 [ 0.000000] psci: probing for conduit method from DT.
231 16:28:57.312855 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 16:28:57.312969 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 16:28:57.313078 [ 0.000000] psci: Trusted OS migration not required
234 16:28:57.313422 [ 0.000000] psci: SMC Calling Convention v1.0
235 16:28:57.315542 [ 0.000000] percpu: Embedded 20 pages/cpu s44840 r8192 d28888 u81920
236 16:28:57.316334 [ 0.000000] pcpu-alloc: s44840 r8192 d28888 u81920 alloc=20*4096
237 16:28:57.316456 [ 0.000000] pcpu-alloc: [0] 0
238 16:28:57.317860 [ 0.000000] Detected PIPT I-cache on CPU0
239 16:28:57.323562 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 16:28:57.324241 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 16:28:57.324436 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 16:28:57.324633 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 16:28:57.324801 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 16:28:57.325189 [ 0.000000] CPU features: detected: Spectre-v4
245 16:28:57.329735 [ 0.000000] alternatives: applying boot alternatives
246 16:28:57.333552 [ 0.000000] Fallback order for Node 0: 0
247 16:28:57.333685 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 16:28:57.333808 [ 0.000000] Policy zone: DMA
249 16:28:57.334490 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 16:28:57.337766 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 16:28:57.341250 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 16:28:57.341638 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 16:28:57.342322 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 16:28:57.351607 <6>[ 0.000000] Memory: 870732K/1048576K available (16128K kernel code, 3712K rwdata, 8856K rodata, 7552K init, 609K bss, 145076K reserved, 32768K cma-reserved)
255 16:28:57.357493 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 16:28:57.364475 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 16:28:57.364660 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 16:28:57.364830 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 16:28:57.364989 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 16:28:57.365153 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 16:28:57.365341 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 16:28:57.365494 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 16:28:57.366527 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 16:28:57.373205 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 16:28:57.373553 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 16:28:57.375235 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 16:28:57.375885 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 16:28:57.376126 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 16:28:57.380501 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 16:28:57.381552 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @42830000 (indirect, esz 8, psz 64K, shr 1)
271 16:28:57.382097 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @42840000 (flat, esz 8, psz 64K, shr 1)
272 16:28:57.382617 <6>[ 0.000000] GICv3: using LPI property table @0x0000000042850000
273 16:28:57.383380 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000042860000
274 16:28:57.384724 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 16:28:57.392974 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 16:28:57.393262 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 16:28:57.394116 <6>[ 0.000077] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 16:28:57.411269 <6>[ 0.014806] Console: colour dummy device 80x25
279 16:28:57.415443 <6>[ 0.020900] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 16:28:57.415739 <6>[ 0.021834] pid_max: default: 32768 minimum: 301
281 16:28:57.418349 <6>[ 0.024487] LSM: Security Framework initializing
282 16:28:57.424178 <6>[ 0.030266] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 16:28:57.424413 <6>[ 0.030556] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 16:28:57.456458 <4>[ 0.062814] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 16:28:57.462870 <6>[ 0.068990] cblist_init_generic: Setting adjustable number of callback queues.
286 16:28:57.463041 <6>[ 0.069334] cblist_init_generic: Setting shift to 0 and lim to 1.
287 16:28:57.463674 <6>[ 0.069888] cblist_init_generic: Setting shift to 0 and lim to 1.
288 16:28:57.465428 <6>[ 0.071611] rcu: Hierarchical SRCU implementation.
289 16:28:57.465552 <6>[ 0.071823] rcu: Max phase no-delay instances is 1000.
290 16:28:57.471970 <6>[ 0.078098] Platform MSI: its@8080000 domain created
291 16:28:57.472682 <6>[ 0.078727] PCI/MSI: /intc@8000000/its@8080000 domain created
292 16:28:57.473026 <6>[ 0.079329] fsl-mc MSI: its@8080000 domain created
293 16:28:57.476070 <6>[ 0.082459] EFI services will not be available.
294 16:28:57.477308 <6>[ 0.083509] smp: Bringing up secondary CPUs ...
295 16:28:57.477417 <6>[ 0.083717] smp: Brought up 1 node, 1 CPU
296 16:28:57.477526 <6>[ 0.083861] SMP: Total of 1 processors activated.
297 16:28:57.478103 <6>[ 0.084324] CPU features: detected: Branch Target Identification
298 16:28:57.478228 <6>[ 0.084553] CPU features: detected: 32-bit EL0 Support
299 16:28:57.478331 <6>[ 0.084699] CPU features: detected: 32-bit EL1 Support
300 16:28:57.478664 <6>[ 0.084904] CPU features: detected: ARMv8.4 Translation Table Level
301 16:28:57.479017 <6>[ 0.085210] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 16:28:57.479344 <6>[ 0.085532] CPU features: detected: Common not Private translations
303 16:28:57.479454 <6>[ 0.085735] CPU features: detected: CRC32 instructions
304 16:28:57.479548 <6>[ 0.085850] CPU features: detected: E0PD
305 16:28:57.479875 <6>[ 0.086080] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 16:28:57.479984 <6>[ 0.086297] CPU features: detected: RCpc load-acquire (LDAPR)
307 16:28:57.480085 <6>[ 0.086444] CPU features: detected: LSE atomic instructions
308 16:28:57.480418 <6>[ 0.086638] CPU features: detected: Privileged Access Never
309 16:28:57.480535 <6>[ 0.086844] CPU features: detected: RAS Extension Support
310 16:28:57.480639 <6>[ 0.086996] CPU features: detected: Random Number Generator
311 16:28:57.480964 <6>[ 0.087190] CPU features: detected: Speculation barrier (SB)
312 16:28:57.481056 <6>[ 0.087364] CPU features: detected: Stage-2 Force Write-Back
313 16:28:57.481219 <6>[ 0.087507] CPU features: detected: TLB range maintenance instructions
314 16:28:57.481565 <6>[ 0.087786] CPU features: detected: Scalable Matrix Extension
315 16:28:57.481667 <6>[ 0.087984] CPU features: detected: FA64
316 16:28:57.481770 <6>[ 0.088075] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 16:28:57.482114 <6>[ 0.088296] CPU features: detected: Scalable Vector Extension
318 16:28:57.494287 <6>[ 0.097875] SVE: maximum available vector length 256 bytes per vector
319 16:28:57.494745 <6>[ 0.100998] SVE: default vector length 64 bytes per vector
320 16:28:57.496738 <6>[ 0.102844] SME: minimum available vector length 16 bytes per vector
321 16:28:57.496910 <6>[ 0.103025] SME: maximum available vector length 256 bytes per vector
322 16:28:57.497155 <6>[ 0.103181] SME: default vector length 32 bytes per vector
323 16:28:57.497322 <6>[ 0.103572] CPU: All CPU(s) started at EL1
324 16:28:57.497556 <6>[ 0.103905] alternatives: applying system-wide alternatives
325 16:28:57.549955 <6>[ 0.156172] devtmpfs: initialized
326 16:28:57.569913 <6>[ 0.175814] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 16:28:57.570399 <6>[ 0.176559] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 16:28:57.575952 <6>[ 0.182361] pinctrl core: initialized pinctrl subsystem
329 16:28:57.586821 <6>[ 0.193242] DMI not present or invalid.
330 16:28:57.596149 <6>[ 0.202303] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 16:28:57.607718 <6>[ 0.213661] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 16:28:57.608191 <6>[ 0.214425] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 16:28:57.608696 <6>[ 0.214987] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 16:28:57.609151 <6>[ 0.215433] audit: initializing netlink subsys (disabled)
335 16:28:57.613731 <5>[ 0.219798] audit: type=2000 audit(0.184:1): state=initialized audit_enabled=0 res=1
336 16:28:57.617040 <6>[ 0.223108] thermal_sys: Registered thermal governor 'step_wise'
337 16:28:57.617447 <6>[ 0.223176] thermal_sys: Registered thermal governor 'power_allocator'
338 16:28:57.617574 <6>[ 0.223741] cpuidle: using governor menu
339 16:28:57.619268 <6>[ 0.225446] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
340 16:28:57.619752 <6>[ 0.226114] ASID allocator initialised with 65536 entries
341 16:28:57.625345 <6>[ 0.231760] Serial: AMBA PL011 UART driver
342 16:28:57.672201 <6>[ 0.278331] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
343 16:28:57.673769 <6>[ 0.280050] printk: console [ttyAMA0] enabled
344 16:28:57.674119 <6>[ 0.280050] printk: console [ttyAMA0] enabled
345 16:28:57.674238 <6>[ 0.280563] printk: bootconsole [pl11] disabled
346 16:28:57.674347 <6>[ 0.280563] printk: bootconsole [pl11] disabled
347 16:28:57.684624 <6>[ 0.291073] KASLR enabled
348 16:28:57.715603 <6>[ 0.321642] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
349 16:28:57.716148 <6>[ 0.321867] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
350 16:28:57.716328 <6>[ 0.322069] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
351 16:28:57.716471 <6>[ 0.322212] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
352 16:28:57.716603 <6>[ 0.322350] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
353 16:28:57.716739 <6>[ 0.322500] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
354 16:28:57.716895 <6>[ 0.322661] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
355 16:28:57.717030 <6>[ 0.322837] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
356 16:28:57.727857 <6>[ 0.334195] ACPI: Interpreter disabled.
357 16:28:57.735998 <6>[ 0.342358] iommu: Default domain type: Translated
358 16:28:57.736450 <6>[ 0.342536] iommu: DMA domain TLB invalidation policy: strict mode
359 16:28:57.737858 <5>[ 0.344224] SCSI subsystem initialized
360 16:28:57.738885 <7>[ 0.345075] libata version 3.00 loaded.
361 16:28:57.740333 <6>[ 0.346491] usbcore: registered new interface driver usbfs
362 16:28:57.740577 <6>[ 0.346892] usbcore: registered new interface driver hub
363 16:28:57.741031 <6>[ 0.347248] usbcore: registered new device driver usb
364 16:28:57.744078 <6>[ 0.350174] pps_core: LinuxPPS API ver. 1 registered
365 16:28:57.744255 <6>[ 0.350333] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
366 16:28:57.744466 <6>[ 0.350678] PTP clock support registered
367 16:28:57.744913 <6>[ 0.351272] EDAC MC: Ver: 3.0.0
368 16:28:57.750124 <6>[ 0.356517] FPGA manager framework
369 16:28:57.751167 <6>[ 0.357295] Advanced Linux Sound Architecture Driver Initialized.
370 16:28:57.759928 <6>[ 0.366319] vgaarb: loaded
371 16:28:57.763663 <6>[ 0.369780] clocksource: Switched to clocksource arch_sys_counter
372 16:28:57.766032 <5>[ 0.372443] VFS: Disk quotas dquot_6.6.0
373 16:28:57.766458 <6>[ 0.372776] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
374 16:28:57.768506 <6>[ 0.374924] pnp: PnP ACPI: disabled
375 16:28:57.786439 <6>[ 0.392466] NET: Registered PF_INET protocol family
376 16:28:57.788625 <6>[ 0.394672] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
377 16:28:57.793464 <6>[ 0.399450] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
378 16:28:57.793995 <6>[ 0.399759] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
379 16:28:57.794192 <6>[ 0.400007] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
380 16:28:57.794352 <6>[ 0.400471] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
381 16:28:57.794777 <6>[ 0.401051] TCP: Hash tables configured (established 8192 bind 8192)
382 16:28:57.796498 <6>[ 0.402594] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
383 16:28:57.796742 <6>[ 0.403014] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
384 16:28:57.798124 <6>[ 0.404260] NET: Registered PF_UNIX/PF_LOCAL protocol family
385 16:28:57.800442 <6>[ 0.406534] RPC: Registered named UNIX socket transport module.
386 16:28:57.800645 <6>[ 0.406756] RPC: Registered udp transport module.
387 16:28:57.800873 <6>[ 0.406875] RPC: Registered tcp transport module.
388 16:28:57.801029 <6>[ 0.406991] RPC: Registered tcp NFSv4.1 backchannel transport module.
389 16:28:57.801156 <6>[ 0.407232] PCI: CLS 0 bytes, default 64
390 16:28:57.805403 <6>[ 0.411771] Unpacking initramfs...
391 16:28:57.815921 <6>[ 0.421994] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
392 16:28:57.816443 <6>[ 0.422830] kvm [1]: HYP mode not available
393 16:28:57.820224 <5>[ 0.426394] Initialise system trusted keyrings
394 16:28:57.824300 <6>[ 0.430434] workingset: timestamp_bits=42 max_order=18 bucket_order=0
395 16:28:57.863553 <6>[ 0.469816] squashfs: version 4.0 (2009/01/31) Phillip Lougher
396 16:28:57.868760 <5>[ 0.474918] NFS: Registering the id_resolver key type
397 16:28:57.868963 <5>[ 0.475360] Key type id_resolver registered
398 16:28:57.869147 <5>[ 0.475527] Key type id_legacy registered
399 16:28:57.869767 <6>[ 0.476089] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
400 16:28:57.870224 <6>[ 0.476363] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
401 16:28:57.875498 <6>[ 0.481676] 9p: Installing v9fs 9p2000 file system support
402 16:28:57.940639 <5>[ 0.546849] Key type asymmetric registered
403 16:28:57.941138 <5>[ 0.547056] Asymmetric key parser 'x509' registered
404 16:28:57.941274 <6>[ 0.547455] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
405 16:28:57.941414 <6>[ 0.547807] io scheduler mq-deadline registered
406 16:28:57.941732 <6>[ 0.548033] io scheduler kyber registered
407 16:28:58.004043 <6>[ 0.610005] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
408 16:28:58.014419 <6>[ 0.620547] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
409 16:28:58.019358 <6>[ 0.621481] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
410 16:28:58.020051 <6>[ 0.626249] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
411 16:28:58.020414 <6>[ 0.626588] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
412 16:28:58.021108 <4>[ 0.627294] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
413 16:28:58.022199 <6>[ 0.628152] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
414 16:28:58.027545 <6>[ 0.633742] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
415 16:28:58.027932 <6>[ 0.634215] pci_bus 0000:00: root bus resource [bus 00-ff]
416 16:28:58.028164 <6>[ 0.634479] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
417 16:28:58.028660 <6>[ 0.634718] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
418 16:28:58.028821 <6>[ 0.634951] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
419 16:28:58.030327 <6>[ 0.636503] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
420 16:28:58.038035 <6>[ 0.644172] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
421 16:28:58.038272 <6>[ 0.644612] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
422 16:28:58.038467 <6>[ 0.644834] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
423 16:28:58.038905 <6>[ 0.645109] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
424 16:28:58.039113 <6>[ 0.645423] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
425 16:28:58.043777 <6>[ 0.649957] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
426 16:28:58.043910 <6>[ 0.650146] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
427 16:28:58.044020 <6>[ 0.650340] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
428 16:28:58.044428 <6>[ 0.650559] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
429 16:28:58.047130 <6>[ 0.653335] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
430 16:28:58.051695 <6>[ 0.657878] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
431 16:28:58.052064 <6>[ 0.658234] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
432 16:28:58.052195 <6>[ 0.658505] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
433 16:28:58.052598 <6>[ 0.658775] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
434 16:28:58.052792 <6>[ 0.658971] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
435 16:28:58.052952 <6>[ 0.659160] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
436 16:28:58.068385 <6>[ 0.674725] EINJ: ACPI disabled.
437 16:28:58.165895 <6>[ 0.771787] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
438 16:28:58.173068 <6>[ 0.779154] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
439 16:28:58.200262 <6>[ 0.806589] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
440 16:28:58.216452 <6>[ 0.822825] SuperH (H)SCI(F) driver initialized
441 16:28:58.218058 <6>[ 0.824190] msm_serial: driver initialized
442 16:28:58.226610 <4>[ 0.832743] cacheinfo: Unable to detect cache hierarchy for CPU 0
443 16:28:58.258984 <6>[ 0.865306] loop: module loaded
444 16:28:58.260248 <6>[ 0.866337] virtio_blk virtio1: 1/0/0 default/read/poll queues
445 16:28:58.280749 <5>[ 0.887015] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
446 16:28:58.306733 <6>[ 0.913099] megasas: 07.719.03.00-rc1
447 16:28:58.321112 <5>[ 0.927153] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
448 16:28:58.322524 <6>[ 0.928630] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
449 16:28:58.322986 <6>[ 0.929295] Intel/Sharp Extended Query Table at 0x0031
450 16:28:58.328067 <6>[ 0.934206] Using buffer write method
451 16:28:58.328537 <7>[ 0.934660] erase region 0: offset=0x0,size=0x40000,blocks=256
452 16:28:58.328736 <5>[ 0.935008] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
453 16:28:58.329510 <6>[ 0.935669] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
454 16:28:58.329717 <6>[ 0.935956] Intel/Sharp Extended Query Table at 0x0031
455 16:28:58.330191 <6>[ 0.936489] Using buffer write method
456 16:28:58.330401 <7>[ 0.936645] erase region 0: offset=0x0,size=0x40000,blocks=256
457 16:28:58.330598 <5>[ 0.936886] Concatenating MTD devices:
458 16:28:58.330823 <5>[ 0.937029] (0): \"0.flash\"
459 16:28:58.330976 <5>[ 0.937118] (1): \"0.flash\"
460 16:28:58.331104 <5>[ 0.937211] into device \"0.flash\"
461 16:29:03.095068 <6>[ 5.701213] Freeing initrd memory: 86888K
462 16:29:03.209456 <6>[ 5.815662] tun: Universal TUN/TAP device driver, 1.6
463 16:29:03.218931 <6>[ 5.825300] thunder_xcv, ver 1.0
464 16:29:03.219412 <6>[ 5.825589] thunder_bgx, ver 1.0
465 16:29:03.219576 <6>[ 5.825781] nicpf, ver 1.0
466 16:29:03.222778 <6>[ 5.828904] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
467 16:29:03.222946 <6>[ 5.829101] hns3: Copyright (c) 2017 Huawei Corporation.
468 16:29:03.223376 <6>[ 5.829582] hclge is initializing
469 16:29:03.223581 <6>[ 5.829814] e1000: Intel(R) PRO/1000 Network Driver
470 16:29:03.223756 <6>[ 5.829964] e1000: Copyright (c) 1999-2006 Intel Corporation.
471 16:29:03.223955 <6>[ 5.830241] e1000e: Intel(R) PRO/1000 Network Driver
472 16:29:03.224155 <6>[ 5.830375] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
473 16:29:03.224336 <6>[ 5.830691] igb: Intel(R) Gigabit Ethernet Network Driver
474 16:29:03.224768 <6>[ 5.830863] igb: Copyright (c) 2007-2014 Intel Corporation.
475 16:29:03.224971 <6>[ 5.831178] igbvf: Intel(R) Gigabit Virtual Function Network Driver
476 16:29:03.225136 <6>[ 5.831350] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
477 16:29:03.225943 <6>[ 5.832349] sky2: driver version 1.30
478 16:29:03.229046 <6>[ 5.835187] VFIO - User Level meta-driver version: 0.3
479 16:29:03.237772 <6>[ 5.843891] usbcore: registered new interface driver usb-storage
480 16:29:03.246312 <6>[ 5.852683] rtc-pl031 9010000.pl031: registered as rtc0
481 16:29:03.247579 <6>[ 5.853423] rtc-pl031 9010000.pl031: setting system clock to 2023-06-03T16:29:03 UTC (1685809743)
482 16:29:03.249443 <6>[ 5.855575] i2c_dev: i2c /dev entries driver
483 16:29:03.265131 <6>[ 5.871233] sdhci: Secure Digital Host Controller Interface driver
484 16:29:03.265308 <6>[ 5.871439] sdhci: Copyright(c) Pierre Ossman
485 16:29:03.267193 <6>[ 5.873345] Synopsys Designware Multimedia Card Interface Driver
486 16:29:03.269709 <6>[ 5.875831] sdhci-pltfm: SDHCI platform and OF driver helper
487 16:29:03.274620 <6>[ 5.880687] ledtrig-cpu: registered to indicate activity on CPUs
488 16:29:03.280117 <6>[ 5.886237] usbcore: registered new interface driver usbhid
489 16:29:03.280287 <6>[ 5.886397] usbhid: USB HID core driver
490 16:29:03.296393 <6>[ 5.902461] NET: Registered PF_PACKET protocol family
491 16:29:03.297374 <6>[ 5.903550] 9pnet: Installing 9P2000 support
492 16:29:03.297729 <5>[ 5.903939] Key type dns_resolver registered
493 16:29:03.298759 <6>[ 5.905153] registered taskstats version 1
494 16:29:03.299307 <5>[ 5.905670] Loading compiled-in X.509 certificates
495 16:29:03.320262 <6>[ 5.926501] input: gpio-keys as /devices/platform/gpio-keys/input/input0
496 16:29:03.327375 <6>[ 5.933701] ALSA device list:
497 16:29:03.327818 <6>[ 5.933882] No soundcards found.
498 16:29:03.330493 <6>[ 5.936613] uart-pl011 9000000.pl011: no DMA platform data
499 16:29:03.384573 <6>[ 5.990785] Freeing unused kernel memory: 7552K
500 16:29:03.385601 <6>[ 5.991710] Run /init as init process
501 16:29:03.385812 <7>[ 5.991859] with arguments:
502 16:29:03.385974 <7>[ 5.991968] /init
503 16:29:03.386101 <7>[ 5.992052] verbose
504 16:29:03.386248 <7>[ 5.992134] with environment:
505 16:29:03.386377 <7>[ 5.992228] HOME=/
506 16:29:03.386557 <7>[ 5.992309] TERM=linux
507 16:29:03.519080 <30>[ 6.124915] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
508 16:29:03.520292 <31>[ 6.126425] systemd[1]: No virtualization found in DMI
509 16:29:03.521245 <31>[ 6.127372] systemd[1]: UML virtualization not found in /proc/cpuinfo.
510 16:29:03.521441 <31>[ 6.127689] systemd[1]: No virtualization found in CPUID
511 16:29:03.521694 <31>[ 6.127970] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
512 16:29:03.522792 <31>[ 6.129006] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
513 16:29:03.523154 <31>[ 6.129366] systemd[1]: Found VM virtualization qemu
514 16:29:03.523726 <30>[ 6.129902] systemd[1]: Detected virtualization qemu.
515 16:29:03.524089 <30>[ 6.130272] systemd[1]: Detected architecture arm64.
516 16:29:03.524435 <31>[ 6.130701] systemd[1]: Detected initialized system, this is not the first boot.
517 16:29:03.528305
518 16:29:03.528652 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
519 16:29:03.528762
520 16:29:03.530468 <30>[ 6.136612] systemd[1]: Set hostname to <debian-bullseye-arm64>.
521 16:29:03.549579 <31>[ 6.155696] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
522 16:29:03.550729 <31>[ 6.156902] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
523 16:29:03.551077 <31>[ 6.157375] systemd[1]: Successfully brought loopback interface up
524 16:29:03.556026 <31>[ 6.162220] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
525 16:29:03.567809 <31>[ 6.173990] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
526 16:29:03.567981 <31>[ 6.174303] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
527 16:29:03.610145 <31>[ 6.216127] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
528 16:29:03.611626 <31>[ 6.217769] systemd[1]: Controller 'cpu' supported: yes
529 16:29:03.611842 <31>[ 6.218027] systemd[1]: Controller 'cpuacct' supported: no
530 16:29:03.612016 <31>[ 6.218201] systemd[1]: Controller 'cpuset' supported: yes
531 16:29:03.612214 <31>[ 6.218363] systemd[1]: Controller 'io' supported: yes
532 16:29:03.612413 <31>[ 6.218507] systemd[1]: Controller 'blkio' supported: no
533 16:29:03.612645 <31>[ 6.218683] systemd[1]: Controller 'memory' supported: yes
534 16:29:03.612794 <31>[ 6.218865] systemd[1]: Controller 'devices' supported: no
535 16:29:03.612996 <31>[ 6.219043] systemd[1]: Controller 'pids' supported: yes
536 16:29:03.613173 <31>[ 6.219249] systemd[1]: Controller 'bpf-firewall' supported: yes
537 16:29:03.613333 <31>[ 6.219448] systemd[1]: Controller 'bpf-devices' supported: yes
538 16:29:03.614527 <31>[ 6.220688] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
539 16:29:03.614746 <31>[ 6.221047] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
540 16:29:03.615678 <31>[ 6.221850] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
541 16:29:03.622972 <31>[ 6.229023] systemd[1]: Enabling (yes) showing of status (commandline).
542 16:29:03.630564 <31>[ 6.236658] systemd[1]: Successfully forked off '(sd-executor)' as PID 94.
543 16:29:03.639750 <31>[ 6.246111] systemd[94]: Successfully forked off '(direxec)' as PID 95.
544 16:29:03.641985 <31>[ 6.248014] systemd[94]: Successfully forked off '(direxec)' as PID 96.
545 16:29:03.648029 <31>[ 6.254135] systemd[94]: Successfully forked off '(direxec)' as PID 97.
546 16:29:03.649844 <31>[ 6.255974] systemd[94]: Successfully forked off '(direxec)' as PID 98.
547 16:29:03.668282 <31>[ 6.274317] systemd[94]: Successfully forked off '(direxec)' as PID 99.
548 16:29:03.813992 <31>[ 6.420142] systemd-fstab-generator[96]: Parsing /etc/fstab...
549 16:29:03.820571 <31>[ 6.426651] systemd-bless-boot-generator[95]: Skipping generator, not an EFI boot.
550 16:29:03.829873 <31>[ 6.435834] systemd-fstab-generator[96]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
551 16:29:03.835185 <31>[ 6.441256] systemd-getty-generator[97]: Automatically adding serial getty for /dev/ttyAMA0.
552 16:29:03.836704 <31>[ 6.442825] systemd-getty-generator[97]: SELinux enabled state cached to: disabled
553 16:29:03.840844 <31>[ 6.446986] systemd-fstab-generator[96]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
554 16:29:03.850234 <31>[ 6.456390] systemd-fstab-generator[96]: SELinux enabled state cached to: disabled
555 16:29:03.852512 <31>[ 6.458642] systemd[94]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
556 16:29:03.853320 <31>[ 6.459294] systemd[94]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
557 16:29:03.858841 <31>[ 6.464799] systemd[94]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
558 16:29:03.859143 <31>[ 6.465194] systemd[94]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
559 16:29:03.859911 <31>[ 6.466056] systemd[94]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
560 16:29:03.862456 <31>[ 6.468788] systemd[1]: (sd-executor) succeeded.
561 16:29:03.864655 <31>[ 6.470745] systemd[1]: Looking for unit files in (higher priority first):
562 16:29:03.864856 <31>[ 6.471027] systemd[1]: /etc/systemd/system.control
563 16:29:03.865093 <31>[ 6.471186] systemd[1]: /run/systemd/system.control
564 16:29:03.865261 <31>[ 6.471332] systemd[1]: /run/systemd/transient
565 16:29:03.865416 <31>[ 6.471481] systemd[1]: /run/systemd/generator.early
566 16:29:03.865600 <31>[ 6.471639] systemd[1]: /etc/systemd/system
567 16:29:03.865757 <31>[ 6.471768] systemd[1]: /etc/systemd/system.attached
568 16:29:03.865904 <31>[ 6.471932] systemd[1]: /run/systemd/system
569 16:29:03.866084 <31>[ 6.472068] systemd[1]: /run/systemd/system.attached
570 16:29:03.866232 <31>[ 6.472216] systemd[1]: /run/systemd/generator
571 16:29:03.866381 <31>[ 6.472347] systemd[1]: /usr/local/lib/systemd/system
572 16:29:03.866562 <31>[ 6.472504] systemd[1]: /lib/systemd/system
573 16:29:03.866700 <31>[ 6.472646] systemd[1]: /usr/lib/systemd/system
574 16:29:03.866844 <31>[ 6.472799] systemd[1]: /run/systemd/generator.late
575 16:29:03.902187 <31>[ 6.508224] systemd[1]: Modification times have changed, need to update cache.
576 16:29:03.904204 <31>[ 6.510190] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
577 16:29:03.905156 <31>[ 6.511302] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
578 16:29:03.905977 <31>[ 6.512140] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
579 16:29:03.906887 <31>[ 6.513095] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
580 16:29:03.908003 <31>[ 6.514270] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
581 16:29:03.908365 <31>[ 6.514534] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
582 16:29:03.908744 <31>[ 6.514876] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
583 16:29:03.909252 <31>[ 6.515280] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
584 16:29:03.909471 <31>[ 6.515662] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
585 16:29:03.909710 <31>[ 6.516001] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
586 16:29:03.910161 <31>[ 6.516392] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
587 16:29:03.910973 <31>[ 6.517044] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
588 16:29:03.911184 <31>[ 6.517353] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
589 16:29:03.911913 <31>[ 6.518065] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
590 16:29:03.912669 <31>[ 6.518723] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
591 16:29:03.912857 <31>[ 6.519006] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
592 16:29:03.913100 <31>[ 6.519322] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
593 16:29:03.913623 <31>[ 6.519648] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
594 16:29:03.913795 <31>[ 6.519924] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
595 16:29:03.914266 <31>[ 6.520486] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
596 16:29:03.914782 <31>[ 6.520801] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
597 16:29:03.915249 <31>[ 6.521391] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
598 16:29:03.915701 <31>[ 6.521938] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
599 16:29:03.916169 <31>[ 6.522231] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
600 16:29:03.916296 <31>[ 6.522565] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
601 16:29:03.916648 <31>[ 6.522950] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
602 16:29:03.917016 <31>[ 6.523242] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
603 16:29:03.917911 <31>[ 6.524038] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
604 16:29:03.918463 <31>[ 6.524660] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
605 16:29:03.919087 <31>[ 6.525053] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
606 16:29:03.919247 <31>[ 6.525359] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
607 16:29:03.920088 <31>[ 6.526053] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
608 16:29:03.920316 <31>[ 6.526397] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
609 16:29:03.920495 <31>[ 6.526694] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
610 16:29:03.921005 <31>[ 6.526975] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
611 16:29:03.921206 <31>[ 6.527273] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
612 16:29:03.921392 <31>[ 6.527528] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
613 16:29:03.921584 <31>[ 6.527835] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
614 16:29:03.922087 <31>[ 6.528158] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
615 16:29:03.922210 <31>[ 6.528469] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
616 16:29:03.922563 <31>[ 6.528813] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
617 16:29:03.922913 <31>[ 6.529172] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
618 16:29:03.923364 <31>[ 6.529465] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
619 16:29:03.923877 <31>[ 6.530128] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
620 16:29:03.924379 <31>[ 6.530420] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
621 16:29:03.924881 <31>[ 6.530987] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
622 16:29:03.925088 <31>[ 6.531339] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
623 16:29:03.925901 <31>[ 6.532005] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
624 16:29:03.926140 <31>[ 6.532366] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
625 16:29:03.926593 <31>[ 6.532813] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
626 16:29:03.926829 <31>[ 6.533106] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
627 16:29:03.927323 <31>[ 6.533429] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
628 16:29:03.928338 <31>[ 6.534456] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
629 16:29:03.928546 <31>[ 6.534762] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
630 16:29:03.929007 <31>[ 6.535056] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
631 16:29:03.929181 <31>[ 6.535355] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
632 16:29:03.929935 <31>[ 6.535938] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
633 16:29:03.930144 <31>[ 6.536245] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
634 16:29:03.930315 <31>[ 6.536542] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
635 16:29:03.931113 <31>[ 6.537167] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
636 16:29:03.931285 <31>[ 6.537447] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
637 16:29:03.931979 <31>[ 6.538052] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
638 16:29:03.932155 <31>[ 6.538349] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
639 16:29:03.932696 <31>[ 6.538648] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
640 16:29:03.932915 <31>[ 6.538984] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
641 16:29:03.933090 <31>[ 6.539294] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
642 16:29:03.933277 <31>[ 6.539538] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
643 16:29:03.933468 <31>[ 6.539809] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
644 16:29:03.933715 <31>[ 6.540044] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
645 16:29:03.934252 <31>[ 6.540273] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
646 16:29:03.934451 <31>[ 6.540620] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
647 16:29:03.934672 <31>[ 6.540921] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
648 16:29:03.935034 <31>[ 6.541280] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
649 16:29:03.935582 <31>[ 6.541882] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
650 16:29:03.936333 <31>[ 6.542431] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
651 16:29:03.936542 <31>[ 6.542675] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
652 16:29:03.936734 <31>[ 6.542938] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
653 16:29:03.937435 <31>[ 6.543477] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
654 16:29:03.937584 <31>[ 6.543752] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
655 16:29:03.937777 <31>[ 6.543988] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
656 16:29:03.937948 <31>[ 6.544245] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
657 16:29:03.938641 <31>[ 6.544632] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
658 16:29:03.939091 <31>[ 6.545274] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
659 16:29:03.939814 <31>[ 6.545941] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
660 16:29:03.939995 <31>[ 6.546219] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
661 16:29:03.940508 <31>[ 6.546520] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
662 16:29:03.940734 <31>[ 6.546811] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
663 16:29:03.940920 <31>[ 6.547103] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
664 16:29:03.941453 <31>[ 6.547380] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
665 16:29:03.941672 <31>[ 6.547706] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
666 16:29:03.941866 <31>[ 6.548011] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
667 16:29:03.942055 <31>[ 6.548307] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
668 16:29:03.942601 <31>[ 6.548628] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
669 16:29:03.942810 <31>[ 6.548946] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
670 16:29:03.943012 <31>[ 6.549257] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
671 16:29:03.943465 <31>[ 6.549699] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
672 16:29:03.943664 <31>[ 6.549951] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
673 16:29:03.944093 <31>[ 6.550354] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
674 16:29:03.944519 <31>[ 6.550634] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
675 16:29:03.944666 <31>[ 6.550889] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
676 16:29:03.945359 <31>[ 6.551531] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
677 16:29:03.945780 <31>[ 6.551857] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
678 16:29:03.945910 <31>[ 6.552110] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
679 16:29:03.946320 <31>[ 6.552369] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
680 16:29:03.946464 <31>[ 6.552660] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
681 16:29:03.946604 <31>[ 6.552917] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
682 16:29:03.947023 <31>[ 6.553166] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
683 16:29:03.947500 <31>[ 6.553679] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
684 16:29:03.948045 <31>[ 6.554077] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
685 16:29:03.948251 <31>[ 6.554391] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
686 16:29:03.948480 <31>[ 6.554690] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
687 16:29:03.949091 <31>[ 6.555045] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
688 16:29:03.949289 <31>[ 6.555391] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
689 16:29:03.949481 <31>[ 6.555666] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
690 16:29:03.950075 <31>[ 6.555999] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
691 16:29:03.950251 <31>[ 6.556341] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
692 16:29:03.950432 <31>[ 6.556632] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
693 16:29:03.950962 <31>[ 6.556973] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
694 16:29:03.951169 <31>[ 6.557343] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
695 16:29:03.951967 <31>[ 6.557970] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
696 16:29:03.952160 <31>[ 6.558340] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
697 16:29:03.952652 <31>[ 6.558648] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
698 16:29:03.952861 <31>[ 6.558950] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
699 16:29:03.953090 <31>[ 6.559259] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
700 16:29:03.953327 <31>[ 6.559579] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
701 16:29:03.953630 <31>[ 6.559913] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
702 16:29:03.954242 <31>[ 6.560227] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
703 16:29:03.954462 <31>[ 6.560563] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
704 16:29:03.954701 <31>[ 6.560931] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
705 16:29:03.955251 <31>[ 6.561248] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
706 16:29:03.955804 <31>[ 6.561873] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
707 16:29:03.956006 <31>[ 6.562206] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
708 16:29:03.956794 <31>[ 6.562911] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
709 16:29:03.957368 <31>[ 6.563307] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
710 16:29:03.957589 <31>[ 6.563666] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
711 16:29:03.957820 <31>[ 6.564008] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
712 16:29:03.958022 <31>[ 6.564297] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
713 16:29:03.958627 <31>[ 6.564574] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
714 16:29:03.958842 <31>[ 6.564872] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
715 16:29:03.959013 <31>[ 6.565216] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
716 16:29:03.959478 <31>[ 6.565671] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
717 16:29:03.960015 <31>[ 6.566056] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
718 16:29:03.960189 <31>[ 6.566388] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
719 16:29:03.960648 <31>[ 6.566830] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
720 16:29:03.961149 <31>[ 6.567288] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
721 16:29:03.961370 <31>[ 6.567573] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
722 16:29:03.961607 <31>[ 6.567830] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
723 16:29:03.962125 <31>[ 6.568157] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
724 16:29:03.962308 <31>[ 6.568481] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
725 16:29:03.962573 <31>[ 6.568786] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
726 16:29:03.963116 <31>[ 6.569121] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
727 16:29:04.367440 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
728 16:29:04.372070 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
729 16:29:04.375159 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
730 16:29:04.378400 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
731 16:29:04.381982 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
732 16:29:04.383935 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
733 16:29:04.386003 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
734 16:29:04.386996 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
735 16:29:04.388025 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
736 16:29:04.388562 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
737 16:29:04.389465 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
738 16:29:04.393107 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
739 16:29:04.397038 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
740 16:29:04.399708 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
741 16:29:04.401755 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
742 16:29:04.404490 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
743 16:29:04.407035 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
744 16:29:04.409370 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
745 16:29:04.437074 Mounting [0;1;39mHuge Pages File System[0m...
746 16:29:04.456591 Mounting [0;1;39mPOSIX Message Queue File System[0m...
747 16:29:04.492699 Mounting [0;1;39mKernel Debug File System[0m...
748 16:29:04.549204 Starting [0;1;39mLoad Kernel Module configfs[0m...
749 16:29:04.593189 Starting [0;1;39mLoad Kernel Module drm[0m...
750 16:29:04.648867 Starting [0;1;39mJournal Service[0m...
751 16:29:04.681216 Starting [0;1;39mLoad Kernel Modules[0m...
752 16:29:04.720667 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
753 16:29:04.760985 Starting [0;1;39mColdplug All udev Devices[0m...
754 16:29:04.862367 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
755 16:29:04.873172 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
756 16:29:04.889539 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
757 16:29:04.936603 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
758 16:29:04.988470 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
759 16:29:05.017305 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
760 16:29:05.096501 Mounting [0;1;39mKernel Configuration File System[0m...
761 16:29:05.216737 Starting [0;1;39mApply Kernel Variables[0m...
762 16:29:05.289967 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
763 16:29:05.318805 <47>[ 7.925054] systemd-journald[105]: SELinux enabled state cached to: disabled
764 16:29:05.336714 <47>[ 7.942768] systemd-journald[105]: Auditing in kernel turned off.
765 16:29:05.353467 <47>[ 7.959481] systemd-journald[105]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
766 16:29:05.404722 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
767 16:29:05.407731 See 'systemctl status systemd-remount-fs.service' for details.
768 16:29:05.420739 <47>[ 8.026755] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
769 16:29:05.423076 <47>[ 8.029205] systemd-journald[105]: Fixed min_use=3.8M max_use=19.4M max_size=2.4M min_size=512.0K keep_free=9.7M n_max_files=100
770 16:29:05.437098 <47>[ 8.043366] systemd-journald[105]: Reserving 333 entries in field hash table.
771 16:29:05.453804 Starting [0;1;39mLoad/Save Random Seed[0m...
772 16:29:05.474237 <47>[ 8.080063] systemd-journald[105]: Reserving 4437 entries in data hash table.
773 16:29:05.488242 <47>[ 8.094457] systemd-journald[105]: Vacuuming...
774 16:29:05.489217 <47>[ 8.095355] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
775 16:29:05.490003 <47>[ 8.096115] systemd-journald[105]: Flushing /dev/kmsg...
776 16:29:05.517127 Starting [0;1;39mCreate System Users[0m...
777 16:29:05.556039 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
778 16:29:05.664470 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
779 16:29:05.869248 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
780 16:29:05.909078 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
781 16:29:06.038629 <47>[ 8.644476] systemd-journald[105]: systemd-journald running as PID 105 for the system.
782 16:29:06.052943 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
783 16:29:06.059855 <47>[ 8.665896] systemd-journald[105]: Sent READY=1 notification.
784 16:29:06.060095 <47>[ 8.666334] systemd-journald[105]: Sent WATCHDOG=1 notification.
785 16:29:06.094223 <47>[ 8.700397] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
786 16:29:06.105689 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
787 16:29:06.114617 <47>[ 8.720584] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
788 16:29:06.138438 <47>[ 8.744346] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
789 16:29:06.159891 <47>[ 8.765794] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
790 16:29:06.174177 <47>[ 8.780088] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
791 16:29:06.192593 <47>[ 8.798808] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
792 16:29:06.195359 <47>[ 8.801397] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
793 16:29:06.198911 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
794 16:29:06.220366 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
795 16:29:06.225172 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
796 16:29:06.238535 <47>[ 8.844459] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
797 16:29:06.254189 <47>[ 8.860196] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
798 16:29:06.264688 <47>[ 8.870718] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
799 16:29:06.266488 <47>[ 8.872764] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
800 16:29:06.281655 <47>[ 8.887628] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
801 16:29:06.299927 <47>[ 8.906172] systemd-journald[105]: n/a: New incoming connection.
802 16:29:06.300474 <47>[ 8.906774] systemd-journald[105]: varlink-18: varlink: setting state idle-server
803 16:29:06.301955 <47>[ 8.908144] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
804 16:29:06.302789 <47>[ 8.908911] systemd-journald[105]: varlink-18: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
805 16:29:06.317157 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
806 16:29:06.320636 <47>[ 8.926767] systemd-journald[105]: varlink-18: varlink: changing state idle-server → processing-method
807 16:29:06.321080 <46>[ 8.927170] systemd-journald[105]: Received client request to flush runtime journal.
808 16:29:06.321716 <47>[ 8.927755] systemd-journald[105]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
809 16:29:06.322228 <47>[ 8.928601] systemd-journald[105]: Vacuuming...
810 16:29:06.322984 <47>[ 8.929062] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
811 16:29:06.340300 <47>[ 8.946588] systemd-journald[105]: varlink-18: Sending message: {\"parameters\":{}}
812 16:29:06.340929 <47>[ 8.946882] systemd-journald[105]: varlink-18: varlink: changing state processing-method → processed-method
813 16:29:06.341141 <47>[ 8.947263] systemd-journald[105]: varlink-18: varlink: changing state processed-method → idle-server
814 16:29:06.353665 <47>[ 8.959593] systemd-journald[105]: varlink-18: varlink: changing state idle-server → pending-disconnect
815 16:29:06.353955 <47>[ 8.959990] systemd-journald[105]: varlink-18: varlink: changing state pending-disconnect → processing-disconnect
816 16:29:06.354173 <47>[ 8.960327] systemd-journald[105]: varlink-18: varlink: changing state processing-disconnect → disconnected
817 16:29:06.370077 <47>[ 8.976281] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
818 16:29:06.380145 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
819 16:29:06.382744 <47>[ 8.988758] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
820 16:29:06.448790 Starting [0;1;39mCreate Volatile Files and Directories[0m...
821 16:29:06.467457 <47>[ 9.073696] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
822 16:29:06.944618 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
823 16:29:07.021130 Starting [0;1;39mNetwork Service[0m...
824 16:29:07.053179 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
825 16:29:07.062509 <47>[ 9.668399] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
826 16:29:07.181239 Starting [0;1;39mNetwork Time Synchronization[0m...
827 16:29:07.206296 <47>[ 9.812202] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
828 16:29:07.248930 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
829 16:29:07.253939 <47>[ 9.859958] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
830 16:29:07.700480 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
831 16:29:08.732839 <47>[ 11.338594] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
832 16:29:08.733102 <47>[ 11.339191] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
833 16:29:08.733496 <47>[ 11.339555] systemd-journald[105]: Rotating...
834 16:29:08.734479 <47>[ 11.340461] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
835 16:29:08.748567 <47>[ 11.354701] systemd-journald[105]: Reserving 333 entries in field hash table.
836 16:29:08.763403 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
837 16:29:08.798238 <47>[ 11.404429] systemd-journald[105]: Reserving 4437 entries in data hash table.
838 16:29:08.821614 <47>[ 11.427845] systemd-journald[105]: Vacuuming...
839 16:29:08.856023 <47>[ 11.462189] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
840 16:29:08.877341 Starting [0;1;39mNetwork Name Resolution[0m...
841 16:29:08.914064 <47>[ 11.520221] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
842 16:29:09.174004 <47>[ 11.780175] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
843 16:29:09.259958 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
844 16:29:09.261539 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
845 16:29:09.262358 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
846 16:29:10.512970 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
847 16:29:10.522971 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
848 16:29:10.545765 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
849 16:29:10.564560 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
850 16:29:10.570385 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
851 16:29:10.576982 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
852 16:29:10.606986 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
853 16:29:10.612433 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
854 16:29:10.613096 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
855 16:29:10.676972 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
856 16:29:10.688565 <47>[ 13.294791] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
857 16:29:10.858705 <47>[ 13.464911] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
858 16:29:10.871027 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
859 16:29:11.113990 Starting [0;1;39mUser Login Management[0m...
860 16:29:11.122038 <47>[ 13.728103] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
861 16:29:11.542719 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
862 16:29:11.544876 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
863 16:29:11.548245 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
864 16:29:11.620685 Starting [0;1;39mPermit User Sessions[0m...
865 16:29:11.641929 <47>[ 14.248154] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
866 16:29:11.812271 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
867 16:29:11.866590 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
868 16:29:11.912207 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
869 16:29:12.328235 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
870 16:29:14.422426 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
871 16:29:14.508648 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
872 16:29:14.528361 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
873 16:29:14.545748 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
874 16:29:14.554135 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
875 16:29:14.604524 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
876 16:29:14.614990 <47>[ 17.220978] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
877 16:29:14.690950 <6>[ 17.297159] virtio_net virtio0 enp0s1: renamed from eth0
878 16:29:14.843940 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
879 16:29:14.899485 <47>[ 17.505713] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
880 16:29:14.911791 <47>[ 17.517823] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
881 16:29:14.960456
882 16:29:14.961058 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
883 16:29:14.961240
884 16:29:14.961409 debian-bullseye-arm64 login: root (automatic login)
885 16:29:14.961560
886 16:29:15.232825 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:16:15 UTC 2023 aarch64
887 16:29:15.233161
888 16:29:15.233429 The programs included with the Debian GNU/Linux system are free software;
889 16:29:15.233631 the exact distribution terms for each program are described in the
890 16:29:15.233862 individual files in /usr/share/doc/*/copyright.
891 16:29:15.234016
892 16:29:15.234151 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
893 16:29:15.234282 permitted by applicable law.
894 16:29:15.757828 <47>[ 18.363817] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
895 16:29:15.888880 <47>[ 18.494440] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.1 (3331 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
896 16:29:15.889208 <47>[ 18.495058] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
897 16:29:15.889361 <47>[ 18.495488] systemd-journald[105]: Rotating...
898 16:29:15.890962 <47>[ 18.497019] systemd-journald[105]: Reserving 333 entries in field hash table.
899 16:29:15.930373 <47>[ 18.536586] systemd-journald[105]: Reserving 4437 entries in data hash table.
900 16:29:15.942340 <47>[ 18.548635] systemd-journald[105]: Vacuuming...
901 16:29:15.958378 <47>[ 18.564369] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
902 16:29:16.046683 <47>[ 18.652616] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
903 16:29:17.775683 <47>[ 20.381877] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
904 16:29:18.168960 Matched prompt #10: / #
906 16:29:18.169595 Setting prompt string to ['/ #']
907 16:29:18.169813 end: 2.2.1 login-action (duration 00:00:21) [common]
909 16:29:18.170237 end: 2.2 auto-login-action (duration 00:00:27) [common]
910 16:29:18.170409 start: 2.3 expect-shell-connection (timeout 00:04:31) [common]
911 16:29:18.170557 Setting prompt string to ['/ #']
912 16:29:18.170682 Forcing a shell prompt, looking for ['/ #']
914 16:29:18.221244 / #
915 16:29:18.221566 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
916 16:29:18.221809 Waiting using forced prompt support (timeout 00:02:30)
917 16:29:18.223529
918 16:29:18.232438 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
919 16:29:18.232672 start: 2.4 export-device-env (timeout 00:04:31) [common]
920 16:29:18.232852 end: 2.4 export-device-env (duration 00:00:00) [common]
921 16:29:18.233020 end: 2 boot-image-retry (duration 00:00:29) [common]
922 16:29:18.233185 start: 3 lava-test-retry (timeout 00:08:47) [common]
923 16:29:18.233371 start: 3.1 lava-test-shell (timeout 00:08:47) [common]
924 16:29:18.233556 Using namespace: common
926 16:29:18.334460 / # #
927 16:29:18.334768 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
928 16:29:18.335329 #
930 16:29:18.443331 / # mkdir /lava-556488
931 16:29:18.444179 mkdir /lava-556488
933 16:29:18.574351 / # mount /dev/disk/by-uuid/413a60d5-68af-433f-a12d-5b734ebaceff -t ext2 /lava-556488
934 16:29:18.575289 mount /dev/disk/by-uuid/413a60d5-68af-433f-a12d-5b734ebaceff -t ext2 /lava-556488
935 16:29:18.615186 <4>[ 21.221148] ext2 filesystem being mounted at /lava-556488 supports timestamps until 2038 (0x7fffffff)
937 16:29:18.755500 / # ls -la /lava-556488/bin/lava-test-runner
938 16:29:18.756649 ls -la /lava-556488/bin/lava-test-runner
939 16:29:18.798624 -rwxr-xr-x 1 root root 1039 Jun 3 16:28 /lava-556488/bin/lava-test-runner
940 16:29:18.810700 Using /lava-556488
942 16:29:18.911674 / # export SHELL=/bin/sh
943 16:29:18.912549 export SHELL=/bin/sh
945 16:29:19.020848 / # . /lava-556488/environment
946 16:29:19.021564 . /lava-556488/environment
948 16:29:19.132354 / # /lava-556488/bin/lava-test-runner /lava-556488/0
949 16:29:19.132627 Test shell timeout: 10s (minimum of the action and connection timeout)
950 16:29:19.133173 /lava-556488/bin/lava-test-runner /lava-556488/0
951 16:29:19.306820 + export TESTRUN_ID=0_timesync-off
952 16:29:19.307163 + cd /lava-556488/0/tests/0_timesync-off
953 16:29:19.310500 + cat uuid
954 16:29:19.322230 + UUID=556488_1.1.3.1
955 16:29:19.322475 + set +x
956 16:29:19.323122 <LAVA_SIGNAL_STARTRUN 0_timesync-off 556488_1.1.3.1>
957 16:29:19.323328 + systemctl stop systemd-timesyncd
958 16:29:19.323706 Received signal: <STARTRUN> 0_timesync-off 556488_1.1.3.1
959 16:29:19.323864 Starting test lava.0_timesync-off (556488_1.1.3.1)
960 16:29:19.324061 Skipping test definition patterns.
961 16:29:19.587398 + set +x
962 16:29:19.587926 <LAVA_SIGNAL_ENDRUN 0_timesync-off 556488_1.1.3.1>
963 16:29:19.588347 Received signal: <ENDRUN> 0_timesync-off 556488_1.1.3.1
964 16:29:19.588580 Ending use of test pattern.
965 16:29:19.588752 Ending test lava.0_timesync-off (556488_1.1.3.1), duration 0.26
967 16:29:19.630016 + export TESTRUN_ID=1_kselftest-arm64_qemu
968 16:29:19.631280 + cd /lava-556488/0/tests/1_kselftest-arm64_qemu
969 16:29:19.634566 + cat uuid
970 16:29:19.642987 + UUID=556488_1.1.3.5
971 16:29:19.643097 + set +x
972 16:29:19.643403 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 556488_1.1.3.5>
973 16:29:19.643601 + cd ./automated/linux/kselftest/
974 16:29:19.643948 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 556488_1.1.3.5
975 16:29:19.644111 Starting test lava.1_kselftest-arm64_qemu (556488_1.1.3.5)
976 16:29:19.644278 Skipping test definition patterns.
977 16:29:19.648048 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip-gitlab -e -p /opt/kselftests/mainline/ -n 1 -i 1
978 16:29:19.747666 INFO: install_deps skipped
979 16:29:19.784579 --2023-06-03 16:29:20-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig/gcc-10/kselftest.tar.xz
980 16:29:19.935891 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
981 16:29:20.154215 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
982 16:29:20.347178 HTTP request sent, awaiting response... 200 OK
983 16:29:20.350135 Length: 2699460 (2.6M) [application/octet-stream]
984 16:29:20.351615 Saving to: 'kselftest.tar.xz'
985 16:29:20.352870
986 16:29:21.663889 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 153KB/s kselftest.tar.xz 8%[> ] 219.84K 326KB/s kselftest.tar.xz 34%[=====> ] 898.59K 880KB/s kselftest.tar.xz 72%[=============> ] 1.85M 1.52MB/s kselftest.tar.xz 100%[===================>] 2.57M 2.02MB/s in 1.3s
987 16:29:21.664174
988 16:29:21.666445 2023-06-03 16:29:21 (2.02 MB/s) - 'kselftest.tar.xz' saved [2699460/2699460]
989 16:29:21.666617
990 16:29:24.740755 skiplist:
991 16:29:24.741043 ========================================
992 16:29:24.741484 ========================================
993 16:29:24.794251 arm64:tags_test
994 16:29:24.794596 arm64:run_tags_test.sh
995 16:29:24.794782 arm64:fake_sigreturn_bad_magic
996 16:29:24.795215 arm64:fake_sigreturn_bad_size
997 16:29:24.795417 arm64:fake_sigreturn_bad_size_for_magic0
998 16:29:24.795586 arm64:fake_sigreturn_duplicated_fpsimd
999 16:29:24.795751 arm64:fake_sigreturn_misaligned_sp
1000 16:29:24.795920 arm64:fake_sigreturn_missing_fpsimd
1001 16:29:24.796089 arm64:fake_sigreturn_sme_change_vl
1002 16:29:24.796259 arm64:fake_sigreturn_sve_change_vl
1003 16:29:24.796424 arm64:mangle_pstate_invalid_compat_toggle
1004 16:29:24.796582 arm64:mangle_pstate_invalid_daif_bits
1005 16:29:24.796714 arm64:mangle_pstate_invalid_mode_el1h
1006 16:29:24.796831 arm64:mangle_pstate_invalid_mode_el1t
1007 16:29:24.796947 arm64:mangle_pstate_invalid_mode_el2h
1008 16:29:24.797061 arm64:mangle_pstate_invalid_mode_el2t
1009 16:29:24.797174 arm64:mangle_pstate_invalid_mode_el3h
1010 16:29:24.797326 arm64:mangle_pstate_invalid_mode_el3t
1011 16:29:24.797451 arm64:sme_trap_no_sm
1012 16:29:24.797568 arm64:sme_trap_non_streaming
1013 16:29:24.797697 arm64:sme_trap_za
1014 16:29:24.797812 arm64:sme_vl
1015 16:29:24.797924 arm64:ssve_regs
1016 16:29:24.798039 arm64:sve_regs
1017 16:29:24.798152 arm64:sve_vl
1018 16:29:24.798263 arm64:za_no_regs
1019 16:29:24.798374 arm64:za_regs
1020 16:29:24.798486 arm64:pac
1021 16:29:24.798597 arm64:fp-stress
1022 16:29:24.798709 arm64:sve-ptrace
1023 16:29:24.798820 arm64:sve-probe-vls
1024 16:29:24.798933 arm64:vec-syscfg
1025 16:29:24.799056 arm64:za-fork
1026 16:29:24.799171 arm64:za-ptrace
1027 16:29:24.799283 arm64:check_buffer_fill
1028 16:29:24.799394 arm64:check_child_memory
1029 16:29:24.799505 arm64:check_gcr_el1_cswitch
1030 16:29:24.799617 arm64:check_ksm_options
1031 16:29:24.799728 arm64:check_mmap_options
1032 16:29:24.799839 arm64:check_prctl
1033 16:29:24.799949 arm64:check_tags_inclusion
1034 16:29:24.800060 arm64:check_user_mem
1035 16:29:24.800174 arm64:btitest
1036 16:29:24.800286 arm64:nobtitest
1037 16:29:24.800396 arm64:hwcap
1038 16:29:24.800507 arm64:ptrace
1039 16:29:24.800617 arm64:syscall-abi
1040 16:29:24.800728 arm64:tpidr2
1041 16:29:24.808654 ============== Tests to run ===============
1042 16:29:24.813547 arm64:tags_test
1043 16:29:24.813773 arm64:run_tags_test.sh
1044 16:29:24.814173 arm64:fake_sigreturn_bad_magic
1045 16:29:24.814294 arm64:fake_sigreturn_bad_size
1046 16:29:24.814392 arm64:fake_sigreturn_bad_size_for_magic0
1047 16:29:24.814484 arm64:fake_sigreturn_duplicated_fpsimd
1048 16:29:24.814576 arm64:fake_sigreturn_misaligned_sp
1049 16:29:24.814663 arm64:fake_sigreturn_missing_fpsimd
1050 16:29:24.814746 arm64:fake_sigreturn_sme_change_vl
1051 16:29:24.814832 arm64:fake_sigreturn_sve_change_vl
1052 16:29:24.814919 arm64:mangle_pstate_invalid_compat_toggle
1053 16:29:24.815026 arm64:mangle_pstate_invalid_daif_bits
1054 16:29:24.815115 arm64:mangle_pstate_invalid_mode_el1h
1055 16:29:24.815199 arm64:mangle_pstate_invalid_mode_el1t
1056 16:29:24.815281 arm64:mangle_pstate_invalid_mode_el2h
1057 16:29:24.815362 arm64:mangle_pstate_invalid_mode_el2t
1058 16:29:24.815446 arm64:mangle_pstate_invalid_mode_el3h
1059 16:29:24.815529 arm64:mangle_pstate_invalid_mode_el3t
1060 16:29:24.815613 arm64:sme_trap_no_sm
1061 16:29:24.815696 arm64:sme_trap_non_streaming
1062 16:29:24.815780 arm64:sme_trap_za
1063 16:29:24.815863 arm64:sme_vl
1064 16:29:24.815947 arm64:ssve_regs
1065 16:29:24.816031 arm64:sve_regs
1066 16:29:24.816115 arm64:sve_vl
1067 16:29:24.816197 arm64:za_no_regs
1068 16:29:24.816279 arm64:za_regs
1069 16:29:24.816382 arm64:pac
1070 16:29:24.816467 arm64:fp-stress
1071 16:29:24.816549 arm64:sve-ptrace
1072 16:29:24.816632 arm64:sve-probe-vls
1073 16:29:24.816713 arm64:vec-syscfg
1074 16:29:24.816795 arm64:za-fork
1075 16:29:24.816874 arm64:za-ptrace
1076 16:29:24.816956 arm64:check_buffer_fill
1077 16:29:24.817038 arm64:check_child_memory
1078 16:29:24.817126 arm64:check_gcr_el1_cswitch
1079 16:29:24.817212 arm64:check_ksm_options
1080 16:29:24.817295 arm64:check_mmap_options
1081 16:29:24.817378 arm64:check_prctl
1082 16:29:24.817461 arm64:check_tags_inclusion
1083 16:29:24.817546 arm64:check_user_mem
1084 16:29:24.817630 arm64:btitest
1085 16:29:24.817725 arm64:nobtitest
1086 16:29:24.817807 arm64:hwcap
1087 16:29:24.817889 arm64:ptrace
1088 16:29:24.817972 arm64:syscall-abi
1089 16:29:24.818054 arm64:tpidr2
1090 16:29:24.818153 ===========End Tests to run ===============
1091 16:29:25.751919 <12>[ 28.358125] kselftest: Running tests in arm64
1092 16:29:25.780685 TAP version 13
1093 16:29:25.798517 1..48
1094 16:29:25.846343 # selftests: arm64: tags_test
1095 16:29:25.900185 ok 1 selftests: arm64: tags_test
1096 16:29:25.947711 # selftests: arm64: run_tags_test.sh
1097 16:29:25.998268 # --------------------
1098 16:29:25.998517 # running tags test
1099 16:29:25.998643 # --------------------
1100 16:29:25.998759 # [PASS]
1101 16:29:26.006304 ok 2 selftests: arm64: run_tags_test.sh
1102 16:29:26.051981 # selftests: arm64: fake_sigreturn_bad_magic
1103 16:29:26.101440 # Registered handlers for all signals.
1104 16:29:26.101732 # Detected MINSTKSIGSZ:10000
1105 16:29:26.102168 # Testcase initialized.
1106 16:29:26.102328 # uc context validated.
1107 16:29:26.102454 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1108 16:29:26.102572 # Handled SIG_COPYCTX
1109 16:29:26.102687 # Available space:3536
1110 16:29:26.102802 # Using badly built context - ERR: BAD MAGIC !
1111 16:29:26.102918 # SIG_OK -- SP:0xFFFFD3B60540 si_addr@:0xffffd3b60540 si_code:2 token@:0xffffd3b5f2e0 offset:-4704
1112 16:29:26.103035 # ==>> completed. PASS(1)
1113 16:29:26.103151 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1114 16:29:26.103497 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD3B5F2E0
1115 16:29:26.109894 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1116 16:29:26.154977 # selftests: arm64: fake_sigreturn_bad_size
1117 16:29:26.204646 # Registered handlers for all signals.
1118 16:29:26.205114 # Detected MINSTKSIGSZ:10000
1119 16:29:26.205223 # Testcase initialized.
1120 16:29:26.205316 # uc context validated.
1121 16:29:26.205404 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1122 16:29:26.205489 # Handled SIG_COPYCTX
1123 16:29:26.205574 # Available space:3536
1124 16:29:26.205667 # uc context validated.
1125 16:29:26.205772 # Using badly built context - ERR: Bad size for esr_context
1126 16:29:26.205859 # SIG_OK -- SP:0xFFFFF1D6B290 si_addr@:0xfffff1d6b290 si_code:2 token@:0xfffff1d6a030 offset:-4704
1127 16:29:26.205948 # ==>> completed. PASS(1)
1128 16:29:26.206035 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1129 16:29:26.206121 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF1D6A030
1130 16:29:26.213506 ok 4 selftests: arm64: fake_sigreturn_bad_size
1131 16:29:26.259081 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1132 16:29:26.308983 # Registered handlers for all signals.
1133 16:29:26.309286 # Detected MINSTKSIGSZ:10000
1134 16:29:26.309660 # Testcase initialized.
1135 16:29:26.309802 # uc context validated.
1136 16:29:26.309932 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1137 16:29:26.310060 # Handled SIG_COPYCTX
1138 16:29:26.311010 # Available space:3536
1139 16:29:26.311342 # Using badly built context - ERR: Bad size for terminator
1140 16:29:26.311454 # SIG_OK -- SP:0xFFFFD86D2660 si_addr@:0xffffd86d2660 si_code:2 token@:0xffffd86d1400 offset:-4704
1141 16:29:26.311572 # ==>> completed. PASS(1)
1142 16:29:26.311667 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1143 16:29:26.311780 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD86D1400
1144 16:29:26.318470 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1145 16:29:26.364181 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1146 16:29:26.415040 # Registered handlers for all signals.
1147 16:29:26.415386 # Detected MINSTKSIGSZ:10000
1148 16:29:26.415946 # Testcase initialized.
1149 16:29:26.416130 # uc context validated.
1150 16:29:26.416325 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1151 16:29:26.416482 # Handled SIG_COPYCTX
1152 16:29:26.416628 # Available space:3536
1153 16:29:26.416770 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1154 16:29:26.416913 # SIG_OK -- SP:0xFFFFDE1D4F70 si_addr@:0xffffde1d4f70 si_code:2 token@:0xffffde1d3d10 offset:-4704
1155 16:29:26.417059 # ==>> completed. PASS(1)
1156 16:29:26.417239 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1157 16:29:26.417395 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDE1D3D10
1158 16:29:26.426090 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1159 16:29:26.472975 # selftests: arm64: fake_sigreturn_misaligned_sp
1160 16:29:26.521900 # Registered handlers for all signals.
1161 16:29:26.522353 # Detected MINSTKSIGSZ:10000
1162 16:29:26.522450 # Testcase initialized.
1163 16:29:26.522538 # uc context validated.
1164 16:29:26.522623 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1165 16:29:26.522709 # Handled SIG_COPYCTX
1166 16:29:26.522810 # SIG_OK -- SP:0xFFFFEFC6A343 si_addr@:0xffffefc6a343 si_code:2 token@:0xffffefc6a343 offset:0
1167 16:29:26.522899 # ==>> completed. PASS(1)
1168 16:29:26.522983 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1169 16:29:26.523068 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEFC6A343
1170 16:29:26.530468 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1171 16:29:26.579165 # selftests: arm64: fake_sigreturn_missing_fpsimd
1172 16:29:26.628307 # Registered handlers for all signals.
1173 16:29:26.628795 # Detected MINSTKSIGSZ:10000
1174 16:29:26.628914 # Testcase initialized.
1175 16:29:26.629008 # uc context validated.
1176 16:29:26.629094 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1177 16:29:26.629182 # Handled SIG_COPYCTX
1178 16:29:26.629272 # Mangling template header. Spare space:4096
1179 16:29:26.629379 # Using badly built context - ERR: Missing FPSIMD
1180 16:29:26.631028 # SIG_OK -- SP:0xFFFFD0922E60 si_addr@:0xffffd0922e60 si_code:2 token@:0xffffd0921c00 offset:-4704
1181 16:29:26.631459 # ==>> completed. PASS(1)
1182 16:29:26.631573 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1183 16:29:26.631666 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD0921C00
1184 16:29:26.638511 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1185 16:29:26.683767 # selftests: arm64: fake_sigreturn_sme_change_vl
1186 16:29:26.736352 # Registered handlers for all signals.
1187 16:29:26.736606 # Detected MINSTKSIGSZ:10000
1188 16:29:26.736942 # Required Features: [ SME ] supported
1189 16:29:26.737042 # Incompatible Features: [] absent
1190 16:29:26.737125 # Testcase initialized.
1191 16:29:26.737203 # uc context validated.
1192 16:29:26.737273 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1193 16:29:26.737349 # Handled SIG_COPYCTX
1194 16:29:26.737458 # Attempting to change VL from 16 to 256
1195 16:29:26.737569 # SIG_OK -- SP:0xFFFFE071D130 si_addr@:0xffffe071d130 si_code:2 token@:0xffffe071bed0 offset:-4704
1196 16:29:26.737641 # ==>> completed. PASS(1)
1197 16:29:26.737760 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1198 16:29:26.737895 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE071BED0
1199 16:29:26.744430 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1200 16:29:26.789325 # selftests: arm64: fake_sigreturn_sve_change_vl
1201 16:29:26.838998 # Registered handlers for all signals.
1202 16:29:26.839462 # Detected MINSTKSIGSZ:10000
1203 16:29:26.839569 # Required Features: [ SVE ] supported
1204 16:29:26.839664 # Incompatible Features: [] absent
1205 16:29:26.839753 # Testcase initialized.
1206 16:29:26.839839 # uc context validated.
1207 16:29:26.839942 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1208 16:29:26.840036 # Handled SIG_COPYCTX
1209 16:29:26.840121 # Attempting to change VL from 16 to 256
1210 16:29:26.840222 # SIG_OK -- SP:0xFFFFD68CFF30 si_addr@:0xffffd68cff30 si_code:2 token@:0xffffd68cecd0 offset:-4704
1211 16:29:26.840311 # ==>> completed. PASS(1)
1212 16:29:26.840410 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1213 16:29:26.840514 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD68CECD0
1214 16:29:26.849251 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1215 16:29:26.894542 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1216 16:29:26.943708 # Registered handlers for all signals.
1217 16:29:26.944036 # Detected MINSTKSIGSZ:10000
1218 16:29:26.944422 # Testcase initialized.
1219 16:29:26.944557 # uc context validated.
1220 16:29:26.944679 # Handled SIG_TRIG
1221 16:29:26.944797 # SIG_OK -- SP:0xFFFFD01634B0 si_addr@:0xffffd01634b0 si_code:2 token@:(nil) offset:-281474172859568
1222 16:29:26.944919 # ==>> completed. PASS(1)
1223 16:29:26.945036 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1224 16:29:26.952166 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1225 16:29:26.998182 # selftests: arm64: mangle_pstate_invalid_daif_bits
1226 16:29:27.046412 # Registered handlers for all signals.
1227 16:29:27.046677 # Detected MINSTKSIGSZ:10000
1228 16:29:27.047022 # Testcase initialized.
1229 16:29:27.047149 # uc context validated.
1230 16:29:27.047266 # Handled SIG_TRIG
1231 16:29:27.047380 # SIG_OK -- SP:0xFFFFDEBFABD0 si_addr@:0xffffdebfabd0 si_code:2 token@:(nil) offset:-281474418846672
1232 16:29:27.047517 # ==>> completed. PASS(1)
1233 16:29:27.047636 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1234 16:29:27.055847 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1235 16:29:27.101209 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1236 16:29:27.149414 # Registered handlers for all signals.
1237 16:29:27.149730 # Detected MINSTKSIGSZ:10000
1238 16:29:27.149948 # Testcase initialized.
1239 16:29:27.150367 # uc context validated.
1240 16:29:27.150526 # Handled SIG_TRIG
1241 16:29:27.150680 # SIG_OK -- SP:0xFFFFFDC55190 si_addr@:0xfffffdc55190 si_code:2 token@:(nil) offset:-281474939310480
1242 16:29:27.150828 # ==>> completed. PASS(1)
1243 16:29:27.151018 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1244 16:29:27.158297 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1245 16:29:27.204268 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1246 16:29:27.252861 # Registered handlers for all signals.
1247 16:29:27.253089 # Detected MINSTKSIGSZ:10000
1248 16:29:27.253179 # Testcase initialized.
1249 16:29:27.253263 # uc context validated.
1250 16:29:27.253365 # Handled SIG_TRIG
1251 16:29:27.253452 # SIG_OK -- SP:0xFFFFE42FAF30 si_addr@:0xffffe42faf30 si_code:2 token@:(nil) offset:-281474510073648
1252 16:29:27.253537 # ==>> completed. PASS(1)
1253 16:29:27.253635 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1254 16:29:27.262670 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1255 16:29:27.307443 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1256 16:29:27.356158 # Registered handlers for all signals.
1257 16:29:27.356657 # Detected MINSTKSIGSZ:10000
1258 16:29:27.356840 # Testcase initialized.
1259 16:29:27.356937 # uc context validated.
1260 16:29:27.357025 # Handled SIG_TRIG
1261 16:29:27.357118 # SIG_OK -- SP:0xFFFFF35B4480 si_addr@:0xfffff35b4480 si_code:2 token@:(nil) offset:-281474764588160
1262 16:29:27.357208 # ==>> completed. PASS(1)
1263 16:29:27.357313 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1264 16:29:27.364932 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1265 16:29:27.410468 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1266 16:29:27.458773 # Registered handlers for all signals.
1267 16:29:27.459225 # Detected MINSTKSIGSZ:10000
1268 16:29:27.459330 # Testcase initialized.
1269 16:29:27.459419 # uc context validated.
1270 16:29:27.459504 # Handled SIG_TRIG
1271 16:29:27.459588 # SIG_OK -- SP:0xFFFFE37B23C0 si_addr@:0xffffe37b23c0 si_code:2 token@:(nil) offset:-281474498241472
1272 16:29:27.459898 # ==>> completed. PASS(1)
1273 16:29:27.460073 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1274 16:29:27.467942 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1275 16:29:27.513013 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1276 16:29:27.559953 # Registered handlers for all signals.
1277 16:29:27.560299 # Detected MINSTKSIGSZ:10000
1278 16:29:27.560733 # Testcase initialized.
1279 16:29:27.560888 # uc context validated.
1280 16:29:27.561039 # Handled SIG_TRIG
1281 16:29:27.561184 # SIG_OK -- SP:0xFFFFDECED880 si_addr@:0xffffdeced880 si_code:2 token@:(nil) offset:-281474419841152
1282 16:29:27.561332 # ==>> completed. PASS(1)
1283 16:29:27.561477 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1284 16:29:27.569550 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1285 16:29:27.614378 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1286 16:29:27.663010 # Registered handlers for all signals.
1287 16:29:27.663345 # Detected MINSTKSIGSZ:10000
1288 16:29:27.663939 # Testcase initialized.
1289 16:29:27.664107 # uc context validated.
1290 16:29:27.664243 # Handled SIG_TRIG
1291 16:29:27.664410 # SIG_OK -- SP:0xFFFFC295CE70 si_addr@:0xffffc295ce70 si_code:2 token@:(nil) offset:-281473946340976
1292 16:29:27.664598 # ==>> completed. PASS(1)
1293 16:29:27.664741 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1294 16:29:27.671681 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1295 16:29:27.717761 # selftests: arm64: sme_trap_no_sm
1296 16:29:27.824505 # Registered handlers for all signals.
1297 16:29:27.824754 # Detected MINSTKSIGSZ:10000
1298 16:29:27.824871 # Required Features: [ SME ] supported
1299 16:29:27.824965 # Incompatible Features: [] absent
1300 16:29:27.825065 # Testcase initialized.
1301 16:29:27.825366 # SIG_OK -- SP:0xFFFFD833C780 si_addr@:0xaaaaca4a2514 si_code:1 token@:(nil) offset:-187650515019028
1302 16:29:27.825475 # ==>> completed. PASS(1)
1303 16:29:27.825778 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1304 16:29:27.847184 ok 19 selftests: arm64: sme_trap_no_sm
1305 16:29:27.939285 # selftests: arm64: sme_trap_non_streaming
1306 16:29:27.999912 # Registered handlers for all signals.
1307 16:29:28.000163 # Detected MINSTKSIGSZ:10000
1308 16:29:28.000270 # Required Features: [] NOT supported
1309 16:29:28.000365 # Incompatible Features: [] supported
1310 16:29:28.000665 # ==>> completed. SKIP.
1311 16:29:28.001778 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1312 16:29:28.010421 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1313 16:29:28.060898 # selftests: arm64: sme_trap_za
1314 16:29:28.110997 # Registered handlers for all signals.
1315 16:29:28.111238 # Detected MINSTKSIGSZ:10000
1316 16:29:28.111538 # Testcase initialized.
1317 16:29:28.111637 # SIG_OK -- SP:0xFFFFC5431500 si_addr@:0xaaaacc3b2510 si_code:1 token@:(nil) offset:-187650547590416
1318 16:29:28.111733 # ==>> completed. PASS(1)
1319 16:29:28.111823 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1320 16:29:28.117948 ok 21 selftests: arm64: sme_trap_za
1321 16:29:28.164112 # selftests: arm64: sme_vl
1322 16:29:28.214383 # Registered handlers for all signals.
1323 16:29:28.214691 # Detected MINSTKSIGSZ:10000
1324 16:29:28.215111 # Required Features: [ SME ] supported
1325 16:29:28.215272 # Incompatible Features: [] absent
1326 16:29:28.215403 # Testcase initialized.
1327 16:29:28.215522 # uc context validated.
1328 16:29:28.215640 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1329 16:29:28.215783 # Handled SIG_COPYCTX
1330 16:29:28.215917 # got expected VL 32
1331 16:29:28.216037 # ==>> completed. PASS(1)
1332 16:29:28.216154 # # SME VL :: Check that we get the right SME VL reported
1333 16:29:28.223610 ok 22 selftests: arm64: sme_vl
1334 16:29:28.268730 # selftests: arm64: ssve_regs
1335 16:29:28.452232 # Registered handlers for all signals.
1336 16:29:28.453790 # Detected MINSTKSIGSZ:10000
1337 16:29:28.454263 # Required Features: [ SME FA64 ] supported
1338 16:29:28.454435 # Incompatible Features: [] absent
1339 16:29:28.454613 # Testcase initialized.
1340 16:29:28.454765 # Testing VL 256
1341 16:29:28.454910 # Validating EXTRA...
1342 16:29:28.455055 # uc context validated.
1343 16:29:28.455241 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1344 16:29:28.455382 # Handled SIG_COPYCTX
1345 16:29:28.455527 # Got expected size 8752 and VL 256
1346 16:29:28.455671 # Testing VL 128
1347 16:29:28.455815 # Validating EXTRA...
1348 16:29:28.455957 # uc context validated.
1349 16:29:28.456106 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1350 16:29:28.456250 # Handled SIG_COPYCTX
1351 16:29:28.456392 # Got expected size 4384 and VL 128
1352 16:29:28.456533 # Testing VL 64
1353 16:29:28.456675 # uc context validated.
1354 16:29:28.456817 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1355 16:29:28.456960 # Handled SIG_COPYCTX
1356 16:29:28.457102 # Got expected size 2208 and VL 64
1357 16:29:28.457245 # Testing VL 32
1358 16:29:28.457384 # uc context validated.
1359 16:29:28.457564 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1360 16:29:28.457714 # Handled SIG_COPYCTX
1361 16:29:28.457857 # Got expected size 1120 and VL 32
1362 16:29:28.458103 # Testing VL 16
1363 16:29:28.458276 # uc context validated.
1364 16:29:28.458421 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1365 16:29:28.458564 # Handled SIG_COPYCTX
1366 16:29:28.458704 # Got expected size 576 and VL 16
1367 16:29:28.458842 # ==>> completed. PASS(1)
1368 16:29:28.458983 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1369 16:29:28.462809 ok 23 selftests: arm64: ssve_regs
1370 16:29:28.509055 # selftests: arm64: sve_regs
1371 16:29:29.089097 # Registered handlers for all signals.
1372 16:29:29.089327 # Detected MINSTKSIGSZ:10000
1373 16:29:29.089429 # Required Features: [ SVE ] supported
1374 16:29:29.093123 # Incompatible Features: [] absent
1375 16:29:29.093445 # Testcase initialized.
1376 16:29:29.093551 # Testing VL 256
1377 16:29:29.093635 # Validating EXTRA...
1378 16:29:29.093739 # uc context validated.
1379 16:29:29.094023 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1380 16:29:29.094127 # Handled SIG_COPYCTX
1381 16:29:29.103521 # Got expected size 8752 and VL 256
1382 16:29:29.103974 # Testing VL 240
1383 16:29:29.104089 # Validating EXTRA...
1384 16:29:29.104189 # uc context validated.
1385 16:29:29.104316 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1386 16:29:29.104637 # Handled SIG_COPYCTX
1387 16:29:29.104747 # Got expected size 8208 and VL 240
1388 16:29:29.104844 # Testing VL 224
1389 16:29:29.104936 # Validating EXTRA...
1390 16:29:29.105046 # uc context validated.
1391 16:29:29.105358 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1392 16:29:29.105471 # Handled SIG_COPYCTX
1393 16:29:29.105567 # Got expected size 7664 and VL 224
1394 16:29:29.105669 # Testing VL 208
1395 16:29:29.105779 # Validating EXTRA...
1396 16:29:29.105889 # uc context validated.
1397 16:29:29.110401 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1398 16:29:29.110701 # Handled SIG_COPYCTX
1399 16:29:29.110812 # Got expected size 7120 and VL 208
1400 16:29:29.110918 # Testing VL 192
1401 16:29:29.111007 # Validating EXTRA...
1402 16:29:29.111096 # uc context validated.
1403 16:29:29.111185 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1404 16:29:29.111295 # Handled SIG_COPYCTX
1405 16:29:29.111392 # Got expected size 6576 and VL 192
1406 16:29:29.111484 # Testing VL 176
1407 16:29:29.111575 # Validating EXTRA...
1408 16:29:29.111686 # uc context validated.
1409 16:29:29.111779 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1410 16:29:29.111872 # Handled SIG_COPYCTX
1411 16:29:29.111981 # Got expected size 6032 and VL 176
1412 16:29:29.112075 # Testing VL 160
1413 16:29:29.112168 # Validating EXTRA...
1414 16:29:29.112277 # uc context validated.
1415 16:29:29.112373 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1416 16:29:29.112466 # Handled SIG_COPYCTX
1417 16:29:29.112555 # Got expected size 5488 and VL 160
1418 16:29:29.112662 # Testing VL 144
1419 16:29:29.112754 # Validating EXTRA...
1420 16:29:29.112844 # uc context validated.
1421 16:29:29.112945 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1422 16:29:29.113027 # Handled SIG_COPYCTX
1423 16:29:29.113111 # Got expected size 4944 and VL 144
1424 16:29:29.113197 # Testing VL 128
1425 16:29:29.113284 # Validating EXTRA...
1426 16:29:29.113385 # uc context validated.
1427 16:29:29.113475 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1428 16:29:29.113580 # Handled SIG_COPYCTX
1429 16:29:29.113678 # Got expected size 4384 and VL 128
1430 16:29:29.113782 # Testing VL 112
1431 16:29:29.113867 # Validating EXTRA...
1432 16:29:29.113954 # uc context validated.
1433 16:29:29.114057 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1434 16:29:29.114160 # Handled SIG_COPYCTX
1435 16:29:29.114250 # Got expected size 3840 and VL 112
1436 16:29:29.118602 # Testing VL 96
1437 16:29:29.118961 # uc context validated.
1438 16:29:29.119090 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1439 16:29:29.119203 # Handled SIG_COPYCTX
1440 16:29:29.119301 # Got expected size 3296 and VL 96
1441 16:29:29.119409 # Testing VL 80
1442 16:29:29.119500 # uc context validated.
1443 16:29:29.119604 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1444 16:29:29.119901 # Handled SIG_COPYCTX
1445 16:29:29.120001 # Got expected size 2752 and VL 80
1446 16:29:29.120088 # Testing VL 64
1447 16:29:29.120171 # uc context validated.
1448 16:29:29.120270 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1449 16:29:29.120356 # Handled SIG_COPYCTX
1450 16:29:29.120439 # Got expected size 2208 and VL 64
1451 16:29:29.120541 # Testing VL 48
1452 16:29:29.120631 # uc context validated.
1453 16:29:29.120720 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1454 16:29:29.120820 # Handled SIG_COPYCTX
1455 16:29:29.120904 # Got expected size 1664 and VL 48
1456 16:29:29.120999 # Testing VL 32
1457 16:29:29.121083 # uc context validated.
1458 16:29:29.121160 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1459 16:29:29.121254 # Handled SIG_COPYCTX
1460 16:29:29.121341 # Got expected size 1120 and VL 32
1461 16:29:29.121435 # Testing VL 16
1462 16:29:29.121941 # uc context validated.
1463 16:29:29.122050 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1464 16:29:29.122341 # Handled SIG_COPYCTX
1465 16:29:29.122451 # Got expected size 576 and VL 16
1466 16:29:29.122544 # ==>> completed. PASS(1)
1467 16:29:29.122633 # # SVE registers :: Check that we get the right SVE registers reported
1468 16:29:29.126711 ok 24 selftests: arm64: sve_regs
1469 16:29:29.195660 # selftests: arm64: sve_vl
1470 16:29:29.284300 # Registered handlers for all signals.
1471 16:29:29.284495 # Detected MINSTKSIGSZ:10000
1472 16:29:29.284605 # Required Features: [ SVE ] supported
1473 16:29:29.284691 # Incompatible Features: [] absent
1474 16:29:29.284772 # Testcase initialized.
1475 16:29:29.284867 # uc context validated.
1476 16:29:29.284950 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1477 16:29:29.285045 # Handled SIG_COPYCTX
1478 16:29:29.285140 # got expected VL 64
1479 16:29:29.285222 # ==>> completed. PASS(1)
1480 16:29:29.285316 # # SVE VL :: Check that we get the right SVE VL reported
1481 16:29:29.300250 ok 25 selftests: arm64: sve_vl
1482 16:29:29.434463 # selftests: arm64: za_no_regs
1483 16:29:29.548502 # Registered handlers for all signals.
1484 16:29:29.548768 # Detected MINSTKSIGSZ:10000
1485 16:29:29.548885 # Required Features: [ SME ] supported
1486 16:29:29.549185 # Incompatible Features: [] absent
1487 16:29:29.549296 # Testcase initialized.
1488 16:29:29.549414 # Testing VL 256
1489 16:29:29.549512 # uc context validated.
1490 16:29:29.549605 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1491 16:29:29.549706 # Handled SIG_COPYCTX
1492 16:29:29.549816 # Got expected size 16 and VL 256
1493 16:29:29.549910 # Testing VL 128
1494 16:29:29.550001 # uc context validated.
1495 16:29:29.550108 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1496 16:29:29.550216 # Handled SIG_COPYCTX
1497 16:29:29.550310 # Got expected size 16 and VL 128
1498 16:29:29.550417 # Testing VL 64
1499 16:29:29.550511 # uc context validated.
1500 16:29:29.550617 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1501 16:29:29.550711 # Handled SIG_COPYCTX
1502 16:29:29.551020 # Got expected size 16 and VL 64
1503 16:29:29.551131 # Testing VL 32
1504 16:29:29.551225 # uc context validated.
1505 16:29:29.561137 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1506 16:29:29.561651 # Handled SIG_COPYCTX
1507 16:29:29.561969 # Got expected size 16 and VL 32
1508 16:29:29.562298 # Testing VL 16
1509 16:29:29.562624 # uc context validated.
1510 16:29:29.562749 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1511 16:29:29.562862 # Handled SIG_COPYCTX
1512 16:29:29.562971 # Got expected size 16 and VL 16
1513 16:29:29.563279 # ==>> completed. PASS(1)
1514 16:29:29.563388 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1515 16:29:29.563856 ok 26 selftests: arm64: za_no_regs
1516 16:29:29.635512 # selftests: arm64: za_regs
1517 16:29:29.905582 # Registered handlers for all signals.
1518 16:29:29.905856 # Detected MINSTKSIGSZ:10000
1519 16:29:29.905959 # Required Features: [ SME ] supported
1520 16:29:29.906066 # Incompatible Features: [] absent
1521 16:29:29.909747 # Testcase initialized.
1522 16:29:29.909862 # Testing VL 256
1523 16:29:29.909951 # Validating EXTRA...
1524 16:29:29.910035 # uc context validated.
1525 16:29:29.910117 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1526 16:29:29.910201 # Handled SIG_COPYCTX
1527 16:29:29.912189 # Got expected size 65552 and VL 256
1528 16:29:29.912711 # Testing VL 128
1529 16:29:29.922804 # Validating EXTRA...
1530 16:29:29.923222 # uc context validated.
1531 16:29:29.923948 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1532 16:29:29.924282 # Handled SIG_COPYCTX
1533 16:29:29.924390 # Got expected size 16400 and VL 128
1534 16:29:29.924482 # Testing VL 64
1535 16:29:29.924567 # Validating EXTRA...
1536 16:29:29.924669 # uc context validated.
1537 16:29:29.929782 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1538 16:29:29.930090 # Handled SIG_COPYCTX
1539 16:29:29.930425 # Got expected size 4112 and VL 64
1540 16:29:29.930764 # Testing VL 32
1541 16:29:29.931298 # uc context validated.
1542 16:29:29.932660 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1543 16:29:29.933362 # Handled SIG_COPYCTX
1544 16:29:29.937925 # Got expected size 1040 and VL 32
1545 16:29:29.938248 # Testing VL 16
1546 16:29:29.938370 # uc context validated.
1547 16:29:29.938876 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1548 16:29:29.939205 # Handled SIG_COPYCTX
1549 16:29:29.940124 # Got expected size 272 and VL 16
1550 16:29:29.940647 # ==>> completed. PASS(1)
1551 16:29:29.947220 # # ZA register :: Check that we get the right ZA registers reported
1552 16:29:29.947944 ok 27 selftests: arm64: za_regs
1553 16:29:30.018144 # selftests: arm64: pac
1554 16:29:30.272234 # TAP version 13
1555 16:29:30.272479 # 1..7
1556 16:29:30.272809 # # Starting 7 tests from 1 test cases.
1557 16:29:30.272916 # # RUN global.corrupt_pac ...
1558 16:29:30.273008 # # OK global.corrupt_pac
1559 16:29:30.273094 # ok 1 global.corrupt_pac
1560 16:29:30.273197 # # RUN global.pac_instructions_not_nop ...
1561 16:29:30.273285 # # OK global.pac_instructions_not_nop
1562 16:29:30.273370 # ok 2 global.pac_instructions_not_nop
1563 16:29:30.273475 # # RUN global.pac_instructions_not_nop_generic ...
1564 16:29:30.273567 # # OK global.pac_instructions_not_nop_generic
1565 16:29:30.273676 # ok 3 global.pac_instructions_not_nop_generic
1566 16:29:30.273765 # # RUN global.single_thread_different_keys ...
1567 16:29:30.274074 # # OK global.single_thread_different_keys
1568 16:29:30.274197 # ok 4 global.single_thread_different_keys
1569 16:29:30.274494 # # RUN global.exec_changed_keys ...
1570 16:29:30.274621 # # OK global.exec_changed_keys
1571 16:29:30.274717 # ok 5 global.exec_changed_keys
1572 16:29:30.274824 # # RUN global.context_switch_keep_keys ...
1573 16:29:30.275129 # # OK global.context_switch_keep_keys
1574 16:29:30.275249 # ok 6 global.context_switch_keep_keys
1575 16:29:30.277670 # # RUN global.context_switch_keep_keys_generic ...
1576 16:29:30.277981 # # OK global.context_switch_keep_keys_generic
1577 16:29:30.278306 # ok 7 global.context_switch_keep_keys_generic
1578 16:29:30.278409 # # PASSED: 7 / 7 tests passed.
1579 16:29:30.278515 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1580 16:29:30.290283 ok 28 selftests: arm64: pac
1581 16:29:30.360459 # selftests: arm64: fp-stress
1582 16:29:51.560151 # TAP version 13
1583 16:29:51.560573 # 1..27
1584 16:29:51.560901 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1585 16:29:51.561034 # # Will run for 10s
1586 16:29:51.561539 # # Started FPSIMD-0-0
1587 16:29:51.561655 # # Started SVE-VL-256-0
1588 16:29:51.561778 # # Started SVE-VL-240-0
1589 16:29:51.562295 # # Started SVE-VL-224-0
1590 16:29:51.562808 # # Started SVE-VL-208-0
1591 16:29:51.562909 # # Started SVE-VL-192-0
1592 16:29:51.563209 # # Started SVE-VL-176-0
1593 16:29:51.563531 # # Started SVE-VL-160-0
1594 16:29:51.563632 # # Started SVE-VL-144-0
1595 16:29:51.563924 # # Started SVE-VL-128-0
1596 16:29:51.564230 # # Started SVE-VL-112-0
1597 16:29:51.564521 # # Started SVE-VL-96-0
1598 16:29:51.564834 # # Started SVE-VL-80-0
1599 16:29:51.569234 # # Started SVE-VL-64-0
1600 16:29:51.569669 # # Started SVE-VL-48-0
1601 16:29:51.569789 # # Started SVE-VL-32-0
1602 16:29:51.569905 # # Started SVE-VL-16-0
1603 16:29:51.570048 # # Started SSVE-VL-256-0
1604 16:29:51.570167 # # Started ZA-VL-256-0
1605 16:29:51.570298 # # Started SSVE-VL-128-0
1606 16:29:51.570436 # # Started ZA-VL-128-0
1607 16:29:51.592403 # # Started SSVE-VL-64-0
1608 16:29:51.592662 # # Started ZA-VL-64-0
1609 16:29:51.592775 # # Started SSVE-VL-32-0
1610 16:29:51.592882 # # Started ZA-VL-32-0
1611 16:29:51.593239 # # Started SSVE-VL-16-0
1612 16:29:51.593355 # # Started ZA-VL-16-0
1613 16:29:51.593464 # # FPSIMD-0-0: Vector length: 128 bits
1614 16:29:51.593566 # # FPSIMD-0-0: PID: 907
1615 16:29:51.593666 # # SVE-VL-224-0: Vector length: 1792 bits
1616 16:29:51.593774 # # SVE-VL-224-0: PID: 910
1617 16:29:51.593909 # # SVE-VL-192-0: Vector length: 1536 bits
1618 16:29:51.594020 # # SVE-VL-192-0: PID: 912
1619 16:29:51.594128 # # SVE-VL-128-0: Vector length: 1024 bits
1620 16:29:51.594237 # # SVE-VL-128-0: PID: 916
1621 16:29:51.594343 # # SVE-VL-240-0: Vector length: 1920 bits
1622 16:29:51.594469 # # SVE-VL-240-0: PID: 909
1623 16:29:51.594570 # # SVE-VL-96-0: Vector length: 768 bits
1624 16:29:51.594674 # # SVE-VL-96-0: PID: 918
1625 16:29:51.594782 # # SVE-VL-144-0: Vector length: 1152 bits
1626 16:29:51.594855 # # SVE-VL-144-0: PID: 915
1627 16:29:51.594918 # # SVE-VL-208-0: Vector length: 1664 bits
1628 16:29:51.594979 # # SVE-VL-208-0: PID: 911
1629 16:29:51.608142 # # SVE-VL-160-0: Vector length: 1280 bits
1630 16:29:51.608647 # # SVE-VL-160-0: PID: 914
1631 16:29:51.609167 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1632 16:29:51.609566 # # SSVE-VL-128-0: PID: 926
1633 16:29:51.610319 # # SVE-VL-112-0: Vector length: 896 bits
1634 16:29:51.610422 # # SVE-VL-112-0: PID: 917
1635 16:29:51.610759 # # SVE-VL-64-0: Vector length: 512 bits
1636 16:29:51.610865 # # SVE-VL-64-0: PID: 920
1637 16:29:51.610949 # # SVE-VL-16-0: Vector length: 128 bits
1638 16:29:51.652459 # # SVE-VL-16-0: PID: 923
1639 16:29:51.652716 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1640 16:29:51.653068 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1641 16:29:51.653170 # # SVE-VL-48-0: Vector length: 384 bits
1642 16:29:51.653256 # # SVE-VL-48-0: PID: 921
1643 16:29:51.653335 # # ZA-VL-256-0: PID: 925
1644 16:29:51.653621 # # SVE-VL-32-0: Vector length: 256 bits
1645 16:29:51.653730 # # SVE-VL-32-0: PID: 922
1646 16:29:51.653815 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1647 16:29:51.653909 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1648 16:29:51.654391 # # SSVE-VL-256-0: PID: 924
1649 16:29:51.654692 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1650 16:29:51.654819 # # SSVE-VL-16-0: PID: 932
1651 16:29:51.689032 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1652 16:29:51.689511 # # SSVE-VL-32-0: PID: 930
1653 16:29:51.690055 # # ZA-VL-64-0: PID: 929
1654 16:29:51.690587 # # ZA-VL-128-0: PID: 927
1655 16:29:51.717656 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1656 16:29:51.718098 # # SVE-VL-80-0: Vector length: 640 bits
1657 16:29:51.718423 # # SVE-VL-80-0: PID: 919
1658 16:29:51.718551 # # SSVE-VL-64-0: PID: 928
1659 16:29:51.749110 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1660 16:29:51.749348 # # ZA-VL-32-0: PID: 931
1661 16:29:51.749660 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1662 16:29:51.749766 # # ZA-VL-16-0: PID: 933
1663 16:29:51.749869 # # SVE-VL-256-0: Vector length: 2048 bits
1664 16:29:51.749980 # # SVE-VL-256-0: PID: 908
1665 16:29:51.750104 # # SVE-VL-176-0: Vector length: 1408 bits
1666 16:29:51.750197 # # SVE-VL-176-0: PID: 913
1667 16:29:51.750296 # # Finishing up...
1668 16:29:51.750382 # ok 1 FPSIMD-0-0
1669 16:29:51.750465 # ok 2 SVE-VL-256-0
1670 16:29:51.750560 # ok 3 SVE-VL-240-0
1671 16:29:51.750642 # ok 4 SVE-VL-224-0
1672 16:29:51.750722 # ok 5 SVE-VL-208-0
1673 16:29:51.768818 # ok 6 SVE-VL-192-0
1674 16:29:51.769280 # ok 7 SVE-VL-176-0
1675 16:29:51.769388 # ok 8 SVE-VL-160-0
1676 16:29:51.769505 # ok 9 SVE-VL-144-0
1677 16:29:51.769610 # ok 10 SVE-VL-128-0
1678 16:29:51.769719 # ok 11 SVE-VL-112-0
1679 16:29:51.769819 # ok 12 SVE-VL-96-0
1680 16:29:51.769919 # ok 13 SVE-VL-80-0
1681 16:29:51.770002 # ok 14 SVE-VL-64-0
1682 16:29:51.770080 # ok 15 SVE-VL-48-0
1683 16:29:51.770165 # ok 16 SVE-VL-32-0
1684 16:29:51.770258 # ok 17 SVE-VL-16-0
1685 16:29:51.770337 # ok 18 SSVE-VL-256-0
1686 16:29:51.770413 # ok 19 ZA-VL-256-0
1687 16:29:51.770502 # ok 20 SSVE-VL-128-0
1688 16:29:51.770583 # ok 21 ZA-VL-128-0
1689 16:29:51.770670 # ok 22 SSVE-VL-64-0
1690 16:29:51.770801 # ok 23 ZA-VL-64-0
1691 16:29:51.770898 # ok 24 SSVE-VL-32-0
1692 16:29:51.770980 # ok 25 ZA-VL-32-0
1693 16:29:51.771060 # ok 26 SSVE-VL-16-0
1694 16:29:51.800425 # ok 27 ZA-VL-16-0
1695 16:29:51.800943 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1181, signals=9
1696 16:29:51.801325 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=591, signals=9
1697 16:29:51.801682 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=969, signals=9
1698 16:29:51.801812 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=8889, signals=9
1699 16:29:51.802776 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1384, signals=9
1700 16:29:51.802887 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=8573, signals=9
1701 16:29:51.803198 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2168, signals=9
1702 16:29:51.828623 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=4759, signals=9
1703 16:29:51.830083 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=11328, signals=9
1704 16:29:51.830411 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3531, signals=9
1705 16:29:51.890277 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6362, signals=9
1706 16:29:51.890758 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=3631, signals=9
1707 16:29:51.899262 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=4310, signals=9
1708 16:29:51.899683 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=4191, signals=9
1709 16:29:51.899988 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=5241, signals=9
1710 16:29:51.900506 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2776, signals=9
1711 16:29:51.900623 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=3827, signals=9
1712 16:29:51.900749 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=2824, signals=9
1713 16:29:51.901060 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=12669, signals=9
1714 16:29:51.901161 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=3068, signals=9
1715 16:29:51.901451 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2476, signals=9
1716 16:29:51.901772 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=997, signals=7
1717 16:29:51.902724 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=98, signals=1
1718 16:29:51.902830 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=5760, signals=9
1719 16:29:51.902922 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=3599, signals=9
1720 16:29:51.903002 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=6866, signals=9
1721 16:29:51.907612 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=221, signals=9
1722 16:29:51.908370 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1723 16:29:51.908497 ok 29 selftests: arm64: fp-stress
1724 16:29:52.241514 # selftests: arm64: sve-ptrace
1725 16:29:52.524965 # TAP version 13
1726 16:29:52.525199 # 1..4104
1727 16:29:52.525285 # # Parent is 950, child is 951
1728 16:29:52.525575 # ok 1 SVE FPSIMD set via SVE: 0
1729 16:29:52.525902 # ok 2 SVE get_fpsimd() gave same state
1730 16:29:52.526214 # ok 3 SVE SVE_PT_VL_INHERIT set
1731 16:29:52.526311 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1732 16:29:52.526406 # ok 5 Set SVE VL 16
1733 16:29:52.526487 # ok 6 Set and get SVE data for VL 16
1734 16:29:52.526577 # ok 7 Set and get FPSIMD data for SVE VL 16
1735 16:29:52.526669 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1736 16:29:52.526749 # ok 9 Set SVE VL 32
1737 16:29:52.527023 # ok 10 Set and get SVE data for VL 32
1738 16:29:52.527123 # ok 11 Set and get FPSIMD data for SVE VL 32
1739 16:29:52.527219 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1740 16:29:52.533424 # ok 13 Set SVE VL 48
1741 16:29:52.533933 # ok 14 Set and get SVE data for VL 48
1742 16:29:52.534037 # ok 15 Set and get FPSIMD data for SVE VL 48
1743 16:29:52.534580 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1744 16:29:52.535152 # ok 17 Set SVE VL 64
1745 16:29:52.535259 # ok 18 Set and get SVE data for VL 64
1746 16:29:52.535343 # ok 19 Set and get FPSIMD data for SVE VL 64
1747 16:29:52.535425 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1748 16:29:52.535506 # ok 21 Set SVE VL 80
1749 16:29:52.535586 # ok 22 Set and get SVE data for VL 80
1750 16:29:52.539531 # ok 23 Set and get FPSIMD data for SVE VL 80
1751 16:29:52.539635 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1752 16:29:52.539721 # ok 25 Set SVE VL 96
1753 16:29:52.539802 # ok 26 Set and get SVE data for VL 96
1754 16:29:52.539884 # ok 27 Set and get FPSIMD data for SVE VL 96
1755 16:29:52.539964 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1756 16:29:52.540045 # ok 29 Set SVE VL 112
1757 16:29:52.540126 # ok 30 Set and get SVE data for VL 112
1758 16:29:52.540208 # ok 31 Set and get FPSIMD data for SVE VL 112
1759 16:29:52.540288 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1760 16:29:52.540369 # ok 33 Set SVE VL 128
1761 16:29:52.540450 # ok 34 Set and get SVE data for VL 128
1762 16:29:52.540530 # ok 35 Set and get FPSIMD data for SVE VL 128
1763 16:29:52.540611 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1764 16:29:52.540696 # ok 37 Set SVE VL 144
1765 16:29:52.540776 # ok 38 Set and get SVE data for VL 144
1766 16:29:52.540857 # ok 39 Set and get FPSIMD data for SVE VL 144
1767 16:29:52.540937 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1768 16:29:52.541017 # ok 41 Set SVE VL 160
1769 16:29:52.541097 # ok 42 Set and get SVE data for VL 160
1770 16:29:52.541177 # ok 43 Set and get FPSIMD data for SVE VL 160
1771 16:29:52.541257 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1772 16:29:52.541337 # ok 45 Set SVE VL 176
1773 16:29:52.541416 # ok 46 Set and get SVE data for VL 176
1774 16:29:52.541496 # ok 47 Set and get FPSIMD data for SVE VL 176
1775 16:29:52.541576 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1776 16:29:52.541660 # ok 49 Set SVE VL 192
1777 16:29:52.547154 # ok 50 Set and get SVE data for VL 192
1778 16:29:52.548612 # ok 51 Set and get FPSIMD data for SVE VL 192
1779 16:29:52.548945 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1780 16:29:52.549047 # ok 53 Set SVE VL 208
1781 16:29:52.549330 # ok 54 Set and get SVE data for VL 208
1782 16:29:52.549435 # ok 55 Set and get FPSIMD data for SVE VL 208
1783 16:29:52.549530 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1784 16:29:52.549841 # ok 57 Set SVE VL 224
1785 16:29:52.549946 # ok 58 Set and get SVE data for VL 224
1786 16:29:52.550239 # ok 59 Set and get FPSIMD data for SVE VL 224
1787 16:29:52.550343 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1788 16:29:52.550428 # ok 61 Set SVE VL 240
1789 16:29:52.550520 # ok 62 Set and get SVE data for VL 240
1790 16:29:52.550790 # ok 63 Set and get FPSIMD data for SVE VL 240
1791 16:29:52.550909 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1792 16:29:52.551018 # ok 65 Set SVE VL 256
1793 16:29:52.551114 # ok 66 Set and get SVE data for VL 256
1794 16:29:52.551206 # ok 67 Set and get FPSIMD data for SVE VL 256
1795 16:29:52.551275 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1796 16:29:52.558799 # ok 69 Set SVE VL 272
1797 16:29:52.559178 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1798 16:29:52.559924 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1799 16:29:52.560246 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1800 16:29:52.560556 # ok 73 Set SVE VL 288
1801 16:29:52.561067 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1802 16:29:52.561574 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1803 16:29:52.561900 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1804 16:29:52.562011 # ok 77 Set SVE VL 304
1805 16:29:52.562517 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1806 16:29:52.562639 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1807 16:29:52.563135 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1808 16:29:52.567015 # ok 81 Set SVE VL 320
1809 16:29:52.567821 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1810 16:29:52.568114 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1811 16:29:52.568245 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1812 16:29:52.568554 # ok 85 Set SVE VL 336
1813 16:29:52.568868 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1814 16:29:52.569041 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1815 16:29:52.569327 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1816 16:29:52.569428 # ok 89 Set SVE VL 352
1817 16:29:52.569512 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1818 16:29:52.570292 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1819 16:29:52.570394 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1820 16:29:52.570478 # ok 93 Set SVE VL 368
1821 16:29:52.570557 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1822 16:29:52.570821 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1823 16:29:52.570922 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1824 16:29:52.571004 # ok 97 Set SVE VL 384
1825 16:29:52.571082 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1826 16:29:52.571175 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1827 16:29:52.571453 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1828 16:29:52.578832 # ok 101 Set SVE VL 400
1829 16:29:52.580781 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1830 16:29:52.581139 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1831 16:29:52.581804 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1832 16:29:52.581906 # ok 105 Set SVE VL 416
1833 16:29:52.581990 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1834 16:29:52.582070 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1835 16:29:52.582150 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1836 16:29:52.582228 # ok 109 Set SVE VL 432
1837 16:29:52.582623 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1838 16:29:52.582725 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1839 16:29:52.582806 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1840 16:29:52.582885 # ok 113 Set SVE VL 448
1841 16:29:52.582964 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1842 16:29:52.583046 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1843 16:29:52.583325 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1844 16:29:52.583426 # ok 117 Set SVE VL 464
1845 16:29:52.583507 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1846 16:29:52.583586 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1847 16:29:52.583663 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1848 16:29:52.583741 # ok 121 Set SVE VL 480
1849 16:29:52.592196 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1850 16:29:52.592367 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1851 16:29:52.592817 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1852 16:29:52.593135 # ok 125 Set SVE VL 496
1853 16:29:52.593473 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1854 16:29:52.593589 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1855 16:29:52.594143 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1856 16:29:52.594528 # ok 129 Set SVE VL 512
1857 16:29:52.594630 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1858 16:29:52.594741 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1859 16:29:52.594869 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1860 16:29:52.594994 # ok 133 Set SVE VL 528
1861 16:29:52.599963 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1862 16:29:52.600333 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1863 16:29:52.600886 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1864 16:29:52.601005 # ok 137 Set SVE VL 544
1865 16:29:52.601517 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1866 16:29:52.601871 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1867 16:29:52.601998 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1868 16:29:52.602313 # ok 141 Set SVE VL 560
1869 16:29:52.602424 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1870 16:29:52.602516 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1871 16:29:52.602623 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1872 16:29:52.602716 # ok 145 Set SVE VL 576
1873 16:29:52.602825 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1874 16:29:52.602916 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1875 16:29:52.603253 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1876 16:29:52.603371 # ok 149 Set SVE VL 592
1877 16:29:52.603507 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1878 16:29:52.603620 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1879 16:29:52.603752 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1880 16:29:52.603866 # ok 153 Set SVE VL 608
1881 16:29:52.604001 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1882 16:29:52.604114 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1883 16:29:52.604246 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1884 16:29:52.604352 # ok 157 Set SVE VL 624
1885 16:29:52.604710 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1886 16:29:52.604844 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1887 16:29:52.604944 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1888 16:29:52.605054 # ok 161 Set SVE VL 640
1889 16:29:52.605172 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1890 16:29:52.605287 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1891 16:29:52.605383 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1892 16:29:52.605474 # ok 165 Set SVE VL 656
1893 16:29:52.605590 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1894 16:29:52.605708 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1895 16:29:52.605822 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1896 16:29:52.605913 # ok 169 Set SVE VL 672
1897 16:29:52.606019 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1898 16:29:52.606126 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1899 16:29:52.606485 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1900 16:29:52.606588 # ok 173 Set SVE VL 688
1901 16:29:52.606676 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1902 16:29:52.606779 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1903 16:29:52.606868 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1904 16:29:52.606956 # ok 177 Set SVE VL 704
1905 16:29:52.607286 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1906 16:29:52.607417 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1907 16:29:52.607503 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1908 16:29:52.607571 # ok 181 Set SVE VL 720
1909 16:29:52.621951 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1910 16:29:52.622323 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1911 16:29:52.622622 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1912 16:29:52.622732 # ok 185 Set SVE VL 736
1913 16:29:52.623033 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1914 16:29:52.623141 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1915 16:29:52.623777 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1916 16:29:52.624105 # ok 189 Set SVE VL 752
1917 16:29:52.624531 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1918 16:29:52.624640 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1919 16:29:52.624925 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1920 16:29:52.625037 # ok 193 Set SVE VL 768
1921 16:29:52.625144 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1922 16:29:52.625479 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1923 16:29:52.625616 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1924 16:29:52.625747 # ok 197 Set SVE VL 784
1925 16:29:52.626189 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1926 16:29:52.626309 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1927 16:29:52.626813 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1928 16:29:52.626935 # ok 201 Set SVE VL 800
1929 16:29:52.627042 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1930 16:29:52.627403 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1931 16:29:52.639027 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1932 16:29:52.640203 # ok 205 Set SVE VL 816
1933 16:29:52.640801 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1934 16:29:52.641140 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1935 16:29:52.641251 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1936 16:29:52.641379 # ok 209 Set SVE VL 832
1937 16:29:52.641733 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1938 16:29:52.642053 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1939 16:29:52.642155 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1940 16:29:52.642238 # ok 213 Set SVE VL 848
1941 16:29:52.642568 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1942 16:29:52.642670 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1943 16:29:52.642751 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1944 16:29:52.643032 # ok 217 Set SVE VL 864
1945 16:29:52.643141 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1946 16:29:52.643233 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1947 16:29:52.643311 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1948 16:29:52.643403 # ok 221 Set SVE VL 880
1949 16:29:52.651523 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1950 16:29:52.651935 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1951 16:29:52.652048 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1952 16:29:52.652155 # ok 225 Set SVE VL 896
1953 16:29:52.652279 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1954 16:29:52.652415 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1955 16:29:52.652744 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1956 16:29:52.652863 # ok 229 Set SVE VL 912
1957 16:29:52.653150 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1958 16:29:52.653463 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1959 16:29:52.653563 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1960 16:29:52.653885 # ok 233 Set SVE VL 928
1961 16:29:52.653987 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1962 16:29:52.654273 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1963 16:29:52.654374 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1964 16:29:52.654457 # ok 237 Set SVE VL 944
1965 16:29:52.654548 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1966 16:29:52.654863 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1967 16:29:52.654964 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1968 16:29:52.655044 # ok 241 Set SVE VL 960
1969 16:29:52.655134 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1970 16:29:52.655225 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1971 16:29:52.659737 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1972 16:29:52.660217 # ok 245 Set SVE VL 976
1973 16:29:52.660334 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1974 16:29:52.660463 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1975 16:29:52.660594 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1976 16:29:52.660727 # ok 249 Set SVE VL 992
1977 16:29:52.660971 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1978 16:29:52.661086 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1979 16:29:52.661239 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1980 16:29:52.661345 # ok 253 Set SVE VL 1008
1981 16:29:52.661469 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1982 16:29:52.661576 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1983 16:29:52.661726 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1984 16:29:52.661848 # ok 257 Set SVE VL 1024
1985 16:29:52.661967 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1986 16:29:52.662267 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1987 16:29:52.662368 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1988 16:29:52.662462 # ok 261 Set SVE VL 1040
1989 16:29:52.662542 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1990 16:29:52.662619 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1991 16:29:52.662709 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1992 16:29:52.662990 # ok 265 Set SVE VL 1056
1993 16:29:52.663097 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1994 16:29:52.663190 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1995 16:29:52.663261 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1996 16:29:52.667812 # ok 269 Set SVE VL 1072
1997 16:29:52.668158 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
1998 16:29:52.668268 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
1999 16:29:52.668359 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2000 16:29:52.668458 # ok 273 Set SVE VL 1088
2001 16:29:52.668578 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2002 16:29:52.668715 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2003 16:29:52.669047 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2004 16:29:52.669394 # ok 277 Set SVE VL 1104
2005 16:29:52.669514 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2006 16:29:52.669656 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2007 16:29:52.669789 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2008 16:29:52.669928 # ok 281 Set SVE VL 1120
2009 16:29:52.670258 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2010 16:29:52.670577 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2011 16:29:52.670707 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2012 16:29:52.670840 # ok 285 Set SVE VL 1136
2013 16:29:52.670962 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2014 16:29:52.675679 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2015 16:29:52.676225 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2016 16:29:52.676576 # ok 289 Set SVE VL 1152
2017 16:29:52.677137 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2018 16:29:52.677440 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2019 16:29:52.677560 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2020 16:29:52.687941 # ok 293 Set SVE VL 1168
2021 16:29:52.688158 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2022 16:29:52.688655 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2023 16:29:52.688776 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2024 16:29:52.689267 # ok 297 Set SVE VL 1184
2025 16:29:52.689387 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2026 16:29:52.689891 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2027 16:29:52.690173 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2028 16:29:52.690277 # ok 301 Set SVE VL 1200
2029 16:29:52.690625 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2030 16:29:52.690727 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2031 16:29:52.690809 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2032 16:29:52.690888 # ok 305 Set SVE VL 1216
2033 16:29:52.690981 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2034 16:29:52.691061 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2035 16:29:52.691151 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2036 16:29:52.691242 # ok 309 Set SVE VL 1232
2037 16:29:52.695888 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2038 16:29:52.696223 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2039 16:29:52.696324 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2040 16:29:52.696419 # ok 313 Set SVE VL 1248
2041 16:29:52.696498 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2042 16:29:52.696836 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2043 16:29:52.696958 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2044 16:29:52.697068 # ok 317 Set SVE VL 1264
2045 16:29:52.697387 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2046 16:29:52.697511 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2047 16:29:52.697625 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2048 16:29:52.697752 # ok 321 Set SVE VL 1280
2049 16:29:52.697884 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2050 16:29:52.698216 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2051 16:29:52.698373 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2052 16:29:52.698493 # ok 325 Set SVE VL 1296
2053 16:29:52.698628 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2054 16:29:52.698754 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2055 16:29:52.699106 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2056 16:29:52.699211 # ok 329 Set SVE VL 1312
2057 16:29:52.703776 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2058 16:29:52.704352 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2059 16:29:52.704483 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2060 16:29:52.704815 # ok 333 Set SVE VL 1328
2061 16:29:52.705191 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2062 16:29:52.705556 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2063 16:29:52.705873 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2064 16:29:52.705988 # ok 337 Set SVE VL 1344
2065 16:29:52.706102 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2066 16:29:52.706223 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2067 16:29:52.706539 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2068 16:29:52.706655 # ok 341 Set SVE VL 1360
2069 16:29:52.706781 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2070 16:29:52.706885 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2071 16:29:52.707002 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2072 16:29:52.707301 # ok 345 Set SVE VL 1376
2073 16:29:52.707404 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2074 16:29:52.711852 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2075 16:29:52.712226 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2076 16:29:52.712362 # ok 349 Set SVE VL 1392
2077 16:29:52.712850 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2078 16:29:52.713418 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2079 16:29:52.713551 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2080 16:29:52.713944 # ok 353 Set SVE VL 1408
2081 16:29:52.714051 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2082 16:29:52.714349 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2083 16:29:52.714451 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2084 16:29:52.714550 # ok 357 Set SVE VL 1424
2085 16:29:52.714629 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2086 16:29:52.714719 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2087 16:29:52.715048 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2088 16:29:52.715179 # ok 361 Set SVE VL 1440
2089 16:29:52.719754 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2090 16:29:52.720295 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2091 16:29:52.720444 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2092 16:29:52.720571 # ok 365 Set SVE VL 1456
2093 16:29:52.721125 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2094 16:29:52.721492 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2095 16:29:52.721628 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2096 16:29:52.721961 # ok 369 Set SVE VL 1472
2097 16:29:52.722071 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2098 16:29:52.722193 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2099 16:29:52.722299 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2100 16:29:52.722411 # ok 373 Set SVE VL 1488
2101 16:29:52.722540 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2102 16:29:52.722650 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2103 16:29:52.722779 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2104 16:29:52.722882 # ok 377 Set SVE VL 1504
2105 16:29:52.723017 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2106 16:29:52.723134 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2107 16:29:52.723264 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2108 16:29:52.723375 # ok 381 Set SVE VL 1520
2109 16:29:52.723501 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2110 16:29:52.723632 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2111 16:29:52.723756 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2112 16:29:52.723885 # ok 385 Set SVE VL 1536
2113 16:29:52.724014 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2114 16:29:52.724142 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2115 16:29:52.724680 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2116 16:29:52.724801 # ok 389 Set SVE VL 1552
2117 16:29:52.724908 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2118 16:29:52.725012 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2119 16:29:52.725141 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2120 16:29:52.725249 # ok 393 Set SVE VL 1568
2121 16:29:52.725355 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2122 16:29:52.725460 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2123 16:29:52.725595 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2124 16:29:52.725711 # ok 397 Set SVE VL 1584
2125 16:29:52.725822 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2126 16:29:52.725945 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2127 16:29:52.726052 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2128 16:29:52.726158 # ok 401 Set SVE VL 1600
2129 16:29:52.726271 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2130 16:29:52.726373 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2131 16:29:52.726505 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2132 16:29:52.726616 # ok 405 Set SVE VL 1616
2133 16:29:52.726729 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2134 16:29:52.726845 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2135 16:29:52.726959 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2136 16:29:52.727068 # ok 409 Set SVE VL 1632
2137 16:29:52.727171 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2138 16:29:52.727293 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2139 16:29:52.727412 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2140 16:29:52.727532 # ok 413 Set SVE VL 1648
2141 16:29:52.727656 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2142 16:29:52.727784 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2143 16:29:52.727916 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2144 16:29:52.728029 # ok 417 Set SVE VL 1664
2145 16:29:52.728149 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2146 16:29:52.728267 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2147 16:29:52.728392 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2148 16:29:52.729134 # ok 421 Set SVE VL 1680
2149 16:29:52.729251 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2150 16:29:52.729352 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2151 16:29:52.729453 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2152 16:29:52.729565 # ok 425 Set SVE VL 1696
2153 16:29:52.729693 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2154 16:29:52.729797 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2155 16:29:52.729899 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2156 16:29:52.730007 # ok 429 Set SVE VL 1712
2157 16:29:52.730130 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2158 16:29:52.730221 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2159 16:29:52.730303 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2160 16:29:52.730440 # ok 433 Set SVE VL 1728
2161 16:29:52.730538 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2162 16:29:52.730637 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2163 16:29:52.730752 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2164 16:29:52.730867 # ok 437 Set SVE VL 1744
2165 16:29:52.731002 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2166 16:29:52.731110 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2167 16:29:52.731241 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2168 16:29:52.731346 # ok 441 Set SVE VL 1760
2169 16:29:52.731479 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2170 16:29:52.731587 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2171 16:29:52.731717 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2172 16:29:52.731829 # ok 445 Set SVE VL 1776
2173 16:29:52.731953 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2174 16:29:52.732078 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2175 16:29:52.732380 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2176 16:29:52.732493 # ok 449 Set SVE VL 1792
2177 16:29:52.747687 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2178 16:29:52.748055 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2179 16:29:52.748157 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2180 16:29:52.748245 # ok 453 Set SVE VL 1808
2181 16:29:52.748328 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2182 16:29:52.748966 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2183 16:29:52.749174 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2184 16:29:52.749285 # ok 457 Set SVE VL 1824
2185 16:29:52.749390 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2186 16:29:52.749473 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2187 16:29:52.749555 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2188 16:29:52.749638 # ok 461 Set SVE VL 1840
2189 16:29:52.749921 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2190 16:29:52.750040 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2191 16:29:52.750166 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2192 16:29:52.750277 # ok 465 Set SVE VL 1856
2193 16:29:52.750372 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2194 16:29:52.750458 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2195 16:29:52.750543 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2196 16:29:52.750626 # ok 469 Set SVE VL 1872
2197 16:29:52.750726 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2198 16:29:52.751018 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2199 16:29:52.751125 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2200 16:29:52.751201 # ok 473 Set SVE VL 1888
2201 16:29:52.751270 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2202 16:29:52.751369 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2203 16:29:52.751466 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2204 16:29:52.751571 # ok 477 Set SVE VL 1904
2205 16:29:52.751668 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2206 16:29:52.751765 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2207 16:29:52.758799 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2208 16:29:52.758979 # ok 481 Set SVE VL 1920
2209 16:29:52.759122 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2210 16:29:52.759213 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2211 16:29:52.759496 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2212 16:29:52.759870 # ok 485 Set SVE VL 1936
2213 16:29:52.760286 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2214 16:29:52.760390 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2215 16:29:52.760473 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2216 16:29:52.760566 # ok 489 Set SVE VL 1952
2217 16:29:52.760646 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2218 16:29:52.760736 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2219 16:29:52.761017 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2220 16:29:52.761121 # ok 493 Set SVE VL 1968
2221 16:29:52.761430 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2222 16:29:52.761534 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2223 16:29:52.761628 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2224 16:29:52.761716 # ok 497 Set SVE VL 1984
2225 16:29:52.761794 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2226 16:29:52.761884 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2227 16:29:52.762223 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2228 16:29:52.762444 # ok 501 Set SVE VL 2000
2229 16:29:52.762529 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2230 16:29:52.762623 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2231 16:29:52.762704 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2232 16:29:52.762781 # ok 505 Set SVE VL 2016
2233 16:29:52.762871 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2234 16:29:52.762950 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2235 16:29:52.763273 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2236 16:29:52.763373 # ok 509 Set SVE VL 2032
2237 16:29:52.763454 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2238 16:29:52.763533 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2239 16:29:52.772037 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2240 16:29:52.772183 # ok 513 Set SVE VL 2048
2241 16:29:52.772291 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2242 16:29:52.772396 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2243 16:29:52.772525 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2244 16:29:52.772650 # ok 517 Set SVE VL 2064
2245 16:29:52.772758 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2246 16:29:52.772887 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2247 16:29:52.773016 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2248 16:29:52.773144 # ok 521 Set SVE VL 2080
2249 16:29:52.773269 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2250 16:29:52.773638 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2251 16:29:52.773762 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2252 16:29:52.773892 # ok 525 Set SVE VL 2096
2253 16:29:52.774001 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2254 16:29:52.774124 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2255 16:29:52.774230 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2256 16:29:52.774335 # ok 529 Set SVE VL 2112
2257 16:29:52.774460 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2258 16:29:52.774590 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2259 16:29:52.774927 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2260 16:29:52.775039 # ok 533 Set SVE VL 2128
2261 16:29:52.775148 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2262 16:29:52.775248 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2263 16:29:52.775322 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2264 16:29:52.778305 # ok 537 Set SVE VL 2144
2265 16:29:52.778534 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2266 16:29:52.778867 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2267 16:29:52.778983 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2268 16:29:52.779096 # ok 541 Set SVE VL 2160
2269 16:29:52.779189 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2270 16:29:52.779285 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2271 16:29:52.779353 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2272 16:29:52.779611 # ok 545 Set SVE VL 2176
2273 16:29:52.779933 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2274 16:29:52.780040 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2275 16:29:52.780340 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2276 16:29:52.780442 # ok 549 Set SVE VL 2192
2277 16:29:52.780523 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2278 16:29:52.780811 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2279 16:29:52.780943 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2280 16:29:52.781027 # ok 553 Set SVE VL 2208
2281 16:29:52.781127 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2282 16:29:52.781386 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2283 16:29:52.781488 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2284 16:29:52.781570 # ok 557 Set SVE VL 2224
2285 16:29:52.781655 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2286 16:29:52.781959 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2287 16:29:52.782059 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2288 16:29:52.782141 # ok 561 Set SVE VL 2240
2289 16:29:52.782218 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2290 16:29:52.782736 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2291 16:29:52.782838 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2292 16:29:52.782919 # ok 565 Set SVE VL 2256
2293 16:29:52.782996 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2294 16:29:52.783072 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2295 16:29:52.783150 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2296 16:29:52.783236 # ok 569 Set SVE VL 2272
2297 16:29:52.783328 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2298 16:29:52.783429 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2299 16:29:52.783529 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2300 16:29:52.783649 # ok 573 Set SVE VL 2288
2301 16:29:52.783743 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2302 16:29:52.783837 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2303 16:29:52.783930 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2304 16:29:52.784328 # ok 577 Set SVE VL 2304
2305 16:29:52.784601 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2306 16:29:52.784748 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2307 16:29:52.785040 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2308 16:29:52.785156 # ok 581 Set SVE VL 2320
2309 16:29:52.785246 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2310 16:29:52.785326 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2311 16:29:52.785407 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2312 16:29:52.785489 # ok 585 Set SVE VL 2336
2313 16:29:52.785869 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2314 16:29:52.785982 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2315 16:29:52.786076 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2316 16:29:52.786189 # ok 589 Set SVE VL 2352
2317 16:29:52.786297 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2318 16:29:52.786397 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2319 16:29:52.786521 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2320 16:29:52.786627 # ok 593 Set SVE VL 2368
2321 16:29:52.786734 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2322 16:29:52.786826 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2323 16:29:52.787277 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2324 16:29:52.787385 # ok 597 Set SVE VL 2384
2325 16:29:52.787493 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2326 16:29:52.787603 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2327 16:29:52.787713 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2328 16:29:52.787818 # ok 601 Set SVE VL 2400
2329 16:29:52.787917 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2330 16:29:52.788272 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2331 16:29:52.788390 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2332 16:29:52.788502 # ok 605 Set SVE VL 2416
2333 16:29:52.788609 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2334 16:29:52.788717 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2335 16:29:52.788829 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2336 16:29:52.788958 # ok 609 Set SVE VL 2432
2337 16:29:52.789073 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2338 16:29:52.789181 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2339 16:29:52.789288 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2340 16:29:52.789389 # ok 613 Set SVE VL 2448
2341 16:29:52.789512 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2342 16:29:52.789641 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2343 16:29:52.789758 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2344 16:29:52.789874 # ok 617 Set SVE VL 2464
2345 16:29:52.789986 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2346 16:29:52.790098 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2347 16:29:52.790222 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2348 16:29:52.790333 # ok 621 Set SVE VL 2480
2349 16:29:52.790429 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2350 16:29:52.790520 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2351 16:29:52.790815 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2352 16:29:52.790922 # ok 625 Set SVE VL 2496
2353 16:29:52.791222 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2354 16:29:52.791333 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2355 16:29:52.791446 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2356 16:29:52.791544 # ok 629 Set SVE VL 2512
2357 16:29:52.791651 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2358 16:29:52.791786 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2359 16:29:52.791901 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2360 16:29:52.792002 # ok 633 Set SVE VL 2528
2361 16:29:52.792127 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2362 16:29:52.792243 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2363 16:29:52.792377 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2364 16:29:52.792492 # ok 637 Set SVE VL 2544
2365 16:29:52.792602 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2366 16:29:52.792735 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2367 16:29:52.792840 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2368 16:29:52.792951 # ok 641 Set SVE VL 2560
2369 16:29:52.793451 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2370 16:29:52.793569 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2371 16:29:52.793683 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2372 16:29:52.793795 # ok 645 Set SVE VL 2576
2373 16:29:52.793924 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2374 16:29:52.794036 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2375 16:29:52.794144 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2376 16:29:52.794252 # ok 649 Set SVE VL 2592
2377 16:29:52.794364 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2378 16:29:52.794475 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2379 16:29:52.794580 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2380 16:29:52.794695 # ok 653 Set SVE VL 2608
2381 16:29:52.794795 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2382 16:29:52.794925 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2383 16:29:52.795017 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2384 16:29:52.795128 # ok 657 Set SVE VL 2624
2385 16:29:52.795237 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2386 16:29:52.795323 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2387 16:29:52.795796 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2388 16:29:52.796125 # ok 661 Set SVE VL 2640
2389 16:29:52.796285 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2390 16:29:52.796458 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2391 16:29:52.796596 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2392 16:29:52.796682 # ok 665 Set SVE VL 2656
2393 16:29:52.796758 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2394 16:29:52.808091 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2395 16:29:52.808293 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2396 16:29:52.808421 # ok 669 Set SVE VL 2672
2397 16:29:52.808533 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2398 16:29:52.808661 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2399 16:29:52.808764 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2400 16:29:52.808875 # ok 673 Set SVE VL 2688
2401 16:29:52.809000 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2402 16:29:52.809105 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2403 16:29:52.809233 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2404 16:29:52.809342 # ok 677 Set SVE VL 2704
2405 16:29:52.809471 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2406 16:29:52.809595 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2407 16:29:52.810743 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2408 16:29:52.811141 # ok 681 Set SVE VL 2720
2409 16:29:52.811391 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2410 16:29:52.811487 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2411 16:29:52.811584 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2412 16:29:52.811673 # ok 685 Set SVE VL 2736
2413 16:29:52.811755 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2414 16:29:52.812121 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2415 16:29:52.812229 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2416 16:29:52.812333 # ok 689 Set SVE VL 2752
2417 16:29:52.812447 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2418 16:29:52.812553 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2419 16:29:52.812676 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2420 16:29:52.812765 # ok 693 Set SVE VL 2768
2421 16:29:52.812848 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2422 16:29:52.812928 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2423 16:29:52.813008 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2424 16:29:52.813105 # ok 697 Set SVE VL 2784
2425 16:29:52.814342 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2426 16:29:52.814885 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2427 16:29:52.814993 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2428 16:29:52.815098 # ok 701 Set SVE VL 2800
2429 16:29:52.815195 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2430 16:29:52.815299 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2431 16:29:52.815390 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2432 16:29:52.815473 # ok 705 Set SVE VL 2816
2433 16:29:52.815555 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2434 16:29:52.815636 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2435 16:29:52.815719 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2436 16:29:52.815801 # ok 709 Set SVE VL 2832
2437 16:29:52.815882 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2438 16:29:52.815964 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2439 16:29:52.816046 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2440 16:29:52.816127 # ok 713 Set SVE VL 2848
2441 16:29:52.816227 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2442 16:29:52.816313 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2443 16:29:52.816396 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2444 16:29:52.816478 # ok 717 Set SVE VL 2864
2445 16:29:52.816560 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2446 16:29:52.818032 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2447 16:29:52.818158 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2448 16:29:52.818319 # ok 721 Set SVE VL 2880
2449 16:29:52.818424 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2450 16:29:52.818514 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2451 16:29:52.818621 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2452 16:29:52.818721 # ok 725 Set SVE VL 2896
2453 16:29:52.818827 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2454 16:29:52.818935 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2455 16:29:52.819040 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2456 16:29:52.819149 # ok 729 Set SVE VL 2912
2457 16:29:52.819261 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2458 16:29:52.819356 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2459 16:29:52.819460 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2460 16:29:52.819568 # ok 733 Set SVE VL 2928
2461 16:29:52.819679 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2462 16:29:52.819777 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2463 16:29:52.819867 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2464 16:29:52.819954 # ok 737 Set SVE VL 2944
2465 16:29:52.820042 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2466 16:29:52.820149 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2467 16:29:52.820245 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2468 16:29:52.820373 # ok 741 Set SVE VL 2960
2469 16:29:52.820483 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2470 16:29:52.820579 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2471 16:29:52.820669 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2472 16:29:52.820758 # ok 745 Set SVE VL 2976
2473 16:29:52.820860 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2474 16:29:52.820966 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2475 16:29:52.821067 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2476 16:29:52.821162 # ok 749 Set SVE VL 2992
2477 16:29:52.821276 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2478 16:29:52.821381 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2479 16:29:52.821488 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2480 16:29:52.821590 # ok 753 Set SVE VL 3008
2481 16:29:52.822267 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2482 16:29:52.822377 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2483 16:29:52.822476 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2484 16:29:52.822582 # ok 757 Set SVE VL 3024
2485 16:29:52.822688 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2486 16:29:52.822805 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2487 16:29:52.822910 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2488 16:29:52.823017 # ok 761 Set SVE VL 3040
2489 16:29:52.823128 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2490 16:29:52.823454 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2491 16:29:52.823568 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2492 16:29:52.823664 # ok 765 Set SVE VL 3056
2493 16:29:52.823754 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2494 16:29:52.823865 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2495 16:29:52.823973 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2496 16:29:52.824090 # ok 769 Set SVE VL 3072
2497 16:29:52.824198 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2498 16:29:52.824303 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2499 16:29:52.824398 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2500 16:29:52.824496 # ok 773 Set SVE VL 3088
2501 16:29:52.824602 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2502 16:29:52.824711 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2503 16:29:52.824825 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2504 16:29:52.824926 # ok 777 Set SVE VL 3104
2505 16:29:52.825017 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2506 16:29:52.825108 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2507 16:29:52.825214 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2508 16:29:52.825313 # ok 781 Set SVE VL 3120
2509 16:29:52.825417 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2510 16:29:52.825555 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2511 16:29:52.825661 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2512 16:29:52.825769 # ok 785 Set SVE VL 3136
2513 16:29:52.825865 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2514 16:29:52.825955 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2515 16:29:52.826042 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2516 16:29:52.826130 # ok 789 Set SVE VL 3152
2517 16:29:52.826217 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2518 16:29:52.826307 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2519 16:29:52.826395 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2520 16:29:52.826485 # ok 793 Set SVE VL 3168
2521 16:29:52.826575 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2522 16:29:52.826661 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2523 16:29:52.826748 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2524 16:29:52.826834 # ok 797 Set SVE VL 3184
2525 16:29:52.826923 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2526 16:29:52.827031 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2527 16:29:52.827164 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2528 16:29:52.827264 # ok 801 Set SVE VL 3200
2529 16:29:52.827369 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2530 16:29:52.827476 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2531 16:29:52.827570 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2532 16:29:52.827661 # ok 805 Set SVE VL 3216
2533 16:29:52.827766 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2534 16:29:52.828721 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2535 16:29:52.828828 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2536 16:29:52.828929 # ok 809 Set SVE VL 3232
2537 16:29:52.829042 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2538 16:29:52.829151 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2539 16:29:52.829250 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2540 16:29:52.829355 # ok 813 Set SVE VL 3248
2541 16:29:52.829450 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2542 16:29:52.829557 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2543 16:29:52.829664 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2544 16:29:52.829765 # ok 817 Set SVE VL 3264
2545 16:29:52.829873 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2546 16:29:52.829980 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2547 16:29:52.830086 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2548 16:29:52.830185 # ok 821 Set SVE VL 3280
2549 16:29:52.830296 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2550 16:29:52.830424 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2551 16:29:52.830533 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2552 16:29:52.830643 # ok 825 Set SVE VL 3296
2553 16:29:52.830752 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2554 16:29:52.830855 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2555 16:29:52.830961 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2556 16:29:52.831069 # ok 829 Set SVE VL 3312
2557 16:29:52.831181 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2558 16:29:52.831292 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2559 16:29:52.831402 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2560 16:29:52.831510 # ok 833 Set SVE VL 3328
2561 16:29:52.831609 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2562 16:29:52.831698 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2563 16:29:52.831780 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2564 16:29:52.831890 # ok 837 Set SVE VL 3344
2565 16:29:52.831982 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2566 16:29:52.832074 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2567 16:29:52.832178 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2568 16:29:52.832274 # ok 841 Set SVE VL 3360
2569 16:29:52.832364 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2570 16:29:52.832454 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2571 16:29:52.832542 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2572 16:29:52.832630 # ok 845 Set SVE VL 3376
2573 16:29:52.832717 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2574 16:29:52.832781 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2575 16:29:52.832856 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2576 16:29:52.832920 # ok 849 Set SVE VL 3392
2577 16:29:52.833180 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2578 16:29:52.833292 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2579 16:29:52.833391 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2580 16:29:52.833487 # ok 853 Set SVE VL 3408
2581 16:29:52.833584 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2582 16:29:52.843248 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2583 16:29:52.843428 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2584 16:29:52.843545 # ok 857 Set SVE VL 3424
2585 16:29:52.844106 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2586 16:29:52.844816 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2587 16:29:52.845313 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2588 16:29:52.846164 # ok 861 Set SVE VL 3440
2589 16:29:52.846641 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2590 16:29:52.847158 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2591 16:29:52.847307 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2592 16:29:52.847411 # ok 865 Set SVE VL 3456
2593 16:29:52.847497 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2594 16:29:52.847580 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2595 16:29:52.847661 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2596 16:29:52.847742 # ok 869 Set SVE VL 3472
2597 16:29:52.847823 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2598 16:29:52.847904 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2599 16:29:52.847986 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2600 16:29:52.848068 # ok 873 Set SVE VL 3488
2601 16:29:52.848149 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2602 16:29:52.848231 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2603 16:29:52.848318 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2604 16:29:52.848522 # ok 877 Set SVE VL 3504
2605 16:29:52.849188 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2606 16:29:52.849674 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2607 16:29:52.850255 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2608 16:29:52.850821 # ok 881 Set SVE VL 3520
2609 16:29:52.851201 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2610 16:29:52.851319 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2611 16:29:52.851418 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2612 16:29:52.851502 # ok 885 Set SVE VL 3536
2613 16:29:52.851583 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2614 16:29:52.851665 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2615 16:29:52.851755 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2616 16:29:52.852039 # ok 889 Set SVE VL 3552
2617 16:29:52.852525 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2618 16:29:52.852938 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2619 16:29:52.853616 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2620 16:29:52.854129 # ok 893 Set SVE VL 3568
2621 16:29:52.854854 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2622 16:29:52.854982 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2623 16:29:52.855088 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2624 16:29:52.855217 # ok 897 Set SVE VL 3584
2625 16:29:52.855327 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2626 16:29:52.855435 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2627 16:29:52.855543 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2628 16:29:52.855648 # ok 901 Set SVE VL 3600
2629 16:29:52.855765 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2630 16:29:52.856096 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2631 16:29:52.856206 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2632 16:29:52.856304 # ok 905 Set SVE VL 3616
2633 16:29:52.856412 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2634 16:29:52.856520 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2635 16:29:52.856616 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2636 16:29:52.856719 # ok 909 Set SVE VL 3632
2637 16:29:52.856824 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2638 16:29:52.856932 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2639 16:29:52.857038 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2640 16:29:52.857153 # ok 913 Set SVE VL 3648
2641 16:29:52.857268 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2642 16:29:52.857370 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2643 16:29:52.857485 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2644 16:29:52.857599 # ok 917 Set SVE VL 3664
2645 16:29:52.857708 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2646 16:29:52.857806 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2647 16:29:52.857919 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2648 16:29:52.858031 # ok 921 Set SVE VL 3680
2649 16:29:52.858131 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2650 16:29:52.858236 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2651 16:29:52.858354 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2652 16:29:52.858471 # ok 925 Set SVE VL 3696
2653 16:29:52.858588 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2654 16:29:52.858721 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2655 16:29:52.858835 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2656 16:29:52.858938 # ok 929 Set SVE VL 3712
2657 16:29:52.859048 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2658 16:29:52.859160 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2659 16:29:52.859288 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2660 16:29:52.859402 # ok 933 Set SVE VL 3728
2661 16:29:52.859502 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2662 16:29:52.859605 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2663 16:29:52.859700 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2664 16:29:52.859791 # ok 937 Set SVE VL 3744
2665 16:29:52.859907 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2666 16:29:52.860022 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2667 16:29:52.860126 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2668 16:29:52.860224 # ok 941 Set SVE VL 3760
2669 16:29:52.860313 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2670 16:29:52.860399 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2671 16:29:52.860490 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2672 16:29:52.860578 # ok 945 Set SVE VL 3776
2673 16:29:52.860665 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2674 16:29:52.861080 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2675 16:29:52.861188 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2676 16:29:52.861279 # ok 949 Set SVE VL 3792
2677 16:29:52.861367 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2678 16:29:52.861454 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2679 16:29:52.861543 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2680 16:29:52.861628 # ok 953 Set SVE VL 3808
2681 16:29:52.861722 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2682 16:29:52.861824 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2683 16:29:52.861943 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2684 16:29:52.862040 # ok 957 Set SVE VL 3824
2685 16:29:52.862145 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2686 16:29:52.862238 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2687 16:29:52.862319 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2688 16:29:52.862397 # ok 961 Set SVE VL 3840
2689 16:29:52.862482 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2690 16:29:52.862564 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2691 16:29:52.862646 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2692 16:29:52.862746 # ok 965 Set SVE VL 3856
2693 16:29:52.862859 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2694 16:29:52.862965 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2695 16:29:52.863085 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2696 16:29:52.863199 # ok 969 Set SVE VL 3872
2697 16:29:52.863320 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2698 16:29:52.863430 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2699 16:29:52.863543 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2700 16:29:52.863661 # ok 973 Set SVE VL 3888
2701 16:29:52.863769 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2702 16:29:52.863877 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2703 16:29:52.863984 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2704 16:29:52.864088 # ok 977 Set SVE VL 3904
2705 16:29:52.864197 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2706 16:29:52.864300 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2707 16:29:52.864419 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2708 16:29:52.864534 # ok 981 Set SVE VL 3920
2709 16:29:52.864635 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2710 16:29:52.864735 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2711 16:29:52.864848 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2712 16:29:52.864976 # ok 985 Set SVE VL 3936
2713 16:29:52.865074 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2714 16:29:52.865188 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2715 16:29:52.865299 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2716 16:29:52.865414 # ok 989 Set SVE VL 3952
2717 16:29:52.865526 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2718 16:29:52.865953 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2719 16:29:52.866063 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2720 16:29:52.866181 # ok 993 Set SVE VL 3968
2721 16:29:52.866293 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2722 16:29:52.866401 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2723 16:29:52.866609 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2724 16:29:52.866852 # ok 997 Set SVE VL 3984
2725 16:29:52.867120 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2726 16:29:52.867230 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2727 16:29:52.867331 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2728 16:29:52.867647 # ok 1001 Set SVE VL 4000
2729 16:29:52.867757 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2730 16:29:52.867868 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2731 16:29:52.867977 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2732 16:29:52.868089 # ok 1005 Set SVE VL 4016
2733 16:29:52.868197 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2734 16:29:52.868333 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2735 16:29:52.868445 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2736 16:29:52.868550 # ok 1009 Set SVE VL 4032
2737 16:29:52.868670 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2738 16:29:52.868784 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2739 16:29:52.868887 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2740 16:29:52.869002 # ok 1013 Set SVE VL 4048
2741 16:29:52.869109 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2742 16:29:52.869212 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2743 16:29:52.869309 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2744 16:29:52.869400 # ok 1017 Set SVE VL 4064
2745 16:29:52.869511 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2746 16:29:52.869626 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2747 16:29:52.869736 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2748 16:29:52.869834 # ok 1021 Set SVE VL 4080
2749 16:29:52.869918 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2750 16:29:52.870016 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2751 16:29:52.870149 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2752 16:29:52.870254 # ok 1025 Set SVE VL 4096
2753 16:29:52.870344 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2754 16:29:52.870413 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2755 16:29:52.870475 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2756 16:29:52.870535 # ok 1029 Set SVE VL 4112
2757 16:29:52.870594 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2758 16:29:52.870654 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2759 16:29:52.870713 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2760 16:29:52.870772 # ok 1033 Set SVE VL 4128
2761 16:29:52.871017 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2762 16:29:52.871084 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2763 16:29:52.871144 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2764 16:29:52.871206 # ok 1037 Set SVE VL 4144
2765 16:29:52.871266 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2766 16:29:52.871326 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2767 16:29:52.871386 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2768 16:29:52.880408 # ok 1041 Set SVE VL 4160
2769 16:29:52.881217 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2770 16:29:52.881591 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2771 16:29:52.882105 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2772 16:29:52.882462 # ok 1045 Set SVE VL 4176
2773 16:29:52.882581 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2774 16:29:52.882763 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2775 16:29:52.882921 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2776 16:29:52.883019 # ok 1049 Set SVE VL 4192
2777 16:29:52.883123 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2778 16:29:52.883229 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2779 16:29:52.883341 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2780 16:29:52.883434 # ok 1053 Set SVE VL 4208
2781 16:29:52.883506 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2782 16:29:52.883568 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2783 16:29:52.883629 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2784 16:29:52.883706 # ok 1057 Set SVE VL 4224
2785 16:29:52.883789 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2786 16:29:52.883886 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2787 16:29:52.883992 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2788 16:29:52.884103 # ok 1061 Set SVE VL 4240
2789 16:29:52.884210 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2790 16:29:52.884331 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2791 16:29:52.884432 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2792 16:29:52.884537 # ok 1065 Set SVE VL 4256
2793 16:29:52.884662 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2794 16:29:52.884767 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2795 16:29:52.884892 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2796 16:29:52.884997 # ok 1069 Set SVE VL 4272
2797 16:29:52.885121 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2798 16:29:52.885231 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2799 16:29:52.885353 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2800 16:29:52.885456 # ok 1073 Set SVE VL 4288
2801 16:29:52.885575 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2802 16:29:52.885704 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2803 16:29:52.885832 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2804 16:29:52.885951 # ok 1077 Set SVE VL 4304
2805 16:29:52.886050 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2806 16:29:52.886174 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2807 16:29:52.886298 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2808 16:29:52.889756 # ok 1081 Set SVE VL 4320
2809 16:29:52.889877 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2810 16:29:52.889996 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2811 16:29:52.890108 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2812 16:29:52.890210 # ok 1085 Set SVE VL 4336
2813 16:29:52.890314 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2814 16:29:52.890427 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2815 16:29:52.890537 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2816 16:29:52.890649 # ok 1089 Set SVE VL 4352
2817 16:29:52.890757 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2818 16:29:52.890866 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2819 16:29:52.890971 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2820 16:29:52.891075 # ok 1093 Set SVE VL 4368
2821 16:29:52.891195 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2822 16:29:52.891309 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2823 16:29:52.891423 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2824 16:29:52.891524 # ok 1097 Set SVE VL 4384
2825 16:29:52.891632 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2826 16:29:52.891740 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2827 16:29:52.891848 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2828 16:29:52.891949 # ok 1101 Set SVE VL 4400
2829 16:29:52.892043 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2830 16:29:52.892140 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2831 16:29:52.892240 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2832 16:29:52.892345 # ok 1105 Set SVE VL 4416
2833 16:29:52.892450 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2834 16:29:52.892557 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2835 16:29:52.893088 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2836 16:29:52.893202 # ok 1109 Set SVE VL 4432
2837 16:29:52.893301 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2838 16:29:52.893409 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2839 16:29:52.893523 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2840 16:29:52.893635 # ok 1113 Set SVE VL 4448
2841 16:29:52.893743 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2842 16:29:52.893846 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2843 16:29:52.893955 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2844 16:29:52.894059 # ok 1117 Set SVE VL 4464
2845 16:29:52.894166 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2846 16:29:52.894270 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2847 16:29:52.894374 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2848 16:29:52.894471 # ok 1121 Set SVE VL 4480
2849 16:29:52.894581 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2850 16:29:52.894679 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2851 16:29:52.894775 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2852 16:29:52.894881 # ok 1125 Set SVE VL 4496
2853 16:29:52.894973 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2854 16:29:52.895060 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2855 16:29:52.895163 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2856 16:29:52.895265 # ok 1129 Set SVE VL 4512
2857 16:29:52.895366 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2858 16:29:52.895462 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2859 16:29:52.895573 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2860 16:29:52.895684 # ok 1133 Set SVE VL 4528
2861 16:29:52.895793 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2862 16:29:52.895915 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2863 16:29:52.896025 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2864 16:29:52.896133 # ok 1137 Set SVE VL 4544
2865 16:29:52.896236 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2866 16:29:52.896345 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2867 16:29:52.896452 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2868 16:29:52.896562 # ok 1141 Set SVE VL 4560
2869 16:29:52.896671 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2870 16:29:52.896774 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2871 16:29:52.896875 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2872 16:29:52.896974 # ok 1145 Set SVE VL 4576
2873 16:29:52.897077 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2874 16:29:52.897186 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2875 16:29:52.897291 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2876 16:29:52.897393 # ok 1149 Set SVE VL 4592
2877 16:29:52.897497 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2878 16:29:52.897858 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2879 16:29:52.897967 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2880 16:29:52.898069 # ok 1153 Set SVE VL 4608
2881 16:29:52.898162 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2882 16:29:52.898267 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2883 16:29:52.898367 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2884 16:29:52.898467 # ok 1157 Set SVE VL 4624
2885 16:29:52.898570 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2886 16:29:52.898680 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2887 16:29:52.898781 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2888 16:29:52.898887 # ok 1161 Set SVE VL 4640
2889 16:29:52.898984 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2890 16:29:52.899073 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2891 16:29:52.899188 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2892 16:29:52.899291 # ok 1165 Set SVE VL 4656
2893 16:29:52.899372 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2894 16:29:52.899443 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2895 16:29:52.899504 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2896 16:29:52.899574 # ok 1169 Set SVE VL 4672
2897 16:29:52.899694 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2898 16:29:52.899793 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2899 16:29:52.899904 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2900 16:29:52.899998 # ok 1173 Set SVE VL 4688
2901 16:29:52.900103 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2902 16:29:52.900205 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2903 16:29:52.900310 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2904 16:29:52.900409 # ok 1177 Set SVE VL 4704
2905 16:29:52.900516 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2906 16:29:52.900624 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2907 16:29:52.900733 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2908 16:29:52.900832 # ok 1181 Set SVE VL 4720
2909 16:29:52.900950 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2910 16:29:52.901050 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2911 16:29:52.901155 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2912 16:29:52.901261 # ok 1185 Set SVE VL 4736
2913 16:29:52.901358 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2914 16:29:52.901462 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2915 16:29:52.901565 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2916 16:29:52.901687 # ok 1189 Set SVE VL 4752
2917 16:29:52.901787 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2918 16:29:52.901915 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2919 16:29:52.902020 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2920 16:29:52.902127 # ok 1193 Set SVE VL 4768
2921 16:29:52.902509 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2922 16:29:52.902750 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2923 16:29:52.902900 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2924 16:29:52.903030 # ok 1197 Set SVE VL 4784
2925 16:29:52.903167 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2926 16:29:52.903281 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2927 16:29:52.903375 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2928 16:29:52.903463 # ok 1201 Set SVE VL 4800
2929 16:29:52.903566 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2930 16:29:52.903683 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2931 16:29:52.903781 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2932 16:29:52.903884 # ok 1205 Set SVE VL 4816
2933 16:29:52.903988 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2934 16:29:52.904090 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2935 16:29:52.904203 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2936 16:29:52.904308 # ok 1209 Set SVE VL 4832
2937 16:29:52.904407 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2938 16:29:52.904531 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2939 16:29:52.904631 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2940 16:29:52.904741 # ok 1213 Set SVE VL 4848
2941 16:29:52.904865 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2942 16:29:52.904965 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2943 16:29:52.905287 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2944 16:29:52.905394 # ok 1217 Set SVE VL 4864
2945 16:29:52.905477 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2946 16:29:52.905556 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2947 16:29:52.905634 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2948 16:29:52.905720 # ok 1221 Set SVE VL 4880
2949 16:29:52.905797 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2950 16:29:52.906085 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2951 16:29:52.918691 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2952 16:29:52.918930 # ok 1225 Set SVE VL 4896
2953 16:29:52.919085 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2954 16:29:52.919219 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2955 16:29:52.919316 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2956 16:29:52.919423 # ok 1229 Set SVE VL 4912
2957 16:29:52.922178 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2958 16:29:52.923181 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2959 16:29:52.923320 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2960 16:29:52.923423 # ok 1233 Set SVE VL 4928
2961 16:29:52.923514 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2962 16:29:52.923600 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2963 16:29:52.923688 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2964 16:29:52.923820 # ok 1237 Set SVE VL 4944
2965 16:29:52.924694 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2966 16:29:52.925086 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2967 16:29:52.925307 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2968 16:29:52.925609 # ok 1241 Set SVE VL 4960
2969 16:29:52.925732 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2970 16:29:52.925851 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2971 16:29:52.925939 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2972 16:29:52.926021 # ok 1245 Set SVE VL 4976
2973 16:29:52.926369 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2974 16:29:52.926488 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2975 16:29:52.926578 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2976 16:29:52.926656 # ok 1249 Set SVE VL 4992
2977 16:29:52.926732 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2978 16:29:52.927007 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2979 16:29:52.927133 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2980 16:29:52.927233 # ok 1253 Set SVE VL 5008
2981 16:29:52.927314 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2982 16:29:52.927391 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2983 16:29:52.927468 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2984 16:29:52.927560 # ok 1257 Set SVE VL 5024
2985 16:29:52.928329 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2986 16:29:52.928800 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2987 16:29:52.928901 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2988 16:29:52.928983 # ok 1261 Set SVE VL 5040
2989 16:29:52.929061 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2990 16:29:52.929152 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2991 16:29:52.929499 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2992 16:29:52.929599 # ok 1265 Set SVE VL 5056
2993 16:29:52.929688 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2994 16:29:52.929766 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2995 16:29:52.929857 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2996 16:29:52.930051 # ok 1269 Set SVE VL 5072
2997 16:29:52.930253 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
2998 16:29:52.930412 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
2999 16:29:52.930819 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3000 16:29:52.930954 # ok 1273 Set SVE VL 5088
3001 16:29:52.931114 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3002 16:29:52.931208 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3003 16:29:52.931287 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3004 16:29:52.931380 # ok 1277 Set SVE VL 5104
3005 16:29:52.931460 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3006 16:29:52.931538 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3007 16:29:52.931825 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3008 16:29:52.931926 # ok 1281 Set SVE VL 5120
3009 16:29:52.932006 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3010 16:29:52.932083 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3011 16:29:52.932175 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3012 16:29:52.932254 # ok 1285 Set SVE VL 5136
3013 16:29:52.932506 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3014 16:29:52.932612 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3015 16:29:52.932709 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3016 16:29:52.932790 # ok 1289 Set SVE VL 5152
3017 16:29:52.932881 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3018 16:29:52.932959 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3019 16:29:52.933049 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3020 16:29:52.933128 # ok 1293 Set SVE VL 5168
3021 16:29:52.933217 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3022 16:29:52.933654 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3023 16:29:52.933757 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3024 16:29:52.933837 # ok 1297 Set SVE VL 5184
3025 16:29:52.933914 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3026 16:29:52.934004 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3027 16:29:52.934095 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3028 16:29:52.934417 # ok 1301 Set SVE VL 5200
3029 16:29:52.934544 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3030 16:29:52.934626 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3031 16:29:52.934719 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3032 16:29:52.934798 # ok 1305 Set SVE VL 5216
3033 16:29:52.934876 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3034 16:29:52.934967 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3035 16:29:52.935047 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3036 16:29:52.935137 # ok 1309 Set SVE VL 5232
3037 16:29:52.935423 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3038 16:29:52.935863 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3039 16:29:52.935964 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3040 16:29:52.936045 # ok 1313 Set SVE VL 5248
3041 16:29:52.936137 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3042 16:29:52.936230 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3043 16:29:52.936310 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3044 16:29:52.936400 # ok 1317 Set SVE VL 5264
3045 16:29:52.936491 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3046 16:29:52.936833 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3047 16:29:52.936935 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3048 16:29:52.937016 # ok 1321 Set SVE VL 5280
3049 16:29:52.937107 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3050 16:29:52.937187 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3051 16:29:52.937277 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3052 16:29:52.937368 # ok 1325 Set SVE VL 5296
3053 16:29:52.937722 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3054 16:29:52.937844 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3055 16:29:52.937934 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3056 16:29:52.938028 # ok 1329 Set SVE VL 5312
3057 16:29:52.938109 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3058 16:29:52.938199 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3059 16:29:52.938290 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3060 16:29:52.938600 # ok 1333 Set SVE VL 5328
3061 16:29:52.938739 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3062 16:29:52.938926 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3063 16:29:52.939014 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3064 16:29:52.939290 # ok 1337 Set SVE VL 5344
3065 16:29:52.939476 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3066 16:29:52.939739 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3067 16:29:52.939844 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3068 16:29:52.940024 # ok 1341 Set SVE VL 5360
3069 16:29:52.940109 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3070 16:29:52.940203 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3071 16:29:52.940283 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3072 16:29:52.940360 # ok 1345 Set SVE VL 5376
3073 16:29:52.940437 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3074 16:29:52.940527 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3075 16:29:52.940605 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3076 16:29:52.940694 # ok 1349 Set SVE VL 5392
3077 16:29:52.941018 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3078 16:29:52.941118 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3079 16:29:52.941199 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3080 16:29:52.941276 # ok 1353 Set SVE VL 5408
3081 16:29:52.941367 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3082 16:29:52.941445 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3083 16:29:52.941535 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3084 16:29:52.941812 # ok 1357 Set SVE VL 5424
3085 16:29:52.941912 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3086 16:29:52.942007 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3087 16:29:52.942086 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3088 16:29:52.942175 # ok 1361 Set SVE VL 5440
3089 16:29:52.942370 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3090 16:29:52.942685 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3091 16:29:52.942785 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3092 16:29:52.942865 # ok 1365 Set SVE VL 5456
3093 16:29:52.942955 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3094 16:29:52.943237 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3095 16:29:52.943360 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3096 16:29:52.943446 # ok 1369 Set SVE VL 5472
3097 16:29:52.943541 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3098 16:29:52.943622 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3099 16:29:52.943965 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3100 16:29:52.944130 # ok 1373 Set SVE VL 5488
3101 16:29:52.944298 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3102 16:29:52.944385 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3103 16:29:52.944464 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3104 16:29:52.944555 # ok 1377 Set SVE VL 5504
3105 16:29:52.944633 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3106 16:29:52.944724 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3107 16:29:52.944814 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3108 16:29:52.944906 # ok 1381 Set SVE VL 5520
3109 16:29:52.944984 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3110 16:29:52.945269 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3111 16:29:52.945368 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3112 16:29:52.945448 # ok 1385 Set SVE VL 5536
3113 16:29:52.945745 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3114 16:29:52.945991 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3115 16:29:52.946148 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3116 16:29:52.946254 # ok 1389 Set SVE VL 5552
3117 16:29:52.946335 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3118 16:29:52.946413 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3119 16:29:52.946613 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3120 16:29:52.946699 # ok 1393 Set SVE VL 5568
3121 16:29:52.946791 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3122 16:29:52.946870 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3123 16:29:52.946947 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3124 16:29:52.947037 # ok 1397 Set SVE VL 5584
3125 16:29:52.947116 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3126 16:29:52.947207 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3127 16:29:52.947286 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3128 16:29:52.947606 # ok 1401 Set SVE VL 5600
3129 16:29:52.947704 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3130 16:29:52.947992 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3131 16:29:52.948192 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3132 16:29:52.948294 # ok 1405 Set SVE VL 5616
3133 16:29:52.948393 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3134 16:29:52.993110 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3135 16:29:52.993328 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3136 16:29:52.993411 # ok 1409 Set SVE VL 5632
3137 16:29:52.993505 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3138 16:29:52.993594 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3139 16:29:52.993700 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3140 16:29:52.993781 # ok 1413 Set SVE VL 5648
3141 16:29:52.993877 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3142 16:29:52.994060 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3143 16:29:52.994162 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3144 16:29:52.994565 # ok 1417 Set SVE VL 5664
3145 16:29:52.994665 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3146 16:29:52.994747 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3147 16:29:52.994826 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3148 16:29:52.995148 # ok 1421 Set SVE VL 5680
3149 16:29:52.995247 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3150 16:29:52.995330 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3151 16:29:52.995409 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3152 16:29:52.995501 # ok 1425 Set SVE VL 5696
3153 16:29:53.000863 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3154 16:29:53.001260 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3155 16:29:53.001364 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3156 16:29:53.001483 # ok 1429 Set SVE VL 5712
3157 16:29:53.001614 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3158 16:29:53.001732 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3159 16:29:53.001853 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3160 16:29:53.001958 # ok 1433 Set SVE VL 5728
3161 16:29:53.002076 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3162 16:29:53.002202 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3163 16:29:53.002310 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3164 16:29:53.002440 # ok 1437 Set SVE VL 5744
3165 16:29:53.002543 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3166 16:29:53.002669 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3167 16:29:53.002797 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3168 16:29:53.002932 # ok 1441 Set SVE VL 5760
3169 16:29:53.003023 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3170 16:29:53.004449 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3171 16:29:53.004566 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3172 16:29:53.006085 # ok 1445 Set SVE VL 5776
3173 16:29:53.006220 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3174 16:29:53.006320 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3175 16:29:53.006429 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3176 16:29:53.006826 # ok 1449 Set SVE VL 5792
3177 16:29:53.007353 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3178 16:29:53.007456 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3179 16:29:53.007548 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3180 16:29:53.007635 # ok 1453 Set SVE VL 5808
3181 16:29:53.007719 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3182 16:29:53.007801 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3183 16:29:53.007878 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3184 16:29:53.023336 # ok 1457 Set SVE VL 5824
3185 16:29:53.023795 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3186 16:29:53.025156 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3187 16:29:53.025574 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3188 16:29:53.025693 # ok 1461 Set SVE VL 5840
3189 16:29:53.025816 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3190 16:29:53.026178 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3191 16:29:53.026302 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3192 16:29:53.026411 # ok 1465 Set SVE VL 5856
3193 16:29:53.026526 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3194 16:29:53.026636 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3195 16:29:53.026770 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3196 16:29:53.026883 # ok 1469 Set SVE VL 5872
3197 16:29:53.026992 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3198 16:29:53.027116 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3199 16:29:53.027220 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3200 16:29:53.027327 # ok 1473 Set SVE VL 5888
3201 16:29:53.027426 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3202 16:29:53.036972 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3203 16:29:53.037432 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3204 16:29:53.037549 # ok 1477 Set SVE VL 5904
3205 16:29:53.037671 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3206 16:29:53.037778 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3207 16:29:53.037911 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3208 16:29:53.038025 # ok 1481 Set SVE VL 5920
3209 16:29:53.038138 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3210 16:29:53.038248 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3211 16:29:53.038384 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3212 16:29:53.038495 # ok 1485 Set SVE VL 5936
3213 16:29:53.038607 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3214 16:29:53.038744 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3215 16:29:53.038853 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3216 16:29:53.038963 # ok 1489 Set SVE VL 5952
3217 16:29:53.039095 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3218 16:29:53.039207 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3219 16:29:53.039333 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3220 16:29:53.039428 # ok 1493 Set SVE VL 5968
3221 16:29:53.042296 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3222 16:29:53.042726 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3223 16:29:53.042845 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3224 16:29:53.042964 # ok 1497 Set SVE VL 5984
3225 16:29:53.043089 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3226 16:29:53.043207 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3227 16:29:53.043363 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3228 16:29:53.043497 # ok 1501 Set SVE VL 6000
3229 16:29:53.043610 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3230 16:29:53.049680 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3231 16:29:53.050269 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3232 16:29:53.050391 # ok 1505 Set SVE VL 6016
3233 16:29:53.050484 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3234 16:29:53.050555 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3235 16:29:53.050630 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3236 16:29:53.050922 # ok 1509 Set SVE VL 6032
3237 16:29:53.051037 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3238 16:29:53.051150 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3239 16:29:53.051262 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3240 16:29:53.051350 # ok 1513 Set SVE VL 6048
3241 16:29:53.051431 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3242 16:29:53.051497 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3243 16:29:53.051558 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3244 16:29:53.053208 # ok 1517 Set SVE VL 6064
3245 16:29:53.053340 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3246 16:29:53.053450 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3247 16:29:53.053589 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3248 16:29:53.053706 # ok 1521 Set SVE VL 6080
3249 16:29:53.053838 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3250 16:29:53.053954 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3251 16:29:53.054080 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3252 16:29:53.054190 # ok 1525 Set SVE VL 6096
3253 16:29:53.054315 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3254 16:29:53.054439 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3255 16:29:53.054573 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3256 16:29:53.054689 # ok 1529 Set SVE VL 6112
3257 16:29:53.054816 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3258 16:29:53.054943 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3259 16:29:53.055071 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3260 16:29:53.055208 # ok 1533 Set SVE VL 6128
3261 16:29:53.055317 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3262 16:29:53.057067 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3263 16:29:53.057407 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3264 16:29:53.057514 # ok 1537 Set SVE VL 6144
3265 16:29:53.057604 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3266 16:29:53.057727 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3267 16:29:53.057817 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3268 16:29:53.058034 # ok 1541 Set SVE VL 6160
3269 16:29:53.058126 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3270 16:29:53.058230 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3271 16:29:53.058356 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3272 16:29:53.058484 # ok 1545 Set SVE VL 6176
3273 16:29:53.058611 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3274 16:29:53.058733 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3275 16:29:53.058862 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3276 16:29:53.058988 # ok 1549 Set SVE VL 6192
3277 16:29:53.059117 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3278 16:29:53.059248 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3279 16:29:53.060789 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3280 16:29:53.060902 # ok 1553 Set SVE VL 6208
3281 16:29:53.061224 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3282 16:29:53.061331 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3283 16:29:53.061764 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3284 16:29:53.061991 # ok 1557 Set SVE VL 6224
3285 16:29:53.062102 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3286 16:29:53.062197 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3287 16:29:53.062308 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3288 16:29:53.062400 # ok 1561 Set SVE VL 6240
3289 16:29:53.062706 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3290 16:29:53.062818 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3291 16:29:53.062912 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3292 16:29:53.063003 # ok 1565 Set SVE VL 6256
3293 16:29:53.063093 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3294 16:29:53.063187 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3295 16:29:53.063482 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3296 16:29:53.063592 # ok 1569 Set SVE VL 6272
3297 16:29:53.063684 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3298 16:29:53.063772 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3299 16:29:53.063859 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3300 16:29:53.063960 # ok 1573 Set SVE VL 6288
3301 16:29:53.065957 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3302 16:29:53.066077 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3303 16:29:53.066183 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3304 16:29:53.066297 # ok 1577 Set SVE VL 6304
3305 16:29:53.066402 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3306 16:29:53.066508 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3307 16:29:53.066601 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3308 16:29:53.066689 # ok 1581 Set SVE VL 6320
3309 16:29:53.066774 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3310 16:29:53.066860 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3311 16:29:53.066945 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3312 16:29:53.067234 # ok 1585 Set SVE VL 6336
3313 16:29:53.067339 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3314 16:29:53.067412 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3315 16:29:53.067475 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3316 16:29:53.067551 # ok 1589 Set SVE VL 6352
3317 16:29:53.072341 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3318 16:29:53.072978 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3319 16:29:53.073597 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3320 16:29:53.074382 # ok 1593 Set SVE VL 6368
3321 16:29:53.074491 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3322 16:29:53.074573 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3323 16:29:53.074669 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3324 16:29:53.074750 # ok 1597 Set SVE VL 6384
3325 16:29:53.074828 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3326 16:29:53.074904 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3327 16:29:53.074980 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3328 16:29:53.075057 # ok 1601 Set SVE VL 6400
3329 16:29:53.075135 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3330 16:29:53.075218 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3331 16:29:53.075294 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3332 16:29:53.075371 # ok 1605 Set SVE VL 6416
3333 16:29:53.075448 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3334 16:29:53.075542 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3335 16:29:53.075620 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3336 16:29:53.075702 # ok 1609 Set SVE VL 6432
3337 16:29:53.075779 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3338 16:29:53.075857 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3339 16:29:53.075949 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3340 16:29:53.076027 # ok 1613 Set SVE VL 6448
3341 16:29:53.076104 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3342 16:29:53.076181 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3343 16:29:53.076272 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3344 16:29:53.076351 # ok 1617 Set SVE VL 6464
3345 16:29:53.076439 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3346 16:29:53.076933 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3347 16:29:53.077037 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3348 16:29:53.077118 # ok 1621 Set SVE VL 6480
3349 16:29:53.077195 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3350 16:29:53.077287 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3351 16:29:53.077367 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3352 16:29:53.077644 # ok 1625 Set SVE VL 6496
3353 16:29:53.077755 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3354 16:29:53.077834 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3355 16:29:53.077915 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3356 16:29:53.077992 # ok 1629 Set SVE VL 6512
3357 16:29:53.078083 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3358 16:29:53.078378 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3359 16:29:53.078755 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3360 16:29:53.079100 # ok 1633 Set SVE VL 6528
3361 16:29:53.079213 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3362 16:29:53.079319 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3363 16:29:53.079400 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3364 16:29:53.079478 # ok 1637 Set SVE VL 6544
3365 16:29:53.079555 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3366 16:29:53.079632 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3367 16:29:53.079725 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3368 16:29:53.079805 # ok 1641 Set SVE VL 6560
3369 16:29:53.079882 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3370 16:29:53.079972 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3371 16:29:53.080292 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3372 16:29:53.080392 # ok 1645 Set SVE VL 6576
3373 16:29:53.080485 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3374 16:29:53.080771 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3375 16:29:53.081246 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3376 16:29:53.081623 # ok 1649 Set SVE VL 6592
3377 16:29:53.082125 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3378 16:29:53.082533 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3379 16:29:53.082935 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3380 16:29:53.083113 # ok 1653 Set SVE VL 6608
3381 16:29:53.083428 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3382 16:29:53.083607 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3383 16:29:53.083800 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3384 16:29:53.083972 # ok 1657 Set SVE VL 6624
3385 16:29:53.084226 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3386 16:29:53.084369 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3387 16:29:53.084599 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3388 16:29:53.084753 # ok 1661 Set SVE VL 6640
3389 16:29:53.084926 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3390 16:29:53.085126 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3391 16:29:53.085311 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3392 16:29:53.085510 # ok 1665 Set SVE VL 6656
3393 16:29:53.085691 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3394 16:29:53.085933 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3395 16:29:53.086065 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3396 16:29:53.086238 # ok 1669 Set SVE VL 6672
3397 16:29:53.086429 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3398 16:29:53.086606 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3399 16:29:53.086784 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3400 16:29:53.086979 # ok 1673 Set SVE VL 6688
3401 16:29:53.087161 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3402 16:29:53.087386 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3403 16:29:53.087565 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3404 16:29:53.087777 # ok 1677 Set SVE VL 6704
3405 16:29:53.087912 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3406 16:29:53.088102 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3407 16:29:53.088321 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3408 16:29:53.088463 # ok 1681 Set SVE VL 6720
3409 16:29:53.088644 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3410 16:29:53.088864 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3411 16:29:53.089012 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3412 16:29:53.089185 # ok 1685 Set SVE VL 6736
3413 16:29:53.089288 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3414 16:29:53.089389 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3415 16:29:53.089494 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3416 16:29:53.089594 # ok 1689 Set SVE VL 6752
3417 16:29:53.090087 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3418 16:29:53.090349 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3419 16:29:53.090716 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3420 16:29:53.091024 # ok 1693 Set SVE VL 6768
3421 16:29:53.091323 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3422 16:29:53.091597 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3423 16:29:53.091884 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3424 16:29:53.092172 # ok 1697 Set SVE VL 6784
3425 16:29:53.092379 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3426 16:29:53.092838 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3427 16:29:53.093079 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3428 16:29:53.093970 # ok 1701 Set SVE VL 6800
3429 16:29:53.095044 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3430 16:29:53.096140 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3431 16:29:53.097170 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3432 16:29:53.097841 # ok 1705 Set SVE VL 6816
3433 16:29:53.098101 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3434 16:29:53.098198 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3435 16:29:53.098278 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3436 16:29:53.098356 # ok 1709 Set SVE VL 6832
3437 16:29:53.098432 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3438 16:29:53.098509 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3439 16:29:53.098586 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3440 16:29:53.098663 # ok 1713 Set SVE VL 6848
3441 16:29:53.098739 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3442 16:29:53.098816 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3443 16:29:53.098892 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3444 16:29:53.098968 # ok 1717 Set SVE VL 6864
3445 16:29:53.099044 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3446 16:29:53.099121 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3447 16:29:53.099448 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3448 16:29:53.099533 # ok 1721 Set SVE VL 6880
3449 16:29:53.099610 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3450 16:29:53.099686 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3451 16:29:53.099783 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3452 16:29:53.099863 # ok 1725 Set SVE VL 6896
3453 16:29:53.099939 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3454 16:29:53.100016 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3455 16:29:53.100257 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3456 16:29:53.100344 # ok 1729 Set SVE VL 6912
3457 16:29:53.100422 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3458 16:29:53.100498 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3459 16:29:53.100575 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3460 16:29:53.100863 # ok 1733 Set SVE VL 6928
3461 16:29:53.100962 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3462 16:29:53.101043 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3463 16:29:53.101120 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3464 16:29:53.101198 # ok 1737 Set SVE VL 6944
3465 16:29:53.101274 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3466 16:29:53.101351 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3467 16:29:53.101428 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3468 16:29:53.101505 # ok 1741 Set SVE VL 6960
3469 16:29:53.101581 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3470 16:29:53.101666 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3471 16:29:53.101745 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3472 16:29:53.103344 # ok 1745 Set SVE VL 6976
3473 16:29:53.103435 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3474 16:29:53.103512 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3475 16:29:53.104243 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3476 16:29:53.105015 # ok 1749 Set SVE VL 6992
3477 16:29:53.105846 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3478 16:29:53.106507 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3479 16:29:53.107237 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3480 16:29:53.107417 # ok 1753 Set SVE VL 7008
3481 16:29:53.108219 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3482 16:29:53.109032 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3483 16:29:53.109729 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3484 16:29:53.110326 # ok 1757 Set SVE VL 7024
3485 16:29:53.110740 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3486 16:29:53.110986 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3487 16:29:53.111138 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3488 16:29:53.111458 # ok 1761 Set SVE VL 7040
3489 16:29:53.111631 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3490 16:29:53.111713 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3491 16:29:53.111791 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3492 16:29:53.111867 # ok 1765 Set SVE VL 7056
3493 16:29:53.111944 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3494 16:29:53.112021 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3495 16:29:53.112097 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3496 16:29:53.112174 # ok 1769 Set SVE VL 7072
3497 16:29:53.112251 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3498 16:29:53.112327 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3499 16:29:53.112404 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3500 16:29:53.112500 # ok 1773 Set SVE VL 7088
3501 16:29:53.112580 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3502 16:29:53.112657 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3503 16:29:53.113022 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3504 16:29:53.113142 # ok 1777 Set SVE VL 7104
3505 16:29:53.113223 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3506 16:29:53.113299 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3507 16:29:53.113376 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3508 16:29:53.113455 # ok 1781 Set SVE VL 7120
3509 16:29:53.113534 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3510 16:29:53.113614 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3511 16:29:53.113710 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3512 16:29:53.113810 # ok 1785 Set SVE VL 7136
3513 16:29:53.113897 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3514 16:29:53.113984 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3515 16:29:53.114068 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3516 16:29:53.114168 # ok 1789 Set SVE VL 7152
3517 16:29:53.114262 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3518 16:29:53.114355 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3519 16:29:53.114456 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3520 16:29:53.114558 # ok 1793 Set SVE VL 7168
3521 16:29:53.114660 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3522 16:29:53.114761 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3523 16:29:53.114877 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3524 16:29:53.114981 # ok 1797 Set SVE VL 7184
3525 16:29:53.115087 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3526 16:29:53.115720 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3527 16:29:53.115817 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3528 16:29:53.115900 # ok 1801 Set SVE VL 7200
3529 16:29:53.115981 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3530 16:29:53.116063 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3531 16:29:53.116143 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3532 16:29:53.116224 # ok 1805 Set SVE VL 7216
3533 16:29:53.116303 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3534 16:29:53.116384 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3535 16:29:53.116464 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3536 16:29:53.116545 # ok 1809 Set SVE VL 7232
3537 16:29:53.116626 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3538 16:29:53.116706 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3539 16:29:53.116787 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3540 16:29:53.116867 # ok 1813 Set SVE VL 7248
3541 16:29:53.116947 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3542 16:29:53.117027 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3543 16:29:53.117106 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3544 16:29:53.117186 # ok 1817 Set SVE VL 7264
3545 16:29:53.117266 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3546 16:29:53.117703 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3547 16:29:53.117806 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3548 16:29:53.117895 # ok 1821 Set SVE VL 7280
3549 16:29:53.118004 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3550 16:29:53.118096 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3551 16:29:53.118177 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3552 16:29:53.118257 # ok 1825 Set SVE VL 7296
3553 16:29:53.118337 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3554 16:29:53.118415 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3555 16:29:53.118494 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3556 16:29:53.118573 # ok 1829 Set SVE VL 7312
3557 16:29:53.118652 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3558 16:29:53.118731 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3559 16:29:53.118810 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3560 16:29:53.118891 # ok 1833 Set SVE VL 7328
3561 16:29:53.118970 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3562 16:29:53.119048 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3563 16:29:53.119129 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3564 16:29:53.119488 # ok 1837 Set SVE VL 7344
3565 16:29:53.119601 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3566 16:29:53.119713 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3567 16:29:53.119803 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3568 16:29:53.119887 # ok 1841 Set SVE VL 7360
3569 16:29:53.119976 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3570 16:29:53.120062 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3571 16:29:53.120183 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3572 16:29:53.120280 # ok 1845 Set SVE VL 7376
3573 16:29:53.120365 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3574 16:29:53.120446 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3575 16:29:53.120534 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3576 16:29:53.120642 # ok 1849 Set SVE VL 7392
3577 16:29:53.120747 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3578 16:29:53.120863 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3579 16:29:53.120970 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3580 16:29:53.121072 # ok 1853 Set SVE VL 7408
3581 16:29:53.121163 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3582 16:29:53.121260 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3583 16:29:53.121369 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3584 16:29:53.121476 # ok 1857 Set SVE VL 7424
3585 16:29:53.121572 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3586 16:29:53.121667 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3587 16:29:53.121752 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3588 16:29:53.121837 # ok 1861 Set SVE VL 7440
3589 16:29:53.129774 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3590 16:29:53.129984 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3591 16:29:53.130099 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3592 16:29:53.130212 # ok 1865 Set SVE VL 7456
3593 16:29:53.130324 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3594 16:29:53.130437 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3595 16:29:53.130555 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3596 16:29:53.130665 # ok 1869 Set SVE VL 7472
3597 16:29:53.130777 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3598 16:29:53.130889 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3599 16:29:53.130992 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3600 16:29:53.131104 # ok 1873 Set SVE VL 7488
3601 16:29:53.131218 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3602 16:29:53.131329 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3603 16:29:53.131426 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3604 16:29:53.131515 # ok 1877 Set SVE VL 7504
3605 16:29:53.131599 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3606 16:29:53.131684 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3607 16:29:53.131769 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3608 16:29:53.131855 # ok 1881 Set SVE VL 7520
3609 16:29:53.131937 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3610 16:29:53.132020 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3611 16:29:53.132104 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3612 16:29:53.132191 # ok 1885 Set SVE VL 7536
3613 16:29:53.132270 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3614 16:29:53.132357 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3615 16:29:53.132445 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3616 16:29:53.132533 # ok 1889 Set SVE VL 7552
3617 16:29:53.132618 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3618 16:29:53.132699 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3619 16:29:53.132782 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3620 16:29:53.132875 # ok 1893 Set SVE VL 7568
3621 16:29:53.132960 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3622 16:29:53.133046 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3623 16:29:53.133124 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3624 16:29:53.133208 # ok 1897 Set SVE VL 7584
3625 16:29:53.133290 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3626 16:29:53.133372 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3627 16:29:53.133448 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3628 16:29:53.133533 # ok 1901 Set SVE VL 7600
3629 16:29:53.133615 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3630 16:29:53.133708 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3631 16:29:53.134003 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3632 16:29:53.134105 # ok 1905 Set SVE VL 7616
3633 16:29:53.134190 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3634 16:29:53.134269 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3635 16:29:53.134349 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3636 16:29:53.134430 # ok 1909 Set SVE VL 7632
3637 16:29:53.134512 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3638 16:29:53.134594 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3639 16:29:53.134670 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3640 16:29:53.134731 # ok 1913 Set SVE VL 7648
3641 16:29:53.134789 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3642 16:29:53.134848 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3643 16:29:53.134915 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3644 16:29:53.134974 # ok 1917 Set SVE VL 7664
3645 16:29:53.135032 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3646 16:29:53.135091 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3647 16:29:53.135152 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3648 16:29:53.135242 # ok 1921 Set SVE VL 7680
3649 16:29:53.135345 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3650 16:29:53.135445 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3651 16:29:53.135530 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3652 16:29:53.135612 # ok 1925 Set SVE VL 7696
3653 16:29:53.135694 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3654 16:29:53.135773 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3655 16:29:53.135852 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3656 16:29:53.135932 # ok 1929 Set SVE VL 7712
3657 16:29:53.136013 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3658 16:29:53.136090 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3659 16:29:53.136171 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3660 16:29:53.136250 # ok 1933 Set SVE VL 7728
3661 16:29:53.136331 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3662 16:29:53.136409 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3663 16:29:53.136489 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3664 16:29:53.136569 # ok 1937 Set SVE VL 7744
3665 16:29:53.136648 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3666 16:29:53.136726 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3667 16:29:53.136807 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3668 16:29:53.136887 # ok 1941 Set SVE VL 7760
3669 16:29:53.136966 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3670 16:29:53.137046 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3671 16:29:53.137125 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3672 16:29:53.137206 # ok 1945 Set SVE VL 7776
3673 16:29:53.137283 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3674 16:29:53.137567 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3675 16:29:53.137684 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3676 16:29:53.137785 # ok 1949 Set SVE VL 7792
3677 16:29:53.137856 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3678 16:29:53.137948 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3679 16:29:53.138038 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3680 16:29:53.138117 # ok 1953 Set SVE VL 7808
3681 16:29:53.138196 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3682 16:29:53.138278 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3683 16:29:53.138344 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3684 16:29:53.138424 # ok 1957 Set SVE VL 7824
3685 16:29:53.138505 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3686 16:29:53.138581 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3687 16:29:53.138642 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3688 16:29:53.138703 # ok 1961 Set SVE VL 7840
3689 16:29:53.138764 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3690 16:29:53.138824 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3691 16:29:53.138883 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3692 16:29:53.138943 # ok 1965 Set SVE VL 7856
3693 16:29:53.139002 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3694 16:29:53.139062 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3695 16:29:53.139122 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3696 16:29:53.139185 # ok 1969 Set SVE VL 7872
3697 16:29:53.139269 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3698 16:29:53.139344 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3699 16:29:53.139406 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3700 16:29:53.139467 # ok 1973 Set SVE VL 7888
3701 16:29:53.139528 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3702 16:29:53.139587 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3703 16:29:53.139647 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3704 16:29:53.139707 # ok 1977 Set SVE VL 7904
3705 16:29:53.139767 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3706 16:29:53.139826 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3707 16:29:53.139886 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3708 16:29:53.139946 # ok 1981 Set SVE VL 7920
3709 16:29:53.140007 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3710 16:29:53.140067 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3711 16:29:53.140141 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3712 16:29:53.140234 # ok 1985 Set SVE VL 7936
3713 16:29:53.140317 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3714 16:29:53.140401 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3715 16:29:53.140485 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3716 16:29:53.140579 # ok 1989 Set SVE VL 7952
3717 16:29:53.140890 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3718 16:29:53.140999 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3719 16:29:53.141092 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3720 16:29:53.141179 # ok 1993 Set SVE VL 7968
3721 16:29:53.141279 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3722 16:29:53.141393 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3723 16:29:53.141480 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3724 16:29:53.141565 # ok 1997 Set SVE VL 7984
3725 16:29:53.141661 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3726 16:29:53.141750 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3727 16:29:53.141837 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3728 16:29:53.141924 # ok 2001 Set SVE VL 8000
3729 16:29:53.142010 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3730 16:29:53.142097 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3731 16:29:53.142185 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3732 16:29:53.142273 # ok 2005 Set SVE VL 8016
3733 16:29:53.142360 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3734 16:29:53.142448 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3735 16:29:53.142535 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3736 16:29:53.142621 # ok 2009 Set SVE VL 8032
3737 16:29:53.142707 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3738 16:29:53.142794 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3739 16:29:53.142882 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3740 16:29:53.142969 # ok 2013 Set SVE VL 8048
3741 16:29:53.143056 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3742 16:29:53.143144 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3743 16:29:53.143229 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3744 16:29:53.143315 # ok 2017 Set SVE VL 8064
3745 16:29:53.143405 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3746 16:29:53.143495 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3747 16:29:53.143585 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3748 16:29:53.143673 # ok 2021 Set SVE VL 8080
3749 16:29:53.143760 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3750 16:29:53.143850 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3751 16:29:53.143937 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3752 16:29:53.144024 # ok 2025 Set SVE VL 8096
3753 16:29:53.144111 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3754 16:29:53.144198 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3755 16:29:53.144284 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3756 16:29:53.144370 # ok 2029 Set SVE VL 8112
3757 16:29:53.144457 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3758 16:29:53.144543 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3759 16:29:53.144847 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3760 16:29:53.144963 # ok 2033 Set SVE VL 8128
3761 16:29:53.145054 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3762 16:29:53.145140 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3763 16:29:53.145226 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3764 16:29:53.145312 # ok 2037 Set SVE VL 8144
3765 16:29:53.145397 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3766 16:29:53.145483 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3767 16:29:53.145569 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3768 16:29:53.145662 # ok 2041 Set SVE VL 8160
3769 16:29:53.145749 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3770 16:29:53.145834 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3771 16:29:53.145927 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3772 16:29:53.146013 # ok 2045 Set SVE VL 8176
3773 16:29:53.146098 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3774 16:29:53.146184 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3775 16:29:53.146270 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3776 16:29:53.146356 # ok 2049 Set SVE VL 8192
3777 16:29:53.146442 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3778 16:29:53.146528 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3779 16:29:53.146615 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3780 16:29:53.146703 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3781 16:29:53.146791 # ok 2054 Streaming SVE get_fpsimd() gave same state
3782 16:29:53.146878 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3783 16:29:53.146964 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3784 16:29:53.147050 # ok 2057 Set Streaming SVE VL 16
3785 16:29:53.147138 # ok 2058 Set and get Streaming SVE data for VL 16
3786 16:29:53.147225 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3787 16:29:53.147311 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3788 16:29:53.147398 # ok 2061 Set Streaming SVE VL 32
3789 16:29:53.147484 # ok 2062 Set and get Streaming SVE data for VL 32
3790 16:29:53.147568 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3791 16:29:53.147655 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3792 16:29:53.147742 # ok 2065 Set Streaming SVE VL 48
3793 16:29:53.147830 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3794 16:29:53.147917 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3795 16:29:53.148004 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3796 16:29:53.148091 # ok 2069 Set Streaming SVE VL 64
3797 16:29:53.148177 # ok 2070 Set and get Streaming SVE data for VL 64
3798 16:29:53.148266 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3799 16:29:53.148352 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3800 16:29:53.148737 # ok 2073 Set Streaming SVE VL 80
3801 16:29:53.148842 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3802 16:29:53.148931 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3803 16:29:53.149018 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3804 16:29:53.149106 # ok 2077 Set Streaming SVE VL 96
3805 16:29:53.149194 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3806 16:29:53.149282 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3807 16:29:53.149367 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3808 16:29:53.149449 # ok 2081 Set Streaming SVE VL 112
3809 16:29:53.149525 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3810 16:29:53.149601 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3811 16:29:53.149682 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3812 16:29:53.149756 # ok 2085 Set Streaming SVE VL 128
3813 16:29:53.149827 # ok 2086 Set and get Streaming SVE data for VL 128
3814 16:29:53.149899 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3815 16:29:53.149973 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3816 16:29:53.150046 # ok 2089 Set Streaming SVE VL 144
3817 16:29:53.150118 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3818 16:29:53.150196 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3819 16:29:53.150275 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3820 16:29:53.150361 # ok 2093 Set Streaming SVE VL 160
3821 16:29:53.150439 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3822 16:29:53.150514 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3823 16:29:53.150589 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3824 16:29:53.150660 # ok 2097 Set Streaming SVE VL 176
3825 16:29:53.150731 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3826 16:29:53.150802 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3827 16:29:53.150873 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3828 16:29:53.150944 # ok 2101 Set Streaming SVE VL 192
3829 16:29:53.151016 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3830 16:29:53.151089 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3831 16:29:53.151160 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3832 16:29:53.151233 # ok 2105 Set Streaming SVE VL 208
3833 16:29:53.151307 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3834 16:29:53.151381 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3835 16:29:53.151454 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3836 16:29:53.151725 # ok 2109 Set Streaming SVE VL 224
3837 16:29:53.151805 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3838 16:29:53.151878 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3839 16:29:53.151949 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3840 16:29:53.152024 # ok 2113 Set Streaming SVE VL 240
3841 16:29:53.152095 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3842 16:29:53.152169 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3843 16:29:53.152242 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3844 16:29:53.152315 # ok 2117 Set Streaming SVE VL 256
3845 16:29:53.152386 # ok 2118 Set and get Streaming SVE data for VL 256
3846 16:29:53.152462 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3847 16:29:53.152549 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3848 16:29:53.152638 # ok 2121 Set Streaming SVE VL 272
3849 16:29:53.152711 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3850 16:29:53.152785 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3851 16:29:53.152861 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3852 16:29:53.152937 # ok 2125 Set Streaming SVE VL 288
3853 16:29:53.154345 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3854 16:29:53.154534 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3855 16:29:53.154631 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3856 16:29:53.155121 # ok 2129 Set Streaming SVE VL 304
3857 16:29:53.155225 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3858 16:29:53.155316 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3859 16:29:53.155500 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3860 16:29:53.155583 # ok 2133 Set Streaming SVE VL 320
3861 16:29:53.156078 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3862 16:29:53.156454 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3863 16:29:53.156664 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3864 16:29:53.156801 # ok 2137 Set Streaming SVE VL 336
3865 16:29:53.157604 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3866 16:29:53.157739 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3867 16:29:53.157858 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3868 16:29:53.157951 # ok 2141 Set Streaming SVE VL 352
3869 16:29:53.158068 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3870 16:29:53.158181 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3871 16:29:53.158272 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3872 16:29:53.158360 # ok 2145 Set Streaming SVE VL 368
3873 16:29:53.158791 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3874 16:29:53.158896 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3875 16:29:53.158985 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3876 16:29:53.159072 # ok 2149 Set Streaming SVE VL 384
3877 16:29:53.159360 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3878 16:29:53.159463 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3879 16:29:53.159553 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3880 16:29:53.159656 # ok 2153 Set Streaming SVE VL 400
3881 16:29:53.160151 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3882 16:29:53.160258 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3883 16:29:53.160347 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3884 16:29:53.160967 # ok 2157 Set Streaming SVE VL 416
3885 16:29:53.161410 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3886 16:29:53.161508 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3887 16:29:53.161594 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3888 16:29:53.161736 # ok 2161 Set Streaming SVE VL 432
3889 16:29:53.161848 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3890 16:29:53.161947 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3891 16:29:53.162035 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3892 16:29:53.162125 # ok 2165 Set Streaming SVE VL 448
3893 16:29:53.162435 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3894 16:29:53.162604 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3895 16:29:53.162823 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3896 16:29:53.162918 # ok 2169 Set Streaming SVE VL 464
3897 16:29:53.163022 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3898 16:29:53.163128 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3899 16:29:53.163219 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3900 16:29:53.163305 # ok 2173 Set Streaming SVE VL 480
3901 16:29:53.163391 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3902 16:29:53.163492 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3903 16:29:53.163865 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3904 16:29:53.163995 # ok 2177 Set Streaming SVE VL 496
3905 16:29:53.164464 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3906 16:29:53.164776 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3907 16:29:53.164989 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3908 16:29:53.165262 # ok 2181 Set Streaming SVE VL 512
3909 16:29:53.165361 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3910 16:29:53.165467 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3911 16:29:53.165558 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3912 16:29:53.165933 # ok 2185 Set Streaming SVE VL 528
3913 16:29:53.166037 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3914 16:29:53.166125 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3915 16:29:53.166866 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3916 16:29:53.167064 # ok 2189 Set Streaming SVE VL 544
3917 16:29:53.167157 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3918 16:29:53.167243 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3919 16:29:53.167330 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3920 16:29:53.167427 # ok 2193 Set Streaming SVE VL 560
3921 16:29:53.167522 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3922 16:29:53.167890 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3923 16:29:53.168334 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3924 16:29:53.168508 # ok 2197 Set Streaming SVE VL 576
3925 16:29:53.168604 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3926 16:29:53.168691 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3927 16:29:53.168796 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3928 16:29:53.168887 # ok 2201 Set Streaming SVE VL 592
3929 16:29:53.168981 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3930 16:29:53.169094 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3931 16:29:53.169190 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3932 16:29:53.169294 # ok 2205 Set Streaming SVE VL 608
3933 16:29:53.169398 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3934 16:29:53.169543 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3935 16:29:53.169801 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3936 16:29:53.169903 # ok 2209 Set Streaming SVE VL 624
3937 16:29:53.169990 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3938 16:29:53.170112 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3939 16:29:53.170229 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3940 16:29:53.170537 # ok 2213 Set Streaming SVE VL 640
3941 16:29:53.170641 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3942 16:29:53.170745 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3943 16:29:53.170848 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3944 16:29:53.170948 # ok 2217 Set Streaming SVE VL 656
3945 16:29:53.171059 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3946 16:29:53.171375 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3947 16:29:53.171749 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3948 16:29:53.171854 # ok 2221 Set Streaming SVE VL 672
3949 16:29:53.171960 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3950 16:29:53.172061 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3951 16:29:53.172164 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3952 16:29:53.172650 # ok 2225 Set Streaming SVE VL 688
3953 16:29:53.173110 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3954 16:29:53.173223 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3955 16:29:53.173311 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3956 16:29:53.173413 # ok 2229 Set Streaming SVE VL 704
3957 16:29:53.173499 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3958 16:29:53.173798 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3959 16:29:53.173920 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3960 16:29:53.174013 # ok 2233 Set Streaming SVE VL 720
3961 16:29:53.174432 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3962 16:29:53.175108 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3963 16:29:53.175223 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3964 16:29:53.175313 # ok 2237 Set Streaming SVE VL 736
3965 16:29:53.175400 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3966 16:29:53.175487 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3967 16:29:53.175587 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3968 16:29:53.175676 # ok 2241 Set Streaming SVE VL 752
3969 16:29:53.175780 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3970 16:29:53.176326 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3971 16:29:53.176488 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3972 16:29:53.176581 # ok 2245 Set Streaming SVE VL 768
3973 16:29:53.176687 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3974 16:29:53.176792 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3975 16:29:53.176898 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3976 16:29:53.177003 # ok 2249 Set Streaming SVE VL 784
3977 16:29:53.177328 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3978 16:29:53.178091 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3979 16:29:53.178196 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3980 16:29:53.178286 # ok 2253 Set Streaming SVE VL 800
3981 16:29:53.178372 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3982 16:29:53.178462 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3983 16:29:53.178992 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3984 16:29:53.179169 # ok 2257 Set Streaming SVE VL 816
3985 16:29:53.179270 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3986 16:29:53.179357 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3987 16:29:53.179445 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3988 16:29:53.179551 # ok 2261 Set Streaming SVE VL 832
3989 16:29:53.180023 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3990 16:29:53.180210 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3991 16:29:53.180304 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3992 16:29:53.180408 # ok 2265 Set Streaming SVE VL 848
3993 16:29:53.180499 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3994 16:29:53.180780 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3995 16:29:53.180933 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3996 16:29:53.181025 # ok 2269 Set Streaming SVE VL 864
3997 16:29:53.181130 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
3998 16:29:53.181220 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
3999 16:29:53.181322 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4000 16:29:53.181412 # ok 2273 Set Streaming SVE VL 880
4001 16:29:53.181513 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4002 16:29:53.181617 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4003 16:29:53.181950 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4004 16:29:53.182055 # ok 2277 Set Streaming SVE VL 896
4005 16:29:53.182337 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4006 16:29:53.185443 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4007 16:29:53.185761 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4008 16:29:53.185860 # ok 2281 Set Streaming SVE VL 912
4009 16:29:53.185947 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4010 16:29:53.186051 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4011 16:29:53.186452 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4012 16:29:53.186562 # ok 2285 Set Streaming SVE VL 928
4013 16:29:53.186652 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4014 16:29:53.186756 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4015 16:29:53.186864 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4016 16:29:53.186966 # ok 2289 Set Streaming SVE VL 944
4017 16:29:53.187068 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4018 16:29:53.187381 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4019 16:29:53.188279 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4020 16:29:53.188386 # ok 2293 Set Streaming SVE VL 960
4021 16:29:53.188477 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4022 16:29:53.188849 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4023 16:29:53.189328 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4024 16:29:53.189451 # ok 2297 Set Streaming SVE VL 976
4025 16:29:53.189564 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4026 16:29:53.189662 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4027 16:29:53.189753 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4028 16:29:53.189854 # ok 2301 Set Streaming SVE VL 992
4029 16:29:53.189943 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4030 16:29:53.190046 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4031 16:29:53.190151 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4032 16:29:53.190263 # ok 2305 Set Streaming SVE VL 1008
4033 16:29:53.190621 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4034 16:29:53.190821 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4035 16:29:53.191109 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4036 16:29:53.191255 # ok 2309 Set Streaming SVE VL 1024
4037 16:29:53.191425 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4038 16:29:53.191583 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4039 16:29:53.191739 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4040 16:29:53.192211 # ok 2313 Set Streaming SVE VL 1040
4041 16:29:53.192369 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4042 16:29:53.192488 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4043 16:29:53.192581 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4044 16:29:53.192684 # ok 2317 Set Streaming SVE VL 1056
4045 16:29:53.193029 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4046 16:29:53.193134 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4047 16:29:53.193237 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4048 16:29:53.193343 # ok 2321 Set Streaming SVE VL 1072
4049 16:29:53.193445 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4050 16:29:53.195270 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4051 16:29:53.195389 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4052 16:29:53.195490 # ok 2325 Set Streaming SVE VL 1088
4053 16:29:53.195587 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4054 16:29:53.195684 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4055 16:29:53.195780 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4056 16:29:53.195876 # ok 2329 Set Streaming SVE VL 1104
4057 16:29:53.195972 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4058 16:29:53.196068 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4059 16:29:53.196165 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4060 16:29:53.198250 # ok 2333 Set Streaming SVE VL 1120
4061 16:29:53.198715 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4062 16:29:53.198833 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4063 16:29:53.198949 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4064 16:29:53.199046 # ok 2337 Set Streaming SVE VL 1136
4065 16:29:53.199164 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4066 16:29:53.199270 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4067 16:29:53.199366 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4068 16:29:53.199466 # ok 2341 Set Streaming SVE VL 1152
4069 16:29:53.199584 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4070 16:29:53.199686 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4071 16:29:53.199799 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4072 16:29:53.199896 # ok 2345 Set Streaming SVE VL 1168
4073 16:29:53.199999 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4074 16:29:53.200094 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4075 16:29:53.200208 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4076 16:29:53.200304 # ok 2349 Set Streaming SVE VL 1184
4077 16:29:53.200399 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4078 16:29:53.200494 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4079 16:29:53.200590 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4080 16:29:53.200686 # ok 2353 Set Streaming SVE VL 1200
4081 16:29:53.201015 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4082 16:29:53.201607 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4083 16:29:53.201753 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4084 16:29:53.201893 # ok 2357 Set Streaming SVE VL 1216
4085 16:29:53.202024 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4086 16:29:53.202157 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4087 16:29:53.202285 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4088 16:29:53.202391 # ok 2361 Set Streaming SVE VL 1232
4089 16:29:53.202504 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4090 16:29:53.202629 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4091 16:29:53.202773 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4092 16:29:53.202904 # ok 2365 Set Streaming SVE VL 1248
4093 16:29:53.203038 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4094 16:29:53.203155 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4095 16:29:53.203283 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4096 16:29:53.203425 # ok 2369 Set Streaming SVE VL 1264
4097 16:29:53.203549 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4098 16:29:53.203678 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4099 16:29:53.203808 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4100 16:29:53.203939 # ok 2373 Set Streaming SVE VL 1280
4101 16:29:53.204059 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4102 16:29:53.204198 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4103 16:29:53.204322 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4104 16:29:53.204459 # ok 2377 Set Streaming SVE VL 1296
4105 16:29:53.204586 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4106 16:29:53.204709 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4107 16:29:53.204839 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4108 16:29:53.204987 # ok 2381 Set Streaming SVE VL 1312
4109 16:29:53.205119 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4110 16:29:53.205244 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4111 16:29:53.205372 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4112 16:29:53.205497 # ok 2385 Set Streaming SVE VL 1328
4113 16:29:53.205621 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4114 16:29:53.205779 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4115 16:29:53.205911 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4116 16:29:53.206053 # ok 2389 Set Streaming SVE VL 1344
4117 16:29:53.206466 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4118 16:29:53.206763 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4119 16:29:53.207266 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4120 16:29:53.207468 # ok 2393 Set Streaming SVE VL 1360
4121 16:29:53.208024 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4122 16:29:53.208283 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4123 16:29:53.208404 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4124 16:29:53.208521 # ok 2397 Set Streaming SVE VL 1376
4125 16:29:53.208645 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4126 16:29:53.208779 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4127 16:29:53.208877 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4128 16:29:53.208970 # ok 2401 Set Streaming SVE VL 1392
4129 16:29:53.209061 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4130 16:29:53.209152 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4131 16:29:53.209277 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4132 16:29:53.209390 # ok 2405 Set Streaming SVE VL 1408
4133 16:29:53.209521 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4134 16:29:53.209641 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4135 16:29:53.209769 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4136 16:29:53.209889 # ok 2409 Set Streaming SVE VL 1424
4137 16:29:53.210024 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4138 16:29:53.210141 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4139 16:29:53.210278 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4140 16:29:53.210455 # ok 2413 Set Streaming SVE VL 1440
4141 16:29:53.211376 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4142 16:29:53.211490 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4143 16:29:53.211590 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4144 16:29:53.212264 # ok 2417 Set Streaming SVE VL 1456
4145 16:29:53.212367 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4146 16:29:53.212457 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4147 16:29:53.212554 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4148 16:29:53.212638 # ok 2421 Set Streaming SVE VL 1472
4149 16:29:53.212718 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4150 16:29:53.212800 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4151 16:29:53.212873 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4152 16:29:53.213125 # ok 2425 Set Streaming SVE VL 1488
4153 16:29:53.213209 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4154 16:29:53.213303 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4155 16:29:53.213380 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4156 16:29:53.215919 # ok 2429 Set Streaming SVE VL 1504
4157 16:29:53.216269 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4158 16:29:53.216407 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4159 16:29:53.216599 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4160 16:29:53.216897 # ok 2433 Set Streaming SVE VL 1520
4161 16:29:53.217002 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4162 16:29:53.217096 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4163 16:29:53.217375 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4164 16:29:53.217475 # ok 2437 Set Streaming SVE VL 1536
4165 16:29:53.217568 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4166 16:29:53.217937 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4167 16:29:53.218248 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4168 16:29:53.218347 # ok 2441 Set Streaming SVE VL 1552
4169 16:29:53.218427 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4170 16:29:53.218518 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4171 16:29:53.218810 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4172 16:29:53.218911 # ok 2445 Set Streaming SVE VL 1568
4173 16:29:53.219003 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4174 16:29:53.219299 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4175 16:29:53.219608 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4176 16:29:53.219721 # ok 2449 Set Streaming SVE VL 1584
4177 16:29:53.220050 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4178 16:29:53.220164 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4179 16:29:53.220270 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4180 16:29:53.220617 # ok 2453 Set Streaming SVE VL 1600
4181 16:29:53.220723 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4182 16:29:53.220825 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4183 16:29:53.221253 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4184 16:29:53.221633 # ok 2457 Set Streaming SVE VL 1616
4185 16:29:53.221757 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4186 16:29:53.221861 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4187 16:29:53.222221 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4188 16:29:53.222328 # ok 2461 Set Streaming SVE VL 1632
4189 16:29:53.222416 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4190 16:29:53.222502 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4191 16:29:53.222813 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4192 16:29:53.222924 # ok 2465 Set Streaming SVE VL 1648
4193 16:29:53.223017 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4194 16:29:53.223429 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4195 16:29:53.223609 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4196 16:29:53.223776 # ok 2469 Set Streaming SVE VL 1664
4197 16:29:53.223876 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4198 16:29:53.224165 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4199 16:29:53.224277 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4200 16:29:53.224372 # ok 2473 Set Streaming SVE VL 1680
4201 16:29:53.224463 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4202 16:29:53.224569 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4203 16:29:53.224846 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4204 16:29:53.224954 # ok 2477 Set Streaming SVE VL 1696
4205 16:29:53.225047 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4206 16:29:53.225139 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4207 16:29:53.225487 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4208 16:29:53.225595 # ok 2481 Set Streaming SVE VL 1712
4209 16:29:53.225693 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4210 16:29:53.225783 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4211 16:29:53.225887 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4212 16:29:53.225978 # ok 2485 Set Streaming SVE VL 1728
4213 16:29:53.226389 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4214 16:29:53.226503 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4215 16:29:53.226592 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4216 16:29:53.226679 # ok 2489 Set Streaming SVE VL 1744
4217 16:29:53.226779 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4218 16:29:53.226867 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4219 16:29:53.227366 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4220 16:29:53.227480 # ok 2493 Set Streaming SVE VL 1760
4221 16:29:53.227570 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4222 16:29:53.227659 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4223 16:29:53.227956 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4224 16:29:53.228071 # ok 2497 Set Streaming SVE VL 1776
4225 16:29:53.228176 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4226 16:29:53.228528 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4227 16:29:53.228635 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4228 16:29:53.228726 # ok 2501 Set Streaming SVE VL 1792
4229 16:29:53.229061 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4230 16:29:53.229168 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4231 16:29:53.229257 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4232 16:29:53.229361 # ok 2505 Set Streaming SVE VL 1808
4233 16:29:53.229452 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4234 16:29:53.230091 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4235 16:29:53.230203 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4236 16:29:53.230295 # ok 2509 Set Streaming SVE VL 1824
4237 16:29:53.230384 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4238 16:29:53.230473 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4239 16:29:53.230966 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4240 16:29:53.231073 # ok 2513 Set Streaming SVE VL 1840
4241 16:29:53.231162 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4242 16:29:53.231249 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4243 16:29:53.231334 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4244 16:29:53.231418 # ok 2517 Set Streaming SVE VL 1856
4245 16:29:53.231536 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4246 16:29:53.231632 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4247 16:29:53.231972 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4248 16:29:53.232302 # ok 2521 Set Streaming SVE VL 1872
4249 16:29:53.232408 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4250 16:29:53.232514 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4251 16:29:53.232846 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4252 16:29:53.232952 # ok 2525 Set Streaming SVE VL 1888
4253 16:29:53.233042 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4254 16:29:53.233131 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4255 16:29:53.233235 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4256 16:29:53.233667 # ok 2529 Set Streaming SVE VL 1904
4257 16:29:53.233777 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4258 16:29:53.233867 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4259 16:29:53.233957 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4260 16:29:53.234247 # ok 2533 Set Streaming SVE VL 1920
4261 16:29:53.234355 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4262 16:29:53.234461 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4263 16:29:53.234781 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4264 16:29:53.234902 # ok 2537 Set Streaming SVE VL 1936
4265 16:29:53.234996 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4266 16:29:53.235086 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4267 16:29:53.235189 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4268 16:29:53.235294 # ok 2541 Set Streaming SVE VL 1952
4269 16:29:53.235385 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4270 16:29:53.235775 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4271 16:29:53.235932 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4272 16:29:53.236033 # ok 2545 Set Streaming SVE VL 1968
4273 16:29:53.236274 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4274 16:29:53.236372 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4275 16:29:53.236721 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4276 16:29:53.237081 # ok 2549 Set Streaming SVE VL 1984
4277 16:29:53.237406 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4278 16:29:53.237785 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4279 16:29:53.237996 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4280 16:29:53.238092 # ok 2553 Set Streaming SVE VL 2000
4281 16:29:53.238199 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4282 16:29:53.238292 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4283 16:29:53.238599 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4284 16:29:53.238706 # ok 2557 Set Streaming SVE VL 2016
4285 16:29:53.238795 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4286 16:29:53.238884 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4287 16:29:53.239271 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4288 16:29:53.239382 # ok 2561 Set Streaming SVE VL 2032
4289 16:29:53.239474 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4290 16:29:53.239560 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4291 16:29:53.239664 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4292 16:29:53.239753 # ok 2565 Set Streaming SVE VL 2048
4293 16:29:53.239856 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4294 16:29:53.239944 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4295 16:29:53.240049 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4296 16:29:53.240567 # ok 2569 Set Streaming SVE VL 2064
4297 16:29:53.240744 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4298 16:29:53.240860 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4299 16:29:53.241235 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4300 16:29:53.241355 # ok 2573 Set Streaming SVE VL 2080
4301 16:29:53.241671 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4302 16:29:53.241786 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4303 16:29:53.241872 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4304 16:29:53.241950 # ok 2577 Set Streaming SVE VL 2096
4305 16:29:53.242025 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4306 16:29:53.245464 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4307 16:29:53.245756 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4308 16:29:53.245852 # ok 2581 Set Streaming SVE VL 2112
4309 16:29:53.245959 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4310 16:29:53.246049 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4311 16:29:53.246138 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4312 16:29:53.246241 # ok 2585 Set Streaming SVE VL 2128
4313 16:29:53.246345 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4314 16:29:53.246641 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4315 16:29:53.246749 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4316 16:29:53.246855 # ok 2589 Set Streaming SVE VL 2144
4317 16:29:53.247174 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4318 16:29:53.247281 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4319 16:29:53.247562 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4320 16:29:53.247660 # ok 2593 Set Streaming SVE VL 2160
4321 16:29:53.248218 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4322 16:29:53.248370 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4323 16:29:53.248941 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4324 16:29:53.249047 # ok 2597 Set Streaming SVE VL 2176
4325 16:29:53.249349 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4326 16:29:53.249526 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4327 16:29:53.249614 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4328 16:29:53.249699 # ok 2601 Set Streaming SVE VL 2192
4329 16:29:53.249793 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4330 16:29:53.249874 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4331 16:29:53.249953 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4332 16:29:53.250043 # ok 2605 Set Streaming SVE VL 2208
4333 16:29:53.250123 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4334 16:29:53.250212 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4335 16:29:53.250512 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4336 16:29:53.250614 # ok 2609 Set Streaming SVE VL 2224
4337 16:29:53.250707 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4338 16:29:53.250798 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4339 16:29:53.251172 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4340 16:29:53.251289 # ok 2613 Set Streaming SVE VL 2240
4341 16:29:53.251711 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4342 16:29:53.251971 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4343 16:29:53.252077 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4344 16:29:53.252158 # ok 2617 Set Streaming SVE VL 2256
4345 16:29:53.252236 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4346 16:29:53.252599 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4347 16:29:53.252755 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4348 16:29:53.252843 # ok 2621 Set Streaming SVE VL 2272
4349 16:29:53.252937 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4350 16:29:53.253034 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4351 16:29:53.253348 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4352 16:29:53.253490 # ok 2625 Set Streaming SVE VL 2288
4353 16:29:53.253591 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4354 16:29:53.253690 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4355 16:29:53.254004 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4356 16:29:53.254288 # ok 2629 Set Streaming SVE VL 2304
4357 16:29:53.254406 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4358 16:29:53.254705 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4359 16:29:53.255024 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4360 16:29:53.255427 # ok 2633 Set Streaming SVE VL 2320
4361 16:29:53.255535 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4362 16:29:53.256047 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4363 16:29:53.256423 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4364 16:29:53.256542 # ok 2637 Set Streaming SVE VL 2336
4365 16:29:53.256631 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4366 16:29:53.256717 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4367 16:29:53.257076 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4368 16:29:53.257192 # ok 2641 Set Streaming SVE VL 2352
4369 16:29:53.257293 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4370 16:29:53.257379 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4371 16:29:53.257478 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4372 16:29:53.257801 # ok 2645 Set Streaming SVE VL 2368
4373 16:29:53.257914 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4374 16:29:53.258006 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4375 16:29:53.258092 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4376 16:29:53.258176 # ok 2649 Set Streaming SVE VL 2384
4377 16:29:53.258621 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4378 16:29:53.258729 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4379 16:29:53.258815 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4380 16:29:53.258898 # ok 2653 Set Streaming SVE VL 2400
4381 16:29:53.258982 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4382 16:29:53.259065 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4383 16:29:53.259147 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4384 16:29:53.259235 # ok 2657 Set Streaming SVE VL 2416
4385 16:29:53.259731 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4386 16:29:53.259837 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4387 16:29:53.259925 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4388 16:29:53.260009 # ok 2661 Set Streaming SVE VL 2432
4389 16:29:53.260098 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4390 16:29:53.260183 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4391 16:29:53.260267 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4392 16:29:53.260350 # ok 2665 Set Streaming SVE VL 2448
4393 16:29:53.260438 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4394 16:29:53.260538 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4395 16:29:53.261186 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4396 16:29:53.261488 # ok 2669 Set Streaming SVE VL 2464
4397 16:29:53.261619 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4398 16:29:53.261747 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4399 16:29:53.261878 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4400 16:29:53.262029 # ok 2673 Set Streaming SVE VL 2480
4401 16:29:53.262226 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4402 16:29:53.262413 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4403 16:29:53.262735 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4404 16:29:53.263028 # ok 2677 Set Streaming SVE VL 2496
4405 16:29:53.263192 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4406 16:29:53.263432 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4407 16:29:53.263541 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4408 16:29:53.263630 # ok 2681 Set Streaming SVE VL 2512
4409 16:29:53.263715 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4410 16:29:53.263799 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4411 16:29:53.263883 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4412 16:29:53.263966 # ok 2685 Set Streaming SVE VL 2528
4413 16:29:53.264355 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4414 16:29:53.264464 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4415 16:29:53.264551 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4416 16:29:53.264636 # ok 2689 Set Streaming SVE VL 2544
4417 16:29:53.264719 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4418 16:29:53.264803 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4419 16:29:53.264886 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4420 16:29:53.264970 # ok 2693 Set Streaming SVE VL 2560
4421 16:29:53.265073 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4422 16:29:53.265160 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4423 16:29:53.265244 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4424 16:29:53.265327 # ok 2697 Set Streaming SVE VL 2576
4425 16:29:53.265425 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4426 16:29:53.265510 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4427 16:29:53.265594 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4428 16:29:53.265702 # ok 2701 Set Streaming SVE VL 2592
4429 16:29:53.265788 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4430 16:29:53.266269 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4431 16:29:53.266376 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4432 16:29:53.266463 # ok 2705 Set Streaming SVE VL 2608
4433 16:29:53.267396 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4434 16:29:53.267502 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4435 16:29:53.267590 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4436 16:29:53.267675 # ok 2709 Set Streaming SVE VL 2624
4437 16:29:53.267759 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4438 16:29:53.267843 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4439 16:29:53.267926 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4440 16:29:53.268025 # ok 2713 Set Streaming SVE VL 2640
4441 16:29:53.268111 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4442 16:29:53.268701 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4443 16:29:53.268808 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4444 16:29:53.268895 # ok 2717 Set Streaming SVE VL 2656
4445 16:29:53.268980 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4446 16:29:53.269063 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4447 16:29:53.269147 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4448 16:29:53.269247 # ok 2721 Set Streaming SVE VL 2672
4449 16:29:53.269333 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4450 16:29:53.269417 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4451 16:29:53.269517 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4452 16:29:53.269603 # ok 2725 Set Streaming SVE VL 2688
4453 16:29:53.270012 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4454 16:29:53.270122 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4455 16:29:53.272870 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4456 16:29:53.273452 # ok 2729 Set Streaming SVE VL 2704
4457 16:29:53.273591 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4458 16:29:53.273916 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4459 16:29:53.274021 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4460 16:29:53.274112 # ok 2733 Set Streaming SVE VL 2720
4461 16:29:53.274196 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4462 16:29:53.274297 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4463 16:29:53.274384 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4464 16:29:53.274467 # ok 2737 Set Streaming SVE VL 2736
4465 16:29:53.274565 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4466 16:29:53.274867 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4467 16:29:53.274974 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4468 16:29:53.275076 # ok 2741 Set Streaming SVE VL 2752
4469 16:29:53.275163 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4470 16:29:53.275261 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4471 16:29:53.276109 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4472 16:29:53.276394 # ok 2745 Set Streaming SVE VL 2768
4473 16:29:53.276692 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4474 16:29:53.276800 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4475 16:29:53.276890 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4476 16:29:53.276976 # ok 2749 Set Streaming SVE VL 2784
4477 16:29:53.277075 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4478 16:29:53.277451 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4479 16:29:53.277558 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4480 16:29:53.277653 # ok 2753 Set Streaming SVE VL 2800
4481 16:29:53.277739 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4482 16:29:53.277823 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4483 16:29:53.277908 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4484 16:29:53.278010 # ok 2757 Set Streaming SVE VL 2816
4485 16:29:53.278300 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4486 16:29:53.278486 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4487 16:29:53.278599 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4488 16:29:53.278687 # ok 2761 Set Streaming SVE VL 2832
4489 16:29:53.278771 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4490 16:29:53.279276 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4491 16:29:53.279432 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4492 16:29:53.279530 # ok 2765 Set Streaming SVE VL 2848
4493 16:29:53.279616 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4494 16:29:53.279954 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4495 16:29:53.280168 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4496 16:29:53.280635 # ok 2769 Set Streaming SVE VL 2864
4497 16:29:53.282055 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4498 16:29:53.282708 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4499 16:29:53.282803 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4500 16:29:53.282888 # ok 2773 Set Streaming SVE VL 2880
4501 16:29:53.282972 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4502 16:29:53.283055 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4503 16:29:53.283162 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4504 16:29:53.283249 # ok 2777 Set Streaming SVE VL 2896
4505 16:29:53.283334 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4506 16:29:53.283417 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4507 16:29:53.283501 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4508 16:29:53.283584 # ok 2781 Set Streaming SVE VL 2912
4509 16:29:53.283667 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4510 16:29:53.283750 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4511 16:29:53.283833 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4512 16:29:53.283916 # ok 2785 Set Streaming SVE VL 2928
4513 16:29:53.283999 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4514 16:29:53.284082 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4515 16:29:53.284165 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4516 16:29:53.284248 # ok 2789 Set Streaming SVE VL 2944
4517 16:29:53.284349 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4518 16:29:53.284436 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4519 16:29:53.284520 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4520 16:29:53.284603 # ok 2793 Set Streaming SVE VL 2960
4521 16:29:53.284686 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4522 16:29:53.284769 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4523 16:29:53.284869 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4524 16:29:53.284956 # ok 2797 Set Streaming SVE VL 2976
4525 16:29:53.285040 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4526 16:29:53.285152 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4527 16:29:53.285724 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4528 16:29:53.285831 # ok 2801 Set Streaming SVE VL 2992
4529 16:29:53.285920 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4530 16:29:53.286024 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4531 16:29:53.286125 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4532 16:29:53.286225 # ok 2805 Set Streaming SVE VL 3008
4533 16:29:53.286637 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4534 16:29:53.286784 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4535 16:29:53.287093 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4536 16:29:53.287456 # ok 2809 Set Streaming SVE VL 3024
4537 16:29:53.287565 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4538 16:29:53.288439 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4539 16:29:53.288543 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4540 16:29:53.288630 # ok 2813 Set Streaming SVE VL 3040
4541 16:29:53.288714 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4542 16:29:53.288798 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4543 16:29:53.288882 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4544 16:29:53.288982 # ok 2817 Set Streaming SVE VL 3056
4545 16:29:53.289068 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4546 16:29:53.289153 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4547 16:29:53.289252 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4548 16:29:53.289338 # ok 2821 Set Streaming SVE VL 3072
4549 16:29:53.289436 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4550 16:29:53.289789 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4551 16:29:53.289910 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4552 16:29:53.290003 # ok 2825 Set Streaming SVE VL 3088
4553 16:29:53.290676 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4554 16:29:53.291083 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4555 16:29:53.291202 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4556 16:29:53.291293 # ok 2829 Set Streaming SVE VL 3104
4557 16:29:53.291379 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4558 16:29:53.291465 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4559 16:29:53.291774 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4560 16:29:53.291903 # ok 2833 Set Streaming SVE VL 3120
4561 16:29:53.292007 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4562 16:29:53.292093 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4563 16:29:53.292196 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4564 16:29:53.292283 # ok 2837 Set Streaming SVE VL 3136
4565 16:29:53.292381 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4566 16:29:53.292480 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4567 16:29:53.292812 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4568 16:29:53.292931 # ok 2841 Set Streaming SVE VL 3152
4569 16:29:53.293019 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4570 16:29:53.293117 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4571 16:29:53.293429 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4572 16:29:53.293535 # ok 2845 Set Streaming SVE VL 3168
4573 16:29:53.294195 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4574 16:29:53.294302 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4575 16:29:53.294388 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4576 16:29:53.294473 # ok 2849 Set Streaming SVE VL 3184
4577 16:29:53.294556 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4578 16:29:53.294986 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4579 16:29:53.295125 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4580 16:29:53.295220 # ok 2853 Set Streaming SVE VL 3200
4581 16:29:53.295304 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4582 16:29:53.295403 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4583 16:29:53.295490 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4584 16:29:53.295574 # ok 2857 Set Streaming SVE VL 3216
4585 16:29:53.295672 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4586 16:29:53.295772 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4587 16:29:53.301742 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4588 16:29:53.301908 # ok 2861 Set Streaming SVE VL 3232
4589 16:29:53.301997 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4590 16:29:53.302083 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4591 16:29:53.302168 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4592 16:29:53.302253 # ok 2865 Set Streaming SVE VL 3248
4593 16:29:53.302337 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4594 16:29:53.302421 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4595 16:29:53.302504 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4596 16:29:53.302588 # ok 2869 Set Streaming SVE VL 3264
4597 16:29:53.302671 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4598 16:29:53.302754 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4599 16:29:53.302837 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4600 16:29:53.302922 # ok 2873 Set Streaming SVE VL 3280
4601 16:29:53.303005 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4602 16:29:53.303089 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4603 16:29:53.303173 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4604 16:29:53.303257 # ok 2877 Set Streaming SVE VL 3296
4605 16:29:53.307467 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4606 16:29:53.307653 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4607 16:29:53.314365 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4608 16:29:53.314594 # ok 2881 Set Streaming SVE VL 3312
4609 16:29:53.315006 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4610 16:29:53.315243 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4611 16:29:53.315384 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4612 16:29:53.315470 # ok 2885 Set Streaming SVE VL 3328
4613 16:29:53.315561 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4614 16:29:53.315638 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4615 16:29:53.325911 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4616 16:29:53.326656 # ok 2889 Set Streaming SVE VL 3344
4617 16:29:53.327227 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4618 16:29:53.327635 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4619 16:29:53.327755 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4620 16:29:53.327836 # ok 2893 Set Streaming SVE VL 3360
4621 16:29:53.327911 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4622 16:29:53.327987 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4623 16:29:53.328062 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4624 16:29:53.328137 # ok 2897 Set Streaming SVE VL 3376
4625 16:29:53.328213 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4626 16:29:53.328302 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4627 16:29:53.337807 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4628 16:29:53.338421 # ok 2901 Set Streaming SVE VL 3392
4629 16:29:53.338572 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4630 16:29:53.338670 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4631 16:29:53.338762 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4632 16:29:53.338853 # ok 2905 Set Streaming SVE VL 3408
4633 16:29:53.338943 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4634 16:29:53.339034 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4635 16:29:53.339122 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4636 16:29:53.339667 # ok 2909 Set Streaming SVE VL 3424
4637 16:29:53.339763 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4638 16:29:53.339843 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4639 16:29:53.339960 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4640 16:29:53.340042 # ok 2913 Set Streaming SVE VL 3440
4641 16:29:53.340115 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4642 16:29:53.345061 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4643 16:29:53.346398 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4644 16:29:53.346618 # ok 2917 Set Streaming SVE VL 3456
4645 16:29:53.347030 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4646 16:29:53.347128 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4647 16:29:53.347240 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4648 16:29:53.347339 # ok 2921 Set Streaming SVE VL 3472
4649 16:29:53.347633 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4650 16:29:53.347727 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4651 16:29:53.353200 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4652 16:29:53.353461 # ok 2925 Set Streaming SVE VL 3488
4653 16:29:53.353574 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4654 16:29:53.357745 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4655 16:29:53.357889 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4656 16:29:53.357965 # ok 2929 Set Streaming SVE VL 3504
4657 16:29:53.358042 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4658 16:29:53.358118 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4659 16:29:53.358197 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4660 16:29:53.358277 # ok 2933 Set Streaming SVE VL 3520
4661 16:29:53.358353 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4662 16:29:53.358435 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4663 16:29:53.358521 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4664 16:29:53.361659 # ok 2937 Set Streaming SVE VL 3536
4665 16:29:53.361801 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4666 16:29:53.361891 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4667 16:29:53.362659 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4668 16:29:53.365704 # ok 2941 Set Streaming SVE VL 3552
4669 16:29:53.365853 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4670 16:29:53.365934 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4671 16:29:53.366013 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4672 16:29:53.366090 # ok 2945 Set Streaming SVE VL 3568
4673 16:29:53.366167 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4674 16:29:53.366244 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4675 16:29:53.366321 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4676 16:29:53.366399 # ok 2949 Set Streaming SVE VL 3584
4677 16:29:53.366475 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4678 16:29:53.369220 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4679 16:29:53.369975 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4680 16:29:53.370081 # ok 2953 Set Streaming SVE VL 3600
4681 16:29:53.370173 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4682 16:29:53.370263 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4683 16:29:53.370554 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4684 16:29:53.370657 # ok 2957 Set Streaming SVE VL 3616
4685 16:29:53.370758 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4686 16:29:53.371078 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4687 16:29:53.371183 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4688 16:29:53.371565 # ok 2961 Set Streaming SVE VL 3632
4689 16:29:53.371658 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4690 16:29:53.377041 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4691 16:29:53.377607 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4692 16:29:53.379605 # ok 2965 Set Streaming SVE VL 3648
4693 16:29:53.379840 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4694 16:29:53.379933 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4695 16:29:53.380011 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4696 16:29:53.380088 # ok 2969 Set Streaming SVE VL 3664
4697 16:29:53.380164 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4698 16:29:53.380238 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4699 16:29:53.386723 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4700 16:29:53.386956 # ok 2973 Set Streaming SVE VL 3680
4701 16:29:53.387054 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4702 16:29:53.387145 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4703 16:29:53.387234 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4704 16:29:53.387335 # ok 2977 Set Streaming SVE VL 3696
4705 16:29:53.387427 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4706 16:29:53.387715 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4707 16:29:53.387815 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4708 16:29:53.387896 # ok 2981 Set Streaming SVE VL 3712
4709 16:29:53.396458 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4710 16:29:53.396913 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4711 16:29:53.397227 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4712 16:29:53.397965 # ok 2985 Set Streaming SVE VL 3728
4713 16:29:53.398570 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4714 16:29:53.398668 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4715 16:29:53.399083 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4716 16:29:53.399475 # ok 2989 Set Streaming SVE VL 3744
4717 16:29:53.400111 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4718 16:29:53.409277 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4719 16:29:53.409763 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4720 16:29:53.409867 # ok 2993 Set Streaming SVE VL 3760
4721 16:29:53.409950 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4722 16:29:53.410195 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4723 16:29:53.410529 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4724 16:29:53.410846 # ok 2997 Set Streaming SVE VL 3776
4725 16:29:53.410944 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4726 16:29:53.411473 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4727 16:29:53.411577 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4728 16:29:53.416929 # ok 3001 Set Streaming SVE VL 3792
4729 16:29:53.417360 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4730 16:29:53.417465 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4731 16:29:53.417781 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4732 16:29:53.417893 # ok 3005 Set Streaming SVE VL 3808
4733 16:29:53.418272 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4734 16:29:53.418656 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4735 16:29:53.418755 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4736 16:29:53.419187 # ok 3009 Set Streaming SVE VL 3824
4737 16:29:53.419291 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4738 16:29:53.419379 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4739 16:29:53.419471 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4740 16:29:53.419782 # ok 3013 Set Streaming SVE VL 3840
4741 16:29:53.419916 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4742 16:29:53.420003 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4743 16:29:53.425777 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4744 16:29:53.425977 # ok 3017 Set Streaming SVE VL 3856
4745 16:29:53.426345 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4746 16:29:53.426445 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4747 16:29:53.427543 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4748 16:29:53.427654 # ok 3021 Set Streaming SVE VL 3872
4749 16:29:53.427736 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4750 16:29:53.427814 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4751 16:29:53.427892 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4752 16:29:53.427970 # ok 3025 Set Streaming SVE VL 3888
4753 16:29:53.428048 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4754 16:29:53.438954 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4755 16:29:53.441771 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4756 16:29:53.441879 # ok 3029 Set Streaming SVE VL 3904
4757 16:29:53.441961 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4758 16:29:53.442041 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4759 16:29:53.442119 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4760 16:29:53.442197 # ok 3033 Set Streaming SVE VL 3920
4761 16:29:53.442274 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4762 16:29:53.442351 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4763 16:29:53.442429 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4764 16:29:53.442506 # ok 3037 Set Streaming SVE VL 3936
4765 16:29:53.442582 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4766 16:29:53.442660 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4767 16:29:53.442737 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4768 16:29:53.442815 # ok 3041 Set Streaming SVE VL 3952
4769 16:29:53.443153 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4770 16:29:53.443259 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4771 16:29:53.443340 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4772 16:29:53.443421 # ok 3045 Set Streaming SVE VL 3968
4773 16:29:53.443498 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4774 16:29:53.443589 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4775 16:29:53.449852 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4776 16:29:53.450601 # ok 3049 Set Streaming SVE VL 3984
4777 16:29:53.450704 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4778 16:29:53.450786 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4779 16:29:53.450872 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4780 16:29:53.450964 # ok 3053 Set Streaming SVE VL 4000
4781 16:29:53.451456 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4782 16:29:53.451558 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4783 16:29:53.451875 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4784 16:29:53.451976 # ok 3057 Set Streaming SVE VL 4016
4785 16:29:53.457960 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4786 16:29:53.458426 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4787 16:29:53.458772 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4788 16:29:53.459140 # ok 3061 Set Streaming SVE VL 4032
4789 16:29:53.464874 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4790 16:29:53.465482 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4791 16:29:53.465837 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4792 16:29:53.466582 # ok 3065 Set Streaming SVE VL 4048
4793 16:29:53.469438 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4794 16:29:53.469692 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4795 16:29:53.469841 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4796 16:29:53.469965 # ok 3069 Set Streaming SVE VL 4064
4797 16:29:53.470374 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4798 16:29:53.489486 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4799 16:29:53.490107 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4800 16:29:53.490224 # ok 3073 Set Streaming SVE VL 4080
4801 16:29:53.490318 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4802 16:29:53.490738 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4803 16:29:53.490852 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4804 16:29:53.490947 # ok 3077 Set Streaming SVE VL 4096
4805 16:29:53.491256 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4806 16:29:53.491569 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4807 16:29:53.501279 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4808 16:29:53.501819 # ok 3081 Set Streaming SVE VL 4112
4809 16:29:53.502146 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4810 16:29:53.502465 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4811 16:29:53.502846 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4812 16:29:53.503244 # ok 3085 Set Streaming SVE VL 4128
4813 16:29:53.503356 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4814 16:29:53.503451 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4815 16:29:53.503695 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4816 16:29:53.517256 # ok 3089 Set Streaming SVE VL 4144
4817 16:29:53.517482 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4818 16:29:53.517575 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4819 16:29:53.518451 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4820 16:29:53.518562 # ok 3093 Set Streaming SVE VL 4160
4821 16:29:53.518653 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4822 16:29:53.518744 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4823 16:29:53.518833 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4824 16:29:53.519467 # ok 3097 Set Streaming SVE VL 4176
4825 16:29:53.519569 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4826 16:29:53.519661 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4827 16:29:53.519740 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4828 16:29:53.519816 # ok 3101 Set Streaming SVE VL 4192
4829 16:29:53.519891 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4830 16:29:53.519966 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4831 16:29:53.520041 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4832 16:29:53.538169 # ok 3105 Set Streaming SVE VL 4208
4833 16:29:53.539473 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4834 16:29:53.539580 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4835 16:29:53.539682 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4836 16:29:53.539773 # ok 3109 Set Streaming SVE VL 4224
4837 16:29:53.539862 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4838 16:29:53.539952 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4839 16:29:53.540041 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4840 16:29:53.540130 # ok 3113 Set Streaming SVE VL 4240
4841 16:29:53.540218 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4842 16:29:53.540307 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4843 16:29:53.540769 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4844 16:29:53.540878 # ok 3117 Set Streaming SVE VL 4256
4845 16:29:53.540969 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4846 16:29:53.541058 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4847 16:29:53.541148 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4848 16:29:53.541236 # ok 3121 Set Streaming SVE VL 4272
4849 16:29:53.541325 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4850 16:29:53.542223 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4851 16:29:53.543300 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4852 16:29:53.543985 # ok 3125 Set Streaming SVE VL 4288
4853 16:29:53.544601 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4854 16:29:53.544973 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4855 16:29:53.545263 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4856 16:29:53.545684 # ok 3129 Set Streaming SVE VL 4304
4857 16:29:53.545957 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4858 16:29:53.546116 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4859 16:29:53.546206 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4860 16:29:53.546285 # ok 3133 Set Streaming SVE VL 4320
4861 16:29:53.546362 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4862 16:29:53.546437 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4863 16:29:53.546514 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4864 16:29:53.546590 # ok 3137 Set Streaming SVE VL 4336
4865 16:29:53.546666 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4866 16:29:53.546742 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4867 16:29:53.547030 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4868 16:29:53.547136 # ok 3141 Set Streaming SVE VL 4352
4869 16:29:53.547216 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4870 16:29:53.547295 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4871 16:29:53.547372 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4872 16:29:53.547449 # ok 3145 Set Streaming SVE VL 4368
4873 16:29:53.547526 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4874 16:29:53.547604 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4875 16:29:53.547687 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4876 16:29:53.547769 # ok 3149 Set Streaming SVE VL 4384
4877 16:29:53.547846 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4878 16:29:53.547923 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4879 16:29:53.548000 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4880 16:29:53.548077 # ok 3153 Set Streaming SVE VL 4400
4881 16:29:53.548153 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4882 16:29:53.548229 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4883 16:29:53.548306 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4884 16:29:53.548383 # ok 3157 Set Streaming SVE VL 4416
4885 16:29:53.548460 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4886 16:29:53.548537 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4887 16:29:53.548616 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4888 16:29:53.548693 # ok 3161 Set Streaming SVE VL 4432
4889 16:29:53.548769 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4890 16:29:53.548845 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4891 16:29:53.548921 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4892 16:29:53.548998 # ok 3165 Set Streaming SVE VL 4448
4893 16:29:53.549074 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4894 16:29:53.549150 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4895 16:29:53.549243 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4896 16:29:53.549323 # ok 3169 Set Streaming SVE VL 4464
4897 16:29:53.549399 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4898 16:29:53.549476 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4899 16:29:53.549552 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4900 16:29:53.549633 # ok 3173 Set Streaming SVE VL 4480
4901 16:29:53.549721 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4902 16:29:53.550326 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4903 16:29:53.550457 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4904 16:29:53.550544 # ok 3177 Set Streaming SVE VL 4496
4905 16:29:53.583500 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4906 16:29:53.583713 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4907 16:29:53.591497 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4908 16:29:53.591716 # ok 3181 Set Streaming SVE VL 4512
4909 16:29:53.591800 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4910 16:29:53.594358 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4911 16:29:53.595759 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4912 16:29:53.595866 # ok 3185 Set Streaming SVE VL 4528
4913 16:29:53.595949 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4914 16:29:53.596028 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4915 16:29:53.596107 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4916 16:29:53.596185 # ok 3189 Set Streaming SVE VL 4544
4917 16:29:53.599602 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4918 16:29:53.599719 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4919 16:29:53.599799 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4920 16:29:53.599878 # ok 3193 Set Streaming SVE VL 4560
4921 16:29:53.599955 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4922 16:29:53.600032 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4923 16:29:53.600108 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4924 16:29:53.600185 # ok 3197 Set Streaming SVE VL 4576
4925 16:29:53.600261 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4926 16:29:53.600338 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4927 16:29:53.609397 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4928 16:29:53.609829 # ok 3201 Set Streaming SVE VL 4592
4929 16:29:53.609931 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4930 16:29:53.610032 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4931 16:29:53.610351 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4932 16:29:53.611396 # ok 3205 Set Streaming SVE VL 4608
4933 16:29:53.611699 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4934 16:29:53.611801 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4935 16:29:53.611883 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4936 16:29:53.611964 # ok 3209 Set Streaming SVE VL 4624
4937 16:29:53.612043 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4938 16:29:53.615433 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4939 16:29:53.615802 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4940 16:29:53.615909 # ok 3213 Set Streaming SVE VL 4640
4941 16:29:53.623593 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4942 16:29:53.623787 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4943 16:29:53.623870 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4944 16:29:53.623948 # ok 3217 Set Streaming SVE VL 4656
4945 16:29:53.624026 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4946 16:29:53.624104 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4947 16:29:53.624183 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4948 16:29:53.624261 # ok 3221 Set Streaming SVE VL 4672
4949 16:29:53.624339 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4950 16:29:53.624416 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4951 16:29:53.624494 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4952 16:29:53.624571 # ok 3225 Set Streaming SVE VL 4688
4953 16:29:53.624648 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4954 16:29:53.624725 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4955 16:29:53.624802 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4956 16:29:53.624880 # ok 3229 Set Streaming SVE VL 4704
4957 16:29:53.630826 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4958 16:29:53.631543 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4959 16:29:53.631640 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4960 16:29:53.631719 # ok 3233 Set Streaming SVE VL 4720
4961 16:29:53.631798 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4962 16:29:53.632167 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4963 16:29:53.632274 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4964 16:29:53.632355 # ok 3237 Set Streaming SVE VL 4736
4965 16:29:53.635318 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4966 16:29:53.635663 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4967 16:29:53.635759 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4968 16:29:53.635846 # ok 3241 Set Streaming SVE VL 4752
4969 16:29:53.635923 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4970 16:29:53.636000 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4971 16:29:53.636078 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4972 16:29:53.636156 # ok 3245 Set Streaming SVE VL 4768
4973 16:29:53.636233 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4974 16:29:53.636310 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4975 16:29:53.636386 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4976 16:29:53.636817 # ok 3249 Set Streaming SVE VL 4784
4977 16:29:53.636924 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4978 16:29:53.637005 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4979 16:29:53.637083 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4980 16:29:53.637160 # ok 3253 Set Streaming SVE VL 4800
4981 16:29:53.641373 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4982 16:29:53.642264 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4983 16:29:53.643069 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4984 16:29:53.643422 # ok 3257 Set Streaming SVE VL 4816
4985 16:29:53.643596 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4986 16:29:53.643874 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4987 16:29:53.649943 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4988 16:29:53.650867 # ok 3261 Set Streaming SVE VL 4832
4989 16:29:53.651659 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4990 16:29:53.651763 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4991 16:29:53.651852 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4992 16:29:53.651930 # ok 3265 Set Streaming SVE VL 4848
4993 16:29:53.652007 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4994 16:29:53.657986 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4995 16:29:53.659843 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4996 16:29:53.659949 # ok 3269 Set Streaming SVE VL 4864
4997 16:29:53.660031 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
4998 16:29:53.660109 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
4999 16:29:53.660187 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5000 16:29:53.660264 # ok 3273 Set Streaming SVE VL 4880
5001 16:29:53.660341 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5002 16:29:53.660422 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5003 16:29:53.660500 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5004 16:29:53.660577 # ok 3277 Set Streaming SVE VL 4896
5005 16:29:53.660653 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5006 16:29:53.660729 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5007 16:29:53.667505 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5008 16:29:53.667686 # ok 3281 Set Streaming SVE VL 4912
5009 16:29:53.667767 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5010 16:29:53.667849 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5011 16:29:53.667932 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5012 16:29:53.668009 # ok 3285 Set Streaming SVE VL 4928
5013 16:29:53.668086 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5014 16:29:53.668162 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5015 16:29:53.668239 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5016 16:29:53.668317 # ok 3289 Set Streaming SVE VL 4944
5017 16:29:53.668394 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5018 16:29:53.668858 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5019 16:29:53.668963 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5020 16:29:53.669044 # ok 3293 Set Streaming SVE VL 4960
5021 16:29:53.675704 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5022 16:29:53.675874 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5023 16:29:53.675956 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5024 16:29:53.676034 # ok 3297 Set Streaming SVE VL 4976
5025 16:29:53.676111 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5026 16:29:53.676189 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5027 16:29:53.676265 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5028 16:29:53.676347 # ok 3301 Set Streaming SVE VL 4992
5029 16:29:53.676424 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5030 16:29:53.676502 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5031 16:29:53.676579 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5032 16:29:53.676656 # ok 3305 Set Streaming SVE VL 5008
5033 16:29:53.683823 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5034 16:29:53.683993 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5035 16:29:53.684075 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5036 16:29:53.684153 # ok 3309 Set Streaming SVE VL 5024
5037 16:29:53.684230 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5038 16:29:53.684307 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5039 16:29:53.684385 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5040 16:29:53.684462 # ok 3313 Set Streaming SVE VL 5040
5041 16:29:53.684539 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5042 16:29:53.684615 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5043 16:29:53.684691 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5044 16:29:53.684768 # ok 3317 Set Streaming SVE VL 5056
5045 16:29:53.684844 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5046 16:29:53.684920 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5047 16:29:53.684997 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5048 16:29:53.685074 # ok 3321 Set Streaming SVE VL 5072
5049 16:29:53.685150 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5050 16:29:53.686377 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5051 16:29:53.686673 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5052 16:29:53.686772 # ok 3325 Set Streaming SVE VL 5088
5053 16:29:53.686852 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5054 16:29:53.699605 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5055 16:29:53.699834 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5056 16:29:53.699918 # ok 3329 Set Streaming SVE VL 5104
5057 16:29:53.699995 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5058 16:29:53.700071 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5059 16:29:53.700145 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5060 16:29:53.700220 # ok 3333 Set Streaming SVE VL 5120
5061 16:29:53.700297 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5062 16:29:53.700373 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5063 16:29:53.700449 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5064 16:29:53.700528 # ok 3337 Set Streaming SVE VL 5136
5065 16:29:53.700604 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5066 16:29:53.706771 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5067 16:29:53.706958 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5068 16:29:53.707050 # ok 3341 Set Streaming SVE VL 5152
5069 16:29:53.707138 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5070 16:29:53.707226 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5071 16:29:53.707315 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5072 16:29:53.707611 # ok 3345 Set Streaming SVE VL 5168
5073 16:29:53.707709 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5074 16:29:53.707788 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5075 16:29:53.707866 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5076 16:29:53.707942 # ok 3349 Set Streaming SVE VL 5184
5077 16:29:53.710024 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5078 16:29:53.710131 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5079 16:29:53.710219 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5080 16:29:53.710307 # ok 3353 Set Streaming SVE VL 5200
5081 16:29:53.710393 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5082 16:29:53.710481 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5083 16:29:53.710566 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5084 16:29:53.710652 # ok 3357 Set Streaming SVE VL 5216
5085 16:29:53.710938 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5086 16:29:53.711044 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5087 16:29:53.711134 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5088 16:29:53.711221 # ok 3361 Set Streaming SVE VL 5232
5089 16:29:53.711309 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5090 16:29:53.711397 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5091 16:29:53.711501 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5092 16:29:53.711586 # ok 3365 Set Streaming SVE VL 5248
5093 16:29:53.711665 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5094 16:29:53.711741 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5095 16:29:53.714832 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5096 16:29:53.715493 # ok 3369 Set Streaming SVE VL 5264
5097 16:29:53.715591 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5098 16:29:53.715668 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5099 16:29:53.715743 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5100 16:29:53.715817 # ok 3373 Set Streaming SVE VL 5280
5101 16:29:53.716974 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5102 16:29:53.717081 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5103 16:29:53.717172 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5104 16:29:53.717261 # ok 3377 Set Streaming SVE VL 5296
5105 16:29:53.717347 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5106 16:29:53.717823 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5107 16:29:53.717932 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5108 16:29:53.718028 # ok 3381 Set Streaming SVE VL 5312
5109 16:29:53.718116 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5110 16:29:53.718203 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5111 16:29:53.718487 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5112 16:29:53.718595 # ok 3385 Set Streaming SVE VL 5328
5113 16:29:53.719569 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5114 16:29:53.719679 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5115 16:29:53.719767 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5116 16:29:53.719844 # ok 3389 Set Streaming SVE VL 5344
5117 16:29:53.719921 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5118 16:29:53.719998 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5119 16:29:53.720073 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5120 16:29:53.720149 # ok 3393 Set Streaming SVE VL 5360
5121 16:29:53.720419 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5122 16:29:53.728755 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5123 16:29:53.729161 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5124 16:29:53.729270 # ok 3397 Set Streaming SVE VL 5376
5125 16:29:53.729603 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5126 16:29:53.729722 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5127 16:29:53.729818 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5128 16:29:53.730121 # ok 3401 Set Streaming SVE VL 5392
5129 16:29:53.730444 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5130 16:29:53.730551 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5131 16:29:53.730675 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5132 16:29:53.731072 # ok 3405 Set Streaming SVE VL 5408
5133 16:29:53.731178 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5134 16:29:53.731472 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5135 16:29:53.731575 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5136 16:29:53.731651 # ok 3409 Set Streaming SVE VL 5424
5137 16:29:53.731737 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5138 16:29:53.739488 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5139 16:29:53.739670 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5140 16:29:53.739753 # ok 3413 Set Streaming SVE VL 5440
5141 16:29:53.739831 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5142 16:29:53.739907 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5143 16:29:53.739982 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5144 16:29:53.740540 # ok 3417 Set Streaming SVE VL 5456
5145 16:29:53.740650 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5146 16:29:53.740936 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5147 16:29:53.741259 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5148 16:29:53.741571 # ok 3421 Set Streaming SVE VL 5472
5149 16:29:53.741681 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5150 16:29:53.741983 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5151 16:29:53.742092 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5152 16:29:53.742388 # ok 3425 Set Streaming SVE VL 5488
5153 16:29:53.742498 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5154 16:29:53.742603 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5155 16:29:53.742731 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5156 16:29:53.743072 # ok 3429 Set Streaming SVE VL 5504
5157 16:29:53.743552 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5158 16:29:53.743655 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5159 16:29:53.751553 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5160 16:29:53.752753 # ok 3433 Set Streaming SVE VL 5520
5161 16:29:53.752864 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5162 16:29:53.753154 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5163 16:29:53.753464 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5164 16:29:53.753569 # ok 3437 Set Streaming SVE VL 5536
5165 16:29:53.753664 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5166 16:29:53.753954 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5167 16:29:53.754376 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5168 16:29:53.754483 # ok 3441 Set Streaming SVE VL 5552
5169 16:29:53.754572 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5170 16:29:53.755515 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5171 16:29:53.755624 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5172 16:29:53.755710 # ok 3445 Set Streaming SVE VL 5568
5173 16:29:53.755787 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5174 16:29:53.755864 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5175 16:29:53.755939 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5176 16:29:53.756015 # ok 3449 Set Streaming SVE VL 5584
5177 16:29:53.756093 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5178 16:29:53.765743 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5179 16:29:53.765965 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5180 16:29:53.766564 # ok 3453 Set Streaming SVE VL 5600
5181 16:29:53.766672 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5182 16:29:53.766763 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5183 16:29:53.766850 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5184 16:29:53.766938 # ok 3457 Set Streaming SVE VL 5616
5185 16:29:53.767028 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5186 16:29:53.767115 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5187 16:29:53.767403 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5188 16:29:53.767510 # ok 3461 Set Streaming SVE VL 5632
5189 16:29:53.767598 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5190 16:29:53.767679 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5191 16:29:53.767772 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5192 16:29:53.767850 # ok 3465 Set Streaming SVE VL 5648
5193 16:29:53.767927 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5194 16:29:53.768008 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5195 16:29:53.781918 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5196 16:29:53.782154 # ok 3469 Set Streaming SVE VL 5664
5197 16:29:53.782247 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5198 16:29:53.782335 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5199 16:29:53.782633 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5200 16:29:53.782732 # ok 3473 Set Streaming SVE VL 5680
5201 16:29:53.782813 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5202 16:29:53.782891 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5203 16:29:53.793344 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5204 16:29:53.794411 # ok 3477 Set Streaming SVE VL 5696
5205 16:29:53.794544 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5206 16:29:53.794640 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5207 16:29:53.794728 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5208 16:29:53.794817 # ok 3481 Set Streaming SVE VL 5712
5209 16:29:53.794904 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5210 16:29:53.794992 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5211 16:29:53.795099 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5212 16:29:53.795205 # ok 3485 Set Streaming SVE VL 5728
5213 16:29:53.795293 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5214 16:29:53.795381 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5215 16:29:53.795486 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5216 16:29:53.795612 # ok 3489 Set Streaming SVE VL 5744
5217 16:29:53.795705 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5218 16:29:53.805410 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5219 16:29:53.805642 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5220 16:29:53.805745 # ok 3493 Set Streaming SVE VL 5760
5221 16:29:53.805835 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5222 16:29:53.806228 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5223 16:29:53.806336 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5224 16:29:53.806427 # ok 3497 Set Streaming SVE VL 5776
5225 16:29:53.806516 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5226 16:29:53.806605 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5227 16:29:53.806939 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5228 16:29:53.807048 # ok 3501 Set Streaming SVE VL 5792
5229 16:29:53.807141 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5230 16:29:53.807229 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5231 16:29:53.807533 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5232 16:29:53.807632 # ok 3505 Set Streaming SVE VL 5808
5233 16:29:53.807710 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5234 16:29:53.817019 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5235 16:29:53.817642 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5236 16:29:53.817756 # ok 3509 Set Streaming SVE VL 5824
5237 16:29:53.817839 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5238 16:29:53.817921 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5239 16:29:53.819445 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5240 16:29:53.819552 # ok 3513 Set Streaming SVE VL 5840
5241 16:29:53.819633 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5242 16:29:53.819710 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5243 16:29:53.819786 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5244 16:29:53.819864 # ok 3517 Set Streaming SVE VL 5856
5245 16:29:53.819941 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5246 16:29:53.820018 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5247 16:29:53.820093 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5248 16:29:53.820170 # ok 3521 Set Streaming SVE VL 5872
5249 16:29:53.820246 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5250 16:29:53.820321 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5251 16:29:53.831568 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5252 16:29:53.831799 # ok 3525 Set Streaming SVE VL 5888
5253 16:29:53.831881 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5254 16:29:53.831958 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5255 16:29:53.832033 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5256 16:29:53.832108 # ok 3529 Set Streaming SVE VL 5904
5257 16:29:53.832184 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5258 16:29:53.832260 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5259 16:29:53.832340 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5260 16:29:53.832419 # ok 3533 Set Streaming SVE VL 5920
5261 16:29:53.832495 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5262 16:29:53.832570 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5263 16:29:53.832651 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5264 16:29:53.832732 # ok 3537 Set Streaming SVE VL 5936
5265 16:29:53.832812 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5266 16:29:53.832887 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5267 16:29:53.833312 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5268 16:29:53.845362 # ok 3541 Set Streaming SVE VL 5952
5269 16:29:53.847721 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5270 16:29:53.847822 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5271 16:29:53.847905 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5272 16:29:53.847982 # ok 3545 Set Streaming SVE VL 5968
5273 16:29:53.848059 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5274 16:29:53.848134 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5275 16:29:53.848213 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5276 16:29:53.848288 # ok 3549 Set Streaming SVE VL 5984
5277 16:29:53.848364 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5278 16:29:53.848438 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5279 16:29:53.848514 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5280 16:29:53.848592 # ok 3553 Set Streaming SVE VL 6000
5281 16:29:53.848670 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5282 16:29:53.848749 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5283 16:29:53.859602 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5284 16:29:53.859829 # ok 3557 Set Streaming SVE VL 6016
5285 16:29:53.859912 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5286 16:29:53.859988 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5287 16:29:53.860065 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5288 16:29:53.860140 # ok 3561 Set Streaming SVE VL 6032
5289 16:29:53.860218 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5290 16:29:53.860296 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5291 16:29:53.860372 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5292 16:29:53.860453 # ok 3565 Set Streaming SVE VL 6048
5293 16:29:53.860532 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5294 16:29:53.861031 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5295 16:29:53.861133 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5296 16:29:53.861217 # ok 3569 Set Streaming SVE VL 6064
5297 16:29:53.861291 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5298 16:29:53.861364 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5299 16:29:53.861437 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5300 16:29:53.871562 # ok 3573 Set Streaming SVE VL 6080
5301 16:29:53.871785 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5302 16:29:53.871865 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5303 16:29:53.871942 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5304 16:29:53.872018 # ok 3577 Set Streaming SVE VL 6096
5305 16:29:53.872091 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5306 16:29:53.872164 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5307 16:29:53.872237 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5308 16:29:53.872311 # ok 3581 Set Streaming SVE VL 6112
5309 16:29:53.872383 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5310 16:29:53.872456 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5311 16:29:53.872530 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5312 16:29:53.872608 # ok 3585 Set Streaming SVE VL 6128
5313 16:29:53.872685 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5314 16:29:53.872760 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5315 16:29:53.875933 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5316 16:29:53.876035 # ok 3589 Set Streaming SVE VL 6144
5317 16:29:53.876113 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5318 16:29:53.876193 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5319 16:29:53.876281 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5320 16:29:53.876358 # ok 3593 Set Streaming SVE VL 6160
5321 16:29:53.876441 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5322 16:29:53.876524 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5323 16:29:53.876605 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5324 16:29:53.876688 # ok 3597 Set Streaming SVE VL 6176
5325 16:29:53.876772 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5326 16:29:53.876849 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5327 16:29:53.876932 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5328 16:29:53.877012 # ok 3601 Set Streaming SVE VL 6192
5329 16:29:53.877088 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5330 16:29:53.877162 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5331 16:29:53.877235 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5332 16:29:53.877309 # ok 3605 Set Streaming SVE VL 6208
5333 16:29:53.877382 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5334 16:29:53.877454 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5335 16:29:53.881401 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5336 16:29:53.883691 # ok 3609 Set Streaming SVE VL 6224
5337 16:29:53.883823 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5338 16:29:53.883908 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5339 16:29:53.883985 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5340 16:29:53.884062 # ok 3613 Set Streaming SVE VL 6240
5341 16:29:53.884137 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5342 16:29:53.884213 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5343 16:29:53.884287 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5344 16:29:53.888454 # ok 3617 Set Streaming SVE VL 6256
5345 16:29:53.889818 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5346 16:29:53.890672 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5347 16:29:53.890769 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5348 16:29:53.891061 # ok 3621 Set Streaming SVE VL 6272
5349 16:29:53.891158 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5350 16:29:53.891247 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5351 16:29:53.891332 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5352 16:29:53.891417 # ok 3625 Set Streaming SVE VL 6288
5353 16:29:53.950142 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5354 16:29:53.950863 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5355 16:29:53.951144 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5356 16:29:53.951255 # ok 3629 Set Streaming SVE VL 6304
5357 16:29:53.951347 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5358 16:29:53.951451 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5359 16:29:53.951542 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5360 16:29:53.951648 # ok 3633 Set Streaming SVE VL 6320
5361 16:29:53.951740 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5362 16:29:53.953664 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5363 16:29:53.954259 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5364 16:29:53.954394 # ok 3637 Set Streaming SVE VL 6336
5365 16:29:53.954500 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5366 16:29:53.954605 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5367 16:29:53.954713 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5368 16:29:53.954802 # ok 3641 Set Streaming SVE VL 6352
5369 16:29:53.954904 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5370 16:29:53.955212 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5371 16:29:53.955318 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5372 16:29:53.955619 # ok 3645 Set Streaming SVE VL 6368
5373 16:29:53.955729 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5374 16:29:53.957458 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5375 16:29:53.957747 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5376 16:29:53.957844 # ok 3649 Set Streaming SVE VL 6384
5377 16:29:53.958330 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5378 16:29:53.959002 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5379 16:29:53.959290 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5380 16:29:53.959383 # ok 3653 Set Streaming SVE VL 6400
5381 16:29:53.959470 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5382 16:29:53.959564 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5383 16:29:53.959674 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5384 16:29:53.959764 # ok 3657 Set Streaming SVE VL 6416
5385 16:29:53.959849 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5386 16:29:53.959934 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5387 16:29:53.960018 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5388 16:29:53.960104 # ok 3661 Set Streaming SVE VL 6432
5389 16:29:53.960189 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5390 16:29:53.964372 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5391 16:29:53.964733 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5392 16:29:53.965192 # ok 3665 Set Streaming SVE VL 6448
5393 16:29:53.965351 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5394 16:29:53.965516 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5395 16:29:53.965797 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5396 16:29:53.965912 # ok 3669 Set Streaming SVE VL 6464
5397 16:29:53.966004 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5398 16:29:53.966091 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5399 16:29:53.966179 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5400 16:29:53.966265 # ok 3673 Set Streaming SVE VL 6480
5401 16:29:53.966368 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5402 16:29:53.966458 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5403 16:29:53.966844 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5404 16:29:53.966953 # ok 3677 Set Streaming SVE VL 6496
5405 16:29:53.967042 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5406 16:29:53.967128 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5407 16:29:53.967416 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5408 16:29:53.967521 # ok 3681 Set Streaming SVE VL 6512
5409 16:29:53.967611 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5410 16:29:53.967711 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5411 16:29:53.970527 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5412 16:29:53.970636 # ok 3685 Set Streaming SVE VL 6528
5413 16:29:53.970727 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5414 16:29:53.970815 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5415 16:29:53.970902 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5416 16:29:53.970990 # ok 3689 Set Streaming SVE VL 6544
5417 16:29:53.971075 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5418 16:29:53.971361 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5419 16:29:53.971466 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5420 16:29:53.971559 # ok 3693 Set Streaming SVE VL 6560
5421 16:29:53.971646 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5422 16:29:53.971729 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5423 16:29:53.971827 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5424 16:29:53.972401 # ok 3697 Set Streaming SVE VL 6576
5425 16:29:53.972706 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5426 16:29:53.972812 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5427 16:29:53.973325 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5428 16:29:53.973432 # ok 3701 Set Streaming SVE VL 6592
5429 16:29:53.973521 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5430 16:29:53.973861 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5431 16:29:53.973968 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5432 16:29:53.974058 # ok 3705 Set Streaming SVE VL 6608
5433 16:29:53.974145 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5434 16:29:53.974429 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5435 16:29:53.974536 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5436 16:29:53.974825 # ok 3709 Set Streaming SVE VL 6624
5437 16:29:53.974930 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5438 16:29:53.975221 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5439 16:29:53.975326 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5440 16:29:53.975417 # ok 3713 Set Streaming SVE VL 6640
5441 16:29:53.975504 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5442 16:29:53.975610 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5443 16:29:53.975698 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5444 16:29:53.984991 # ok 3717 Set Streaming SVE VL 6656
5445 16:29:53.985135 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5446 16:29:53.985476 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5447 16:29:53.985582 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5448 16:29:53.985678 # ok 3721 Set Streaming SVE VL 6672
5449 16:29:53.985968 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5450 16:29:53.986078 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5451 16:29:53.986354 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5452 16:29:53.986465 # ok 3725 Set Streaming SVE VL 6688
5453 16:29:53.986555 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5454 16:29:53.986855 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5455 16:29:53.986963 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5456 16:29:53.987051 # ok 3729 Set Streaming SVE VL 6704
5457 16:29:53.987137 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5458 16:29:53.987421 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5459 16:29:53.987543 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5460 16:29:53.987649 # ok 3733 Set Streaming SVE VL 6720
5461 16:29:53.987774 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5462 16:29:53.991968 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5463 16:29:53.992285 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5464 16:29:53.992391 # ok 3737 Set Streaming SVE VL 6736
5465 16:29:53.992669 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5466 16:29:53.993021 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5467 16:29:53.993120 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5468 16:29:53.993202 # ok 3741 Set Streaming SVE VL 6752
5469 16:29:53.993279 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5470 16:29:53.993561 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5471 16:29:53.993879 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5472 16:29:53.993978 # ok 3745 Set Streaming SVE VL 6768
5473 16:29:53.994058 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5474 16:29:53.994135 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5475 16:29:53.994420 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5476 16:29:53.994533 # ok 3749 Set Streaming SVE VL 6784
5477 16:29:53.994916 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5478 16:29:53.995018 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5479 16:29:53.995098 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5480 16:29:53.995175 # ok 3753 Set Streaming SVE VL 6800
5481 16:29:53.995252 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5482 16:29:53.995328 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5483 16:29:53.995404 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5484 16:29:53.995484 # ok 3757 Set Streaming SVE VL 6816
5485 16:29:53.995760 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5486 16:29:53.995862 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5487 16:29:53.995944 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5488 16:29:53.996023 # ok 3761 Set Streaming SVE VL 6832
5489 16:29:53.996101 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5490 16:29:53.998242 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5491 16:29:53.998528 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5492 16:29:53.998955 # ok 3765 Set Streaming SVE VL 6848
5493 16:29:53.999052 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5494 16:29:53.999349 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5495 16:29:53.999447 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5496 16:29:53.999529 # ok 3769 Set Streaming SVE VL 6864
5497 16:29:53.999807 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5498 16:29:54.007727 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5499 16:29:54.013348 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5500 16:29:54.013701 # ok 3773 Set Streaming SVE VL 6880
5501 16:29:54.013804 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5502 16:29:54.022000 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5503 16:29:54.023465 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5504 16:29:54.023937 # ok 3777 Set Streaming SVE VL 6896
5505 16:29:54.024046 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5506 16:29:54.024131 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5507 16:29:54.024215 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5508 16:29:54.024302 # ok 3781 Set Streaming SVE VL 6912
5509 16:29:54.024385 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5510 16:29:54.024469 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5511 16:29:54.024550 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5512 16:29:54.033088 # ok 3785 Set Streaming SVE VL 6928
5513 16:29:54.034028 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5514 16:29:54.034133 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5515 16:29:54.034479 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5516 16:29:54.034590 # ok 3789 Set Streaming SVE VL 6944
5517 16:29:54.034681 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5518 16:29:54.034770 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5519 16:29:54.034859 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5520 16:29:54.034948 # ok 3793 Set Streaming SVE VL 6960
5521 16:29:54.035036 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5522 16:29:54.035143 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5523 16:29:54.035235 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5524 16:29:54.035325 # ok 3797 Set Streaming SVE VL 6976
5525 16:29:54.035414 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5526 16:29:54.035501 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5527 16:29:54.035944 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5528 16:29:54.036051 # ok 3801 Set Streaming SVE VL 6992
5529 16:29:54.036134 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5530 16:29:54.036213 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5531 16:29:54.036293 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5532 16:29:54.036372 # ok 3805 Set Streaming SVE VL 7008
5533 16:29:54.036450 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5534 16:29:54.036530 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5535 16:29:54.041304 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5536 16:29:54.041421 # ok 3809 Set Streaming SVE VL 7024
5537 16:29:54.041502 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5538 16:29:54.041581 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5539 16:29:54.043672 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5540 16:29:54.043776 # ok 3813 Set Streaming SVE VL 7040
5541 16:29:54.043856 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5542 16:29:54.043936 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5543 16:29:54.044014 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5544 16:29:54.044092 # ok 3817 Set Streaming SVE VL 7056
5545 16:29:54.044169 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5546 16:29:54.044247 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5547 16:29:54.044325 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5548 16:29:54.044403 # ok 3821 Set Streaming SVE VL 7072
5549 16:29:54.044679 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5550 16:29:54.044785 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5551 16:29:54.044874 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5552 16:29:54.044960 # ok 3825 Set Streaming SVE VL 7088
5553 16:29:54.045045 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5554 16:29:54.051550 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5555 16:29:54.051671 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5556 16:29:54.051784 # ok 3829 Set Streaming SVE VL 7104
5557 16:29:54.051879 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5558 16:29:54.051967 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5559 16:29:54.052052 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5560 16:29:54.052138 # ok 3833 Set Streaming SVE VL 7120
5561 16:29:54.052225 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5562 16:29:54.052311 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5563 16:29:54.052399 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5564 16:29:54.052485 # ok 3837 Set Streaming SVE VL 7136
5565 16:29:54.052571 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5566 16:29:54.052656 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5567 16:29:54.052739 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5568 16:29:54.052825 # ok 3841 Set Streaming SVE VL 7152
5569 16:29:54.052906 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5570 16:29:54.052991 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5571 16:29:54.053076 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5572 16:29:54.053161 # ok 3845 Set Streaming SVE VL 7168
5573 16:29:54.053247 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5574 16:29:54.053332 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5575 16:29:54.053419 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5576 16:29:54.053501 # ok 3849 Set Streaming SVE VL 7184
5577 16:29:54.054003 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5578 16:29:54.056799 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5579 16:29:54.057347 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5580 16:29:54.058765 # ok 3853 Set Streaming SVE VL 7200
5581 16:29:54.059769 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5582 16:29:54.059876 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5583 16:29:54.059965 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5584 16:29:54.060053 # ok 3857 Set Streaming SVE VL 7216
5585 16:29:54.060137 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5586 16:29:54.060222 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5587 16:29:54.060306 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5588 16:29:54.060391 # ok 3861 Set Streaming SVE VL 7232
5589 16:29:54.060481 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5590 16:29:54.060567 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5591 16:29:54.060652 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5592 16:29:54.060737 # ok 3865 Set Streaming SVE VL 7248
5593 16:29:54.060823 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5594 16:29:54.068005 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5595 16:29:54.070047 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5596 16:29:54.070613 # ok 3869 Set Streaming SVE VL 7264
5597 16:29:54.071509 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5598 16:29:54.071777 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5599 16:29:54.071874 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5600 16:29:54.071961 # ok 3873 Set Streaming SVE VL 7280
5601 16:29:54.072047 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5602 16:29:54.072132 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5603 16:29:54.072218 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5604 16:29:54.072304 # ok 3877 Set Streaming SVE VL 7296
5605 16:29:54.072390 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5606 16:29:54.072476 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5607 16:29:54.072579 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5608 16:29:54.072677 # ok 3881 Set Streaming SVE VL 7312
5609 16:29:54.072763 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5610 16:29:54.072851 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5611 16:29:54.072939 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5612 16:29:54.073025 # ok 3885 Set Streaming SVE VL 7328
5613 16:29:54.073110 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5614 16:29:54.073195 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5615 16:29:54.073279 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5616 16:29:54.073365 # ok 3889 Set Streaming SVE VL 7344
5617 16:29:54.075925 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5618 16:29:54.076474 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5619 16:29:54.077021 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5620 16:29:54.077473 # ok 3893 Set Streaming SVE VL 7360
5621 16:29:54.077934 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5622 16:29:54.078652 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5623 16:29:54.079190 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5624 16:29:54.079804 # ok 3897 Set Streaming SVE VL 7376
5625 16:29:54.079910 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5626 16:29:54.080001 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5627 16:29:54.080111 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5628 16:29:54.080199 # ok 3901 Set Streaming SVE VL 7392
5629 16:29:54.080284 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5630 16:29:54.080370 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5631 16:29:54.080457 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5632 16:29:54.080543 # ok 3905 Set Streaming SVE VL 7408
5633 16:29:54.080629 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5634 16:29:54.080714 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5635 16:29:54.080801 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5636 16:29:54.080887 # ok 3909 Set Streaming SVE VL 7424
5637 16:29:54.080973 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5638 16:29:54.081059 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5639 16:29:54.081144 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5640 16:29:54.081230 # ok 3913 Set Streaming SVE VL 7440
5641 16:29:54.081316 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5642 16:29:54.082924 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5643 16:29:54.083775 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5644 16:29:54.084052 # ok 3917 Set Streaming SVE VL 7456
5645 16:29:54.084241 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5646 16:29:54.084334 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5647 16:29:54.084416 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5648 16:29:54.084499 # ok 3921 Set Streaming SVE VL 7472
5649 16:29:54.084605 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5650 16:29:54.084693 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5651 16:29:54.084772 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5652 16:29:54.085634 # ok 3925 Set Streaming SVE VL 7488
5653 16:29:54.086135 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5654 16:29:54.086401 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5655 16:29:54.086566 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5656 16:29:54.086888 # ok 3929 Set Streaming SVE VL 7504
5657 16:29:54.087077 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5658 16:29:54.087247 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5659 16:29:54.087440 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5660 16:29:54.087633 # ok 3933 Set Streaming SVE VL 7520
5661 16:29:54.087843 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5662 16:29:54.088134 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5663 16:29:54.088330 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5664 16:29:54.088533 # ok 3937 Set Streaming SVE VL 7536
5665 16:29:54.088651 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5666 16:29:54.088743 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5667 16:29:54.088830 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5668 16:29:54.088917 # ok 3941 Set Streaming SVE VL 7552
5669 16:29:54.089023 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5670 16:29:54.089112 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5671 16:29:54.089200 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5672 16:29:54.089301 # ok 3945 Set Streaming SVE VL 7568
5673 16:29:54.089391 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5674 16:29:54.089494 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5675 16:29:54.089584 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5676 16:29:54.089692 # ok 3949 Set Streaming SVE VL 7584
5677 16:29:54.090010 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5678 16:29:54.090115 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5679 16:29:54.090219 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5680 16:29:54.090327 # ok 3953 Set Streaming SVE VL 7600
5681 16:29:54.090615 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5682 16:29:54.090719 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5683 16:29:54.090822 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5684 16:29:54.090913 # ok 3957 Set Streaming SVE VL 7616
5685 16:29:54.091301 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5686 16:29:54.091409 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5687 16:29:54.091697 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5688 16:29:54.091801 # ok 3961 Set Streaming SVE VL 7632
5689 16:29:54.091890 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5690 16:29:54.091991 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5691 16:29:54.092081 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5692 16:29:54.092167 # ok 3965 Set Streaming SVE VL 7648
5693 16:29:54.092267 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5694 16:29:54.092370 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5695 16:29:54.092657 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5696 16:29:54.092968 # ok 3969 Set Streaming SVE VL 7664
5697 16:29:54.093071 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5698 16:29:54.093364 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5699 16:29:54.093472 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5700 16:29:54.093561 # ok 3973 Set Streaming SVE VL 7680
5701 16:29:54.093670 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5702 16:29:54.093762 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5703 16:29:54.093896 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5704 16:29:54.094045 # ok 3977 Set Streaming SVE VL 7696
5705 16:29:54.094161 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5706 16:29:54.094268 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5707 16:29:54.094573 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5708 16:29:54.094678 # ok 3981 Set Streaming SVE VL 7712
5709 16:29:54.094964 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5710 16:29:54.095066 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5711 16:29:54.095169 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5712 16:29:54.095256 # ok 3985 Set Streaming SVE VL 7728
5713 16:29:54.095546 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5714 16:29:54.095650 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5715 16:29:54.095758 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5716 16:29:54.096045 # ok 3989 Set Streaming SVE VL 7744
5717 16:29:54.096149 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5718 16:29:54.096251 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5719 16:29:54.096340 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5720 16:29:54.096630 # ok 3993 Set Streaming SVE VL 7760
5721 16:29:54.096734 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5722 16:29:54.097002 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5723 16:29:54.097172 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5724 16:29:54.097351 # ok 3997 Set Streaming SVE VL 7776
5725 16:29:54.097802 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5726 16:29:54.097974 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5727 16:29:54.098067 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5728 16:29:54.098155 # ok 4001 Set Streaming SVE VL 7792
5729 16:29:54.098240 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5730 16:29:54.098326 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5731 16:29:54.112149 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5732 16:29:54.112852 # ok 4005 Set Streaming SVE VL 7808
5733 16:29:54.112957 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5734 16:29:54.113049 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5735 16:29:54.113138 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5736 16:29:54.113225 # ok 4009 Set Streaming SVE VL 7824
5737 16:29:54.113652 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5738 16:29:54.113758 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5739 16:29:54.113849 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5740 16:29:54.113944 # ok 4013 Set Streaming SVE VL 7840
5741 16:29:54.114032 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5742 16:29:54.115681 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5743 16:29:54.115785 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5744 16:29:54.115872 # ok 4017 Set Streaming SVE VL 7856
5745 16:29:54.115960 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5746 16:29:54.116048 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5747 16:29:54.116133 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5748 16:29:54.116218 # ok 4021 Set Streaming SVE VL 7872
5749 16:29:54.116302 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5750 16:29:54.116387 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5751 16:29:54.116470 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5752 16:29:54.116553 # ok 4025 Set Streaming SVE VL 7888
5753 16:29:54.116636 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5754 16:29:54.120099 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5755 16:29:54.121184 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5756 16:29:54.121288 # ok 4029 Set Streaming SVE VL 7904
5757 16:29:54.121382 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5758 16:29:54.121471 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5759 16:29:54.121562 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5760 16:29:54.121661 # ok 4033 Set Streaming SVE VL 7920
5761 16:29:54.121915 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5762 16:29:54.122019 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5763 16:29:54.122110 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5764 16:29:54.122197 # ok 4037 Set Streaming SVE VL 7936
5765 16:29:54.122580 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5766 16:29:54.122683 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5767 16:29:54.122772 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5768 16:29:54.122859 # ok 4041 Set Streaming SVE VL 7952
5769 16:29:54.122960 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5770 16:29:54.123384 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5771 16:29:54.123599 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5772 16:29:54.123693 # ok 4045 Set Streaming SVE VL 7968
5773 16:29:54.123816 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5774 16:29:54.123916 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5775 16:29:54.132094 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5776 16:29:54.132453 # ok 4049 Set Streaming SVE VL 7984
5777 16:29:54.132764 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5778 16:29:54.133161 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5779 16:29:54.133267 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5780 16:29:54.133358 # ok 4053 Set Streaming SVE VL 8000
5781 16:29:54.133678 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5782 16:29:54.133782 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5783 16:29:54.133872 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5784 16:29:54.133974 # ok 4057 Set Streaming SVE VL 8016
5785 16:29:54.134265 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5786 16:29:54.134369 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5787 16:29:54.134673 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5788 16:29:54.134779 # ok 4061 Set Streaming SVE VL 8032
5789 16:29:54.134882 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5790 16:29:54.134983 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5791 16:29:54.135275 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5792 16:29:54.135578 # ok 4065 Set Streaming SVE VL 8048
5793 16:29:54.135696 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5794 16:29:54.140378 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5795 16:29:54.140705 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5796 16:29:54.140809 # ok 4069 Set Streaming SVE VL 8064
5797 16:29:54.141101 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5798 16:29:54.141206 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5799 16:29:54.141309 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5800 16:29:54.141394 # ok 4073 Set Streaming SVE VL 8080
5801 16:29:54.141491 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5802 16:29:54.142425 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5803 16:29:54.142532 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5804 16:29:54.142820 # ok 4077 Set Streaming SVE VL 8096
5805 16:29:54.142926 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5806 16:29:54.143018 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5807 16:29:54.143628 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5808 16:29:54.143739 # ok 4081 Set Streaming SVE VL 8112
5809 16:29:54.143826 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5810 16:29:54.143908 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5811 16:29:54.143995 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5812 16:29:54.144079 # ok 4085 Set Streaming SVE VL 8128
5813 16:29:54.144163 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5814 16:29:54.144247 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5815 16:29:54.148642 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5816 16:29:54.150887 # ok 4089 Set Streaming SVE VL 8144
5817 16:29:54.151317 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5818 16:29:54.151418 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5819 16:29:54.151501 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5820 16:29:54.151581 # ok 4093 Set Streaming SVE VL 8160
5821 16:29:54.151659 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5822 16:29:54.151738 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5823 16:29:54.151827 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5824 16:29:54.151904 # ok 4097 Set Streaming SVE VL 8176
5825 16:29:54.151982 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5826 16:29:54.152060 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5827 16:29:54.152139 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5828 16:29:54.152217 # ok 4101 Set Streaming SVE VL 8192
5829 16:29:54.152295 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5830 16:29:54.152372 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5831 16:29:54.152451 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5832 16:29:54.152529 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5833 16:29:54.152608 ok 30 selftests: arm64: sve-ptrace
5834 16:29:54.152688 # selftests: arm64: sve-probe-vls
5835 16:29:54.152766 # TAP version 13
5836 16:29:54.152844 # 1..2
5837 16:29:54.152922 # ok 1 Enumerated 16 vector lengths
5838 16:29:54.152999 # ok 2 All vector lengths valid
5839 16:29:54.153077 # # 16
5840 16:29:54.153155 # # 32
5841 16:29:54.153232 # # 48
5842 16:29:54.153309 # # 64
5843 16:29:54.153386 # # 80
5844 16:29:54.153464 # # 96
5845 16:29:54.153540 # # 112
5846 16:29:54.153618 # # 128
5847 16:29:54.153705 # # 144
5848 16:29:54.153784 # # 160
5849 16:29:54.153861 # # 176
5850 16:29:54.153939 # # 192
5851 16:29:54.154017 # # 208
5852 16:29:54.154094 # # 224
5853 16:29:54.154171 # # 240
5854 16:29:54.154248 # # 256
5855 16:29:54.154325 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5856 16:29:54.154620 ok 31 selftests: arm64: sve-probe-vls
5857 16:29:54.231726 # selftests: arm64: vec-syscfg
5858 16:29:56.006321 # TAP version 13
5859 16:29:56.007015 # 1..20
5860 16:29:56.007119 # ok 1 SVE default vector length 64
5861 16:29:56.007205 # ok 2 SVE minimum vector length 16
5862 16:29:56.007289 # ok 3 SVE maximum vector length 256
5863 16:29:56.007370 # ok 4 SVE current VL is 64
5864 16:29:56.007465 # ok 5 SVE set VL 64 and have VL 64
5865 16:29:56.007546 # ok 6 SVE prctl() set min/max
5866 16:29:56.007627 # ok 7 SVE vector length used default
5867 16:29:56.007719 # ok 8 SVE vector length was inherited
5868 16:29:56.007799 # ok 9 SVE vector length set on exec
5869 16:29:56.008080 # ok 10 SVE prctl() set all VLs, 0 errors
5870 16:29:56.008190 # ok 11 SME default vector length 32
5871 16:29:56.008275 # ok 12 SME minimum vector length 16
5872 16:29:56.008352 # ok 13 SME maximum vector length 256
5873 16:29:56.008442 # ok 14 SME current VL is 32
5874 16:29:56.008520 # ok 15 SME set VL 32 and have VL 32
5875 16:29:56.019549 # ok 16 SME prctl() set min/max
5876 16:29:56.019972 # ok 17 SME vector length used default
5877 16:29:56.020094 # ok 18 SME vector length was inherited
5878 16:29:56.020214 # ok 19 SME vector length set on exec
5879 16:29:56.020306 # ok 20 SME prctl() set all VLs, 0 errors
5880 16:29:56.030870 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5881 16:29:56.079976 ok 32 selftests: arm64: vec-syscfg
5882 16:29:56.542932 # selftests: arm64: za-fork
5883 16:29:57.095305 # TAP version 13
5884 16:29:57.095734 # 1..1
5885 16:29:57.095819 # # PID: 1014
5886 16:29:57.095887 # ok 1 fork_test
5887 16:29:57.095950 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5888 16:29:57.167578 ok 33 selftests: arm64: za-fork
5889 16:29:57.683900 # selftests: arm64: za-ptrace
5890 16:29:58.135542 # TAP version 13
5891 16:29:58.135788 # 1..1536
5892 16:29:58.135894 # # Parent is 1032, child is 1033
5893 16:29:58.136218 # ok 1 Set VL 16
5894 16:29:58.136339 # ok 2 Disabled ZA for VL 16
5895 16:29:58.136478 # ok 3 Data match for VL 16
5896 16:29:58.136590 # ok 4 Set VL 32
5897 16:29:58.136729 # ok 5 Disabled ZA for VL 32
5898 16:29:58.136842 # ok 6 Data match for VL 32
5899 16:29:58.138601 # ok 7 Set VL 48
5900 16:29:58.138728 # ok 8 # SKIP Disabled ZA for VL 48
5901 16:29:58.139057 # ok 9 # SKIP Get and set data for VL 48
5902 16:29:58.139162 # ok 10 Set VL 64
5903 16:29:58.139290 # ok 11 Disabled ZA for VL 64
5904 16:29:58.139382 # ok 12 Data match for VL 64
5905 16:29:58.139486 # ok 13 Set VL 80
5906 16:29:58.139608 # ok 14 # SKIP Disabled ZA for VL 80
5907 16:29:58.139720 # ok 15 # SKIP Get and set data for VL 80
5908 16:29:58.139829 # ok 16 Set VL 96
5909 16:29:58.140295 # ok 17 # SKIP Disabled ZA for VL 96
5910 16:29:58.140417 # ok 18 # SKIP Get and set data for VL 96
5911 16:29:58.140520 # ok 19 Set VL 112
5912 16:29:58.141411 # ok 20 # SKIP Disabled ZA for VL 112
5913 16:29:58.141705 # ok 21 # SKIP Get and set data for VL 112
5914 16:29:58.141849 # ok 22 Set VL 128
5915 16:29:58.141991 # ok 23 Disabled ZA for VL 128
5916 16:29:58.142094 # ok 24 Data match for VL 128
5917 16:29:58.142226 # ok 25 Set VL 144
5918 16:29:58.142325 # ok 26 # SKIP Disabled ZA for VL 144
5919 16:29:58.142448 # ok 27 # SKIP Get and set data for VL 144
5920 16:29:58.142558 # ok 28 Set VL 160
5921 16:29:58.142661 # ok 29 # SKIP Disabled ZA for VL 160
5922 16:29:58.142769 # ok 30 # SKIP Get and set data for VL 160
5923 16:29:58.142864 # ok 31 Set VL 176
5924 16:29:58.142993 # ok 32 # SKIP Disabled ZA for VL 176
5925 16:29:58.143093 # ok 33 # SKIP Get and set data for VL 176
5926 16:29:58.143208 # ok 34 Set VL 192
5927 16:29:58.143321 # ok 35 # SKIP Disabled ZA for VL 192
5928 16:29:58.143427 # ok 36 # SKIP Get and set data for VL 192
5929 16:29:58.143511 # ok 37 Set VL 208
5930 16:29:58.143612 # ok 38 # SKIP Disabled ZA for VL 208
5931 16:29:58.143702 # ok 39 # SKIP Get and set data for VL 208
5932 16:29:58.143821 # ok 40 Set VL 224
5933 16:29:58.143923 # ok 41 # SKIP Disabled ZA for VL 224
5934 16:29:58.144031 # ok 42 # SKIP Get and set data for VL 224
5935 16:29:58.144148 # ok 43 Set VL 240
5936 16:29:58.144262 # ok 44 # SKIP Disabled ZA for VL 240
5937 16:29:58.144387 # ok 45 # SKIP Get and set data for VL 240
5938 16:29:58.144521 # ok 46 Set VL 256
5939 16:29:58.144601 # ok 47 Disabled ZA for VL 256
5940 16:29:58.157542 # ok 48 Data match for VL 256
5941 16:29:58.157859 # ok 49 Set VL 272
5942 16:29:58.157977 # ok 50 # SKIP Disabled ZA for VL 272
5943 16:29:58.158099 # ok 51 # SKIP Get and set data for VL 272
5944 16:29:58.158222 # ok 52 Set VL 288
5945 16:29:58.158538 # ok 53 # SKIP Disabled ZA for VL 288
5946 16:29:58.158858 # ok 54 # SKIP Get and set data for VL 288
5947 16:29:58.158962 # ok 55 Set VL 304
5948 16:29:58.159285 # ok 56 # SKIP Disabled ZA for VL 304
5949 16:29:58.159388 # ok 57 # SKIP Get and set data for VL 304
5950 16:29:58.159498 # ok 58 Set VL 320
5951 16:29:58.159603 # ok 59 # SKIP Disabled ZA for VL 320
5952 16:29:58.159731 # ok 60 # SKIP Get and set data for VL 320
5953 16:29:58.159835 # ok 61 Set VL 336
5954 16:29:58.159943 # ok 62 # SKIP Disabled ZA for VL 336
5955 16:29:58.160033 # ok 63 # SKIP Get and set data for VL 336
5956 16:29:58.160132 # ok 64 Set VL 352
5957 16:29:58.160230 # ok 65 # SKIP Disabled ZA for VL 352
5958 16:29:58.160328 # ok 66 # SKIP Get and set data for VL 352
5959 16:29:58.160438 # ok 67 Set VL 368
5960 16:29:58.165545 # ok 68 # SKIP Disabled ZA for VL 368
5961 16:29:58.165870 # ok 69 # SKIP Get and set data for VL 368
5962 16:29:58.165980 # ok 70 Set VL 384
5963 16:29:58.166091 # ok 71 # SKIP Disabled ZA for VL 384
5964 16:29:58.166406 # ok 72 # SKIP Get and set data for VL 384
5965 16:29:58.166523 # ok 73 Set VL 400
5966 16:29:58.166664 # ok 74 # SKIP Disabled ZA for VL 400
5967 16:29:58.167186 # ok 75 # SKIP Get and set data for VL 400
5968 16:29:58.167294 # ok 76 Set VL 416
5969 16:29:58.167634 # ok 77 # SKIP Disabled ZA for VL 416
5970 16:29:58.167936 # ok 78 # SKIP Get and set data for VL 416
5971 16:29:58.168061 # ok 79 Set VL 432
5972 16:29:58.168410 # ok 80 # SKIP Disabled ZA for VL 432
5973 16:29:58.168539 # ok 81 # SKIP Get and set data for VL 432
5974 16:29:58.168656 # ok 82 Set VL 448
5975 16:29:58.178128 # ok 83 # SKIP Disabled ZA for VL 448
5976 16:29:58.178448 # ok 84 # SKIP Get and set data for VL 448
5977 16:29:58.178598 # ok 85 Set VL 464
5978 16:29:58.178724 # ok 86 # SKIP Disabled ZA for VL 464
5979 16:29:58.178858 # ok 87 # SKIP Get and set data for VL 464
5980 16:29:58.178992 # ok 88 Set VL 480
5981 16:29:58.179089 # ok 89 # SKIP Disabled ZA for VL 480
5982 16:29:58.179390 # ok 90 # SKIP Get and set data for VL 480
5983 16:29:58.179719 # ok 91 Set VL 496
5984 16:29:58.179844 # ok 92 # SKIP Disabled ZA for VL 496
5985 16:29:58.180194 # ok 93 # SKIP Get and set data for VL 496
5986 16:29:58.180287 # ok 94 Set VL 512
5987 16:29:58.180593 # ok 95 # SKIP Disabled ZA for VL 512
5988 16:29:58.180686 # ok 96 # SKIP Get and set data for VL 512
5989 16:29:58.180754 # ok 97 Set VL 528
5990 16:29:58.181464 # ok 98 # SKIP Disabled ZA for VL 528
5991 16:29:58.181788 # ok 99 # SKIP Get and set data for VL 528
5992 16:29:58.181915 # ok 100 Set VL 544
5993 16:29:58.182298 # ok 101 # SKIP Disabled ZA for VL 544
5994 16:29:58.182645 # ok 102 # SKIP Get and set data for VL 544
5995 16:29:58.182951 # ok 103 Set VL 560
5996 16:29:58.183265 # ok 104 # SKIP Disabled ZA for VL 560
5997 16:29:58.183390 # ok 105 # SKIP Get and set data for VL 560
5998 16:29:58.183498 # ok 106 Set VL 576
5999 16:29:58.183597 # ok 107 # SKIP Disabled ZA for VL 576
6000 16:29:58.183705 # ok 108 # SKIP Get and set data for VL 576
6001 16:29:58.183802 # ok 109 Set VL 592
6002 16:29:58.183898 # ok 110 # SKIP Disabled ZA for VL 592
6003 16:29:58.184202 # ok 111 # SKIP Get and set data for VL 592
6004 16:29:58.184303 # ok 112 Set VL 608
6005 16:29:58.184588 # ok 113 # SKIP Disabled ZA for VL 608
6006 16:29:58.184688 # ok 114 # SKIP Get and set data for VL 608
6007 16:29:58.189665 # ok 115 Set VL 624
6008 16:29:58.189988 # ok 116 # SKIP Disabled ZA for VL 624
6009 16:29:58.190089 # ok 117 # SKIP Get and set data for VL 624
6010 16:29:58.190196 # ok 118 Set VL 640
6011 16:29:58.190295 # ok 119 # SKIP Disabled ZA for VL 640
6012 16:29:58.190418 # ok 120 # SKIP Get and set data for VL 640
6013 16:29:58.190528 # ok 121 Set VL 656
6014 16:29:58.190637 # ok 122 # SKIP Disabled ZA for VL 656
6015 16:29:58.191124 # ok 123 # SKIP Get and set data for VL 656
6016 16:29:58.191419 # ok 124 Set VL 672
6017 16:29:58.212076 # ok 125 # SKIP Disabled ZA for VL 672
6018 16:29:58.212200 # ok 126 # SKIP Get and set data for VL 672
6019 16:29:58.212311 # ok 127 Set VL 688
6020 16:29:58.212440 # ok 128 # SKIP Disabled ZA for VL 688
6021 16:29:58.212540 # ok 129 # SKIP Get and set data for VL 688
6022 16:29:58.220993 # ok 130 Set VL 704
6023 16:29:58.221324 # ok 131 # SKIP Disabled ZA for VL 704
6024 16:29:58.221468 # ok 132 # SKIP Get and set data for VL 704
6025 16:29:58.221596 # ok 133 Set VL 720
6026 16:29:58.221705 # ok 134 # SKIP Disabled ZA for VL 720
6027 16:29:58.221817 # ok 135 # SKIP Get and set data for VL 720
6028 16:29:58.221908 # ok 136 Set VL 736
6029 16:29:58.222221 # ok 137 # SKIP Disabled ZA for VL 736
6030 16:29:58.222544 # ok 138 # SKIP Get and set data for VL 736
6031 16:29:58.222660 # ok 139 Set VL 752
6032 16:29:58.222969 # ok 140 # SKIP Disabled ZA for VL 752
6033 16:29:58.223084 # ok 141 # SKIP Get and set data for VL 752
6034 16:29:58.223170 # ok 142 Set VL 768
6035 16:29:58.223263 # ok 143 # SKIP Disabled ZA for VL 768
6036 16:29:58.223364 # ok 144 # SKIP Get and set data for VL 768
6037 16:29:58.223654 # ok 145 Set VL 784
6038 16:29:58.223758 # ok 146 # SKIP Disabled ZA for VL 784
6039 16:29:58.223885 # ok 147 # SKIP Get and set data for VL 784
6040 16:29:58.223982 # ok 148 Set VL 800
6041 16:29:58.224112 # ok 149 # SKIP Disabled ZA for VL 800
6042 16:29:58.224216 # ok 150 # SKIP Get and set data for VL 800
6043 16:29:58.224336 # ok 151 Set VL 816
6044 16:29:58.224431 # ok 152 # SKIP Disabled ZA for VL 816
6045 16:29:58.224537 # ok 153 # SKIP Get and set data for VL 816
6046 16:29:58.224627 # ok 154 Set VL 832
6047 16:29:58.224725 # ok 155 # SKIP Disabled ZA for VL 832
6048 16:29:58.224826 # ok 156 # SKIP Get and set data for VL 832
6049 16:29:58.224937 # ok 157 Set VL 848
6050 16:29:58.225064 # ok 158 # SKIP Disabled ZA for VL 848
6051 16:29:58.225184 # ok 159 # SKIP Get and set data for VL 848
6052 16:29:58.225299 # ok 160 Set VL 864
6053 16:29:58.225424 # ok 161 # SKIP Disabled ZA for VL 864
6054 16:29:58.225573 # ok 162 # SKIP Get and set data for VL 864
6055 16:29:58.233454 # ok 163 Set VL 880
6056 16:29:58.233968 # ok 164 # SKIP Disabled ZA for VL 880
6057 16:29:58.234479 # ok 165 # SKIP Get and set data for VL 880
6058 16:29:58.234804 # ok 166 Set VL 896
6059 16:29:58.234960 # ok 167 # SKIP Disabled ZA for VL 896
6060 16:29:58.235107 # ok 168 # SKIP Get and set data for VL 896
6061 16:29:58.235242 # ok 169 Set VL 912
6062 16:29:58.235373 # ok 170 # SKIP Disabled ZA for VL 912
6063 16:29:58.235502 # ok 171 # SKIP Get and set data for VL 912
6064 16:29:58.235756 # ok 172 Set VL 928
6065 16:29:58.235865 # ok 173 # SKIP Disabled ZA for VL 928
6066 16:29:58.235952 # ok 174 # SKIP Get and set data for VL 928
6067 16:29:58.236052 # ok 175 Set VL 944
6068 16:29:58.236157 # ok 176 # SKIP Disabled ZA for VL 944
6069 16:29:58.236264 # ok 177 # SKIP Get and set data for VL 944
6070 16:29:58.236350 # ok 178 Set VL 960
6071 16:29:58.236433 # ok 179 # SKIP Disabled ZA for VL 960
6072 16:29:58.236534 # ok 180 # SKIP Get and set data for VL 960
6073 16:29:58.236622 # ok 181 Set VL 976
6074 16:29:58.236718 # ok 182 # SKIP Disabled ZA for VL 976
6075 16:29:58.236837 # ok 183 # SKIP Get and set data for VL 976
6076 16:29:58.236922 # ok 184 Set VL 992
6077 16:29:58.237004 # ok 185 # SKIP Disabled ZA for VL 992
6078 16:29:58.237104 # ok 186 # SKIP Get and set data for VL 992
6079 16:29:58.237190 # ok 187 Set VL 1008
6080 16:29:58.237273 # ok 188 # SKIP Disabled ZA for VL 1008
6081 16:29:58.237372 # ok 189 # SKIP Get and set data for VL 1008
6082 16:29:58.237470 # ok 190 Set VL 1024
6083 16:29:58.237555 # ok 191 # SKIP Disabled ZA for VL 1024
6084 16:29:58.237656 # ok 192 # SKIP Get and set data for VL 1024
6085 16:29:58.237740 # ok 193 Set VL 1040
6086 16:29:58.237866 # ok 194 # SKIP Disabled ZA for VL 1040
6087 16:29:58.237973 # ok 195 # SKIP Get and set data for VL 1040
6088 16:29:58.238088 # ok 196 Set VL 1056
6089 16:29:58.238193 # ok 197 # SKIP Disabled ZA for VL 1056
6090 16:29:58.238314 # ok 198 # SKIP Get and set data for VL 1056
6091 16:29:58.238433 # ok 199 Set VL 1072
6092 16:29:58.238558 # ok 200 # SKIP Disabled ZA for VL 1072
6093 16:29:58.238668 # ok 201 # SKIP Get and set data for VL 1072
6094 16:29:58.238769 # ok 202 Set VL 1088
6095 16:29:58.238874 # ok 203 # SKIP Disabled ZA for VL 1088
6096 16:29:58.238961 # ok 204 # SKIP Get and set data for VL 1088
6097 16:29:58.239042 # ok 205 Set VL 1104
6098 16:29:58.239126 # ok 206 # SKIP Disabled ZA for VL 1104
6099 16:29:58.239210 # ok 207 # SKIP Get and set data for VL 1104
6100 16:29:58.239309 # ok 208 Set VL 1120
6101 16:29:58.239409 # ok 209 # SKIP Disabled ZA for VL 1120
6102 16:29:58.239521 # ok 210 # SKIP Get and set data for VL 1120
6103 16:29:58.239623 # ok 211 Set VL 1136
6104 16:29:58.239723 # ok 212 # SKIP Disabled ZA for VL 1136
6105 16:29:58.239806 # ok 213 # SKIP Get and set data for VL 1136
6106 16:29:58.239899 # ok 214 Set VL 1152
6107 16:29:58.239996 # ok 215 # SKIP Disabled ZA for VL 1152
6108 16:29:58.240114 # ok 216 # SKIP Get and set data for VL 1152
6109 16:29:58.240224 # ok 217 Set VL 1168
6110 16:29:58.240345 # ok 218 # SKIP Disabled ZA for VL 1168
6111 16:29:58.240441 # ok 219 # SKIP Get and set data for VL 1168
6112 16:29:58.240543 # ok 220 Set VL 1184
6113 16:29:58.241392 # ok 221 # SKIP Disabled ZA for VL 1184
6114 16:29:58.241495 # ok 222 # SKIP Get and set data for VL 1184
6115 16:29:58.241593 # ok 223 Set VL 1200
6116 16:29:58.241697 # ok 224 # SKIP Disabled ZA for VL 1200
6117 16:29:58.241797 # ok 225 # SKIP Get and set data for VL 1200
6118 16:29:58.241908 # ok 226 Set VL 1216
6119 16:29:58.241999 # ok 227 # SKIP Disabled ZA for VL 1216
6120 16:29:58.242078 # ok 228 # SKIP Get and set data for VL 1216
6121 16:29:58.242155 # ok 229 Set VL 1232
6122 16:29:58.242248 # ok 230 # SKIP Disabled ZA for VL 1232
6123 16:29:58.242328 # ok 231 # SKIP Get and set data for VL 1232
6124 16:29:58.242405 # ok 232 Set VL 1248
6125 16:29:58.242481 # ok 233 # SKIP Disabled ZA for VL 1248
6126 16:29:58.242558 # ok 234 # SKIP Get and set data for VL 1248
6127 16:29:58.242634 # ok 235 Set VL 1264
6128 16:29:58.242710 # ok 236 # SKIP Disabled ZA for VL 1264
6129 16:29:58.242801 # ok 237 # SKIP Get and set data for VL 1264
6130 16:29:58.242879 # ok 238 Set VL 1280
6131 16:29:58.242955 # ok 239 # SKIP Disabled ZA for VL 1280
6132 16:29:58.243031 # ok 240 # SKIP Get and set data for VL 1280
6133 16:29:58.243106 # ok 241 Set VL 1296
6134 16:29:58.243196 # ok 242 # SKIP Disabled ZA for VL 1296
6135 16:29:58.243275 # ok 243 # SKIP Get and set data for VL 1296
6136 16:29:58.243352 # ok 244 Set VL 1312
6137 16:29:58.243427 # ok 245 # SKIP Disabled ZA for VL 1312
6138 16:29:58.243517 # ok 246 # SKIP Get and set data for VL 1312
6139 16:29:58.243595 # ok 247 Set VL 1328
6140 16:29:58.243672 # ok 248 # SKIP Disabled ZA for VL 1328
6141 16:29:58.243762 # ok 249 # SKIP Get and set data for VL 1328
6142 16:29:58.243840 # ok 250 Set VL 1344
6143 16:29:58.243916 # ok 251 # SKIP Disabled ZA for VL 1344
6144 16:29:58.244005 # ok 252 # SKIP Get and set data for VL 1344
6145 16:29:58.244083 # ok 253 Set VL 1360
6146 16:29:58.244172 # ok 254 # SKIP Disabled ZA for VL 1360
6147 16:29:58.244261 # ok 255 # SKIP Get and set data for VL 1360
6148 16:29:58.244340 # ok 256 Set VL 1376
6149 16:29:58.244428 # ok 257 # SKIP Disabled ZA for VL 1376
6150 16:29:58.244518 # ok 258 # SKIP Get and set data for VL 1376
6151 16:29:58.244608 # ok 259 Set VL 1392
6152 16:29:58.244697 # ok 260 # SKIP Disabled ZA for VL 1392
6153 16:29:58.244787 # ok 261 # SKIP Get and set data for VL 1392
6154 16:29:58.245071 # ok 262 Set VL 1408
6155 16:29:58.271904 # ok 263 # SKIP Disabled ZA for VL 1408
6156 16:29:58.272441 # ok 264 # SKIP Get and set data for VL 1408
6157 16:29:58.274661 # ok 265 Set VL 1424
6158 16:29:58.275014 # ok 266 # SKIP Disabled ZA for VL 1424
6159 16:29:58.277424 # ok 267 # SKIP Get and set data for VL 1424
6160 16:29:58.277545 # ok 268 Set VL 1440
6161 16:29:58.277656 # ok 269 # SKIP Disabled ZA for VL 1440
6162 16:29:58.277753 # ok 270 # SKIP Get and set data for VL 1440
6163 16:29:58.277875 # ok 271 Set VL 1456
6164 16:29:58.277979 # ok 272 # SKIP Disabled ZA for VL 1456
6165 16:29:58.278071 # ok 273 # SKIP Get and set data for VL 1456
6166 16:29:58.278160 # ok 274 Set VL 1472
6167 16:29:58.278240 # ok 275 # SKIP Disabled ZA for VL 1472
6168 16:29:58.278348 # ok 276 # SKIP Get and set data for VL 1472
6169 16:29:58.278460 # ok 277 Set VL 1488
6170 16:29:58.278589 # ok 278 # SKIP Disabled ZA for VL 1488
6171 16:29:58.278684 # ok 279 # SKIP Get and set data for VL 1488
6172 16:29:58.278801 # ok 280 Set VL 1504
6173 16:29:58.278893 # ok 281 # SKIP Disabled ZA for VL 1504
6174 16:29:58.278966 # ok 282 # SKIP Get and set data for VL 1504
6175 16:29:58.279039 # ok 283 Set VL 1520
6176 16:29:58.279149 # ok 284 # SKIP Disabled ZA for VL 1520
6177 16:29:58.279231 # ok 285 # SKIP Get and set data for VL 1520
6178 16:29:58.279294 # ok 286 Set VL 1536
6179 16:29:58.279764 # ok 287 # SKIP Disabled ZA for VL 1536
6180 16:29:58.279893 # ok 288 # SKIP Get and set data for VL 1536
6181 16:29:58.280008 # ok 289 Set VL 1552
6182 16:29:58.280528 # ok 290 # SKIP Disabled ZA for VL 1552
6183 16:29:58.280858 # ok 291 # SKIP Get and set data for VL 1552
6184 16:29:58.291706 # ok 292 Set VL 1568
6185 16:29:58.292033 # ok 293 # SKIP Disabled ZA for VL 1568
6186 16:29:58.292574 # ok 294 # SKIP Get and set data for VL 1568
6187 16:29:58.292681 # ok 295 Set VL 1584
6188 16:29:58.292772 # ok 296 # SKIP Disabled ZA for VL 1584
6189 16:29:58.292857 # ok 297 # SKIP Get and set data for VL 1584
6190 16:29:58.292941 # ok 298 Set VL 1600
6191 16:29:58.293023 # ok 299 # SKIP Disabled ZA for VL 1600
6192 16:29:58.319398 # ok 300 # SKIP Get and set data for VL 1600
6193 16:29:58.319722 # ok 301 Set VL 1616
6194 16:29:58.320096 # ok 302 # SKIP Disabled ZA for VL 1616
6195 16:29:58.338742 # ok 303 # SKIP Get and set data for VL 1616
6196 16:29:58.339063 # ok 304 Set VL 1632
6197 16:29:58.339476 # ok 305 # SKIP Disabled ZA for VL 1632
6198 16:29:58.339774 # ok 306 # SKIP Get and set data for VL 1632
6199 16:29:58.340247 # ok 307 Set VL 1648
6200 16:29:58.340589 # ok 308 # SKIP Disabled ZA for VL 1648
6201 16:29:58.399149 # ok 309 # SKIP Get and set data for VL 1648
6202 16:29:58.399701 # ok 310 Set VL 1664
6203 16:29:58.400589 # ok 311 # SKIP Disabled ZA for VL 1664
6204 16:29:58.419529 # ok 312 # SKIP Get and set data for VL 1664
6205 16:29:58.420040 # ok 313 Set VL 1680
6206 16:29:58.420701 # ok 314 # SKIP Disabled ZA for VL 1680
6207 16:29:58.435827 # ok 315 # SKIP Get and set data for VL 1680
6208 16:29:58.435956 # ok 316 Set VL 1696
6209 16:29:58.436268 # ok 317 # SKIP Disabled ZA for VL 1696
6210 16:29:58.451363 # ok 318 # SKIP Get and set data for VL 1696
6211 16:29:58.451665 # ok 319 Set VL 1712
6212 16:29:58.451986 # ok 320 # SKIP Disabled ZA for VL 1712
6213 16:29:58.478808 # ok 321 # SKIP Get and set data for VL 1712
6214 16:29:58.479502 # ok 322 Set VL 1728
6215 16:29:58.486478 # ok 323 # SKIP Disabled ZA for VL 1728
6216 16:29:58.487565 # ok 324 # SKIP Get and set data for VL 1728
6217 16:29:58.487702 # ok 325 Set VL 1744
6218 16:29:58.488422 # ok 326 # SKIP Disabled ZA for VL 1744
6219 16:29:58.491672 # ok 327 # SKIP Get and set data for VL 1744
6220 16:29:58.491999 # ok 328 Set VL 1760
6221 16:29:58.492321 # ok 329 # SKIP Disabled ZA for VL 1760
6222 16:29:58.492624 # ok 330 # SKIP Get and set data for VL 1760
6223 16:29:58.492725 # ok 331 Set VL 1776
6224 16:29:58.503347 # ok 332 # SKIP Disabled ZA for VL 1776
6225 16:29:58.503682 # ok 333 # SKIP Get and set data for VL 1776
6226 16:29:58.504026 # ok 334 Set VL 1792
6227 16:29:58.504378 # ok 335 # SKIP Disabled ZA for VL 1792
6228 16:29:58.510569 # ok 336 # SKIP Get and set data for VL 1792
6229 16:29:58.511081 # ok 337 Set VL 1808
6230 16:29:58.512189 # ok 338 # SKIP Disabled ZA for VL 1808
6231 16:29:58.518600 # ok 339 # SKIP Get and set data for VL 1808
6232 16:29:58.519106 # ok 340 Set VL 1824
6233 16:29:58.519625 # ok 341 # SKIP Disabled ZA for VL 1824
6234 16:29:58.520137 # ok 342 # SKIP Get and set data for VL 1824
6235 16:29:58.527334 # ok 343 Set VL 1840
6236 16:29:58.528424 # ok 344 # SKIP Disabled ZA for VL 1840
6237 16:29:58.534989 # ok 345 # SKIP Get and set data for VL 1840
6238 16:29:58.535298 # ok 346 Set VL 1856
6239 16:29:58.535619 # ok 347 # SKIP Disabled ZA for VL 1856
6240 16:29:58.535724 # ok 348 # SKIP Get and set data for VL 1856
6241 16:29:58.535854 # ok 349 Set VL 1872
6242 16:29:58.536175 # ok 350 # SKIP Disabled ZA for VL 1872
6243 16:29:58.536300 # ok 351 # SKIP Get and set data for VL 1872
6244 16:29:58.536692 # ok 352 Set VL 1888
6245 16:29:58.536985 # ok 353 # SKIP Disabled ZA for VL 1888
6246 16:29:58.539450 # ok 354 # SKIP Get and set data for VL 1888
6247 16:29:58.539752 # ok 355 Set VL 1904
6248 16:29:58.539873 # ok 356 # SKIP Disabled ZA for VL 1904
6249 16:29:58.540163 # ok 357 # SKIP Get and set data for VL 1904
6250 16:29:58.540300 # ok 358 Set VL 1920
6251 16:29:58.559601 # ok 359 # SKIP Disabled ZA for VL 1920
6252 16:29:58.559767 # ok 360 # SKIP Get and set data for VL 1920
6253 16:29:58.559864 # ok 361 Set VL 1936
6254 16:29:58.560161 # ok 362 # SKIP Disabled ZA for VL 1936
6255 16:29:58.571546 # ok 363 # SKIP Get and set data for VL 1936
6256 16:29:58.571912 # ok 364 Set VL 1952
6257 16:29:58.572229 # ok 365 # SKIP Disabled ZA for VL 1952
6258 16:29:58.578727 # ok 366 # SKIP Get and set data for VL 1952
6259 16:29:58.579234 # ok 367 Set VL 1968
6260 16:29:58.580329 # ok 368 # SKIP Disabled ZA for VL 1968
6261 16:29:58.595399 # ok 369 # SKIP Get and set data for VL 1968
6262 16:29:58.595906 # ok 370 Set VL 1984
6263 16:29:58.602730 # ok 371 # SKIP Disabled ZA for VL 1984
6264 16:29:58.603998 # ok 372 # SKIP Get and set data for VL 1984
6265 16:29:58.604699 # ok 373 Set VL 2000
6266 16:29:58.606642 # ok 374 # SKIP Disabled ZA for VL 2000
6267 16:29:58.607546 # ok 375 # SKIP Get and set data for VL 2000
6268 16:29:58.607664 # ok 376 Set VL 2016
6269 16:29:58.608347 # ok 377 # SKIP Disabled ZA for VL 2016
6270 16:29:58.618773 # ok 378 # SKIP Get and set data for VL 2016
6271 16:29:58.619091 # ok 379 Set VL 2032
6272 16:29:58.619445 # ok 380 # SKIP Disabled ZA for VL 2032
6273 16:29:58.619953 # ok 381 # SKIP Get and set data for VL 2032
6274 16:29:58.620265 # ok 382 Set VL 2048
6275 16:29:58.627127 # ok 383 # SKIP Disabled ZA for VL 2048
6276 16:29:58.628259 # ok 384 # SKIP Get and set data for VL 2048
6277 16:29:58.635356 # ok 385 Set VL 2064
6278 16:29:58.636250 # ok 386 # SKIP Disabled ZA for VL 2064
6279 16:29:58.643063 # ok 387 # SKIP Get and set data for VL 2064
6280 16:29:58.643366 # ok 388 Set VL 2080
6281 16:29:58.643883 # ok 389 # SKIP Disabled ZA for VL 2080
6282 16:29:58.651278 # ok 390 # SKIP Get and set data for VL 2080
6283 16:29:58.651763 # ok 391 Set VL 2096
6284 16:29:58.662684 # ok 392 # SKIP Disabled ZA for VL 2096
6285 16:29:58.663760 # ok 393 # SKIP Get and set data for VL 2096
6286 16:29:58.664467 # ok 394 Set VL 2112
6287 16:29:58.667375 # ok 395 # SKIP Disabled ZA for VL 2112
6288 16:29:58.668063 # ok 396 # SKIP Get and set data for VL 2112
6289 16:29:58.668577 # ok 397 Set VL 2128
6290 16:29:58.670395 # ok 398 # SKIP Disabled ZA for VL 2128
6291 16:29:58.671666 # ok 399 # SKIP Get and set data for VL 2128
6292 16:29:58.672184 # ok 400 Set VL 2144
6293 16:29:58.684750 # ok 401 # SKIP Disabled ZA for VL 2144
6294 16:29:58.686981 # ok 402 # SKIP Get and set data for VL 2144
6295 16:29:58.687267 # ok 403 Set VL 2160
6296 16:29:58.687780 # ok 404 # SKIP Disabled ZA for VL 2160
6297 16:29:58.688498 # ok 405 # SKIP Get and set data for VL 2160
6298 16:29:58.694829 # ok 406 Set VL 2176
6299 16:29:58.695914 # ok 407 # SKIP Disabled ZA for VL 2176
6300 16:29:58.696661 # ok 408 # SKIP Get and set data for VL 2176
6301 16:29:58.706992 # ok 409 Set VL 2192
6302 16:29:58.707878 # ok 410 # SKIP Disabled ZA for VL 2192
6303 16:29:58.707981 # ok 411 # SKIP Get and set data for VL 2192
6304 16:29:58.708089 # ok 412 Set VL 2208
6305 16:29:58.711715 # ok 413 # SKIP Disabled ZA for VL 2208
6306 16:29:58.712016 # ok 414 # SKIP Get and set data for VL 2208
6307 16:29:58.712134 # ok 415 Set VL 2224
6308 16:29:58.712455 # ok 416 # SKIP Disabled ZA for VL 2224
6309 16:29:58.712768 # ok 417 # SKIP Get and set data for VL 2224
6310 16:29:58.723154 # ok 418 Set VL 2240
6311 16:29:58.723647 # ok 419 # SKIP Disabled ZA for VL 2240
6312 16:29:58.723765 # ok 420 # SKIP Get and set data for VL 2240
6313 16:29:58.724057 # ok 421 Set VL 2256
6314 16:29:58.724161 # ok 422 # SKIP Disabled ZA for VL 2256
6315 16:29:58.724292 # ok 423 # SKIP Get and set data for VL 2256
6316 16:29:58.724399 # ok 424 Set VL 2272
6317 16:29:58.724527 # ok 425 # SKIP Disabled ZA for VL 2272
6318 16:29:58.724649 # ok 426 # SKIP Get and set data for VL 2272
6319 16:29:58.724755 # ok 427 Set VL 2288
6320 16:29:58.731109 # ok 428 # SKIP Disabled ZA for VL 2288
6321 16:29:58.731411 # ok 429 # SKIP Get and set data for VL 2288
6322 16:29:58.731516 # ok 430 Set VL 2304
6323 16:29:58.731815 # ok 431 # SKIP Disabled ZA for VL 2304
6324 16:29:58.731935 # ok 432 # SKIP Get and set data for VL 2304
6325 16:29:58.732226 # ok 433 Set VL 2320
6326 16:29:58.732346 # ok 434 # SKIP Disabled ZA for VL 2320
6327 16:29:58.732437 # ok 435 # SKIP Get and set data for VL 2320
6328 16:29:58.732737 # ok 436 Set VL 2336
6329 16:29:58.743311 # ok 437 # SKIP Disabled ZA for VL 2336
6330 16:29:58.744580 # ok 438 # SKIP Get and set data for VL 2336
6331 16:29:58.746511 # ok 439 Set VL 2352
6332 16:29:58.747201 # ok 440 # SKIP Disabled ZA for VL 2352
6333 16:29:58.747709 # ok 441 # SKIP Get and set data for VL 2352
6334 16:29:58.747827 # ok 442 Set VL 2368
6335 16:29:58.748126 # ok 443 # SKIP Disabled ZA for VL 2368
6336 16:29:58.748446 # ok 444 # SKIP Get and set data for VL 2368
6337 16:29:58.748784 # ok 445 Set VL 2384
6338 16:29:58.749922 # ok 446 # SKIP Disabled ZA for VL 2384
6339 16:29:58.750423 # ok 447 # SKIP Get and set data for VL 2384
6340 16:29:58.750564 # ok 448 Set VL 2400
6341 16:29:58.750891 # ok 449 # SKIP Disabled ZA for VL 2400
6342 16:29:58.751424 # ok 450 # SKIP Get and set data for VL 2400
6343 16:29:58.751544 # ok 451 Set VL 2416
6344 16:29:58.751674 # ok 452 # SKIP Disabled ZA for VL 2416
6345 16:29:58.752219 # ok 453 # SKIP Get and set data for VL 2416
6346 16:29:58.752348 # ok 454 Set VL 2432
6347 16:29:58.752475 # ok 455 # SKIP Disabled ZA for VL 2432
6348 16:29:58.759317 # ok 456 # SKIP Get and set data for VL 2432
6349 16:29:58.759846 # ok 457 Set VL 2448
6350 16:29:58.760178 # ok 458 # SKIP Disabled ZA for VL 2448
6351 16:29:58.760347 # ok 459 # SKIP Get and set data for VL 2448
6352 16:29:58.760478 # ok 460 Set VL 2464
6353 16:29:58.760804 # ok 461 # SKIP Disabled ZA for VL 2464
6354 16:29:58.767916 # ok 462 # SKIP Get and set data for VL 2464
6355 16:29:58.768051 # ok 463 Set VL 2480
6356 16:29:58.768192 # ok 464 # SKIP Disabled ZA for VL 2480
6357 16:29:58.768550 # ok 465 # SKIP Get and set data for VL 2480
6358 16:29:58.768668 # ok 466 Set VL 2496
6359 16:29:58.775163 # ok 467 # SKIP Disabled ZA for VL 2496
6360 16:29:58.775685 # ok 468 # SKIP Get and set data for VL 2496
6361 16:29:58.776205 # ok 469 Set VL 2512
6362 16:29:58.776574 # ok 470 # SKIP Disabled ZA for VL 2512
6363 16:29:58.778319 # ok 471 # SKIP Get and set data for VL 2512
6364 16:29:58.778631 # ok 472 Set VL 2528
6365 16:29:58.778752 # ok 473 # SKIP Disabled ZA for VL 2528
6366 16:29:58.779057 # ok 474 # SKIP Get and set data for VL 2528
6367 16:29:58.779179 # ok 475 Set VL 2544
6368 16:29:58.779320 # ok 476 # SKIP Disabled ZA for VL 2544
6369 16:29:58.779644 # ok 477 # SKIP Get and set data for VL 2544
6370 16:29:58.779756 # ok 478 Set VL 2560
6371 16:29:58.779856 # ok 479 # SKIP Disabled ZA for VL 2560
6372 16:29:58.780177 # ok 480 # SKIP Get and set data for VL 2560
6373 16:29:58.780283 # ok 481 Set VL 2576
6374 16:29:58.780594 # ok 482 # SKIP Disabled ZA for VL 2576
6375 16:29:58.780708 # ok 483 # SKIP Get and set data for VL 2576
6376 16:29:58.780821 # ok 484 Set VL 2592
6377 16:29:58.780920 # ok 485 # SKIP Disabled ZA for VL 2592
6378 16:29:58.781215 # ok 486 # SKIP Get and set data for VL 2592
6379 16:29:58.781331 # ok 487 Set VL 2608
6380 16:29:58.781440 # ok 488 # SKIP Disabled ZA for VL 2608
6381 16:29:58.791656 # ok 489 # SKIP Get and set data for VL 2608
6382 16:29:58.791803 # ok 490 Set VL 2624
6383 16:29:58.791929 # ok 491 # SKIP Disabled ZA for VL 2624
6384 16:29:58.792471 # ok 492 # SKIP Get and set data for VL 2624
6385 16:29:58.792581 # ok 493 Set VL 2640
6386 16:29:58.792717 # ok 494 # SKIP Disabled ZA for VL 2640
6387 16:29:58.802640 # ok 495 # SKIP Get and set data for VL 2640
6388 16:29:58.802943 # ok 496 Set VL 2656
6389 16:29:58.803059 # ok 497 # SKIP Disabled ZA for VL 2656
6390 16:29:58.803344 # ok 498 # SKIP Get and set data for VL 2656
6391 16:29:58.803459 # ok 499 Set VL 2672
6392 16:29:58.803559 # ok 500 # SKIP Disabled ZA for VL 2672
6393 16:29:58.803847 # ok 501 # SKIP Get and set data for VL 2672
6394 16:29:58.803963 # ok 502 Set VL 2688
6395 16:29:58.804473 # ok 503 # SKIP Disabled ZA for VL 2688
6396 16:29:58.804737 # ok 504 # SKIP Get and set data for VL 2688
6397 16:29:58.804839 # ok 505 Set VL 2704
6398 16:29:58.806909 # ok 506 # SKIP Disabled ZA for VL 2704
6399 16:29:58.807225 # ok 507 # SKIP Get and set data for VL 2704
6400 16:29:58.807325 # ok 508 Set VL 2720
6401 16:29:58.807452 # ok 509 # SKIP Disabled ZA for VL 2720
6402 16:29:58.807981 # ok 510 # SKIP Get and set data for VL 2720
6403 16:29:58.808084 # ok 511 Set VL 2736
6404 16:29:58.808368 # ok 512 # SKIP Disabled ZA for VL 2736
6405 16:29:58.808486 # ok 513 # SKIP Get and set data for VL 2736
6406 16:29:58.808624 # ok 514 Set VL 2752
6407 16:29:58.809749 # ok 515 # SKIP Disabled ZA for VL 2752
6408 16:29:58.810059 # ok 516 # SKIP Get and set data for VL 2752
6409 16:29:58.810347 # ok 517 Set VL 2768
6410 16:29:58.810658 # ok 518 # SKIP Disabled ZA for VL 2768
6411 16:29:58.810978 # ok 519 # SKIP Get and set data for VL 2768
6412 16:29:58.811280 # ok 520 Set VL 2784
6413 16:29:58.811396 # ok 521 # SKIP Disabled ZA for VL 2784
6414 16:29:58.811486 # ok 522 # SKIP Get and set data for VL 2784
6415 16:29:58.811587 # ok 523 Set VL 2800
6416 16:29:58.811878 # ok 524 # SKIP Disabled ZA for VL 2800
6417 16:29:58.811982 # ok 525 # SKIP Get and set data for VL 2800
6418 16:29:58.812071 # ok 526 Set VL 2816
6419 16:29:58.812170 # ok 527 # SKIP Disabled ZA for VL 2816
6420 16:29:58.812270 # ok 528 # SKIP Get and set data for VL 2816
6421 16:29:58.812566 # ok 529 Set VL 2832
6422 16:29:58.823002 # ok 530 # SKIP Disabled ZA for VL 2832
6423 16:29:58.823304 # ok 531 # SKIP Get and set data for VL 2832
6424 16:29:58.823422 # ok 532 Set VL 2848
6425 16:29:58.823927 # ok 533 # SKIP Disabled ZA for VL 2848
6426 16:29:58.824251 # ok 534 # SKIP Get and set data for VL 2848
6427 16:29:58.824365 # ok 535 Set VL 2864
6428 16:29:58.824475 # ok 536 # SKIP Disabled ZA for VL 2864
6429 16:29:58.824578 # ok 537 # SKIP Get and set data for VL 2864
6430 16:29:58.824880 # ok 538 Set VL 2880
6431 16:29:58.828515 # ok 539 # SKIP Disabled ZA for VL 2880
6432 16:29:58.842521 # ok 540 # SKIP Get and set data for VL 2880
6433 16:29:58.842826 # ok 541 Set VL 2896
6434 16:29:58.842931 # ok 542 # SKIP Disabled ZA for VL 2896
6435 16:29:58.843653 # ok 543 # SKIP Get and set data for VL 2896
6436 16:29:58.843972 # ok 544 Set VL 2912
6437 16:29:58.850951 # ok 545 # SKIP Disabled ZA for VL 2912
6438 16:29:58.852030 # ok 546 # SKIP Get and set data for VL 2912
6439 16:29:58.852339 # ok 547 Set VL 2928
6440 16:29:58.867086 # ok 548 # SKIP Disabled ZA for VL 2928
6441 16:29:58.867772 # ok 549 # SKIP Get and set data for VL 2928
6442 16:29:58.867874 # ok 550 Set VL 2944
6443 16:29:58.868167 # ok 551 # SKIP Disabled ZA for VL 2944
6444 16:29:58.868281 # ok 552 # SKIP Get and set data for VL 2944
6445 16:29:58.868366 # ok 553 Set VL 2960
6446 16:29:58.868652 # ok 554 # SKIP Disabled ZA for VL 2960
6447 16:29:58.874938 # ok 555 # SKIP Get and set data for VL 2960
6448 16:29:58.875239 # ok 556 Set VL 2976
6449 16:29:58.875552 # ok 557 # SKIP Disabled ZA for VL 2976
6450 16:29:58.876058 # ok 558 # SKIP Get and set data for VL 2976
6451 16:29:58.876164 # ok 559 Set VL 2992
6452 16:29:58.876488 # ok 560 # SKIP Disabled ZA for VL 2992
6453 16:29:58.876616 # ok 561 # SKIP Get and set data for VL 2992
6454 16:29:58.876743 # ok 562 Set VL 3008
6455 16:29:58.876864 # ok 563 # SKIP Disabled ZA for VL 3008
6456 16:29:58.886972 # ok 564 # SKIP Get and set data for VL 3008
6457 16:29:58.887273 # ok 565 Set VL 3024
6458 16:29:58.887789 # ok 566 # SKIP Disabled ZA for VL 3024
6459 16:29:58.888486 # ok 567 # SKIP Get and set data for VL 3024
6460 16:29:58.888587 # ok 568 Set VL 3040
6461 16:29:58.899337 # ok 569 # SKIP Disabled ZA for VL 3040
6462 16:29:58.899675 # ok 570 # SKIP Get and set data for VL 3040
6463 16:29:58.899981 # ok 571 Set VL 3056
6464 16:29:58.910186 # ok 572 # SKIP Disabled ZA for VL 3056
6465 16:29:58.910860 # ok 573 # SKIP Get and set data for VL 3056
6466 16:29:58.910980 # ok 574 Set VL 3072
6467 16:29:58.911280 # ok 575 # SKIP Disabled ZA for VL 3072
6468 16:29:58.911599 # ok 576 # SKIP Get and set data for VL 3072
6469 16:29:58.911702 # ok 577 Set VL 3088
6470 16:29:58.911810 # ok 578 # SKIP Disabled ZA for VL 3088
6471 16:29:58.911913 # ok 579 # SKIP Get and set data for VL 3088
6472 16:29:58.912207 # ok 580 Set VL 3104
6473 16:29:58.931200 # ok 581 # SKIP Disabled ZA for VL 3104
6474 16:29:58.931500 # ok 582 # SKIP Get and set data for VL 3104
6475 16:29:58.931613 # ok 583 Set VL 3120
6476 16:29:58.931905 # ok 584 # SKIP Disabled ZA for VL 3120
6477 16:29:58.932413 # ok 585 # SKIP Get and set data for VL 3120
6478 16:29:58.932727 # ok 586 Set VL 3136
6479 16:29:58.946725 # ok 587 # SKIP Disabled ZA for VL 3136
6480 16:29:58.947140 # ok 588 # SKIP Get and set data for VL 3136
6481 16:29:58.947267 # ok 589 Set VL 3152
6482 16:29:58.963917 # ok 590 # SKIP Disabled ZA for VL 3152
6483 16:29:58.964067 # ok 591 # SKIP Get and set data for VL 3152
6484 16:29:58.964156 # ok 592 Set VL 3168
6485 16:29:58.964234 # ok 593 # SKIP Disabled ZA for VL 3168
6486 16:29:58.964661 # ok 594 # SKIP Get and set data for VL 3168
6487 16:29:58.965045 # ok 595 Set VL 3184
6488 16:29:58.979235 # ok 596 # SKIP Disabled ZA for VL 3184
6489 16:29:58.979668 # ok 597 # SKIP Get and set data for VL 3184
6490 16:29:58.979772 # ok 598 Set VL 3200
6491 16:29:58.979856 # ok 599 # SKIP Disabled ZA for VL 3200
6492 16:29:58.979950 # ok 600 # SKIP Get and set data for VL 3200
6493 16:29:58.980031 # ok 601 Set VL 3216
6494 16:29:58.980109 # ok 602 # SKIP Disabled ZA for VL 3216
6495 16:29:58.980200 # ok 603 # SKIP Get and set data for VL 3216
6496 16:29:58.980280 # ok 604 Set VL 3232
6497 16:29:58.980358 # ok 605 # SKIP Disabled ZA for VL 3232
6498 16:29:58.980449 # ok 606 # SKIP Get and set data for VL 3232
6499 16:29:58.980529 # ok 607 Set VL 3248
6500 16:29:58.980607 # ok 608 # SKIP Disabled ZA for VL 3248
6501 16:29:58.980698 # ok 609 # SKIP Get and set data for VL 3248
6502 16:29:58.995283 # ok 610 Set VL 3264
6503 16:29:58.995735 # ok 611 # SKIP Disabled ZA for VL 3264
6504 16:29:58.995840 # ok 612 # SKIP Get and set data for VL 3264
6505 16:29:58.995936 # ok 613 Set VL 3280
6506 16:29:58.996386 # ok 614 # SKIP Disabled ZA for VL 3280
6507 16:29:58.996895 # ok 615 # SKIP Get and set data for VL 3280
6508 16:29:59.012416 # ok 616 Set VL 3296
6509 16:29:59.012855 # ok 617 # SKIP Disabled ZA for VL 3296
6510 16:29:59.026426 # ok 618 # SKIP Get and set data for VL 3296
6511 16:29:59.026995 # ok 619 Set VL 3312
6512 16:29:59.027097 # ok 620 # SKIP Disabled ZA for VL 3312
6513 16:29:59.027180 # ok 621 # SKIP Get and set data for VL 3312
6514 16:29:59.027258 # ok 622 Set VL 3328
6515 16:29:59.027351 # ok 623 # SKIP Disabled ZA for VL 3328
6516 16:29:59.028332 # ok 624 # SKIP Get and set data for VL 3328
6517 16:29:59.028680 # ok 625 Set VL 3344
6518 16:29:59.046229 # ok 626 # SKIP Disabled ZA for VL 3344
6519 16:29:59.047049 # ok 627 # SKIP Get and set data for VL 3344
6520 16:29:59.047152 # ok 628 Set VL 3360
6521 16:29:59.047438 # ok 629 # SKIP Disabled ZA for VL 3360
6522 16:29:59.047701 # ok 630 # SKIP Get and set data for VL 3360
6523 16:29:59.047802 # ok 631 Set VL 3376
6524 16:29:59.048282 # ok 632 # SKIP Disabled ZA for VL 3376
6525 16:29:59.048877 # ok 633 # SKIP Get and set data for VL 3376
6526 16:29:59.048995 # ok 634 Set VL 3392
6527 16:29:59.049100 # ok 635 # SKIP Disabled ZA for VL 3392
6528 16:29:59.049184 # ok 636 # SKIP Get and set data for VL 3392
6529 16:29:59.049264 # ok 637 Set VL 3408
6530 16:29:59.049343 # ok 638 # SKIP Disabled ZA for VL 3408
6531 16:29:59.049421 # ok 639 # SKIP Get and set data for VL 3408
6532 16:29:59.049499 # ok 640 Set VL 3424
6533 16:29:59.067491 # ok 641 # SKIP Disabled ZA for VL 3424
6534 16:29:59.073804 # ok 642 # SKIP Get and set data for VL 3424
6535 16:29:59.074089 # ok 643 Set VL 3440
6536 16:29:59.074228 # ok 644 # SKIP Disabled ZA for VL 3440
6537 16:29:59.074350 # ok 645 # SKIP Get and set data for VL 3440
6538 16:29:59.074483 # ok 646 Set VL 3456
6539 16:29:59.074618 # ok 647 # SKIP Disabled ZA for VL 3456
6540 16:29:59.074740 # ok 648 # SKIP Get and set data for VL 3456
6541 16:29:59.074874 # ok 649 Set VL 3472
6542 16:29:59.075009 # ok 650 # SKIP Disabled ZA for VL 3472
6543 16:29:59.075130 # ok 651 # SKIP Get and set data for VL 3472
6544 16:29:59.075263 # ok 652 Set VL 3488
6545 16:29:59.075397 # ok 653 # SKIP Disabled ZA for VL 3488
6546 16:29:59.083530 # ok 654 # SKIP Get and set data for VL 3488
6547 16:29:59.084496 # ok 655 Set VL 3504
6548 16:29:59.084917 # ok 656 # SKIP Disabled ZA for VL 3504
6549 16:29:59.085248 # ok 657 # SKIP Get and set data for VL 3504
6550 16:29:59.085465 # ok 658 Set VL 3520
6551 16:29:59.085748 # ok 659 # SKIP Disabled ZA for VL 3520
6552 16:29:59.086009 # ok 660 # SKIP Get and set data for VL 3520
6553 16:29:59.086313 # ok 661 Set VL 3536
6554 16:29:59.086720 # ok 662 # SKIP Disabled ZA for VL 3536
6555 16:29:59.086947 # ok 663 # SKIP Get and set data for VL 3536
6556 16:29:59.087283 # ok 664 Set VL 3552
6557 16:29:59.087596 # ok 665 # SKIP Disabled ZA for VL 3552
6558 16:29:59.088055 # ok 666 # SKIP Get and set data for VL 3552
6559 16:29:59.088595 # ok 667 Set VL 3568
6560 16:29:59.088856 # ok 668 # SKIP Disabled ZA for VL 3568
6561 16:29:59.089178 # ok 669 # SKIP Get and set data for VL 3568
6562 16:29:59.091675 # ok 670 Set VL 3584
6563 16:29:59.091766 # ok 671 # SKIP Disabled ZA for VL 3584
6564 16:29:59.091846 # ok 672 # SKIP Get and set data for VL 3584
6565 16:29:59.091924 # ok 673 Set VL 3600
6566 16:29:59.092002 # ok 674 # SKIP Disabled ZA for VL 3600
6567 16:29:59.092088 # ok 675 # SKIP Get and set data for VL 3600
6568 16:29:59.092165 # ok 676 Set VL 3616
6569 16:29:59.092244 # ok 677 # SKIP Disabled ZA for VL 3616
6570 16:29:59.092321 # ok 678 # SKIP Get and set data for VL 3616
6571 16:29:59.092399 # ok 679 Set VL 3632
6572 16:29:59.092476 # ok 680 # SKIP Disabled ZA for VL 3632
6573 16:29:59.092553 # ok 681 # SKIP Get and set data for VL 3632
6574 16:29:59.092642 # ok 682 Set VL 3648
6575 16:29:59.092719 # ok 683 # SKIP Disabled ZA for VL 3648
6576 16:29:59.092798 # ok 684 # SKIP Get and set data for VL 3648
6577 16:29:59.092876 # ok 685 Set VL 3664
6578 16:29:59.092954 # ok 686 # SKIP Disabled ZA for VL 3664
6579 16:29:59.093032 # ok 687 # SKIP Get and set data for VL 3664
6580 16:29:59.093110 # ok 688 Set VL 3680
6581 16:29:59.093188 # ok 689 # SKIP Disabled ZA for VL 3680
6582 16:29:59.093265 # ok 690 # SKIP Get and set data for VL 3680
6583 16:29:59.093344 # ok 691 Set VL 3696
6584 16:29:59.093421 # ok 692 # SKIP Disabled ZA for VL 3696
6585 16:29:59.093500 # ok 693 # SKIP Get and set data for VL 3696
6586 16:29:59.093577 # ok 694 Set VL 3712
6587 16:29:59.093665 # ok 695 # SKIP Disabled ZA for VL 3712
6588 16:29:59.093765 # ok 696 # SKIP Get and set data for VL 3712
6589 16:29:59.093850 # ok 697 Set VL 3728
6590 16:29:59.093932 # ok 698 # SKIP Disabled ZA for VL 3728
6591 16:29:59.094011 # ok 699 # SKIP Get and set data for VL 3728
6592 16:29:59.094109 # ok 700 Set VL 3744
6593 16:29:59.094191 # ok 701 # SKIP Disabled ZA for VL 3744
6594 16:29:59.094270 # ok 702 # SKIP Get and set data for VL 3744
6595 16:29:59.094349 # ok 703 Set VL 3760
6596 16:29:59.094427 # ok 704 # SKIP Disabled ZA for VL 3760
6597 16:29:59.094506 # ok 705 # SKIP Get and set data for VL 3760
6598 16:29:59.094585 # ok 706 Set VL 3776
6599 16:29:59.094662 # ok 707 # SKIP Disabled ZA for VL 3776
6600 16:29:59.095073 # ok 708 # SKIP Get and set data for VL 3776
6601 16:29:59.095174 # ok 709 Set VL 3792
6602 16:29:59.095256 # ok 710 # SKIP Disabled ZA for VL 3792
6603 16:29:59.095335 # ok 711 # SKIP Get and set data for VL 3792
6604 16:29:59.095414 # ok 712 Set VL 3808
6605 16:29:59.095492 # ok 713 # SKIP Disabled ZA for VL 3808
6606 16:29:59.095571 # ok 714 # SKIP Get and set data for VL 3808
6607 16:29:59.095650 # ok 715 Set VL 3824
6608 16:29:59.095729 # ok 716 # SKIP Disabled ZA for VL 3824
6609 16:29:59.095808 # ok 717 # SKIP Get and set data for VL 3824
6610 16:29:59.095885 # ok 718 Set VL 3840
6611 16:29:59.095960 # ok 719 # SKIP Disabled ZA for VL 3840
6612 16:29:59.096037 # ok 720 # SKIP Get and set data for VL 3840
6613 16:29:59.096117 # ok 721 Set VL 3856
6614 16:29:59.096196 # ok 722 # SKIP Disabled ZA for VL 3856
6615 16:29:59.096275 # ok 723 # SKIP Get and set data for VL 3856
6616 16:29:59.096354 # ok 724 Set VL 3872
6617 16:29:59.096432 # ok 725 # SKIP Disabled ZA for VL 3872
6618 16:29:59.096510 # ok 726 # SKIP Get and set data for VL 3872
6619 16:29:59.096589 # ok 727 Set VL 3888
6620 16:29:59.096668 # ok 728 # SKIP Disabled ZA for VL 3888
6621 16:29:59.096746 # ok 729 # SKIP Get and set data for VL 3888
6622 16:29:59.096826 # ok 730 Set VL 3904
6623 16:29:59.096904 # ok 731 # SKIP Disabled ZA for VL 3904
6624 16:29:59.096984 # ok 732 # SKIP Get and set data for VL 3904
6625 16:29:59.097063 # ok 733 Set VL 3920
6626 16:29:59.097143 # ok 734 # SKIP Disabled ZA for VL 3920
6627 16:29:59.097221 # ok 735 # SKIP Get and set data for VL 3920
6628 16:29:59.097299 # ok 736 Set VL 3936
6629 16:29:59.097377 # ok 737 # SKIP Disabled ZA for VL 3936
6630 16:29:59.097454 # ok 738 # SKIP Get and set data for VL 3936
6631 16:29:59.097533 # ok 739 Set VL 3952
6632 16:29:59.097610 # ok 740 # SKIP Disabled ZA for VL 3952
6633 16:29:59.097700 # ok 741 # SKIP Get and set data for VL 3952
6634 16:29:59.097778 # ok 742 Set VL 3968
6635 16:29:59.097856 # ok 743 # SKIP Disabled ZA for VL 3968
6636 16:29:59.097935 # ok 744 # SKIP Get and set data for VL 3968
6637 16:29:59.098013 # ok 745 Set VL 3984
6638 16:29:59.098091 # ok 746 # SKIP Disabled ZA for VL 3984
6639 16:29:59.098176 # ok 747 # SKIP Get and set data for VL 3984
6640 16:29:59.098254 # ok 748 Set VL 4000
6641 16:29:59.098333 # ok 749 # SKIP Disabled ZA for VL 4000
6642 16:29:59.098411 # ok 750 # SKIP Get and set data for VL 4000
6643 16:29:59.098490 # ok 751 Set VL 4016
6644 16:29:59.098568 # ok 752 # SKIP Disabled ZA for VL 4016
6645 16:29:59.147620 # ok 753 # SKIP Get and set data for VL 4016
6646 16:29:59.148293 # ok 754 Set VL 4032
6647 16:29:59.149145 # ok 755 # SKIP Disabled ZA for VL 4032
6648 16:29:59.149229 # ok 756 # SKIP Get and set data for VL 4032
6649 16:29:59.149513 # ok 757 Set VL 4048
6650 16:29:59.149601 # ok 758 # SKIP Disabled ZA for VL 4048
6651 16:29:59.149720 # ok 759 # SKIP Get and set data for VL 4048
6652 16:29:59.149829 # ok 760 Set VL 4064
6653 16:29:59.149938 # ok 761 # SKIP Disabled ZA for VL 4064
6654 16:29:59.150047 # ok 762 # SKIP Get and set data for VL 4064
6655 16:29:59.150156 # ok 763 Set VL 4080
6656 16:29:59.150266 # ok 764 # SKIP Disabled ZA for VL 4080
6657 16:29:59.150375 # ok 765 # SKIP Get and set data for VL 4080
6658 16:29:59.150484 # ok 766 Set VL 4096
6659 16:29:59.150594 # ok 767 # SKIP Disabled ZA for VL 4096
6660 16:29:59.163432 # ok 768 # SKIP Get and set data for VL 4096
6661 16:29:59.163659 # ok 769 Set VL 4112
6662 16:29:59.163976 # ok 770 # SKIP Disabled ZA for VL 4112
6663 16:29:59.164102 # ok 771 # SKIP Get and set data for VL 4112
6664 16:29:59.164203 # ok 772 Set VL 4128
6665 16:29:59.164296 # ok 773 # SKIP Disabled ZA for VL 4128
6666 16:29:59.164381 # ok 774 # SKIP Get and set data for VL 4128
6667 16:29:59.164482 # ok 775 Set VL 4144
6668 16:29:59.164791 # ok 776 # SKIP Disabled ZA for VL 4144
6669 16:29:59.164878 # ok 777 # SKIP Get and set data for VL 4144
6670 16:29:59.164969 # ok 778 Set VL 4160
6671 16:29:59.165047 # ok 779 # SKIP Disabled ZA for VL 4160
6672 16:29:59.165121 # ok 780 # SKIP Get and set data for VL 4160
6673 16:29:59.165196 # ok 781 Set VL 4176
6674 16:29:59.179427 # ok 782 # SKIP Disabled ZA for VL 4176
6675 16:29:59.179671 # ok 783 # SKIP Get and set data for VL 4176
6676 16:29:59.179779 # ok 784 Set VL 4192
6677 16:29:59.180114 # ok 785 # SKIP Disabled ZA for VL 4192
6678 16:29:59.180261 # ok 786 # SKIP Get and set data for VL 4192
6679 16:29:59.180375 # ok 787 Set VL 4208
6680 16:29:59.180493 # ok 788 # SKIP Disabled ZA for VL 4208
6681 16:29:59.180632 # ok 789 # SKIP Get and set data for VL 4208
6682 16:29:59.180943 # ok 790 Set VL 4224
6683 16:29:59.181044 # ok 791 # SKIP Disabled ZA for VL 4224
6684 16:29:59.181126 # ok 792 # SKIP Get and set data for VL 4224
6685 16:29:59.181206 # ok 793 Set VL 4240
6686 16:29:59.181288 # ok 794 # SKIP Disabled ZA for VL 4240
6687 16:29:59.195441 # ok 795 # SKIP Get and set data for VL 4240
6688 16:29:59.195877 # ok 796 Set VL 4256
6689 16:29:59.195980 # ok 797 # SKIP Disabled ZA for VL 4256
6690 16:29:59.196090 # ok 798 # SKIP Get and set data for VL 4256
6691 16:29:59.196182 # ok 799 Set VL 4272
6692 16:29:59.196307 # ok 800 # SKIP Disabled ZA for VL 4272
6693 16:29:59.196443 # ok 801 # SKIP Get and set data for VL 4272
6694 16:29:59.196540 # ok 802 Set VL 4288
6695 16:29:59.196649 # ok 803 # SKIP Disabled ZA for VL 4288
6696 16:29:59.196759 # ok 804 # SKIP Get and set data for VL 4288
6697 16:29:59.196857 # ok 805 Set VL 4304
6698 16:29:59.196959 # ok 806 # SKIP Disabled ZA for VL 4304
6699 16:29:59.197043 # ok 807 # SKIP Get and set data for VL 4304
6700 16:29:59.197123 # ok 808 Set VL 4320
6701 16:29:59.210644 # ok 809 # SKIP Disabled ZA for VL 4320
6702 16:29:59.211127 # ok 810 # SKIP Get and set data for VL 4320
6703 16:29:59.211233 # ok 811 Set VL 4336
6704 16:29:59.211323 # ok 812 # SKIP Disabled ZA for VL 4336
6705 16:29:59.211411 # ok 813 # SKIP Get and set data for VL 4336
6706 16:29:59.211498 # ok 814 Set VL 4352
6707 16:29:59.211840 # ok 815 # SKIP Disabled ZA for VL 4352
6708 16:29:59.211959 # ok 816 # SKIP Get and set data for VL 4352
6709 16:29:59.212042 # ok 817 Set VL 4368
6710 16:29:59.212125 # ok 818 # SKIP Disabled ZA for VL 4368
6711 16:29:59.212204 # ok 819 # SKIP Get and set data for VL 4368
6712 16:29:59.212282 # ok 820 Set VL 4384
6713 16:29:59.212376 # ok 821 # SKIP Disabled ZA for VL 4384
6714 16:29:59.228880 # ok 822 # SKIP Get and set data for VL 4384
6715 16:29:59.229083 # ok 823 Set VL 4400
6716 16:29:59.229187 # ok 824 # SKIP Disabled ZA for VL 4400
6717 16:29:59.236820 # ok 825 # SKIP Get and set data for VL 4400
6718 16:29:59.243796 # ok 826 Set VL 4416
6719 16:29:59.244003 # ok 827 # SKIP Disabled ZA for VL 4416
6720 16:29:59.244086 # ok 828 # SKIP Get and set data for VL 4416
6721 16:29:59.244164 # ok 829 Set VL 4432
6722 16:29:59.244763 # ok 830 # SKIP Disabled ZA for VL 4432
6723 16:29:59.244865 # ok 831 # SKIP Get and set data for VL 4432
6724 16:29:59.244947 # ok 832 Set VL 4448
6725 16:29:59.245027 # ok 833 # SKIP Disabled ZA for VL 4448
6726 16:29:59.245106 # ok 834 # SKIP Get and set data for VL 4448
6727 16:29:59.245185 # ok 835 Set VL 4464
6728 16:29:59.245263 # ok 836 # SKIP Disabled ZA for VL 4464
6729 16:29:59.245340 # ok 837 # SKIP Get and set data for VL 4464
6730 16:29:59.245417 # ok 838 Set VL 4480
6731 16:29:59.245495 # ok 839 # SKIP Disabled ZA for VL 4480
6732 16:29:59.252283 # ok 840 # SKIP Get and set data for VL 4480
6733 16:29:59.252493 # ok 841 Set VL 4496
6734 16:29:59.252585 # ok 842 # SKIP Disabled ZA for VL 4496
6735 16:29:59.252668 # ok 843 # SKIP Get and set data for VL 4496
6736 16:29:59.252754 # ok 844 Set VL 4512
6737 16:29:59.252820 # ok 845 # SKIP Disabled ZA for VL 4512
6738 16:29:59.252887 # ok 846 # SKIP Get and set data for VL 4512
6739 16:29:59.252950 # ok 847 Set VL 4528
6740 16:29:59.253215 # ok 848 # SKIP Disabled ZA for VL 4528
6741 16:29:59.253299 # ok 849 # SKIP Get and set data for VL 4528
6742 16:29:59.253366 # ok 850 Set VL 4544
6743 16:29:59.253429 # ok 851 # SKIP Disabled ZA for VL 4544
6744 16:29:59.254378 # ok 852 # SKIP Get and set data for VL 4544
6745 16:29:59.254685 # ok 853 Set VL 4560
6746 16:29:59.254786 # ok 854 # SKIP Disabled ZA for VL 4560
6747 16:29:59.254912 # ok 855 # SKIP Get and set data for VL 4560
6748 16:29:59.255023 # ok 856 Set VL 4576
6749 16:29:59.255135 # ok 857 # SKIP Disabled ZA for VL 4576
6750 16:29:59.255272 # ok 858 # SKIP Get and set data for VL 4576
6751 16:29:59.255391 # ok 859 Set VL 4592
6752 16:29:59.255506 # ok 860 # SKIP Disabled ZA for VL 4592
6753 16:29:59.255634 # ok 861 # SKIP Get and set data for VL 4592
6754 16:29:59.255749 # ok 862 Set VL 4608
6755 16:29:59.255865 # ok 863 # SKIP Disabled ZA for VL 4608
6756 16:29:59.255997 # ok 864 # SKIP Get and set data for VL 4608
6757 16:29:59.256109 # ok 865 Set VL 4624
6758 16:29:59.256225 # ok 866 # SKIP Disabled ZA for VL 4624
6759 16:29:59.256365 # ok 867 # SKIP Get and set data for VL 4624
6760 16:29:59.256485 # ok 868 Set VL 4640
6761 16:29:59.256602 # ok 869 # SKIP Disabled ZA for VL 4640
6762 16:29:59.256717 # ok 870 # SKIP Get and set data for VL 4640
6763 16:29:59.256848 # ok 871 Set VL 4656
6764 16:29:59.256940 # ok 872 # SKIP Disabled ZA for VL 4656
6765 16:29:59.257019 # ok 873 # SKIP Get and set data for VL 4656
6766 16:29:59.257096 # ok 874 Set VL 4672
6767 16:29:59.272023 # ok 875 # SKIP Disabled ZA for VL 4672
6768 16:29:59.272697 # ok 876 # SKIP Get and set data for VL 4672
6769 16:29:59.272801 # ok 877 Set VL 4688
6770 16:29:59.272885 # ok 878 # SKIP Disabled ZA for VL 4688
6771 16:29:59.272969 # ok 879 # SKIP Get and set data for VL 4688
6772 16:29:59.273047 # ok 880 Set VL 4704
6773 16:29:59.273124 # ok 881 # SKIP Disabled ZA for VL 4704
6774 16:29:59.273201 # ok 882 # SKIP Get and set data for VL 4704
6775 16:29:59.273277 # ok 883 Set VL 4720
6776 16:29:59.273353 # ok 884 # SKIP Disabled ZA for VL 4720
6777 16:29:59.279262 # ok 885 # SKIP Get and set data for VL 4720
6778 16:29:59.279514 # ok 886 Set VL 4736
6779 16:29:59.279837 # ok 887 # SKIP Disabled ZA for VL 4736
6780 16:29:59.279944 # ok 888 # SKIP Get and set data for VL 4736
6781 16:29:59.280036 # ok 889 Set VL 4752
6782 16:29:59.280118 # ok 890 # SKIP Disabled ZA for VL 4752
6783 16:29:59.280199 # ok 891 # SKIP Get and set data for VL 4752
6784 16:29:59.280269 # ok 892 Set VL 4768
6785 16:29:59.280389 # ok 893 # SKIP Disabled ZA for VL 4768
6786 16:29:59.280485 # ok 894 # SKIP Get and set data for VL 4768
6787 16:29:59.280585 # ok 895 Set VL 4784
6788 16:29:59.280688 # ok 896 # SKIP Disabled ZA for VL 4784
6789 16:29:59.280783 # ok 897 # SKIP Get and set data for VL 4784
6790 16:29:59.280867 # ok 898 Set VL 4800
6791 16:29:59.280948 # ok 899 # SKIP Disabled ZA for VL 4800
6792 16:29:59.281012 # ok 900 # SKIP Get and set data for VL 4800
6793 16:29:59.281074 # ok 901 Set VL 4816
6794 16:29:59.288864 # ok 902 # SKIP Disabled ZA for VL 4816
6795 16:29:59.300099 # ok 903 # SKIP Get and set data for VL 4816
6796 16:29:59.300351 # ok 904 Set VL 4832
6797 16:29:59.301380 # ok 905 # SKIP Disabled ZA for VL 4832
6798 16:29:59.301501 # ok 906 # SKIP Get and set data for VL 4832
6799 16:29:59.301613 # ok 907 Set VL 4848
6800 16:29:59.301733 # ok 908 # SKIP Disabled ZA for VL 4848
6801 16:29:59.301848 # ok 909 # SKIP Get and set data for VL 4848
6802 16:29:59.301959 # ok 910 Set VL 4864
6803 16:29:59.308732 # ok 911 # SKIP Disabled ZA for VL 4864
6804 16:29:59.308946 # ok 912 # SKIP Get and set data for VL 4864
6805 16:29:59.309046 # ok 913 Set VL 4880
6806 16:29:59.309148 # ok 914 # SKIP Disabled ZA for VL 4880
6807 16:29:59.309269 # ok 915 # SKIP Get and set data for VL 4880
6808 16:29:59.309390 # ok 916 Set VL 4896
6809 16:29:59.309496 # ok 917 # SKIP Disabled ZA for VL 4896
6810 16:29:59.309584 # ok 918 # SKIP Get and set data for VL 4896
6811 16:29:59.309675 # ok 919 Set VL 4912
6812 16:29:59.309756 # ok 920 # SKIP Disabled ZA for VL 4912
6813 16:29:59.309834 # ok 921 # SKIP Get and set data for VL 4912
6814 16:29:59.310131 # ok 922 Set VL 4928
6815 16:29:59.318297 # ok 923 # SKIP Disabled ZA for VL 4928
6816 16:29:59.318775 # ok 924 # SKIP Get and set data for VL 4928
6817 16:29:59.318900 # ok 925 Set VL 4944
6818 16:29:59.319013 # ok 926 # SKIP Disabled ZA for VL 4944
6819 16:29:59.319126 # ok 927 # SKIP Get and set data for VL 4944
6820 16:29:59.319246 # ok 928 Set VL 4960
6821 16:29:59.319380 # ok 929 # SKIP Disabled ZA for VL 4960
6822 16:29:59.319491 # ok 930 # SKIP Get and set data for VL 4960
6823 16:29:59.319597 # ok 931 Set VL 4976
6824 16:29:59.319710 # ok 932 # SKIP Disabled ZA for VL 4976
6825 16:29:59.319828 # ok 933 # SKIP Get and set data for VL 4976
6826 16:29:59.319940 # ok 934 Set VL 4992
6827 16:29:59.320069 # ok 935 # SKIP Disabled ZA for VL 4992
6828 16:29:59.320183 # ok 936 # SKIP Get and set data for VL 4992
6829 16:29:59.320297 # ok 937 Set VL 5008
6830 16:29:59.320406 # ok 938 # SKIP Disabled ZA for VL 5008
6831 16:29:59.320516 # ok 939 # SKIP Get and set data for VL 5008
6832 16:29:59.320630 # ok 940 Set VL 5024
6833 16:29:59.320755 # ok 941 # SKIP Disabled ZA for VL 5024
6834 16:29:59.320869 # ok 942 # SKIP Get and set data for VL 5024
6835 16:29:59.320971 # ok 943 Set VL 5040
6836 16:29:59.321065 # ok 944 # SKIP Disabled ZA for VL 5040
6837 16:29:59.321146 # ok 945 # SKIP Get and set data for VL 5040
6838 16:29:59.321225 # ok 946 Set VL 5056
6839 16:29:59.321320 # ok 947 # SKIP Disabled ZA for VL 5056
6840 16:29:59.327275 # ok 948 # SKIP Get and set data for VL 5056
6841 16:29:59.327721 # ok 949 Set VL 5072
6842 16:29:59.327841 # ok 950 # SKIP Disabled ZA for VL 5072
6843 16:29:59.327957 # ok 951 # SKIP Get and set data for VL 5072
6844 16:29:59.328070 # ok 952 Set VL 5088
6845 16:29:59.328200 # ok 953 # SKIP Disabled ZA for VL 5088
6846 16:29:59.328317 # ok 954 # SKIP Get and set data for VL 5088
6847 16:29:59.328428 # ok 955 Set VL 5104
6848 16:29:59.328542 # ok 956 # SKIP Disabled ZA for VL 5104
6849 16:29:59.328652 # ok 957 # SKIP Get and set data for VL 5104
6850 16:29:59.328783 # ok 958 Set VL 5120
6851 16:29:59.328882 # ok 959 # SKIP Disabled ZA for VL 5120
6852 16:29:59.328966 # ok 960 # SKIP Get and set data for VL 5120
6853 16:29:59.329045 # ok 961 Set VL 5136
6854 16:29:59.329124 # ok 962 # SKIP Disabled ZA for VL 5136
6855 16:29:59.339212 # ok 963 # SKIP Get and set data for VL 5136
6856 16:29:59.339672 # ok 964 Set VL 5152
6857 16:29:59.339790 # ok 965 # SKIP Disabled ZA for VL 5152
6858 16:29:59.339895 # ok 966 # SKIP Get and set data for VL 5152
6859 16:29:59.340007 # ok 967 Set VL 5168
6860 16:29:59.340132 # ok 968 # SKIP Disabled ZA for VL 5168
6861 16:29:59.340237 # ok 969 # SKIP Get and set data for VL 5168
6862 16:29:59.340344 # ok 970 Set VL 5184
6863 16:29:59.340452 # ok 971 # SKIP Disabled ZA for VL 5184
6864 16:29:59.340560 # ok 972 # SKIP Get and set data for VL 5184
6865 16:29:59.340685 # ok 973 Set VL 5200
6866 16:29:59.340789 # ok 974 # SKIP Disabled ZA for VL 5200
6867 16:29:59.340876 # ok 975 # SKIP Get and set data for VL 5200
6868 16:29:59.340956 # ok 976 Set VL 5216
6869 16:29:59.341035 # ok 977 # SKIP Disabled ZA for VL 5216
6870 16:29:59.341129 # ok 978 # SKIP Get and set data for VL 5216
6871 16:29:59.342771 # ok 979 Set VL 5232
6872 16:29:59.342907 # ok 980 # SKIP Disabled ZA for VL 5232
6873 16:29:59.343031 # ok 981 # SKIP Get and set data for VL 5232
6874 16:29:59.343135 # ok 982 Set VL 5248
6875 16:29:59.343257 # ok 983 # SKIP Disabled ZA for VL 5248
6876 16:29:59.343364 # ok 984 # SKIP Get and set data for VL 5248
6877 16:29:59.343467 # ok 985 Set VL 5264
6878 16:29:59.343585 # ok 986 # SKIP Disabled ZA for VL 5264
6879 16:29:59.343693 # ok 987 # SKIP Get and set data for VL 5264
6880 16:29:59.343821 # ok 988 Set VL 5280
6881 16:29:59.343924 # ok 989 # SKIP Disabled ZA for VL 5280
6882 16:29:59.344031 # ok 990 # SKIP Get and set data for VL 5280
6883 16:29:59.344154 # ok 991 Set VL 5296
6884 16:29:59.344268 # ok 992 # SKIP Disabled ZA for VL 5296
6885 16:29:59.344373 # ok 993 # SKIP Get and set data for VL 5296
6886 16:29:59.344482 # ok 994 Set VL 5312
6887 16:29:59.344605 # ok 995 # SKIP Disabled ZA for VL 5312
6888 16:29:59.344711 # ok 996 # SKIP Get and set data for VL 5312
6889 16:29:59.344815 # ok 997 Set VL 5328
6890 16:29:59.344923 # ok 998 # SKIP Disabled ZA for VL 5328
6891 16:29:59.346193 # ok 999 # SKIP Get and set data for VL 5328
6892 16:29:59.346512 # ok 1000 Set VL 5344
6893 16:29:59.346610 # ok 1001 # SKIP Disabled ZA for VL 5344
6894 16:29:59.346703 # ok 1002 # SKIP Get and set data for VL 5344
6895 16:29:59.346800 # ok 1003 Set VL 5360
6896 16:29:59.346872 # ok 1004 # SKIP Disabled ZA for VL 5360
6897 16:29:59.346948 # ok 1005 # SKIP Get and set data for VL 5360
6898 16:29:59.347038 # ok 1006 Set VL 5376
6899 16:29:59.347109 # ok 1007 # SKIP Disabled ZA for VL 5376
6900 16:29:59.347199 # ok 1008 # SKIP Get and set data for VL 5376
6901 16:29:59.347270 # ok 1009 Set VL 5392
6902 16:29:59.347361 # ok 1010 # SKIP Disabled ZA for VL 5392
6903 16:29:59.347630 # ok 1011 # SKIP Get and set data for VL 5392
6904 16:29:59.347734 # ok 1012 Set VL 5408
6905 16:29:59.347842 # ok 1013 # SKIP Disabled ZA for VL 5408
6906 16:29:59.347945 # ok 1014 # SKIP Get and set data for VL 5408
6907 16:29:59.348027 # ok 1015 Set VL 5424
6908 16:29:59.348120 # ok 1016 # SKIP Disabled ZA for VL 5424
6909 16:29:59.348241 # ok 1017 # SKIP Get and set data for VL 5424
6910 16:29:59.348357 # ok 1018 Set VL 5440
6911 16:29:59.348454 # ok 1019 # SKIP Disabled ZA for VL 5440
6912 16:29:59.348549 # ok 1020 # SKIP Get and set data for VL 5440
6913 16:29:59.348630 # ok 1021 Set VL 5456
6914 16:29:59.348742 # ok 1022 # SKIP Disabled ZA for VL 5456
6915 16:29:59.348849 # ok 1023 # SKIP Get and set data for VL 5456
6916 16:29:59.348930 # ok 1024 Set VL 5472
6917 16:29:59.355756 # ok 1025 # SKIP Disabled ZA for VL 5472
6918 16:29:59.356174 # ok 1026 # SKIP Get and set data for VL 5472
6919 16:29:59.356276 # ok 1027 Set VL 5488
6920 16:29:59.356378 # ok 1028 # SKIP Disabled ZA for VL 5488
6921 16:29:59.356488 # ok 1029 # SKIP Get and set data for VL 5488
6922 16:29:59.356618 # ok 1030 Set VL 5504
6923 16:29:59.356723 # ok 1031 # SKIP Disabled ZA for VL 5504
6924 16:29:59.356833 # ok 1032 # SKIP Get and set data for VL 5504
6925 16:29:59.356943 # ok 1033 Set VL 5520
6926 16:29:59.357072 # ok 1034 # SKIP Disabled ZA for VL 5520
6927 16:29:59.366721 # ok 1035 # SKIP Get and set data for VL 5520
6928 16:29:59.367241 # ok 1036 Set VL 5536
6929 16:29:59.367349 # ok 1037 # SKIP Disabled ZA for VL 5536
6930 16:29:59.367461 # ok 1038 # SKIP Get and set data for VL 5536
6931 16:29:59.367573 # ok 1039 Set VL 5552
6932 16:29:59.367657 # ok 1040 # SKIP Disabled ZA for VL 5552
6933 16:29:59.367938 # ok 1041 # SKIP Get and set data for VL 5552
6934 16:29:59.368039 # ok 1042 Set VL 5568
6935 16:29:59.368119 # ok 1043 # SKIP Disabled ZA for VL 5568
6936 16:29:59.368197 # ok 1044 # SKIP Get and set data for VL 5568
6937 16:29:59.368288 # ok 1045 Set VL 5584
6938 16:29:59.368841 # ok 1046 # SKIP Disabled ZA for VL 5584
6939 16:29:59.368941 # ok 1047 # SKIP Get and set data for VL 5584
6940 16:29:59.369021 # ok 1048 Set VL 5600
6941 16:29:59.369099 # ok 1049 # SKIP Disabled ZA for VL 5600
6942 16:29:59.369175 # ok 1050 # SKIP Get and set data for VL 5600
6943 16:29:59.369251 # ok 1051 Set VL 5616
6944 16:29:59.378599 # ok 1052 # SKIP Disabled ZA for VL 5616
6945 16:29:59.383587 # ok 1053 # SKIP Get and set data for VL 5616
6946 16:29:59.383987 # ok 1054 Set VL 5632
6947 16:29:59.384654 # ok 1055 # SKIP Disabled ZA for VL 5632
6948 16:29:59.384777 # ok 1056 # SKIP Get and set data for VL 5632
6949 16:29:59.384867 # ok 1057 Set VL 5648
6950 16:29:59.386700 # ok 1058 # SKIP Disabled ZA for VL 5648
6951 16:29:59.386810 # ok 1059 # SKIP Get and set data for VL 5648
6952 16:29:59.386919 # ok 1060 Set VL 5664
6953 16:29:59.387030 # ok 1061 # SKIP Disabled ZA for VL 5664
6954 16:29:59.387148 # ok 1062 # SKIP Get and set data for VL 5664
6955 16:29:59.387258 # ok 1063 Set VL 5680
6956 16:29:59.387348 # ok 1064 # SKIP Disabled ZA for VL 5680
6957 16:29:59.387446 # ok 1065 # SKIP Get and set data for VL 5680
6958 16:29:59.387528 # ok 1066 Set VL 5696
6959 16:29:59.387607 # ok 1067 # SKIP Disabled ZA for VL 5696
6960 16:29:59.387708 # ok 1068 # SKIP Get and set data for VL 5696
6961 16:29:59.388086 # ok 1069 Set VL 5712
6962 16:29:59.388198 # ok 1070 # SKIP Disabled ZA for VL 5712
6963 16:29:59.388504 # ok 1071 # SKIP Get and set data for VL 5712
6964 16:29:59.388610 # ok 1072 Set VL 5728
6965 16:29:59.388722 # ok 1073 # SKIP Disabled ZA for VL 5728
6966 16:29:59.388823 # ok 1074 # SKIP Get and set data for VL 5728
6967 16:29:59.388909 # ok 1075 Set VL 5744
6968 16:29:59.389004 # ok 1076 # SKIP Disabled ZA for VL 5744
6969 16:29:59.389086 # ok 1077 # SKIP Get and set data for VL 5744
6970 16:29:59.389166 # ok 1078 Set VL 5760
6971 16:29:59.389244 # ok 1079 # SKIP Disabled ZA for VL 5760
6972 16:29:59.397081 # ok 1080 # SKIP Get and set data for VL 5760
6973 16:29:59.397324 # ok 1081 Set VL 5776
6974 16:29:59.397450 # ok 1082 # SKIP Disabled ZA for VL 5776
6975 16:29:59.397563 # ok 1083 # SKIP Get and set data for VL 5776
6976 16:29:59.397663 # ok 1084 Set VL 5792
6977 16:29:59.397769 # ok 1085 # SKIP Disabled ZA for VL 5792
6978 16:29:59.397860 # ok 1086 # SKIP Get and set data for VL 5792
6979 16:29:59.397965 # ok 1087 Set VL 5808
6980 16:29:59.398080 # ok 1088 # SKIP Disabled ZA for VL 5808
6981 16:29:59.398177 # ok 1089 # SKIP Get and set data for VL 5808
6982 16:29:59.398258 # ok 1090 Set VL 5824
6983 16:29:59.398350 # ok 1091 # SKIP Disabled ZA for VL 5824
6984 16:29:59.398447 # ok 1092 # SKIP Get and set data for VL 5824
6985 16:29:59.398526 # ok 1093 Set VL 5840
6986 16:29:59.398620 # ok 1094 # SKIP Disabled ZA for VL 5840
6987 16:29:59.398719 # ok 1095 # SKIP Get and set data for VL 5840
6988 16:29:59.398820 # ok 1096 Set VL 5856
6989 16:29:59.398921 # ok 1097 # SKIP Disabled ZA for VL 5856
6990 16:29:59.399365 # ok 1098 # SKIP Get and set data for VL 5856
6991 16:29:59.399458 # ok 1099 Set VL 5872
6992 16:29:59.399549 # ok 1100 # SKIP Disabled ZA for VL 5872
6993 16:29:59.410671 # ok 1101 # SKIP Get and set data for VL 5872
6994 16:29:59.411143 # ok 1102 Set VL 5888
6995 16:29:59.411247 # ok 1103 # SKIP Disabled ZA for VL 5888
6996 16:29:59.411357 # ok 1104 # SKIP Get and set data for VL 5888
6997 16:29:59.411461 # ok 1105 Set VL 5904
6998 16:29:59.411544 # ok 1106 # SKIP Disabled ZA for VL 5904
6999 16:29:59.411636 # ok 1107 # SKIP Get and set data for VL 5904
7000 16:29:59.411895 # ok 1108 Set VL 5920
7001 16:29:59.412227 # ok 1109 # SKIP Disabled ZA for VL 5920
7002 16:29:59.412522 # ok 1110 # SKIP Get and set data for VL 5920
7003 16:29:59.412622 # ok 1111 Set VL 5936
7004 16:29:59.412702 # ok 1112 # SKIP Disabled ZA for VL 5936
7005 16:29:59.423118 # ok 1113 # SKIP Get and set data for VL 5936
7006 16:29:59.423548 # ok 1114 Set VL 5952
7007 16:29:59.423673 # ok 1115 # SKIP Disabled ZA for VL 5952
7008 16:29:59.423985 # ok 1116 # SKIP Get and set data for VL 5952
7009 16:29:59.424088 # ok 1117 Set VL 5968
7010 16:29:59.424392 # ok 1118 # SKIP Disabled ZA for VL 5968
7011 16:29:59.424497 # ok 1119 # SKIP Get and set data for VL 5968
7012 16:29:59.424600 # ok 1120 Set VL 5984
7013 16:29:59.424715 # ok 1121 # SKIP Disabled ZA for VL 5984
7014 16:29:59.424800 # ok 1122 # SKIP Get and set data for VL 5984
7015 16:29:59.426643 # ok 1123 Set VL 6000
7016 16:29:59.426765 # ok 1124 # SKIP Disabled ZA for VL 6000
7017 16:29:59.427068 # ok 1125 # SKIP Get and set data for VL 6000
7018 16:29:59.427176 # ok 1126 Set VL 6016
7019 16:29:59.427266 # ok 1127 # SKIP Disabled ZA for VL 6016
7020 16:29:59.427367 # ok 1128 # SKIP Get and set data for VL 6016
7021 16:29:59.427457 # ok 1129 Set VL 6032
7022 16:29:59.427559 # ok 1130 # SKIP Disabled ZA for VL 6032
7023 16:29:59.427648 # ok 1131 # SKIP Get and set data for VL 6032
7024 16:29:59.427755 # ok 1132 Set VL 6048
7025 16:29:59.427855 # ok 1133 # SKIP Disabled ZA for VL 6048
7026 16:29:59.428160 # ok 1134 # SKIP Get and set data for VL 6048
7027 16:29:59.428267 # ok 1135 Set VL 6064
7028 16:29:59.428369 # ok 1136 # SKIP Disabled ZA for VL 6064
7029 16:29:59.428472 # ok 1137 # SKIP Get and set data for VL 6064
7030 16:29:59.428572 # ok 1138 Set VL 6080
7031 16:29:59.428673 # ok 1139 # SKIP Disabled ZA for VL 6080
7032 16:29:59.436871 # ok 1140 # SKIP Get and set data for VL 6080
7033 16:29:59.438633 # ok 1141 Set VL 6096
7034 16:29:59.438972 # ok 1142 # SKIP Disabled ZA for VL 6096
7035 16:29:59.439091 # ok 1143 # SKIP Get and set data for VL 6096
7036 16:29:59.439226 # ok 1144 Set VL 6112
7037 16:29:59.439572 # ok 1145 # SKIP Disabled ZA for VL 6112
7038 16:29:59.439701 # ok 1146 # SKIP Get and set data for VL 6112
7039 16:29:59.440017 # ok 1147 Set VL 6128
7040 16:29:59.440142 # ok 1148 # SKIP Disabled ZA for VL 6128
7041 16:29:59.440463 # ok 1149 # SKIP Get and set data for VL 6128
7042 16:29:59.440574 # ok 1150 Set VL 6144
7043 16:29:59.440685 # ok 1151 # SKIP Disabled ZA for VL 6144
7044 16:29:59.446769 # ok 1152 # SKIP Get and set data for VL 6144
7045 16:29:59.447199 # ok 1153 Set VL 6160
7046 16:29:59.447315 # ok 1154 # SKIP Disabled ZA for VL 6160
7047 16:29:59.447441 # ok 1155 # SKIP Get and set data for VL 6160
7048 16:29:59.447551 # ok 1156 Set VL 6176
7049 16:29:59.447682 # ok 1157 # SKIP Disabled ZA for VL 6176
7050 16:29:59.448013 # ok 1158 # SKIP Get and set data for VL 6176
7051 16:29:59.448126 # ok 1159 Set VL 6192
7052 16:29:59.448244 # ok 1160 # SKIP Disabled ZA for VL 6192
7053 16:29:59.448367 # ok 1161 # SKIP Get and set data for VL 6192
7054 16:29:59.448483 # ok 1162 Set VL 6208
7055 16:29:59.448778 # ok 1163 # SKIP Disabled ZA for VL 6208
7056 16:29:59.448879 # ok 1164 # SKIP Get and set data for VL 6208
7057 16:29:59.449884 # ok 1165 Set VL 6224
7058 16:29:59.450570 # ok 1166 # SKIP Disabled ZA for VL 6224
7059 16:29:59.450693 # ok 1167 # SKIP Get and set data for VL 6224
7060 16:29:59.450797 # ok 1168 Set VL 6240
7061 16:29:59.451126 # ok 1169 # SKIP Disabled ZA for VL 6240
7062 16:29:59.451416 # ok 1170 # SKIP Get and set data for VL 6240
7063 16:29:59.451518 # ok 1171 Set VL 6256
7064 16:29:59.451613 # ok 1172 # SKIP Disabled ZA for VL 6256
7065 16:29:59.451693 # ok 1173 # SKIP Get and set data for VL 6256
7066 16:29:59.451783 # ok 1174 Set VL 6272
7067 16:29:59.451873 # ok 1175 # SKIP Disabled ZA for VL 6272
7068 16:29:59.451994 # ok 1176 # SKIP Get and set data for VL 6272
7069 16:29:59.452384 # ok 1177 Set VL 6288
7070 16:29:59.452508 # ok 1178 # SKIP Disabled ZA for VL 6288
7071 16:29:59.452629 # ok 1179 # SKIP Get and set data for VL 6288
7072 16:29:59.452756 # ok 1180 Set VL 6304
7073 16:29:59.452876 # ok 1181 # SKIP Disabled ZA for VL 6304
7074 16:29:59.455450 # ok 1182 # SKIP Get and set data for VL 6304
7075 16:29:59.455979 # ok 1183 Set VL 6320
7076 16:29:59.456093 # ok 1184 # SKIP Disabled ZA for VL 6320
7077 16:29:59.456366 # ok 1185 # SKIP Get and set data for VL 6320
7078 16:29:59.456472 # ok 1186 Set VL 6336
7079 16:29:59.456753 # ok 1187 # SKIP Disabled ZA for VL 6336
7080 16:29:59.458536 # ok 1188 # SKIP Get and set data for VL 6336
7081 16:29:59.458643 # ok 1189 Set VL 6352
7082 16:29:59.458902 # ok 1190 # SKIP Disabled ZA for VL 6352
7083 16:29:59.459006 # ok 1191 # SKIP Get and set data for VL 6352
7084 16:29:59.459086 # ok 1192 Set VL 6368
7085 16:29:59.459164 # ok 1193 # SKIP Disabled ZA for VL 6368
7086 16:29:59.459255 # ok 1194 # SKIP Get and set data for VL 6368
7087 16:29:59.459333 # ok 1195 Set VL 6384
7088 16:29:59.459410 # ok 1196 # SKIP Disabled ZA for VL 6384
7089 16:29:59.459486 # ok 1197 # SKIP Get and set data for VL 6384
7090 16:29:59.459576 # ok 1198 Set VL 6400
7091 16:29:59.459655 # ok 1199 # SKIP Disabled ZA for VL 6400
7092 16:29:59.459745 # ok 1200 # SKIP Get and set data for VL 6400
7093 16:29:59.459823 # ok 1201 Set VL 6416
7094 16:29:59.459912 # ok 1202 # SKIP Disabled ZA for VL 6416
7095 16:29:59.460003 # ok 1203 # SKIP Get and set data for VL 6416
7096 16:29:59.460083 # ok 1204 Set VL 6432
7097 16:29:59.460171 # ok 1205 # SKIP Disabled ZA for VL 6432
7098 16:29:59.460262 # ok 1206 # SKIP Get and set data for VL 6432
7099 16:29:59.460353 # ok 1207 Set VL 6448
7100 16:29:59.460737 # ok 1208 # SKIP Disabled ZA for VL 6448
7101 16:29:59.460844 # ok 1209 # SKIP Get and set data for VL 6448
7102 16:29:59.460924 # ok 1210 Set VL 6464
7103 16:29:59.466854 # ok 1211 # SKIP Disabled ZA for VL 6464
7104 16:29:59.467464 # ok 1212 # SKIP Get and set data for VL 6464
7105 16:29:59.467566 # ok 1213 Set VL 6480
7106 16:29:59.467665 # ok 1214 # SKIP Disabled ZA for VL 6480
7107 16:29:59.467976 # ok 1215 # SKIP Get and set data for VL 6480
7108 16:29:59.468081 # ok 1216 Set VL 6496
7109 16:29:59.468175 # ok 1217 # SKIP Disabled ZA for VL 6496
7110 16:29:59.468291 # ok 1218 # SKIP Get and set data for VL 6496
7111 16:29:59.468375 # ok 1219 Set VL 6512
7112 16:29:59.468465 # ok 1220 # SKIP Disabled ZA for VL 6512
7113 16:29:59.468746 # ok 1221 # SKIP Get and set data for VL 6512
7114 16:29:59.468847 # ok 1222 Set VL 6528
7115 16:29:59.468926 # ok 1223 # SKIP Disabled ZA for VL 6528
7116 16:29:59.469862 # ok 1224 # SKIP Get and set data for VL 6528
7117 16:29:59.470165 # ok 1225 Set VL 6544
7118 16:29:59.470265 # ok 1226 # SKIP Disabled ZA for VL 6544
7119 16:29:59.470359 # ok 1227 # SKIP Get and set data for VL 6544
7120 16:29:59.470449 # ok 1228 Set VL 6560
7121 16:29:59.470539 # ok 1229 # SKIP Disabled ZA for VL 6560
7122 16:29:59.470635 # ok 1230 # SKIP Get and set data for VL 6560
7123 16:29:59.470725 # ok 1231 Set VL 6576
7124 16:29:59.471013 # ok 1232 # SKIP Disabled ZA for VL 6576
7125 16:29:59.471114 # ok 1233 # SKIP Get and set data for VL 6576
7126 16:29:59.471211 # ok 1234 Set VL 6592
7127 16:29:59.471292 # ok 1235 # SKIP Disabled ZA for VL 6592
7128 16:29:59.471370 # ok 1236 # SKIP Get and set data for VL 6592
7129 16:29:59.471463 # ok 1237 Set VL 6608
7130 16:29:59.471543 # ok 1238 # SKIP Disabled ZA for VL 6608
7131 16:29:59.471622 # ok 1239 # SKIP Get and set data for VL 6608
7132 16:29:59.471713 # ok 1240 Set VL 6624
7133 16:29:59.471793 # ok 1241 # SKIP Disabled ZA for VL 6624
7134 16:29:59.471884 # ok 1242 # SKIP Get and set data for VL 6624
7135 16:29:59.471964 # ok 1243 Set VL 6640
7136 16:29:59.472057 # ok 1244 # SKIP Disabled ZA for VL 6640
7137 16:29:59.472137 # ok 1245 # SKIP Get and set data for VL 6640
7138 16:29:59.472216 # ok 1246 Set VL 6656
7139 16:29:59.472308 # ok 1247 # SKIP Disabled ZA for VL 6656
7140 16:29:59.472389 # ok 1248 # SKIP Get and set data for VL 6656
7141 16:29:59.472479 # ok 1249 Set VL 6672
7142 16:29:59.472559 # ok 1250 # SKIP Disabled ZA for VL 6672
7143 16:29:59.472649 # ok 1251 # SKIP Get and set data for VL 6672
7144 16:29:59.472730 # ok 1252 Set VL 6688
7145 16:29:59.472823 # ok 1253 # SKIP Disabled ZA for VL 6688
7146 16:29:59.486544 # ok 1254 # SKIP Get and set data for VL 6688
7147 16:29:59.486974 # ok 1255 Set VL 6704
7148 16:29:59.487075 # ok 1256 # SKIP Disabled ZA for VL 6704
7149 16:29:59.487578 # ok 1257 # SKIP Get and set data for VL 6704
7150 16:29:59.487680 # ok 1258 Set VL 6720
7151 16:29:59.487762 # ok 1259 # SKIP Disabled ZA for VL 6720
7152 16:29:59.487855 # ok 1260 # SKIP Get and set data for VL 6720
7153 16:29:59.487938 # ok 1261 Set VL 6736
7154 16:29:59.488031 # ok 1262 # SKIP Disabled ZA for VL 6736
7155 16:29:59.488114 # ok 1263 # SKIP Get and set data for VL 6736
7156 16:29:59.488205 # ok 1264 Set VL 6752
7157 16:29:59.488300 # ok 1265 # SKIP Disabled ZA for VL 6752
7158 16:29:59.488420 # ok 1266 # SKIP Get and set data for VL 6752
7159 16:29:59.488517 # ok 1267 Set VL 6768
7160 16:29:59.488617 # ok 1268 # SKIP Disabled ZA for VL 6768
7161 16:29:59.488914 # ok 1269 # SKIP Get and set data for VL 6768
7162 16:29:59.494165 # ok 1270 Set VL 6784
7163 16:29:59.494605 # ok 1271 # SKIP Disabled ZA for VL 6784
7164 16:29:59.494922 # ok 1272 # SKIP Get and set data for VL 6784
7165 16:29:59.495028 # ok 1273 Set VL 6800
7166 16:29:59.495133 # ok 1274 # SKIP Disabled ZA for VL 6800
7167 16:29:59.495242 # ok 1275 # SKIP Get and set data for VL 6800
7168 16:29:59.495542 # ok 1276 Set VL 6816
7169 16:29:59.495816 # ok 1277 # SKIP Disabled ZA for VL 6816
7170 16:29:59.503911 # ok 1278 # SKIP Get and set data for VL 6816
7171 16:29:59.504123 # ok 1279 Set VL 6832
7172 16:29:59.504400 # ok 1280 # SKIP Disabled ZA for VL 6832
7173 16:29:59.504520 # ok 1281 # SKIP Get and set data for VL 6832
7174 16:29:59.504663 # ok 1282 Set VL 6848
7175 16:29:59.504757 # ok 1283 # SKIP Disabled ZA for VL 6848
7176 16:29:59.518283 # ok 1284 # SKIP Get and set data for VL 6848
7177 16:29:59.518727 # ok 1285 Set VL 6864
7178 16:29:59.518843 # ok 1286 # SKIP Disabled ZA for VL 6864
7179 16:29:59.519156 # ok 1287 # SKIP Get and set data for VL 6864
7180 16:29:59.519277 # ok 1288 Set VL 6880
7181 16:29:59.519620 # ok 1289 # SKIP Disabled ZA for VL 6880
7182 16:29:59.519946 # ok 1290 # SKIP Get and set data for VL 6880
7183 16:29:59.520064 # ok 1291 Set VL 6896
7184 16:29:59.520410 # ok 1292 # SKIP Disabled ZA for VL 6896
7185 16:29:59.520514 # ok 1293 # SKIP Get and set data for VL 6896
7186 16:29:59.520799 # ok 1294 Set VL 6912
7187 16:29:59.520901 # ok 1295 # SKIP Disabled ZA for VL 6912
7188 16:29:59.531973 # ok 1296 # SKIP Get and set data for VL 6912
7189 16:29:59.532403 # ok 1297 Set VL 6928
7190 16:29:59.532497 # ok 1298 # SKIP Disabled ZA for VL 6928
7191 16:29:59.532586 # ok 1299 # SKIP Get and set data for VL 6928
7192 16:29:59.532668 # ok 1300 Set VL 6944
7193 16:29:59.534103 # ok 1301 # SKIP Disabled ZA for VL 6944
7194 16:29:59.534433 # ok 1302 # SKIP Get and set data for VL 6944
7195 16:29:59.534546 # ok 1303 Set VL 6960
7196 16:29:59.535038 # ok 1304 # SKIP Disabled ZA for VL 6960
7197 16:29:59.535178 # ok 1305 # SKIP Get and set data for VL 6960
7198 16:29:59.535313 # ok 1306 Set VL 6976
7199 16:29:59.535840 # ok 1307 # SKIP Disabled ZA for VL 6976
7200 16:29:59.535955 # ok 1308 # SKIP Get and set data for VL 6976
7201 16:29:59.536272 # ok 1309 Set VL 6992
7202 16:29:59.536395 # ok 1310 # SKIP Disabled ZA for VL 6992
7203 16:29:59.536708 # ok 1311 # SKIP Get and set data for VL 6992
7204 16:29:59.536822 # ok 1312 Set VL 7008
7205 16:29:59.555173 # ok 1313 # SKIP Disabled ZA for VL 7008
7206 16:29:59.555659 # ok 1314 # SKIP Get and set data for VL 7008
7207 16:29:59.555771 # ok 1315 Set VL 7024
7208 16:29:59.555885 # ok 1316 # SKIP Disabled ZA for VL 7024
7209 16:29:59.556197 # ok 1317 # SKIP Get and set data for VL 7024
7210 16:29:59.556525 # ok 1318 Set VL 7040
7211 16:29:59.556655 # ok 1319 # SKIP Disabled ZA for VL 7040
7212 16:29:59.556782 # ok 1320 # SKIP Get and set data for VL 7040
7213 16:29:59.567263 # ok 1321 Set VL 7056
7214 16:29:59.568136 # ok 1322 # SKIP Disabled ZA for VL 7056
7215 16:29:59.568649 # ok 1323 # SKIP Get and set data for VL 7056
7216 16:29:59.568757 # ok 1324 Set VL 7072
7217 16:29:59.569067 # ok 1325 # SKIP Disabled ZA for VL 7072
7218 16:29:59.583117 # ok 1326 # SKIP Get and set data for VL 7072
7219 16:29:59.583574 # ok 1327 Set VL 7088
7220 16:29:59.583687 # ok 1328 # SKIP Disabled ZA for VL 7088
7221 16:29:59.583797 # ok 1329 # SKIP Get and set data for VL 7088
7222 16:29:59.583923 # ok 1330 Set VL 7104
7223 16:29:59.584042 # ok 1331 # SKIP Disabled ZA for VL 7104
7224 16:29:59.584164 # ok 1332 # SKIP Get and set data for VL 7104
7225 16:29:59.584277 # ok 1333 Set VL 7120
7226 16:29:59.584413 # ok 1334 # SKIP Disabled ZA for VL 7120
7227 16:29:59.584542 # ok 1335 # SKIP Get and set data for VL 7120
7228 16:29:59.584875 # ok 1336 Set VL 7136
7229 16:29:59.591233 # ok 1337 # SKIP Disabled ZA for VL 7136
7230 16:29:59.591878 # ok 1338 # SKIP Get and set data for VL 7136
7231 16:29:59.591998 # ok 1339 Set VL 7152
7232 16:29:59.592864 # ok 1340 # SKIP Disabled ZA for VL 7152
7233 16:29:59.607302 # ok 1341 # SKIP Get and set data for VL 7152
7234 16:29:59.607774 # ok 1342 Set VL 7168
7235 16:29:59.608516 # ok 1343 # SKIP Disabled ZA for VL 7168
7236 16:29:59.623385 # ok 1344 # SKIP Get and set data for VL 7168
7237 16:29:59.623802 # ok 1345 Set VL 7184
7238 16:29:59.624103 # ok 1346 # SKIP Disabled ZA for VL 7184
7239 16:29:59.624817 # ok 1347 # SKIP Get and set data for VL 7184
7240 16:29:59.639676 # ok 1348 Set VL 7200
7241 16:29:59.640126 # ok 1349 # SKIP Disabled ZA for VL 7200
7242 16:29:59.640437 # ok 1350 # SKIP Get and set data for VL 7200
7243 16:29:59.640747 # ok 1351 Set VL 7216
7244 16:29:59.651359 # ok 1352 # SKIP Disabled ZA for VL 7216
7245 16:29:59.652203 # ok 1353 # SKIP Get and set data for VL 7216
7246 16:29:59.652739 # ok 1354 Set VL 7232
7247 16:29:59.663416 # ok 1355 # SKIP Disabled ZA for VL 7232
7248 16:29:59.664084 # ok 1356 # SKIP Get and set data for VL 7232
7249 16:29:59.664382 # ok 1357 Set VL 7248
7250 16:29:59.664898 # ok 1358 # SKIP Disabled ZA for VL 7248
7251 16:29:59.679359 # ok 1359 # SKIP Get and set data for VL 7248
7252 16:29:59.679855 # ok 1360 Set VL 7264
7253 16:29:59.680386 # ok 1361 # SKIP Disabled ZA for VL 7264
7254 16:29:59.680522 # ok 1362 # SKIP Get and set data for VL 7264
7255 16:29:59.680860 # ok 1363 Set VL 7280
7256 16:29:59.680958 # ok 1364 # SKIP Disabled ZA for VL 7280
7257 16:29:59.690696 # ok 1365 # SKIP Get and set data for VL 7280
7258 16:29:59.690961 # ok 1366 Set VL 7296
7259 16:29:59.691282 # ok 1367 # SKIP Disabled ZA for VL 7296
7260 16:29:59.691389 # ok 1368 # SKIP Get and set data for VL 7296
7261 16:29:59.691889 # ok 1369 Set VL 7312
7262 16:29:59.691995 # ok 1370 # SKIP Disabled ZA for VL 7312
7263 16:29:59.692085 # ok 1371 # SKIP Get and set data for VL 7312
7264 16:29:59.692398 # ok 1372 Set VL 7328
7265 16:29:59.692504 # ok 1373 # SKIP Disabled ZA for VL 7328
7266 16:29:59.692594 # ok 1374 # SKIP Get and set data for VL 7328
7267 16:29:59.703491 # ok 1375 Set VL 7344
7268 16:29:59.703963 # ok 1376 # SKIP Disabled ZA for VL 7344
7269 16:29:59.704294 # ok 1377 # SKIP Get and set data for VL 7344
7270 16:29:59.704823 # ok 1378 Set VL 7360
7271 16:29:59.715520 # ok 1379 # SKIP Disabled ZA for VL 7360
7272 16:29:59.716228 # ok 1380 # SKIP Get and set data for VL 7360
7273 16:29:59.716810 # ok 1381 Set VL 7376
7274 16:29:59.731557 # ok 1382 # SKIP Disabled ZA for VL 7376
7275 16:29:59.743139 # ok 1383 # SKIP Get and set data for VL 7376
7276 16:29:59.743600 # ok 1384 Set VL 7392
7277 16:29:59.744555 # ok 1385 # SKIP Disabled ZA for VL 7392
7278 16:29:59.756705 # ok 1386 # SKIP Get and set data for VL 7392
7279 16:29:59.757183 # ok 1387 Set VL 7408
7280 16:29:59.771542 # ok 1388 # SKIP Disabled ZA for VL 7408
7281 16:29:59.772353 # ok 1389 # SKIP Get and set data for VL 7408
7282 16:29:59.772468 # ok 1390 Set VL 7424
7283 16:29:59.783148 # ok 1391 # SKIP Disabled ZA for VL 7424
7284 16:29:59.783998 # ok 1392 # SKIP Get and set data for VL 7424
7285 16:29:59.784588 # ok 1393 Set VL 7440
7286 16:29:59.799316 # ok 1394 # SKIP Disabled ZA for VL 7440
7287 16:29:59.799769 # ok 1395 # SKIP Get and set data for VL 7440
7288 16:29:59.799880 # ok 1396 Set VL 7456
7289 16:29:59.800401 # ok 1397 # SKIP Disabled ZA for VL 7456
7290 16:29:59.807291 # ok 1398 # SKIP Get and set data for VL 7456
7291 16:29:59.807721 # ok 1399 Set VL 7472
7292 16:29:59.808242 # ok 1400 # SKIP Disabled ZA for VL 7472
7293 16:29:59.808362 # ok 1401 # SKIP Get and set data for VL 7472
7294 16:29:59.808455 # ok 1402 Set VL 7488
7295 16:29:59.808753 # ok 1403 # SKIP Disabled ZA for VL 7488
7296 16:29:59.808879 # ok 1404 # SKIP Get and set data for VL 7488
7297 16:29:59.819348 # ok 1405 Set VL 7504
7298 16:29:59.820234 # ok 1406 # SKIP Disabled ZA for VL 7504
7299 16:29:59.830867 # ok 1407 # SKIP Get and set data for VL 7504
7300 16:29:59.831513 # ok 1408 Set VL 7520
7301 16:29:59.831834 # ok 1409 # SKIP Disabled ZA for VL 7520
7302 16:29:59.832761 # ok 1410 # SKIP Get and set data for VL 7520
7303 16:29:59.840707 # ok 1411 Set VL 7536
7304 16:29:59.847103 # ok 1412 # SKIP Disabled ZA for VL 7536
7305 16:29:59.847534 # ok 1413 # SKIP Get and set data for VL 7536
7306 16:29:59.847642 # ok 1414 Set VL 7552
7307 16:29:59.847731 # ok 1415 # SKIP Disabled ZA for VL 7552
7308 16:29:59.847832 # ok 1416 # SKIP Get and set data for VL 7552
7309 16:29:59.847920 # ok 1417 Set VL 7568
7310 16:29:59.848217 # ok 1418 # SKIP Disabled ZA for VL 7568
7311 16:29:59.848536 # ok 1419 # SKIP Get and set data for VL 7568
7312 16:29:59.848656 # ok 1420 Set VL 7584
7313 16:29:59.848947 # ok 1421 # SKIP Disabled ZA for VL 7584
7314 16:29:59.858912 # ok 1422 # SKIP Get and set data for VL 7584
7315 16:29:59.859365 # ok 1423 Set VL 7600
7316 16:29:59.859683 # ok 1424 # SKIP Disabled ZA for VL 7600
7317 16:29:59.860196 # ok 1425 # SKIP Get and set data for VL 7600
7318 16:29:59.860525 # ok 1426 Set VL 7616
7319 16:29:59.860817 # ok 1427 # SKIP Disabled ZA for VL 7616
7320 16:29:59.860921 # ok 1428 # SKIP Get and set data for VL 7616
7321 16:29:59.863207 # ok 1429 Set VL 7632
7322 16:29:59.863540 # ok 1430 # SKIP Disabled ZA for VL 7632
7323 16:29:59.863660 # ok 1431 # SKIP Get and set data for VL 7632
7324 16:29:59.864005 # ok 1432 Set VL 7648
7325 16:29:59.864324 # ok 1433 # SKIP Disabled ZA for VL 7648
7326 16:29:59.864735 # ok 1434 # SKIP Get and set data for VL 7648
7327 16:29:59.864841 # ok 1435 Set VL 7664
7328 16:29:59.866632 # ok 1436 # SKIP Disabled ZA for VL 7664
7329 16:29:59.866994 # ok 1437 # SKIP Get and set data for VL 7664
7330 16:29:59.867400 # ok 1438 Set VL 7680
7331 16:29:59.867511 # ok 1439 # SKIP Disabled ZA for VL 7680
7332 16:29:59.867602 # ok 1440 # SKIP Get and set data for VL 7680
7333 16:29:59.867868 # ok 1441 Set VL 7696
7334 16:29:59.868184 # ok 1442 # SKIP Disabled ZA for VL 7696
7335 16:29:59.868515 # ok 1443 # SKIP Get and set data for VL 7696
7336 16:29:59.868822 # ok 1444 Set VL 7712
7337 16:29:59.879120 # ok 1445 # SKIP Disabled ZA for VL 7712
7338 16:29:59.879574 # ok 1446 # SKIP Get and set data for VL 7712
7339 16:29:59.879699 # ok 1447 Set VL 7728
7340 16:29:59.880209 # ok 1448 # SKIP Disabled ZA for VL 7728
7341 16:29:59.882306 # ok 1449 # SKIP Get and set data for VL 7728
7342 16:29:59.882809 # ok 1450 Set VL 7744
7343 16:29:59.883152 # ok 1451 # SKIP Disabled ZA for VL 7744
7344 16:29:59.884757 # ok 1452 # SKIP Get and set data for VL 7744
7345 16:29:59.908788 # ok 1453 Set VL 7760
7346 16:29:59.911260 # ok 1454 # SKIP Disabled ZA for VL 7760
7347 16:29:59.912346 # ok 1455 # SKIP Get and set data for VL 7760
7348 16:29:59.912662 # ok 1456 Set VL 7776
7349 16:29:59.914048 # ok 1457 # SKIP Disabled ZA for VL 7776
7350 16:29:59.914415 # ok 1458 # SKIP Get and set data for VL 7776
7351 16:29:59.914524 # ok 1459 Set VL 7792
7352 16:29:59.914982 # ok 1460 # SKIP Disabled ZA for VL 7792
7353 16:29:59.915277 # ok 1461 # SKIP Get and set data for VL 7792
7354 16:29:59.915394 # ok 1462 Set VL 7808
7355 16:29:59.915756 # ok 1463 # SKIP Disabled ZA for VL 7808
7356 16:29:59.915847 # ok 1464 # SKIP Get and set data for VL 7808
7357 16:29:59.915945 # ok 1465 Set VL 7824
7358 16:29:59.917184 # ok 1466 # SKIP Disabled ZA for VL 7824
7359 16:29:59.917855 # ok 1467 # SKIP Get and set data for VL 7824
7360 16:29:59.918362 # ok 1468 Set VL 7840
7361 16:29:59.919101 # ok 1469 # SKIP Disabled ZA for VL 7840
7362 16:29:59.919391 # ok 1470 # SKIP Get and set data for VL 7840
7363 16:29:59.919491 # ok 1471 Set VL 7856
7364 16:29:59.919788 # ok 1472 # SKIP Disabled ZA for VL 7856
7365 16:29:59.919889 # ok 1473 # SKIP Get and set data for VL 7856
7366 16:29:59.919985 # ok 1474 Set VL 7872
7367 16:29:59.920064 # ok 1475 # SKIP Disabled ZA for VL 7872
7368 16:29:59.920356 # ok 1476 # SKIP Get and set data for VL 7872
7369 16:29:59.920725 # ok 1477 Set VL 7888
7370 16:29:59.921257 # ok 1478 # SKIP Disabled ZA for VL 7888
7371 16:29:59.921375 # ok 1479 # SKIP Get and set data for VL 7888
7372 16:29:59.921480 # ok 1480 Set VL 7904
7373 16:29:59.921811 # ok 1481 # SKIP Disabled ZA for VL 7904
7374 16:29:59.922148 # ok 1482 # SKIP Get and set data for VL 7904
7375 16:29:59.922495 # ok 1483 Set VL 7920
7376 16:29:59.922598 # ok 1484 # SKIP Disabled ZA for VL 7920
7377 16:29:59.922702 # ok 1485 # SKIP Get and set data for VL 7920
7378 16:29:59.922791 # ok 1486 Set VL 7936
7379 16:29:59.923112 # ok 1487 # SKIP Disabled ZA for VL 7936
7380 16:29:59.923446 # ok 1488 # SKIP Get and set data for VL 7936
7381 16:29:59.923551 # ok 1489 Set VL 7952
7382 16:29:59.923637 # ok 1490 # SKIP Disabled ZA for VL 7952
7383 16:29:59.923722 # ok 1491 # SKIP Get and set data for VL 7952
7384 16:29:59.923823 # ok 1492 Set VL 7968
7385 16:29:59.923910 # ok 1493 # SKIP Disabled ZA for VL 7968
7386 16:29:59.924009 # ok 1494 # SKIP Get and set data for VL 7968
7387 16:29:59.924312 # ok 1495 Set VL 7984
7388 16:29:59.924423 # ok 1496 # SKIP Disabled ZA for VL 7984
7389 16:29:59.924524 # ok 1497 # SKIP Get and set data for VL 7984
7390 16:29:59.924613 # ok 1498 Set VL 8000
7391 16:29:59.924713 # ok 1499 # SKIP Disabled ZA for VL 8000
7392 16:29:59.925021 # ok 1500 # SKIP Get and set data for VL 8000
7393 16:29:59.925144 # ok 1501 Set VL 8016
7394 16:29:59.925247 # ok 1502 # SKIP Disabled ZA for VL 8016
7395 16:29:59.927038 # ok 1503 # SKIP Get and set data for VL 8016
7396 16:29:59.927328 # ok 1504 Set VL 8032
7397 16:29:59.927437 # ok 1505 # SKIP Disabled ZA for VL 8032
7398 16:29:59.927541 # ok 1506 # SKIP Get and set data for VL 8032
7399 16:29:59.927630 # ok 1507 Set VL 8048
7400 16:29:59.927952 # ok 1508 # SKIP Disabled ZA for VL 8048
7401 16:29:59.928075 # ok 1509 # SKIP Get and set data for VL 8048
7402 16:29:59.928178 # ok 1510 Set VL 8064
7403 16:29:59.928500 # ok 1511 # SKIP Disabled ZA for VL 8064
7404 16:29:59.928838 # ok 1512 # SKIP Get and set data for VL 8064
7405 16:29:59.928942 # ok 1513 Set VL 8080
7406 16:29:59.935867 # ok 1514 # SKIP Disabled ZA for VL 8080
7407 16:29:59.936270 # ok 1515 # SKIP Get and set data for VL 8080
7408 16:29:59.936632 # ok 1516 Set VL 8096
7409 16:29:59.936747 # ok 1517 # SKIP Disabled ZA for VL 8096
7410 16:29:59.936849 # ok 1518 # SKIP Get and set data for VL 8096
7411 16:29:59.937996 # ok 1519 Set VL 8112
7412 16:29:59.938425 # ok 1520 # SKIP Disabled ZA for VL 8112
7413 16:29:59.938534 # ok 1521 # SKIP Get and set data for VL 8112
7414 16:29:59.938631 # ok 1522 Set VL 8128
7415 16:29:59.938730 # ok 1523 # SKIP Disabled ZA for VL 8128
7416 16:29:59.938837 # ok 1524 # SKIP Get and set data for VL 8128
7417 16:29:59.938956 # ok 1525 Set VL 8144
7418 16:29:59.939071 # ok 1526 # SKIP Disabled ZA for VL 8144
7419 16:29:59.939182 # ok 1527 # SKIP Get and set data for VL 8144
7420 16:29:59.939270 # ok 1528 Set VL 8160
7421 16:29:59.939354 # ok 1529 # SKIP Disabled ZA for VL 8160
7422 16:29:59.939452 # ok 1530 # SKIP Get and set data for VL 8160
7423 16:29:59.939537 # ok 1531 Set VL 8176
7424 16:29:59.939633 # ok 1532 # SKIP Disabled ZA for VL 8176
7425 16:29:59.939732 # ok 1533 # SKIP Get and set data for VL 8176
7426 16:29:59.939816 # ok 1534 Set VL 8192
7427 16:29:59.940149 # ok 1535 # SKIP Disabled ZA for VL 8192
7428 16:29:59.940245 # ok 1536 # SKIP Get and set data for VL 8192
7429 16:29:59.940544 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7430 16:29:59.940648 ok 34 selftests: arm64: za-ptrace
7431 16:29:59.940737 # selftests: arm64: check_buffer_fill
7432 16:30:01.108631 # 1..20
7433 16:30:01.109095 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7434 16:30:01.115958 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7435 16:30:01.116532 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7436 16:30:01.116641 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7437 16:30:01.117134 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7438 16:30:01.139173 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7439 16:30:01.139747 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7440 16:30:01.140057 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7441 16:30:01.140195 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7442 16:30:01.140706 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 16:30:01.140827 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7444 16:30:01.140959 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7445 16:30:01.147194 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7446 16:30:01.147740 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7447 16:30:01.148056 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7448 16:30:01.148377 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7449 16:30:01.148687 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7450 16:30:01.150108 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7451 16:30:01.150630 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7452 16:30:01.150963 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7453 16:30:01.151070 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7454 16:30:01.205200 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7455 16:30:01.651156 # selftests: arm64: check_child_memory
7456 16:30:03.004256 # 1..12
7457 16:30:03.005002 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7458 16:30:03.005115 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7459 16:30:03.005403 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7460 16:30:03.005517 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7461 16:30:03.011299 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7462 16:30:03.024293 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7463 16:30:03.028742 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7464 16:30:03.040073 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7465 16:30:03.045742 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7466 16:30:03.045856 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7467 16:30:03.055623 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7468 16:30:03.076292 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7469 16:30:03.081222 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7470 16:30:03.104320 not ok 36 selftests: arm64: check_child_memory # exit=1
7471 16:30:03.561349 # selftests: arm64: check_gcr_el1_cswitch
7472 16:30:49.014078 <47>[ 111.618068] systemd-journald[105]: Sent WATCHDOG=1 notification.
7473 16:30:51.446747 <47>[ 114.052165] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3328 of 4437 items, 2555904 file size, 768 bytes per hash table item), suggesting rotation.
7474 16:30:51.448625 <47>[ 114.054616] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7475 16:30:51.448950 <47>[ 114.055134] systemd-journald[105]: Rotating...
7476 16:30:51.543890 <47>[ 114.148312] systemd-journald[105]: Reserving 333 entries in field hash table.
7477 16:30:51.713186 <47>[ 114.319171] systemd-journald[105]: Reserving 4437 entries in data hash table.
7478 16:30:51.764436 <47>[ 114.370438] systemd-journald[105]: Vacuuming...
7479 16:30:51.790686 <47>[ 114.395753] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7480 16:30:52.717893 # 1..1
7481 16:30:52.718139 # 1..1
7482 16:30:52.718249 # 1..1
7483 16:30:52.718341 # 1..1
7484 16:30:52.718646 # 1..1
7485 16:30:52.718767 # 1..1
7486 16:30:52.732881 # 1..1
7487 16:30:52.733114 # 1..1
7488 16:30:52.733219 # 1..1
7489 16:30:52.733595 # 1..1
7490 16:30:52.733707 # 1..1
7491 16:30:52.733798 # 1..1
7492 16:30:52.733880 # 1..1
7493 16:30:52.733961 # 1..1
7494 16:30:52.734041 # 1..1
7495 16:30:52.734120 # 1..1
7496 16:30:52.734199 # 1..1
7497 16:30:52.734279 # 1..1
7498 16:30:52.734358 # 1..1
7499 16:30:52.734423 # 1..1
7500 16:30:52.734505 # 1..1
7501 16:30:52.734589 # 1..1
7502 16:30:52.734670 # 1..1
7503 16:30:52.734760 # 1..1
7504 16:30:52.734845 # 1..1
7505 16:30:52.734924 # 1..1
7506 16:30:52.735008 # 1..1
7507 16:30:52.735089 # 1..1
7508 16:30:52.735185 # 1..1
7509 16:30:52.735266 # 1..1
7510 16:30:52.736310 # 1..1
7511 16:30:52.736418 # 1..1
7512 16:30:52.736501 # 1..1
7513 16:30:52.736581 # 1..1
7514 16:30:52.736661 # 1..1
7515 16:30:52.736740 # 1..1
7516 16:30:52.736815 # 1..1
7517 16:30:52.736882 # 1..1
7518 16:30:52.736961 # 1..1
7519 16:30:52.737039 # 1..1
7520 16:30:52.737118 # 1..1
7521 16:30:52.737197 # 1..1
7522 16:30:52.737274 # 1..1
7523 16:30:52.737352 # 1..1
7524 16:30:52.737431 # 1..1
7525 16:30:52.737509 # 1..1
7526 16:30:52.737586 # 1..1
7527 16:30:52.737670 # 1..1
7528 16:30:52.737751 # 1..1
7529 16:30:52.737830 # 1..1
7530 16:30:52.737909 # 1..1
7531 16:30:52.737987 # 1..1
7532 16:30:52.738065 # 1..1
7533 16:30:52.738143 # 1..1
7534 16:30:52.738222 # 1..1
7535 16:30:52.738300 # 1..1
7536 16:30:52.738378 # 1..1
7537 16:30:52.738456 # 1..1
7538 16:30:52.738534 # 1..1
7539 16:30:52.738612 # 1..1
7540 16:30:52.738690 # 1..1
7541 16:30:52.738768 # 1..1
7542 16:30:52.738846 # 1..1
7543 16:30:52.738924 # 1..1
7544 16:30:52.739003 # 1..1
7545 16:30:52.739081 # 1..1
7546 16:30:52.739159 # 1..1
7547 16:30:52.739238 # 1..1
7548 16:30:52.739316 # 1..1
7549 16:30:52.739393 # 1..1
7550 16:30:52.739471 # 1..1
7551 16:30:52.739549 # 1..1
7552 16:30:52.739627 # 1..1
7553 16:30:52.739709 # 1..1
7554 16:30:52.739791 # 1..1
7555 16:30:52.739869 # 1..1
7556 16:30:52.739947 # 1..1
7557 16:30:52.740026 # 1..1
7558 16:30:52.740104 # 1..1
7559 16:30:52.740183 # 1..1
7560 16:30:52.740262 # 1..1
7561 16:30:52.740340 # 1..1
7562 16:30:52.740419 # 1..1
7563 16:30:52.740498 # 1..1
7564 16:30:52.740577 # 1..1
7565 16:30:52.740655 # 1..1
7566 16:30:52.740738 # 1..1
7567 16:30:52.740816 # 1..1
7568 16:30:52.740894 # 1..1
7569 16:30:52.740972 # 1..1
7570 16:30:52.741050 # 1..1
7571 16:30:52.785041 # 1..1
7572 16:30:52.785615 # 1..1
7573 16:30:52.785731 # 1..1
7574 16:30:52.785820 # 1..1
7575 16:30:52.785900 # 1..1
7576 16:30:52.785977 # 1..1
7577 16:30:52.786053 # 1..1
7578 16:30:52.786129 # 1..1
7579 16:30:52.786206 # 1..1
7580 16:30:52.786283 # 1..1
7581 16:30:52.786923 # 1..1
7582 16:30:52.787027 # 1..1
7583 16:30:52.808725 # 1..1
7584 16:30:52.809194 # 1..1
7585 16:30:52.809513 # 1..1
7586 16:30:52.809838 # 1..1
7587 16:30:52.809962 # 1..1
7588 16:30:52.810064 # 1..1
7589 16:30:52.810364 # 1..1
7590 16:30:52.855915 # 1..1
7591 16:30:52.856158 # 1..1
7592 16:30:52.856247 # 1..1
7593 16:30:52.857772 # 1..1
7594 16:30:52.857994 # 1..1
7595 16:30:52.858076 # 1..1
7596 16:30:52.858150 # 1..1
7597 16:30:52.858464 # 1..1
7598 16:30:52.858558 # 1..1
7599 16:30:52.858634 # 1..1
7600 16:30:52.858708 # 1..1
7601 16:30:52.859101 # 1..1
7602 16:30:52.859203 # 1..1
7603 16:30:52.859285 # 1..1
7604 16:30:52.859363 # 1..1
7605 16:30:52.859447 # 1..1
7606 16:30:52.859777 # 1..1
7607 16:30:52.859885 # 1..1
7608 16:30:52.859976 # 1..1
7609 16:30:52.860065 # 1..1
7610 16:30:52.860154 # 1..1
7611 16:30:52.860262 # 1..1
7612 16:30:52.860384 # 1..1
7613 16:30:52.860495 # 1..1
7614 16:30:52.860609 # 1..1
7615 16:30:52.860721 # 1..1
7616 16:30:52.860831 # 1..1
7617 16:30:52.860931 # 1..1
7618 16:30:52.861021 # 1..1
7619 16:30:52.861111 # 1..1
7620 16:30:52.861200 # 1..1
7621 16:30:52.861306 # 1..1
7622 16:30:52.861400 # 1..1
7623 16:30:52.861488 # 1..1
7624 16:30:52.861594 # 1..1
7625 16:30:52.861711 # 1..1
7626 16:30:52.861834 # 1..1
7627 16:30:52.861917 # 1..1
7628 16:30:52.861991 # 1..1
7629 16:30:52.862063 # 1..1
7630 16:30:52.862135 # 1..1
7631 16:30:52.862205 # 1..1
7632 16:30:52.862275 # 1..1
7633 16:30:52.862345 # 1..1
7634 16:30:52.862414 # 1..1
7635 16:30:52.862485 # 1..1
7636 16:30:52.862555 # 1..1
7637 16:30:52.862626 # 1..1
7638 16:30:52.862696 # 1..1
7639 16:30:52.862768 # 1..1
7640 16:30:52.862837 # 1..1
7641 16:30:52.862907 # 1..1
7642 16:30:52.862985 # 1..1
7643 16:30:52.863058 # 1..1
7644 16:30:52.863128 # 1..1
7645 16:30:52.863198 # 1..1
7646 16:30:52.863270 # 1..1
7647 16:30:52.863342 # 1..1
7648 16:30:52.863415 # 1..1
7649 16:30:52.863487 # 1..1
7650 16:30:52.863558 # 1..1
7651 16:30:52.863651 # 1..1
7652 16:30:52.892755 # 1..1
7653 16:30:52.893003 # 1..1
7654 16:30:52.893116 # 1..1
7655 16:30:52.893249 # 1..1
7656 16:30:52.893354 # 1..1
7657 16:30:52.893458 # 1..1
7658 16:30:52.893559 # 1..1
7659 16:30:52.893671 # 1..1
7660 16:30:52.893764 # 1..1
7661 16:30:52.893850 # 1..1
7662 16:30:52.893943 # 1..1
7663 16:30:52.894023 # 1..1
7664 16:30:52.894096 # 1..1
7665 16:30:52.894167 # 1..1
7666 16:30:52.894238 # 1..1
7667 16:30:52.894307 # 1..1
7668 16:30:52.894378 # 1..1
7669 16:30:52.894449 # 1..1
7670 16:30:52.894519 # 1..1
7671 16:30:52.894590 # 1..1
7672 16:30:52.894660 # 1..1
7673 16:30:52.894731 # 1..1
7674 16:30:52.894801 # 1..1
7675 16:30:52.917628 # 1..1
7676 16:30:52.917892 # 1..1
7677 16:30:52.918008 # 1..1
7678 16:30:52.918096 # 1..1
7679 16:30:52.947837 # 1..1
7680 16:30:52.948334 # 1..1
7681 16:30:52.948443 # 1..1
7682 16:30:52.948548 # 1..1
7683 16:30:52.948670 # 1..1
7684 16:30:52.948805 # 1..1
7685 16:30:52.948920 # 1..1
7686 16:30:52.949025 # 1..1
7687 16:30:52.949134 # 1..1
7688 16:30:52.949243 # 1..1
7689 16:30:52.949362 # 1..1
7690 16:30:52.949459 # 1..1
7691 16:30:52.949567 # 1..1
7692 16:30:52.950001 # 1..1
7693 16:30:52.950092 # 1..1
7694 16:30:52.950167 # 1..1
7695 16:30:52.950239 # 1..1
7696 16:30:52.950310 # 1..1
7697 16:30:52.950380 # 1..1
7698 16:30:52.950451 # 1..1
7699 16:30:52.950540 # 1..1
7700 16:30:52.950615 # 1..1
7701 16:30:52.950689 # 1..1
7702 16:30:52.950760 # 1..1
7703 16:30:52.950832 # 1..1
7704 16:30:52.950904 # 1..1
7705 16:30:52.972610 # 1..1
7706 16:30:52.972846 # 1..1
7707 16:30:52.972959 # 1..1
7708 16:30:52.973049 # 1..1
7709 16:30:52.973137 # 1..1
7710 16:30:52.973226 # 1..1
7711 16:30:52.973314 # 1..1
7712 16:30:52.973402 # 1..1
7713 16:30:52.973488 # 1..1
7714 16:30:52.973574 # 1..1
7715 16:30:52.973666 # 1..1
7716 16:30:52.973761 # 1..1
7717 16:30:52.973837 # 1..1
7718 16:30:52.973910 # 1..1
7719 16:30:52.973982 # 1..1
7720 16:30:52.974054 # 1..1
7721 16:30:52.974126 # 1..1
7722 16:30:52.974197 # 1..1
7723 16:30:52.974268 # 1..1
7724 16:30:52.974338 # 1..1
7725 16:30:52.974409 # 1..1
7726 16:30:52.974480 # 1..1
7727 16:30:52.974551 # 1..1
7728 16:30:52.974623 # 1..1
7729 16:30:52.974694 # 1..1
7730 16:30:52.974766 # 1..1
7731 16:30:53.173067 #
7732 16:30:53.185346 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
7733 16:30:55.892214 # selftests: arm64: check_ksm_options
7734 16:30:58.006233 # 1..4
7735 16:30:58.006471 # # Invalid MTE synchronous exception caught!
7736 16:30:58.204091 not ok 38 selftests: arm64: check_ksm_options # exit=1
7737 16:30:59.637134 # selftests: arm64: check_mmap_options
7738 16:31:01.362006 # 1..22
7739 16:31:01.362459 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
7740 16:31:01.369477 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
7741 16:31:01.370106 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
7742 16:31:01.370638 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
7743 16:31:01.371249 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
7744 16:31:01.385578 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7745 16:31:01.397911 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
7746 16:31:01.400080 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7747 16:31:01.400428 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
7748 16:31:01.400967 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
7749 16:31:01.401471 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
7750 16:31:01.401784 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
7751 16:31:01.403078 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
7752 16:31:01.403571 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7753 16:31:01.404037 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
7754 16:31:01.404532 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7755 16:31:01.404657 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
7756 16:31:01.404975 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
7757 16:31:01.405301 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
7758 16:31:01.405612 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
7759 16:31:01.405748 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
7760 16:31:01.407513 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
7761 16:31:01.407810 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
7762 16:31:01.449012 not ok 39 selftests: arm64: check_mmap_options # exit=1
7763 16:31:01.880746 # selftests: arm64: check_prctl
7764 16:31:02.296544 # TAP version 13
7765 16:31:02.296698 # 1..5
7766 16:31:02.296796 # ok 1 check_basic_read
7767 16:31:02.296902 # ok 2 NONE
7768 16:31:02.297014 # ok 3 SYNC
7769 16:31:02.297103 # ok 4 ASYNC
7770 16:31:02.297188 # ok 5 SYNC+ASYNC
7771 16:31:02.297272 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
7772 16:31:02.356798 ok 40 selftests: arm64: check_prctl
7773 16:31:02.792772 # selftests: arm64: check_tags_inclusion
7774 16:31:03.223694 # 1..4
7775 16:31:03.233500 # # Unexpected fault recorded for 0xc00ffff90d75000-0xc00ffff90d75050 in mode 1
7776 16:31:03.237751 # not ok 1 Check an included tag value with sync mode
7777 16:31:03.252959 # # Unexpected fault recorded for 0x700ffff90d75000-0x700ffff90d75050 in mode 1
7778 16:31:03.253481 # not ok 2 Check different included tags value with sync mode
7779 16:31:03.253796 # ok 3 Check none included tags value with sync mode
7780 16:31:03.253903 # # Unexpected fault recorded for 0x700ffff90d75000-0x700ffff90d75050 in mode 1
7781 16:31:03.254015 # not ok 4 Check all included tags value with sync mode
7782 16:31:03.259825 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
7783 16:31:03.336170 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
7784 16:31:03.772759 # selftests: arm64: check_user_mem
7785 16:31:17.058121 # 1..64
7786 16:31:17.060432 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7787 16:31:17.061000 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7788 16:31:17.061261 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7789 16:31:17.061395 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7790 16:31:17.061751 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7791 16:31:17.063809 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7792 16:31:17.064122 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7793 16:31:17.064426 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7794 16:31:17.064544 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7795 16:31:17.064860 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7796 16:31:17.064985 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7797 16:31:17.066430 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7798 16:31:17.066561 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7799 16:31:17.066648 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7800 16:31:17.066747 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7801 16:31:17.074924 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7802 16:31:17.075483 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7803 16:31:17.075586 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7804 16:31:17.075670 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7805 16:31:17.075763 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7806 16:31:17.075857 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7807 16:31:17.076155 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7808 16:31:17.076469 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7809 16:31:17.076569 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7810 16:31:17.076665 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7811 16:31:17.077112 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7812 16:31:17.077243 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7813 16:31:17.077834 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7814 16:31:17.077938 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7815 16:31:17.086601 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7816 16:31:17.087052 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7817 16:31:17.087169 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7818 16:31:17.087300 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7819 16:31:17.087626 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7820 16:31:17.087763 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7821 16:31:17.088108 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7822 16:31:17.088235 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7823 16:31:17.088562 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7824 16:31:17.088685 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7825 16:31:17.088801 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7826 16:31:17.089148 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7827 16:31:17.089469 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7828 16:31:17.089586 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7829 16:31:17.089706 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7830 16:31:17.094860 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7831 16:31:17.095389 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7832 16:31:17.095525 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7833 16:31:17.095841 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7834 16:31:17.095964 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7835 16:31:17.096487 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7836 16:31:17.096817 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7837 16:31:19.809086 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7838 16:31:19.809340 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7839 16:31:19.809668 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7840 16:31:19.809796 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7841 16:31:19.817027 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7842 16:31:19.817641 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7843 16:31:19.817761 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7844 16:31:19.817857 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7845 16:31:19.817944 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7846 16:31:19.818038 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7847 16:31:19.833164 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7848 16:31:19.833816 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7849 16:31:19.833938 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7850 16:31:19.835222 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
7851 16:31:19.876946 ok 42 selftests: arm64: check_user_mem
7852 16:31:20.328837 # selftests: arm64: btitest
7853 16:31:20.781061 # TAP version 13
7854 16:31:20.781285 # 1..18
7855 16:31:20.781610 # # HWCAP_PACA present
7856 16:31:20.781719 # # HWCAP2_BTI present
7857 16:31:20.782054 # # Test binary built for BTI
7858 16:31:20.789740 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
7859 16:31:20.790180 # ok 1 nohint_func/call_using_br_x0
7860 16:31:20.791533 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
7861 16:31:20.791859 # ok 2 nohint_func/call_using_br_x16
7862 16:31:20.791994 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
7863 16:31:20.792355 # ok 3 nohint_func/call_using_blr
7864 16:31:20.792469 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
7865 16:31:20.792579 # ok 4 bti_none_func/call_using_br_x0
7866 16:31:20.792686 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
7867 16:31:20.792996 # ok 5 bti_none_func/call_using_br_x16
7868 16:31:20.793394 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
7869 16:31:20.793747 # ok 6 bti_none_func/call_using_blr
7870 16:31:20.793890 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
7871 16:31:20.793989 # ok 7 bti_c_func/call_using_br_x0
7872 16:31:20.794070 # ok 8 bti_c_func/call_using_br_x16
7873 16:31:20.794150 # ok 9 bti_c_func/call_using_blr
7874 16:31:20.803965 # ok 10 bti_j_func/call_using_br_x0
7875 16:31:20.804420 # ok 11 bti_j_func/call_using_br_x16
7876 16:31:20.804545 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
7877 16:31:20.804645 # ok 12 bti_j_func/call_using_blr
7878 16:31:20.804754 # ok 13 bti_jc_func/call_using_br_x0
7879 16:31:20.804864 # ok 14 bti_jc_func/call_using_br_x16
7880 16:31:20.804973 # ok 15 bti_jc_func/call_using_blr
7881 16:31:20.805269 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
7882 16:31:20.805397 # ok 16 paciasp_func/call_using_br_x0
7883 16:31:20.805521 # ok 17 paciasp_func/call_using_br_x16
7884 16:31:20.805851 # ok 18 paciasp_func/call_using_blr
7885 16:31:20.805965 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
7886 16:31:20.857083 ok 43 selftests: arm64: btitest
7887 16:31:21.316646 # selftests: arm64: nobtitest
7888 16:31:21.660472 # TAP version 13
7889 16:31:21.660913 # 1..18
7890 16:31:21.661017 # # HWCAP_PACA present
7891 16:31:21.661102 # # HWCAP2_BTI present
7892 16:31:21.661182 # # Test binary not built for BTI
7893 16:31:21.661259 # ok 1 nohint_func/call_using_br_x0
7894 16:31:21.661338 # ok 2 nohint_func/call_using_br_x16
7895 16:31:21.661431 # ok 3 nohint_func/call_using_blr
7896 16:31:21.661512 # ok 4 bti_none_func/call_using_br_x0
7897 16:31:21.661591 # ok 5 bti_none_func/call_using_br_x16
7898 16:31:21.661678 # ok 6 bti_none_func/call_using_blr
7899 16:31:21.661771 # ok 7 bti_c_func/call_using_br_x0
7900 16:31:21.661856 # ok 8 bti_c_func/call_using_br_x16
7901 16:31:21.661934 # ok 9 bti_c_func/call_using_blr
7902 16:31:21.662024 # ok 10 bti_j_func/call_using_br_x0
7903 16:31:21.667733 # ok 11 bti_j_func/call_using_br_x16
7904 16:31:21.668136 # ok 12 bti_j_func/call_using_blr
7905 16:31:21.668237 # ok 13 bti_jc_func/call_using_br_x0
7906 16:31:21.668321 # ok 14 bti_jc_func/call_using_br_x16
7907 16:31:21.668417 # ok 15 bti_jc_func/call_using_blr
7908 16:31:21.668497 # ok 16 paciasp_func/call_using_br_x0
7909 16:31:21.668784 # ok 17 paciasp_func/call_using_br_x16
7910 16:31:21.668885 # ok 18 paciasp_func/call_using_blr
7911 16:31:21.668965 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
7912 16:31:21.724936 ok 44 selftests: arm64: nobtitest
7913 16:31:22.128599 # selftests: arm64: hwcap
7914 16:31:22.577775 # TAP version 13
7915 16:31:22.578011 # 1..28
7916 16:31:22.578321 # # RNG present
7917 16:31:22.578443 # ok 1 cpuinfo_match_RNG
7918 16:31:22.578555 # ok 2 sigill_RNG
7919 16:31:22.578664 # # SME present
7920 16:31:22.578775 # ok 3 cpuinfo_match_SME
7921 16:31:22.578885 # ok 4 sigill_SME
7922 16:31:22.579014 # # SVE present
7923 16:31:22.579120 # ok 5 cpuinfo_match_SVE
7924 16:31:22.583740 # ok 6 sigill_SVE
7925 16:31:22.584413 # # SVE 2 present
7926 16:31:22.584520 # ok 7 cpuinfo_match_SVE 2
7927 16:31:22.584605 # ok 8 sigill_SVE 2
7928 16:31:22.584685 # # SVE AES present
7929 16:31:22.584763 # ok 9 cpuinfo_match_SVE AES
7930 16:31:22.584841 # ok 10 sigill_SVE AES
7931 16:31:22.584919 # # SVE2 PMULL present
7932 16:31:22.584997 # ok 11 cpuinfo_match_SVE2 PMULL
7933 16:31:22.585075 # ok 12 sigill_SVE2 PMULL
7934 16:31:22.585152 # # SVE2 BITPERM present
7935 16:31:22.585521 # ok 13 cpuinfo_match_SVE2 BITPERM
7936 16:31:22.585622 # ok 14 sigill_SVE2 BITPERM
7937 16:31:22.585711 # # SVE2 SHA3 present
7938 16:31:22.585789 # ok 15 cpuinfo_match_SVE2 SHA3
7939 16:31:22.585865 # ok 16 sigill_SVE2 SHA3
7940 16:31:22.585942 # # SVE2 SM4 present
7941 16:31:22.586018 # ok 17 cpuinfo_match_SVE2 SM4
7942 16:31:22.586094 # ok 18 sigill_SVE2 SM4
7943 16:31:22.586170 # # SVE2 I8MM present
7944 16:31:22.586446 # ok 19 cpuinfo_match_SVE2 I8MM
7945 16:31:22.586547 # ok 20 sigill_SVE2 I8MM
7946 16:31:22.586629 # # SVE2 F32MM present
7947 16:31:22.593639 # ok 21 cpuinfo_match_SVE2 F32MM
7948 16:31:22.594060 # ok 22 sigill_SVE2 F32MM
7949 16:31:22.594166 # # SVE2 F64MM present
7950 16:31:22.603225 # ok 23 cpuinfo_match_SVE2 F64MM
7951 16:31:22.603660 # ok 24 sigill_SVE2 F64MM
7952 16:31:22.603764 # # SVE2 BF16 present
7953 16:31:22.604243 # ok 25 cpuinfo_match_SVE2 BF16
7954 16:31:22.604361 # ok 26 sigill_SVE2 BF16
7955 16:31:22.604647 # ok 27 cpuinfo_match_SVE2 EBF16
7956 16:31:22.604760 # ok 28 # SKIP sigill_SVE2 EBF16
7957 16:31:22.605240 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
7958 16:31:22.639754 ok 45 selftests: arm64: hwcap
7959 16:31:22.916954 # selftests: arm64: ptrace
7960 16:31:23.195727 # TAP version 13
7961 16:31:23.195960 # 1..7
7962 16:31:23.196262 # # Parent is 2774, child is 2775
7963 16:31:23.196365 # ok 1 read_tpidr_one
7964 16:31:23.196451 # ok 2 write_tpidr_one
7965 16:31:23.196529 # ok 3 verify_tpidr_one
7966 16:31:23.196622 # ok 4 count_tpidrs
7967 16:31:23.196703 # ok 5 tpidr2_write
7968 16:31:23.196780 # ok 6 tpidr2_read
7969 16:31:23.196857 # ok 7 write_tpidr_only
7970 16:31:23.196947 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
7971 16:31:23.241192 ok 46 selftests: arm64: ptrace
7972 16:31:23.457199 # selftests: arm64: syscall-abi
7973 16:31:27.321209 # TAP version 13
7974 16:31:27.321656 # 1..514
7975 16:31:27.321774 # # SME with FA64
7976 16:31:27.321894 # ok 1 getpid() FPSIMD
7977 16:31:27.322003 # ok 2 getpid() SVE VL 256
7978 16:31:27.322112 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
7979 16:31:27.322240 # ok 4 getpid() SVE VL 256/SME VL 256 SM
7980 16:31:27.322726 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
7981 16:31:27.323028 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
7982 16:31:27.323136 # ok 7 getpid() SVE VL 256/SME VL 128 SM
7983 16:31:27.323258 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
7984 16:31:27.323366 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
7985 16:31:27.323658 # ok 10 getpid() SVE VL 256/SME VL 64 SM
7986 16:31:27.323757 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
7987 16:31:27.324046 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
7988 16:31:27.324145 # ok 13 getpid() SVE VL 256/SME VL 32 SM
7989 16:31:27.324245 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
7990 16:31:27.324364 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
7991 16:31:27.324690 # ok 16 getpid() SVE VL 256/SME VL 16 SM
7992 16:31:27.325007 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
7993 16:31:27.325324 # ok 18 getpid() SVE VL 240
7994 16:31:27.325481 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
7995 16:31:27.325826 # ok 20 getpid() SVE VL 240/SME VL 256 SM
7996 16:31:27.330238 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
7997 16:31:27.330759 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
7998 16:31:27.330900 # ok 23 getpid() SVE VL 240/SME VL 128 SM
7999 16:31:27.331199 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8000 16:31:27.331710 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8001 16:31:27.332023 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8002 16:31:27.332306 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8003 16:31:27.332429 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8004 16:31:27.332731 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8005 16:31:27.332830 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8006 16:31:27.332929 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8007 16:31:27.333027 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8008 16:31:27.333125 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8009 16:31:27.333221 # ok 34 getpid() SVE VL 224
8010 16:31:27.333318 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8011 16:31:27.333416 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8012 16:31:27.333695 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8013 16:31:27.333818 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8014 16:31:27.333923 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8015 16:31:27.334216 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8016 16:31:27.342312 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8017 16:31:27.342715 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8018 16:31:27.342834 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8019 16:31:27.342932 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8020 16:31:27.343041 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8021 16:31:27.343159 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8022 16:31:27.343274 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8023 16:31:27.343395 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8024 16:31:27.343827 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8025 16:31:27.344114 # ok 50 getpid() SVE VL 208
8026 16:31:27.344214 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8027 16:31:27.344511 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8028 16:31:27.344631 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8029 16:31:27.344731 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8030 16:31:27.345025 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8031 16:31:27.345134 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8032 16:31:27.345456 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8033 16:31:27.345555 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8034 16:31:27.345662 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8035 16:31:27.345748 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8036 16:31:27.345855 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8037 16:31:27.350204 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8038 16:31:27.350529 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8039 16:31:27.350616 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8040 16:31:27.350708 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8041 16:31:27.351007 # ok 66 getpid() SVE VL 192
8042 16:31:27.351118 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8043 16:31:27.351213 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8044 16:31:27.351301 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8045 16:31:27.351386 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8046 16:31:27.351487 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8047 16:31:27.351574 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8048 16:31:27.351660 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8049 16:31:27.351763 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8050 16:31:27.351852 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8051 16:31:27.351938 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8052 16:31:27.352040 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8053 16:31:27.352129 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8054 16:31:27.352233 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8055 16:31:27.352337 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8056 16:31:27.352726 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8057 16:31:27.352833 # ok 82 getpid() SVE VL 176
8058 16:31:27.352924 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8059 16:31:27.353029 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8060 16:31:27.353117 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8061 16:31:27.353218 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8062 16:31:27.353307 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8063 16:31:27.353405 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8064 16:31:27.353698 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8065 16:31:27.353805 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8066 16:31:27.353908 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8067 16:31:27.358170 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8068 16:31:27.358479 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8069 16:31:27.358602 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8070 16:31:27.358712 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8071 16:31:27.358819 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8072 16:31:27.359125 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8073 16:31:27.359231 # ok 98 getpid() SVE VL 160
8074 16:31:31.233797 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8075 16:31:31.235038 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8076 16:31:31.235355 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8077 16:31:31.235465 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8078 16:31:31.235575 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8079 16:31:31.235671 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8080 16:31:31.235777 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8081 16:31:31.235882 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8082 16:31:31.236172 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8083 16:31:31.236281 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8084 16:31:31.236387 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8085 16:31:31.236492 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8086 16:31:31.236582 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8087 16:31:31.236690 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8088 16:31:31.236991 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8089 16:31:31.237098 # ok 114 getpid() SVE VL 144
8090 16:31:31.237204 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8091 16:31:31.237295 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8092 16:31:31.237399 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8093 16:31:31.237504 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8094 16:31:31.237607 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8095 16:31:31.237925 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8096 16:31:31.238045 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8097 16:31:31.242580 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8098 16:31:31.242903 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8099 16:31:31.243007 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8100 16:31:31.243303 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8101 16:31:31.243405 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8102 16:31:31.243696 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8103 16:31:31.243798 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8104 16:31:31.243882 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8105 16:31:31.243976 # ok 130 getpid() SVE VL 128
8106 16:31:31.244059 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8107 16:31:31.244140 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8108 16:31:31.244233 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8109 16:31:31.244513 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8110 16:31:31.244615 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8111 16:31:31.244711 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8112 16:31:31.244793 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8113 16:31:31.244886 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8114 16:31:31.244978 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8115 16:31:31.245272 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8116 16:31:31.245372 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8117 16:31:31.245468 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8118 16:31:31.245549 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8119 16:31:31.245641 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8120 16:31:31.245741 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8121 16:31:31.246021 # ok 146 getpid() SVE VL 112
8122 16:31:31.250616 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8123 16:31:31.250744 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8124 16:31:31.251036 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8125 16:31:31.251161 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8126 16:31:31.251487 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8127 16:31:31.251607 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8128 16:31:31.251745 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8129 16:31:31.251861 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8130 16:31:31.252441 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8131 16:31:31.252549 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8132 16:31:31.252637 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8133 16:31:31.252719 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8134 16:31:31.253016 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8135 16:31:31.253120 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8136 16:31:31.253206 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8137 16:31:31.253303 # ok 162 getpid() SVE VL 96
8138 16:31:31.253831 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8139 16:31:31.253996 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8140 16:31:31.258321 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8141 16:31:31.258681 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8142 16:31:31.258786 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8143 16:31:31.258877 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8144 16:31:31.258980 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8145 16:31:31.259083 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8146 16:31:31.259186 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8147 16:31:31.259288 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8148 16:31:31.259575 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8149 16:31:31.259697 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8150 16:31:31.259788 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8151 16:31:31.259890 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8152 16:31:31.260180 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8153 16:31:31.260286 # ok 178 getpid() SVE VL 80
8154 16:31:31.260393 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8155 16:31:31.260485 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8156 16:31:31.260605 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8157 16:31:31.260719 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8158 16:31:31.260861 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8159 16:31:31.260971 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8160 16:31:31.261111 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8161 16:31:31.261238 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8162 16:31:31.261563 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8163 16:31:31.261703 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8164 16:31:31.262097 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8165 16:31:31.266313 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8166 16:31:31.266634 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8167 16:31:31.266978 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8168 16:31:31.267071 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8169 16:31:31.267167 # ok 194 getpid() SVE VL 64
8170 16:31:31.267239 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8171 16:31:34.406307 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8172 16:31:34.406533 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8173 16:31:34.406615 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8174 16:31:34.415264 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8175 16:31:34.416583 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8176 16:31:34.416704 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8177 16:31:34.416812 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8178 16:31:34.416945 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8179 16:31:34.417071 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8180 16:31:34.417198 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8181 16:31:34.417510 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8182 16:31:34.417616 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8183 16:31:34.417718 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8184 16:31:34.417809 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8185 16:31:34.417916 # ok 210 getpid() SVE VL 48
8186 16:31:34.418206 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8187 16:31:34.418300 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8188 16:31:34.418379 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8189 16:31:34.419155 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8190 16:31:34.419460 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8191 16:31:34.419564 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8192 16:31:34.419671 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8193 16:31:34.419777 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8194 16:31:34.419864 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8195 16:31:34.420152 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8196 16:31:34.420255 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8197 16:31:34.420361 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8198 16:31:34.420452 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8199 16:31:34.420587 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8200 16:31:34.420708 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8201 16:31:34.421046 # ok 226 getpid() SVE VL 32
8202 16:31:34.421598 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8203 16:31:34.421739 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8204 16:31:34.422064 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8205 16:31:34.422380 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8206 16:31:34.422508 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8207 16:31:34.422603 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8208 16:31:34.422710 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8209 16:31:34.422815 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8210 16:31:34.423149 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8211 16:31:34.423453 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8212 16:31:34.423554 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8213 16:31:34.423642 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8214 16:31:34.423934 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8215 16:31:34.424037 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8216 16:31:34.424124 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8217 16:31:34.424224 # ok 242 getpid() SVE VL 16
8218 16:31:34.424312 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8219 16:31:34.424401 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8220 16:31:34.424486 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8221 16:31:34.424968 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8222 16:31:34.425085 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8223 16:31:34.425188 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8224 16:31:34.425288 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8225 16:31:34.425586 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8226 16:31:34.425696 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8227 16:31:34.425798 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8228 16:31:34.425886 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8229 16:31:34.425988 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8230 16:31:34.434242 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8231 16:31:34.434807 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8232 16:31:34.434913 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8233 16:31:34.435026 # ok 258 sched_yield() FPSIMD
8234 16:31:34.435153 # ok 259 sched_yield() SVE VL 256
8235 16:31:34.435473 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8236 16:31:34.435600 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8237 16:31:34.435936 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8238 16:31:34.436056 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8239 16:31:34.436354 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8240 16:31:34.436673 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8241 16:31:34.436808 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8242 16:31:34.437352 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8243 16:31:34.437482 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8244 16:31:34.437819 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8245 16:31:34.446564 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8246 16:31:34.447020 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8247 16:31:34.447127 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8248 16:31:34.447237 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8249 16:31:34.447333 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8250 16:31:34.447441 # ok 275 sched_yield() SVE VL 240
8251 16:31:34.447984 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8252 16:31:34.448132 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8253 16:31:34.448467 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8254 16:31:34.448613 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8255 16:31:34.448940 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8256 16:31:34.449283 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8257 16:31:34.449618 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8258 16:31:34.449955 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8259 16:31:34.458486 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8260 16:31:34.458948 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8261 16:31:34.459745 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8262 16:31:34.460503 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8263 16:31:34.461055 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8264 16:31:34.461382 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8265 16:31:37.302594 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8266 16:31:37.303067 # ok 291 sched_yield() SVE VL 224
8267 16:31:37.303394 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8268 16:31:37.303708 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8269 16:31:37.303810 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8270 16:31:37.303909 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8271 16:31:37.303991 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8272 16:31:37.304082 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8273 16:31:37.304402 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8274 16:31:37.304504 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8275 16:31:37.304785 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8276 16:31:37.304886 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8277 16:31:37.304967 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8278 16:31:37.305059 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8279 16:31:37.305142 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8280 16:31:37.305232 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8281 16:31:37.305311 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8282 16:31:37.305400 # ok 307 sched_yield() SVE VL 208
8283 16:31:37.305491 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8284 16:31:37.305570 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8285 16:31:37.305670 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8286 16:31:37.305804 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8287 16:31:37.305931 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8288 16:31:37.310363 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8289 16:31:37.310720 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8290 16:31:37.311104 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8291 16:31:37.311753 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8292 16:31:37.312163 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8293 16:31:37.312598 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8294 16:31:37.312704 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8295 16:31:37.313021 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8296 16:31:37.313127 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8297 16:31:37.313423 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8298 16:31:37.313549 # ok 323 sched_yield() SVE VL 192
8299 16:31:37.313658 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8300 16:31:37.313782 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8301 16:31:37.313895 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8302 16:31:37.314407 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8303 16:31:37.322123 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8304 16:31:37.322448 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8305 16:31:37.322756 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8306 16:31:37.322858 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8307 16:31:37.322956 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8308 16:31:37.323471 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8309 16:31:37.323772 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8310 16:31:37.323874 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8311 16:31:37.323971 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8312 16:31:37.324065 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8313 16:31:37.324362 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8314 16:31:37.324463 # ok 339 sched_yield() SVE VL 176
8315 16:31:37.324755 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8316 16:31:37.324870 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8317 16:31:37.325160 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8318 16:31:37.325468 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8319 16:31:37.325553 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8320 16:31:37.325690 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8321 16:31:37.325980 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8322 16:31:37.326082 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8323 16:31:37.331102 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8324 16:31:37.331408 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8325 16:31:37.331576 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8326 16:31:37.331724 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8327 16:31:37.331819 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8328 16:31:37.331923 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8329 16:31:37.332014 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8330 16:31:37.332117 # ok 355 sched_yield() SVE VL 160
8331 16:31:37.332227 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8332 16:31:37.332518 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8333 16:31:37.332626 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8334 16:31:37.332936 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8335 16:31:37.333233 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8336 16:31:37.333468 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8337 16:31:37.334143 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8338 16:31:37.334264 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8339 16:31:37.334350 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8340 16:31:37.334432 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8341 16:31:37.334513 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8342 16:31:37.334593 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8343 16:31:37.334673 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8344 16:31:37.334754 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8345 16:31:37.338203 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8346 16:31:37.338554 # ok 371 sched_yield() SVE VL 144
8347 16:31:37.338657 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8348 16:31:37.338781 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8349 16:31:37.338875 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8350 16:31:37.338956 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8351 16:31:37.339031 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8352 16:31:40.236255 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8353 16:31:40.239209 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8354 16:31:40.239334 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8355 16:31:40.243745 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8356 16:31:40.244751 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8357 16:31:40.245309 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8358 16:31:40.245853 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8359 16:31:40.246643 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8360 16:31:40.246960 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8361 16:31:40.247084 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8362 16:31:40.247388 # ok 387 sched_yield() SVE VL 128
8363 16:31:40.247542 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8364 16:31:40.248486 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8365 16:31:40.249259 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8366 16:31:40.249993 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8367 16:31:40.254963 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8368 16:31:40.256140 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8369 16:31:40.256816 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8370 16:31:40.257694 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8371 16:31:40.257995 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8372 16:31:40.263372 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8373 16:31:40.263547 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8374 16:31:40.263906 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8375 16:31:40.264442 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8376 16:31:40.264955 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8377 16:31:40.265873 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8378 16:31:40.270371 # ok 403 sched_yield() SVE VL 112
8379 16:31:40.270697 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8380 16:31:40.270813 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8381 16:31:40.270922 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8382 16:31:40.271028 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8383 16:31:40.271133 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8384 16:31:40.271441 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8385 16:31:40.271546 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8386 16:31:40.271677 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8387 16:31:40.271785 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8388 16:31:40.271916 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8389 16:31:40.272023 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8390 16:31:40.272154 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8391 16:31:40.272279 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8392 16:31:40.272603 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8393 16:31:40.272711 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8394 16:31:40.272841 # ok 419 sched_yield() SVE VL 96
8395 16:31:40.273697 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8396 16:31:40.274240 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8397 16:31:40.278599 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8398 16:31:40.278728 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8399 16:31:40.278851 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8400 16:31:40.279355 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8401 16:31:40.279730 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8402 16:31:40.279855 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8403 16:31:40.280410 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8404 16:31:40.280510 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8405 16:31:40.280832 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8406 16:31:40.281167 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8407 16:31:40.281686 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8408 16:31:40.282018 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8409 16:31:40.286359 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8410 16:31:40.286772 # ok 435 sched_yield() SVE VL 80
8411 16:31:40.286902 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8412 16:31:40.287034 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8413 16:31:40.287176 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8414 16:31:40.287494 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8415 16:31:40.287930 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8416 16:31:40.288250 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8417 16:31:40.288354 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8418 16:31:40.288438 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8419 16:31:40.288536 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8420 16:31:40.288638 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8421 16:31:40.288741 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8422 16:31:40.288823 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8423 16:31:40.289251 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8424 16:31:40.289353 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8425 16:31:40.289434 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8426 16:31:40.289511 # ok 451 sched_yield() SVE VL 64
8427 16:31:40.289602 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8428 16:31:40.289703 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8429 16:31:40.294349 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8430 16:31:40.294677 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8431 16:31:40.294990 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8432 16:31:40.295112 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8433 16:31:40.295441 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8434 16:31:40.295848 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8435 16:31:40.295955 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8436 16:31:40.296261 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8437 16:31:40.296364 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8438 16:31:40.296459 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8439 16:31:41.187291 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8440 16:31:41.187516 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8441 16:31:41.187603 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8442 16:31:41.187685 # ok 467 sched_yield() SVE VL 48
8443 16:31:41.187767 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8444 16:31:41.188161 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8445 16:31:41.188277 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8446 16:31:41.188383 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8447 16:31:41.188490 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8448 16:31:41.189761 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8449 16:31:41.189877 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8450 16:31:41.190304 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8451 16:31:41.190390 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8452 16:31:41.190461 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8453 16:31:41.193865 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8454 16:31:41.203573 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8455 16:31:41.204213 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8456 16:31:41.204521 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8457 16:31:41.204659 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8458 16:31:41.205002 # ok 483 sched_yield() SVE VL 32
8459 16:31:41.205349 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8460 16:31:41.205473 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8461 16:31:41.205890 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8462 16:31:41.210182 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8463 16:31:41.210493 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8464 16:31:41.210618 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8465 16:31:41.210930 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8466 16:31:41.211260 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8467 16:31:41.211364 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8468 16:31:41.211652 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8469 16:31:41.211754 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8470 16:31:41.212039 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8471 16:31:41.212140 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8472 16:31:41.212573 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8473 16:31:41.212674 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8474 16:31:41.212756 # ok 499 sched_yield() SVE VL 16
8475 16:31:41.212834 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8476 16:31:41.213154 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8477 16:31:41.213257 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8478 16:31:41.213338 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8479 16:31:41.213629 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8480 16:31:41.213736 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8481 16:31:41.213818 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8482 16:31:41.214101 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8483 16:31:41.218617 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8484 16:31:41.218959 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8485 16:31:41.219580 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8486 16:31:41.219925 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8487 16:31:41.220262 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8488 16:31:41.220371 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8489 16:31:41.220512 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8490 16:31:41.220831 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8491 16:31:41.221117 ok 47 selftests: arm64: syscall-abi
8492 16:31:41.283147 # selftests: arm64: tpidr2
8493 16:31:41.446716 # TAP version 13
8494 16:31:41.447202 # 1..5
8495 16:31:41.447309 # # PID: 2809
8496 16:31:41.447607 # ok 1 default_value
8497 16:31:41.447718 # ok 2 write_read
8498 16:31:41.447806 # ok 3 write_sleep_read
8499 16:31:41.447906 # ok 4 write_fork_read
8500 16:31:41.447991 # ok 5 write_clone_read
8501 16:31:41.448072 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8502 16:31:41.464848 ok 48 selftests: arm64: tpidr2
8503 16:31:42.094258 arm64_tags_test pass
8504 16:31:42.094503 arm64_run_tags_test_sh pass
8505 16:31:42.094631 arm64_fake_sigreturn_bad_magic pass
8506 16:31:42.094974 arm64_fake_sigreturn_bad_size pass
8507 16:31:42.095309 arm64_fake_sigreturn_bad_size_for_magic0 pass
8508 16:31:42.095860 arm64_fake_sigreturn_duplicated_fpsimd pass
8509 16:31:42.095987 arm64_fake_sigreturn_misaligned_sp pass
8510 16:31:42.096120 arm64_fake_sigreturn_missing_fpsimd pass
8511 16:31:42.096232 arm64_fake_sigreturn_sme_change_vl pass
8512 16:31:42.096374 arm64_fake_sigreturn_sve_change_vl pass
8513 16:31:42.096485 arm64_mangle_pstate_invalid_compat_toggle pass
8514 16:31:42.096622 arm64_mangle_pstate_invalid_daif_bits pass
8515 16:31:42.096761 arm64_mangle_pstate_invalid_mode_el1h pass
8516 16:31:42.096894 arm64_mangle_pstate_invalid_mode_el1t pass
8517 16:31:42.097029 arm64_mangle_pstate_invalid_mode_el2h pass
8518 16:31:42.097167 arm64_mangle_pstate_invalid_mode_el2t pass
8519 16:31:42.097307 arm64_mangle_pstate_invalid_mode_el3h pass
8520 16:31:42.097441 arm64_mangle_pstate_invalid_mode_el3t pass
8521 16:31:42.097580 arm64_sme_trap_no_sm pass
8522 16:31:42.097722 arm64_sme_trap_non_streaming skip
8523 16:31:42.098062 arm64_sme_trap_za pass
8524 16:31:42.102141 arm64_sme_vl pass
8525 16:31:42.102550 arm64_ssve_regs pass
8526 16:31:42.102662 arm64_sve_regs pass
8527 16:31:42.102776 arm64_sve_vl pass
8528 16:31:42.102911 arm64_za_no_regs pass
8529 16:31:42.103020 arm64_za_regs pass
8530 16:31:42.103140 arm64_pac_global_corrupt_pac pass
8531 16:31:42.103277 arm64_pac_global_pac_instructions_not_nop pass
8532 16:31:42.103597 arm64_pac_global_pac_instructions_not_nop_generic pass
8533 16:31:42.103956 arm64_pac_global_single_thread_different_keys pass
8534 16:31:42.104069 arm64_pac_global_exec_changed_keys pass
8535 16:31:42.104196 arm64_pac_global_context_switch_keep_keys pass
8536 16:31:42.104520 arm64_pac_global_context_switch_keep_keys_generic pass
8537 16:31:42.104635 arm64_pac pass
8538 16:31:42.104768 arm64_fp-stress_FPSIMD-0-0 pass
8539 16:31:42.104869 arm64_fp-stress_SVE-VL-256-0 pass
8540 16:31:42.105198 arm64_fp-stress_SVE-VL-240-0 pass
8541 16:31:42.105513 arm64_fp-stress_SVE-VL-224-0 pass
8542 16:31:42.105626 arm64_fp-stress_SVE-VL-208-0 pass
8543 16:31:42.105921 arm64_fp-stress_SVE-VL-192-0 pass
8544 16:31:42.110130 arm64_fp-stress_SVE-VL-176-0 pass
8545 16:31:42.110435 arm64_fp-stress_SVE-VL-160-0 pass
8546 16:31:42.110542 arm64_fp-stress_SVE-VL-144-0 pass
8547 16:31:42.110655 arm64_fp-stress_SVE-VL-128-0 pass
8548 16:31:42.110793 arm64_fp-stress_SVE-VL-112-0 pass
8549 16:31:42.110923 arm64_fp-stress_SVE-VL-96-0 pass
8550 16:31:42.111270 arm64_fp-stress_SVE-VL-80-0 pass
8551 16:31:42.111610 arm64_fp-stress_SVE-VL-64-0 pass
8552 16:31:42.111734 arm64_fp-stress_SVE-VL-48-0 pass
8553 16:31:42.112037 arm64_fp-stress_SVE-VL-32-0 pass
8554 16:31:42.112521 arm64_fp-stress_SVE-VL-16-0 pass
8555 16:31:42.112635 arm64_fp-stress_SSVE-VL-256-0 pass
8556 16:31:42.112936 arm64_fp-stress_ZA-VL-256-0 pass
8557 16:31:42.113253 arm64_fp-stress_SSVE-VL-128-0 pass
8558 16:31:42.113561 arm64_fp-stress_ZA-VL-128-0 pass
8559 16:31:42.113685 arm64_fp-stress_SSVE-VL-64-0 pass
8560 16:31:42.118087 arm64_fp-stress_ZA-VL-64-0 pass
8561 16:31:42.122128 arm64_fp-stress_SSVE-VL-32-0 pass
8562 16:31:42.122234 arm64_fp-stress_ZA-VL-32-0 pass
8563 16:31:42.122319 arm64_fp-stress_SSVE-VL-16-0 pass
8564 16:31:42.122401 arm64_fp-stress_ZA-VL-16-0 pass
8565 16:31:42.122483 arm64_fp-stress pass
8566 16:31:42.122563 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8567 16:31:42.122645 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8568 16:31:42.122725 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8569 16:31:42.122806 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8570 16:31:42.122887 arm64_sve-ptrace_Set_SVE_VL_16 pass
8571 16:31:42.122968 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8572 16:31:42.123049 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8573 16:31:42.123130 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8574 16:31:42.123211 arm64_sve-ptrace_Set_SVE_VL_32 pass
8575 16:31:42.123294 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8576 16:31:42.123374 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8577 16:31:42.123455 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8578 16:31:42.123535 arm64_sve-ptrace_Set_SVE_VL_48 pass
8579 16:31:42.123615 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8580 16:31:42.123695 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8581 16:31:42.123774 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8582 16:31:42.123855 arm64_sve-ptrace_Set_SVE_VL_64 pass
8583 16:31:42.123934 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8584 16:31:42.124014 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8585 16:31:42.124094 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8586 16:31:42.124174 arm64_sve-ptrace_Set_SVE_VL_80 pass
8587 16:31:42.124254 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8588 16:31:42.126145 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8589 16:31:42.127409 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8590 16:31:42.128198 arm64_sve-ptrace_Set_SVE_VL_96 pass
8591 16:31:42.128496 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8592 16:31:42.129292 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8593 16:31:42.129414 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8594 16:31:42.129714 arm64_sve-ptrace_Set_SVE_VL_112 pass
8595 16:31:42.130023 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8596 16:31:42.134121 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8597 16:31:42.134425 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8598 16:31:42.134547 arm64_sve-ptrace_Set_SVE_VL_128 pass
8599 16:31:42.134876 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8600 16:31:42.135415 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8601 16:31:42.135519 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8602 16:31:42.135651 arm64_sve-ptrace_Set_SVE_VL_144 pass
8603 16:31:42.135779 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8604 16:31:42.136108 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8605 16:31:42.136632 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8606 16:31:42.136773 arm64_sve-ptrace_Set_SVE_VL_160 pass
8607 16:31:42.137340 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8608 16:31:42.137915 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8609 16:31:42.142093 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8610 16:31:42.142830 arm64_sve-ptrace_Set_SVE_VL_176 pass
8611 16:31:42.143198 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8612 16:31:42.143310 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8613 16:31:42.143406 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8614 16:31:42.143498 arm64_sve-ptrace_Set_SVE_VL_192 pass
8615 16:31:42.143688 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8616 16:31:42.144002 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8617 16:31:42.144126 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8618 16:31:42.144425 arm64_sve-ptrace_Set_SVE_VL_208 pass
8619 16:31:42.144539 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8620 16:31:42.144822 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8621 16:31:42.144942 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8622 16:31:42.145076 arm64_sve-ptrace_Set_SVE_VL_224 pass
8623 16:31:42.145384 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8624 16:31:42.145693 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8625 16:31:42.150078 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8626 16:31:42.150571 arm64_sve-ptrace_Set_SVE_VL_240 pass
8627 16:31:42.150903 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8628 16:31:42.151005 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8629 16:31:42.151289 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8630 16:31:42.151394 arm64_sve-ptrace_Set_SVE_VL_256 pass
8631 16:31:42.151490 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8632 16:31:42.151775 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8633 16:31:42.151888 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8634 16:31:42.151985 arm64_sve-ptrace_Set_SVE_VL_272 pass
8635 16:31:42.152276 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8636 16:31:42.152595 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8637 16:31:42.152708 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8638 16:31:42.153008 arm64_sve-ptrace_Set_SVE_VL_288 pass
8639 16:31:42.153108 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8640 16:31:42.153202 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8641 16:31:42.153495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8642 16:31:42.153822 arm64_sve-ptrace_Set_SVE_VL_304 pass
8643 16:31:42.153921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8644 16:31:42.158086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8645 16:31:42.158429 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8646 16:31:42.158542 arm64_sve-ptrace_Set_SVE_VL_320 pass
8647 16:31:42.158832 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8648 16:31:42.159307 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8649 16:31:42.159413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8650 16:31:42.159687 arm64_sve-ptrace_Set_SVE_VL_336 pass
8651 16:31:42.159790 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8652 16:31:42.160248 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8653 16:31:42.160353 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8654 16:31:42.160436 arm64_sve-ptrace_Set_SVE_VL_352 pass
8655 16:31:42.160741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8656 16:31:42.160842 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8657 16:31:42.160925 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8658 16:31:42.161004 arm64_sve-ptrace_Set_SVE_VL_368 pass
8659 16:31:42.161084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8660 16:31:42.161176 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8661 16:31:42.161259 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8662 16:31:42.161355 arm64_sve-ptrace_Set_SVE_VL_384 pass
8663 16:31:42.161643 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8664 16:31:42.161962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8665 16:31:42.166488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8666 16:31:42.166618 arm64_sve-ptrace_Set_SVE_VL_400 pass
8667 16:31:42.166951 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8668 16:31:42.167094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8669 16:31:42.167234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8670 16:31:42.167576 arm64_sve-ptrace_Set_SVE_VL_416 pass
8671 16:31:42.167688 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8672 16:31:42.167960 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8673 16:31:42.168275 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8674 16:31:42.168388 arm64_sve-ptrace_Set_SVE_VL_432 pass
8675 16:31:42.168669 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8676 16:31:42.168853 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8677 16:31:42.169288 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8678 16:31:42.169394 arm64_sve-ptrace_Set_SVE_VL_448 pass
8679 16:31:42.169731 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8680 16:31:42.169844 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8681 16:31:42.174815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8682 16:31:42.175097 arm64_sve-ptrace_Set_SVE_VL_464 pass
8683 16:31:42.175416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8684 16:31:42.176559 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8685 16:31:42.176673 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8686 16:31:42.177388 arm64_sve-ptrace_Set_SVE_VL_480 pass
8687 16:31:42.177704 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8688 16:31:42.182086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8689 16:31:42.182392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8690 16:31:42.182686 arm64_sve-ptrace_Set_SVE_VL_496 pass
8691 16:31:42.182800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8692 16:31:42.182926 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8693 16:31:42.183053 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8694 16:31:42.183183 arm64_sve-ptrace_Set_SVE_VL_512 pass
8695 16:31:42.183317 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8696 16:31:42.183452 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8697 16:31:42.183585 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8698 16:31:42.183710 arm64_sve-ptrace_Set_SVE_VL_528 pass
8699 16:31:42.183836 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8700 16:31:42.183962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8701 16:31:42.184285 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8702 16:31:42.184419 arm64_sve-ptrace_Set_SVE_VL_544 pass
8703 16:31:42.184528 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8704 16:31:42.184655 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8705 16:31:42.184980 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8706 16:31:42.185094 arm64_sve-ptrace_Set_SVE_VL_560 pass
8707 16:31:42.185230 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8708 16:31:42.185548 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8709 16:31:42.185677 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8710 16:31:42.185787 arm64_sve-ptrace_Set_SVE_VL_576 pass
8711 16:31:42.194076 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8712 16:31:42.194596 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8713 16:31:42.194943 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8714 16:31:42.195077 arm64_sve-ptrace_Set_SVE_VL_592 pass
8715 16:31:42.195596 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8716 16:31:42.195713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8717 16:31:42.196022 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8718 16:31:42.196330 arm64_sve-ptrace_Set_SVE_VL_608 pass
8719 16:31:42.196447 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
8720 16:31:42.196742 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
8721 16:31:42.197041 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
8722 16:31:42.197351 arm64_sve-ptrace_Set_SVE_VL_624 pass
8723 16:31:42.197458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
8724 16:31:42.197752 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
8725 16:31:42.197853 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
8726 16:31:42.202075 arm64_sve-ptrace_Set_SVE_VL_640 pass
8727 16:31:42.202708 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
8728 16:31:42.203043 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
8729 16:31:42.203603 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
8730 16:31:42.203725 arm64_sve-ptrace_Set_SVE_VL_656 pass
8731 16:31:42.203844 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
8732 16:31:42.204162 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
8733 16:31:42.204311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
8734 16:31:42.204799 arm64_sve-ptrace_Set_SVE_VL_672 pass
8735 16:31:42.205380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
8736 16:31:42.205745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
8737 16:31:42.205849 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
8738 16:31:42.210080 arm64_sve-ptrace_Set_SVE_VL_688 pass
8739 16:31:42.210660 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
8740 16:31:42.211002 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
8741 16:31:42.211325 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
8742 16:31:42.211454 arm64_sve-ptrace_Set_SVE_VL_704 pass
8743 16:31:42.212203 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
8744 16:31:42.212510 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
8745 16:31:42.212625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
8746 16:31:42.212742 arm64_sve-ptrace_Set_SVE_VL_720 pass
8747 16:31:42.212872 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
8748 16:31:42.213009 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
8749 16:31:42.213339 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
8750 16:31:42.213467 arm64_sve-ptrace_Set_SVE_VL_736 pass
8751 16:31:42.213802 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
8752 16:31:42.213915 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
8753 16:31:42.214042 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
8754 16:31:42.218083 arm64_sve-ptrace_Set_SVE_VL_752 pass
8755 16:31:42.218384 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
8756 16:31:42.218708 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
8757 16:31:42.219026 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
8758 16:31:42.219325 arm64_sve-ptrace_Set_SVE_VL_768 pass
8759 16:31:42.219425 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
8760 16:31:42.219530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
8761 16:31:42.220016 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
8762 16:31:42.220130 arm64_sve-ptrace_Set_SVE_VL_784 pass
8763 16:31:42.220422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
8764 16:31:42.220536 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
8765 16:31:42.220829 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
8766 16:31:42.220930 arm64_sve-ptrace_Set_SVE_VL_800 pass
8767 16:31:42.221219 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
8768 16:31:42.221333 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
8769 16:31:42.221625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
8770 16:31:42.221746 arm64_sve-ptrace_Set_SVE_VL_816 pass
8771 16:31:42.222040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
8772 16:31:42.226082 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
8773 16:31:42.226757 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
8774 16:31:42.226928 arm64_sve-ptrace_Set_SVE_VL_832 pass
8775 16:31:42.227239 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
8776 16:31:42.227354 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
8777 16:31:42.227861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
8778 16:31:42.227961 arm64_sve-ptrace_Set_SVE_VL_848 pass
8779 16:31:42.228266 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
8780 16:31:42.228367 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
8781 16:31:42.228449 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
8782 16:31:42.228743 arm64_sve-ptrace_Set_SVE_VL_864 pass
8783 16:31:42.228844 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
8784 16:31:42.228928 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
8785 16:31:42.229211 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
8786 16:31:42.229322 arm64_sve-ptrace_Set_SVE_VL_880 pass
8787 16:31:42.229419 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
8788 16:31:42.229697 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
8789 16:31:42.229821 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
8790 16:31:42.229921 arm64_sve-ptrace_Set_SVE_VL_896 pass
8791 16:31:42.230011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
8792 16:31:42.230300 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
8793 16:31:42.230411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
8794 16:31:42.234095 arm64_sve-ptrace_Set_SVE_VL_912 pass
8795 16:31:42.234419 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
8796 16:31:42.234742 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
8797 16:31:42.234883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
8798 16:31:42.235405 arm64_sve-ptrace_Set_SVE_VL_928 pass
8799 16:31:42.235514 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
8800 16:31:42.235809 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
8801 16:31:42.236107 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
8802 16:31:42.236234 arm64_sve-ptrace_Set_SVE_VL_944 pass
8803 16:31:42.236620 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
8804 16:31:42.236962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
8805 16:31:42.237301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
8806 16:31:42.237941 arm64_sve-ptrace_Set_SVE_VL_960 pass
8807 16:31:42.242079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
8808 16:31:42.242482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
8809 16:31:42.242793 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
8810 16:31:42.243348 arm64_sve-ptrace_Set_SVE_VL_976 pass
8811 16:31:42.243692 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
8812 16:31:42.244020 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
8813 16:31:42.244766 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
8814 16:31:42.244885 arm64_sve-ptrace_Set_SVE_VL_992 pass
8815 16:31:42.245020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
8816 16:31:42.245546 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
8817 16:31:42.245677 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
8818 16:31:42.245812 arm64_sve-ptrace_Set_SVE_VL_1008 pass
8819 16:31:42.250188 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
8820 16:31:42.250569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
8821 16:31:42.250723 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
8822 16:31:42.250852 arm64_sve-ptrace_Set_SVE_VL_1024 pass
8823 16:31:42.251182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
8824 16:31:42.251323 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
8825 16:31:42.251463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
8826 16:31:42.251791 arm64_sve-ptrace_Set_SVE_VL_1040 pass
8827 16:31:42.251956 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
8828 16:31:42.252285 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
8829 16:31:42.252591 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
8830 16:31:42.252736 arm64_sve-ptrace_Set_SVE_VL_1056 pass
8831 16:31:42.253069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
8832 16:31:42.253411 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
8833 16:31:42.253715 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
8834 16:31:42.253821 arm64_sve-ptrace_Set_SVE_VL_1072 pass
8835 16:31:42.253917 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
8836 16:31:42.258402 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
8837 16:31:42.260327 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
8838 16:31:42.260433 arm64_sve-ptrace_Set_SVE_VL_1088 pass
8839 16:31:42.260515 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
8840 16:31:42.260596 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
8841 16:31:42.260676 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
8842 16:31:42.260754 arm64_sve-ptrace_Set_SVE_VL_1104 pass
8843 16:31:42.260831 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
8844 16:31:42.261112 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
8845 16:31:42.261212 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
8846 16:31:42.261293 arm64_sve-ptrace_Set_SVE_VL_1120 pass
8847 16:31:42.261384 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
8848 16:31:42.261476 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
8849 16:31:42.261889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
8850 16:31:42.261995 arm64_sve-ptrace_Set_SVE_VL_1136 pass
8851 16:31:42.266237 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
8852 16:31:42.266660 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
8853 16:31:42.266795 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
8854 16:31:42.266929 arm64_sve-ptrace_Set_SVE_VL_1152 pass
8855 16:31:42.267255 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
8856 16:31:42.267368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
8857 16:31:42.267478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
8858 16:31:42.267588 arm64_sve-ptrace_Set_SVE_VL_1168 pass
8859 16:31:42.267905 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
8860 16:31:42.268045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
8861 16:31:42.268368 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
8862 16:31:42.268475 arm64_sve-ptrace_Set_SVE_VL_1184 pass
8863 16:31:42.268862 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
8864 16:31:42.268974 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
8865 16:31:42.269286 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
8866 16:31:42.269423 arm64_sve-ptrace_Set_SVE_VL_1200 pass
8867 16:31:42.269694 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
8868 16:31:42.269806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
8869 16:31:42.270116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
8870 16:31:42.274122 arm64_sve-ptrace_Set_SVE_VL_1216 pass
8871 16:31:42.274667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
8872 16:31:42.274804 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
8873 16:31:42.275132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
8874 16:31:42.275722 arm64_sve-ptrace_Set_SVE_VL_1232 pass
8875 16:31:42.276258 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
8876 16:31:42.276732 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
8877 16:31:42.277057 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
8878 16:31:42.277382 arm64_sve-ptrace_Set_SVE_VL_1248 pass
8879 16:31:42.277482 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
8880 16:31:42.277567 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
8881 16:31:42.277669 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
8882 16:31:42.277766 arm64_sve-ptrace_Set_SVE_VL_1264 pass
8883 16:31:42.282287 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
8884 16:31:42.282619 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
8885 16:31:42.283000 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
8886 16:31:42.283332 arm64_sve-ptrace_Set_SVE_VL_1280 pass
8887 16:31:42.283439 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
8888 16:31:42.283743 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
8889 16:31:42.283860 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
8890 16:31:42.283976 arm64_sve-ptrace_Set_SVE_VL_1296 pass
8891 16:31:42.284275 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
8892 16:31:42.284611 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
8893 16:31:42.284742 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
8894 16:31:42.284859 arm64_sve-ptrace_Set_SVE_VL_1312 pass
8895 16:31:42.285143 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
8896 16:31:42.285472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
8897 16:31:42.285963 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
8898 16:31:42.294107 arm64_sve-ptrace_Set_SVE_VL_1328 pass
8899 16:31:42.294530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
8900 16:31:42.294804 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
8901 16:31:42.294918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
8902 16:31:42.295040 arm64_sve-ptrace_Set_SVE_VL_1344 pass
8903 16:31:42.295147 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
8904 16:31:42.295263 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
8905 16:31:42.295562 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
8906 16:31:42.295674 arm64_sve-ptrace_Set_SVE_VL_1360 pass
8907 16:31:42.295804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
8908 16:31:42.295910 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
8909 16:31:42.296069 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
8910 16:31:42.296411 arm64_sve-ptrace_Set_SVE_VL_1376 pass
8911 16:31:42.296757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
8912 16:31:42.296885 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
8913 16:31:42.297003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
8914 16:31:42.297135 arm64_sve-ptrace_Set_SVE_VL_1392 pass
8915 16:31:42.297239 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
8916 16:31:42.297369 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
8917 16:31:42.297685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
8918 16:31:42.297788 arm64_sve-ptrace_Set_SVE_VL_1408 pass
8919 16:31:42.298084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
8920 16:31:42.302308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
8921 16:31:42.302632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
8922 16:31:42.302760 arm64_sve-ptrace_Set_SVE_VL_1424 pass
8923 16:31:42.303154 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
8924 16:31:42.303287 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
8925 16:31:42.303434 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
8926 16:31:42.303889 arm64_sve-ptrace_Set_SVE_VL_1440 pass
8927 16:31:42.304156 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
8928 16:31:42.304264 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
8929 16:31:42.304373 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
8930 16:31:42.304479 arm64_sve-ptrace_Set_SVE_VL_1456 pass
8931 16:31:42.304581 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
8932 16:31:42.304886 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
8933 16:31:42.305008 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
8934 16:31:42.305325 arm64_sve-ptrace_Set_SVE_VL_1472 pass
8935 16:31:42.305455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
8936 16:31:42.305563 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
8937 16:31:42.305974 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
8938 16:31:42.310227 arm64_sve-ptrace_Set_SVE_VL_1488 pass
8939 16:31:42.310570 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
8940 16:31:42.310763 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
8941 16:31:42.310895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
8942 16:31:42.311004 arm64_sve-ptrace_Set_SVE_VL_1504 pass
8943 16:31:42.311106 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
8944 16:31:42.311393 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
8945 16:31:42.311514 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
8946 16:31:42.311977 arm64_sve-ptrace_Set_SVE_VL_1520 pass
8947 16:31:42.312087 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
8948 16:31:42.312178 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
8949 16:31:42.312659 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
8950 16:31:42.312765 arm64_sve-ptrace_Set_SVE_VL_1536 pass
8951 16:31:42.312858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
8952 16:31:42.312943 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
8953 16:31:42.313046 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
8954 16:31:42.313342 arm64_sve-ptrace_Set_SVE_VL_1552 pass
8955 16:31:42.313448 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
8956 16:31:42.313539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
8957 16:31:42.313675 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
8958 16:31:42.314269 arm64_sve-ptrace_Set_SVE_VL_1568 pass
8959 16:31:42.314382 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
8960 16:31:42.314478 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
8961 16:31:42.314571 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
8962 16:31:42.318154 arm64_sve-ptrace_Set_SVE_VL_1584 pass
8963 16:31:42.318462 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
8964 16:31:42.318843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
8965 16:31:42.318952 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
8966 16:31:42.319047 arm64_sve-ptrace_Set_SVE_VL_1600 pass
8967 16:31:42.319176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
8968 16:31:42.319291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
8969 16:31:42.319816 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
8970 16:31:42.319923 arm64_sve-ptrace_Set_SVE_VL_1616 pass
8971 16:31:42.320032 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
8972 16:31:42.320342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
8973 16:31:42.320462 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
8974 16:31:42.320755 arm64_sve-ptrace_Set_SVE_VL_1632 pass
8975 16:31:42.320877 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
8976 16:31:42.321200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
8977 16:31:42.321397 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
8978 16:31:42.321530 arm64_sve-ptrace_Set_SVE_VL_1648 pass
8979 16:31:42.321853 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
8980 16:31:42.321965 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
8981 16:31:42.322077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
8982 16:31:42.322192 arm64_sve-ptrace_Set_SVE_VL_1664 pass
8983 16:31:42.326076 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
8984 16:31:42.326523 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
8985 16:31:42.326755 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
8986 16:31:42.326965 arm64_sve-ptrace_Set_SVE_VL_1680 pass
8987 16:31:42.327076 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
8988 16:31:42.327188 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
8989 16:31:42.327557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
8990 16:31:42.327786 arm64_sve-ptrace_Set_SVE_VL_1696 pass
8991 16:31:42.328086 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
8992 16:31:42.328207 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
8993 16:31:42.328313 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
8994 16:31:42.328603 arm64_sve-ptrace_Set_SVE_VL_1712 pass
8995 16:31:42.328708 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
8996 16:31:42.329009 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
8997 16:31:42.329116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
8998 16:31:42.329205 arm64_sve-ptrace_Set_SVE_VL_1728 pass
8999 16:31:42.329307 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9000 16:31:42.329393 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9001 16:31:42.329696 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9002 16:31:42.334605 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9003 16:31:42.334928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9004 16:31:42.335277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9005 16:31:42.335605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9006 16:31:42.335735 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9007 16:31:42.335866 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9008 16:31:42.336636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9009 16:31:42.336782 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9010 16:31:42.337128 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9011 16:31:42.337453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9012 16:31:42.337567 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9013 16:31:42.337923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9014 16:31:42.338016 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9015 16:31:42.338118 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9016 16:31:42.342215 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9017 16:31:42.342556 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9018 16:31:42.342681 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9019 16:31:42.342811 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9020 16:31:42.343155 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9021 16:31:42.343286 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9022 16:31:42.343412 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9023 16:31:42.343756 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9024 16:31:42.344120 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9025 16:31:42.344467 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9026 16:31:42.344585 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9027 16:31:42.344716 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9028 16:31:42.345033 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9029 16:31:42.345360 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9030 16:31:42.345743 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9031 16:31:42.345871 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9032 16:31:42.350152 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9033 16:31:42.350686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9034 16:31:42.350812 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9035 16:31:42.350923 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9036 16:31:42.351238 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9037 16:31:42.351343 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9038 16:31:42.351453 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9039 16:31:42.351768 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9040 16:31:42.351870 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9041 16:31:42.351955 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9042 16:31:42.352035 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9043 16:31:42.352364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9044 16:31:42.352465 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9045 16:31:42.352548 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9046 16:31:42.352629 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9047 16:31:42.352708 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9048 16:31:42.352802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9049 16:31:42.353091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9050 16:31:42.353198 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9051 16:31:42.353307 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9052 16:31:42.353784 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9053 16:31:42.353895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9054 16:31:42.353991 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9055 16:31:42.354285 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9056 16:31:42.358178 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9057 16:31:42.358457 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9058 16:31:42.358583 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9059 16:31:42.358904 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9060 16:31:42.359031 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9061 16:31:42.359356 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9062 16:31:42.359462 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9063 16:31:42.359567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9064 16:31:42.359884 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9065 16:31:42.360010 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9066 16:31:42.360383 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9067 16:31:42.360556 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9068 16:31:42.360664 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9069 16:31:42.360774 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9070 16:31:42.360864 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9071 16:31:42.360966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9072 16:31:42.361070 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9073 16:31:42.361570 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9074 16:31:42.361898 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9075 16:31:42.361995 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9076 16:31:42.362084 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9077 16:31:42.366114 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9078 16:31:42.366424 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9079 16:31:42.366549 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9080 16:31:42.366901 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9081 16:31:42.367117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9082 16:31:42.367429 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9083 16:31:42.367568 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9084 16:31:42.367710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9085 16:31:42.368048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9086 16:31:42.368169 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9087 16:31:42.368496 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9088 16:31:42.368628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9089 16:31:42.368933 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9090 16:31:42.369046 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9091 16:31:42.369349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9092 16:31:42.369456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9093 16:31:42.369564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9094 16:31:42.369907 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9095 16:31:42.370015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9096 16:31:42.374085 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9097 16:31:42.374401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9098 16:31:42.374510 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9099 16:31:42.374824 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9100 16:31:42.374947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9101 16:31:42.375313 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9102 16:31:42.375434 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9103 16:31:42.375743 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9104 16:31:42.375866 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9105 16:31:42.376170 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9106 16:31:42.376486 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9107 16:31:42.376791 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9108 16:31:42.376896 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9109 16:31:42.377002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9110 16:31:42.377093 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9111 16:31:42.377196 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9112 16:31:42.377506 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9113 16:31:42.377628 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9114 16:31:42.377742 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9115 16:31:42.382153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9116 16:31:42.382482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9117 16:31:42.382801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9118 16:31:42.382908 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9119 16:31:42.383239 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9120 16:31:42.383340 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9121 16:31:42.383437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9122 16:31:42.383534 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9123 16:31:42.383628 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9124 16:31:42.384077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9125 16:31:42.384180 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9126 16:31:42.384275 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9127 16:31:42.384560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9128 16:31:42.384856 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9129 16:31:42.384958 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9130 16:31:42.385052 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9131 16:31:42.385346 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9132 16:31:42.385464 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9133 16:31:42.385781 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9134 16:31:42.386086 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9135 16:31:42.390084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9136 16:31:42.390395 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9137 16:31:42.390731 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9138 16:31:42.390844 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9139 16:31:42.391167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9140 16:31:42.391276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9141 16:31:42.391389 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9142 16:31:42.391720 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9143 16:31:42.391840 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9144 16:31:42.391949 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9145 16:31:42.392043 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9146 16:31:42.392554 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9147 16:31:42.392667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9148 16:31:42.392757 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9149 16:31:42.392841 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9150 16:31:42.392919 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9151 16:31:42.393232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9152 16:31:42.393343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9153 16:31:42.393430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9154 16:31:42.393511 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9155 16:31:42.393589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9156 16:31:42.393947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9157 16:31:42.394050 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9158 16:31:42.394133 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9159 16:31:42.394213 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9160 16:31:42.394292 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9161 16:31:42.398507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9162 16:31:42.398808 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9163 16:31:42.398922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9164 16:31:42.399052 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9165 16:31:42.399166 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9166 16:31:42.399303 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9167 16:31:42.399432 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9168 16:31:42.399569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9169 16:31:42.399702 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9170 16:31:42.399831 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9171 16:31:42.400153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9172 16:31:42.400276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9173 16:31:42.400568 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9174 16:31:42.400690 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9175 16:31:42.400789 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9176 16:31:42.400882 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9177 16:31:42.400990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9178 16:31:42.401097 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9179 16:31:42.401212 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9180 16:31:42.401345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9181 16:31:42.401710 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9182 16:31:42.402009 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9183 16:31:42.402089 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9184 16:31:42.406093 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9185 16:31:42.406407 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9186 16:31:42.406524 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9187 16:31:42.406647 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9188 16:31:42.406738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9189 16:31:42.407159 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9190 16:31:42.407285 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9191 16:31:42.407394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9192 16:31:42.407497 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9193 16:31:42.407613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9194 16:31:42.407707 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9195 16:31:42.407866 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9196 16:31:42.407979 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9197 16:31:42.408127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9198 16:31:42.408255 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9199 16:31:42.408369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9200 16:31:42.408485 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9201 16:31:42.408608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9202 16:31:42.408708 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9203 16:31:42.409001 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9204 16:31:42.409115 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9205 16:31:42.409455 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9206 16:31:42.409558 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9207 16:31:42.409668 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9208 16:31:42.409761 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9209 16:31:42.409882 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9210 16:31:42.409990 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9211 16:31:42.414092 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9212 16:31:42.414415 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9213 16:31:42.414525 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9214 16:31:42.414651 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9215 16:31:42.414790 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9216 16:31:42.414970 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9217 16:31:42.415098 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9218 16:31:42.415224 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9219 16:31:42.415336 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9220 16:31:42.415466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9221 16:31:42.415621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9222 16:31:42.415738 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9223 16:31:42.415878 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9224 16:31:42.416015 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9225 16:31:42.416154 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9226 16:31:42.416287 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9227 16:31:42.416415 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9228 16:31:42.416538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9229 16:31:42.416943 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9230 16:31:42.417047 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9231 16:31:42.417174 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9232 16:31:42.417303 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9233 16:31:42.417425 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9234 16:31:42.417755 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9235 16:31:42.417863 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9236 16:31:42.417957 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9237 16:31:42.418050 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9238 16:31:42.418142 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9239 16:31:42.418429 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9240 16:31:42.426004 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9241 16:31:42.426301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9242 16:31:42.426613 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9243 16:31:42.426765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9244 16:31:42.426862 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9245 16:31:42.426957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9246 16:31:42.427048 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9247 16:31:42.427139 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9248 16:31:42.427426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9249 16:31:42.427552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9250 16:31:42.427659 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9251 16:31:42.427767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9252 16:31:42.427874 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9253 16:31:42.428182 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9254 16:31:42.428298 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9255 16:31:42.428426 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9256 16:31:42.428554 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9257 16:31:42.428676 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9258 16:31:42.428771 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9259 16:31:42.428876 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9260 16:31:42.428979 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9261 16:31:42.429315 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9262 16:31:42.429437 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9263 16:31:42.429560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9264 16:31:42.429876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9265 16:31:42.429966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9266 16:31:42.434134 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9267 16:31:42.434663 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9268 16:31:42.434807 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9269 16:31:42.435033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9270 16:31:42.435161 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9271 16:31:42.435269 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9272 16:31:42.435367 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9273 16:31:42.435489 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9274 16:31:42.435601 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9275 16:31:42.435728 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9276 16:31:42.435848 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9277 16:31:42.435981 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9278 16:31:42.436088 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9279 16:31:42.436229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9280 16:31:42.436359 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9281 16:31:42.436777 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9282 16:31:42.436893 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9283 16:31:42.437027 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9284 16:31:42.437143 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9285 16:31:42.437279 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9286 16:31:42.437396 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9287 16:31:42.437538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9288 16:31:42.437675 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9289 16:31:42.437802 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9290 16:31:42.437928 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9291 16:31:42.442307 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9292 16:31:42.442637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9293 16:31:42.442747 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9294 16:31:42.442842 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9295 16:31:42.443162 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9296 16:31:42.443266 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9297 16:31:42.443347 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9298 16:31:42.443441 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9299 16:31:42.443537 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9300 16:31:42.443631 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9301 16:31:42.443921 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9302 16:31:42.444036 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9303 16:31:42.444337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9304 16:31:42.444452 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9305 16:31:42.444776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9306 16:31:42.444881 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9307 16:31:42.444975 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9308 16:31:42.445068 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9309 16:31:42.445369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9310 16:31:42.445469 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9311 16:31:42.445782 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9312 16:31:42.445883 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9313 16:31:42.445977 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9314 16:31:42.446271 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9315 16:31:42.446376 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9316 16:31:42.450438 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9317 16:31:42.450763 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9318 16:31:42.450868 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9319 16:31:42.450957 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9320 16:31:42.451429 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9321 16:31:42.451548 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9322 16:31:42.451632 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9323 16:31:42.458219 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9324 16:31:42.458531 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9325 16:31:42.458638 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9326 16:31:42.458938 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9327 16:31:42.459046 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9328 16:31:42.459136 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9329 16:31:42.459239 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9330 16:31:42.459340 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9331 16:31:42.459643 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9332 16:31:42.459749 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9333 16:31:42.459839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9334 16:31:42.459927 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9335 16:31:42.460032 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9336 16:31:42.460124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9337 16:31:42.460230 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9338 16:31:42.460320 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9339 16:31:42.460422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9340 16:31:42.460547 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9341 16:31:42.460674 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9342 16:31:42.460802 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9343 16:31:42.460931 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9344 16:31:42.461056 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9345 16:31:42.461186 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9346 16:31:42.461320 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9347 16:31:42.461449 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9348 16:31:42.461919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9349 16:31:42.462033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9350 16:31:42.462154 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9351 16:31:42.462277 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9352 16:31:42.462385 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9353 16:31:42.462513 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9354 16:31:42.462610 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9355 16:31:42.462728 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9356 16:31:42.462853 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9357 16:31:42.462978 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9358 16:31:42.463107 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9359 16:31:42.463232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9360 16:31:42.463364 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9361 16:31:42.463491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9362 16:31:42.463817 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9363 16:31:42.463927 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9364 16:31:42.464627 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9365 16:31:42.464732 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9366 16:31:42.464816 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9367 16:31:42.464900 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9368 16:31:42.464984 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9369 16:31:42.465264 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9370 16:31:42.465368 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9371 16:31:42.465452 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9372 16:31:42.465697 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9373 16:31:42.465800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9374 16:31:42.465884 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9375 16:31:42.465974 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9376 16:31:42.466257 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9377 16:31:42.470132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9378 16:31:42.470535 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9379 16:31:42.470639 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9380 16:31:42.470748 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9381 16:31:42.470837 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9382 16:31:42.470949 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9383 16:31:42.471055 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9384 16:31:42.471159 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9385 16:31:42.471456 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9386 16:31:42.471587 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9387 16:31:42.471714 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9388 16:31:42.471830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9389 16:31:42.472260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9390 16:31:42.472364 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9391 16:31:42.472497 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9392 16:31:42.472843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9393 16:31:42.472952 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9394 16:31:42.473044 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9395 16:31:42.473133 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9396 16:31:42.473236 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9397 16:31:42.473327 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9398 16:31:42.473414 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9399 16:31:42.473517 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9400 16:31:42.473622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9401 16:31:42.473754 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9402 16:31:42.473924 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9403 16:31:42.474076 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9404 16:31:42.474390 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9405 16:31:42.478180 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9406 16:31:42.478527 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9407 16:31:42.478645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9408 16:31:42.478760 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9409 16:31:42.478890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9410 16:31:42.478987 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9411 16:31:42.479080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9412 16:31:42.479173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9413 16:31:42.479474 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9414 16:31:42.479576 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9415 16:31:42.479824 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9416 16:31:42.480381 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9417 16:31:42.480480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9418 16:31:42.480568 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9419 16:31:42.480655 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9420 16:31:42.480739 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9421 16:31:42.480841 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9422 16:31:42.480934 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9423 16:31:42.481022 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9424 16:31:42.481123 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9425 16:31:42.481208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9426 16:31:42.481292 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9427 16:31:42.481391 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9428 16:31:42.481491 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9429 16:31:42.481592 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9430 16:31:42.481700 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9431 16:31:42.481801 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9432 16:31:42.486113 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9433 16:31:42.486454 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9434 16:31:42.486583 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9435 16:31:42.486692 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9436 16:31:42.486819 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9437 16:31:42.486944 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9438 16:31:42.487034 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9439 16:31:42.487140 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9440 16:31:42.487244 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9441 16:31:42.487560 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9442 16:31:42.487664 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9443 16:31:42.487770 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9444 16:31:42.487874 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9445 16:31:42.488191 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9446 16:31:42.488306 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9447 16:31:42.488422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9448 16:31:42.488517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9449 16:31:42.488619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9450 16:31:42.488725 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9451 16:31:42.488828 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9452 16:31:42.489140 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9453 16:31:42.489256 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9454 16:31:42.489382 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9455 16:31:42.489691 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9456 16:31:42.489811 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9457 16:31:42.489922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9458 16:31:42.490053 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9459 16:31:42.490167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9460 16:31:42.490272 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9461 16:31:42.490400 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9462 16:31:42.490528 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9463 16:31:42.490651 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9464 16:31:42.490774 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9465 16:31:42.490905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9466 16:31:42.491029 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9467 16:31:42.491173 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9468 16:31:42.491490 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9469 16:31:42.498117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9470 16:31:42.498432 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9471 16:31:42.498529 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9472 16:31:42.498819 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9473 16:31:42.498916 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9474 16:31:42.499003 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9475 16:31:42.499094 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9476 16:31:42.499174 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9477 16:31:42.499264 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9478 16:31:42.499355 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9479 16:31:42.499633 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9480 16:31:42.499731 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9481 16:31:42.499824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9482 16:31:42.499904 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9483 16:31:42.517844 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9484 16:31:42.518379 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9485 16:31:42.518726 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9486 16:31:42.518837 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9487 16:31:42.519150 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9488 16:31:42.519271 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9489 16:31:42.519405 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9490 16:31:42.519538 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9491 16:31:42.519866 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9492 16:31:42.519988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9493 16:31:42.520094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9494 16:31:42.520199 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9495 16:31:42.520518 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9496 16:31:42.520627 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9497 16:31:42.520932 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9498 16:31:42.521043 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9499 16:31:42.521169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9500 16:31:42.521299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9501 16:31:42.521427 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9502 16:31:42.521553 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9503 16:31:42.521683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9504 16:31:42.521817 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9505 16:31:42.522156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9506 16:31:42.522252 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9507 16:31:42.526386 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9508 16:31:42.526503 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9509 16:31:42.526878 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9510 16:31:42.527040 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9511 16:31:42.527154 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9512 16:31:42.527288 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9513 16:31:42.527403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9514 16:31:42.527505 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9515 16:31:42.527610 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9516 16:31:42.527733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9517 16:31:42.527833 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9518 16:31:42.527946 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9519 16:31:42.528057 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9520 16:31:42.528138 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9521 16:31:42.528267 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9522 16:31:42.528393 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9523 16:31:42.528526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9524 16:31:42.528859 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9525 16:31:42.529202 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9526 16:31:42.529532 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9527 16:31:42.529651 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9528 16:31:42.529808 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9529 16:31:42.529914 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9530 16:31:42.530024 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9531 16:31:42.530121 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9532 16:31:42.530232 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9533 16:31:42.530327 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9534 16:31:42.530440 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9535 16:31:42.530574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9536 16:31:42.530687 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9537 16:31:42.530814 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9538 16:31:42.530949 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9539 16:31:42.531083 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9540 16:31:42.531204 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9541 16:31:42.531333 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9542 16:31:42.531433 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9543 16:31:42.531562 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9544 16:31:42.531898 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9545 16:31:42.538115 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9546 16:31:42.538421 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9547 16:31:42.538526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9548 16:31:42.538632 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9549 16:31:42.538736 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9550 16:31:42.539066 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9551 16:31:42.539251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9552 16:31:42.539367 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9553 16:31:42.539648 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9554 16:31:42.539744 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9555 16:31:42.539848 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9556 16:31:42.539936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9557 16:31:42.540268 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9558 16:31:42.540379 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9559 16:31:42.540484 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9560 16:31:42.540586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9561 16:31:42.540932 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9562 16:31:42.541041 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9563 16:31:42.541417 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9564 16:31:42.541523 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9565 16:31:42.541606 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9566 16:31:42.541915 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9567 16:31:42.542017 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9568 16:31:42.542106 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9569 16:31:42.547003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9570 16:31:42.547108 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9571 16:31:42.547188 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9572 16:31:42.547265 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9573 16:31:42.547540 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9574 16:31:42.547641 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9575 16:31:42.547722 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9576 16:31:42.547799 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9577 16:31:42.547889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9578 16:31:42.547968 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9579 16:31:42.548058 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9580 16:31:42.548149 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9581 16:31:42.548666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9582 16:31:42.548767 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9583 16:31:42.548846 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9584 16:31:42.549135 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9585 16:31:42.549236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9586 16:31:42.549317 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9587 16:31:42.549407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9588 16:31:42.549486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9589 16:31:42.549575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9590 16:31:42.549660 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9591 16:31:42.549751 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9592 16:31:42.550037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9593 16:31:42.554354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9594 16:31:42.554470 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9595 16:31:42.554554 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9596 16:31:42.554839 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9597 16:31:42.554952 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9598 16:31:42.555242 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9599 16:31:42.555343 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9600 16:31:42.555443 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9601 16:31:42.555535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9602 16:31:42.555822 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9603 16:31:42.555934 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9604 16:31:42.556027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9605 16:31:42.556320 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9606 16:31:42.556428 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9607 16:31:42.556734 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9608 16:31:42.556846 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9609 16:31:42.556952 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9610 16:31:42.557074 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9611 16:31:42.557185 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9612 16:31:42.557292 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9613 16:31:42.557623 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9614 16:31:42.557785 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9615 16:31:42.557888 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9616 16:31:42.558015 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9617 16:31:42.558370 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9618 16:31:42.558469 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9619 16:31:42.562090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9620 16:31:42.562521 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9621 16:31:42.562658 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9622 16:31:42.562794 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9623 16:31:42.562907 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9624 16:31:42.563037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9625 16:31:42.563384 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9626 16:31:42.563514 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9627 16:31:42.563665 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9628 16:31:42.563813 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9629 16:31:42.563965 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9630 16:31:42.564092 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9631 16:31:42.564238 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9632 16:31:42.564383 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9633 16:31:42.564798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9634 16:31:42.564922 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9635 16:31:42.565046 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9636 16:31:42.565188 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9637 16:31:42.565312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9638 16:31:42.565445 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9639 16:31:42.565590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9640 16:31:42.565702 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9641 16:31:42.565773 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9642 16:31:42.565846 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9643 16:31:42.581452 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9644 16:31:42.581842 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9645 16:31:42.581961 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9646 16:31:42.582088 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9647 16:31:42.582501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9648 16:31:42.582897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9649 16:31:42.582999 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9650 16:31:42.583081 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9651 16:31:42.583391 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9652 16:31:42.583492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9653 16:31:42.583573 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9654 16:31:42.583651 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9655 16:31:42.583959 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9656 16:31:42.584070 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9657 16:31:42.584163 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9658 16:31:42.584245 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9659 16:31:42.584361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9660 16:31:42.584668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9661 16:31:42.584769 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9662 16:31:42.584852 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9663 16:31:42.584932 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9664 16:31:42.585012 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9665 16:31:42.585106 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9666 16:31:42.585195 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9667 16:31:42.585275 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9668 16:31:42.585642 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9669 16:31:42.585754 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9670 16:31:42.585835 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9671 16:31:42.585928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9672 16:31:42.586008 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9673 16:31:42.590157 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9674 16:31:42.590425 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9675 16:31:42.590529 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9676 16:31:42.590822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9677 16:31:42.590922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9678 16:31:42.591017 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9679 16:31:42.591109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9680 16:31:42.591200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9681 16:31:42.591488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9682 16:31:42.591594 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9683 16:31:42.591698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9684 16:31:42.591992 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9685 16:31:42.592301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9686 16:31:42.592401 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9687 16:31:42.592497 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9688 16:31:42.592581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9689 16:31:42.592673 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9690 16:31:42.592956 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9691 16:31:42.593059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9692 16:31:42.593366 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9693 16:31:42.593470 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9694 16:31:42.593553 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9695 16:31:42.593632 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9696 16:31:42.593732 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9697 16:31:42.593991 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9698 16:31:42.598138 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9699 16:31:42.598451 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9700 16:31:42.598553 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9701 16:31:42.599001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9702 16:31:42.599107 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9703 16:31:42.599191 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9704 16:31:42.599430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9705 16:31:42.599531 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9706 16:31:42.599613 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9707 16:31:42.599706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9708 16:31:42.599788 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9709 16:31:42.599880 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9710 16:31:42.599973 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9711 16:31:42.600261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9712 16:31:42.600362 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9713 16:31:42.600459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9714 16:31:42.600552 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9715 16:31:42.600646 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9716 16:31:42.600933 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9717 16:31:42.601047 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9718 16:31:42.601142 arm64_sve-ptrace_Set_SVE_VL_4608 pass
9719 16:31:42.601434 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
9720 16:31:42.601535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
9721 16:31:42.601628 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
9722 16:31:42.601726 arm64_sve-ptrace_Set_SVE_VL_4624 pass
9723 16:31:42.602009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
9724 16:31:42.606353 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
9725 16:31:42.606502 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
9726 16:31:42.606782 arm64_sve-ptrace_Set_SVE_VL_4640 pass
9727 16:31:42.606925 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
9728 16:31:42.607242 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
9729 16:31:42.607352 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
9730 16:31:42.607444 arm64_sve-ptrace_Set_SVE_VL_4656 pass
9731 16:31:42.607546 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
9732 16:31:42.607832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
9733 16:31:42.607930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
9734 16:31:42.608097 arm64_sve-ptrace_Set_SVE_VL_4672 pass
9735 16:31:42.608219 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
9736 16:31:42.608312 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
9737 16:31:42.609110 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
9738 16:31:42.609207 arm64_sve-ptrace_Set_SVE_VL_4688 pass
9739 16:31:42.609297 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
9740 16:31:42.609383 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
9741 16:31:42.609471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
9742 16:31:42.609558 arm64_sve-ptrace_Set_SVE_VL_4704 pass
9743 16:31:42.609651 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
9744 16:31:42.609739 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
9745 16:31:42.609831 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
9746 16:31:42.609922 arm64_sve-ptrace_Set_SVE_VL_4720 pass
9747 16:31:42.610224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
9748 16:31:42.610330 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
9749 16:31:42.610420 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
9750 16:31:42.610507 arm64_sve-ptrace_Set_SVE_VL_4736 pass
9751 16:31:42.610593 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
9752 16:31:42.610678 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
9753 16:31:42.610765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
9754 16:31:42.610868 arm64_sve-ptrace_Set_SVE_VL_4752 pass
9755 16:31:42.610956 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
9756 16:31:42.611059 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
9757 16:31:42.611147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
9758 16:31:42.611236 arm64_sve-ptrace_Set_SVE_VL_4768 pass
9759 16:31:42.611337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
9760 16:31:42.611439 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
9761 16:31:42.611541 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
9762 16:31:42.611646 arm64_sve-ptrace_Set_SVE_VL_4784 pass
9763 16:31:42.612048 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
9764 16:31:42.612170 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
9765 16:31:42.612275 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
9766 16:31:42.612458 arm64_sve-ptrace_Set_SVE_VL_4800 pass
9767 16:31:42.612567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
9768 16:31:42.612669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
9769 16:31:42.612960 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
9770 16:31:42.622056 arm64_sve-ptrace_Set_SVE_VL_4816 pass
9771 16:31:42.622396 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
9772 16:31:42.622939 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
9773 16:31:42.623093 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
9774 16:31:42.623174 arm64_sve-ptrace_Set_SVE_VL_4832 pass
9775 16:31:42.623265 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
9776 16:31:42.623344 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
9777 16:31:42.623433 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
9778 16:31:42.623523 arm64_sve-ptrace_Set_SVE_VL_4848 pass
9779 16:31:42.623800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
9780 16:31:42.624136 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
9781 16:31:42.624244 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
9782 16:31:42.624325 arm64_sve-ptrace_Set_SVE_VL_4864 pass
9783 16:31:42.624692 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
9784 16:31:42.624794 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
9785 16:31:42.624876 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
9786 16:31:42.624966 arm64_sve-ptrace_Set_SVE_VL_4880 pass
9787 16:31:42.625058 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
9788 16:31:42.625345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
9789 16:31:42.625722 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
9790 16:31:42.625822 arm64_sve-ptrace_Set_SVE_VL_4896 pass
9791 16:31:42.625902 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
9792 16:31:42.625993 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
9793 16:31:42.630116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
9794 16:31:42.630481 arm64_sve-ptrace_Set_SVE_VL_4912 pass
9795 16:31:42.630600 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
9796 16:31:42.630723 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
9797 16:31:42.631029 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
9798 16:31:42.631141 arm64_sve-ptrace_Set_SVE_VL_4928 pass
9799 16:31:42.631251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
9800 16:31:42.631362 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
9801 16:31:42.631488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
9802 16:31:42.631583 arm64_sve-ptrace_Set_SVE_VL_4944 pass
9803 16:31:42.645416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
9804 16:31:42.645921 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
9805 16:31:42.646028 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
9806 16:31:42.646127 arm64_sve-ptrace_Set_SVE_VL_4960 pass
9807 16:31:42.646614 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
9808 16:31:42.646719 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
9809 16:31:42.646802 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
9810 16:31:42.646882 arm64_sve-ptrace_Set_SVE_VL_4976 pass
9811 16:31:42.647162 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
9812 16:31:42.647269 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
9813 16:31:42.647349 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
9814 16:31:42.647441 arm64_sve-ptrace_Set_SVE_VL_4992 pass
9815 16:31:42.647533 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
9816 16:31:42.647624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
9817 16:31:42.647717 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
9818 16:31:42.647808 arm64_sve-ptrace_Set_SVE_VL_5008 pass
9819 16:31:42.648160 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
9820 16:31:42.648266 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
9821 16:31:42.648361 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
9822 16:31:42.648453 arm64_sve-ptrace_Set_SVE_VL_5024 pass
9823 16:31:42.648756 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
9824 16:31:42.648875 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
9825 16:31:42.649207 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
9826 16:31:42.649318 arm64_sve-ptrace_Set_SVE_VL_5040 pass
9827 16:31:42.649614 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
9828 16:31:42.649727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
9829 16:31:42.649836 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
9830 16:31:42.649930 arm64_sve-ptrace_Set_SVE_VL_5056 pass
9831 16:31:42.650233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
9832 16:31:42.654068 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
9833 16:31:42.654392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
9834 16:31:42.654517 arm64_sve-ptrace_Set_SVE_VL_5072 pass
9835 16:31:42.654807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
9836 16:31:42.654919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
9837 16:31:42.655027 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
9838 16:31:42.655121 arm64_sve-ptrace_Set_SVE_VL_5088 pass
9839 16:31:42.655226 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
9840 16:31:42.655540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
9841 16:31:42.655651 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
9842 16:31:42.656026 arm64_sve-ptrace_Set_SVE_VL_5104 pass
9843 16:31:42.656139 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
9844 16:31:42.656412 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
9845 16:31:42.656519 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
9846 16:31:42.656825 arm64_sve-ptrace_Set_SVE_VL_5120 pass
9847 16:31:42.656938 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
9848 16:31:42.657030 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
9849 16:31:42.657135 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
9850 16:31:42.657465 arm64_sve-ptrace_Set_SVE_VL_5136 pass
9851 16:31:42.657698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
9852 16:31:42.657797 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
9853 16:31:42.658090 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
9854 16:31:42.658201 arm64_sve-ptrace_Set_SVE_VL_5152 pass
9855 16:31:42.658296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
9856 16:31:42.662585 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
9857 16:31:42.662711 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
9858 16:31:42.663081 arm64_sve-ptrace_Set_SVE_VL_5168 pass
9859 16:31:42.663191 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
9860 16:31:42.663285 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
9861 16:31:42.663619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
9862 16:31:42.663729 arm64_sve-ptrace_Set_SVE_VL_5184 pass
9863 16:31:42.663820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
9864 16:31:42.664118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
9865 16:31:42.664219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
9866 16:31:42.664303 arm64_sve-ptrace_Set_SVE_VL_5200 pass
9867 16:31:42.664400 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
9868 16:31:42.664803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
9869 16:31:42.665185 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
9870 16:31:42.665289 arm64_sve-ptrace_Set_SVE_VL_5216 pass
9871 16:31:42.665380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
9872 16:31:42.665478 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
9873 16:31:42.665572 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
9874 16:31:42.665903 arm64_sve-ptrace_Set_SVE_VL_5232 pass
9875 16:31:42.666008 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
9876 16:31:42.666108 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
9877 16:31:42.666200 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
9878 16:31:42.666295 arm64_sve-ptrace_Set_SVE_VL_5248 pass
9879 16:31:42.670216 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
9880 16:31:42.670539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
9881 16:31:42.670647 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
9882 16:31:42.670778 arm64_sve-ptrace_Set_SVE_VL_5264 pass
9883 16:31:42.670893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
9884 16:31:42.671235 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
9885 16:31:42.671348 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
9886 16:31:42.671471 arm64_sve-ptrace_Set_SVE_VL_5280 pass
9887 16:31:42.671590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
9888 16:31:42.671709 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
9889 16:31:42.671825 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
9890 16:31:42.672241 arm64_sve-ptrace_Set_SVE_VL_5296 pass
9891 16:31:42.672740 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
9892 16:31:42.673103 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
9893 16:31:42.673302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
9894 16:31:42.673405 arm64_sve-ptrace_Set_SVE_VL_5312 pass
9895 16:31:42.673510 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
9896 16:31:42.673617 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
9897 16:31:42.673733 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
9898 16:31:42.673848 arm64_sve-ptrace_Set_SVE_VL_5328 pass
9899 16:31:42.673974 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
9900 16:31:42.674071 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
9901 16:31:42.674141 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
9902 16:31:42.674203 arm64_sve-ptrace_Set_SVE_VL_5344 pass
9903 16:31:42.678156 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
9904 16:31:42.678484 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
9905 16:31:42.678606 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
9906 16:31:42.678735 arm64_sve-ptrace_Set_SVE_VL_5360 pass
9907 16:31:42.678848 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
9908 16:31:42.678978 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
9909 16:31:42.679110 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
9910 16:31:42.679240 arm64_sve-ptrace_Set_SVE_VL_5376 pass
9911 16:31:42.679369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
9912 16:31:42.679499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
9913 16:31:42.679826 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
9914 16:31:42.679933 arm64_sve-ptrace_Set_SVE_VL_5392 pass
9915 16:31:42.680051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
9916 16:31:42.680180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
9917 16:31:42.680542 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
9918 16:31:42.680651 arm64_sve-ptrace_Set_SVE_VL_5408 pass
9919 16:31:42.681014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
9920 16:31:42.681128 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
9921 16:31:42.681254 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
9922 16:31:42.681362 arm64_sve-ptrace_Set_SVE_VL_5424 pass
9923 16:31:42.681835 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
9924 16:31:42.682009 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
9925 16:31:42.682095 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
9926 16:31:42.682172 arm64_sve-ptrace_Set_SVE_VL_5440 pass
9927 16:31:42.682250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
9928 16:31:42.686158 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
9929 16:31:42.686689 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
9930 16:31:42.686862 arm64_sve-ptrace_Set_SVE_VL_5456 pass
9931 16:31:42.686957 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
9932 16:31:42.687065 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
9933 16:31:42.687388 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
9934 16:31:42.687508 arm64_sve-ptrace_Set_SVE_VL_5472 pass
9935 16:31:42.687619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
9936 16:31:42.687738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
9937 16:31:42.687968 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
9938 16:31:42.688071 arm64_sve-ptrace_Set_SVE_VL_5488 pass
9939 16:31:42.688170 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
9940 16:31:42.688293 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
9941 16:31:42.688431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
9942 16:31:42.688552 arm64_sve-ptrace_Set_SVE_VL_5504 pass
9943 16:31:42.688685 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
9944 16:31:42.688822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
9945 16:31:42.688961 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
9946 16:31:42.689084 arm64_sve-ptrace_Set_SVE_VL_5520 pass
9947 16:31:42.689491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
9948 16:31:42.689797 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
9949 16:31:42.689924 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
9950 16:31:42.690030 arm64_sve-ptrace_Set_SVE_VL_5536 pass
9951 16:31:42.690127 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
9952 16:31:42.694149 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
9953 16:31:42.694464 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
9954 16:31:42.694612 arm64_sve-ptrace_Set_SVE_VL_5552 pass
9955 16:31:42.694948 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
9956 16:31:42.695091 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
9957 16:31:42.695241 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
9958 16:31:42.695380 arm64_sve-ptrace_Set_SVE_VL_5568 pass
9959 16:31:42.695518 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
9960 16:31:42.695624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
9961 16:31:42.695733 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
9962 16:31:42.695810 arm64_sve-ptrace_Set_SVE_VL_5584 pass
9963 16:31:42.711006 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
9964 16:31:42.711350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
9965 16:31:42.711500 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
9966 16:31:42.711844 arm64_sve-ptrace_Set_SVE_VL_5600 pass
9967 16:31:42.711959 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
9968 16:31:42.712084 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
9969 16:31:42.712189 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
9970 16:31:42.712617 arm64_sve-ptrace_Set_SVE_VL_5616 pass
9971 16:31:42.712729 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
9972 16:31:42.712823 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
9973 16:31:42.712928 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
9974 16:31:42.713018 arm64_sve-ptrace_Set_SVE_VL_5632 pass
9975 16:31:42.713121 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
9976 16:31:42.713225 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
9977 16:31:42.713564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
9978 16:31:42.713691 arm64_sve-ptrace_Set_SVE_VL_5648 pass
9979 16:31:42.713986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
9980 16:31:42.718157 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
9981 16:31:42.718457 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
9982 16:31:42.718565 arm64_sve-ptrace_Set_SVE_VL_5664 pass
9983 16:31:42.718888 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
9984 16:31:42.718988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
9985 16:31:42.719084 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
9986 16:31:42.719558 arm64_sve-ptrace_Set_SVE_VL_5680 pass
9987 16:31:42.719659 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
9988 16:31:42.719742 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
9989 16:31:42.720003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
9990 16:31:42.720104 arm64_sve-ptrace_Set_SVE_VL_5696 pass
9991 16:31:42.720186 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
9992 16:31:42.720266 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
9993 16:31:42.720585 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
9994 16:31:42.720686 arm64_sve-ptrace_Set_SVE_VL_5712 pass
9995 16:31:42.720768 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
9996 16:31:42.720848 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
9997 16:31:42.721129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
9998 16:31:42.721231 arm64_sve-ptrace_Set_SVE_VL_5728 pass
9999 16:31:42.721316 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10000 16:31:42.721682 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10001 16:31:42.721784 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10002 16:31:42.721866 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10003 16:31:42.721947 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10004 16:31:42.722213 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10005 16:31:42.726401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10006 16:31:42.726513 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10007 16:31:42.726803 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10008 16:31:42.726911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10009 16:31:42.727205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10010 16:31:42.727309 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10011 16:31:42.727391 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10012 16:31:42.727659 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10013 16:31:42.727760 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10014 16:31:42.727840 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10015 16:31:42.728114 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10016 16:31:42.728215 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10017 16:31:42.728298 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10018 16:31:42.728391 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10019 16:31:42.728734 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10020 16:31:42.728839 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10021 16:31:42.728918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10022 16:31:42.729222 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10023 16:31:42.729323 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10024 16:31:42.729604 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10025 16:31:42.729712 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10026 16:31:42.729798 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10027 16:31:42.730077 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10028 16:31:42.730177 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10029 16:31:42.734301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10030 16:31:42.734428 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10031 16:31:42.734718 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10032 16:31:42.734821 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10033 16:31:42.734915 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10034 16:31:42.735317 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10035 16:31:42.735427 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10036 16:31:42.735510 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10037 16:31:42.735819 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10038 16:31:42.735945 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10039 16:31:42.736045 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10040 16:31:42.736162 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10041 16:31:42.736282 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10042 16:31:42.736389 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10043 16:31:42.736494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10044 16:31:42.736575 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10045 16:31:42.736953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10046 16:31:42.737072 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10047 16:31:42.737181 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10048 16:31:42.737286 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10049 16:31:42.737602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10050 16:31:42.737729 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10051 16:31:42.737849 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10052 16:31:42.737957 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10053 16:31:42.738073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10054 16:31:42.738194 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10055 16:31:42.738301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10056 16:31:42.738393 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10057 16:31:42.738521 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10058 16:31:42.738640 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10059 16:31:42.738776 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10060 16:31:42.738904 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10061 16:31:42.739033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10062 16:31:42.739130 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10063 16:31:42.739255 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10064 16:31:42.739751 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10065 16:31:42.739864 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10066 16:31:42.739965 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10067 16:31:42.740078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10068 16:31:42.740192 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10069 16:31:42.740303 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10070 16:31:42.740628 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10071 16:31:42.740732 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10072 16:31:42.740816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10073 16:31:42.740912 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10074 16:31:42.740995 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10075 16:31:42.746185 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10076 16:31:42.746299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10077 16:31:42.746603 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10078 16:31:42.746695 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10079 16:31:42.746809 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10080 16:31:42.746934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10081 16:31:42.747037 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10082 16:31:42.747163 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10083 16:31:42.747502 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10084 16:31:42.747633 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10085 16:31:42.747765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10086 16:31:42.747861 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10087 16:31:42.747983 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10088 16:31:42.748124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10089 16:31:42.748259 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10090 16:31:42.748370 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10091 16:31:42.748480 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10092 16:31:42.748608 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10093 16:31:42.748714 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10094 16:31:42.748817 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10095 16:31:42.748942 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10096 16:31:42.749047 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10097 16:31:42.749158 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10098 16:31:42.749270 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10099 16:31:42.749389 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10100 16:31:42.749500 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10101 16:31:42.749606 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10102 16:31:42.749743 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10103 16:31:42.749847 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10104 16:31:42.749968 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10105 16:31:42.754171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10106 16:31:42.754286 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10107 16:31:42.754592 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10108 16:31:42.754696 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10109 16:31:42.754789 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10110 16:31:42.754906 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10111 16:31:42.755011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10112 16:31:42.755145 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10113 16:31:42.755246 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10114 16:31:42.755367 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10115 16:31:42.755473 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10116 16:31:42.755593 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10117 16:31:42.755721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10118 16:31:42.755843 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10119 16:31:42.755967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10120 16:31:42.756085 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10121 16:31:42.756207 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10122 16:31:42.756326 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10123 16:31:42.774364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10124 16:31:42.774707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10125 16:31:42.774824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10126 16:31:42.775146 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10127 16:31:42.775264 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10128 16:31:42.775350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10129 16:31:42.775443 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10130 16:31:42.775537 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10131 16:31:42.775632 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10132 16:31:42.775930 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10133 16:31:42.776032 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10134 16:31:42.776112 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10135 16:31:42.776204 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10136 16:31:42.776284 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10137 16:31:42.776374 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10138 16:31:42.776465 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10139 16:31:42.776557 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10140 16:31:42.776852 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10141 16:31:42.776957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10142 16:31:42.777052 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10143 16:31:42.777131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10144 16:31:42.777419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10145 16:31:42.777524 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10146 16:31:42.777620 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10147 16:31:42.777710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10148 16:31:42.777803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10149 16:31:42.777883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10150 16:31:42.782030 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10151 16:31:42.782393 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10152 16:31:42.782495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10153 16:31:42.782596 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10154 16:31:42.782699 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10155 16:31:42.782994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10156 16:31:42.783110 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10157 16:31:42.783401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10158 16:31:42.783504 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10159 16:31:42.783789 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10160 16:31:42.783907 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10161 16:31:42.783991 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10162 16:31:42.784084 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10163 16:31:42.784185 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10164 16:31:42.784645 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10165 16:31:42.784951 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10166 16:31:42.785055 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10167 16:31:42.785138 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10168 16:31:42.785217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10169 16:31:42.785484 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10170 16:31:42.785585 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10171 16:31:42.785676 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10172 16:31:42.785757 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10173 16:31:42.786036 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10174 16:31:42.786139 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10175 16:31:42.786220 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10176 16:31:42.786300 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10177 16:31:42.786380 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10178 16:31:42.790291 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10179 16:31:42.790621 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10180 16:31:42.790722 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10181 16:31:42.791030 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10182 16:31:42.791143 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10183 16:31:42.791234 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10184 16:31:42.791330 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10185 16:31:42.791613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10186 16:31:42.791724 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10187 16:31:42.791831 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10188 16:31:42.791945 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10189 16:31:42.792083 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10190 16:31:42.792201 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10191 16:31:42.792340 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10192 16:31:42.792446 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10193 16:31:42.792585 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10194 16:31:42.792676 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10195 16:31:42.792804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10196 16:31:42.792932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10197 16:31:42.793064 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10198 16:31:42.793196 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10199 16:31:42.793562 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10200 16:31:42.793690 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10201 16:31:42.798074 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10202 16:31:42.798382 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10203 16:31:42.798520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10204 16:31:42.798862 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10205 16:31:42.799191 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10206 16:31:42.799325 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10207 16:31:42.799645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10208 16:31:42.799978 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10209 16:31:42.800099 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10210 16:31:42.800216 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10211 16:31:42.800544 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10212 16:31:42.800838 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10213 16:31:42.800956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10214 16:31:42.801259 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10215 16:31:42.801371 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10216 16:31:42.801678 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10217 16:31:42.801999 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10218 16:31:42.802319 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10219 16:31:42.802418 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10220 16:31:42.806076 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10221 16:31:42.806380 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10222 16:31:42.806658 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10223 16:31:42.806756 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10224 16:31:42.806852 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10225 16:31:42.807153 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10226 16:31:42.807455 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10227 16:31:42.807567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10228 16:31:42.807661 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10229 16:31:42.807948 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10230 16:31:42.808060 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10231 16:31:42.808153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10232 16:31:42.808454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10233 16:31:42.808755 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10234 16:31:42.808856 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10235 16:31:42.809136 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10236 16:31:42.809248 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10237 16:31:42.809537 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10238 16:31:42.809655 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10239 16:31:42.814043 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10240 16:31:42.814359 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10241 16:31:42.814706 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10242 16:31:42.814843 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10243 16:31:42.815100 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10244 16:31:42.815410 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10245 16:31:42.815782 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10246 16:31:42.815896 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10247 16:31:42.816021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10248 16:31:42.816366 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10249 16:31:42.816735 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10250 16:31:42.817068 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10251 16:31:42.817430 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10252 16:31:42.817777 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10253 16:31:42.817904 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10254 16:31:42.818223 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10255 16:31:42.818306 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10256 16:31:42.822424 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10257 16:31:42.822685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10258 16:31:42.822784 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10259 16:31:42.823084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10260 16:31:42.823185 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10261 16:31:42.823281 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10262 16:31:42.823593 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10263 16:31:42.823699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10264 16:31:42.823991 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10265 16:31:42.824091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10266 16:31:42.824187 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10267 16:31:42.824280 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10268 16:31:42.824586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10269 16:31:42.824704 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10270 16:31:42.824994 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10271 16:31:42.825301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10272 16:31:42.825422 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10273 16:31:42.825697 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10274 16:31:42.825822 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10275 16:31:42.830096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10276 16:31:42.830405 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10277 16:31:42.830536 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10278 16:31:42.830852 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10279 16:31:42.831173 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10280 16:31:42.831280 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10281 16:31:42.831586 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10282 16:31:42.831693 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10283 16:31:42.842410 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10284 16:31:42.842736 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10285 16:31:42.843076 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10286 16:31:42.843182 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10287 16:31:42.843303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10288 16:31:42.843630 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10289 16:31:42.843735 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10290 16:31:42.844045 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10291 16:31:42.844157 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10292 16:31:42.844286 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10293 16:31:42.844395 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10294 16:31:42.844754 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10295 16:31:42.844858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10296 16:31:42.845152 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10297 16:31:42.845257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10298 16:31:42.845384 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10299 16:31:42.845493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10300 16:31:42.845630 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10301 16:31:42.845776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10302 16:31:42.845895 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10303 16:31:42.850362 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10304 16:31:42.850673 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10305 16:31:42.851000 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10306 16:31:42.851125 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10307 16:31:42.851434 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10308 16:31:42.851577 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10309 16:31:42.851709 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10310 16:31:42.851837 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10311 16:31:42.852167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10312 16:31:42.852303 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10313 16:31:42.852431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10314 16:31:42.852552 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10315 16:31:42.852866 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10316 16:31:42.852971 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10317 16:31:42.853080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10318 16:31:42.853401 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10319 16:31:42.853506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10320 16:31:42.853809 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10321 16:31:42.853917 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10322 16:31:42.858031 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10323 16:31:42.858350 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10324 16:31:42.858636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10325 16:31:42.858756 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10326 16:31:42.859063 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10327 16:31:42.859164 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10328 16:31:42.859247 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10329 16:31:42.859494 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10330 16:31:42.859598 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10331 16:31:42.859680 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10332 16:31:42.859965 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10333 16:31:42.860067 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10334 16:31:42.860148 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10335 16:31:42.860226 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10336 16:31:42.860317 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10337 16:31:42.860409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10338 16:31:42.860743 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10339 16:31:42.860861 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10340 16:31:42.861152 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10341 16:31:42.865940 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10342 16:31:42.866041 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10343 16:31:42.866125 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10344 16:31:42.866205 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10345 16:31:42.866284 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10346 16:31:42.866364 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10347 16:31:42.866444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10348 16:31:42.866525 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10349 16:31:42.866605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10350 16:31:42.866685 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10351 16:31:42.866765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10352 16:31:42.866846 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10353 16:31:42.866925 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10354 16:31:42.867003 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10355 16:31:42.867082 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10356 16:31:42.867160 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10357 16:31:42.867239 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10358 16:31:42.867317 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10359 16:31:42.867396 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10360 16:31:42.867475 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10361 16:31:42.867552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10362 16:31:42.867629 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10363 16:31:42.867707 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10364 16:31:42.867783 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10365 16:31:42.867860 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10366 16:31:42.867937 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10367 16:31:42.868015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10368 16:31:42.868091 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10369 16:31:42.868169 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10370 16:31:42.868248 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10371 16:31:42.868326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10372 16:31:42.868404 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10373 16:31:42.868482 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10374 16:31:42.868559 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10375 16:31:42.868638 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10376 16:31:42.868718 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10377 16:31:42.877291 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10378 16:31:42.877836 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10379 16:31:42.878336 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10380 16:31:42.878637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10381 16:31:42.878947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10382 16:31:42.879055 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10383 16:31:42.879346 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10384 16:31:42.879682 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10385 16:31:42.879795 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10386 16:31:42.880155 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10387 16:31:42.880300 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10388 16:31:42.880835 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10389 16:31:42.881157 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10390 16:31:42.881450 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10391 16:31:42.881761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10392 16:31:42.882098 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10393 16:31:42.882416 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10394 16:31:42.882544 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10395 16:31:42.882674 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10396 16:31:42.883181 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10397 16:31:42.883530 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10398 16:31:42.883861 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10399 16:31:42.884172 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10400 16:31:42.884466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10401 16:31:42.884591 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10402 16:31:42.884749 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10403 16:31:42.885157 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10404 16:31:42.885470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10405 16:31:42.885600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10406 16:31:42.890224 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10407 16:31:42.890893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10408 16:31:42.891005 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10409 16:31:42.891116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10410 16:31:42.891420 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10411 16:31:42.891530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10412 16:31:42.891670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10413 16:31:42.891795 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10414 16:31:42.892163 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10415 16:31:42.892485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10416 16:31:42.892793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10417 16:31:42.893132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10418 16:31:42.893439 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10419 16:31:42.894008 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10420 16:31:42.901983 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10421 16:31:42.902290 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10422 16:31:42.902430 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10423 16:31:42.902555 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10424 16:31:42.902881 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10425 16:31:42.903016 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10426 16:31:42.903338 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10427 16:31:42.903474 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10428 16:31:42.903603 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10429 16:31:42.903919 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10430 16:31:42.904055 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10431 16:31:42.904593 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10432 16:31:42.904912 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10433 16:31:42.905428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10434 16:31:42.905695 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10435 16:31:42.910026 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10436 16:31:42.910721 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10437 16:31:42.911052 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10438 16:31:42.911150 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10439 16:31:42.911394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10440 16:31:42.911492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10441 16:31:42.911728 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10442 16:31:42.912057 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10443 16:31:42.912646 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10444 16:31:42.912946 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10445 16:31:42.913245 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10446 16:31:42.913342 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10447 16:31:42.913423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10448 16:31:42.913514 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10449 16:31:42.913606 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10450 16:31:42.913706 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10451 16:31:42.913999 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10452 16:31:42.918147 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10453 16:31:42.918634 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10454 16:31:42.918732 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10455 16:31:42.919007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10456 16:31:42.919107 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10457 16:31:42.919188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10458 16:31:42.919265 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10459 16:31:42.919355 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10460 16:31:42.919433 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10461 16:31:42.919524 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10462 16:31:42.919808 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10463 16:31:42.919906 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10464 16:31:42.920000 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10465 16:31:42.920091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10466 16:31:42.920188 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10467 16:31:42.920475 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10468 16:31:42.920830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10469 16:31:42.920929 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10470 16:31:42.921221 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10471 16:31:42.921324 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10472 16:31:42.921405 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10473 16:31:42.921495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10474 16:31:42.921586 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10475 16:31:42.921685 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10476 16:31:42.921975 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10477 16:31:42.926389 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10478 16:31:42.926504 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10479 16:31:42.926598 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10480 16:31:42.926897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10481 16:31:42.927000 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10482 16:31:42.927510 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10483 16:31:42.927609 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10484 16:31:42.927689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10485 16:31:42.927766 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10486 16:31:42.928018 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10487 16:31:42.928116 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10488 16:31:42.928196 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10489 16:31:42.928272 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10490 16:31:42.928364 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10491 16:31:42.928455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10492 16:31:42.928544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10493 16:31:42.928635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10494 16:31:42.928725 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10495 16:31:42.928815 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10496 16:31:42.929101 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10497 16:31:42.929217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10498 16:31:42.929310 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10499 16:31:42.929603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10500 16:31:42.929713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10501 16:31:42.930022 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10502 16:31:42.930125 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10503 16:31:42.930218 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10504 16:31:42.930297 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10505 16:31:42.930592 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10506 16:31:42.930695 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10507 16:31:42.930774 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10508 16:31:42.930870 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10509 16:31:42.930949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10510 16:31:42.938021 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10511 16:31:42.938688 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10512 16:31:42.938803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10513 16:31:42.938886 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10514 16:31:42.939175 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10515 16:31:42.939478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10516 16:31:42.939784 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10517 16:31:42.940085 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10518 16:31:42.940427 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10519 16:31:42.940560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10520 16:31:42.940902 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10521 16:31:42.941035 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10522 16:31:42.941373 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10523 16:31:42.941502 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10524 16:31:42.941863 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10525 16:31:42.946133 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10526 16:31:42.946507 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10527 16:31:42.946639 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10528 16:31:42.946773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10529 16:31:42.946901 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10530 16:31:42.947233 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10531 16:31:42.947354 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10532 16:31:42.947741 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10533 16:31:42.947841 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10534 16:31:42.947926 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10535 16:31:42.948284 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10536 16:31:42.948391 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10537 16:31:42.948483 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10538 16:31:42.948573 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10539 16:31:42.948868 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10540 16:31:42.948957 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10541 16:31:42.949022 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10542 16:31:42.949094 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10543 16:31:42.949356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10544 16:31:42.949448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10545 16:31:42.949514 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10546 16:31:42.949587 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10547 16:31:42.949863 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10548 16:31:42.949960 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10549 16:31:42.950033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10550 16:31:42.950095 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10551 16:31:42.954326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10552 16:31:42.954841 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10553 16:31:42.954976 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10554 16:31:42.955319 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10555 16:31:42.955422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10556 16:31:42.955708 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10557 16:31:42.956030 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10558 16:31:42.956134 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10559 16:31:42.956228 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10560 16:31:42.956468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10561 16:31:42.956566 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10562 16:31:42.956853 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10563 16:31:42.956951 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10564 16:31:42.957043 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10565 16:31:42.957526 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10566 16:31:42.957633 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10567 16:31:42.957734 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10568 16:31:42.958031 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10569 16:31:42.958136 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10570 16:31:42.958228 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10571 16:31:42.958561 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10572 16:31:42.958665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10573 16:31:42.958793 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10574 16:31:42.958922 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10575 16:31:42.959352 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10576 16:31:42.959472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10577 16:31:42.959600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10578 16:31:42.959734 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10579 16:31:42.960122 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10580 16:31:42.960394 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10581 16:31:42.960696 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10582 16:31:42.960820 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10583 16:31:42.960937 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10584 16:31:42.961066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10585 16:31:42.961187 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10586 16:31:42.961326 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10587 16:31:42.961447 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10588 16:31:42.961576 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10589 16:31:42.961728 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10590 16:31:42.961862 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10591 16:31:42.961957 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10592 16:31:42.970013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10593 16:31:42.970383 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10594 16:31:42.970503 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10595 16:31:42.970599 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10596 16:31:42.970913 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10597 16:31:42.971257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10598 16:31:42.971391 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10599 16:31:42.971747 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10600 16:31:42.972048 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10601 16:31:42.972469 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10602 16:31:42.972767 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10603 16:31:42.975873 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10604 16:31:42.975986 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10605 16:31:42.976488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10606 16:31:42.976600 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10607 16:31:42.976734 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10608 16:31:42.976867 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10609 16:31:42.977205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10610 16:31:42.977344 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10611 16:31:42.977681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10612 16:31:42.977790 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10613 16:31:42.977894 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10614 16:31:42.978365 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10615 16:31:42.978464 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10616 16:31:42.978753 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10617 16:31:42.978864 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10618 16:31:42.979145 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10619 16:31:42.979255 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10620 16:31:42.979349 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10621 16:31:42.979635 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10622 16:31:42.979732 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10623 16:31:42.979827 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10624 16:31:42.980134 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10625 16:31:42.980427 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10626 16:31:42.980550 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10627 16:31:42.980689 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10628 16:31:42.981006 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10629 16:31:42.981121 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10630 16:31:42.981217 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10631 16:31:42.981311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10632 16:31:42.981588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10633 16:31:42.981907 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10634 16:31:42.986063 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10635 16:31:42.986405 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10636 16:31:42.986517 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10637 16:31:42.986814 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10638 16:31:42.986913 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10639 16:31:42.987007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10640 16:31:42.987296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10641 16:31:42.987407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10642 16:31:42.987501 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10643 16:31:42.987794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10644 16:31:42.987905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10645 16:31:42.988198 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10646 16:31:42.988296 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10647 16:31:42.988604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10648 16:31:42.988712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10649 16:31:42.988840 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10650 16:31:42.988987 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10651 16:31:42.989118 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10652 16:31:42.989454 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10653 16:31:42.989576 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10654 16:31:42.989694 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10655 16:31:42.994126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10656 16:31:42.994514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10657 16:31:42.995970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10658 16:31:42.996077 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10659 16:31:42.996159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10660 16:31:42.996238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10661 16:31:42.996317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10662 16:31:42.996395 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10663 16:31:42.996473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10664 16:31:42.996552 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10665 16:31:42.996629 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10666 16:31:42.996902 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10667 16:31:42.997004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10668 16:31:42.997099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10669 16:31:42.997180 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10670 16:31:42.997465 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10671 16:31:42.997578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10672 16:31:42.997871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10673 16:31:43.006033 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10674 16:31:43.006335 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10675 16:31:43.006640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10676 16:31:43.006953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10677 16:31:43.007326 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10678 16:31:43.007654 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10679 16:31:43.007979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10680 16:31:43.008342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10681 16:31:43.008636 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10682 16:31:43.008765 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10683 16:31:43.009076 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10684 16:31:43.009404 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10685 16:31:43.009707 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10686 16:31:43.010058 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10687 16:31:43.014133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10688 16:31:43.014502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10689 16:31:43.014921 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10690 16:31:43.015029 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10691 16:31:43.015125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10692 16:31:43.015416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10693 16:31:43.015522 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10694 16:31:43.015823 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10695 16:31:43.015924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10696 16:31:43.016020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10697 16:31:43.016112 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10698 16:31:43.016399 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10699 16:31:43.016516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10700 16:31:43.016695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10701 16:31:43.017060 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10702 16:31:43.017162 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10703 16:31:43.017257 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10704 16:31:43.017546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10705 16:31:43.017863 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10706 16:31:43.017968 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10707 16:31:43.018064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10708 16:31:43.018348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10709 16:31:43.022172 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10710 16:31:43.022503 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10711 16:31:43.022610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10712 16:31:43.022940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10713 16:31:43.023269 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10714 16:31:43.023389 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10715 16:31:43.023513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10716 16:31:43.023844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10717 16:31:43.024248 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10718 16:31:43.024512 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
10719 16:31:43.024605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
10720 16:31:43.024935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
10721 16:31:43.025076 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
10722 16:31:43.025197 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
10723 16:31:43.025518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
10724 16:31:43.025879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
10725 16:31:43.030128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
10726 16:31:43.030465 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
10727 16:31:43.030607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
10728 16:31:43.031125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
10729 16:31:43.031635 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
10730 16:31:43.031759 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
10731 16:31:43.031899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
10732 16:31:43.032198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
10733 16:31:43.032305 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
10734 16:31:43.032415 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
10735 16:31:43.032517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
10736 16:31:43.033020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
10737 16:31:43.033130 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
10738 16:31:43.033433 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
10739 16:31:43.033562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
10740 16:31:43.041856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
10741 16:31:43.042584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
10742 16:31:43.042907 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
10743 16:31:43.043192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
10744 16:31:43.043493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
10745 16:31:43.043802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
10746 16:31:43.043905 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
10747 16:31:43.044215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
10748 16:31:43.044319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
10749 16:31:43.044402 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
10750 16:31:43.044685 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
10751 16:31:43.044791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
10752 16:31:43.044875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
10753 16:31:43.044968 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
10754 16:31:43.045268 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
10755 16:31:43.045585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
10756 16:31:43.045898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
10757 16:31:43.050105 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
10758 16:31:43.050616 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
10759 16:31:43.050755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
10760 16:31:43.050878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
10761 16:31:43.051196 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
10762 16:31:43.051316 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
10763 16:31:43.051426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
10764 16:31:43.051740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
10765 16:31:43.052079 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
10766 16:31:43.052389 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
10767 16:31:43.052496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
10768 16:31:43.052613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
10769 16:31:43.052720 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
10770 16:31:43.052939 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
10771 16:31:43.053458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
10772 16:31:43.053816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
10773 16:31:43.054149 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
10774 16:31:43.058060 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
10775 16:31:43.058380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
10776 16:31:43.058695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
10777 16:31:43.058796 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
10778 16:31:43.059068 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
10779 16:31:43.059189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
10780 16:31:43.059301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
10781 16:31:43.059428 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
10782 16:31:43.059889 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
10783 16:31:43.060029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
10784 16:31:43.060352 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
10785 16:31:43.060460 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
10786 16:31:43.060584 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
10787 16:31:43.060872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
10788 16:31:43.060987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
10789 16:31:43.061341 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
10790 16:31:43.061483 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
10791 16:31:43.061592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
10792 16:31:43.061685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
10793 16:31:43.062073 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
10794 16:31:43.062172 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
10795 16:31:43.066188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
10796 16:31:43.066547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
10797 16:31:43.066890 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
10798 16:31:43.067006 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
10799 16:31:43.067276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
10800 16:31:43.067410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
10801 16:31:43.067758 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
10802 16:31:43.068107 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
10803 16:31:43.068542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
10804 16:31:43.068697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
10805 16:31:43.069182 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
10806 16:31:43.069272 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
10807 16:31:43.069364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
10808 16:31:43.069696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
10809 16:31:43.070134 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
10810 16:31:43.070222 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
10811 16:31:43.074118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
10812 16:31:43.075068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
10813 16:31:43.075384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
10814 16:31:43.075497 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
10815 16:31:43.076584 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
10816 16:31:43.076856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
10817 16:31:43.076960 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
10818 16:31:43.077047 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
10819 16:31:43.077130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
10820 16:31:43.077227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
10821 16:31:43.077571 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
10822 16:31:43.077763 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
10823 16:31:43.077956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
10824 16:31:43.078093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
10825 16:31:43.082119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
10826 16:31:43.082619 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
10827 16:31:43.082754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
10828 16:31:43.083276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
10829 16:31:43.083600 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
10830 16:31:43.083725 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
10831 16:31:43.083994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
10832 16:31:43.084345 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
10833 16:31:43.084694 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
10834 16:31:43.084821 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
10835 16:31:43.085146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
10836 16:31:43.085274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
10837 16:31:43.085850 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
10838 16:31:43.085975 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
10839 16:31:43.090590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
10840 16:31:43.090712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
10841 16:31:43.090971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
10842 16:31:43.091243 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
10843 16:31:43.091353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
10844 16:31:43.091664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
10845 16:31:43.092007 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
10846 16:31:43.092119 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
10847 16:31:43.092210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
10848 16:31:43.092314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
10849 16:31:43.092678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
10850 16:31:43.092783 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
10851 16:31:43.092890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
10852 16:31:43.093198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
10853 16:31:43.093324 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
10854 16:31:43.093665 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
10855 16:31:43.093775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
10856 16:31:43.093883 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
10857 16:31:43.094194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
10858 16:31:43.102055 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
10859 16:31:43.102417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
10860 16:31:43.102729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
10861 16:31:43.103053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
10862 16:31:43.103170 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
10863 16:31:43.103468 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
10864 16:31:43.103570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
10865 16:31:43.104044 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
10866 16:31:43.104214 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
10867 16:31:43.104468 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
10868 16:31:43.104574 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
10869 16:31:43.104656 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
10870 16:31:43.104734 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
10871 16:31:43.104824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
10872 16:31:43.105187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
10873 16:31:43.105291 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
10874 16:31:43.105372 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
10875 16:31:43.105452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
10876 16:31:43.110182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
10877 16:31:43.110499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
10878 16:31:43.110773 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
10879 16:31:43.111309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
10880 16:31:43.111649 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
10881 16:31:43.111956 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
10882 16:31:43.112060 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
10883 16:31:43.112352 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
10884 16:31:43.112672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
10885 16:31:43.112983 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
10886 16:31:43.113082 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
10887 16:31:43.113390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
10888 16:31:43.113490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
10889 16:31:43.113808 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
10890 16:31:43.114084 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
10891 16:31:43.114193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
10892 16:31:43.118065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
10893 16:31:43.118954 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
10894 16:31:43.119263 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
10895 16:31:43.119375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
10896 16:31:43.119667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
10897 16:31:43.119975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
10898 16:31:43.120090 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
10899 16:31:43.120185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
10900 16:31:43.120482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
10901 16:31:43.120975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
10902 16:31:43.121321 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
10903 16:31:43.121443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
10904 16:31:43.121800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
10905 16:31:43.126110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
10906 16:31:43.126418 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
10907 16:31:43.126727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
10908 16:31:43.127050 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
10909 16:31:43.127427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
10910 16:31:43.127551 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
10911 16:31:43.127861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
10912 16:31:43.127974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
10913 16:31:43.128113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
10914 16:31:43.128248 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
10915 16:31:43.128598 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
10916 16:31:43.128741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
10917 16:31:43.129103 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
10918 16:31:43.129236 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
10919 16:31:43.129369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
10920 16:31:43.129505 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
10921 16:31:43.129823 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
10922 16:31:43.129959 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
10923 16:31:43.134164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
10924 16:31:43.134498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
10925 16:31:43.134813 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
10926 16:31:43.135157 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
10927 16:31:43.135522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
10928 16:31:43.135845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
10929 16:31:43.135979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
10930 16:31:43.136324 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
10931 16:31:43.136667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
10932 16:31:43.137007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
10933 16:31:43.137125 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
10934 16:31:43.137411 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
10935 16:31:43.137702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
10936 16:31:43.138010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
10937 16:31:43.142482 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
10938 16:31:43.142787 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
10939 16:31:43.142900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
10940 16:31:43.142994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
10941 16:31:43.143495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
10942 16:31:43.143965 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
10943 16:31:43.144284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
10944 16:31:43.144397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
10945 16:31:43.144727 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
10946 16:31:43.144845 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
10947 16:31:43.145151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
10948 16:31:43.145466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
10949 16:31:43.145762 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
10950 16:31:43.145868 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
10951 16:31:43.146200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
10952 16:31:43.146300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
10953 16:31:43.150062 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
10954 16:31:43.150563 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
10955 16:31:43.150677 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
10956 16:31:43.151190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
10957 16:31:43.151291 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
10958 16:31:43.151385 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
10959 16:31:43.151708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
10960 16:31:43.152045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
10961 16:31:43.152146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
10962 16:31:43.152443 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
10963 16:31:43.152543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
10964 16:31:43.152637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
10965 16:31:43.152944 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
10966 16:31:43.153265 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
10967 16:31:43.153795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
10968 16:31:43.154168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
10969 16:31:43.158086 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
10970 16:31:43.158622 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
10971 16:31:43.158931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
10972 16:31:43.159034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
10973 16:31:43.159345 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
10974 16:31:43.159472 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
10975 16:31:43.159799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
10976 16:31:43.160130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
10977 16:31:43.160238 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
10978 16:31:43.160544 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
10979 16:31:43.160875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
10980 16:31:43.161391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
10981 16:31:43.161713 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
10982 16:31:43.162055 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
10983 16:31:43.166241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
10984 16:31:43.166555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
10985 16:31:43.166896 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
10986 16:31:43.167001 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
10987 16:31:43.167095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
10988 16:31:43.167434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
10989 16:31:43.167541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
10990 16:31:43.167840 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
10991 16:31:43.167948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
10992 16:31:43.168433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
10993 16:31:43.168703 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
10994 16:31:43.168795 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
10995 16:31:43.168904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
10996 16:31:43.168995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
10997 16:31:43.169100 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
10998 16:31:43.169205 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
10999 16:31:43.169513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11000 16:31:43.169621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11001 16:31:43.169734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11002 16:31:43.170034 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11003 16:31:43.170146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11004 16:31:43.170459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11005 16:31:43.170572 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11006 16:31:43.170678 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11007 16:31:43.170983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11008 16:31:43.171125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11009 16:31:43.171232 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11010 16:31:43.178745 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11011 16:31:43.179059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11012 16:31:43.179167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11013 16:31:43.179276 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11014 16:31:43.179384 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11015 16:31:43.179492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11016 16:31:43.179796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11017 16:31:43.179947 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11018 16:31:43.180068 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11019 16:31:43.180379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11020 16:31:43.180740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11021 16:31:43.180862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11022 16:31:43.180971 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11023 16:31:43.181300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11024 16:31:43.181623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11025 16:31:43.181753 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11026 16:31:43.186223 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11027 16:31:43.186734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11028 16:31:43.186982 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11029 16:31:43.187075 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11030 16:31:43.187354 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11031 16:31:43.187482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11032 16:31:43.187839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11033 16:31:43.187955 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11034 16:31:43.188070 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11035 16:31:43.188289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11036 16:31:43.188417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11037 16:31:43.188565 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11038 16:31:43.188699 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11039 16:31:43.188826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11040 16:31:43.188953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11041 16:31:43.189317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11042 16:31:43.189615 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11043 16:31:43.189726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11044 16:31:43.190009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11045 16:31:43.190110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11046 16:31:43.194392 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11047 16:31:43.194507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11048 16:31:43.194797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11049 16:31:43.195120 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11050 16:31:43.195219 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11051 16:31:43.195519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11052 16:31:43.195620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11053 16:31:43.195910 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11054 16:31:43.196024 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11055 16:31:43.196119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11056 16:31:43.196212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11057 16:31:43.196499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11058 16:31:43.196613 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11059 16:31:43.196895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11060 16:31:43.197009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11061 16:31:43.197300 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11062 16:31:43.197414 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11063 16:31:43.197703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11064 16:31:43.197817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11065 16:31:43.198107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11066 16:31:43.202370 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11067 16:31:43.202490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11068 16:31:43.202787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11069 16:31:43.202929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11070 16:31:43.203063 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11071 16:31:43.203402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11072 16:31:43.203528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11073 16:31:43.203661 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11074 16:31:43.203994 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11075 16:31:43.204127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11076 16:31:43.204461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11077 16:31:43.204596 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11078 16:31:43.204727 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11079 16:31:43.205057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11080 16:31:43.205193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11081 16:31:43.205525 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11082 16:31:43.205653 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11083 16:31:43.205787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11084 16:31:43.206088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11085 16:31:43.210084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11086 16:31:43.210379 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11087 16:31:43.210492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11088 16:31:43.210775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11089 16:31:43.210892 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11090 16:31:43.211178 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11091 16:31:43.211279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11092 16:31:43.211372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11093 16:31:43.211701 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11094 16:31:43.211802 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11095 16:31:43.212147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11096 16:31:43.212248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11097 16:31:43.212534 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11098 16:31:43.212637 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11099 16:31:43.212949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11100 16:31:43.213251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11101 16:31:43.213352 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11102 16:31:43.213632 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11103 16:31:43.213741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11104 16:31:43.213838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11105 16:31:43.218122 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11106 16:31:43.218450 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11107 16:31:43.218591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11108 16:31:43.218927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11109 16:31:43.219054 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11110 16:31:43.219435 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11111 16:31:43.219788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11112 16:31:43.219901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11113 16:31:43.220239 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11114 16:31:43.220349 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11115 16:31:43.220660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11116 16:31:43.220786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11117 16:31:43.221084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11118 16:31:43.221214 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11119 16:31:43.221537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11120 16:31:43.221856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11121 16:31:43.222167 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11122 16:31:43.230063 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11123 16:31:43.230376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11124 16:31:43.230695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11125 16:31:43.231020 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11126 16:31:43.231148 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11127 16:31:43.231459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11128 16:31:43.231792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11129 16:31:43.232129 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11130 16:31:43.232306 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11131 16:31:43.232621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11132 16:31:43.232770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11133 16:31:43.233255 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11134 16:31:43.233592 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11135 16:31:43.233706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11136 16:31:43.233818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11137 16:31:43.234142 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11138 16:31:43.238098 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11139 16:31:43.238440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11140 16:31:43.238779 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11141 16:31:43.239121 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11142 16:31:43.239669 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11143 16:31:43.240512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11144 16:31:43.240790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11145 16:31:43.241119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11146 16:31:43.241239 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11147 16:31:43.241348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11148 16:31:43.241653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11149 16:31:43.241975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11150 16:31:43.246104 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11151 16:31:43.246398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11152 16:31:43.246796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11153 16:31:43.247362 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11154 16:31:43.247696 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11155 16:31:43.248019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11156 16:31:43.248354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11157 16:31:43.248462 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11158 16:31:43.248781 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11159 16:31:43.249131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11160 16:31:43.249245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11161 16:31:43.249599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11162 16:31:43.249701 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11163 16:31:43.250175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11164 16:31:43.254343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11165 16:31:43.254752 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11166 16:31:43.254859 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11167 16:31:43.255138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11168 16:31:43.255484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11169 16:31:43.255595 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11170 16:31:43.255914 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11171 16:31:43.256035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11172 16:31:43.256189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11173 16:31:43.256737 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11174 16:31:43.256845 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11175 16:31:43.257153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11176 16:31:43.257293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11177 16:31:43.257662 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11178 16:31:43.262114 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11179 16:31:43.262432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11180 16:31:43.262721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11181 16:31:43.263050 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11182 16:31:43.263361 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11183 16:31:43.263475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11184 16:31:43.263761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11185 16:31:43.263878 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11186 16:31:43.263994 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11187 16:31:43.264296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11188 16:31:43.264417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11189 16:31:43.264731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11190 16:31:43.265022 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11191 16:31:43.265321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11192 16:31:43.265435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11193 16:31:43.265709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11194 16:31:43.265996 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11195 16:31:43.266133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11196 16:31:43.270079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11197 16:31:43.270636 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11198 16:31:43.271136 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11199 16:31:43.271475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11200 16:31:43.271613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11201 16:31:43.271938 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11202 16:31:43.272270 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11203 16:31:43.272547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11204 16:31:43.272687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11205 16:31:43.272818 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11206 16:31:43.272951 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11207 16:31:43.273322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11208 16:31:43.273681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11209 16:31:43.273830 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11210 16:31:43.282186 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11211 16:31:43.282542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11212 16:31:43.283129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11213 16:31:43.283446 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11214 16:31:43.283548 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11215 16:31:43.283854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11216 16:31:43.283969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11217 16:31:43.284486 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11218 16:31:43.284603 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11219 16:31:43.284911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11220 16:31:43.285228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11221 16:31:43.285356 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11222 16:31:43.285692 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11223 16:31:43.286023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11224 16:31:43.290084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11225 16:31:43.290396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11226 16:31:43.290732 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11227 16:31:43.290855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11228 16:31:43.291333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11229 16:31:43.291439 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11230 16:31:43.291551 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11231 16:31:43.291657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11232 16:31:43.291979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11233 16:31:43.292087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11234 16:31:43.292193 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11235 16:31:43.292525 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11236 16:31:43.292642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11237 16:31:43.292970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11238 16:31:43.293099 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11239 16:31:43.293423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11240 16:31:43.293729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11241 16:31:43.293849 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11242 16:31:43.298234 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11243 16:31:43.299013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11244 16:31:43.300207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11245 16:31:43.300524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11246 16:31:43.300625 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11247 16:31:43.300717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11248 16:31:43.300807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11249 16:31:43.300897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11250 16:31:43.300986 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11251 16:31:43.301075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11252 16:31:43.301522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11253 16:31:43.301633 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11254 16:31:43.301748 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11255 16:31:43.301843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11256 16:31:43.301930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11257 16:31:43.302438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11258 16:31:43.302551 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11259 16:31:43.306090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11260 16:31:43.306442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11261 16:31:43.307002 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11262 16:31:43.307327 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11263 16:31:43.307891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11264 16:31:43.308023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11265 16:31:43.308364 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11266 16:31:43.308501 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11267 16:31:43.308849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11268 16:31:43.309400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11269 16:31:43.309748 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11270 16:31:43.314158 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11271 16:31:43.314473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11272 16:31:43.314807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11273 16:31:43.314920 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11274 16:31:43.315031 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11275 16:31:43.315327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11276 16:31:43.316238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11277 16:31:43.316393 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11278 16:31:43.316506 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11279 16:31:43.316601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11280 16:31:43.316993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11281 16:31:43.317107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11282 16:31:43.317218 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11283 16:31:43.317355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11284 16:31:43.317716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11285 16:31:43.318037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11286 16:31:43.318145 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11287 16:31:43.322489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11288 16:31:43.322822 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11289 16:31:43.323277 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11290 16:31:43.323406 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11291 16:31:43.323502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11292 16:31:43.324192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11293 16:31:43.324681 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11294 16:31:43.324796 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11295 16:31:43.324888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11296 16:31:43.324979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11297 16:31:43.325068 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11298 16:31:43.325896 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11299 16:31:43.326010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11300 16:31:43.326103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11301 16:31:43.326192 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11302 16:31:43.326483 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11303 16:31:43.326597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11304 16:31:43.330122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11305 16:31:43.330430 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11306 16:31:43.330536 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11307 16:31:43.330644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11308 16:31:43.330944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11309 16:31:43.331076 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11310 16:31:43.331380 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11311 16:31:43.331501 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11312 16:31:43.331829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11313 16:31:43.332158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11314 16:31:43.332289 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11315 16:31:43.332611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11316 16:31:43.332934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11317 16:31:43.333253 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11318 16:31:43.333374 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11319 16:31:43.333886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11320 16:31:43.333997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11321 16:31:43.338167 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11322 16:31:43.338518 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11323 16:31:43.338656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11324 16:31:43.339221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11325 16:31:43.339541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11326 16:31:43.339661 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11327 16:31:43.340055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11328 16:31:43.340191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11329 16:31:43.340520 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11330 16:31:43.340912 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11331 16:31:43.341021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11332 16:31:43.341492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11333 16:31:43.341844 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11334 16:31:43.341944 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11335 16:31:43.342054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11336 16:31:43.342147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11337 16:31:43.342253 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11338 16:31:43.342359 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11339 16:31:43.342674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11340 16:31:43.350047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11341 16:31:43.350560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11342 16:31:43.350881 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11343 16:31:43.351008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11344 16:31:43.351146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11345 16:31:43.351474 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11346 16:31:43.351606 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11347 16:31:43.351902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11348 16:31:43.352038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11349 16:31:43.352136 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11350 16:31:43.352243 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11351 16:31:43.352555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11352 16:31:43.352700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11353 16:31:43.357775 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11354 16:31:43.357988 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11355 16:31:43.358080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11356 16:31:43.358166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11357 16:31:43.358250 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11358 16:31:43.358333 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11359 16:31:43.358415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11360 16:31:43.358498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11361 16:31:43.358580 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11362 16:31:43.358687 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11363 16:31:43.358773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11364 16:31:43.358856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11365 16:31:43.358955 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11366 16:31:43.359040 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11367 16:31:43.359412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11368 16:31:43.359515 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11369 16:31:43.359601 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11370 16:31:43.359684 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11371 16:31:43.359783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11372 16:31:43.359868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11373 16:31:43.359950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11374 16:31:43.360047 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11375 16:31:43.360146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11376 16:31:43.360460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11377 16:31:43.360737 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11378 16:31:43.360838 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11379 16:31:43.360936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11380 16:31:43.361232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11381 16:31:43.361347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11382 16:31:43.361643 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11383 16:31:43.361766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11384 16:31:43.362060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11385 16:31:43.366663 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11386 16:31:43.366773 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11387 16:31:43.366874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11388 16:31:43.366973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11389 16:31:43.367273 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11390 16:31:43.367397 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11391 16:31:43.367699 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11392 16:31:43.368009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11393 16:31:43.368319 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11394 16:31:43.368432 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11395 16:31:43.368722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11396 16:31:43.369008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11397 16:31:43.369318 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11398 16:31:43.369418 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11399 16:31:43.369518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11400 16:31:43.369802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11401 16:31:43.374090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11402 16:31:43.374401 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11403 16:31:43.374515 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11404 16:31:43.374813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11405 16:31:43.375113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11406 16:31:43.375227 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11407 16:31:43.375504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11408 16:31:43.375584 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11409 16:31:43.376107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11410 16:31:43.376209 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11411 16:31:43.376489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11412 16:31:43.376603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11413 16:31:43.376897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11414 16:31:43.376997 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11415 16:31:43.377094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11416 16:31:43.377463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11417 16:31:43.377754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11418 16:31:43.377834 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11419 16:31:43.378096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11420 16:31:43.382100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11421 16:31:43.382414 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11422 16:31:43.383108 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11423 16:31:43.383608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11424 16:31:43.384694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11425 16:31:43.385609 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11426 16:31:43.386117 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11427 16:31:43.390421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11428 16:31:43.390959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11429 16:31:43.391072 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11430 16:31:43.391366 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11431 16:31:43.391675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11432 16:31:43.392022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11433 16:31:43.392319 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11434 16:31:43.392432 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11435 16:31:43.392727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11436 16:31:43.392841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11437 16:31:43.393136 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11438 16:31:43.393443 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11439 16:31:43.393946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11440 16:31:43.398081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11441 16:31:43.398584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11442 16:31:43.398882 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11443 16:31:43.399182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11444 16:31:43.399282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11445 16:31:43.399384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11446 16:31:43.399483 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11447 16:31:43.399778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11448 16:31:43.399891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11449 16:31:43.399989 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11450 16:31:43.400094 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11451 16:31:43.400375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11452 16:31:43.400688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11453 16:31:43.400787 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11454 16:31:43.400884 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11455 16:31:43.401368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11456 16:31:43.401880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11457 16:31:43.406438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11458 16:31:43.406746 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11459 16:31:43.407062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11460 16:31:43.407369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11461 16:31:43.407677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11462 16:31:43.407995 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11463 16:31:43.408689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11464 16:31:43.409158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11465 16:31:43.409860 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11466 16:31:43.414110 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11467 16:31:43.414837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11468 16:31:43.415340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11469 16:31:43.415452 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11470 16:31:43.415980 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11471 16:31:43.416317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11472 16:31:43.416632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11473 16:31:43.416939 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11474 16:31:43.417448 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11475 16:31:43.417951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11476 16:31:43.422533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11477 16:31:43.422677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11478 16:31:43.422782 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11479 16:31:43.423068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11480 16:31:43.423382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11481 16:31:43.423502 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11482 16:31:43.423591 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11483 16:31:43.423690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11484 16:31:43.423985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11485 16:31:43.424514 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11486 16:31:43.424642 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11487 16:31:43.424949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11488 16:31:43.425070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11489 16:31:43.425374 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11490 16:31:43.425691 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11491 16:31:43.430096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11492 16:31:43.430808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11493 16:31:43.431323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11494 16:31:43.431831 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11495 16:31:43.432339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11496 16:31:43.433045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11497 16:31:43.433358 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11498 16:31:43.433674 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11499 16:31:43.442049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11500 16:31:43.442544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11501 16:31:43.442866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11502 16:31:43.443179 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11503 16:31:43.443881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11504 16:31:43.444387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11505 16:31:43.444699 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11506 16:31:43.445014 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11507 16:31:43.445335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11508 16:31:43.445844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11509 16:31:43.450286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11510 16:31:43.450593 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11511 16:31:43.450685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11512 16:31:43.451155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11513 16:31:43.451467 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11514 16:31:43.451806 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11515 16:31:43.452122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11516 16:31:43.452241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11517 16:31:43.452347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11518 16:31:43.452451 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11519 16:31:43.452937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11520 16:31:43.453043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11521 16:31:43.453327 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11522 16:31:43.453448 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11523 16:31:43.453538 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11524 16:31:43.453621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11525 16:31:43.453726 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11526 16:31:43.454025 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11527 16:31:43.461837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11528 16:31:43.461945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11529 16:31:43.462057 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11530 16:31:43.462151 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11531 16:31:43.462237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11532 16:31:43.462322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11533 16:31:43.462405 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11534 16:31:43.462489 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11535 16:31:43.462572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11536 16:31:43.462656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11537 16:31:43.462739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11538 16:31:43.462823 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11539 16:31:43.462913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11540 16:31:43.462996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11541 16:31:43.463079 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11542 16:31:43.463162 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11543 16:31:43.463244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11544 16:31:43.463327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11545 16:31:43.463410 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11546 16:31:43.463494 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11547 16:31:43.466336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11548 16:31:43.466443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11549 16:31:43.466730 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11550 16:31:43.466835 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11551 16:31:43.466937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11552 16:31:43.467036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11553 16:31:43.467136 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11554 16:31:43.467434 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11555 16:31:43.467739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11556 16:31:43.467850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11557 16:31:43.467954 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11558 16:31:43.468055 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11559 16:31:43.468379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11560 16:31:43.468689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11561 16:31:43.468794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11562 16:31:43.468879 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11563 16:31:43.468974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11564 16:31:43.469055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11565 16:31:43.469146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11566 16:31:43.469436 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11567 16:31:43.469539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11568 16:31:43.469831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11569 16:31:43.469934 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11570 16:31:43.470029 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11571 16:31:43.474540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11572 16:31:43.474643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11573 16:31:43.475077 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11574 16:31:43.475180 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11575 16:31:43.475261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11576 16:31:43.475535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11577 16:31:43.475638 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11578 16:31:43.475919 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11579 16:31:43.476034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11580 16:31:43.476315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11581 16:31:43.476417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11582 16:31:43.476512 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11583 16:31:43.476604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11584 16:31:43.476683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11585 16:31:43.476961 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11586 16:31:43.477076 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11587 16:31:43.477160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11588 16:31:43.477251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11589 16:31:43.477530 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11590 16:31:43.477830 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11591 16:31:43.477944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11592 16:31:43.478225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11593 16:31:43.482097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11594 16:31:43.482398 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11595 16:31:43.482500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11596 16:31:43.482866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11597 16:31:43.482981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11598 16:31:43.483271 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11599 16:31:43.483385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11600 16:31:43.483682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11601 16:31:43.483797 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11602 16:31:43.483891 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11603 16:31:43.484180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11604 16:31:43.484294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11605 16:31:43.484575 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11606 16:31:43.484677 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11607 16:31:43.484968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11608 16:31:43.485069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11609 16:31:43.485163 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11610 16:31:43.485255 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11611 16:31:43.485334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11612 16:31:43.485432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11613 16:31:43.485698 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11614 16:31:43.486009 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11615 16:31:43.486110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11616 16:31:43.490379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11617 16:31:43.490494 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11618 16:31:43.490778 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11619 16:31:43.490886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11620 16:31:43.491189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11621 16:31:43.491293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11622 16:31:43.491398 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11623 16:31:43.491487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11624 16:31:43.491588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11625 16:31:43.491712 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11626 16:31:43.492013 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11627 16:31:43.492358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11628 16:31:43.492465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11629 16:31:43.492748 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11630 16:31:43.492853 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11631 16:31:43.492956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11632 16:31:43.493045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11633 16:31:43.493146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11634 16:31:43.493236 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11635 16:31:43.493336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11636 16:31:43.493635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11637 16:31:43.493760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11638 16:31:43.494050 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11639 16:31:43.498084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11640 16:31:43.498386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11641 16:31:43.498510 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11642 16:31:43.498637 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11643 16:31:43.498962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11644 16:31:43.499069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11645 16:31:43.499396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11646 16:31:43.499492 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11647 16:31:43.499595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11648 16:31:43.499879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11649 16:31:43.499984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11650 16:31:43.500115 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11651 16:31:43.500458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11652 16:31:43.500561 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11653 16:31:43.500844 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11654 16:31:43.500957 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11655 16:31:43.501247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11656 16:31:43.501353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11657 16:31:43.501483 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11658 16:31:43.501588 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11659 16:31:43.501714 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11660 16:31:43.502012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11661 16:31:43.502117 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11662 16:31:43.502203 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11663 16:31:43.506463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11664 16:31:43.506563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11665 16:31:43.507583 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11666 16:31:43.507675 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11667 16:31:43.507743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11668 16:31:43.507823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11669 16:31:43.507911 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11670 16:31:43.508183 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11671 16:31:43.508289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11672 16:31:43.508378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11673 16:31:43.508480 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11674 16:31:43.508570 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11675 16:31:43.508656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11676 16:31:43.509142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11677 16:31:43.509269 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11678 16:31:43.509378 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11679 16:31:43.509693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11680 16:31:43.514316 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11681 16:31:43.514620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11682 16:31:43.514926 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11683 16:31:43.515031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11684 16:31:43.515135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11685 16:31:43.515222 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11686 16:31:43.515327 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11687 16:31:43.515612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11688 16:31:43.515732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11689 16:31:43.515837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11690 16:31:43.516140 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11691 16:31:43.516246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11692 16:31:43.516547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11693 16:31:43.516653 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11694 16:31:43.516757 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11695 16:31:43.516857 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11696 16:31:43.516958 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11697 16:31:43.517254 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11698 16:31:43.517373 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11699 16:31:43.517677 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11700 16:31:43.517796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11701 16:31:43.517899 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11702 16:31:43.522791 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11703 16:31:43.522907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11704 16:31:43.523002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11705 16:31:43.523089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11706 16:31:43.523708 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11707 16:31:43.523816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11708 16:31:43.523906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11709 16:31:43.523993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11710 16:31:43.524079 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11711 16:31:43.524181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11712 16:31:43.524270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11713 16:31:43.524359 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11714 16:31:43.524447 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11715 16:31:43.524550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11716 16:31:43.524655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11717 16:31:43.524745 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11718 16:31:43.526725 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
11719 16:31:43.526833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
11720 16:31:43.526921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
11721 16:31:43.527005 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
11722 16:31:43.527086 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
11723 16:31:43.527168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
11724 16:31:43.527251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
11725 16:31:43.527333 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
11726 16:31:43.527415 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
11727 16:31:43.531902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
11728 16:31:43.532207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
11729 16:31:43.532331 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
11730 16:31:43.532439 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
11731 16:31:43.532731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
11732 16:31:43.532827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
11733 16:31:43.533101 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
11734 16:31:43.533207 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
11735 16:31:43.533313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
11736 16:31:43.533417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
11737 16:31:43.533693 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
11738 16:31:43.533814 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
11739 16:31:43.534258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
11740 16:31:43.534365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
11741 16:31:43.534650 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
11742 16:31:43.534756 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
11743 16:31:43.534859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
11744 16:31:43.534965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
11745 16:31:43.535249 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
11746 16:31:43.535554 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
11747 16:31:43.535658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
11748 16:31:43.535760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
11749 16:31:43.535862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
11750 16:31:43.536158 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
11751 16:31:43.536278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
11752 16:31:43.536567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
11753 16:31:43.536673 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
11754 16:31:43.536777 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
11755 16:31:43.536879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
11756 16:31:43.537185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
11757 16:31:43.537304 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
11758 16:31:43.537409 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
11759 16:31:43.537687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
11760 16:31:43.537968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
11761 16:31:43.538072 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
11762 16:31:43.542166 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
11763 16:31:43.542470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
11764 16:31:43.542575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
11765 16:31:43.542879 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
11766 16:31:43.542986 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
11767 16:31:43.543090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
11768 16:31:43.543193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
11769 16:31:43.543491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
11770 16:31:43.543597 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
11771 16:31:43.543702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
11772 16:31:43.543805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
11773 16:31:43.543907 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
11774 16:31:43.544214 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
11775 16:31:43.544335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
11776 16:31:43.544440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
11777 16:31:43.544544 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
11778 16:31:43.544833 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
11779 16:31:43.544953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
11780 16:31:43.545254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
11781 16:31:43.545358 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
11782 16:31:43.545455 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
11783 16:31:43.545586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
11784 16:31:43.545716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
11785 16:31:43.550179 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
11786 16:31:43.550481 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
11787 16:31:43.550586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
11788 16:31:43.550688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
11789 16:31:43.550788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
11790 16:31:43.550887 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
11791 16:31:43.550986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
11792 16:31:43.551271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
11793 16:31:43.551586 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
11794 16:31:43.551691 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
11795 16:31:43.551794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
11796 16:31:43.551881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
11797 16:31:43.551981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
11798 16:31:43.552387 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
11799 16:31:43.552493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
11800 16:31:43.552796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
11801 16:31:43.552902 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
11802 16:31:43.553002 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
11803 16:31:43.553188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
11804 16:31:43.553294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
11805 16:31:43.553397 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
11806 16:31:43.553498 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
11807 16:31:43.553596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
11808 16:31:43.553907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
11809 16:31:43.558153 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
11810 16:31:43.558455 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
11811 16:31:43.558772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
11812 16:31:43.558890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
11813 16:31:43.558995 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
11814 16:31:43.571939 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
11815 16:31:43.572243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
11816 16:31:43.572349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
11817 16:31:43.572460 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
11818 16:31:43.572784 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
11819 16:31:43.572904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
11820 16:31:43.572996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
11821 16:31:43.573099 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
11822 16:31:43.573402 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
11823 16:31:43.573520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
11824 16:31:43.573803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
11825 16:31:43.574117 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
11826 16:31:43.574220 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
11827 16:31:43.574318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
11828 16:31:43.575019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
11829 16:31:43.575123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
11830 16:31:43.575206 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
11831 16:31:43.575286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
11832 16:31:43.575563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
11833 16:31:43.575671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
11834 16:31:43.575760 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
11835 16:31:43.575859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
11836 16:31:43.576147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
11837 16:31:43.576267 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
11838 16:31:43.576554 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
11839 16:31:43.576659 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
11840 16:31:43.576760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
11841 16:31:43.577045 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
11842 16:31:43.577165 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
11843 16:31:43.577254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
11844 16:31:43.577353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
11845 16:31:43.577638 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
11846 16:31:43.577949 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
11847 16:31:43.578057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
11848 16:31:43.582152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
11849 16:31:43.582452 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
11850 16:31:43.582554 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
11851 16:31:43.582650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
11852 16:31:43.582745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
11853 16:31:43.583224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
11854 16:31:43.583327 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
11855 16:31:43.583424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
11856 16:31:43.583507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
11857 16:31:43.583808 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
11858 16:31:43.584107 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
11859 16:31:43.584210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
11860 16:31:43.584306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
11861 16:31:43.584775 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
11862 16:31:43.584882 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
11863 16:31:43.584972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
11864 16:31:43.585262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
11865 16:31:43.585369 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
11866 16:31:43.585460 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
11867 16:31:43.585563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
11868 16:31:43.585658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
11869 16:31:43.585958 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
11870 16:31:43.586066 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
11871 16:31:43.590209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
11872 16:31:43.590515 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
11873 16:31:43.590622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
11874 16:31:43.590754 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
11875 16:31:43.590882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
11876 16:31:43.593683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
11877 16:31:43.593794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
11878 16:31:43.593908 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
11879 16:31:43.594020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
11880 16:31:43.594131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
11881 16:31:43.594242 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
11882 16:31:43.594335 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
11883 16:31:43.594420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
11884 16:31:43.594504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
11885 16:31:43.594588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
11886 16:31:43.594670 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
11887 16:31:43.594753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
11888 16:31:43.594836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
11889 16:31:43.594919 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
11890 16:31:43.595002 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
11891 16:31:43.595084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
11892 16:31:43.595398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
11893 16:31:43.595504 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
11894 16:31:43.599552 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
11895 16:31:43.599657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
11896 16:31:43.599742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
11897 16:31:43.599825 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
11898 16:31:43.599907 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
11899 16:31:43.599989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
11900 16:31:43.600071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
11901 16:31:43.600153 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
11902 16:31:43.600433 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
11903 16:31:43.600538 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
11904 16:31:43.600624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
11905 16:31:43.600709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
11906 16:31:43.600792 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
11907 16:31:43.600874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
11908 16:31:43.600973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
11909 16:31:43.601059 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
11910 16:31:43.601142 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
11911 16:31:43.601241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
11912 16:31:43.601327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
11913 16:31:43.601430 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
11914 16:31:43.601530 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
11915 16:31:43.601817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
11916 16:31:43.601937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
11917 16:31:43.610472 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
11918 16:31:43.610775 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
11919 16:31:43.611213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
11920 16:31:43.611320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
11921 16:31:43.611408 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
11922 16:31:43.611689 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
11923 16:31:43.611794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
11924 16:31:43.611882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
11925 16:31:43.611983 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
11926 16:31:43.612071 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
11927 16:31:43.612368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
11928 16:31:43.612489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
11929 16:31:43.612579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
11930 16:31:43.612679 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
11931 16:31:43.612779 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
11932 16:31:43.613077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
11933 16:31:43.613197 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
11934 16:31:43.613299 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
11935 16:31:43.613399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
11936 16:31:43.613710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
11937 16:31:43.614009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
11938 16:31:43.614894 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
11939 16:31:43.615001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
11940 16:31:43.615085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
11941 16:31:43.615166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
11942 16:31:43.615247 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
11943 16:31:43.615587 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
11944 16:31:43.615690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
11945 16:31:43.615771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
11946 16:31:43.615848 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
11947 16:31:43.615925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
11948 16:31:43.632653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
11949 16:31:43.632957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
11950 16:31:43.633062 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
11951 16:31:43.633168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
11952 16:31:43.633272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
11953 16:31:43.633570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
11954 16:31:43.633683 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
11955 16:31:43.633786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
11956 16:31:43.634200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
11957 16:31:43.634307 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
11958 16:31:43.634774 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
11959 16:31:43.634856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
11960 16:31:43.634932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
11961 16:31:43.634996 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
11962 16:31:43.635059 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
11963 16:31:43.635327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
11964 16:31:43.635444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
11965 16:31:43.635540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
11966 16:31:43.635828 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
11967 16:31:43.635949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
11968 16:31:43.636038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
11969 16:31:43.636145 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
11970 16:31:43.636435 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
11971 16:31:43.636540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
11972 16:31:43.636839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
11973 16:31:43.636944 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
11974 16:31:43.637046 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
11975 16:31:43.637335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
11976 16:31:43.637439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
11977 16:31:43.637543 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
11978 16:31:43.637629 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
11979 16:31:43.637735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
11980 16:31:43.642063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
11981 16:31:43.642367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
11982 16:31:43.642492 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
11983 16:31:43.642622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
11984 16:31:43.642748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
11985 16:31:43.643071 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
11986 16:31:43.643178 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
11987 16:31:43.643310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
11988 16:31:43.643437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
11989 16:31:43.643759 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
11990 16:31:43.643884 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
11991 16:31:43.644012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
11992 16:31:43.644138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
11993 16:31:43.644469 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
11994 16:31:43.644595 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
11995 16:31:43.644905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
11996 16:31:43.645012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
11997 16:31:43.645146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
11998 16:31:43.645255 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
11999 16:31:43.645383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12000 16:31:43.645692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12001 16:31:43.645811 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12002 16:31:43.645913 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12003 16:31:43.650096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12004 16:31:43.650594 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12005 16:31:43.650699 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12006 16:31:43.650789 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12007 16:31:43.650897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12008 16:31:43.651072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12009 16:31:43.651194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12010 16:31:43.651295 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12011 16:31:43.651591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12012 16:31:43.651696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12013 16:31:43.651984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12014 16:31:43.652089 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12015 16:31:43.652189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12016 16:31:43.652289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12017 16:31:43.652388 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12018 16:31:43.652486 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12019 16:31:43.652788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12020 16:31:43.652906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12021 16:31:43.653203 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12022 16:31:43.653323 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12023 16:31:43.653425 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12024 16:31:43.653694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12025 16:31:43.653998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12026 16:31:43.654103 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12027 16:31:43.658294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12028 16:31:43.658414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12029 16:31:43.658878 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12030 16:31:43.658983 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12031 16:31:43.659268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12032 16:31:43.659374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12033 16:31:43.659464 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12034 16:31:43.659564 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12035 16:31:43.659849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12036 16:31:43.659969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12037 16:31:43.660072 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12038 16:31:43.660358 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12039 16:31:43.660477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12040 16:31:43.660578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12041 16:31:43.660678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12042 16:31:43.660973 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12043 16:31:43.661079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12044 16:31:43.661185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12045 16:31:43.661475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12046 16:31:43.661581 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12047 16:31:43.661713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12048 16:31:43.662069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12049 16:31:43.666237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12050 16:31:43.666344 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12051 16:31:43.666631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12052 16:31:43.666737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12053 16:31:43.666839 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12054 16:31:43.666938 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12055 16:31:43.667037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12056 16:31:43.667332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12057 16:31:43.667451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12058 16:31:43.667554 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12059 16:31:43.667870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12060 16:31:43.667972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12061 16:31:43.668254 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12062 16:31:43.668358 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12063 16:31:43.668460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12064 16:31:43.668758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12065 16:31:43.668862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12066 16:31:43.668963 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12067 16:31:43.669250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12068 16:31:43.669368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12069 16:31:43.669470 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12070 16:31:43.669755 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12071 16:31:43.669860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12072 16:31:43.669961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12073 16:31:43.674550 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12074 16:31:43.674659 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12075 16:31:43.674967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12076 16:31:43.675074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12077 16:31:43.675206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12078 16:31:43.675314 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12079 16:31:43.675442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12080 16:31:43.675551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12081 16:31:43.675653 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12082 16:31:43.692940 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12083 16:31:43.693047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12084 16:31:43.693332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12085 16:31:43.693452 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12086 16:31:43.693543 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12087 16:31:43.693644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12088 16:31:43.693940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12089 16:31:43.694255 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12090 16:31:43.694566 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12091 16:31:43.694670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12092 16:31:43.694773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12093 16:31:43.694861 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12094 16:31:43.695157 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12095 16:31:43.695261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12096 16:31:43.695704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12097 16:31:43.695809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12098 16:31:43.695898 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12099 16:31:43.696650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12100 16:31:43.696756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12101 16:31:43.696842 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12102 16:31:43.696926 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12103 16:31:43.697009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12104 16:31:43.697092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12105 16:31:43.697453 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12106 16:31:43.697560 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12107 16:31:43.697884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12108 16:31:43.697991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12109 16:31:43.698080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12110 16:31:43.698167 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12111 16:31:43.698449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12112 16:31:43.702087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12113 16:31:43.702391 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12114 16:31:43.702496 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12115 16:31:43.702625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12116 16:31:43.702949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12117 16:31:43.703055 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12118 16:31:43.703186 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12119 16:31:43.704075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12120 16:31:43.704184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12121 16:31:43.704296 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12122 16:31:43.704407 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12123 16:31:43.704518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12124 16:31:43.704827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12125 16:31:43.704933 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12126 16:31:43.705045 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12127 16:31:43.705155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12128 16:31:43.705293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12129 16:31:43.705401 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12130 16:31:43.705512 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12131 16:31:43.705643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12132 16:31:43.705757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12133 16:31:43.705885 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12134 16:31:43.705982 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12135 16:31:43.710162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12136 16:31:43.710466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12137 16:31:43.710572 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12138 16:31:43.710674 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12139 16:31:43.710960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12140 16:31:43.711080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12141 16:31:43.711183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12142 16:31:43.711470 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12143 16:31:43.711588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12144 16:31:43.711691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12145 16:31:43.711978 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12146 16:31:43.712084 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12147 16:31:43.712188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12148 16:31:43.712290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12149 16:31:43.712576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12150 16:31:43.712696 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12151 16:31:43.712985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12152 16:31:43.713090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12153 16:31:43.713389 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12154 16:31:43.713494 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12155 16:31:43.713595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12156 16:31:43.713702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12157 16:31:43.713803 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12158 16:31:43.718224 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12159 16:31:43.718530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12160 16:31:43.718636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12161 16:31:43.718737 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12162 16:31:43.718824 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12163 16:31:43.718923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12164 16:31:43.719218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12165 16:31:43.719323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12166 16:31:43.719424 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12167 16:31:43.719719 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12168 16:31:43.720024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12169 16:31:43.720143 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12170 16:31:43.720808 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12171 16:31:43.720913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12172 16:31:43.721001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12173 16:31:43.721087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12174 16:31:43.721171 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12175 16:31:43.721453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12176 16:31:43.721558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12177 16:31:43.721652 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12178 16:31:43.721757 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12179 16:31:43.721845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12180 16:31:43.721954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12181 16:31:43.726189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12182 16:31:43.726491 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12183 16:31:43.726596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12184 16:31:43.726707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12185 16:31:43.726837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12186 16:31:43.726964 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12187 16:31:43.727092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12188 16:31:43.727413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12189 16:31:43.727519 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12190 16:31:43.727622 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12191 16:31:43.727921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12192 16:31:43.728228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12193 16:31:43.728336 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12194 16:31:43.728468 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12195 16:31:43.728576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12196 16:31:43.728708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12197 16:31:43.728836 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12198 16:31:43.729144 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12199 16:31:43.729262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12200 16:31:43.729368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12201 16:31:43.729468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12202 16:31:43.729768 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12203 16:31:43.729886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12204 16:31:43.734077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12205 16:31:43.734385 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12206 16:31:43.734506 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12207 16:31:43.734610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12208 16:31:43.734916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12209 16:31:43.735217 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12210 16:31:43.735321 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12211 16:31:43.735410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12212 16:31:43.735506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12213 16:31:43.735805 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12214 16:31:43.735912 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12215 16:31:43.736016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12216 16:31:43.753177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12217 16:31:43.753479 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12218 16:31:43.753599 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12219 16:31:43.753694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12220 16:31:43.753993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12221 16:31:43.754302 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12222 16:31:43.754410 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12223 16:31:43.754540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12224 16:31:43.754859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12225 16:31:43.754979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12226 16:31:43.755084 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12227 16:31:43.755372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12228 16:31:43.755477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12229 16:31:43.755580 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12230 16:31:43.755690 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12231 16:31:43.755982 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12232 16:31:43.756073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12233 16:31:43.756328 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12234 16:31:43.756409 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12235 16:31:43.756672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12236 16:31:43.756778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12237 16:31:43.756909 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12238 16:31:43.757014 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12239 16:31:43.757314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12240 16:31:43.757418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12241 16:31:43.757521 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12242 16:31:43.757623 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12243 16:31:43.757731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12244 16:31:43.758024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12245 16:31:43.762395 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12246 16:31:43.762704 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12247 16:31:43.762809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12248 16:31:43.762970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12249 16:31:43.763078 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12250 16:31:43.763207 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12251 16:31:43.763316 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12252 16:31:43.763602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12253 16:31:43.764093 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12254 16:31:43.764199 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12255 16:31:43.764286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12256 16:31:43.764837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12257 16:31:43.764942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12258 16:31:43.765031 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12259 16:31:43.765115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12260 16:31:43.765397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12261 16:31:43.765502 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12262 16:31:43.765591 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12263 16:31:43.765698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12264 16:31:43.765786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12265 16:31:43.765887 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12266 16:31:43.765974 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12267 16:31:43.770174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12268 16:31:43.770478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12269 16:31:43.770582 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12270 16:31:43.770685 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12271 16:31:43.770785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12272 16:31:43.771072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12273 16:31:43.771192 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12274 16:31:43.771482 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12275 16:31:43.771586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12276 16:31:43.771689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12277 16:31:43.771779 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12278 16:31:43.771879 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12279 16:31:43.772176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12280 16:31:43.772280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12281 16:31:43.772384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12282 16:31:43.772765 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12283 16:31:43.772870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12284 16:31:43.772973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12285 16:31:43.773073 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12286 16:31:43.773173 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12287 16:31:43.773463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12288 16:31:43.773566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12289 16:31:43.773869 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12290 16:31:43.773973 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12291 16:31:43.778121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12292 16:31:43.778423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12293 16:31:43.778541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12294 16:31:43.778644 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12295 16:31:43.778752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12296 16:31:43.779038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12297 16:31:43.779344 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12298 16:31:43.779450 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12299 16:31:43.779553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12300 16:31:43.779841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12301 16:31:43.779967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12302 16:31:43.780096 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12303 16:31:43.780204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12304 16:31:43.780327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12305 16:31:43.780636 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12306 16:31:43.780741 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12307 16:31:43.780843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12308 16:31:43.780963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12309 16:31:43.781280 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12310 16:31:43.781385 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12311 16:31:43.781517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12312 16:31:43.781637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12313 16:31:43.781933 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12314 16:31:43.782039 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12315 16:31:43.789956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12316 16:31:43.790064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12317 16:31:43.790151 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12318 16:31:43.790237 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12319 16:31:43.790320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12320 16:31:43.790404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12321 16:31:43.790488 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12322 16:31:43.790573 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12323 16:31:43.790657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12324 16:31:43.790741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12325 16:31:43.790824 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12326 16:31:43.790906 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12327 16:31:43.790989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12328 16:31:43.791073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12329 16:31:43.791157 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12330 16:31:43.791242 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12331 16:31:43.791325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12332 16:31:43.791408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12333 16:31:43.791494 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12334 16:31:43.791576 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12335 16:31:43.794080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12336 16:31:43.795554 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12337 16:31:43.796862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12338 16:31:43.797893 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12339 16:31:43.802070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12340 16:31:43.802565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12341 16:31:43.803074 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12342 16:31:43.803579 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12343 16:31:43.804086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12344 16:31:43.805139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12345 16:31:43.806425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12346 16:31:43.814019 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12347 16:31:43.814321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12348 16:31:43.814440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12349 16:31:43.814743 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12350 16:31:43.821857 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12351 16:31:43.822354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12352 16:31:43.822664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12353 16:31:43.822973 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12354 16:31:43.823478 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12355 16:31:43.823597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12356 16:31:43.823895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12357 16:31:43.824406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12358 16:31:43.824521 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12359 16:31:43.825010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12360 16:31:43.830069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12361 16:31:43.830562 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12362 16:31:43.830676 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12363 16:31:43.830978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12364 16:31:43.831510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12365 16:31:43.831820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12366 16:31:43.832129 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12367 16:31:43.832657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12368 16:31:43.832978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12369 16:31:43.833691 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12370 16:31:43.838113 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12371 16:31:43.838612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12372 16:31:43.838924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12373 16:31:43.839633 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12374 16:31:43.839943 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12375 16:31:43.840252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12376 16:31:43.840567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12377 16:31:43.841068 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12378 16:31:43.841404 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12379 16:31:43.841693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12380 16:31:43.846051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12381 16:31:43.846350 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12382 16:31:43.846661 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12383 16:31:43.846969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12384 16:31:43.847477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12385 16:31:43.847786 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12386 16:31:43.848328 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12387 16:31:43.848828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12388 16:31:43.849330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12389 16:31:43.858029 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12390 16:31:43.859206 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12391 16:31:43.859531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12392 16:31:43.859828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12393 16:31:43.860137 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12394 16:31:43.860440 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12395 16:31:43.860917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12396 16:31:43.861434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12397 16:31:43.861959 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12398 16:31:43.867224 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12399 16:31:43.867720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12400 16:31:43.868220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12401 16:31:43.869495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12402 16:31:43.874069 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12403 16:31:43.875349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12404 16:31:43.876241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12405 16:31:43.876972 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12406 16:31:43.877470 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12407 16:31:43.882088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12408 16:31:43.883357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12409 16:31:43.883665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12410 16:31:43.884166 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12411 16:31:43.884897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12412 16:31:43.885989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12413 16:31:43.890064 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12414 16:31:43.890564 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12415 16:31:43.890689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12416 16:31:43.891211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12417 16:31:43.891735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12418 16:31:43.892235 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12419 16:31:43.892548 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12420 16:31:43.893055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12421 16:31:43.893392 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12422 16:31:43.893941 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12423 16:31:43.898051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12424 16:31:43.898743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12425 16:31:43.899644 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12426 16:31:43.900157 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12427 16:31:43.900666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12428 16:31:43.901170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12429 16:31:43.901877 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12430 16:31:43.906084 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12431 16:31:43.906776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12432 16:31:43.906895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12433 16:31:43.907392 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12434 16:31:43.907520 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12435 16:31:43.908035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12436 16:31:43.908159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12437 16:31:43.908483 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12438 16:31:43.908608 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12439 16:31:43.908928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12440 16:31:43.909256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12441 16:31:43.909577 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12442 16:31:43.914120 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12443 16:31:43.915009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12444 16:31:43.915321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12445 16:31:43.915870 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12446 16:31:43.916576 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12447 16:31:43.917509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12448 16:31:43.922077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12449 16:31:43.922771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12450 16:31:43.923478 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12451 16:31:43.924194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12452 16:31:43.925496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12453 16:31:43.934011 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12454 16:31:43.934530 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12455 16:31:43.935444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12456 16:31:43.935972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12457 16:31:43.936479 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12458 16:31:43.936981 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12459 16:31:43.937299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12460 16:31:43.937805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12461 16:31:43.942088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12462 16:31:43.942391 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12463 16:31:43.942710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12464 16:31:43.943222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12465 16:31:43.943734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12466 16:31:43.944238 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12467 16:31:43.944748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12468 16:31:43.945457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12469 16:31:43.945949 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12470 16:31:43.950348 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12471 16:31:43.950860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12472 16:31:43.951180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12473 16:31:43.951918 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12474 16:31:43.952636 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12475 16:31:43.953570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12476 16:31:43.958061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12477 16:31:43.958754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12478 16:31:43.960158 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12479 16:31:43.960262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12480 16:31:43.960343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12481 16:31:43.960421 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12482 16:31:43.960694 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12483 16:31:43.960795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12484 16:31:43.961463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12485 16:31:43.961774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12486 16:31:43.961891 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12487 16:31:43.966139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12488 16:31:43.966441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12489 16:31:43.966754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12490 16:31:43.966858 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12491 16:31:43.967157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12492 16:31:43.967276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12493 16:31:43.967575 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12494 16:31:43.967695 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12495 16:31:43.967801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12496 16:31:43.967911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12497 16:31:43.968237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12498 16:31:43.968356 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12499 16:31:43.968866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12500 16:31:43.968970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12501 16:31:43.969272 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12502 16:31:43.969390 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12503 16:31:43.969699 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12504 16:31:43.970001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12505 16:31:43.974155 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12506 16:31:43.974457 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12507 16:31:43.974970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12508 16:31:43.975480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12509 16:31:43.975960 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12510 16:31:43.976078 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12511 16:31:43.976395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12512 16:31:43.976683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12513 16:31:43.976961 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12514 16:31:43.977268 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12515 16:31:43.977578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12516 16:31:43.982091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12517 16:31:43.982968 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12518 16:31:43.983085 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12519 16:31:43.983584 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12520 16:31:43.983897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12521 16:31:43.984404 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12522 16:31:43.984717 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12523 16:31:43.985034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12524 16:31:43.985348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12525 16:31:43.985667 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12526 16:31:43.985991 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12527 16:31:43.990053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12528 16:31:43.990754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12529 16:31:43.991084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12530 16:31:43.991189 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12531 16:31:43.991516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12532 16:31:43.992040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12533 16:31:43.992171 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12534 16:31:43.992490 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12535 16:31:43.993036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12536 16:31:43.993547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12537 16:31:43.998082 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12538 16:31:43.998581 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12539 16:31:43.998897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12540 16:31:43.999231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12541 16:31:43.999734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12542 16:31:44.000178 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12543 16:31:44.000731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12544 16:31:44.001045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12545 16:31:44.001358 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12546 16:31:44.001681 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12547 16:31:44.006117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12548 16:31:44.006631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12549 16:31:44.007145 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12550 16:31:44.007506 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12551 16:31:44.008454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12552 16:31:44.009690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12553 16:31:44.018031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12554 16:31:44.018331 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12555 16:31:44.018769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12556 16:31:44.019447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12557 16:31:44.020149 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12558 16:31:44.020857 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12559 16:31:44.021206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12560 16:31:44.021891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12561 16:31:44.026088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12562 16:31:44.026747 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12563 16:31:44.027451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12564 16:31:44.027764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12565 16:31:44.027885 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12566 16:31:44.027989 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12567 16:31:44.028479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12568 16:31:44.028790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12569 16:31:44.029118 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12570 16:31:44.029430 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12571 16:31:44.029743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12572 16:31:44.034084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12573 16:31:44.034771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12574 16:31:44.034888 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12575 16:31:44.035195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12576 16:31:44.035474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12577 16:31:44.035974 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12578 16:31:44.036253 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12579 16:31:44.036534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12580 16:31:44.036652 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12581 16:31:44.037150 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12582 16:31:44.037679 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12583 16:31:44.037989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12584 16:31:44.042853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12585 16:31:44.043363 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12586 16:31:44.043488 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12587 16:31:44.044114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12588 16:31:44.045046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12589 16:31:44.045977 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12590 16:31:44.050532 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12591 16:31:44.051840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12592 16:31:44.053325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12593 16:31:44.058103 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12594 16:31:44.059184 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12595 16:31:44.060470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12596 16:31:44.061700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12597 16:31:44.061981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12598 16:31:44.066086 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12599 16:31:44.067177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12600 16:31:44.067905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12601 16:31:44.068431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12602 16:31:44.069574 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12603 16:31:44.070281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12604 16:31:44.078624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12605 16:31:44.078937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12606 16:31:44.079062 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12607 16:31:44.079187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12608 16:31:44.079508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12609 16:31:44.079828 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12610 16:31:44.079964 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12611 16:31:44.080101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12612 16:31:44.080466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12613 16:31:44.080601 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12614 16:31:44.080922 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12615 16:31:44.081255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12616 16:31:44.081391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12617 16:31:44.086066 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12618 16:31:44.086563 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12619 16:31:44.088051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12620 16:31:44.088616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12621 16:31:44.089130 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12622 16:31:44.089623 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12623 16:31:44.098027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12624 16:31:44.098542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12625 16:31:44.099010 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12626 16:31:44.099518 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12627 16:31:44.100234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12628 16:31:44.100571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12629 16:31:44.100885 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12630 16:31:44.101197 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12631 16:31:44.101512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12632 16:31:44.102226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12633 16:31:44.102740 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12634 16:31:44.103065 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12635 16:31:44.103950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12636 16:31:44.104269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12637 16:31:44.104588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12638 16:31:44.104906 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12639 16:31:44.105226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12640 16:31:44.105921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12641 16:31:44.110128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12642 16:31:44.110635 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12643 16:31:44.110947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12644 16:31:44.111654 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12645 16:31:44.112159 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12646 16:31:44.112469 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12647 16:31:44.112794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12648 16:31:44.113103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12649 16:31:44.113610 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12650 16:31:44.122010 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12651 16:31:44.122890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12652 16:31:44.123399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12653 16:31:44.124301 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12654 16:31:44.124781 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12655 16:31:44.126043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12656 16:31:44.130159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12657 16:31:44.130679 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12658 16:31:44.131196 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12659 16:31:44.131705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12660 16:31:44.132228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12661 16:31:44.132553 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12662 16:31:44.132866 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12663 16:31:44.133566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12664 16:31:44.138091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12665 16:31:44.140408 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12666 16:31:44.140528 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12667 16:31:44.140645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12668 16:31:44.140750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12669 16:31:44.141263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12670 16:31:44.141397 arm64_sve-ptrace pass
12671 16:31:44.141886 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12672 16:31:44.146134 arm64_sve-probe-vls_All_vector_lengths_valid pass
12673 16:31:44.146454 arm64_sve-probe-vls pass
12674 16:31:44.146559 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12675 16:31:44.146662 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12676 16:31:44.146764 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12677 16:31:44.147060 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12678 16:31:44.147382 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12679 16:31:44.149140 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12680 16:31:44.149259 arm64_vec-syscfg_SVE_vector_length_used_default pass
12681 16:31:44.149369 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12682 16:31:44.149483 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12683 16:31:44.149594 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12684 16:31:44.149710 arm64_vec-syscfg_SME_default_vector_length_32 pass
12685 16:31:44.149804 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12686 16:31:44.149908 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12687 16:31:44.149995 arm64_vec-syscfg_SME_current_VL_is_32 pass
12688 16:31:44.150080 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12689 16:31:44.154062 arm64_vec-syscfg_SME_prctl_set_min_max pass
12690 16:31:44.155209 arm64_vec-syscfg_SME_vector_length_used_default pass
12691 16:31:44.156107 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12692 16:31:44.156206 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12693 16:31:44.156665 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12694 16:31:44.156788 arm64_vec-syscfg pass
12695 16:31:44.156892 arm64_za-fork_fork_test pass
12696 16:31:44.157190 arm64_za-fork pass
12697 16:31:44.157513 arm64_za-ptrace_Set_VL_16 pass
12698 16:31:44.157629 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12699 16:31:44.158005 arm64_za-ptrace_Data_match_for_VL_16 pass
12700 16:31:44.162073 arm64_za-ptrace_Set_VL_32 pass
12701 16:31:44.162371 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12702 16:31:44.162676 arm64_za-ptrace_Data_match_for_VL_32 pass
12703 16:31:44.162780 arm64_za-ptrace_Set_VL_48 pass
12704 16:31:44.163069 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12705 16:31:44.163192 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12706 16:31:44.163321 arm64_za-ptrace_Set_VL_64 pass
12707 16:31:44.163436 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12708 16:31:44.163742 arm64_za-ptrace_Data_match_for_VL_64 pass
12709 16:31:44.163845 arm64_za-ptrace_Set_VL_80 pass
12710 16:31:44.164141 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12711 16:31:44.165044 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12712 16:31:44.165149 arm64_za-ptrace_Set_VL_96 pass
12713 16:31:44.165279 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12714 16:31:44.165405 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12715 16:31:44.165697 arm64_za-ptrace_Set_VL_112 pass
12716 16:31:44.165826 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12717 16:31:44.170091 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12718 16:31:44.170392 arm64_za-ptrace_Set_VL_128 pass
12719 16:31:44.170728 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
12720 16:31:44.171232 arm64_za-ptrace_Data_match_for_VL_128 pass
12721 16:31:44.171333 arm64_za-ptrace_Set_VL_144 pass
12722 16:31:44.171431 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
12723 16:31:44.171514 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
12724 16:31:44.171608 arm64_za-ptrace_Set_VL_160 pass
12725 16:31:44.171699 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
12726 16:31:44.172075 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
12727 16:31:44.172189 arm64_za-ptrace_Set_VL_176 pass
12728 16:31:44.172479 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
12729 16:31:44.172789 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
12730 16:31:44.173098 arm64_za-ptrace_Set_VL_192 pass
12731 16:31:44.173216 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
12732 16:31:44.173506 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
12733 16:31:44.173881 arm64_za-ptrace_Set_VL_208 pass
12734 16:31:44.178120 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
12735 16:31:44.178419 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
12736 16:31:44.178519 arm64_za-ptrace_Set_VL_224 pass
12737 16:31:44.178811 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
12738 16:31:44.178925 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
12739 16:31:44.179218 arm64_za-ptrace_Set_VL_240 pass
12740 16:31:44.179719 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
12741 16:31:44.179833 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
12742 16:31:44.180127 arm64_za-ptrace_Set_VL_256 pass
12743 16:31:44.180240 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
12744 16:31:44.180531 arm64_za-ptrace_Data_match_for_VL_256 pass
12745 16:31:44.180645 arm64_za-ptrace_Set_VL_272 pass
12746 16:31:44.181005 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
12747 16:31:44.181119 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
12748 16:31:44.181409 arm64_za-ptrace_Set_VL_288 pass
12749 16:31:44.181509 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
12750 16:31:44.181602 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
12751 16:31:44.181925 arm64_za-ptrace_Set_VL_304 pass
12752 16:31:44.186120 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
12753 16:31:44.186424 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
12754 16:31:44.186528 arm64_za-ptrace_Set_VL_320 pass
12755 16:31:44.186633 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
12756 16:31:44.186929 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
12757 16:31:44.187047 arm64_za-ptrace_Set_VL_336 pass
12758 16:31:44.187349 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
12759 16:31:44.187465 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
12760 16:31:44.187767 arm64_za-ptrace_Set_VL_352 pass
12761 16:31:44.187874 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
12762 16:31:44.187983 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
12763 16:31:44.188287 arm64_za-ptrace_Set_VL_368 pass
12764 16:31:44.188562 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
12765 16:31:44.188872 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
12766 16:31:44.188974 arm64_za-ptrace_Set_VL_384 pass
12767 16:31:44.189272 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
12768 16:31:44.189591 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
12769 16:31:44.189700 arm64_za-ptrace_Set_VL_400 pass
12770 16:31:44.189830 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
12771 16:31:44.194058 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
12772 16:31:44.194377 arm64_za-ptrace_Set_VL_416 pass
12773 16:31:44.194724 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
12774 16:31:44.195227 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
12775 16:31:44.195332 arm64_za-ptrace_Set_VL_432 pass
12776 16:31:44.195686 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
12777 16:31:44.196004 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
12778 16:31:44.196123 arm64_za-ptrace_Set_VL_448 pass
12779 16:31:44.196408 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
12780 16:31:44.196886 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
12781 16:31:44.197006 arm64_za-ptrace_Set_VL_464 pass
12782 16:31:44.197418 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
12783 16:31:44.197691 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
12784 16:31:44.197793 arm64_za-ptrace_Set_VL_480 pass
12785 16:31:44.197923 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
12786 16:31:44.202074 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
12787 16:31:44.202813 arm64_za-ptrace_Set_VL_496 pass
12788 16:31:44.203111 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
12789 16:31:44.203387 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
12790 16:31:44.203655 arm64_za-ptrace_Set_VL_512 pass
12791 16:31:44.203915 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
12792 16:31:44.204173 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
12793 16:31:44.204424 arm64_za-ptrace_Set_VL_528 pass
12794 16:31:44.204498 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
12795 16:31:44.204928 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
12796 16:31:44.205369 arm64_za-ptrace_Set_VL_544 pass
12797 16:31:44.205821 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
12798 16:31:44.214035 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
12799 16:31:44.214338 arm64_za-ptrace_Set_VL_560 pass
12800 16:31:44.214435 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
12801 16:31:44.214717 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
12802 16:31:44.214833 arm64_za-ptrace_Set_VL_576 pass
12803 16:31:44.214958 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
12804 16:31:44.215288 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
12805 16:31:44.215805 arm64_za-ptrace_Set_VL_592 pass
12806 16:31:44.216117 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
12807 16:31:44.216424 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
12808 16:31:44.216516 arm64_za-ptrace_Set_VL_608 pass
12809 16:31:44.217003 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
12810 16:31:44.217291 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
12811 16:31:44.217603 arm64_za-ptrace_Set_VL_624 pass
12812 16:31:44.217935 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
12813 16:31:44.222110 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
12814 16:31:44.222420 arm64_za-ptrace_Set_VL_640 pass
12815 16:31:44.222753 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
12816 16:31:44.222885 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
12817 16:31:44.223200 arm64_za-ptrace_Set_VL_656 pass
12818 16:31:44.223335 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
12819 16:31:44.223674 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
12820 16:31:44.223793 arm64_za-ptrace_Set_VL_672 pass
12821 16:31:44.224096 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
12822 16:31:44.224199 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
12823 16:31:44.224302 arm64_za-ptrace_Set_VL_688 pass
12824 16:31:44.224404 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
12825 16:31:44.224711 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
12826 16:31:44.224817 arm64_za-ptrace_Set_VL_704 pass
12827 16:31:44.224928 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
12828 16:31:44.225055 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
12829 16:31:44.225357 arm64_za-ptrace_Set_VL_720 pass
12830 16:31:44.225471 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
12831 16:31:44.225786 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
12832 16:31:44.226103 arm64_za-ptrace_Set_VL_736 pass
12833 16:31:44.230059 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
12834 16:31:44.230370 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
12835 16:31:44.230507 arm64_za-ptrace_Set_VL_752 pass
12836 16:31:44.231202 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
12837 16:31:44.231721 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
12838 16:31:44.231837 arm64_za-ptrace_Set_VL_768 pass
12839 16:31:44.231976 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
12840 16:31:44.232505 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
12841 16:31:44.232835 arm64_za-ptrace_Set_VL_784 pass
12842 16:31:44.233157 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
12843 16:31:44.233453 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
12844 16:31:44.233563 arm64_za-ptrace_Set_VL_800 pass
12845 16:31:44.234087 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
12846 16:31:44.238259 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
12847 16:31:44.238382 arm64_za-ptrace_Set_VL_816 pass
12848 16:31:44.238757 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
12849 16:31:44.238861 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
12850 16:31:44.238962 arm64_za-ptrace_Set_VL_832 pass
12851 16:31:44.239259 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
12852 16:31:44.239377 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
12853 16:31:44.239489 arm64_za-ptrace_Set_VL_848 pass
12854 16:31:44.239791 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
12855 16:31:44.239904 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
12856 16:31:44.240388 arm64_za-ptrace_Set_VL_864 pass
12857 16:31:44.240493 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
12858 16:31:44.240596 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
12859 16:31:44.240696 arm64_za-ptrace_Set_VL_880 pass
12860 16:31:44.240790 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
12861 16:31:44.241085 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
12862 16:31:44.241400 arm64_za-ptrace_Set_VL_896 pass
12863 16:31:44.241515 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
12864 16:31:44.241825 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
12865 16:31:44.241931 arm64_za-ptrace_Set_VL_912 pass
12866 16:31:44.246117 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
12867 16:31:44.246648 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
12868 16:31:44.246752 arm64_za-ptrace_Set_VL_928 pass
12869 16:31:44.246882 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
12870 16:31:44.247197 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
12871 16:31:44.247512 arm64_za-ptrace_Set_VL_944 pass
12872 16:31:44.247635 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
12873 16:31:44.248131 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
12874 16:31:44.248644 arm64_za-ptrace_Set_VL_960 pass
12875 16:31:44.248958 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
12876 16:31:44.249266 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
12877 16:31:44.249386 arm64_za-ptrace_Set_VL_976 pass
12878 16:31:44.249683 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
12879 16:31:44.249994 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
12880 16:31:44.254273 arm64_za-ptrace_Set_VL_992 pass
12881 16:31:44.254570 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
12882 16:31:44.254691 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
12883 16:31:44.254795 arm64_za-ptrace_Set_VL_1008 pass
12884 16:31:44.255097 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
12885 16:31:44.255406 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
12886 16:31:44.255507 arm64_za-ptrace_Set_VL_1024 pass
12887 16:31:44.255608 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
12888 16:31:44.255691 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
12889 16:31:44.255792 arm64_za-ptrace_Set_VL_1040 pass
12890 16:31:44.255893 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
12891 16:31:44.255995 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
12892 16:31:44.256083 arm64_za-ptrace_Set_VL_1056 pass
12893 16:31:44.256181 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
12894 16:31:44.256478 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
12895 16:31:44.256607 arm64_za-ptrace_Set_VL_1072 pass
12896 16:31:44.256713 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
12897 16:31:44.256832 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
12898 16:31:44.256939 arm64_za-ptrace_Set_VL_1088 pass
12899 16:31:44.257241 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
12900 16:31:44.257324 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
12901 16:31:44.257402 arm64_za-ptrace_Set_VL_1104 pass
12902 16:31:44.257468 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
12903 16:31:44.257532 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
12904 16:31:44.257607 arm64_za-ptrace_Set_VL_1120 pass
12905 16:31:44.257890 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
12906 16:31:44.257994 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
12907 16:31:44.258079 arm64_za-ptrace_Set_VL_1136 pass
12908 16:31:44.258176 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
12909 16:31:44.258275 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
12910 16:31:44.258360 arm64_za-ptrace_Set_VL_1152 pass
12911 16:31:44.258458 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
12912 16:31:44.258542 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
12913 16:31:44.262352 arm64_za-ptrace_Set_VL_1168 pass
12914 16:31:44.262457 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
12915 16:31:44.262962 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
12916 16:31:44.263067 arm64_za-ptrace_Set_VL_1184 pass
12917 16:31:44.263353 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
12918 16:31:44.263457 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
12919 16:31:44.263558 arm64_za-ptrace_Set_VL_1200 pass
12920 16:31:44.263643 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
12921 16:31:44.263740 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
12922 16:31:44.263839 arm64_za-ptrace_Set_VL_1216 pass
12923 16:31:44.264132 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
12924 16:31:44.264446 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
12925 16:31:44.264584 arm64_za-ptrace_Set_VL_1232 pass
12926 16:31:44.264725 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
12927 16:31:44.265048 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
12928 16:31:44.265176 arm64_za-ptrace_Set_VL_1248 pass
12929 16:31:44.265306 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
12930 16:31:44.265607 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
12931 16:31:44.265719 arm64_za-ptrace_Set_VL_1264 pass
12932 16:31:44.265823 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
12933 16:31:44.266157 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
12934 16:31:44.266260 arm64_za-ptrace_Set_VL_1280 pass
12935 16:31:44.266343 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
12936 16:31:44.266435 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
12937 16:31:44.266713 arm64_za-ptrace_Set_VL_1296 pass
12938 16:31:44.266795 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
12939 16:31:44.266859 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
12940 16:31:44.266931 arm64_za-ptrace_Set_VL_1312 pass
12941 16:31:44.266993 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
12942 16:31:44.267054 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
12943 16:31:44.267125 arm64_za-ptrace_Set_VL_1328 pass
12944 16:31:44.267188 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
12945 16:31:44.267258 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
12946 16:31:44.267517 arm64_za-ptrace_Set_VL_1344 pass
12947 16:31:44.267622 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
12948 16:31:44.267725 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
12949 16:31:44.267813 arm64_za-ptrace_Set_VL_1360 pass
12950 16:31:44.267912 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
12951 16:31:44.268012 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
12952 16:31:44.268296 arm64_za-ptrace_Set_VL_1376 pass
12953 16:31:44.268400 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
12954 16:31:44.268501 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
12955 16:31:44.268588 arm64_za-ptrace_Set_VL_1392 pass
12956 16:31:44.268685 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
12957 16:31:44.268784 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
12958 16:31:44.268869 arm64_za-ptrace_Set_VL_1408 pass
12959 16:31:44.268965 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
12960 16:31:44.269249 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
12961 16:31:44.269353 arm64_za-ptrace_Set_VL_1424 pass
12962 16:31:44.269453 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
12963 16:31:44.269553 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
12964 16:31:44.269638 arm64_za-ptrace_Set_VL_1440 pass
12965 16:31:44.269741 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
12966 16:31:44.269838 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
12967 16:31:44.269923 arm64_za-ptrace_Set_VL_1456 pass
12968 16:31:44.270206 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
12969 16:31:44.270310 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
12970 16:31:44.270411 arm64_za-ptrace_Set_VL_1472 pass
12971 16:31:44.270496 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
12972 16:31:44.270593 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
12973 16:31:44.270678 arm64_za-ptrace_Set_VL_1488 pass
12974 16:31:44.270777 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
12975 16:31:44.271060 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
12976 16:31:44.271161 arm64_za-ptrace_Set_VL_1504 pass
12977 16:31:44.271264 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
12978 16:31:44.271366 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
12979 16:31:44.271454 arm64_za-ptrace_Set_VL_1520 pass
12980 16:31:44.271556 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
12981 16:31:44.282756 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
12982 16:31:44.283070 arm64_za-ptrace_Set_VL_1536 pass
12983 16:31:44.283383 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
12984 16:31:44.283687 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
12985 16:31:44.283794 arm64_za-ptrace_Set_VL_1552 pass
12986 16:31:44.283924 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
12987 16:31:44.284255 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
12988 16:31:44.284361 arm64_za-ptrace_Set_VL_1568 pass
12989 16:31:44.284693 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
12990 16:31:44.284820 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
12991 16:31:44.284946 arm64_za-ptrace_Set_VL_1584 pass
12992 16:31:44.285462 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
12993 16:31:44.285585 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
12994 16:31:44.285699 arm64_za-ptrace_Set_VL_1600 pass
12995 16:31:44.286027 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
12996 16:31:44.290106 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
12997 16:31:44.290424 arm64_za-ptrace_Set_VL_1616 pass
12998 16:31:44.290527 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
12999 16:31:44.290628 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13000 16:31:44.290922 arm64_za-ptrace_Set_VL_1632 pass
13001 16:31:44.291039 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13002 16:31:44.291139 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13003 16:31:44.291433 arm64_za-ptrace_Set_VL_1648 pass
13004 16:31:44.291555 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13005 16:31:44.291655 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13006 16:31:44.291754 arm64_za-ptrace_Set_VL_1664 pass
13007 16:31:44.292064 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13008 16:31:44.292181 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13009 16:31:44.292462 arm64_za-ptrace_Set_VL_1680 pass
13010 16:31:44.292565 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13011 16:31:44.292667 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13012 16:31:44.292764 arm64_za-ptrace_Set_VL_1696 pass
13013 16:31:44.292863 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13014 16:31:44.293163 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13015 16:31:44.293271 arm64_za-ptrace_Set_VL_1712 pass
13016 16:31:44.293372 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13017 16:31:44.293474 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13018 16:31:44.293575 arm64_za-ptrace_Set_VL_1728 pass
13019 16:31:44.293682 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13020 16:31:44.293783 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13021 16:31:44.294086 arm64_za-ptrace_Set_VL_1744 pass
13022 16:31:44.294193 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13023 16:31:44.298456 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13024 16:31:44.298573 arm64_za-ptrace_Set_VL_1760 pass
13025 16:31:44.298672 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13026 16:31:44.298971 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13027 16:31:44.299281 arm64_za-ptrace_Set_VL_1776 pass
13028 16:31:44.299603 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13029 16:31:44.299718 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13030 16:31:44.300011 arm64_za-ptrace_Set_VL_1792 pass
13031 16:31:44.300320 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13032 16:31:44.300825 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13033 16:31:44.300927 arm64_za-ptrace_Set_VL_1808 pass
13034 16:31:44.301014 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13035 16:31:44.301111 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13036 16:31:44.301190 arm64_za-ptrace_Set_VL_1824 pass
13037 16:31:44.301288 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13038 16:31:44.301583 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13039 16:31:44.301713 arm64_za-ptrace_Set_VL_1840 pass
13040 16:31:44.301840 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13041 16:31:44.310020 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13042 16:31:44.310320 arm64_za-ptrace_Set_VL_1856 pass
13043 16:31:44.310457 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13044 16:31:44.310594 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13045 16:31:44.310703 arm64_za-ptrace_Set_VL_1872 pass
13046 16:31:44.310832 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13047 16:31:44.310992 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13048 16:31:44.311134 arm64_za-ptrace_Set_VL_1888 pass
13049 16:31:44.311269 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13050 16:31:44.311599 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13051 16:31:44.311735 arm64_za-ptrace_Set_VL_1904 pass
13052 16:31:44.311851 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13053 16:31:44.311979 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13054 16:31:44.312106 arm64_za-ptrace_Set_VL_1920 pass
13055 16:31:44.312234 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13056 16:31:44.312356 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13057 16:31:44.312492 arm64_za-ptrace_Set_VL_1936 pass
13058 16:31:44.312624 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13059 16:31:44.312746 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13060 16:31:44.312877 arm64_za-ptrace_Set_VL_1952 pass
13061 16:31:44.313200 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13062 16:31:44.313900 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13063 16:31:44.318132 arm64_za-ptrace_Set_VL_1968 pass
13064 16:31:44.318441 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13065 16:31:44.318556 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13066 16:31:44.318666 arm64_za-ptrace_Set_VL_1984 pass
13067 16:31:44.318959 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13068 16:31:44.319084 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13069 16:31:44.319211 arm64_za-ptrace_Set_VL_2000 pass
13070 16:31:44.319336 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13071 16:31:44.319660 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13072 16:31:44.319764 arm64_za-ptrace_Set_VL_2016 pass
13073 16:31:44.319946 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13074 16:31:44.320262 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13075 16:31:44.320396 arm64_za-ptrace_Set_VL_2032 pass
13076 16:31:44.320719 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13077 16:31:44.320852 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13078 16:31:44.320979 arm64_za-ptrace_Set_VL_2048 pass
13079 16:31:44.321319 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13080 16:31:44.321845 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13081 16:31:44.321962 arm64_za-ptrace_Set_VL_2064 pass
13082 16:31:44.326074 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13083 16:31:44.326373 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13084 16:31:44.326478 arm64_za-ptrace_Set_VL_2080 pass
13085 16:31:44.326769 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13086 16:31:44.326872 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13087 16:31:44.326976 arm64_za-ptrace_Set_VL_2096 pass
13088 16:31:44.327271 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13089 16:31:44.327393 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13090 16:31:44.327716 arm64_za-ptrace_Set_VL_2112 pass
13091 16:31:44.327852 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13092 16:31:44.327980 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13093 16:31:44.328114 arm64_za-ptrace_Set_VL_2128 pass
13094 16:31:44.328258 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13095 16:31:44.328586 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13096 16:31:44.328691 arm64_za-ptrace_Set_VL_2144 pass
13097 16:31:44.328992 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13098 16:31:44.329109 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13099 16:31:44.329212 arm64_za-ptrace_Set_VL_2160 pass
13100 16:31:44.329500 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13101 16:31:44.329604 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13102 16:31:44.329910 arm64_za-ptrace_Set_VL_2176 pass
13103 16:31:44.330027 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13104 16:31:44.334079 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13105 16:31:44.334581 arm64_za-ptrace_Set_VL_2192 pass
13106 16:31:44.335119 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13107 16:31:44.335232 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13108 16:31:44.335365 arm64_za-ptrace_Set_VL_2208 pass
13109 16:31:44.335480 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13110 16:31:44.335608 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13111 16:31:44.335738 arm64_za-ptrace_Set_VL_2224 pass
13112 16:31:44.335868 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13113 16:31:44.336192 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13114 16:31:44.336311 arm64_za-ptrace_Set_VL_2240 pass
13115 16:31:44.336616 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13116 16:31:44.336926 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13117 16:31:44.337029 arm64_za-ptrace_Set_VL_2256 pass
13118 16:31:44.337133 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13119 16:31:44.337224 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13120 16:31:44.337550 arm64_za-ptrace_Set_VL_2272 pass
13121 16:31:44.337677 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13122 16:31:44.342101 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13123 16:31:44.342594 arm64_za-ptrace_Set_VL_2288 pass
13124 16:31:44.342916 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13125 16:31:44.343024 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13126 16:31:44.343127 arm64_za-ptrace_Set_VL_2304 pass
13127 16:31:44.343212 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13128 16:31:44.343314 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13129 16:31:44.343415 arm64_za-ptrace_Set_VL_2320 pass
13130 16:31:44.343515 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13131 16:31:44.343774 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13132 16:31:44.344282 arm64_za-ptrace_Set_VL_2336 pass
13133 16:31:44.344399 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13134 16:31:44.344701 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13135 16:31:44.344804 arm64_za-ptrace_Set_VL_2352 pass
13136 16:31:44.344907 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13137 16:31:44.345194 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13138 16:31:44.345311 arm64_za-ptrace_Set_VL_2368 pass
13139 16:31:44.345609 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13140 16:31:44.345732 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13141 16:31:44.345921 arm64_za-ptrace_Set_VL_2384 pass
13142 16:31:44.350366 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13143 16:31:44.350487 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13144 16:31:44.350591 arm64_za-ptrace_Set_VL_2400 pass
13145 16:31:44.350877 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13146 16:31:44.350995 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13147 16:31:44.351097 arm64_za-ptrace_Set_VL_2416 pass
13148 16:31:44.351196 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13149 16:31:44.351490 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13150 16:31:44.351608 arm64_za-ptrace_Set_VL_2432 pass
13151 16:31:44.351907 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13152 16:31:44.352026 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13153 16:31:44.352157 arm64_za-ptrace_Set_VL_2448 pass
13154 16:31:44.352258 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13155 16:31:44.352556 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13156 16:31:44.352660 arm64_za-ptrace_Set_VL_2464 pass
13157 16:31:44.352960 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13158 16:31:44.353063 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13159 16:31:44.353160 arm64_za-ptrace_Set_VL_2480 pass
13160 16:31:44.353457 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13161 16:31:44.353563 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13162 16:31:44.353890 arm64_za-ptrace_Set_VL_2496 pass
13163 16:31:44.353994 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13164 16:31:44.358166 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13165 16:31:44.358447 arm64_za-ptrace_Set_VL_2512 pass
13166 16:31:44.358563 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13167 16:31:44.358856 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13168 16:31:44.358939 arm64_za-ptrace_Set_VL_2528 pass
13169 16:31:44.359049 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13170 16:31:44.359140 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13171 16:31:44.359411 arm64_za-ptrace_Set_VL_2544 pass
13172 16:31:44.359517 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13173 16:31:44.360023 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13174 16:31:44.360126 arm64_za-ptrace_Set_VL_2560 pass
13175 16:31:44.360210 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13176 16:31:44.360511 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13177 16:31:44.360617 arm64_za-ptrace_Set_VL_2576 pass
13178 16:31:44.360718 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13179 16:31:44.360804 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13180 16:31:44.360888 arm64_za-ptrace_Set_VL_2592 pass
13181 16:31:44.360984 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13182 16:31:44.361081 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13183 16:31:44.361180 arm64_za-ptrace_Set_VL_2608 pass
13184 16:31:44.361278 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13185 16:31:44.361376 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13186 16:31:44.361695 arm64_za-ptrace_Set_VL_2624 pass
13187 16:31:44.361799 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13188 16:31:44.361900 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13189 16:31:44.366072 arm64_za-ptrace_Set_VL_2640 pass
13190 16:31:44.366378 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13191 16:31:44.366694 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13192 16:31:44.366809 arm64_za-ptrace_Set_VL_2656 pass
13193 16:31:44.367105 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13194 16:31:44.367222 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13195 16:31:44.367334 arm64_za-ptrace_Set_VL_2672 pass
13196 16:31:44.367630 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13197 16:31:44.367748 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13198 16:31:44.368045 arm64_za-ptrace_Set_VL_2688 pass
13199 16:31:44.368163 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13200 16:31:44.368265 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13201 16:31:44.368348 arm64_za-ptrace_Set_VL_2704 pass
13202 16:31:44.368447 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13203 16:31:44.368744 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13204 16:31:44.368850 arm64_za-ptrace_Set_VL_2720 pass
13205 16:31:44.368965 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13206 16:31:44.369087 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13207 16:31:44.369185 arm64_za-ptrace_Set_VL_2736 pass
13208 16:31:44.369306 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13209 16:31:44.369414 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13210 16:31:44.369543 arm64_za-ptrace_Set_VL_2752 pass
13211 16:31:44.369658 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13212 16:31:44.369786 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13213 16:31:44.369895 arm64_za-ptrace_Set_VL_2768 pass
13214 16:31:44.370015 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13215 16:31:44.374154 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13216 16:31:44.374262 arm64_za-ptrace_Set_VL_2784 pass
13217 16:31:44.374530 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13218 16:31:44.374651 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13219 16:31:44.374739 arm64_za-ptrace_Set_VL_2800 pass
13220 16:31:44.375049 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13221 16:31:44.375380 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13222 16:31:44.375496 arm64_za-ptrace_Set_VL_2816 pass
13223 16:31:44.375792 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13224 16:31:44.376105 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13225 16:31:44.376207 arm64_za-ptrace_Set_VL_2832 pass
13226 16:31:44.376293 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13227 16:31:44.376393 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13228 16:31:44.376685 arm64_za-ptrace_Set_VL_2848 pass
13229 16:31:44.376808 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13230 16:31:44.377125 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13231 16:31:44.377438 arm64_za-ptrace_Set_VL_2864 pass
13232 16:31:44.377756 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13233 16:31:44.377871 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13234 16:31:44.385813 arm64_za-ptrace_Set_VL_2880 pass
13235 16:31:44.386129 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13236 16:31:44.386233 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13237 16:31:44.386320 arm64_za-ptrace_Set_VL_2896 pass
13238 16:31:44.386404 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13239 16:31:44.386488 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13240 16:31:44.386571 arm64_za-ptrace_Set_VL_2912 pass
13241 16:31:44.386654 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13242 16:31:44.386738 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13243 16:31:44.386821 arm64_za-ptrace_Set_VL_2928 pass
13244 16:31:44.386903 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13245 16:31:44.386986 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13246 16:31:44.387068 arm64_za-ptrace_Set_VL_2944 pass
13247 16:31:44.387151 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13248 16:31:44.387234 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13249 16:31:44.387317 arm64_za-ptrace_Set_VL_2960 pass
13250 16:31:44.387399 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13251 16:31:44.387482 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13252 16:31:44.387563 arm64_za-ptrace_Set_VL_2976 pass
13253 16:31:44.387648 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13254 16:31:44.387751 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13255 16:31:44.387841 arm64_za-ptrace_Set_VL_2992 pass
13256 16:31:44.387924 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13257 16:31:44.388008 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13258 16:31:44.388090 arm64_za-ptrace_Set_VL_3008 pass
13259 16:31:44.388173 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13260 16:31:44.388255 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13261 16:31:44.388338 arm64_za-ptrace_Set_VL_3024 pass
13262 16:31:44.388420 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13263 16:31:44.388503 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13264 16:31:44.388585 arm64_za-ptrace_Set_VL_3040 pass
13265 16:31:44.388666 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13266 16:31:44.388749 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13267 16:31:44.388830 arm64_za-ptrace_Set_VL_3056 pass
13268 16:31:44.388912 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13269 16:31:44.388994 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13270 16:31:44.389077 arm64_za-ptrace_Set_VL_3072 pass
13271 16:31:44.389159 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13272 16:31:44.389241 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13273 16:31:44.389329 arm64_za-ptrace_Set_VL_3088 pass
13274 16:31:44.389412 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13275 16:31:44.390132 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13276 16:31:44.390431 arm64_za-ptrace_Set_VL_3104 pass
13277 16:31:44.390734 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13278 16:31:44.390836 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13279 16:31:44.390937 arm64_za-ptrace_Set_VL_3120 pass
13280 16:31:44.391023 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13281 16:31:44.391120 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13282 16:31:44.391203 arm64_za-ptrace_Set_VL_3136 pass
13283 16:31:44.391300 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13284 16:31:44.391397 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13285 16:31:44.391681 arm64_za-ptrace_Set_VL_3152 pass
13286 16:31:44.391784 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13287 16:31:44.391883 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13288 16:31:44.391979 arm64_za-ptrace_Set_VL_3168 pass
13289 16:31:44.392074 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13290 16:31:44.392364 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13291 16:31:44.392467 arm64_za-ptrace_Set_VL_3184 pass
13292 16:31:44.392759 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13293 16:31:44.392863 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13294 16:31:44.392963 arm64_za-ptrace_Set_VL_3200 pass
13295 16:31:44.393048 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13296 16:31:44.393145 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13297 16:31:44.393230 arm64_za-ptrace_Set_VL_3216 pass
13298 16:31:44.393324 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13299 16:31:44.393422 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13300 16:31:44.393520 arm64_za-ptrace_Set_VL_3232 pass
13301 16:31:44.393618 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13302 16:31:44.393928 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13303 16:31:44.394032 arm64_za-ptrace_Set_VL_3248 pass
13304 16:31:44.394118 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13305 16:31:44.398316 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13306 16:31:44.398432 arm64_za-ptrace_Set_VL_3264 pass
13307 16:31:44.398534 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13308 16:31:44.398633 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13309 16:31:44.398734 arm64_za-ptrace_Set_VL_3280 pass
13310 16:31:44.398835 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13311 16:31:44.399119 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13312 16:31:44.399237 arm64_za-ptrace_Set_VL_3296 pass
13313 16:31:44.399336 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13314 16:31:44.399419 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13315 16:31:44.399515 arm64_za-ptrace_Set_VL_3312 pass
13316 16:31:44.399612 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13317 16:31:44.399710 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13318 16:31:44.400004 arm64_za-ptrace_Set_VL_3328 pass
13319 16:31:44.400137 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13320 16:31:44.400267 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13321 16:31:44.400361 arm64_za-ptrace_Set_VL_3344 pass
13322 16:31:44.400460 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13323 16:31:44.400558 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13324 16:31:44.400789 arm64_za-ptrace_Set_VL_3360 pass
13325 16:31:44.400893 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13326 16:31:44.400995 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13327 16:31:44.401081 arm64_za-ptrace_Set_VL_3376 pass
13328 16:31:44.401179 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13329 16:31:44.401275 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13330 16:31:44.401577 arm64_za-ptrace_Set_VL_3392 pass
13331 16:31:44.401701 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13332 16:31:44.402074 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13333 16:31:44.406159 arm64_za-ptrace_Set_VL_3408 pass
13334 16:31:44.406454 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13335 16:31:44.406558 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13336 16:31:44.406659 arm64_za-ptrace_Set_VL_3424 pass
13337 16:31:44.406757 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13338 16:31:44.406855 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13339 16:31:44.406953 arm64_za-ptrace_Set_VL_3440 pass
13340 16:31:44.407247 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13341 16:31:44.407351 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13342 16:31:44.407458 arm64_za-ptrace_Set_VL_3456 pass
13343 16:31:44.407583 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13344 16:31:44.407703 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13345 16:31:44.407993 arm64_za-ptrace_Set_VL_3472 pass
13346 16:31:44.408109 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13347 16:31:44.408211 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13348 16:31:44.408309 arm64_za-ptrace_Set_VL_3488 pass
13349 16:31:44.408604 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13350 16:31:44.408726 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13351 16:31:44.408812 arm64_za-ptrace_Set_VL_3504 pass
13352 16:31:44.408917 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13353 16:31:44.409203 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13354 16:31:44.409303 arm64_za-ptrace_Set_VL_3520 pass
13355 16:31:44.409402 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13356 16:31:44.409498 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13357 16:31:44.409595 arm64_za-ptrace_Set_VL_3536 pass
13358 16:31:44.409698 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13359 16:31:44.409996 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13360 16:31:44.414151 arm64_za-ptrace_Set_VL_3552 pass
13361 16:31:44.414459 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13362 16:31:44.414772 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13363 16:31:44.415086 arm64_za-ptrace_Set_VL_3568 pass
13364 16:31:44.415201 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13365 16:31:44.415909 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13366 16:31:44.416024 arm64_za-ptrace_Set_VL_3584 pass
13367 16:31:44.416330 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13368 16:31:44.416431 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13369 16:31:44.416523 arm64_za-ptrace_Set_VL_3600 pass
13370 16:31:44.416817 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13371 16:31:44.417127 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13372 16:31:44.417241 arm64_za-ptrace_Set_VL_3616 pass
13373 16:31:44.417351 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13374 16:31:44.417658 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13375 16:31:44.417786 arm64_za-ptrace_Set_VL_3632 pass
13376 16:31:44.417898 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13377 16:31:44.423140 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13378 16:31:44.423753 arm64_za-ptrace_Set_VL_3648 pass
13379 16:31:44.424053 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13380 16:31:44.424155 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13381 16:31:44.424452 arm64_za-ptrace_Set_VL_3664 pass
13382 16:31:44.424779 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13383 16:31:44.424898 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13384 16:31:44.424986 arm64_za-ptrace_Set_VL_3680 pass
13385 16:31:44.425106 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13386 16:31:44.425422 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13387 16:31:44.425535 arm64_za-ptrace_Set_VL_3696 pass
13388 16:31:44.425663 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13389 16:31:44.425770 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13390 16:31:44.426264 arm64_za-ptrace_Set_VL_3712 pass
13391 16:31:44.426399 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13392 16:31:44.426724 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13393 16:31:44.427043 arm64_za-ptrace_Set_VL_3728 pass
13394 16:31:44.427158 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13395 16:31:44.429700 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13396 16:31:44.429800 arm64_za-ptrace_Set_VL_3744 pass
13397 16:31:44.429881 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13398 16:31:44.429963 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13399 16:31:44.430043 arm64_za-ptrace_Set_VL_3760 pass
13400 16:31:44.430119 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13401 16:31:44.430196 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13402 16:31:44.430272 arm64_za-ptrace_Set_VL_3776 pass
13403 16:31:44.430348 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13404 16:31:44.430425 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13405 16:31:44.430501 arm64_za-ptrace_Set_VL_3792 pass
13406 16:31:44.430592 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13407 16:31:44.438067 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13408 16:31:44.438371 arm64_za-ptrace_Set_VL_3808 pass
13409 16:31:44.438667 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13410 16:31:44.438764 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13411 16:31:44.438843 arm64_za-ptrace_Set_VL_3824 pass
13412 16:31:44.438934 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13413 16:31:44.439014 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13414 16:31:44.439103 arm64_za-ptrace_Set_VL_3840 pass
13415 16:31:44.439193 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13416 16:31:44.439470 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13417 16:31:44.439580 arm64_za-ptrace_Set_VL_3856 pass
13418 16:31:44.439660 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13419 16:31:44.439944 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13420 16:31:44.440041 arm64_za-ptrace_Set_VL_3872 pass
13421 16:31:44.440133 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13422 16:31:44.440420 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13423 16:31:44.440724 arm64_za-ptrace_Set_VL_3888 pass
13424 16:31:44.441028 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13425 16:31:44.441125 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13426 16:31:44.441608 arm64_za-ptrace_Set_VL_3904 pass
13427 16:31:44.441727 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13428 16:31:44.442039 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13429 16:31:44.446229 arm64_za-ptrace_Set_VL_3920 pass
13430 16:31:44.446535 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13431 16:31:44.446631 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13432 16:31:44.446740 arm64_za-ptrace_Set_VL_3936 pass
13433 16:31:44.446848 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13434 16:31:44.446956 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13435 16:31:44.447273 arm64_za-ptrace_Set_VL_3952 pass
13436 16:31:44.447380 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13437 16:31:44.447477 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13438 16:31:44.447575 arm64_za-ptrace_Set_VL_3968 pass
13439 16:31:44.447873 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13440 16:31:44.447978 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13441 16:31:44.448073 arm64_za-ptrace_Set_VL_3984 pass
13442 16:31:44.448356 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13443 16:31:44.448476 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13444 16:31:44.448833 arm64_za-ptrace_Set_VL_4000 pass
13445 16:31:44.448937 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13446 16:31:44.449219 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13447 16:31:44.449327 arm64_za-ptrace_Set_VL_4016 pass
13448 16:31:44.449409 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13449 16:31:44.449503 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13450 16:31:44.449587 arm64_za-ptrace_Set_VL_4032 pass
13451 16:31:44.449672 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13452 16:31:44.449768 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13453 16:31:44.449862 arm64_za-ptrace_Set_VL_4048 pass
13454 16:31:44.454174 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13455 16:31:44.458297 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13456 16:31:44.458513 arm64_za-ptrace_Set_VL_4064 pass
13457 16:31:44.458595 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13458 16:31:44.458673 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13459 16:31:44.458755 arm64_za-ptrace_Set_VL_4080 pass
13460 16:31:44.458833 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13461 16:31:44.458911 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13462 16:31:44.458988 arm64_za-ptrace_Set_VL_4096 pass
13463 16:31:44.459065 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13464 16:31:44.459143 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13465 16:31:44.459225 arm64_za-ptrace_Set_VL_4112 pass
13466 16:31:44.459301 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13467 16:31:44.459378 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13468 16:31:44.459454 arm64_za-ptrace_Set_VL_4128 pass
13469 16:31:44.459532 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13470 16:31:44.459609 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13471 16:31:44.459686 arm64_za-ptrace_Set_VL_4144 pass
13472 16:31:44.459762 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13473 16:31:44.459839 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13474 16:31:44.459916 arm64_za-ptrace_Set_VL_4160 pass
13475 16:31:44.459992 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13476 16:31:44.460068 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13477 16:31:44.460145 arm64_za-ptrace_Set_VL_4176 pass
13478 16:31:44.460222 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13479 16:31:44.460299 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13480 16:31:44.460375 arm64_za-ptrace_Set_VL_4192 pass
13481 16:31:44.460452 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13482 16:31:44.460528 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13483 16:31:44.460604 arm64_za-ptrace_Set_VL_4208 pass
13484 16:31:44.460683 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13485 16:31:44.460759 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13486 16:31:44.460835 arm64_za-ptrace_Set_VL_4224 pass
13487 16:31:44.460911 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13488 16:31:44.460988 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13489 16:31:44.461065 arm64_za-ptrace_Set_VL_4240 pass
13490 16:31:44.461141 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13491 16:31:44.461218 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13492 16:31:44.461295 arm64_za-ptrace_Set_VL_4256 pass
13493 16:31:44.461373 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13494 16:31:44.462096 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13495 16:31:44.462977 arm64_za-ptrace_Set_VL_4272 pass
13496 16:31:44.463883 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13497 16:31:44.464954 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13498 16:31:44.465640 arm64_za-ptrace_Set_VL_4288 pass
13499 16:31:44.470216 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13500 16:31:44.471041 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13501 16:31:44.471350 arm64_za-ptrace_Set_VL_4304 pass
13502 16:31:44.472570 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13503 16:31:44.472659 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13504 16:31:44.473088 arm64_za-ptrace_Set_VL_4320 pass
13505 16:31:44.473189 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13506 16:31:44.473512 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13507 16:31:44.473593 arm64_za-ptrace_Set_VL_4336 pass
13508 16:31:44.473863 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13509 16:31:44.474332 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13510 16:31:44.474433 arm64_za-ptrace_Set_VL_4352 pass
13511 16:31:44.474516 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13512 16:31:44.482171 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13513 16:31:44.482813 arm64_za-ptrace_Set_VL_4368 pass
13514 16:31:44.483133 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13515 16:31:44.483245 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13516 16:31:44.483344 arm64_za-ptrace_Set_VL_4384 pass
13517 16:31:44.483631 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13518 16:31:44.483724 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13519 16:31:44.483799 arm64_za-ptrace_Set_VL_4400 pass
13520 16:31:44.484061 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13521 16:31:44.484173 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13522 16:31:44.484257 arm64_za-ptrace_Set_VL_4416 pass
13523 16:31:44.484546 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13524 16:31:44.484645 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13525 16:31:44.484742 arm64_za-ptrace_Set_VL_4432 pass
13526 16:31:44.484821 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13527 16:31:44.484917 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13528 16:31:44.485014 arm64_za-ptrace_Set_VL_4448 pass
13529 16:31:44.485112 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13530 16:31:44.485393 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13531 16:31:44.485492 arm64_za-ptrace_Set_VL_4464 pass
13532 16:31:44.485575 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13533 16:31:44.485678 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13534 16:31:44.485763 arm64_za-ptrace_Set_VL_4480 pass
13535 16:31:44.485858 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13536 16:31:44.485956 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13537 16:31:44.490309 arm64_za-ptrace_Set_VL_4496 pass
13538 16:31:44.490512 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13539 16:31:44.490811 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13540 16:31:44.490911 arm64_za-ptrace_Set_VL_4512 pass
13541 16:31:44.490996 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13542 16:31:44.491093 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13543 16:31:44.491190 arm64_za-ptrace_Set_VL_4528 pass
13544 16:31:44.491294 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13545 16:31:44.491390 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13546 16:31:44.491490 arm64_za-ptrace_Set_VL_4544 pass
13547 16:31:44.491586 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13548 16:31:44.491870 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13549 16:31:44.491968 arm64_za-ptrace_Set_VL_4560 pass
13550 16:31:44.492051 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13551 16:31:44.492149 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13552 16:31:44.492232 arm64_za-ptrace_Set_VL_4576 pass
13553 16:31:44.492324 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13554 16:31:44.492416 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13555 16:31:44.492707 arm64_za-ptrace_Set_VL_4592 pass
13556 16:31:44.492806 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13557 16:31:44.493415 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13558 16:31:44.493696 arm64_za-ptrace_Set_VL_4608 pass
13559 16:31:44.493799 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13560 16:31:44.493883 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13561 16:31:44.493980 arm64_za-ptrace_Set_VL_4624 pass
13562 16:31:44.494062 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13563 16:31:44.498171 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13564 16:31:44.498508 arm64_za-ptrace_Set_VL_4640 pass
13565 16:31:44.498613 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13566 16:31:44.498709 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13567 16:31:44.498792 arm64_za-ptrace_Set_VL_4656 pass
13568 16:31:44.498885 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13569 16:31:44.498967 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13570 16:31:44.499059 arm64_za-ptrace_Set_VL_4672 pass
13571 16:31:44.499153 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13572 16:31:44.499449 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13573 16:31:44.499564 arm64_za-ptrace_Set_VL_4688 pass
13574 16:31:44.499660 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13575 16:31:44.499753 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13576 16:31:44.499851 arm64_za-ptrace_Set_VL_4704 pass
13577 16:31:44.500137 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13578 16:31:44.500240 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13579 16:31:44.500335 arm64_za-ptrace_Set_VL_4720 pass
13580 16:31:44.500417 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13581 16:31:44.500509 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13582 16:31:44.500590 arm64_za-ptrace_Set_VL_4736 pass
13583 16:31:44.500683 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13584 16:31:44.500979 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13585 16:31:44.501084 arm64_za-ptrace_Set_VL_4752 pass
13586 16:31:44.501178 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13587 16:31:44.501271 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13588 16:31:44.501364 arm64_za-ptrace_Set_VL_4768 pass
13589 16:31:44.501456 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13590 16:31:44.501696 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13591 16:31:44.501805 arm64_za-ptrace_Set_VL_4784 pass
13592 16:31:44.501908 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13593 16:31:44.501992 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13594 16:31:44.506095 arm64_za-ptrace_Set_VL_4800 pass
13595 16:31:44.506387 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13596 16:31:44.506495 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13597 16:31:44.506592 arm64_za-ptrace_Set_VL_4816 pass
13598 16:31:44.506690 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13599 16:31:44.506801 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13600 16:31:44.506909 arm64_za-ptrace_Set_VL_4832 pass
13601 16:31:44.507004 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13602 16:31:44.507293 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13603 16:31:44.507391 arm64_za-ptrace_Set_VL_4848 pass
13604 16:31:44.507483 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13605 16:31:44.507574 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13606 16:31:44.507667 arm64_za-ptrace_Set_VL_4864 pass
13607 16:31:44.507760 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13608 16:31:44.507853 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13609 16:31:44.508141 arm64_za-ptrace_Set_VL_4880 pass
13610 16:31:44.508240 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13611 16:31:44.508334 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13612 16:31:44.508427 arm64_za-ptrace_Set_VL_4896 pass
13613 16:31:44.508721 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13614 16:31:44.508825 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13615 16:31:44.508919 arm64_za-ptrace_Set_VL_4912 pass
13616 16:31:44.509012 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13617 16:31:44.509112 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13618 16:31:44.509399 arm64_za-ptrace_Set_VL_4928 pass
13619 16:31:44.509498 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13620 16:31:44.509592 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13621 16:31:44.509681 arm64_za-ptrace_Set_VL_4944 pass
13622 16:31:44.509775 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13623 16:31:44.514170 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13624 16:31:44.514515 arm64_za-ptrace_Set_VL_4960 pass
13625 16:31:44.514618 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13626 16:31:44.514700 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13627 16:31:44.514795 arm64_za-ptrace_Set_VL_4976 pass
13628 16:31:44.514881 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13629 16:31:44.514974 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13630 16:31:44.515056 arm64_za-ptrace_Set_VL_4992 pass
13631 16:31:44.515147 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13632 16:31:44.515246 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13633 16:31:44.515341 arm64_za-ptrace_Set_VL_5008 pass
13634 16:31:44.515434 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13635 16:31:44.515727 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13636 16:31:44.515830 arm64_za-ptrace_Set_VL_5024 pass
13637 16:31:44.515926 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13638 16:31:44.516008 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13639 16:31:44.516101 arm64_za-ptrace_Set_VL_5040 pass
13640 16:31:44.516217 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13641 16:31:44.516336 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13642 16:31:44.516618 arm64_za-ptrace_Set_VL_5056 pass
13643 16:31:44.516722 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13644 16:31:44.516805 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13645 16:31:44.516898 arm64_za-ptrace_Set_VL_5072 pass
13646 16:31:44.516979 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13647 16:31:44.517235 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13648 16:31:44.517337 arm64_za-ptrace_Set_VL_5088 pass
13649 16:31:44.517432 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13650 16:31:44.517527 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13651 16:31:44.517609 arm64_za-ptrace_Set_VL_5104 pass
13652 16:31:44.517731 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13653 16:31:44.517832 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13654 16:31:44.522383 arm64_za-ptrace_Set_VL_5120 pass
13655 16:31:44.522488 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13656 16:31:44.522772 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13657 16:31:44.522875 arm64_za-ptrace_Set_VL_5136 pass
13658 16:31:44.522957 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13659 16:31:44.523036 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13660 16:31:44.523130 arm64_za-ptrace_Set_VL_5152 pass
13661 16:31:44.523211 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13662 16:31:44.523290 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13663 16:31:44.523369 arm64_za-ptrace_Set_VL_5168 pass
13664 16:31:44.523462 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13665 16:31:44.523542 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13666 16:31:44.523634 arm64_za-ptrace_Set_VL_5184 pass
13667 16:31:44.523727 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13668 16:31:44.524018 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13669 16:31:44.524132 arm64_za-ptrace_Set_VL_5200 pass
13670 16:31:44.524226 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13671 16:31:44.524319 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13672 16:31:44.524400 arm64_za-ptrace_Set_VL_5216 pass
13673 16:31:44.524491 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13674 16:31:44.524770 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13675 16:31:44.525051 arm64_za-ptrace_Set_VL_5232 pass
13676 16:31:44.525150 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13677 16:31:44.525252 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13678 16:31:44.525336 arm64_za-ptrace_Set_VL_5248 pass
13679 16:31:44.525625 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13680 16:31:44.525733 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13681 16:31:44.525814 arm64_za-ptrace_Set_VL_5264 pass
13682 16:31:44.525905 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13683 16:31:44.525984 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13684 16:31:44.530257 arm64_za-ptrace_Set_VL_5280 pass
13685 16:31:44.530552 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13686 16:31:44.530662 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13687 16:31:44.530758 arm64_za-ptrace_Set_VL_5296 pass
13688 16:31:44.531036 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13689 16:31:44.531135 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13690 16:31:44.531227 arm64_za-ptrace_Set_VL_5312 pass
13691 16:31:44.531307 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13692 16:31:44.531598 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13693 16:31:44.531915 arm64_za-ptrace_Set_VL_5328 pass
13694 16:31:44.532020 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13695 16:31:44.532108 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13696 16:31:44.533678 arm64_za-ptrace_Set_VL_5344 pass
13697 16:31:44.533795 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13698 16:31:44.533899 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13699 16:31:44.533996 arm64_za-ptrace_Set_VL_5360 pass
13700 16:31:44.534093 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13701 16:31:44.534189 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13702 16:31:44.534286 arm64_za-ptrace_Set_VL_5376 pass
13703 16:31:44.534381 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13704 16:31:44.534478 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13705 16:31:44.534575 arm64_za-ptrace_Set_VL_5392 pass
13706 16:31:44.534672 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13707 16:31:44.534768 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13708 16:31:44.534865 arm64_za-ptrace_Set_VL_5408 pass
13709 16:31:44.535158 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13710 16:31:44.538096 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13711 16:31:44.538375 arm64_za-ptrace_Set_VL_5424 pass
13712 16:31:44.538494 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13713 16:31:44.538593 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13714 16:31:44.538884 arm64_za-ptrace_Set_VL_5440 pass
13715 16:31:44.538989 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13716 16:31:44.539087 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13717 16:31:44.539379 arm64_za-ptrace_Set_VL_5456 pass
13718 16:31:44.539497 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
13719 16:31:44.539931 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
13720 16:31:44.540033 arm64_za-ptrace_Set_VL_5472 pass
13721 16:31:44.540130 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
13722 16:31:44.540212 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
13723 16:31:44.540305 arm64_za-ptrace_Set_VL_5488 pass
13724 16:31:44.540594 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
13725 16:31:44.540703 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
13726 16:31:44.540802 arm64_za-ptrace_Set_VL_5504 pass
13727 16:31:44.540884 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
13728 16:31:44.540978 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
13729 16:31:44.541072 arm64_za-ptrace_Set_VL_5520 pass
13730 16:31:44.541167 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
13731 16:31:44.541446 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
13732 16:31:44.541552 arm64_za-ptrace_Set_VL_5536 pass
13733 16:31:44.541654 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
13734 16:31:44.541755 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
13735 16:31:44.541852 arm64_za-ptrace_Set_VL_5552 pass
13736 16:31:44.542144 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
13737 16:31:44.546311 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
13738 16:31:44.546416 arm64_za-ptrace_Set_VL_5568 pass
13739 16:31:44.546513 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
13740 16:31:44.546606 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
13741 16:31:44.546699 arm64_za-ptrace_Set_VL_5584 pass
13742 16:31:44.546791 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
13743 16:31:44.547090 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
13744 16:31:44.547192 arm64_za-ptrace_Set_VL_5600 pass
13745 16:31:44.547288 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
13746 16:31:44.547383 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
13747 16:31:44.547464 arm64_za-ptrace_Set_VL_5616 pass
13748 16:31:44.547745 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
13749 16:31:44.548217 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
13750 16:31:44.548319 arm64_za-ptrace_Set_VL_5632 pass
13751 16:31:44.548418 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
13752 16:31:44.548515 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
13753 16:31:44.548610 arm64_za-ptrace_Set_VL_5648 pass
13754 16:31:44.548699 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
13755 16:31:44.548997 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
13756 16:31:44.549100 arm64_za-ptrace_Set_VL_5664 pass
13757 16:31:44.549196 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
13758 16:31:44.549279 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
13759 16:31:44.549373 arm64_za-ptrace_Set_VL_5680 pass
13760 16:31:44.549468 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
13761 16:31:44.549758 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
13762 16:31:44.549842 arm64_za-ptrace_Set_VL_5696 pass
13763 16:31:44.549922 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
13764 16:31:44.554255 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
13765 16:31:44.554569 arm64_za-ptrace_Set_VL_5712 pass
13766 16:31:44.554682 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
13767 16:31:44.554777 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
13768 16:31:44.554889 arm64_za-ptrace_Set_VL_5728 pass
13769 16:31:44.555016 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
13770 16:31:44.555116 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
13771 16:31:44.555224 arm64_za-ptrace_Set_VL_5744 pass
13772 16:31:44.555335 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
13773 16:31:44.555435 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
13774 16:31:44.555520 arm64_za-ptrace_Set_VL_5760 pass
13775 16:31:44.555601 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
13776 16:31:44.555696 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
13777 16:31:44.555979 arm64_za-ptrace_Set_VL_5776 pass
13778 16:31:44.556083 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
13779 16:31:44.556167 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
13780 16:31:44.556262 arm64_za-ptrace_Set_VL_5792 pass
13781 16:31:44.556360 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
13782 16:31:44.556443 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
13783 16:31:44.556733 arm64_za-ptrace_Set_VL_5808 pass
13784 16:31:44.557038 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
13785 16:31:44.557144 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
13786 16:31:44.557229 arm64_za-ptrace_Set_VL_5824 pass
13787 16:31:44.557312 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
13788 16:31:44.557409 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
13789 16:31:44.557508 arm64_za-ptrace_Set_VL_5840 pass
13790 16:31:44.557605 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
13791 16:31:44.557899 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
13792 16:31:44.558004 arm64_za-ptrace_Set_VL_5856 pass
13793 16:31:44.562159 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
13794 16:31:44.562420 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
13795 16:31:44.562686 arm64_za-ptrace_Set_VL_5872 pass
13796 16:31:44.562794 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
13797 16:31:44.562896 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
13798 16:31:44.562984 arm64_za-ptrace_Set_VL_5888 pass
13799 16:31:44.563070 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
13800 16:31:44.563341 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
13801 16:31:44.563445 arm64_za-ptrace_Set_VL_5904 pass
13802 16:31:44.563533 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
13803 16:31:44.563633 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
13804 16:31:44.563719 arm64_za-ptrace_Set_VL_5920 pass
13805 16:31:44.563819 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
13806 16:31:44.563920 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
13807 16:31:44.564037 arm64_za-ptrace_Set_VL_5936 pass
13808 16:31:44.564172 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
13809 16:31:44.564290 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
13810 16:31:44.564576 arm64_za-ptrace_Set_VL_5952 pass
13811 16:31:44.564698 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
13812 16:31:44.564784 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
13813 16:31:44.564879 arm64_za-ptrace_Set_VL_5968 pass
13814 16:31:44.565182 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
13815 16:31:44.565281 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
13816 16:31:44.565375 arm64_za-ptrace_Set_VL_5984 pass
13817 16:31:44.565472 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
13818 16:31:44.565546 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
13819 16:31:44.565622 arm64_za-ptrace_Set_VL_6000 pass
13820 16:31:44.565748 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
13821 16:31:44.565849 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
13822 16:31:44.565944 arm64_za-ptrace_Set_VL_6016 pass
13823 16:31:44.570023 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
13824 16:31:44.570334 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
13825 16:31:44.570435 arm64_za-ptrace_Set_VL_6032 pass
13826 16:31:44.570532 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
13827 16:31:44.570616 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
13828 16:31:44.570708 arm64_za-ptrace_Set_VL_6048 pass
13829 16:31:44.570996 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
13830 16:31:44.571097 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
13831 16:31:44.571178 arm64_za-ptrace_Set_VL_6064 pass
13832 16:31:44.571269 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
13833 16:31:44.571349 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
13834 16:31:44.571439 arm64_za-ptrace_Set_VL_6080 pass
13835 16:31:44.571728 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
13836 16:31:44.571830 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
13837 16:31:44.571911 arm64_za-ptrace_Set_VL_6096 pass
13838 16:31:44.572002 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
13839 16:31:44.572082 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
13840 16:31:44.572160 arm64_za-ptrace_Set_VL_6112 pass
13841 16:31:44.572250 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
13842 16:31:44.572341 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
13843 16:31:44.572421 arm64_za-ptrace_Set_VL_6128 pass
13844 16:31:44.572512 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
13845 16:31:44.572804 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
13846 16:31:44.572905 arm64_za-ptrace_Set_VL_6144 pass
13847 16:31:44.573001 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
13848 16:31:44.573093 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
13849 16:31:44.573184 arm64_za-ptrace_Set_VL_6160 pass
13850 16:31:44.573275 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
13851 16:31:44.573562 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
13852 16:31:44.573675 arm64_za-ptrace_Set_VL_6176 pass
13853 16:31:44.573756 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
13854 16:31:44.573847 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
13855 16:31:44.573939 arm64_za-ptrace_Set_VL_6192 pass
13856 16:31:44.578247 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
13857 16:31:44.578365 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
13858 16:31:44.578465 arm64_za-ptrace_Set_VL_6208 pass
13859 16:31:44.578578 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
13860 16:31:44.578881 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
13861 16:31:44.579007 arm64_za-ptrace_Set_VL_6224 pass
13862 16:31:44.579100 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
13863 16:31:44.579199 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
13864 16:31:44.579285 arm64_za-ptrace_Set_VL_6240 pass
13865 16:31:44.579382 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
13866 16:31:44.579508 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
13867 16:31:44.579630 arm64_za-ptrace_Set_VL_6256 pass
13868 16:31:44.579759 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
13869 16:31:44.579861 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
13870 16:31:44.579968 arm64_za-ptrace_Set_VL_6272 pass
13871 16:31:44.580096 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
13872 16:31:44.580204 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
13873 16:31:44.580325 arm64_za-ptrace_Set_VL_6288 pass
13874 16:31:44.580431 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
13875 16:31:44.580544 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
13876 16:31:44.580632 arm64_za-ptrace_Set_VL_6304 pass
13877 16:31:44.580729 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
13878 16:31:44.580850 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
13879 16:31:44.580971 arm64_za-ptrace_Set_VL_6320 pass
13880 16:31:44.581397 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
13881 16:31:44.581481 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
13882 16:31:44.581591 arm64_za-ptrace_Set_VL_6336 pass
13883 16:31:44.581690 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
13884 16:31:44.581816 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
13885 16:31:44.581904 arm64_za-ptrace_Set_VL_6352 pass
13886 16:31:44.586151 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
13887 16:31:44.586449 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
13888 16:31:44.586553 arm64_za-ptrace_Set_VL_6368 pass
13889 16:31:44.586652 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
13890 16:31:44.586750 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
13891 16:31:44.586943 arm64_za-ptrace_Set_VL_6384 pass
13892 16:31:44.587048 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
13893 16:31:44.587145 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
13894 16:31:44.587239 arm64_za-ptrace_Set_VL_6400 pass
13895 16:31:44.587779 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
13896 16:31:44.587882 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
13897 16:31:44.587979 arm64_za-ptrace_Set_VL_6416 pass
13898 16:31:44.588060 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
13899 16:31:44.588152 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
13900 16:31:44.588235 arm64_za-ptrace_Set_VL_6432 pass
13901 16:31:44.588328 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
13902 16:31:44.588562 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
13903 16:31:44.588651 arm64_za-ptrace_Set_VL_6448 pass
13904 16:31:44.588777 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
13905 16:31:44.589109 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
13906 16:31:44.589211 arm64_za-ptrace_Set_VL_6464 pass
13907 16:31:44.589308 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
13908 16:31:44.589620 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
13909 16:31:44.589730 arm64_za-ptrace_Set_VL_6480 pass
13910 16:31:44.589825 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
13911 16:31:44.589919 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
13912 16:31:44.594075 arm64_za-ptrace_Set_VL_6496 pass
13913 16:31:44.594379 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
13914 16:31:44.594480 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
13915 16:31:44.594575 arm64_za-ptrace_Set_VL_6512 pass
13916 16:31:44.594670 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
13917 16:31:44.594787 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
13918 16:31:44.595090 arm64_za-ptrace_Set_VL_6528 pass
13919 16:31:44.595206 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
13920 16:31:44.595499 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
13921 16:31:44.595602 arm64_za-ptrace_Set_VL_6544 pass
13922 16:31:44.595699 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
13923 16:31:44.595781 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
13924 16:31:44.595900 arm64_za-ptrace_Set_VL_6560 pass
13925 16:31:44.596205 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
13926 16:31:44.596319 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
13927 16:31:44.596417 arm64_za-ptrace_Set_VL_6576 pass
13928 16:31:44.596607 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
13929 16:31:44.596743 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
13930 16:31:44.596855 arm64_za-ptrace_Set_VL_6592 pass
13931 16:31:44.597159 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
13932 16:31:44.597262 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
13933 16:31:44.597362 arm64_za-ptrace_Set_VL_6608 pass
13934 16:31:44.597471 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
13935 16:31:44.597565 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
13936 16:31:44.597689 arm64_za-ptrace_Set_VL_6624 pass
13937 16:31:44.597974 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
13938 16:31:44.606178 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
13939 16:31:44.606281 arm64_za-ptrace_Set_VL_6640 pass
13940 16:31:44.606559 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
13941 16:31:44.606859 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
13942 16:31:44.606974 arm64_za-ptrace_Set_VL_6656 pass
13943 16:31:44.607070 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
13944 16:31:44.607164 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
13945 16:31:44.607453 arm64_za-ptrace_Set_VL_6672 pass
13946 16:31:44.607556 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
13947 16:31:44.607652 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
13948 16:31:44.607746 arm64_za-ptrace_Set_VL_6688 pass
13949 16:31:44.608038 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
13950 16:31:44.608154 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
13951 16:31:44.608249 arm64_za-ptrace_Set_VL_6704 pass
13952 16:31:44.608343 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
13953 16:31:44.608438 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
13954 16:31:44.608728 arm64_za-ptrace_Set_VL_6720 pass
13955 16:31:44.608842 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
13956 16:31:44.608938 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
13957 16:31:44.609032 arm64_za-ptrace_Set_VL_6736 pass
13958 16:31:44.609321 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
13959 16:31:44.609423 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
13960 16:31:44.609505 arm64_za-ptrace_Set_VL_6752 pass
13961 16:31:44.609598 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
13962 16:31:44.609703 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
13963 16:31:44.609824 arm64_za-ptrace_Set_VL_6768 pass
13964 16:31:44.609914 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
13965 16:31:44.614031 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
13966 16:31:44.614330 arm64_za-ptrace_Set_VL_6784 pass
13967 16:31:44.614432 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
13968 16:31:44.614530 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
13969 16:31:44.614615 arm64_za-ptrace_Set_VL_6800 pass
13970 16:31:44.614711 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
13971 16:31:44.614809 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
13972 16:31:44.614906 arm64_za-ptrace_Set_VL_6816 pass
13973 16:31:44.615004 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
13974 16:31:44.615109 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
13975 16:31:44.615207 arm64_za-ptrace_Set_VL_6832 pass
13976 16:31:44.615487 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
13977 16:31:44.615607 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
13978 16:31:44.615693 arm64_za-ptrace_Set_VL_6848 pass
13979 16:31:44.615882 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
13980 16:31:44.616009 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
13981 16:31:44.616136 arm64_za-ptrace_Set_VL_6864 pass
13982 16:31:44.616262 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
13983 16:31:44.616387 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
13984 16:31:44.616513 arm64_za-ptrace_Set_VL_6880 pass
13985 16:31:44.616653 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
13986 16:31:44.616756 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
13987 16:31:44.616848 arm64_za-ptrace_Set_VL_6896 pass
13988 16:31:44.616949 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
13989 16:31:44.617057 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
13990 16:31:44.617248 arm64_za-ptrace_Set_VL_6912 pass
13991 16:31:44.617374 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
13992 16:31:44.617497 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
13993 16:31:44.617599 arm64_za-ptrace_Set_VL_6928 pass
13994 16:31:44.617703 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
13995 16:31:44.617999 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
13996 16:31:44.622159 arm64_za-ptrace_Set_VL_6944 pass
13997 16:31:44.622465 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
13998 16:31:44.622566 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
13999 16:31:44.622650 arm64_za-ptrace_Set_VL_6960 pass
14000 16:31:44.622744 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14001 16:31:44.623036 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14002 16:31:44.623139 arm64_za-ptrace_Set_VL_6976 pass
14003 16:31:44.623239 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14004 16:31:44.623323 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14005 16:31:44.623448 arm64_za-ptrace_Set_VL_6992 pass
14006 16:31:44.623556 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14007 16:31:44.623675 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14008 16:31:44.623770 arm64_za-ptrace_Set_VL_7008 pass
14009 16:31:44.623865 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14010 16:31:44.623965 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14011 16:31:44.624051 arm64_za-ptrace_Set_VL_7024 pass
14012 16:31:44.624148 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14013 16:31:44.624247 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14014 16:31:44.624343 arm64_za-ptrace_Set_VL_7040 pass
14015 16:31:44.624700 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14016 16:31:44.624827 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14017 16:31:44.624935 arm64_za-ptrace_Set_VL_7056 pass
14018 16:31:44.625069 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14019 16:31:44.625211 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14020 16:31:44.625319 arm64_za-ptrace_Set_VL_7072 pass
14021 16:31:44.625447 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14022 16:31:44.625872 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14023 16:31:44.625976 arm64_za-ptrace_Set_VL_7088 pass
14024 16:31:44.626060 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14025 16:31:44.630143 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14026 16:31:44.630446 arm64_za-ptrace_Set_VL_7104 pass
14027 16:31:44.630723 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14028 16:31:44.630827 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14029 16:31:44.630940 arm64_za-ptrace_Set_VL_7120 pass
14030 16:31:44.631069 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14031 16:31:44.631173 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14032 16:31:44.631299 arm64_za-ptrace_Set_VL_7136 pass
14033 16:31:44.631407 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14034 16:31:44.631509 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14035 16:31:44.631794 arm64_za-ptrace_Set_VL_7152 pass
14036 16:31:44.631910 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14037 16:31:44.632012 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14038 16:31:44.632110 arm64_za-ptrace_Set_VL_7168 pass
14039 16:31:44.632226 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14040 16:31:44.632501 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14041 16:31:44.632779 arm64_za-ptrace_Set_VL_7184 pass
14042 16:31:44.632880 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14043 16:31:44.632978 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14044 16:31:44.633076 arm64_za-ptrace_Set_VL_7200 pass
14045 16:31:44.633176 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14046 16:31:44.633468 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14047 16:31:44.633584 arm64_za-ptrace_Set_VL_7216 pass
14048 16:31:44.633692 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14049 16:31:44.633987 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14050 16:31:44.634107 arm64_za-ptrace_Set_VL_7232 pass
14051 16:31:44.638529 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14052 16:31:44.638632 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14053 16:31:44.638714 arm64_za-ptrace_Set_VL_7248 pass
14054 16:31:44.640332 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14055 16:31:44.640433 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14056 16:31:44.640514 arm64_za-ptrace_Set_VL_7264 pass
14057 16:31:44.640592 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14058 16:31:44.640671 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14059 16:31:44.640749 arm64_za-ptrace_Set_VL_7280 pass
14060 16:31:44.640826 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14061 16:31:44.640904 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14062 16:31:44.640982 arm64_za-ptrace_Set_VL_7296 pass
14063 16:31:44.641060 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14064 16:31:44.641146 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14065 16:31:44.641225 arm64_za-ptrace_Set_VL_7312 pass
14066 16:31:44.641303 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14067 16:31:44.641381 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14068 16:31:44.641459 arm64_za-ptrace_Set_VL_7328 pass
14069 16:31:44.641538 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14070 16:31:44.641815 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14071 16:31:44.641916 arm64_za-ptrace_Set_VL_7344 pass
14072 16:31:44.641998 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14073 16:31:44.642079 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14074 16:31:44.642157 arm64_za-ptrace_Set_VL_7360 pass
14075 16:31:44.642235 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14076 16:31:44.642312 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14077 16:31:44.642390 arm64_za-ptrace_Set_VL_7376 pass
14078 16:31:44.642467 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14079 16:31:44.642544 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14080 16:31:44.642636 arm64_za-ptrace_Set_VL_7392 pass
14081 16:31:44.646069 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14082 16:31:44.646335 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14083 16:31:44.646436 arm64_za-ptrace_Set_VL_7408 pass
14084 16:31:44.646530 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14085 16:31:44.646611 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14086 16:31:44.646702 arm64_za-ptrace_Set_VL_7424 pass
14087 16:31:44.646982 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14088 16:31:44.647085 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14089 16:31:44.647167 arm64_za-ptrace_Set_VL_7440 pass
14090 16:31:44.647259 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14091 16:31:44.647339 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14092 16:31:44.647429 arm64_za-ptrace_Set_VL_7456 pass
14093 16:31:44.647509 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14094 16:31:44.647600 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14095 16:31:44.647692 arm64_za-ptrace_Set_VL_7472 pass
14096 16:31:44.647978 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14097 16:31:44.648092 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14098 16:31:44.648183 arm64_za-ptrace_Set_VL_7488 pass
14099 16:31:44.648277 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14100 16:31:44.648370 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14101 16:31:44.648451 arm64_za-ptrace_Set_VL_7504 pass
14102 16:31:44.648551 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14103 16:31:44.648840 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14104 16:31:44.648942 arm64_za-ptrace_Set_VL_7520 pass
14105 16:31:44.649036 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14106 16:31:44.649120 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14107 16:31:44.649212 arm64_za-ptrace_Set_VL_7536 pass
14108 16:31:44.649292 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14109 16:31:44.649580 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14110 16:31:44.649687 arm64_za-ptrace_Set_VL_7552 pass
14111 16:31:44.649769 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14112 16:31:44.649861 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14113 16:31:44.649942 arm64_za-ptrace_Set_VL_7568 pass
14114 16:31:44.654031 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14115 16:31:44.654334 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14116 16:31:44.654435 arm64_za-ptrace_Set_VL_7584 pass
14117 16:31:44.654530 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14118 16:31:44.654612 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14119 16:31:44.654703 arm64_za-ptrace_Set_VL_7600 pass
14120 16:31:44.654796 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14121 16:31:44.655091 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14122 16:31:44.655196 arm64_za-ptrace_Set_VL_7616 pass
14123 16:31:44.655289 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14124 16:31:44.655576 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14125 16:31:44.655680 arm64_za-ptrace_Set_VL_7632 pass
14126 16:31:44.655776 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14127 16:31:44.655857 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14128 16:31:44.655950 arm64_za-ptrace_Set_VL_7648 pass
14129 16:31:44.656031 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14130 16:31:44.656123 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14131 16:31:44.656216 arm64_za-ptrace_Set_VL_7664 pass
14132 16:31:44.656310 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14133 16:31:44.656910 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14134 16:31:44.657015 arm64_za-ptrace_Set_VL_7680 pass
14135 16:31:44.657121 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14136 16:31:44.657221 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14137 16:31:44.657315 arm64_za-ptrace_Set_VL_7696 pass
14138 16:31:44.657412 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14139 16:31:44.657688 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14140 16:31:44.657771 arm64_za-ptrace_Set_VL_7712 pass
14141 16:31:44.657868 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14142 16:31:44.657940 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14143 16:31:44.662286 arm64_za-ptrace_Set_VL_7728 pass
14144 16:31:44.662404 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14145 16:31:44.662506 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14146 16:31:44.662810 arm64_za-ptrace_Set_VL_7744 pass
14147 16:31:44.662934 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14148 16:31:44.663041 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14149 16:31:44.663170 arm64_za-ptrace_Set_VL_7760 pass
14150 16:31:44.663290 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14151 16:31:44.663398 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14152 16:31:44.663709 arm64_za-ptrace_Set_VL_7776 pass
14153 16:31:44.663816 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14154 16:31:44.664091 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14155 16:31:44.664207 arm64_za-ptrace_Set_VL_7792 pass
14156 16:31:44.664336 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14157 16:31:44.664646 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14158 16:31:44.664750 arm64_za-ptrace_Set_VL_7808 pass
14159 16:31:44.664881 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14160 16:31:44.664986 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14161 16:31:44.665096 arm64_za-ptrace_Set_VL_7824 pass
14162 16:31:44.665228 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14163 16:31:44.665333 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14164 16:31:44.665442 arm64_za-ptrace_Set_VL_7840 pass
14165 16:31:44.665570 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14166 16:31:44.665680 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14167 16:31:44.665772 arm64_za-ptrace_Set_VL_7856 pass
14168 16:31:44.665875 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14169 16:31:44.665964 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14170 16:31:44.666065 arm64_za-ptrace_Set_VL_7872 pass
14171 16:31:44.670158 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14172 16:31:44.670459 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14173 16:31:44.670563 arm64_za-ptrace_Set_VL_7888 pass
14174 16:31:44.670654 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14175 16:31:44.670754 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14176 16:31:44.670841 arm64_za-ptrace_Set_VL_7904 pass
14177 16:31:44.670942 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14178 16:31:44.671030 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14179 16:31:44.671131 arm64_za-ptrace_Set_VL_7920 pass
14180 16:31:44.671218 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14181 16:31:44.671514 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14182 16:31:44.671618 arm64_za-ptrace_Set_VL_7936 pass
14183 16:31:44.671721 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14184 16:31:44.671809 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14185 16:31:44.671908 arm64_za-ptrace_Set_VL_7952 pass
14186 16:31:44.672009 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14187 16:31:44.672110 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14188 16:31:44.672212 arm64_za-ptrace_Set_VL_7968 pass
14189 16:31:44.672312 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14190 16:31:44.672419 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14191 16:31:44.672721 arm64_za-ptrace_Set_VL_7984 pass
14192 16:31:44.672840 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14193 16:31:44.672973 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14194 16:31:44.673088 arm64_za-ptrace_Set_VL_8000 pass
14195 16:31:44.673228 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14196 16:31:44.673536 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14197 16:31:44.673626 arm64_za-ptrace_Set_VL_8016 pass
14198 16:31:44.674083 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14199 16:31:44.674186 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14200 16:31:44.674267 arm64_za-ptrace_Set_VL_8032 pass
14201 16:31:44.674345 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14202 16:31:44.674424 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14203 16:31:44.678344 arm64_za-ptrace_Set_VL_8048 pass
14204 16:31:44.678465 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14205 16:31:44.678781 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14206 16:31:44.678901 arm64_za-ptrace_Set_VL_8064 pass
14207 16:31:44.679013 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14208 16:31:44.679145 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14209 16:31:44.679260 arm64_za-ptrace_Set_VL_8080 pass
14210 16:31:44.679391 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14211 16:31:44.679497 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14212 16:31:44.679607 arm64_za-ptrace_Set_VL_8096 pass
14213 16:31:44.679736 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14214 16:31:44.679842 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14215 16:31:44.679961 arm64_za-ptrace_Set_VL_8112 pass
14216 16:31:44.680093 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14217 16:31:44.680216 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14218 16:31:44.680541 arm64_za-ptrace_Set_VL_8128 pass
14219 16:31:44.680651 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14220 16:31:44.680754 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14221 16:31:44.680856 arm64_za-ptrace_Set_VL_8144 pass
14222 16:31:44.681144 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14223 16:31:44.681670 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14224 16:31:44.681780 arm64_za-ptrace_Set_VL_8160 pass
14225 16:31:44.681892 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14226 16:31:44.682002 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14227 16:31:44.682307 arm64_za-ptrace_Set_VL_8176 pass
14228 16:31:44.682412 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14229 16:31:44.686268 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14230 16:31:44.686384 arm64_za-ptrace_Set_VL_8192 pass
14231 16:31:44.686488 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14232 16:31:44.686619 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14233 16:31:44.686746 arm64_za-ptrace pass
14234 16:31:44.686871 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14235 16:31:44.687202 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14236 16:31:44.687328 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14237 16:31:44.687654 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14238 16:31:44.687979 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14239 16:31:44.688299 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14240 16:31:44.688632 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14241 16:31:44.688765 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14242 16:31:44.689082 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14243 16:31:44.689413 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14244 16:31:44.689697 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14245 16:31:44.689802 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14246 16:31:44.694051 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14247 16:31:44.694495 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14248 16:31:44.694628 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14249 16:31:44.695159 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14250 16:31:44.695475 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14251 16:31:44.695784 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14252 16:31:44.696095 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14253 16:31:44.696403 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14254 16:31:44.696703 arm64_check_buffer_fill fail
14255 16:31:44.696802 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14256 16:31:44.696899 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14257 16:31:44.697181 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14258 16:31:44.697689 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14259 16:31:44.697990 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14260 16:31:44.702110 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14261 16:31:44.702412 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14262 16:31:44.702932 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14263 16:31:44.703425 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14264 16:31:44.703724 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14265 16:31:44.704024 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14266 16:31:44.704324 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14267 16:31:44.704428 arm64_check_child_memory fail
14268 16:31:44.704516 arm64_check_gcr_el1_cswitch fail
14269 16:31:44.704600 arm64_check_ksm_options fail
14270 16:31:44.704698 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14271 16:31:44.705254 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14272 16:31:44.705552 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14273 16:31:44.710635 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14274 16:31:44.710962 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14275 16:31:44.711261 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14276 16:31:44.711573 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14277 16:31:44.711687 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14278 16:31:44.712176 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14279 16:31:44.712697 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14280 16:31:44.713261 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14281 16:31:44.713559 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14282 16:31:44.713679 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14283 16:31:44.718157 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14284 16:31:44.718667 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14285 16:31:44.718984 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14286 16:31:44.719310 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14287 16:31:44.719611 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14288 16:31:44.719924 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14289 16:31:44.720440 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14290 16:31:44.720564 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14291 16:31:44.721091 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14292 16:31:44.721197 arm64_check_mmap_options fail
14293 16:31:44.721327 arm64_check_prctl_check_basic_read pass
14294 16:31:44.721435 arm64_check_prctl_NONE pass
14295 16:31:44.721546 arm64_check_prctl_SYNC pass
14296 16:31:44.721682 arm64_check_prctl_ASYNC pass
14297 16:31:44.721788 arm64_check_prctl_SYNC_ASYNC pass
14298 16:31:44.721918 arm64_check_prctl pass
14299 16:31:44.722024 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14300 16:31:44.726180 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14301 16:31:44.726525 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14302 16:31:44.726907 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14303 16:31:44.727022 arm64_check_tags_inclusion fail
14304 16:31:44.727309 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14305 16:31:44.727425 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14306 16:31:44.728068 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14307 16:31:44.728171 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14308 16:31:44.728253 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14309 16:31:44.728529 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14310 16:31:44.728828 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14311 16:31:44.728929 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14312 16:31:44.729223 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14313 16:31:44.729526 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14314 16:31:44.729825 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14315 16:31:44.730124 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14316 16:31:44.734188 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14317 16:31:44.734684 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14318 16:31:44.734799 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14319 16:31:44.735278 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14320 16:31:44.735579 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14321 16:31:44.735692 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14322 16:31:44.736068 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14323 16:31:44.736560 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14324 16:31:44.736859 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14325 16:31:44.736972 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14326 16:31:44.737255 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14327 16:31:44.737556 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14328 16:31:44.737860 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14329 16:31:44.737962 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14330 16:31:44.742206 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14331 16:31:44.742516 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14332 16:31:44.742638 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14333 16:31:44.742936 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14334 16:31:44.743226 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14335 16:31:44.743545 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14336 16:31:44.743632 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14337 16:31:44.744050 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14338 16:31:44.744173 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14339 16:31:44.744902 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14340 16:31:44.745012 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14341 16:31:44.745274 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14342 16:31:44.745670 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14343 16:31:44.745955 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14344 16:31:44.750304 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14345 16:31:44.750614 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14346 16:31:44.750923 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14347 16:31:44.751228 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14348 16:31:44.751529 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14349 16:31:44.751632 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14350 16:31:44.751726 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14351 16:31:44.752205 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14352 16:31:44.752517 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14353 16:31:44.752635 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14354 16:31:44.752934 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14355 16:31:44.753059 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14356 16:31:44.753564 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14357 16:31:44.753679 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14358 16:31:44.763295 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14359 16:31:44.763419 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14360 16:31:44.763503 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14361 16:31:44.763584 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14362 16:31:44.763664 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14363 16:31:44.764206 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14364 16:31:44.764310 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14365 16:31:44.764394 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14366 16:31:44.764489 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14367 16:31:44.764809 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14368 16:31:44.764910 arm64_check_user_mem pass
14369 16:31:44.765009 arm64_btitest_nohint_func_call_using_br_x0 pass
14370 16:31:44.765091 arm64_btitest_nohint_func_call_using_br_x16 pass
14371 16:31:44.765185 arm64_btitest_nohint_func_call_using_blr pass
14372 16:31:44.765482 arm64_btitest_bti_none_func_call_using_br_x0 pass
14373 16:31:44.765582 arm64_btitest_bti_none_func_call_using_br_x16 pass
14374 16:31:44.765687 arm64_btitest_bti_none_func_call_using_blr pass
14375 16:31:44.768193 arm64_btitest_bti_c_func_call_using_br_x0 pass
14376 16:31:44.770049 arm64_btitest_bti_c_func_call_using_br_x16 pass
14377 16:31:44.770332 arm64_btitest_bti_c_func_call_using_blr pass
14378 16:31:44.770435 arm64_btitest_bti_j_func_call_using_br_x0 pass
14379 16:31:44.770730 arm64_btitest_bti_j_func_call_using_br_x16 pass
14380 16:31:44.770827 arm64_btitest_bti_j_func_call_using_blr pass
14381 16:31:44.770908 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14382 16:31:44.771001 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14383 16:31:44.771082 arm64_btitest_bti_jc_func_call_using_blr pass
14384 16:31:44.771174 arm64_btitest_paciasp_func_call_using_br_x0 pass
14385 16:31:44.771456 arm64_btitest_paciasp_func_call_using_br_x16 pass
14386 16:31:44.771546 arm64_btitest_paciasp_func_call_using_blr pass
14387 16:31:44.771627 arm64_btitest pass
14388 16:31:44.771695 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14389 16:31:44.771918 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14390 16:31:44.772017 arm64_nobtitest_nohint_func_call_using_blr pass
14391 16:31:44.772110 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14392 16:31:44.772202 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14393 16:31:44.772293 arm64_nobtitest_bti_none_func_call_using_blr pass
14394 16:31:44.772387 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14395 16:31:44.772676 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14396 16:31:44.772773 arm64_nobtitest_bti_c_func_call_using_blr pass
14397 16:31:44.772865 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14398 16:31:44.772956 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14399 16:31:44.773248 arm64_nobtitest_bti_j_func_call_using_blr pass
14400 16:31:44.773350 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14401 16:31:44.773442 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14402 16:31:44.773532 arm64_nobtitest_bti_jc_func_call_using_blr pass
14403 16:31:44.773623 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14404 16:31:44.773888 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14405 16:31:44.778129 arm64_nobtitest_paciasp_func_call_using_blr pass
14406 16:31:44.778237 arm64_nobtitest pass
14407 16:31:44.778474 arm64_hwcap_cpuinfo_match_RNG pass
14408 16:31:44.778577 arm64_hwcap_sigill_RNG pass
14409 16:31:44.778662 arm64_hwcap_cpuinfo_match_SME pass
14410 16:31:44.778760 arm64_hwcap_sigill_SME pass
14411 16:31:44.778844 arm64_hwcap_cpuinfo_match_SVE pass
14412 16:31:44.778926 arm64_hwcap_sigill_SVE pass
14413 16:31:44.779022 arm64_hwcap_cpuinfo_match_SVE_2 pass
14414 16:31:44.779106 arm64_hwcap_sigill_SVE_2 pass
14415 16:31:44.779201 arm64_hwcap_cpuinfo_match_SVE_AES pass
14416 16:31:44.779286 arm64_hwcap_sigill_SVE_AES pass
14417 16:31:44.779368 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14418 16:31:44.779449 arm64_hwcap_sigill_SVE2_PMULL pass
14419 16:31:44.779545 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14420 16:31:44.779622 arm64_hwcap_sigill_SVE2_BITPERM pass
14421 16:31:44.779909 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14422 16:31:44.780009 arm64_hwcap_sigill_SVE2_SHA3 pass
14423 16:31:44.780091 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14424 16:31:44.780171 arm64_hwcap_sigill_SVE2_SM4 pass
14425 16:31:44.780250 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14426 16:31:44.780344 arm64_hwcap_sigill_SVE2_I8MM pass
14427 16:31:44.780425 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14428 16:31:44.780505 arm64_hwcap_sigill_SVE2_F32MM pass
14429 16:31:44.780584 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14430 16:31:44.780678 arm64_hwcap_sigill_SVE2_F64MM pass
14431 16:31:44.780759 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14432 16:31:44.780839 arm64_hwcap_sigill_SVE2_BF16 pass
14433 16:31:44.780932 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14434 16:31:44.781013 arm64_hwcap_sigill_SVE2_EBF16 skip
14435 16:31:44.781095 arm64_hwcap pass
14436 16:31:44.781189 arm64_ptrace_read_tpidr_one pass
14437 16:31:44.781270 arm64_ptrace_write_tpidr_one pass
14438 16:31:44.781365 arm64_ptrace_verify_tpidr_one pass
14439 16:31:44.781446 arm64_ptrace_count_tpidrs pass
14440 16:31:44.781525 arm64_ptrace_tpidr2_write pass
14441 16:31:44.781617 arm64_ptrace_tpidr2_read pass
14442 16:31:44.781919 arm64_ptrace_write_tpidr_only pass
14443 16:31:44.782017 arm64_ptrace pass
14444 16:31:44.782099 arm64_syscall-abi_getpid_FPSIMD pass
14445 16:31:44.782178 arm64_syscall-abi_getpid_SVE_VL_256 pass
14446 16:31:44.786095 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14447 16:31:44.786406 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14448 16:31:44.786510 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14449 16:31:44.786608 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14450 16:31:44.786896 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14451 16:31:44.787013 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14452 16:31:44.787097 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14453 16:31:44.787190 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14454 16:31:44.787286 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14455 16:31:44.787585 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14456 16:31:44.787702 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14457 16:31:44.787797 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14458 16:31:44.787895 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14459 16:31:44.788186 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14460 16:31:44.788305 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14461 16:31:44.788390 arm64_syscall-abi_getpid_SVE_VL_240 pass
14462 16:31:44.788483 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14463 16:31:44.788760 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14464 16:31:44.788864 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14465 16:31:44.788959 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14466 16:31:44.789226 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14467 16:31:44.789330 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14468 16:31:44.789425 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14469 16:31:44.789519 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14470 16:31:44.789611 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14471 16:31:44.789911 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14472 16:31:44.794053 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14473 16:31:44.794347 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14474 16:31:44.794451 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14475 16:31:44.794546 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14476 16:31:44.794641 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14477 16:31:44.794936 arm64_syscall-abi_getpid_SVE_VL_224 pass
14478 16:31:44.795041 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14479 16:31:44.795138 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14480 16:31:44.795232 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14481 16:31:44.795522 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14482 16:31:44.795622 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14483 16:31:44.795718 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14484 16:31:44.796005 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14485 16:31:44.796108 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14486 16:31:44.796203 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14487 16:31:44.796298 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14488 16:31:44.796392 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14489 16:31:44.796698 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14490 16:31:44.796991 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14491 16:31:44.797093 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14492 16:31:44.797188 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14493 16:31:44.797268 arm64_syscall-abi_getpid_SVE_VL_208 pass
14494 16:31:44.797358 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14495 16:31:44.797652 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14496 16:31:44.797751 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14497 16:31:44.798132 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14498 16:31:44.798230 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14499 16:31:44.802223 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14500 16:31:44.802731 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14501 16:31:44.803042 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14502 16:31:44.803145 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14503 16:31:44.803229 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14504 16:31:44.803325 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14505 16:31:44.803409 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14506 16:31:44.803503 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14507 16:31:44.803599 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14508 16:31:44.803695 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14509 16:31:44.803994 arm64_syscall-abi_getpid_SVE_VL_192 pass
14510 16:31:44.804112 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14511 16:31:44.804422 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14512 16:31:44.804524 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14513 16:31:44.804621 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14514 16:31:44.804919 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14515 16:31:44.805018 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14516 16:31:44.805111 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14517 16:31:44.805404 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14518 16:31:44.805514 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14519 16:31:44.805595 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14520 16:31:44.805894 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14521 16:31:44.805994 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14522 16:31:44.810016 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14523 16:31:44.810319 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14524 16:31:44.810409 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14525 16:31:44.810492 arm64_syscall-abi_getpid_SVE_VL_176 pass
14526 16:31:44.810771 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14527 16:31:44.811077 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14528 16:31:44.811177 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14529 16:31:44.811259 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14530 16:31:44.811379 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14531 16:31:44.811710 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14532 16:31:44.811842 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14533 16:31:44.811967 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14534 16:31:44.812093 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14535 16:31:44.812218 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14536 16:31:44.818181 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14537 16:31:44.818511 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14538 16:31:44.818618 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14539 16:31:44.818736 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14540 16:31:44.818830 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14541 16:31:44.819166 arm64_syscall-abi_getpid_SVE_VL_160 pass
14542 16:31:44.819264 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14543 16:31:44.819564 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14544 16:31:44.819663 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14545 16:31:44.819759 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14546 16:31:44.819852 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14547 16:31:44.819945 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14548 16:31:44.820233 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14549 16:31:44.820531 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14550 16:31:44.823693 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14551 16:31:44.823809 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14552 16:31:44.823893 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14553 16:31:44.823974 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14554 16:31:44.824053 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14555 16:31:44.824132 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14556 16:31:44.824211 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14557 16:31:44.826145 arm64_syscall-abi_getpid_SVE_VL_144 pass
14558 16:31:44.826443 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14559 16:31:44.826558 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14560 16:31:44.826850 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14561 16:31:44.826964 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14562 16:31:44.827060 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14563 16:31:44.827339 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14564 16:31:44.827455 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14565 16:31:44.827744 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14566 16:31:44.827847 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14567 16:31:44.827949 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14568 16:31:44.828033 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14569 16:31:44.828129 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14570 16:31:44.828305 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14571 16:31:44.828626 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14572 16:31:44.828742 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14573 16:31:44.828842 arm64_syscall-abi_getpid_SVE_VL_128 pass
14574 16:31:44.829134 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14575 16:31:44.829272 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14576 16:31:44.829567 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14577 16:31:44.829690 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14578 16:31:44.829784 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14579 16:31:44.834727 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14580 16:31:44.834831 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14581 16:31:44.834917 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14582 16:31:44.835000 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14583 16:31:44.835283 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14584 16:31:44.835385 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14585 16:31:44.835471 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14586 16:31:44.835570 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14587 16:31:44.836040 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14588 16:31:44.836355 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14589 16:31:44.836474 arm64_syscall-abi_getpid_SVE_VL_112 pass
14590 16:31:44.836575 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14591 16:31:44.836869 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14592 16:31:44.836986 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14593 16:31:44.837281 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14594 16:31:44.837593 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14595 16:31:44.837700 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14596 16:31:44.837796 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14597 16:31:44.837891 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14598 16:31:44.842030 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14599 16:31:44.842526 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14600 16:31:44.842630 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14601 16:31:44.842726 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14602 16:31:44.843008 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14603 16:31:44.843127 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14604 16:31:44.843211 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14605 16:31:44.843303 arm64_syscall-abi_getpid_SVE_VL_96 pass
14606 16:31:44.843394 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14607 16:31:44.843684 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14608 16:31:44.843797 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14609 16:31:44.843890 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14610 16:31:44.843981 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14611 16:31:44.844259 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14612 16:31:44.844360 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14613 16:31:44.844528 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14614 16:31:44.844632 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14615 16:31:44.844727 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14616 16:31:44.845273 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14617 16:31:44.845375 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14618 16:31:44.845458 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14619 16:31:44.845535 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14620 16:31:44.845626 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14621 16:31:44.845717 arm64_syscall-abi_getpid_SVE_VL_80 pass
14622 16:31:44.845794 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14623 16:31:44.845884 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14624 16:31:44.845963 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14625 16:31:44.846052 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14626 16:31:44.846130 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14627 16:31:44.850245 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14628 16:31:44.850545 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14629 16:31:44.850646 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14630 16:31:44.850740 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14631 16:31:44.851019 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14632 16:31:44.851121 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14633 16:31:44.851215 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14634 16:31:44.851307 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14635 16:31:44.851595 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14636 16:31:44.851769 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14637 16:31:44.852079 arm64_syscall-abi_getpid_SVE_VL_64 pass
14638 16:31:44.852192 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14639 16:31:44.852484 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14640 16:31:44.852585 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14641 16:31:44.852678 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14642 16:31:44.853153 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14643 16:31:44.853254 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14644 16:31:44.853347 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14645 16:31:44.853625 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14646 16:31:44.853775 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14647 16:31:44.853870 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14648 16:31:44.858079 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14649 16:31:44.858377 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14650 16:31:44.858491 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14651 16:31:44.858585 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14652 16:31:44.858864 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14653 16:31:44.859162 arm64_syscall-abi_getpid_SVE_VL_48 pass
14654 16:31:44.859462 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14655 16:31:44.859583 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14656 16:31:44.859666 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14657 16:31:44.859756 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14658 16:31:44.860035 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14659 16:31:44.860137 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14660 16:31:44.860231 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14661 16:31:44.860511 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14662 16:31:44.860625 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14663 16:31:44.860718 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14664 16:31:44.861004 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14665 16:31:44.861105 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14666 16:31:44.861396 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14667 16:31:44.861500 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14668 16:31:44.861788 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14669 16:31:44.861889 arm64_syscall-abi_getpid_SVE_VL_32 pass
14670 16:31:44.861981 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14671 16:31:44.866099 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14672 16:31:44.867187 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14673 16:31:44.868446 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14674 16:31:44.868956 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14675 16:31:44.869445 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14676 16:31:44.869946 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14677 16:31:44.878034 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14678 16:31:44.878530 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14679 16:31:44.878844 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14680 16:31:44.879151 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14681 16:31:44.879450 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14682 16:31:44.879550 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14683 16:31:44.880036 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14684 16:31:44.880350 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14685 16:31:44.880671 arm64_syscall-abi_getpid_SVE_VL_16 pass
14686 16:31:44.881000 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14687 16:31:44.881325 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14688 16:31:44.881879 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14689 16:31:44.886031 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14690 16:31:44.886327 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14691 16:31:44.886636 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14692 16:31:44.886748 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14693 16:31:44.887031 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14694 16:31:44.887145 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14695 16:31:44.887629 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14696 16:31:44.887731 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14697 16:31:44.887826 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14698 16:31:44.888116 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14699 16:31:44.888418 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14700 16:31:44.888718 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14701 16:31:44.888818 arm64_syscall-abi_sched_yield_FPSIMD pass
14702 16:31:44.888913 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14703 16:31:44.889241 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14704 16:31:44.889343 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14705 16:31:44.889437 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14706 16:31:44.889531 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14707 16:31:44.889845 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14708 16:31:44.890154 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14709 16:31:44.890268 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14710 16:31:44.890554 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14711 16:31:44.890655 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14712 16:31:44.890757 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14713 16:31:44.891629 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14714 16:31:44.891731 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14715 16:31:44.891814 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14716 16:31:44.891893 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14717 16:31:44.891971 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14718 16:31:44.892049 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
14719 16:31:44.892324 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
14720 16:31:44.892425 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
14721 16:31:44.892507 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
14722 16:31:44.892603 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
14723 16:31:44.892715 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
14724 16:31:44.898033 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
14725 16:31:44.898532 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
14726 16:31:44.898663 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
14727 16:31:44.898786 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
14728 16:31:44.898920 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
14729 16:31:44.899233 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
14730 16:31:44.899348 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
14731 16:31:44.899638 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
14732 16:31:44.899752 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
14733 16:31:44.899836 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
14734 16:31:44.900122 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
14735 16:31:44.900239 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
14736 16:31:44.900347 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
14737 16:31:44.900655 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
14738 16:31:44.900778 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
14739 16:31:44.901084 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
14740 16:31:44.901208 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
14741 16:31:44.901334 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
14742 16:31:44.901460 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
14743 16:31:44.901783 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
14744 16:31:44.901888 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
14745 16:31:44.906089 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
14746 16:31:44.906391 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
14747 16:31:44.906514 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
14748 16:31:44.906644 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
14749 16:31:44.909903 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
14750 16:31:44.910010 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
14751 16:31:44.910125 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
14752 16:31:44.910235 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
14753 16:31:44.910345 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
14754 16:31:44.910454 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
14755 16:31:44.910564 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
14756 16:31:44.910675 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
14757 16:31:44.910784 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
14758 16:31:44.910893 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
14759 16:31:44.911001 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
14760 16:31:44.911110 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
14761 16:31:44.911219 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
14762 16:31:44.911327 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
14763 16:31:44.911436 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
14764 16:31:44.911545 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
14765 16:31:44.911654 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
14766 16:31:44.911763 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
14767 16:31:44.911872 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
14768 16:31:44.911981 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
14769 16:31:44.912090 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
14770 16:31:44.914054 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
14771 16:31:44.914360 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
14772 16:31:44.914788 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
14773 16:31:44.914892 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
14774 16:31:44.915201 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
14775 16:31:44.915304 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
14776 16:31:44.915413 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
14777 16:31:44.915548 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
14778 16:31:44.915677 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
14779 16:31:44.915782 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
14780 16:31:44.915910 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
14781 16:31:44.916038 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
14782 16:31:44.916159 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
14783 16:31:44.916485 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
14784 16:31:44.916608 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
14785 16:31:44.916717 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
14786 16:31:44.917022 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
14787 16:31:44.917140 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
14788 16:31:44.917427 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
14789 16:31:44.917542 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
14790 16:31:44.917640 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
14791 16:31:44.917941 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
14792 16:31:44.922307 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
14793 16:31:44.922611 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
14794 16:31:44.922714 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
14795 16:31:44.922815 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
14796 16:31:44.922921 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
14797 16:31:44.923204 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
14798 16:31:44.923307 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
14799 16:31:44.923399 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
14800 16:31:44.923488 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
14801 16:31:44.923588 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
14802 16:31:44.923885 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
14803 16:31:44.924000 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
14804 16:31:44.924293 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
14805 16:31:44.924410 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
14806 16:31:44.924499 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
14807 16:31:44.924601 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
14808 16:31:44.924905 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
14809 16:31:44.925009 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
14810 16:31:44.925307 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
14811 16:31:44.925423 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
14812 16:31:44.925524 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
14813 16:31:44.925629 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
14814 16:31:44.925922 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
14815 16:31:44.930083 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
14816 16:31:44.930386 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
14817 16:31:44.930699 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
14818 16:31:44.931019 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
14819 16:31:44.931135 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
14820 16:31:44.931630 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
14821 16:31:44.931942 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
14822 16:31:44.932249 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
14823 16:31:44.932534 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
14824 16:31:44.932850 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
14825 16:31:44.933161 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
14826 16:31:44.933471 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
14827 16:31:44.938062 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
14828 16:31:44.939178 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
14829 16:31:44.939476 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
14830 16:31:44.939592 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
14831 16:31:44.939888 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
14832 16:31:44.940005 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
14833 16:31:44.940106 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
14834 16:31:44.940400 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
14835 16:31:44.940503 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
14836 16:31:44.940599 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
14837 16:31:44.940889 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
14838 16:31:44.941004 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
14839 16:31:44.941303 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
14840 16:31:44.941418 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
14841 16:31:44.941687 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
14842 16:31:44.941778 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
14843 16:31:44.942046 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
14844 16:31:44.942359 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
14845 16:31:44.942460 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
14846 16:31:44.942559 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
14847 16:31:44.942657 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
14848 16:31:44.942755 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
14849 16:31:44.943051 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
14850 16:31:44.943167 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
14851 16:31:44.943462 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
14852 16:31:44.943565 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
14853 16:31:44.943860 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
14854 16:31:44.943962 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
14855 16:31:44.944061 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
14856 16:31:44.944345 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
14857 16:31:44.944462 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
14858 16:31:44.944562 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
14859 16:31:44.944667 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
14860 16:31:44.944975 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
14861 16:31:44.945091 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
14862 16:31:44.945385 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
14863 16:31:44.945501 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
14864 16:31:44.945588 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
14865 16:31:44.945893 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
14866 16:31:44.945997 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
14867 16:31:44.954113 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
14868 16:31:44.954433 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
14869 16:31:44.954752 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
14870 16:31:44.955058 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
14871 16:31:44.955539 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
14872 16:31:44.955655 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
14873 16:31:44.956145 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
14874 16:31:44.956236 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
14875 16:31:44.956704 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
14876 16:31:44.956822 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
14877 16:31:44.957120 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
14878 16:31:44.957246 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
14879 16:31:44.957540 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
14880 16:31:44.958020 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
14881 16:31:44.962096 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
14882 16:31:44.962397 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
14883 16:31:44.962705 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
14884 16:31:44.962993 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
14885 16:31:44.963304 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
14886 16:31:44.963806 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
14887 16:31:44.964115 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
14888 16:31:44.964428 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
14889 16:31:44.964830 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
14890 16:31:44.965138 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
14891 16:31:44.965447 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
14892 16:31:44.965560 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
14893 16:31:44.966053 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
14894 16:31:44.970349 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
14895 16:31:44.970661 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
14896 16:31:44.970779 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
14897 16:31:44.971078 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
14898 16:31:44.971383 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
14899 16:31:44.971487 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
14900 16:31:44.971587 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
14901 16:31:44.971882 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
14902 16:31:44.971999 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
14903 16:31:44.972300 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
14904 16:31:44.972417 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
14905 16:31:44.972716 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
14906 16:31:44.973028 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
14907 16:31:44.973331 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
14908 16:31:44.973496 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
14909 16:31:44.973798 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
14910 16:31:44.973899 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
14911 16:31:44.978113 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
14912 16:31:44.978412 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
14913 16:31:44.978720 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
14914 16:31:44.979224 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
14915 16:31:44.979726 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
14916 16:31:44.980034 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
14917 16:31:44.980545 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
14918 16:31:44.980858 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
14919 16:31:44.981161 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
14920 16:31:44.981690 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
14921 16:31:44.981998 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
14922 16:31:44.986968 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
14923 16:31:44.987297 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
14924 16:31:44.988005 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
14925 16:31:44.988708 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
14926 16:31:44.989209 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
14927 16:31:44.989491 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
14928 16:31:44.989780 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
14929 16:31:44.994056 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
14930 16:31:44.995126 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
14931 16:31:44.995601 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
14932 16:31:44.995717 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
14933 16:31:44.996237 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
14934 16:31:44.996743 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
14935 16:31:44.997248 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
14936 16:31:44.997591 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
14937 16:31:44.997911 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
14938 16:31:45.002096 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
14939 16:31:45.003176 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
14940 16:31:45.003877 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
14941 16:31:45.004586 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
14942 16:31:45.004703 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
14943 16:31:45.005195 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
14944 16:31:45.005287 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
14945 16:31:45.005949 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
14946 16:31:45.012334 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
14947 16:31:45.012637 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
14948 16:31:45.012949 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
14949 16:31:45.013066 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
14950 16:31:45.013548 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
14951 16:31:45.013672 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
14952 16:31:45.014923 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
14953 16:31:45.015232 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
14954 16:31:45.015732 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
14955 16:31:45.016038 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
14956 16:31:45.016141 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
14957 16:31:45.016436 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
14958 16:31:45.016552 arm64_syscall-abi pass
14959 16:31:45.016851 arm64_tpidr2_default_value pass
14960 16:31:45.016968 arm64_tpidr2_write_read pass
14961 16:31:45.017098 arm64_tpidr2_write_sleep_read pass
14962 16:31:45.017215 arm64_tpidr2_write_fork_read pass
14963 16:31:45.017509 arm64_tpidr2_write_clone_read pass
14964 16:31:45.017612 arm64_tpidr2 pass
14965 16:31:45.022973 + ../../utils/send-to-lava.sh ./output/result.txt
14966 16:31:45.087308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
14967 16:31:45.088230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
14969 16:31:45.133121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
14970 16:31:45.133449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
14972 16:31:45.180072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
14973 16:31:45.180365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
14975 16:31:45.225856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
14976 16:31:45.226147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
14978 16:31:45.272496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
14980 16:31:45.272796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
14981 16:31:45.321687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
14982 16:31:45.322021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
14984 16:31:45.368418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
14985 16:31:45.368708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
14987 16:31:45.415074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
14989 16:31:45.415493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
14990 16:31:45.460735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
14992 16:31:45.460968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
14993 16:31:45.506216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
14995 16:31:45.506518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
14996 16:31:45.552939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
14997 16:31:45.553230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
14999 16:31:45.599150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15000 16:31:45.599437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15002 16:31:45.644618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15003 16:31:45.644909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15005 16:31:45.690833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15006 16:31:45.691127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15008 16:31:45.736830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15009 16:31:45.737120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15011 16:31:45.782932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15012 16:31:45.783221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15014 16:31:45.828974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15016 16:31:45.829264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15017 16:31:45.875935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15018 16:31:45.876225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15020 16:31:45.922765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15022 16:31:45.923054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15023 16:31:45.969403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15024 16:31:45.969678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15026 16:31:46.016620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15028 16:31:46.016920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15029 16:31:46.062678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15031 16:31:46.062946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15032 16:31:46.108006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15033 16:31:46.108295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15035 16:31:46.154425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15037 16:31:46.154837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15038 16:31:46.200498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15039 16:31:46.200785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15041 16:31:46.247536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15043 16:31:46.247823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15044 16:31:46.293567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15045 16:31:46.293862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15047 16:31:46.350448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15049 16:31:46.350878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15050 16:31:46.399701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15051 16:31:46.400026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15053 16:31:46.446471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15055 16:31:46.446779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15056 16:31:46.493722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15057 16:31:46.494123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15059 16:31:46.539792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15060 16:31:46.540169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15062 16:31:46.585838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15064 16:31:46.586259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15065 16:31:46.633420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15066 16:31:46.633729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15068 16:31:46.680792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15069 16:31:46.681204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15071 16:31:46.727698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15073 16:31:46.727999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15074 16:31:46.773869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15075 16:31:46.774161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15077 16:31:46.819932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15078 16:31:46.820241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15080 16:31:46.870371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15082 16:31:46.870811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15083 16:31:46.919203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15084 16:31:46.919498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15086 16:31:46.966334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15088 16:31:46.966679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15089 16:31:47.014587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15091 16:31:47.015035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15092 16:31:47.062569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15094 16:31:47.063009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15095 16:31:47.109354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15096 16:31:47.109775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15098 16:31:47.156319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15099 16:31:47.156608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15101 16:31:47.202436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15103 16:31:47.202742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15104 16:31:47.249431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15106 16:31:47.249738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15107 16:31:47.295943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15108 16:31:47.296237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15110 16:31:47.341625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15112 16:31:47.341933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15113 16:31:47.389651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15115 16:31:47.389952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15116 16:31:47.437335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15117 16:31:47.437624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15119 16:31:47.485570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15120 16:31:47.485871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15122 16:31:47.531684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15123 16:31:47.531976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15125 16:31:47.577087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15126 16:31:47.577382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15128 16:31:47.623982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15130 16:31:47.624306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15131 16:31:47.670151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15133 16:31:47.670477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15134 16:31:47.716236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15136 16:31:47.716541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15137 16:31:47.763225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15139 16:31:47.763560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15140 16:31:47.810722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15142 16:31:47.811047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15143 16:31:47.857590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15144 16:31:47.857894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15146 16:31:47.904404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15148 16:31:47.904705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15149 16:31:47.951085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15151 16:31:47.951386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15152 16:31:47.996689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15153 16:31:47.996980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15155 16:31:48.044300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15156 16:31:48.044593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15158 16:31:48.091736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15160 16:31:48.092031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15161 16:31:48.138203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15163 16:31:48.138496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15164 16:31:48.185870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15165 16:31:48.186159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15167 16:31:48.232472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15168 16:31:48.232759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15170 16:31:48.279662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15171 16:31:48.279954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15173 16:31:48.326183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15175 16:31:48.326483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15176 16:31:48.374432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15178 16:31:48.374768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15179 16:31:48.423539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15181 16:31:48.423842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15182 16:31:48.469581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15183 16:31:48.469877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15185 16:31:48.516668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15186 16:31:48.516960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15188 16:31:48.567520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15190 16:31:48.567844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15191 16:31:48.620778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15192 16:31:48.621069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15194 16:31:48.669751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15195 16:31:48.670042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15197 16:31:48.722146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15199 16:31:48.722668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15200 16:31:48.775583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15202 16:31:48.775989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15203 16:31:48.828992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15205 16:31:48.829282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15206 16:31:48.880953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15208 16:31:48.881242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15209 16:31:48.936295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15211 16:31:48.936706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15212 16:31:48.987827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15213 16:31:48.988117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15215 16:31:49.035204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15217 16:31:49.035497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15218 16:31:49.081629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15219 16:31:49.081926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15221 16:31:49.128510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15222 16:31:49.128768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15224 16:31:49.176180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15226 16:31:49.176607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15227 16:31:49.222629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15229 16:31:49.222935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15230 16:31:49.269884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15231 16:31:49.270188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15233 16:31:49.317806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15234 16:31:49.318108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15236 16:31:49.366192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15238 16:31:49.366501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15239 16:31:49.412821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15241 16:31:49.413122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15242 16:31:49.459392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15244 16:31:49.459699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15245 16:31:49.505769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15246 16:31:49.506062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15248 16:31:49.552370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15249 16:31:49.552663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15251 16:31:49.601255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15253 16:31:49.601568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15254 16:31:49.651032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15256 16:31:49.651424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15257 16:31:49.697229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15259 16:31:49.697533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15260 16:31:49.746243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15262 16:31:49.746570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15263 16:31:49.792556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15264 16:31:49.792852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15266 16:31:49.843597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15267 16:31:49.843937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15269 16:31:49.899089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15271 16:31:49.899435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15272 16:31:49.949821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15273 16:31:49.950111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15275 16:31:50.000724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15276 16:31:50.001010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15278 16:31:50.053055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15279 16:31:50.053452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15281 16:31:50.104151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15282 16:31:50.104440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15284 16:31:50.155728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15285 16:31:50.156017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15287 16:31:50.203797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15288 16:31:50.204085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15290 16:31:50.251729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15291 16:31:50.252034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15293 16:31:50.297852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15295 16:31:50.298137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15296 16:31:50.344332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15297 16:31:50.344620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15299 16:31:50.390594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15300 16:31:50.390880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15302 16:31:50.437365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15304 16:31:50.437657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15305 16:31:50.483586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15306 16:31:50.483882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15308 16:31:50.530342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15310 16:31:50.530772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15311 16:31:50.576138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15312 16:31:50.576525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15314 16:31:50.623313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15315 16:31:50.623740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15317 16:31:50.670764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15318 16:31:50.671174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15320 16:31:50.716998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15321 16:31:50.717417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15323 16:31:50.765317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15324 16:31:50.765696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15326 16:31:50.812175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15328 16:31:50.812614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15329 16:31:50.858314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15331 16:31:50.858737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15332 16:31:50.906712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15334 16:31:50.907187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15335 16:31:50.953119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15337 16:31:50.953582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15338 16:31:50.999993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15339 16:31:51.000405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15341 16:31:51.047110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15342 16:31:51.047522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15344 16:31:51.092879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15346 16:31:51.093301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15347 16:31:51.139406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15349 16:31:51.139849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15350 16:31:51.185778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15351 16:31:51.186200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15353 16:31:51.232432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15354 16:31:51.232855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15356 16:31:51.281620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15357 16:31:51.282031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15359 16:31:51.328532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15361 16:31:51.328993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15362 16:31:51.375659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15363 16:31:51.376077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15365 16:31:51.424664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15366 16:31:51.425080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15368 16:31:51.471789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15369 16:31:51.472203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15371 16:31:51.519307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15372 16:31:51.519715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15374 16:31:51.565021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15375 16:31:51.565433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15377 16:31:51.611932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15379 16:31:51.612370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15380 16:31:51.659156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15381 16:31:51.659563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15383 16:31:51.703552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15384 16:31:51.703948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15386 16:31:51.749807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15387 16:31:51.750217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15389 16:31:51.797011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15390 16:31:51.797411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15392 16:31:51.844563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15393 16:31:51.844978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15395 16:31:51.891438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15397 16:31:51.891861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15398 16:31:51.943607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15399 16:31:51.944020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15401 16:31:51.991027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15403 16:31:51.991460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15404 16:31:52.039230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15406 16:31:52.039666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15407 16:31:52.085902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15409 16:31:52.086335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15410 16:31:52.133358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15411 16:31:52.133766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15413 16:31:52.180987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15414 16:31:52.181399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15416 16:31:52.228253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15417 16:31:52.228658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15419 16:31:52.275739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15421 16:31:52.276149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15422 16:31:52.322354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15424 16:31:52.322799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15425 16:31:52.369281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15426 16:31:52.369685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15428 16:31:52.416974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15429 16:31:52.417380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15431 16:31:52.464260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15432 16:31:52.464631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15434 16:31:52.510866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15435 16:31:52.511136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15437 16:31:52.556772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15438 16:31:52.557063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15440 16:31:52.603878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15441 16:31:52.604142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15443 16:31:52.649566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15445 16:31:52.649900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15446 16:31:52.696918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15447 16:31:52.697200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15449 16:31:52.743515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15450 16:31:52.743808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15452 16:31:52.790706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15453 16:31:52.790989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15455 16:31:52.836713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15456 16:31:52.837007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15458 16:31:52.883817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15460 16:31:52.884122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15461 16:31:52.929501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15462 16:31:52.929789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15464 16:31:52.975755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15466 16:31:52.976185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15467 16:31:53.032219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15468 16:31:53.032641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15470 16:31:53.080833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15472 16:31:53.081268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15473 16:31:53.127473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15474 16:31:53.127875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15476 16:31:53.175340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15477 16:31:53.175746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15479 16:31:53.220912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15480 16:31:53.221246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15482 16:31:53.270790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15483 16:31:53.271201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15485 16:31:53.315331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15487 16:31:53.315726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15488 16:31:53.361192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15489 16:31:53.361489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15491 16:31:53.407820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15492 16:31:53.408116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15494 16:31:53.453462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15496 16:31:53.453899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15497 16:31:53.499715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15498 16:31:53.500125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15500 16:31:53.547195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15501 16:31:53.547610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15503 16:31:53.592680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15504 16:31:53.593014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15506 16:31:53.639345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15508 16:31:53.639610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15509 16:31:53.684983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15510 16:31:53.685279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15512 16:31:53.731445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15513 16:31:53.731741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15515 16:31:53.776377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15516 16:31:53.776667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15518 16:31:53.822834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15519 16:31:53.823127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15521 16:31:53.868019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15522 16:31:53.868278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15524 16:31:53.916452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15525 16:31:53.916736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15527 16:31:53.962703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15528 16:31:53.962993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15530 16:31:54.007867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15531 16:31:54.008156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15533 16:31:54.053613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15535 16:31:54.053914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15536 16:31:54.099439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15537 16:31:54.099731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15539 16:31:54.144793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15541 16:31:54.145083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15542 16:31:54.190968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15543 16:31:54.191257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15545 16:31:54.236480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15546 16:31:54.236773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15548 16:31:54.283896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15549 16:31:54.284187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15551 16:31:54.329048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15552 16:31:54.329350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15554 16:31:54.375534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15555 16:31:54.375825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15557 16:31:54.421681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15558 16:31:54.421974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15560 16:31:54.467796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15561 16:31:54.468094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15563 16:31:54.513908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15564 16:31:54.514318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15566 16:31:54.561268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15568 16:31:54.561691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15569 16:31:54.607623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15570 16:31:54.608048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15572 16:31:54.654870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15573 16:31:54.655257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15575 16:31:54.700768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15576 16:31:54.701168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15578 16:31:54.747463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15579 16:31:54.747859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15581 16:31:54.793515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15583 16:31:54.793947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15584 16:31:54.842368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15586 16:31:54.842864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15587 16:31:54.892929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15589 16:31:54.893412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15590 16:31:54.943551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15591 16:31:54.943917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15593 16:31:54.990407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15595 16:31:54.990864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15596 16:31:55.038262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15598 16:31:55.038688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15599 16:31:55.084011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15601 16:31:55.084431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15602 16:31:55.129902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15603 16:31:55.130307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15605 16:31:55.176476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15606 16:31:55.176887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15608 16:31:55.223989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15609 16:31:55.224405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15611 16:31:55.271274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15612 16:31:55.271685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15614 16:31:55.319179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15615 16:31:55.319581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15617 16:31:55.366329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15619 16:31:55.366717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15620 16:31:55.413735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15621 16:31:55.414024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15623 16:31:55.461194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15625 16:31:55.461615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15626 16:31:55.507841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15628 16:31:55.508263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15629 16:31:55.553508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15630 16:31:55.553922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15632 16:31:55.599931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15634 16:31:55.600340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15635 16:31:55.645591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15636 16:31:55.645999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15638 16:31:55.691791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15639 16:31:55.692144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15641 16:31:55.739462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15642 16:31:55.739854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15644 16:31:55.786985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15645 16:31:55.787395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15647 16:31:55.841010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15648 16:31:55.841345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15650 16:31:55.889441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15651 16:31:55.889908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15653 16:31:55.936628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15654 16:31:55.937033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15656 16:31:55.984593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15658 16:31:55.984899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15659 16:31:56.031391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15660 16:31:56.031683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15662 16:31:56.077429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15663 16:31:56.077730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15665 16:31:56.124545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15666 16:31:56.124833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15668 16:31:56.173682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15669 16:31:56.174004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15671 16:31:56.220515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15672 16:31:56.220929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15674 16:31:56.267693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15675 16:31:56.268114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15677 16:31:56.314549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15679 16:31:56.314907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15680 16:31:56.361283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15681 16:31:56.361574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15683 16:31:56.408957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15684 16:31:56.409318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15686 16:31:56.456740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15688 16:31:56.457054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15689 16:31:56.503916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15690 16:31:56.504184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15692 16:31:56.553294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15693 16:31:56.553583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15695 16:31:56.600145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15696 16:31:56.600444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15698 16:31:56.646874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15700 16:31:56.647201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15701 16:31:56.692921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15702 16:31:56.693212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15704 16:31:56.739477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15705 16:31:56.739769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15707 16:31:56.785054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15708 16:31:56.785349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15710 16:31:56.832020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15712 16:31:56.832347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15713 16:31:56.878628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15715 16:31:56.878957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15716 16:31:56.926412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
15718 16:31:56.926738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15719 16:31:56.972547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
15721 16:31:56.972876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
15722 16:31:57.018919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
15723 16:31:57.019214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
15725 16:31:57.064886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
15726 16:31:57.065178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
15728 16:31:57.111390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
15729 16:31:57.111682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
15731 16:31:57.156904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
15732 16:31:57.157163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
15734 16:31:57.203745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
15736 16:31:57.204045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
15737 16:31:57.249311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
15738 16:31:57.249632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
15740 16:31:57.296385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
15741 16:31:57.296674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
15743 16:31:57.342481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
15745 16:31:57.342775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
15746 16:31:57.388946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
15748 16:31:57.389252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
15749 16:31:57.434436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
15751 16:31:57.434786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
15752 16:31:57.480893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
15754 16:31:57.481197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
15755 16:31:57.527098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
15756 16:31:57.527394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
15758 16:31:57.572849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
15759 16:31:57.573144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
15761 16:31:57.619165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
15762 16:31:57.619465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
15764 16:31:57.665751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
15765 16:31:57.666051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
15767 16:31:57.712710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
15768 16:31:57.713005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
15770 16:31:57.759532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
15771 16:31:57.759828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
15773 16:31:57.805133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
15775 16:31:57.805361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
15776 16:31:57.850999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
15777 16:31:57.851290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
15779 16:31:57.896729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
15780 16:31:57.897026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
15782 16:31:57.943553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
15783 16:31:57.943972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
15785 16:31:57.990346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
15787 16:31:57.990689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
15788 16:31:58.040390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
15789 16:31:58.040710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
15791 16:31:58.085937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
15793 16:31:58.086236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
15794 16:31:58.131674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
15795 16:31:58.131970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
15797 16:31:58.177127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
15799 16:31:58.177429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
15800 16:31:58.223843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
15802 16:31:58.224136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
15803 16:31:58.271959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
15804 16:31:58.272391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
15806 16:31:58.318778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
15807 16:31:58.319071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
15809 16:31:58.363277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
15810 16:31:58.363565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
15812 16:31:58.410582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
15813 16:31:58.410892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
15815 16:31:58.455836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
15816 16:31:58.456131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
15818 16:31:58.501602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
15820 16:31:58.501912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
15821 16:31:58.547827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
15822 16:31:58.548120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
15824 16:31:58.593508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
15825 16:31:58.593804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
15827 16:31:58.639586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
15828 16:31:58.639879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
15830 16:31:58.685195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
15831 16:31:58.685488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
15833 16:31:58.731459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
15835 16:31:58.731799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
15836 16:31:58.778225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
15838 16:31:58.778524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
15839 16:31:58.823915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
15840 16:31:58.824204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
15842 16:31:58.869944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
15843 16:31:58.870224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
15845 16:31:58.916304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
15847 16:31:58.916633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
15848 16:31:58.961775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
15849 16:31:58.962045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
15851 16:31:59.008242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
15852 16:31:59.008512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
15854 16:31:59.055168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
15855 16:31:59.055428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
15857 16:31:59.100787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
15858 16:31:59.101049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
15860 16:31:59.147831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
15861 16:31:59.148112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
15863 16:31:59.192797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
15864 16:31:59.193101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
15866 16:31:59.239339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
15867 16:31:59.239641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
15869 16:31:59.284954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
15871 16:31:59.285284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
15872 16:31:59.331580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
15874 16:31:59.331973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
15875 16:31:59.382429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
15877 16:31:59.382900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
15878 16:31:59.431200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
15879 16:31:59.431513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
15881 16:31:59.477548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
15883 16:31:59.477864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
15884 16:31:59.524827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
15885 16:31:59.525132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
15887 16:31:59.573819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
15888 16:31:59.574233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
15890 16:31:59.620936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
15891 16:31:59.621273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
15893 16:31:59.667850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
15894 16:31:59.668157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
15896 16:31:59.714353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
15898 16:31:59.714647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
15899 16:31:59.761018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
15900 16:31:59.761306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
15902 16:31:59.807920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
15904 16:31:59.808363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
15905 16:31:59.858964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
15906 16:31:59.859377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
15908 16:31:59.908691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
15909 16:31:59.909103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
15911 16:31:59.958524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
15913 16:31:59.958959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
15914 16:32:00.004383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
15916 16:32:00.004820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
15917 16:32:00.055261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
15919 16:32:00.055742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
15920 16:32:00.107959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
15921 16:32:00.108365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
15923 16:32:00.157592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
15924 16:32:00.158025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
15926 16:32:00.212055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
15927 16:32:00.212476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
15929 16:32:00.265881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
15930 16:32:00.266302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
15932 16:32:00.324511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
15934 16:32:00.324949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
15935 16:32:00.377520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
15937 16:32:00.377965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
15938 16:32:00.419212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
15939 16:32:00.419634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
15941 16:32:00.464431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
15943 16:32:00.464897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
15944 16:32:00.511009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
15946 16:32:00.511444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
15947 16:32:00.555573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
15948 16:32:00.555998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
15950 16:32:00.605932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
15952 16:32:00.606400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
15953 16:32:00.653098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
15955 16:32:00.653541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
15956 16:32:00.703358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
15957 16:32:00.703792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
15959 16:32:00.750056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
15960 16:32:00.750485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
15962 16:32:00.800061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
15963 16:32:00.800494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
15965 16:32:00.849790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
15966 16:32:00.850210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
15968 16:32:00.900484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
15969 16:32:00.900895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
15971 16:32:00.947890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
15972 16:32:00.948306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
15974 16:32:00.997797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
15975 16:32:00.998248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
15977 16:32:01.049814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
15978 16:32:01.050239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
15980 16:32:01.099260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
15982 16:32:01.099739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
15983 16:32:01.151818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
15984 16:32:01.152249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
15986 16:32:01.200632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
15988 16:32:01.201084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
15989 16:32:01.251728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
15990 16:32:01.252155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
15992 16:32:01.302217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
15994 16:32:01.302683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
15995 16:32:01.351728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
15996 16:32:01.352153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
15998 16:32:01.400472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
15999 16:32:01.400956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16001 16:32:01.448315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16002 16:32:01.448742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16004 16:32:01.488272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16005 16:32:01.488691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16007 16:32:01.538275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16009 16:32:01.538827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16010 16:32:01.588084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16011 16:32:01.588497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16013 16:32:01.637826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16015 16:32:01.638267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16016 16:32:01.687736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16018 16:32:01.688172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16019 16:32:01.736826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16020 16:32:01.737238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16022 16:32:01.787382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16024 16:32:01.787825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16025 16:32:01.837057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16026 16:32:01.837481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16028 16:32:01.885798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16029 16:32:01.886213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16031 16:32:01.935296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16033 16:32:01.935737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16034 16:32:01.984286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16035 16:32:01.984714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16037 16:32:02.034668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16039 16:32:02.035237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16040 16:32:02.084503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16042 16:32:02.084940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16043 16:32:02.135964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16044 16:32:02.136378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16046 16:32:02.185749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16047 16:32:02.186161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16049 16:32:02.235941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16050 16:32:02.236368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16052 16:32:02.284580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16054 16:32:02.285027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16055 16:32:02.335144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16056 16:32:02.335557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16058 16:32:02.384102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16059 16:32:02.384364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16061 16:32:02.432091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16062 16:32:02.432389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16064 16:32:02.480570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16065 16:32:02.480867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16067 16:32:02.529492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16068 16:32:02.529790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16070 16:32:02.578741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16071 16:32:02.579034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16073 16:32:02.627688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16074 16:32:02.627951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16076 16:32:02.676528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16078 16:32:02.676835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16079 16:32:02.725453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16080 16:32:02.725750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16082 16:32:02.775223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16083 16:32:02.775506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16085 16:32:02.823072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16086 16:32:02.823399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16088 16:32:02.871741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16089 16:32:02.872139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16091 16:32:02.920435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16093 16:32:02.920843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16094 16:32:02.967602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16095 16:32:02.968011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16097 16:32:03.014397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16099 16:32:03.014814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16100 16:32:03.061344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16101 16:32:03.061742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16103 16:32:03.109100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16104 16:32:03.109510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16106 16:32:03.159921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16107 16:32:03.160337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16109 16:32:03.205185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16111 16:32:03.205616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16112 16:32:03.254102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16114 16:32:03.254565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16115 16:32:03.301880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16116 16:32:03.302293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16118 16:32:03.348972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16119 16:32:03.349375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16121 16:32:03.397907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16123 16:32:03.398336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16124 16:32:03.445592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16125 16:32:03.446010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16127 16:32:03.492502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16128 16:32:03.492887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16130 16:32:03.542037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16132 16:32:03.542507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16133 16:32:03.588675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16134 16:32:03.589082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16136 16:32:03.636318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16138 16:32:03.636769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16139 16:32:03.684568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16141 16:32:03.685032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16142 16:32:03.731447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16143 16:32:03.731832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16145 16:32:03.778388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16147 16:32:03.778842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16148 16:32:03.825155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16149 16:32:03.825548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16151 16:32:03.872574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16153 16:32:03.872965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16154 16:32:03.922519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16156 16:32:03.923363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16157 16:32:03.971150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16158 16:32:03.971563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16160 16:32:04.017138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16161 16:32:04.017539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16163 16:32:04.063588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16164 16:32:04.063987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16166 16:32:04.111770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16167 16:32:04.112181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16169 16:32:04.164636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16170 16:32:04.165041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16172 16:32:04.211768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16173 16:32:04.212168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16175 16:32:04.259203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16177 16:32:04.259625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16178 16:32:04.305408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16179 16:32:04.305821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16181 16:32:04.352136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16183 16:32:04.352535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16184 16:32:04.399754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16186 16:32:04.400208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16187 16:32:04.446095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16189 16:32:04.446559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16190 16:32:04.493020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16191 16:32:04.493426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16193 16:32:04.541396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16194 16:32:04.541821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16196 16:32:04.588354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16197 16:32:04.588761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16199 16:32:04.637011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16201 16:32:04.637431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16202 16:32:04.683668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16203 16:32:04.684079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16205 16:32:04.729672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16206 16:32:04.730104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16208 16:32:04.776809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16209 16:32:04.777180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16211 16:32:04.823421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16212 16:32:04.823838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16214 16:32:04.870932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16216 16:32:04.871317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16217 16:32:04.919154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16218 16:32:04.919554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16220 16:32:04.965758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16221 16:32:04.966147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16223 16:32:05.014157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16225 16:32:05.014593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16226 16:32:05.060201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16227 16:32:05.060618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16229 16:32:05.108222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16230 16:32:05.108601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16232 16:32:05.154385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16234 16:32:05.154749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16235 16:32:05.200857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16236 16:32:05.201267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16238 16:32:05.247591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16239 16:32:05.247984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16241 16:32:05.293994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16243 16:32:05.294420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16244 16:32:05.340926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16245 16:32:05.341330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16247 16:32:05.388748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16248 16:32:05.389158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16250 16:32:05.437056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16252 16:32:05.437470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16253 16:32:05.486163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16254 16:32:05.486565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16256 16:32:05.534507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16258 16:32:05.534955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16259 16:32:05.581126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16261 16:32:05.581519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16262 16:32:05.628241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16263 16:32:05.628642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16265 16:32:05.676006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16267 16:32:05.676437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16268 16:32:05.722324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16270 16:32:05.722744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16271 16:32:05.770071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16273 16:32:05.770493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16274 16:32:05.817680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16275 16:32:05.818076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16277 16:32:05.865671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16278 16:32:05.866074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16280 16:32:05.913280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16281 16:32:05.913661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16283 16:32:05.960703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16284 16:32:05.961103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16286 16:32:06.008782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16287 16:32:06.009180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16289 16:32:06.056706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16290 16:32:06.057118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16292 16:32:06.104593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16293 16:32:06.105007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16295 16:32:06.151734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16297 16:32:06.152156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16298 16:32:06.199407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16300 16:32:06.199828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16301 16:32:06.245867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16303 16:32:06.246294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16304 16:32:06.293062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16305 16:32:06.293468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16307 16:32:06.340890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16309 16:32:06.341365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16310 16:32:06.388275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16312 16:32:06.388662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16313 16:32:06.435682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16314 16:32:06.436062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16316 16:32:06.484353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16318 16:32:06.484815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16319 16:32:06.536063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16320 16:32:06.536462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16322 16:32:06.584191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16324 16:32:06.584660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16325 16:32:06.635637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16327 16:32:06.636209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16328 16:32:06.686276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16330 16:32:06.686816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16331 16:32:06.737960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16332 16:32:06.738350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16334 16:32:06.789365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16336 16:32:06.789804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16337 16:32:06.841444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16339 16:32:06.841897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16340 16:32:06.898475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16342 16:32:06.899187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16343 16:32:06.953508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16345 16:32:06.953975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16346 16:32:07.001891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16347 16:32:07.002313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16349 16:32:07.055064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16350 16:32:07.055481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16352 16:32:07.101947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16353 16:32:07.102361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16355 16:32:07.150644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16356 16:32:07.151079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16358 16:32:07.197006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16359 16:32:07.197410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16361 16:32:07.244848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16363 16:32:07.245263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16364 16:32:07.291743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16365 16:32:07.292157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16367 16:32:07.339121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16369 16:32:07.339521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16370 16:32:07.386606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16372 16:32:07.387243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16373 16:32:07.434122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16375 16:32:07.434552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16376 16:32:07.481834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16378 16:32:07.482273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16379 16:32:07.529251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16381 16:32:07.529687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16382 16:32:07.576487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16384 16:32:07.576935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16385 16:32:07.624163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16386 16:32:07.624566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16388 16:32:07.672632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16390 16:32:07.673054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16391 16:32:07.721049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16392 16:32:07.721450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16394 16:32:07.768276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16395 16:32:07.768683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16397 16:32:07.815674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16398 16:32:07.816080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16400 16:32:07.863714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16401 16:32:07.864116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16403 16:32:07.911178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16405 16:32:07.911600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16406 16:32:07.959321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16407 16:32:07.959727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16409 16:32:08.008385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16410 16:32:08.008794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16412 16:32:08.056696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16414 16:32:08.057117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16415 16:32:08.104477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16417 16:32:08.104895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16418 16:32:08.151905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16420 16:32:08.152325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16421 16:32:08.201862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16423 16:32:08.202298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16424 16:32:08.251840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16426 16:32:08.252280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16427 16:32:08.299585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16428 16:32:08.299995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16430 16:32:08.344381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16431 16:32:08.344786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16433 16:32:08.394638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16435 16:32:08.395072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16436 16:32:08.441023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16437 16:32:08.441427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16439 16:32:08.489429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16440 16:32:08.489866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16442 16:32:08.536940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16444 16:32:08.537387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16445 16:32:08.584323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16447 16:32:08.584764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16448 16:32:08.637699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16450 16:32:08.638157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16451 16:32:08.688682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16452 16:32:08.689094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16454 16:32:08.736671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16455 16:32:08.737077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16457 16:32:08.786581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16459 16:32:08.787501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16460 16:32:08.842282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16462 16:32:08.843316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16463 16:32:08.894441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16465 16:32:08.895081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16466 16:32:08.947692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16468 16:32:08.948388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16469 16:32:09.002152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16471 16:32:09.002749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16472 16:32:09.053387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16473 16:32:09.053812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16475 16:32:09.101622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16476 16:32:09.102040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16478 16:32:09.150182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16480 16:32:09.150912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16481 16:32:09.198742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16483 16:32:09.199450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16484 16:32:09.248141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16486 16:32:09.248583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16487 16:32:09.297483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16489 16:32:09.297928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16490 16:32:09.345943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16491 16:32:09.346349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16493 16:32:09.394408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16495 16:32:09.394873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16496 16:32:09.442147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16498 16:32:09.442584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16499 16:32:09.489571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16500 16:32:09.489987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16502 16:32:09.537963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16503 16:32:09.538354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16505 16:32:09.584310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16507 16:32:09.584743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16508 16:32:09.632452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16509 16:32:09.632868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16511 16:32:09.679565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16512 16:32:09.679976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16514 16:32:09.727676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16516 16:32:09.728113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16517 16:32:09.775919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16519 16:32:09.776363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16520 16:32:09.825010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16521 16:32:09.825416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16523 16:32:09.876564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16525 16:32:09.876991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16526 16:32:09.927863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16527 16:32:09.928286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16529 16:32:09.978339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16531 16:32:09.978925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16532 16:32:10.029888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16534 16:32:10.030358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16535 16:32:10.082613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16537 16:32:10.083541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16538 16:32:10.132415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16540 16:32:10.132831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16541 16:32:10.181552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16543 16:32:10.182000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16544 16:32:10.231368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16545 16:32:10.231794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16547 16:32:10.279085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16549 16:32:10.279544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16550 16:32:10.328639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16552 16:32:10.329083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16553 16:32:10.376950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16555 16:32:10.377385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16556 16:32:10.424269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16557 16:32:10.424686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16559 16:32:10.474542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16561 16:32:10.474992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16562 16:32:10.524263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16564 16:32:10.524714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16565 16:32:10.574275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16567 16:32:10.574961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16568 16:32:10.621871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16569 16:32:10.622291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16571 16:32:10.671647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16573 16:32:10.672368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16574 16:32:10.720679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16575 16:32:10.721081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16577 16:32:10.768151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16578 16:32:10.768566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16580 16:32:10.817094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16582 16:32:10.817501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16583 16:32:10.865382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16584 16:32:10.865800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16586 16:32:10.913959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16588 16:32:10.914354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16589 16:32:10.962329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16591 16:32:10.962905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16592 16:32:11.011312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16594 16:32:11.012151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16595 16:32:11.059960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16596 16:32:11.060350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16598 16:32:11.108038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16599 16:32:11.108398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16601 16:32:11.156200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16603 16:32:11.156657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16604 16:32:11.204295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16605 16:32:11.204703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16607 16:32:11.253173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16608 16:32:11.253594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16610 16:32:11.301622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16612 16:32:11.302041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16613 16:32:11.348375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16614 16:32:11.348757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16616 16:32:11.396108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16617 16:32:11.396521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16619 16:32:11.444025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16621 16:32:11.444511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16622 16:32:11.491986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16623 16:32:11.492397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16625 16:32:11.540393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16626 16:32:11.540793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16628 16:32:11.588256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16630 16:32:11.588693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16631 16:32:11.637412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16632 16:32:11.637796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16634 16:32:11.684841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16635 16:32:11.685242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16637 16:32:11.732579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16638 16:32:11.732996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16640 16:32:11.779873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16641 16:32:11.780272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16643 16:32:11.826881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16644 16:32:11.827298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16646 16:32:11.874393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16648 16:32:11.874811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16649 16:32:11.922625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16651 16:32:11.923086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16652 16:32:11.970953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16653 16:32:11.971384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16655 16:32:12.020888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16656 16:32:12.021318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16658 16:32:12.068607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16659 16:32:12.069047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16661 16:32:12.116099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16663 16:32:12.116373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16664 16:32:12.163878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16665 16:32:12.164177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16667 16:32:12.210961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16669 16:32:12.211267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16670 16:32:12.257428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16671 16:32:12.257677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16673 16:32:12.304484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16674 16:32:12.304857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16676 16:32:12.349902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16677 16:32:12.350327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16679 16:32:12.401206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16680 16:32:12.401631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16682 16:32:12.449515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16683 16:32:12.449966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16685 16:32:12.497552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16687 16:32:12.497916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16688 16:32:12.545652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16689 16:32:12.546062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16691 16:32:12.593167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16693 16:32:12.593463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16694 16:32:12.640597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16695 16:32:12.641006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16697 16:32:12.689652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16698 16:32:12.690086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16700 16:32:12.737367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16702 16:32:12.737855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16703 16:32:12.784527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16704 16:32:12.784863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16706 16:32:12.831404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16707 16:32:12.831677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16709 16:32:12.878078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16711 16:32:12.878395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16712 16:32:12.924280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16713 16:32:12.924555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16715 16:32:12.972049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16717 16:32:12.972361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16718 16:32:13.019440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
16720 16:32:13.019749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
16721 16:32:13.066238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
16723 16:32:13.066569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
16724 16:32:13.113450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
16725 16:32:13.113743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
16727 16:32:13.161659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
16728 16:32:13.161950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
16730 16:32:13.209419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
16731 16:32:13.209677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
16733 16:32:13.258509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
16735 16:32:13.258832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
16736 16:32:13.305937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
16737 16:32:13.306238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
16739 16:32:13.353792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
16740 16:32:13.354180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
16742 16:32:13.401269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
16743 16:32:13.401689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
16745 16:32:13.449048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
16746 16:32:13.449451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
16748 16:32:13.497283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
16749 16:32:13.497686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
16751 16:32:13.545937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
16753 16:32:13.546279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
16754 16:32:13.593451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
16756 16:32:13.593752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
16757 16:32:13.640498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
16759 16:32:13.640791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
16760 16:32:13.687811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
16762 16:32:13.688052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
16763 16:32:13.733161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
16764 16:32:13.733456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
16766 16:32:13.784371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
16767 16:32:13.784668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
16769 16:32:13.831682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
16771 16:32:13.831917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
16772 16:32:13.879977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
16774 16:32:13.880442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
16775 16:32:13.930999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
16777 16:32:13.931444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
16778 16:32:13.979757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
16780 16:32:13.980183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
16781 16:32:14.029298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
16782 16:32:14.029686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
16784 16:32:14.076381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
16786 16:32:14.076818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
16787 16:32:14.125086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
16789 16:32:14.125570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
16790 16:32:14.173800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
16791 16:32:14.174217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
16793 16:32:14.223676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
16795 16:32:14.224159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
16796 16:32:14.271535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
16797 16:32:14.271950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
16799 16:32:14.318794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
16800 16:32:14.319154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
16802 16:32:14.367780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
16804 16:32:14.368272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
16805 16:32:14.415435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
16807 16:32:14.415917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
16808 16:32:14.462563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
16810 16:32:14.463029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
16811 16:32:14.510708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
16813 16:32:14.511618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
16814 16:32:14.560441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
16815 16:32:14.560785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
16817 16:32:14.608902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
16818 16:32:14.609314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
16820 16:32:14.657321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
16821 16:32:14.657690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
16823 16:32:14.705702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
16824 16:32:14.706140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
16826 16:32:14.750098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
16827 16:32:14.750522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
16829 16:32:14.797500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
16830 16:32:14.797913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
16832 16:32:14.840659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
16834 16:32:14.841107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
16835 16:32:14.910969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
16836 16:32:14.911389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
16838 16:32:14.969300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
16840 16:32:14.969733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
16841 16:32:15.017439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
16842 16:32:15.017868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
16844 16:32:15.065830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
16846 16:32:15.066212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
16847 16:32:15.114260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
16849 16:32:15.114774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
16850 16:32:15.162022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
16851 16:32:15.162405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
16853 16:32:15.209317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
16854 16:32:15.209691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
16856 16:32:15.253143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
16858 16:32:15.253583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
16859 16:32:15.300955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
16860 16:32:15.301368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
16862 16:32:15.348799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
16864 16:32:15.349250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
16865 16:32:15.396544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
16866 16:32:15.396924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
16868 16:32:15.444265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
16870 16:32:15.444687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
16871 16:32:15.492412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
16872 16:32:15.492827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
16874 16:32:15.539725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
16875 16:32:15.540132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
16877 16:32:15.586840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
16879 16:32:15.587240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
16880 16:32:15.633856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
16881 16:32:15.634247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
16883 16:32:15.681339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
16884 16:32:15.681761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
16886 16:32:15.729209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
16887 16:32:15.729621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
16889 16:32:15.778456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
16891 16:32:15.778922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
16892 16:32:15.825686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
16893 16:32:15.826099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
16895 16:32:15.873521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
16896 16:32:15.873941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
16898 16:32:15.922300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
16900 16:32:15.922764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
16901 16:32:15.969931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
16902 16:32:15.970351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
16904 16:32:16.017470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
16905 16:32:16.017887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
16907 16:32:16.065160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
16909 16:32:16.065594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
16910 16:32:16.113024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
16912 16:32:16.113423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
16913 16:32:16.160425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
16914 16:32:16.160843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
16916 16:32:16.207922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
16917 16:32:16.208337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
16919 16:32:16.255955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
16920 16:32:16.256368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
16922 16:32:16.305363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
16923 16:32:16.305746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
16925 16:32:16.353475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
16926 16:32:16.353885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
16928 16:32:16.402014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
16930 16:32:16.402439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
16931 16:32:16.449913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
16932 16:32:16.450322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
16934 16:32:16.499290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
16936 16:32:16.499737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
16937 16:32:16.547673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
16938 16:32:16.548079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
16940 16:32:16.595998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
16941 16:32:16.596370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
16943 16:32:16.640580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
16945 16:32:16.641006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
16946 16:32:16.689014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
16947 16:32:16.689401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
16949 16:32:16.736470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
16950 16:32:16.736872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
16952 16:32:16.784221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
16953 16:32:16.784634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
16955 16:32:16.831549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
16956 16:32:16.831968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
16958 16:32:16.878401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
16960 16:32:16.878816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
16961 16:32:16.927913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
16962 16:32:16.928319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
16964 16:32:16.975837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
16965 16:32:16.976254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
16967 16:32:17.024522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
16968 16:32:17.024957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
16970 16:32:17.072433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
16971 16:32:17.072853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
16973 16:32:17.120129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
16974 16:32:17.120541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
16976 16:32:17.164587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
16977 16:32:17.164991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
16979 16:32:17.211974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
16980 16:32:17.212389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
16982 16:32:17.260393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
16983 16:32:17.260809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
16985 16:32:17.310303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
16987 16:32:17.310787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
16988 16:32:17.360522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
16989 16:32:17.360894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
16991 16:32:17.407994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
16992 16:32:17.408418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
16994 16:32:17.455372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
16996 16:32:17.455835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
16997 16:32:17.503912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
16998 16:32:17.504302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17000 16:32:17.550979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17001 16:32:17.551379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17003 16:32:17.596577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17004 16:32:17.596954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17006 16:32:17.644933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17007 16:32:17.645353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17009 16:32:17.693223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17010 16:32:17.693605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17012 16:32:17.740488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17013 16:32:17.740895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17015 16:32:17.788460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17016 16:32:17.788860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17018 16:32:17.835717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17019 16:32:17.836120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17021 16:32:17.883118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17022 16:32:17.883521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17024 16:32:17.928779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17026 16:32:17.929230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17027 16:32:17.979543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17028 16:32:17.979847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17030 16:32:18.029107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17031 16:32:18.029372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17033 16:32:18.075856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17034 16:32:18.076157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17036 16:32:18.124338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17038 16:32:18.124768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17039 16:32:18.173519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17040 16:32:18.173960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17042 16:32:18.221272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17043 16:32:18.221689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17045 16:32:18.268910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17047 16:32:18.269299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17048 16:32:18.315956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17050 16:32:18.316320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17051 16:32:18.363201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17053 16:32:18.363616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17054 16:32:18.412863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17056 16:32:18.413311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17057 16:32:18.463937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17059 16:32:18.464358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17060 16:32:18.510915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17061 16:32:18.511318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17063 16:32:18.560277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17064 16:32:18.560699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17066 16:32:18.607519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17068 16:32:18.607942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17069 16:32:18.654380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17071 16:32:18.654835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17072 16:32:18.701911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17073 16:32:18.702316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17075 16:32:18.749490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17077 16:32:18.749952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17078 16:32:18.796129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17079 16:32:18.796492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17081 16:32:18.844226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17082 16:32:18.844536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17084 16:32:18.909463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17086 16:32:18.909918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17087 16:32:18.957241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17088 16:32:18.957632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17090 16:32:19.006143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17092 16:32:19.007963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17093 16:32:19.056004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17095 16:32:19.056488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17096 16:32:19.104410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17097 16:32:19.104825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17099 16:32:19.152597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17100 16:32:19.153012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17102 16:32:19.199775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17103 16:32:19.200201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17105 16:32:19.245671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17106 16:32:19.246075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17108 16:32:19.293184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17109 16:32:19.293560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17111 16:32:19.341714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17112 16:32:19.342143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17114 16:32:19.391202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17115 16:32:19.391635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17117 16:32:19.443808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17119 16:32:19.444255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17120 16:32:19.490937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17121 16:32:19.491353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17123 16:32:19.538221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17125 16:32:19.538681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17126 16:32:19.585748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17128 16:32:19.586213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17129 16:32:19.633710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17131 16:32:19.634130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17132 16:32:19.681496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17134 16:32:19.681954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17135 16:32:19.729203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17137 16:32:19.729648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17138 16:32:19.775937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17139 16:32:19.776320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17141 16:32:19.822790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17142 16:32:19.823213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17144 16:32:19.869610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17145 16:32:19.870019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17147 16:32:19.922310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17149 16:32:19.922734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17150 16:32:19.980718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17152 16:32:19.981087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17153 16:32:20.029356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17154 16:32:20.029791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17156 16:32:20.074839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17158 16:32:20.075300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17159 16:32:20.123507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17160 16:32:20.123937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17162 16:32:20.171313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17163 16:32:20.171687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17165 16:32:20.219469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17166 16:32:20.219880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17168 16:32:20.267506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17170 16:32:20.267928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17171 16:32:20.314952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17172 16:32:20.315356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17174 16:32:20.363022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17176 16:32:20.363449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17177 16:32:20.411689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17179 16:32:20.412140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17180 16:32:20.455780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17181 16:32:20.456196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17183 16:32:20.504052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17185 16:32:20.504532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17186 16:32:20.553408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17187 16:32:20.553832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17189 16:32:20.602192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17191 16:32:20.602632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17192 16:32:20.650175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17194 16:32:20.650617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17195 16:32:20.697715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17196 16:32:20.698141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17198 16:32:20.745690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17200 16:32:20.746142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17201 16:32:20.792921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17202 16:32:20.793220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17204 16:32:20.835589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17205 16:32:20.835888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17207 16:32:20.883427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17208 16:32:20.883719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17210 16:32:20.931578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17211 16:32:20.931976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17213 16:32:20.980103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17214 16:32:20.980511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17216 16:32:21.028056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17217 16:32:21.028432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17219 16:32:21.075334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17220 16:32:21.075738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17222 16:32:21.122246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17224 16:32:21.122679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17225 16:32:21.169249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17227 16:32:21.169608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17228 16:32:21.216503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17229 16:32:21.216776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17231 16:32:21.264991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17232 16:32:21.265285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17234 16:32:21.313151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17236 16:32:21.313461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17237 16:32:21.360597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17238 16:32:21.360881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17240 16:32:21.407850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17241 16:32:21.408145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17243 16:32:21.454311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17245 16:32:21.454690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17246 16:32:21.501277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17247 16:32:21.501686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17249 16:32:21.547917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17250 16:32:21.548342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17252 16:32:21.595178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17253 16:32:21.595574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17255 16:32:21.642249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17257 16:32:21.642629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17258 16:32:21.689496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17259 16:32:21.689882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17261 16:32:21.737885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17263 16:32:21.738318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17264 16:32:21.786741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17266 16:32:21.787569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17267 16:32:21.835346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17268 16:32:21.835753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17270 16:32:21.883669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17271 16:32:21.884072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17273 16:32:21.931867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17274 16:32:21.932282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17276 16:32:21.979418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17277 16:32:21.979823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17279 16:32:22.028386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17280 16:32:22.028763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17282 16:32:22.078050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17284 16:32:22.078633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17285 16:32:22.125323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17287 16:32:22.125772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17288 16:32:22.178386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17289 16:32:22.178839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17291 16:32:22.223764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17292 16:32:22.224193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17294 16:32:22.273679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17295 16:32:22.274109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17297 16:32:22.323098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17298 16:32:22.323508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17300 16:32:22.370453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17302 16:32:22.370904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17303 16:32:22.420746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17305 16:32:22.421174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17306 16:32:22.469064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17308 16:32:22.469491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17309 16:32:22.517702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17310 16:32:22.518118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17312 16:32:22.566935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17314 16:32:22.567364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17315 16:32:22.617137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17316 16:32:22.617590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17318 16:32:22.661830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17319 16:32:22.662257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17321 16:32:22.709536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17323 16:32:22.709934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17324 16:32:22.755937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17325 16:32:22.756306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17327 16:32:22.807760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17328 16:32:22.808162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17330 16:32:22.853607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17332 16:32:22.853996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17333 16:32:22.900838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17334 16:32:22.901219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17336 16:32:22.948100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17337 16:32:22.948400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17339 16:32:22.996080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17340 16:32:22.996434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17342 16:32:23.043891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17343 16:32:23.044202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17345 16:32:23.092705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17346 16:32:23.093129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17348 16:32:23.141223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17349 16:32:23.141657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17351 16:32:23.190941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17352 16:32:23.191360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17354 16:32:23.236648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17355 16:32:23.237029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17357 16:32:23.285111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17359 16:32:23.285524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17360 16:32:23.333846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17362 16:32:23.334322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17363 16:32:23.384973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17364 16:32:23.385380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17366 16:32:23.432885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17367 16:32:23.433303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17369 16:32:23.484139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17370 16:32:23.484549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17372 16:32:23.533755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17373 16:32:23.534122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17375 16:32:23.582856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17376 16:32:23.583216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17378 16:32:23.629451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17379 16:32:23.629814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17381 16:32:23.681476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17382 16:32:23.681780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17384 16:32:23.729691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17386 16:32:23.730037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17387 16:32:23.777023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17388 16:32:23.777379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17390 16:32:23.827389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17391 16:32:23.827803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17393 16:32:23.875608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17394 16:32:23.876041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17396 16:32:23.923432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17397 16:32:23.923842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17399 16:32:23.974386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17401 16:32:23.974844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17402 16:32:24.047906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17404 16:32:24.048326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17405 16:32:24.095140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17406 16:32:24.095551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17408 16:32:24.143167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17410 16:32:24.143592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17411 16:32:24.190515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17413 16:32:24.191167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17414 16:32:24.238997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17415 16:32:24.239406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17417 16:32:24.287154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17418 16:32:24.287555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17420 16:32:24.333551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17422 16:32:24.333990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17423 16:32:24.385846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17424 16:32:24.386264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17426 16:32:24.431271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17427 16:32:24.431690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17429 16:32:24.479337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17430 16:32:24.479756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17432 16:32:24.528078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17433 16:32:24.528495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17435 16:32:24.576074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17436 16:32:24.576482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17438 16:32:24.625511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17439 16:32:24.625958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17441 16:32:24.672029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17442 16:32:24.672466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17444 16:32:24.719776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17446 16:32:24.720271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17447 16:32:24.767656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17448 16:32:24.768089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17450 16:32:24.815608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17451 16:32:24.816029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17453 16:32:24.864091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17454 16:32:24.864506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17456 16:32:24.912541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17457 16:32:24.912958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17459 16:32:24.966694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17461 16:32:24.967265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17462 16:32:25.021133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17463 16:32:25.021572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17465 16:32:25.074916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17467 16:32:25.075525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17468 16:32:25.123949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17470 16:32:25.124375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17471 16:32:25.171236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17472 16:32:25.171652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17474 16:32:25.218693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17476 16:32:25.219127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17477 16:32:25.265522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17478 16:32:25.265942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17480 16:32:25.313412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17482 16:32:25.313869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17483 16:32:25.361402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17484 16:32:25.361816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17486 16:32:25.409249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17487 16:32:25.409664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17489 16:32:25.459690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17490 16:32:25.460114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17492 16:32:25.507605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17493 16:32:25.508020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17495 16:32:25.556416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17496 16:32:25.556847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17498 16:32:25.603899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17499 16:32:25.604315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17501 16:32:25.652043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17502 16:32:25.652457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17504 16:32:25.700582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17505 16:32:25.701020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17507 16:32:25.748370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17508 16:32:25.748780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17510 16:32:25.796160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17511 16:32:25.796565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17513 16:32:25.846292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17515 16:32:25.846751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17516 16:32:25.893714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17517 16:32:25.894132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17519 16:32:25.941936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17520 16:32:25.942375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17522 16:32:25.990418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17524 16:32:25.990885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17525 16:32:26.039438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17526 16:32:26.039848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17528 16:32:26.087450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17529 16:32:26.087863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17531 16:32:26.135284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17533 16:32:26.135773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17534 16:32:26.183725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17535 16:32:26.184142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17537 16:32:26.231658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17539 16:32:26.232092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17540 16:32:26.281446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17542 16:32:26.281900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17543 16:32:26.333728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17545 16:32:26.334201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17546 16:32:26.383284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17547 16:32:26.383705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17549 16:32:26.432738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17550 16:32:26.433158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17552 16:32:26.483346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17553 16:32:26.483761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17555 16:32:26.532302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17557 16:32:26.532745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17558 16:32:26.580780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17559 16:32:26.581187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17561 16:32:26.632078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17563 16:32:26.632535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17564 16:32:26.684376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17566 16:32:26.684868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17567 16:32:26.732255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17568 16:32:26.732690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17570 16:32:26.784758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17571 16:32:26.785222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17573 16:32:26.840775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17575 16:32:26.841279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17576 16:32:26.892452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17577 16:32:26.892897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17579 16:32:26.939973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17580 16:32:26.940383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17582 16:32:26.988026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17583 16:32:26.988444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17585 16:32:27.040080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17586 16:32:27.040500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17588 16:32:27.088718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17589 16:32:27.089129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17591 16:32:27.139412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17592 16:32:27.139832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17594 16:32:27.187520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17595 16:32:27.187940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17597 16:32:27.235879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17598 16:32:27.236289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17600 16:32:27.283487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17601 16:32:27.283890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17603 16:32:27.331055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17604 16:32:27.331444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17606 16:32:27.378453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17608 16:32:27.378933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17609 16:32:27.427049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17610 16:32:27.427385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17612 16:32:27.474433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17614 16:32:27.474900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17615 16:32:27.523391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17617 16:32:27.523835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17618 16:32:27.571224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17619 16:32:27.571641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17621 16:32:27.618857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17622 16:32:27.619279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17624 16:32:27.666118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17625 16:32:27.666533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17627 16:32:27.713882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17629 16:32:27.714342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17630 16:32:27.761458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17631 16:32:27.761885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17633 16:32:27.808784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17634 16:32:27.809188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17636 16:32:27.856740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17638 16:32:27.857235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17639 16:32:27.904754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17640 16:32:27.905183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17642 16:32:27.952397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17643 16:32:27.952805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17645 16:32:27.999954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17646 16:32:28.000347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17648 16:32:28.047018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17649 16:32:28.047416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17651 16:32:28.092907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17652 16:32:28.093315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17654 16:32:28.140545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17655 16:32:28.140954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17657 16:32:28.188822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17658 16:32:28.189193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17660 16:32:28.236306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17661 16:32:28.236724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17663 16:32:28.283930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17665 16:32:28.284380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17666 16:32:28.331708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17667 16:32:28.332114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17669 16:32:28.379248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17670 16:32:28.379661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17672 16:32:28.426845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17673 16:32:28.427250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17675 16:32:28.473972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17676 16:32:28.474383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17678 16:32:28.521715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17679 16:32:28.522126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17681 16:32:28.569932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17682 16:32:28.570341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17684 16:32:28.619258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17686 16:32:28.619688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17687 16:32:28.666888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17688 16:32:28.667332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17690 16:32:28.716873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17691 16:32:28.717356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17693 16:32:28.769194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17694 16:32:28.769583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17696 16:32:28.820638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17697 16:32:28.821087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17699 16:32:28.874900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17701 16:32:28.875336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17702 16:32:28.927685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17704 16:32:28.928168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17705 16:32:28.975841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17707 16:32:28.976308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17708 16:32:29.024141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17709 16:32:29.024568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17711 16:32:29.075640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17713 16:32:29.076115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17714 16:32:29.143402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17715 16:32:29.143822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17717 16:32:29.191072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17718 16:32:29.191486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
17720 16:32:29.238417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
17722 16:32:29.238903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
17723 16:32:29.285686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
17724 16:32:29.286097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
17726 16:32:29.333498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
17727 16:32:29.333902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
17729 16:32:29.381631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
17730 16:32:29.382065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
17732 16:32:29.429321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
17733 16:32:29.429686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
17735 16:32:29.477825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
17736 16:32:29.478296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
17738 16:32:29.526471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
17740 16:32:29.527019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
17741 16:32:29.573881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
17742 16:32:29.574308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
17744 16:32:29.621487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
17745 16:32:29.621879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
17747 16:32:29.669165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
17749 16:32:29.669612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
17750 16:32:29.716259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
17751 16:32:29.716633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
17753 16:32:29.762440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
17755 16:32:29.762864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
17756 16:32:29.809713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
17758 16:32:29.810189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
17759 16:32:29.856774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
17761 16:32:29.857209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
17762 16:32:29.904679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
17764 16:32:29.905103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
17765 16:32:29.952070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
17766 16:32:29.957507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
17768 16:32:30.003061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
17769 16:32:30.003477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
17771 16:32:30.052477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
17772 16:32:30.052894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
17774 16:32:30.101948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
17776 16:32:30.102381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
17777 16:32:30.149477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
17778 16:32:30.149893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
17780 16:32:30.196793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
17781 16:32:30.197202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
17783 16:32:30.244990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
17784 16:32:30.245361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
17786 16:32:30.292713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
17787 16:32:30.293087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
17789 16:32:30.339983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
17791 16:32:30.340423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
17792 16:32:30.387382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
17793 16:32:30.387793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
17795 16:32:30.434825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
17796 16:32:30.435239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
17798 16:32:30.482251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
17800 16:32:30.483134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
17801 16:32:30.529772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
17802 16:32:30.530188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
17804 16:32:30.577086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
17805 16:32:30.577384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
17807 16:32:30.624700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
17808 16:32:30.624993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
17810 16:32:30.672847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
17811 16:32:30.673194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
17813 16:32:30.719952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
17814 16:32:30.720356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
17816 16:32:30.767670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
17817 16:32:30.768081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
17819 16:32:30.813791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
17820 16:32:30.814194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
17822 16:32:30.861446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
17823 16:32:30.861862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
17825 16:32:30.909003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
17826 16:32:30.909409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
17828 16:32:30.956110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
17829 16:32:30.956531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
17831 16:32:31.006292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
17833 16:32:31.006794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
17834 16:32:31.053118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
17835 16:32:31.053420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
17837 16:32:31.099955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
17838 16:32:31.100250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
17840 16:32:31.146850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
17841 16:32:31.147141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
17843 16:32:31.193395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
17844 16:32:31.193678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
17846 16:32:31.240850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
17848 16:32:31.241151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
17849 16:32:31.289138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
17850 16:32:31.289434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
17852 16:32:31.335910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
17853 16:32:31.336205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
17855 16:32:31.383197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
17856 16:32:31.383492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
17858 16:32:31.429682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
17859 16:32:31.429978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
17861 16:32:31.477411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
17862 16:32:31.477677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
17864 16:32:31.523908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
17865 16:32:31.524202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
17867 16:32:31.571052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
17869 16:32:31.571346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
17870 16:32:31.617679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
17872 16:32:31.617969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
17873 16:32:31.665079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
17874 16:32:31.665491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
17876 16:32:31.712659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
17877 16:32:31.713071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
17879 16:32:31.760772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
17880 16:32:31.761187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
17882 16:32:31.808534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
17883 16:32:31.808958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
17885 16:32:31.856334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
17887 16:32:31.856739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
17888 16:32:31.899863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
17889 16:32:31.900268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
17891 16:32:31.947298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
17892 16:32:31.947717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
17894 16:32:31.994445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
17895 16:32:31.994863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
17897 16:32:32.043533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
17898 16:32:32.043951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
17900 16:32:32.090756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
17901 16:32:32.091168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
17903 16:32:32.138951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
17904 16:32:32.139366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
17906 16:32:32.188465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
17907 16:32:32.188884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
17909 16:32:32.239949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
17910 16:32:32.240333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
17912 16:32:32.287560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
17913 16:32:32.287942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
17915 16:32:32.332536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
17916 16:32:32.332942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
17918 16:32:32.377663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
17919 16:32:32.378075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
17921 16:32:32.427001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
17922 16:32:32.427445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
17924 16:32:32.476441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
17925 16:32:32.476865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
17927 16:32:32.524499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
17928 16:32:32.524914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
17930 16:32:32.572048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
17931 16:32:32.572454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
17933 16:32:32.619308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
17934 16:32:32.619686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
17936 16:32:32.665452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
17937 16:32:32.665889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
17939 16:32:32.713232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
17940 16:32:32.713659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
17942 16:32:32.760678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
17943 16:32:32.761101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
17945 16:32:32.809049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
17946 16:32:32.809460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
17948 16:32:32.856740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
17949 16:32:32.857153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
17951 16:32:32.903907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
17953 16:32:32.904372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
17954 16:32:32.951546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
17955 16:32:32.951966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
17957 16:32:32.998612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
17959 16:32:32.999016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
17960 16:32:33.044955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
17961 16:32:33.045369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
17963 16:32:33.092126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
17965 16:32:33.092565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
17966 16:32:33.139822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
17968 16:32:33.140284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
17969 16:32:33.187149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
17970 16:32:33.187559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
17972 16:32:33.234056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
17973 16:32:33.234481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
17975 16:32:33.284586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
17976 16:32:33.284978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
17978 16:32:33.332550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
17980 16:32:33.332952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
17981 16:32:33.379633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
17982 16:32:33.380030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
17984 16:32:33.427358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
17985 16:32:33.427769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
17987 16:32:33.474298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
17989 16:32:33.474846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
17990 16:32:33.521583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
17991 16:32:33.522012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
17993 16:32:33.570337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
17995 16:32:33.570939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
17996 16:32:33.617713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
17997 16:32:33.618132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
17999 16:32:33.665936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18001 16:32:33.666391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18002 16:32:33.713713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18003 16:32:33.714124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18005 16:32:33.761287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18006 16:32:33.761669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18008 16:32:33.809101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18010 16:32:33.809537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18011 16:32:33.856042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18012 16:32:33.856463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18014 16:32:33.903461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18015 16:32:33.903869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18017 16:32:33.950329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18019 16:32:33.950787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18020 16:32:33.999243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18022 16:32:33.999685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18023 16:32:34.047696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18024 16:32:34.048135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18026 16:32:34.095396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18027 16:32:34.095803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18029 16:32:34.141443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18030 16:32:34.141857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18032 16:32:34.189295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18033 16:32:34.189685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18035 16:32:34.251981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18036 16:32:34.252412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18038 16:32:34.307418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18039 16:32:34.307827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18041 16:32:34.357112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18042 16:32:34.357522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18044 16:32:34.405061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18045 16:32:34.405436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18047 16:32:34.451981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18048 16:32:34.452389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18050 16:32:34.499416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18051 16:32:34.499821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18053 16:32:34.546813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18055 16:32:34.547235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18056 16:32:34.592931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18058 16:32:34.593360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18059 16:32:34.640400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18060 16:32:34.640824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18062 16:32:34.687888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18063 16:32:34.688300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18065 16:32:34.735359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18066 16:32:34.735768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18068 16:32:34.781893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18069 16:32:34.782275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18071 16:32:34.829985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18072 16:32:34.830397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18074 16:32:34.877052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18076 16:32:34.877486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18077 16:32:34.923929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18078 16:32:34.924342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18080 16:32:34.971847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18081 16:32:34.972202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18083 16:32:35.021598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18084 16:32:35.022002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18086 16:32:35.073850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18088 16:32:35.074338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18089 16:32:35.124219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18091 16:32:35.124647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18092 16:32:35.171120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18093 16:32:35.171525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18095 16:32:35.219860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18096 16:32:35.220243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18098 16:32:35.267185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18099 16:32:35.267599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18101 16:32:35.314920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18102 16:32:35.315334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18104 16:32:35.362600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18106 16:32:35.363146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18107 16:32:35.411340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18108 16:32:35.411765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18110 16:32:35.460548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18111 16:32:35.460967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18113 16:32:35.508112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18114 16:32:35.508552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18116 16:32:35.555956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18117 16:32:35.556372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18119 16:32:35.603754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18120 16:32:35.604164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18122 16:32:35.651079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18123 16:32:35.651501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18125 16:32:35.698073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18126 16:32:35.698506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18128 16:32:35.745689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18129 16:32:35.746103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18131 16:32:35.792976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18132 16:32:35.793385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18134 16:32:35.840107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18135 16:32:35.840524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18137 16:32:35.888510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18138 16:32:35.888922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18140 16:32:35.935997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18141 16:32:35.936403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18143 16:32:35.983576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18145 16:32:35.984000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18146 16:32:36.031186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18148 16:32:36.031612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18149 16:32:36.078427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18151 16:32:36.078874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18152 16:32:36.125853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18154 16:32:36.126290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18155 16:32:36.173778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18157 16:32:36.174241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18158 16:32:36.221812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18159 16:32:36.222220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18161 16:32:36.268193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18163 16:32:36.268606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18164 16:32:36.315544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18165 16:32:36.315970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18167 16:32:36.363847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18168 16:32:36.364240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18170 16:32:36.411734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18171 16:32:36.412166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18173 16:32:36.459329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18174 16:32:36.459704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18176 16:32:36.508101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18177 16:32:36.508537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18179 16:32:36.556632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18181 16:32:36.557121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18182 16:32:36.604585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18183 16:32:36.604996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18185 16:32:36.652709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18186 16:32:36.653121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18188 16:32:36.700554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18189 16:32:36.700937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18191 16:32:36.750097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18192 16:32:36.750509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18194 16:32:36.799782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18195 16:32:36.800205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18197 16:32:36.847535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18198 16:32:36.847940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18200 16:32:36.894196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18202 16:32:36.894661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18203 16:32:36.941670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18204 16:32:36.942083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18206 16:32:36.989531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18207 16:32:36.989954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18209 16:32:37.037245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18210 16:32:37.037664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18212 16:32:37.084318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18214 16:32:37.084801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18215 16:32:37.132901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18216 16:32:37.133317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18218 16:32:37.180828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18219 16:32:37.181238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18221 16:32:37.228905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18223 16:32:37.229351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18224 16:32:37.277390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18225 16:32:37.277816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18227 16:32:37.325044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18229 16:32:37.325505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18230 16:32:37.372697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18231 16:32:37.373105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18233 16:32:37.421376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18234 16:32:37.421801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18236 16:32:37.468859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18237 16:32:37.469279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18239 16:32:37.516079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18241 16:32:37.516475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18242 16:32:37.563412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18244 16:32:37.563909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18245 16:32:37.612214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18246 16:32:37.612600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18248 16:32:37.660715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18249 16:32:37.661112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18251 16:32:37.707939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18253 16:32:37.708375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18254 16:32:37.756085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18255 16:32:37.756506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18257 16:32:37.805695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18259 16:32:37.806177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18260 16:32:37.853502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18261 16:32:37.853905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18263 16:32:37.902079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18265 16:32:37.902562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18266 16:32:37.949907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18267 16:32:37.950340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18269 16:32:37.997530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18270 16:32:37.997964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18272 16:32:38.045364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18274 16:32:38.045803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18275 16:32:38.092297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18277 16:32:38.092769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18278 16:32:38.140037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18279 16:32:38.140452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18281 16:32:38.187975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18282 16:32:38.188400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18284 16:32:38.235855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18285 16:32:38.236258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18287 16:32:38.284276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18289 16:32:38.284712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18290 16:32:38.331936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18291 16:32:38.332340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18293 16:32:38.379312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18294 16:32:38.379708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18296 16:32:38.425939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18297 16:32:38.426347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18299 16:32:38.473039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18301 16:32:38.473501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18302 16:32:38.520085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18303 16:32:38.520381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18305 16:32:38.568508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18306 16:32:38.568806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18308 16:32:38.614288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18310 16:32:38.614862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18311 16:32:38.663160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18312 16:32:38.663457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18314 16:32:38.710659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18316 16:32:38.711088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18317 16:32:38.757361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18318 16:32:38.757774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18320 16:32:38.805328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18321 16:32:38.805733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18323 16:32:38.852999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18324 16:32:38.853415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18326 16:32:38.900809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18327 16:32:38.901235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18329 16:32:38.949506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18330 16:32:38.949922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18332 16:32:38.997574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18333 16:32:38.997992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18335 16:32:39.044014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18336 16:32:39.044421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18338 16:32:39.091671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18339 16:32:39.092079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18341 16:32:39.139565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18342 16:32:39.139973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18344 16:32:39.186889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18345 16:32:39.187296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18347 16:32:39.233424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18348 16:32:39.233826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18350 16:32:39.281331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18351 16:32:39.281735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18353 16:32:39.328878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18354 16:32:39.329254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18356 16:32:39.401428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18357 16:32:39.401852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18359 16:32:39.453697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18361 16:32:39.454197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18362 16:32:39.501264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18363 16:32:39.501644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18365 16:32:39.548666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18366 16:32:39.549059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18368 16:32:39.596012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18369 16:32:39.596414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18371 16:32:39.643094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18372 16:32:39.643499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18374 16:32:39.689777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18375 16:32:39.690180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18377 16:32:39.737409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18378 16:32:39.737779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18380 16:32:39.785112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18381 16:32:39.785396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18383 16:32:39.832768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18384 16:32:39.833037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18386 16:32:39.880002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18387 16:32:39.880272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18389 16:32:39.927180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18390 16:32:39.927472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18392 16:32:39.974151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18394 16:32:39.974493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18395 16:32:40.025221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18396 16:32:40.025509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18398 16:32:40.076701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18400 16:32:40.076928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18401 16:32:40.126067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18403 16:32:40.126540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18404 16:32:40.173407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18405 16:32:40.173770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18407 16:32:40.221696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18409 16:32:40.222163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18410 16:32:40.269265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18411 16:32:40.269675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18413 16:32:40.317475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18415 16:32:40.317931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18416 16:32:40.364925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18417 16:32:40.365329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18419 16:32:40.411663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18420 16:32:40.412093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18422 16:32:40.459079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18424 16:32:40.459518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18425 16:32:40.507879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18426 16:32:40.508294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18428 16:32:40.555980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18429 16:32:40.556386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18431 16:32:40.602948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18433 16:32:40.603383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18434 16:32:40.649948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18435 16:32:40.650384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18437 16:32:40.697444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18438 16:32:40.697864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18440 16:32:40.745191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18442 16:32:40.745638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18443 16:32:40.792458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18444 16:32:40.792863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18446 16:32:40.839697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18447 16:32:40.840111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18449 16:32:40.886699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18450 16:32:40.887105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18452 16:32:40.933979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18453 16:32:40.934399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18455 16:32:40.983337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18456 16:32:40.983748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18458 16:32:41.030866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18459 16:32:41.031178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18461 16:32:41.077947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18462 16:32:41.078363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18464 16:32:41.127443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18465 16:32:41.127837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18467 16:32:41.172031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18468 16:32:41.172452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18470 16:32:41.219455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18471 16:32:41.219877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18473 16:32:41.267112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18474 16:32:41.267482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18476 16:32:41.313690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18477 16:32:41.314114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18479 16:32:41.361538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18480 16:32:41.361919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18482 16:32:41.409355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18483 16:32:41.409684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18485 16:32:41.457199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18486 16:32:41.457492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18488 16:32:41.504717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18489 16:32:41.505000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18491 16:32:41.552004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18492 16:32:41.552301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18494 16:32:41.599777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18495 16:32:41.600080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18497 16:32:41.647080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18498 16:32:41.647375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18500 16:32:41.693238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18502 16:32:41.693529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18503 16:32:41.741102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18505 16:32:41.741502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18506 16:32:41.793898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18507 16:32:41.794282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18509 16:32:41.843260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18510 16:32:41.843704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18512 16:32:41.891211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18513 16:32:41.891630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18515 16:32:41.932343 <47>[ 224.538501] systemd-journald[105]: Sent WATCHDOG=1 notification.
18516 16:32:41.943902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18517 16:32:41.944238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18519 16:32:41.991894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18520 16:32:41.992310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18522 16:32:42.040453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18523 16:32:42.040864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18525 16:32:42.088772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18526 16:32:42.089186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18528 16:32:42.136602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18530 16:32:42.137088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18531 16:32:42.183861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18532 16:32:42.184275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18534 16:32:42.231488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18535 16:32:42.231890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18537 16:32:42.277315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18539 16:32:42.277691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18540 16:32:42.322256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18542 16:32:42.322694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18543 16:32:42.369433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18544 16:32:42.369848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18546 16:32:42.416883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18547 16:32:42.417309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18549 16:32:42.465210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18551 16:32:42.465696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18552 16:32:42.513182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18553 16:32:42.513591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18555 16:32:42.561273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18556 16:32:42.561687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18558 16:32:42.611596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18559 16:32:42.612008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18561 16:32:42.659641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18562 16:32:42.660089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18564 16:32:42.707466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18565 16:32:42.707867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18567 16:32:42.753933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18568 16:32:42.754342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18570 16:32:42.801782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18571 16:32:42.802193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18573 16:32:42.849265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18574 16:32:42.849657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18576 16:32:42.898077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18578 16:32:42.898548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18579 16:32:42.947370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18580 16:32:42.947786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18582 16:32:42.996140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18583 16:32:42.996559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18585 16:32:43.043852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18586 16:32:43.044264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18588 16:32:43.090926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18590 16:32:43.091358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18591 16:32:43.137429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18593 16:32:43.137875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18594 16:32:43.184706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18595 16:32:43.185117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18597 16:32:43.232561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18598 16:32:43.232986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18600 16:32:43.281909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18601 16:32:43.282345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18603 16:32:43.328946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18605 16:32:43.329374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18606 16:32:43.377450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18607 16:32:43.377864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18609 16:32:43.426399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18611 16:32:43.426836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18612 16:32:43.474023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18614 16:32:43.474497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18615 16:32:43.522095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18617 16:32:43.523061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18618 16:32:43.571837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18619 16:32:43.572268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18621 16:32:43.618968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18622 16:32:43.619374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18624 16:32:43.665430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18625 16:32:43.665829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18627 16:32:43.712657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18629 16:32:43.713097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18630 16:32:43.760211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18632 16:32:43.760636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18633 16:32:43.807006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18634 16:32:43.807413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18636 16:32:43.853072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18638 16:32:43.853520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18639 16:32:43.900041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18640 16:32:43.900396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18642 16:32:43.947600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18644 16:32:43.948030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18645 16:32:43.994273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18647 16:32:43.994705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18648 16:32:44.043087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18649 16:32:44.043504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18651 16:32:44.089933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18652 16:32:44.090346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18654 16:32:44.137135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18655 16:32:44.137537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18657 16:32:44.184011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18658 16:32:44.184422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18660 16:32:44.231471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18662 16:32:44.231939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18663 16:32:44.278219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18665 16:32:44.278675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18666 16:32:44.325549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18667 16:32:44.325967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18669 16:32:44.372654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18670 16:32:44.373062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18672 16:32:44.420364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18673 16:32:44.420743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18675 16:32:44.475920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18677 16:32:44.476349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18678 16:32:44.536134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18680 16:32:44.536574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18681 16:32:44.583325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18682 16:32:44.583736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18684 16:32:44.629752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18685 16:32:44.630088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18687 16:32:44.676916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18689 16:32:44.677209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18690 16:32:44.723767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18692 16:32:44.724062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18693 16:32:44.770293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18695 16:32:44.770658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18696 16:32:44.817915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18697 16:32:44.818203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18699 16:32:44.865121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18700 16:32:44.865411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18702 16:32:44.911883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18703 16:32:44.912174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18705 16:32:44.959237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18706 16:32:44.959524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18708 16:32:45.005443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18710 16:32:45.005902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18711 16:32:45.053190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18712 16:32:45.053607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18714 16:32:45.101642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18716 16:32:45.102103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18717 16:32:45.148808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18718 16:32:45.149211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
18720 16:32:45.196029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
18721 16:32:45.196442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
18723 16:32:45.243651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
18724 16:32:45.244063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
18726 16:32:45.291262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
18727 16:32:45.291675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
18729 16:32:45.337596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
18730 16:32:45.338004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
18732 16:32:45.383540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
18733 16:32:45.383947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
18735 16:32:45.430770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
18736 16:32:45.431174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
18738 16:32:45.477912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
18740 16:32:45.478366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
18741 16:32:45.525160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
18743 16:32:45.525603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
18744 16:32:45.572850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
18745 16:32:45.573213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
18747 16:32:45.620749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
18748 16:32:45.621163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
18750 16:32:45.667364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
18751 16:32:45.667772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
18753 16:32:45.714832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
18754 16:32:45.715247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
18756 16:32:45.761262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
18757 16:32:45.761686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
18759 16:32:45.808375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
18760 16:32:45.808802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
18762 16:32:45.855770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
18763 16:32:45.856168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
18765 16:32:45.901621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
18766 16:32:45.902038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
18768 16:32:45.949383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
18769 16:32:45.949769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
18771 16:32:45.996128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
18772 16:32:45.996535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
18774 16:32:46.043308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
18775 16:32:46.043720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
18777 16:32:46.089825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
18778 16:32:46.090241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
18780 16:32:46.137507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
18781 16:32:46.137893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
18783 16:32:46.181001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
18784 16:32:46.181424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
18786 16:32:46.227881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
18787 16:32:46.228175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
18789 16:32:46.275148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
18790 16:32:46.275436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
18792 16:32:46.322428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
18794 16:32:46.322860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
18795 16:32:46.369608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
18796 16:32:46.370029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
18798 16:32:46.417407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
18800 16:32:46.417872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
18801 16:32:46.464551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
18802 16:32:46.464965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
18804 16:32:46.514248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
18806 16:32:46.514682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
18807 16:32:46.563741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
18809 16:32:46.564220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
18810 16:32:46.612214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
18811 16:32:46.612586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
18813 16:32:46.659918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
18815 16:32:46.660349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
18816 16:32:46.704440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
18818 16:32:46.704891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
18819 16:32:46.755003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
18820 16:32:46.755415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
18822 16:32:46.802571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
18824 16:32:46.803028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
18825 16:32:46.849703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
18827 16:32:46.850136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
18828 16:32:46.896746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
18829 16:32:46.897153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
18831 16:32:46.944192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
18833 16:32:46.944611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
18834 16:32:46.991603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
18835 16:32:46.992028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
18837 16:32:47.038792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
18838 16:32:47.039218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
18840 16:32:47.086578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
18842 16:32:47.087052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
18843 16:32:47.132906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
18844 16:32:47.133276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
18846 16:32:47.181709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
18847 16:32:47.182137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
18849 16:32:47.229230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
18850 16:32:47.229606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
18852 16:32:47.276542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
18853 16:32:47.276938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
18855 16:32:47.323481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
18857 16:32:47.323917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
18858 16:32:47.369570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
18859 16:32:47.369866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
18861 16:32:47.417400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
18862 16:32:47.417771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
18864 16:32:47.467096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
18865 16:32:47.467494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
18867 16:32:47.514330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
18869 16:32:47.514744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
18870 16:32:47.560976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
18871 16:32:47.561269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
18873 16:32:47.607701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
18874 16:32:47.607994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
18876 16:32:47.653808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
18877 16:32:47.654099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
18879 16:32:47.700559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
18880 16:32:47.700833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
18882 16:32:47.747566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
18884 16:32:47.747897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
18885 16:32:47.792916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
18886 16:32:47.793205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
18888 16:32:47.840404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
18889 16:32:47.840696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
18891 16:32:47.887641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
18893 16:32:47.887930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
18894 16:32:47.933640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
18895 16:32:47.933941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
18897 16:32:47.980704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
18898 16:32:47.981008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
18900 16:32:48.027250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
18902 16:32:48.027542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
18903 16:32:48.073414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
18904 16:32:48.073833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
18906 16:32:48.122061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
18908 16:32:48.122532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
18909 16:32:48.169307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
18910 16:32:48.169686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
18912 16:32:48.216160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
18913 16:32:48.216491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
18915 16:32:48.262265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
18917 16:32:48.262710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
18918 16:32:48.307700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
18919 16:32:48.307989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
18921 16:32:48.354933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
18922 16:32:48.355343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
18924 16:32:48.401248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
18925 16:32:48.401537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
18927 16:32:48.448511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
18929 16:32:48.448800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
18930 16:32:48.495709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
18931 16:32:48.496108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
18933 16:32:48.543655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
18934 16:32:48.544054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
18936 16:32:48.590383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
18938 16:32:48.590846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
18939 16:32:48.637871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
18941 16:32:48.638307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
18942 16:32:48.685610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
18944 16:32:48.686055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
18945 16:32:48.736281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
18947 16:32:48.736734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
18948 16:32:48.787772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
18949 16:32:48.788206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
18951 16:32:48.838031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
18953 16:32:48.838477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
18954 16:32:48.889928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
18956 16:32:48.890410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
18957 16:32:48.939265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
18958 16:32:48.939666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
18960 16:32:48.986954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
18962 16:32:48.987400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
18963 16:32:49.033092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
18964 16:32:49.033502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
18966 16:32:49.080542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
18967 16:32:49.080928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
18969 16:32:49.127595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
18971 16:32:49.128015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
18972 16:32:49.173597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
18974 16:32:49.174034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
18975 16:32:49.221304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
18976 16:32:49.221686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
18978 16:32:49.268666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
18980 16:32:49.269096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
18981 16:32:49.315934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
18983 16:32:49.316396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
18984 16:32:49.363673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
18986 16:32:49.364111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
18987 16:32:49.410799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
18988 16:32:49.411203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
18990 16:32:49.457537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
18991 16:32:49.457936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
18993 16:32:49.507688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
18994 16:32:49.508074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
18996 16:32:49.555426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
18997 16:32:49.555841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
18999 16:32:49.624425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19000 16:32:49.624820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19002 16:32:49.672542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19003 16:32:49.672934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19005 16:32:49.719740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19006 16:32:49.720168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19008 16:32:49.765870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19009 16:32:49.766283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19011 16:32:49.812369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19012 16:32:49.812731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19014 16:32:49.859102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19015 16:32:49.859482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19017 16:32:49.905555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19018 16:32:49.905974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19020 16:32:49.951801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19021 16:32:49.952200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19023 16:32:49.998357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19025 16:32:49.998800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19026 16:32:50.044799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19028 16:32:50.045239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19029 16:32:50.100070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19031 16:32:50.100360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19032 16:32:50.152927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19034 16:32:50.153211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19035 16:32:50.202002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19037 16:32:50.202363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19038 16:32:50.248807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19040 16:32:50.249099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19041 16:32:50.295508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19042 16:32:50.295795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19044 16:32:50.341904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19046 16:32:50.342192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19047 16:32:50.388020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19048 16:32:50.388315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19050 16:32:50.436887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19051 16:32:50.437175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19053 16:32:50.483650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19054 16:32:50.483946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19056 16:32:50.529784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19057 16:32:50.530067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19059 16:32:50.575848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19060 16:32:50.576132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19062 16:32:50.622302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19064 16:32:50.622604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19065 16:32:50.668185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19066 16:32:50.668473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19068 16:32:50.713676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19070 16:32:50.713977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19071 16:32:50.759938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19072 16:32:50.760308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19074 16:32:50.806046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19076 16:32:50.806490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19077 16:32:50.852934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19078 16:32:50.853333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19080 16:32:50.900562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19081 16:32:50.900967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19083 16:32:50.947520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19084 16:32:50.947933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19086 16:32:50.993663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19087 16:32:50.994068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19089 16:32:51.040557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19091 16:32:51.040992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19092 16:32:51.086881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19093 16:32:51.087285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19095 16:32:51.134134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19096 16:32:51.134544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19098 16:32:51.180886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19099 16:32:51.181297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19101 16:32:51.229437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19102 16:32:51.229860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19104 16:32:51.276251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19105 16:32:51.276660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19107 16:32:51.323615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19108 16:32:51.324043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19110 16:32:51.370315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19112 16:32:51.370812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19113 16:32:51.417455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19114 16:32:51.417749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19116 16:32:51.463716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19117 16:32:51.464007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19119 16:32:51.509639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19120 16:32:51.510051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19122 16:32:51.556806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19124 16:32:51.557146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19125 16:32:51.603391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19126 16:32:51.603683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19128 16:32:51.650847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19129 16:32:51.651137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19131 16:32:51.696552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19133 16:32:51.696841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19134 16:32:51.742949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19135 16:32:51.743237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19137 16:32:51.788946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19138 16:32:51.789231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19140 16:32:51.835225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19141 16:32:51.835643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19143 16:32:51.881321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19144 16:32:51.881684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19146 16:32:51.928128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19147 16:32:51.928535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19149 16:32:51.984984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19150 16:32:51.985385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19152 16:32:52.032447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19153 16:32:52.032868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19155 16:32:52.079737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19156 16:32:52.080145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19158 16:32:52.126215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19160 16:32:52.126596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19161 16:32:52.173131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19162 16:32:52.173537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19164 16:32:52.219752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19165 16:32:52.220161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19167 16:32:52.265846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19168 16:32:52.266264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19170 16:32:52.312250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19171 16:32:52.312671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19173 16:32:52.359924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19175 16:32:52.360407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19176 16:32:52.407527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19178 16:32:52.407990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19179 16:32:52.455066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19180 16:32:52.455478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19182 16:32:52.501290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19183 16:32:52.501687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19185 16:32:52.547789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19186 16:32:52.548130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19188 16:32:52.593563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19190 16:32:52.593860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19191 16:32:52.640100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19192 16:32:52.640389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19194 16:32:52.688183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19195 16:32:52.688584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19197 16:32:52.736558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19198 16:32:52.736905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19200 16:32:52.785000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19201 16:32:52.785287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19203 16:32:52.831787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19205 16:32:52.832075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19206 16:32:52.877453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19207 16:32:52.877879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19209 16:32:52.924773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19211 16:32:52.925093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19212 16:32:52.971335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19214 16:32:52.971627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19215 16:32:53.017487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19216 16:32:53.017777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19218 16:32:53.063737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19219 16:32:53.064032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19221 16:32:53.109511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19222 16:32:53.109772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19224 16:32:53.156266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19225 16:32:53.156564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19227 16:32:53.203033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19228 16:32:53.203291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19230 16:32:53.248819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19231 16:32:53.249110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19233 16:32:53.295682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19234 16:32:53.295962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19236 16:32:53.341431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19237 16:32:53.341679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19239 16:32:53.387786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19240 16:32:53.388075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19242 16:32:53.434310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19244 16:32:53.434773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19245 16:32:53.481000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19246 16:32:53.481402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19248 16:32:53.528471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19249 16:32:53.528896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19251 16:32:53.575079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19252 16:32:53.575484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19254 16:32:53.621340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19255 16:32:53.621761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19257 16:32:53.667774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19258 16:32:53.668187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19260 16:32:53.712682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19261 16:32:53.713019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19263 16:32:53.759310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19264 16:32:53.759598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19266 16:32:53.805205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19267 16:32:53.805501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19269 16:32:53.851507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19270 16:32:53.851782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19272 16:32:53.900204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19274 16:32:53.900502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19275 16:32:53.948956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19276 16:32:53.949245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19278 16:32:53.995607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19279 16:32:53.995869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19281 16:32:54.041687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19282 16:32:54.042112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19284 16:32:54.088703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19285 16:32:54.089107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19287 16:32:54.135668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19288 16:32:54.136079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19290 16:32:54.182967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19291 16:32:54.183341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19293 16:32:54.229278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19294 16:32:54.229684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19296 16:32:54.275691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19298 16:32:54.276128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19299 16:32:54.321954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19300 16:32:54.322366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19302 16:32:54.369008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19303 16:32:54.369422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19305 16:32:54.415775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19306 16:32:54.416179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19308 16:32:54.461807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19310 16:32:54.462166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19311 16:32:54.508924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19313 16:32:54.509357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19314 16:32:54.555899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19315 16:32:54.556304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19317 16:32:54.602248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19319 16:32:54.602682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19320 16:32:54.652421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19321 16:32:54.652762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19323 16:32:54.699416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19324 16:32:54.699706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19326 16:32:54.766997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19328 16:32:54.767299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19329 16:32:54.812318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19330 16:32:54.812604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19332 16:32:54.859080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19334 16:32:54.859310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19335 16:32:54.904827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19336 16:32:54.905115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19338 16:32:54.951368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19339 16:32:54.951648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19341 16:32:54.997164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19342 16:32:54.997453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19344 16:32:55.044721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19346 16:32:55.045017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19347 16:32:55.097317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19348 16:32:55.097664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19350 16:32:55.153598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19352 16:32:55.154013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19353 16:32:55.204909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19355 16:32:55.205230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19356 16:32:55.253568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19357 16:32:55.253841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19359 16:32:55.302171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19361 16:32:55.302594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19362 16:32:55.349103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19363 16:32:55.349382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19365 16:32:55.395765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19366 16:32:55.396059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19368 16:32:55.442705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19369 16:32:55.442999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19371 16:32:55.488925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19372 16:32:55.489218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19374 16:32:55.535632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19375 16:32:55.535919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19377 16:32:55.581601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19378 16:32:55.581895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19380 16:32:55.627697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19381 16:32:55.627985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19383 16:32:55.677006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19384 16:32:55.677294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19386 16:32:55.724644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19387 16:32:55.724936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19389 16:32:55.770876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19390 16:32:55.771167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19392 16:32:55.816095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19393 16:32:55.816390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19395 16:32:55.862561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19396 16:32:55.862862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19398 16:32:55.908159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19399 16:32:55.908453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19401 16:32:55.954678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19403 16:32:55.954972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19404 16:32:55.999912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19406 16:32:56.000208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19407 16:32:56.045447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19408 16:32:56.045747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19410 16:32:56.092036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19412 16:32:56.092278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19413 16:32:56.137845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19414 16:32:56.138136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19416 16:32:56.184569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19418 16:32:56.185006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19419 16:32:56.230891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19421 16:32:56.231276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19422 16:32:56.276942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19423 16:32:56.277316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19425 16:32:56.323714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19427 16:32:56.324150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19428 16:32:56.369306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19429 16:32:56.369630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19431 16:32:56.415703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19432 16:32:56.416026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19434 16:32:56.469783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19435 16:32:56.470091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19437 16:32:56.511512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19439 16:32:56.511942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19440 16:32:56.559468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19441 16:32:56.559848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19443 16:32:56.605455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19444 16:32:56.605822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19446 16:32:56.652804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19448 16:32:56.653186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19449 16:32:56.699577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19450 16:32:56.699939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19452 16:32:56.746765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19453 16:32:56.747129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19455 16:32:56.796050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19457 16:32:56.797848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19458 16:32:56.845043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19460 16:32:56.845482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19461 16:32:56.893849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19463 16:32:56.894146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19464 16:32:56.943333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19465 16:32:56.943624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19467 16:32:56.991657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19468 16:32:56.991947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19470 16:32:57.040036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19471 16:32:57.040340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19473 16:32:57.087605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19474 16:32:57.087937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19476 16:32:57.135376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19477 16:32:57.135720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19479 16:32:57.182229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19481 16:32:57.182560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19482 16:32:57.231886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19483 16:32:57.232190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19485 16:32:57.279815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19486 16:32:57.280200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19488 16:32:57.327013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19489 16:32:57.327300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19491 16:32:57.375471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19492 16:32:57.375882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19494 16:32:57.424138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19495 16:32:57.424484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19497 16:32:57.472083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19498 16:32:57.472413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19500 16:32:57.518272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19502 16:32:57.518586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19503 16:32:57.567182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19504 16:32:57.567503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19506 16:32:57.614336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19508 16:32:57.614708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19509 16:32:57.662905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19510 16:32:57.663294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19512 16:32:57.710168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19514 16:32:57.710549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19515 16:32:57.757009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19517 16:32:57.757503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19518 16:32:57.805106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19519 16:32:57.805494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19521 16:32:57.851748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19522 16:32:57.852162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19524 16:32:57.898091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19525 16:32:57.898506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19527 16:32:57.947361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19529 16:32:57.947809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19530 16:32:57.996903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19531 16:32:57.997324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19533 16:32:58.044401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19534 16:32:58.044823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19536 16:32:58.091504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19538 16:32:58.091944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19539 16:32:58.138946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19540 16:32:58.139353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19542 16:32:58.185590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19543 16:32:58.186013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19545 16:32:58.233140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19546 16:32:58.233546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19548 16:32:58.280028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19550 16:32:58.280381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19551 16:32:58.327658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19552 16:32:58.328023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19554 16:32:58.374022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19555 16:32:58.374423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19557 16:32:58.421653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19558 16:32:58.422070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19560 16:32:58.469559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19561 16:32:58.470000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19563 16:32:58.517717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19564 16:32:58.518142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19566 16:32:58.565237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19567 16:32:58.565644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19569 16:32:58.612765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19571 16:32:58.613205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19572 16:32:58.660025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19574 16:32:58.660464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19575 16:32:58.707718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19576 16:32:58.708127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19578 16:32:58.755938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19579 16:32:58.756316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19581 16:32:58.803891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19582 16:32:58.804293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19584 16:32:58.851023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19585 16:32:58.851399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19587 16:32:58.897501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19588 16:32:58.897912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19590 16:32:58.947150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19591 16:32:58.947565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19593 16:32:58.994304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19595 16:32:58.994759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19596 16:32:59.042064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19598 16:32:59.042495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19599 16:32:59.089345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19601 16:32:59.089815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19602 16:32:59.136948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19603 16:32:59.137323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19605 16:32:59.184119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19606 16:32:59.184529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19608 16:32:59.231774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19609 16:32:59.232193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19611 16:32:59.279449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19612 16:32:59.279855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19614 16:32:59.325717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19615 16:32:59.326141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19617 16:32:59.373382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19618 16:32:59.373794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19620 16:32:59.420929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19622 16:32:59.421369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19623 16:32:59.469714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19625 16:32:59.470155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19626 16:32:59.517409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19627 16:32:59.517837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19629 16:32:59.564670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19630 16:32:59.565093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19632 16:32:59.611123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19634 16:32:59.611576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19635 16:32:59.659537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19636 16:32:59.659957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19638 16:32:59.707564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19640 16:32:59.708023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19641 16:32:59.753855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19642 16:32:59.754260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19644 16:32:59.799920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19646 16:32:59.800344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19647 16:32:59.867586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19648 16:32:59.868009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19650 16:32:59.914376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19652 16:32:59.914956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19653 16:32:59.961270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19654 16:32:59.961684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19656 16:33:00.008383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19657 16:33:00.008811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19659 16:33:00.055309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19660 16:33:00.060798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19662 16:33:00.102921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19663 16:33:00.103292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19665 16:33:00.149517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19667 16:33:00.149958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19668 16:33:00.195319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19669 16:33:00.195723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19671 16:33:00.241680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19672 16:33:00.242087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19674 16:33:00.289892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19675 16:33:00.290321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19677 16:33:00.337200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19678 16:33:00.337605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19680 16:33:00.384435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19681 16:33:00.384850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19683 16:33:00.431533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19684 16:33:00.431957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19686 16:33:00.478084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19688 16:33:00.478455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19689 16:33:00.525567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19690 16:33:00.525992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19692 16:33:00.572474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19694 16:33:00.572820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19695 16:33:00.621947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19696 16:33:00.622386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19698 16:33:00.671167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19699 16:33:00.671599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19701 16:33:00.718501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19703 16:33:00.718949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19704 16:33:00.765718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19705 16:33:00.766133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19707 16:33:00.813380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19708 16:33:00.813753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19710 16:33:00.859974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19711 16:33:00.860402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19713 16:33:00.907122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19714 16:33:00.907536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19716 16:33:00.952820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19718 16:33:00.953305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19719 16:33:00.999607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
19721 16:33:00.999971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
19722 16:33:01.046451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
19724 16:33:01.046911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
19725 16:33:01.093279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
19726 16:33:01.093686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
19728 16:33:01.140488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
19729 16:33:01.140930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
19731 16:33:01.187605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
19733 16:33:01.188033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
19734 16:33:01.234176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
19736 16:33:01.234674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
19737 16:33:01.281609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
19738 16:33:01.282030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
19740 16:33:01.328195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
19741 16:33:01.328604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
19743 16:33:01.375920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
19745 16:33:01.376341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
19746 16:33:01.423315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
19747 16:33:01.423715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
19749 16:33:01.470908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
19750 16:33:01.471319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
19752 16:33:01.519188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
19753 16:33:01.519594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
19755 16:33:01.566435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
19757 16:33:01.566897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
19758 16:33:01.613460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
19759 16:33:01.613754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
19761 16:33:01.661109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
19762 16:33:01.661399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
19764 16:33:01.708102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
19765 16:33:01.708391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
19767 16:33:01.755532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
19768 16:33:01.755821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
19770 16:33:01.803476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
19772 16:33:01.803773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
19773 16:33:01.851115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
19774 16:33:01.851409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
19776 16:33:01.897385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
19777 16:33:01.897676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
19779 16:33:01.944692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
19780 16:33:01.945093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
19782 16:33:01.992578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
19784 16:33:01.993016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
19785 16:33:02.040369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
19786 16:33:02.040778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
19788 16:33:02.087606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
19789 16:33:02.088010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
19791 16:33:02.135167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
19792 16:33:02.135540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
19794 16:33:02.182033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
19796 16:33:02.182475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
19797 16:33:02.229237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
19798 16:33:02.229655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
19800 16:33:02.277473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
19801 16:33:02.277890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
19803 16:33:02.324800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
19805 16:33:02.325231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
19806 16:33:02.372117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
19808 16:33:02.372546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
19809 16:33:02.419715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
19810 16:33:02.420116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
19812 16:33:02.466890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
19813 16:33:02.467296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
19815 16:33:02.513189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
19816 16:33:02.513592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
19818 16:33:02.559959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
19819 16:33:02.560358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
19821 16:33:02.607165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
19822 16:33:02.607568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
19824 16:33:02.655081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
19825 16:33:02.655487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
19827 16:33:02.701479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
19828 16:33:02.701897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
19830 16:33:02.748665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
19831 16:33:02.749068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
19833 16:33:02.796694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
19834 16:33:02.797095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
19836 16:33:02.843722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
19838 16:33:02.844147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
19839 16:33:02.891692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
19840 16:33:02.892102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
19842 16:33:02.939948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
19844 16:33:02.940410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
19845 16:33:02.988437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
19846 16:33:02.988813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
19848 16:33:03.035435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
19849 16:33:03.035808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
19851 16:33:03.081582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
19853 16:33:03.082029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
19854 16:33:03.128167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
19856 16:33:03.128601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
19857 16:33:03.174379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
19859 16:33:03.174819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
19860 16:33:03.220947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
19861 16:33:03.221361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
19863 16:33:03.267665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
19864 16:33:03.268090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
19866 16:33:03.315862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
19867 16:33:03.316276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
19869 16:33:03.361896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
19870 16:33:03.362315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
19872 16:33:03.408718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
19874 16:33:03.409158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
19875 16:33:03.455713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
19877 16:33:03.456145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
19878 16:33:03.501776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
19880 16:33:03.502206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
19881 16:33:03.548480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
19883 16:33:03.548916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
19884 16:33:03.594208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
19885 16:33:03.594624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
19887 16:33:03.641279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
19889 16:33:03.641711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
19890 16:33:03.688035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
19892 16:33:03.688468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
19893 16:33:03.735034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
19894 16:33:03.735442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
19896 16:33:03.781852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
19898 16:33:03.782284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
19899 16:33:03.828685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
19900 16:33:03.829092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
19902 16:33:03.875870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
19903 16:33:03.876274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
19905 16:33:03.923609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
19906 16:33:03.924012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
19908 16:33:03.971570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
19910 16:33:03.971939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
19911 16:33:04.017818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
19912 16:33:04.018236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
19914 16:33:04.065194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
19915 16:33:04.065602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
19917 16:33:04.111809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
19918 16:33:04.112229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
19920 16:33:04.160487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
19921 16:33:04.160898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
19923 16:33:04.207506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
19924 16:33:04.207914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
19926 16:33:04.254104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
19928 16:33:04.254537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
19929 16:33:04.301042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
19930 16:33:04.301458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
19932 16:33:04.349031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
19933 16:33:04.349470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
19935 16:33:04.395990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
19936 16:33:04.396418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
19938 16:33:04.447682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
19940 16:33:04.448127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
19941 16:33:04.499214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
19942 16:33:04.499625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
19944 16:33:04.547723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
19945 16:33:04.548132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
19947 16:33:04.595620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
19949 16:33:04.596043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
19950 16:33:04.643681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
19951 16:33:04.644098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
19953 16:33:04.690927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
19954 16:33:04.691349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
19956 16:33:04.737702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
19958 16:33:04.738184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
19959 16:33:04.785165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
19960 16:33:04.785594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
19962 16:33:04.833710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
19964 16:33:04.834195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
19965 16:33:04.881270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
19966 16:33:04.881683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
19968 16:33:04.928065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
19970 16:33:04.928498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
19971 16:33:04.996961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
19972 16:33:04.997374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
19974 16:33:05.044797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
19975 16:33:05.045204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
19977 16:33:05.093956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
19978 16:33:05.094368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
19980 16:33:05.145291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
19981 16:33:05.145690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
19983 16:33:05.196796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
19984 16:33:05.197204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
19986 16:33:05.247843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
19987 16:33:05.248274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
19989 16:33:05.295647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
19990 16:33:05.296056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
19992 16:33:05.343380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
19993 16:33:05.343778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
19995 16:33:05.391420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
19997 16:33:05.391785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
19998 16:33:05.439029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
19999 16:33:05.439369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20001 16:33:05.487036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20002 16:33:05.487450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20004 16:33:05.534082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20005 16:33:05.534481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20007 16:33:05.584051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20008 16:33:05.584468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20010 16:33:05.631804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20011 16:33:05.632215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20013 16:33:05.679525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20015 16:33:05.679966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20016 16:33:05.727930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20018 16:33:05.728367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20019 16:33:05.775536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20020 16:33:05.775971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20022 16:33:05.824049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20023 16:33:05.824479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20025 16:33:05.872781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20026 16:33:05.873201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20028 16:33:05.920024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20029 16:33:05.920382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20031 16:33:05.967785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20032 16:33:05.968218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20034 16:33:06.015852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20035 16:33:06.016279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20037 16:33:06.063621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20038 16:33:06.064033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20040 16:33:06.112214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20041 16:33:06.112630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20043 16:33:06.159953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20044 16:33:06.160366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20046 16:33:06.208321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20048 16:33:06.208776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20049 16:33:06.256079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20050 16:33:06.256490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20052 16:33:06.303941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20053 16:33:06.304353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20055 16:33:06.355309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20056 16:33:06.355734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20058 16:33:06.403461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20060 16:33:06.403843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20061 16:33:06.452518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20062 16:33:06.452917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20064 16:33:06.501553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20065 16:33:06.502011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20067 16:33:06.552753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20069 16:33:06.553193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20070 16:33:06.600697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20071 16:33:06.601113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20073 16:33:06.649040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20074 16:33:06.649457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20076 16:33:06.697623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20077 16:33:06.698045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20079 16:33:06.748482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20080 16:33:06.748912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20082 16:33:06.796109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20083 16:33:06.796541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20085 16:33:06.844212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20087 16:33:06.845009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20088 16:33:06.893993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20089 16:33:06.894419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20091 16:33:06.945251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20092 16:33:06.945660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20094 16:33:06.992527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20095 16:33:06.992940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20097 16:33:07.040427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20098 16:33:07.040828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20100 16:33:07.087072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20101 16:33:07.087496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20103 16:33:07.134445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20105 16:33:07.134947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20106 16:33:07.182003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20108 16:33:07.182443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20109 16:33:07.230151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20111 16:33:07.230616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20112 16:33:07.279871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20113 16:33:07.280284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20115 16:33:07.327734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20116 16:33:07.328139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20118 16:33:07.376007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20119 16:33:07.376411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20121 16:33:07.424024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20122 16:33:07.424427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20124 16:33:07.471246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20125 16:33:07.471664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20127 16:33:07.518502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20129 16:33:07.519129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20130 16:33:07.565896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20132 16:33:07.566327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20133 16:33:07.613483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20135 16:33:07.613921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20136 16:33:07.662011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20138 16:33:07.662484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20139 16:33:07.709554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20140 16:33:07.709977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20142 16:33:07.757589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20143 16:33:07.758016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20145 16:33:07.805599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20146 16:33:07.806027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20148 16:33:07.855530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20150 16:33:07.855981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20151 16:33:07.903527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20153 16:33:07.903977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20154 16:33:07.951971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20155 16:33:07.952384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20157 16:33:08.001003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20158 16:33:08.001421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20160 16:33:08.048388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20162 16:33:08.048837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20163 16:33:08.096205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20164 16:33:08.096639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20166 16:33:08.143690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20167 16:33:08.144109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20169 16:33:08.191868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20171 16:33:08.192301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20172 16:33:08.239462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20173 16:33:08.239861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20175 16:33:08.286804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20176 16:33:08.287189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20178 16:33:08.334067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20179 16:33:08.334495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20181 16:33:08.383811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20182 16:33:08.384227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20184 16:33:08.430831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20185 16:33:08.431260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20187 16:33:08.477713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20189 16:33:08.478180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20190 16:33:08.525679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20191 16:33:08.526092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20193 16:33:08.573582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20194 16:33:08.573996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20196 16:33:08.620979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20197 16:33:08.621390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20199 16:33:08.668598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20200 16:33:08.668999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20202 16:33:08.716718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20203 16:33:08.717136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20205 16:33:08.765770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20206 16:33:08.766187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20208 16:33:08.819187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20210 16:33:08.819640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20211 16:33:08.869803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20212 16:33:08.870231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20214 16:33:08.919467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20216 16:33:08.919915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20217 16:33:08.966002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20218 16:33:08.966436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20220 16:33:09.018246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20222 16:33:09.018727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20223 16:33:09.066799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20224 16:33:09.067208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20226 16:33:09.114200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20228 16:33:09.114687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20229 16:33:09.161644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20230 16:33:09.162073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20232 16:33:09.210436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20234 16:33:09.210887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20235 16:33:09.258403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20237 16:33:09.258811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20238 16:33:09.305472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20239 16:33:09.305888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20241 16:33:09.353124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20242 16:33:09.353536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20244 16:33:09.400535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20245 16:33:09.400947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20247 16:33:09.448134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20248 16:33:09.448544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20250 16:33:09.496770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20251 16:33:09.497183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20253 16:33:09.544204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20255 16:33:09.544636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20256 16:33:09.591156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20257 16:33:09.591586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20259 16:33:09.637908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20260 16:33:09.638329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20262 16:33:09.685926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20263 16:33:09.686348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20265 16:33:09.733393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20267 16:33:09.733847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20268 16:33:09.780579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20269 16:33:09.780990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20271 16:33:09.827844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20272 16:33:09.828247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20274 16:33:09.875416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20275 16:33:09.875831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20277 16:33:09.922288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20279 16:33:09.922708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20280 16:33:09.969533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20282 16:33:09.969968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20283 16:33:10.016676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20285 16:33:10.017104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20286 16:33:10.064041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20287 16:33:10.064462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20289 16:33:10.135616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20290 16:33:10.136028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20292 16:33:10.190939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20294 16:33:10.191382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20295 16:33:10.248561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20297 16:33:10.249043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20298 16:33:10.300012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20299 16:33:10.300423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20301 16:33:10.346455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20303 16:33:10.346901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20304 16:33:10.396119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20305 16:33:10.396529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20307 16:33:10.444188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20309 16:33:10.444685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20310 16:33:10.491599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20311 16:33:10.492022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20313 16:33:10.538388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20315 16:33:10.538842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20316 16:33:10.585088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20317 16:33:10.585506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20319 16:33:10.632100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20320 16:33:10.632531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20322 16:33:10.679475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20323 16:33:10.679892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20325 16:33:10.725983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20326 16:33:10.726395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20328 16:33:10.773313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20330 16:33:10.773788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20331 16:33:10.820465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20332 16:33:10.820882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20334 16:33:10.867675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20336 16:33:10.868136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20337 16:33:10.915022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20338 16:33:10.915428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20340 16:33:10.960906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20341 16:33:10.961323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20343 16:33:11.008111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20344 16:33:11.008527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20346 16:33:11.055784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20348 16:33:11.056224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20349 16:33:11.102420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20351 16:33:11.102852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20352 16:33:11.148969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20353 16:33:11.149401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20355 16:33:11.195942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20356 16:33:11.196357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20358 16:33:11.242313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20360 16:33:11.242891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20361 16:33:11.289473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20362 16:33:11.289880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20364 16:33:11.336244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20365 16:33:11.336652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20367 16:33:11.383462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20368 16:33:11.383877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20370 16:33:11.429882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20371 16:33:11.430299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20373 16:33:11.476680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20374 16:33:11.477090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20376 16:33:11.524001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20377 16:33:11.524411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20379 16:33:11.570004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20380 16:33:11.570412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20382 16:33:11.617015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20383 16:33:11.617423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20385 16:33:11.663878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20386 16:33:11.664284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20388 16:33:11.710274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20390 16:33:11.710926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20391 16:33:11.756823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20392 16:33:11.757236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20394 16:33:11.803955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20395 16:33:11.804364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20397 16:33:11.850749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20398 16:33:11.851157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20400 16:33:11.897923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20402 16:33:11.898350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20403 16:33:11.945122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20405 16:33:11.945613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20406 16:33:11.991982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20408 16:33:11.992424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20409 16:33:12.037846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20410 16:33:12.038135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20412 16:33:12.083730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20413 16:33:12.084000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20415 16:33:12.129826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20416 16:33:12.130093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20418 16:33:12.176059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20420 16:33:12.176292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20421 16:33:12.223944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20422 16:33:12.224378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20424 16:33:12.271176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20425 16:33:12.271595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20427 16:33:12.318033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20428 16:33:12.318441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20430 16:33:12.364554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20432 16:33:12.364978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20433 16:33:12.411643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20434 16:33:12.412048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20436 16:33:12.458150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20437 16:33:12.458563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20439 16:33:12.505622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20440 16:33:12.506024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20442 16:33:12.553934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20444 16:33:12.554343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20445 16:33:12.600424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20447 16:33:12.600722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20448 16:33:12.645908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20449 16:33:12.646198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20451 16:33:12.692303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20453 16:33:12.692600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20454 16:33:12.738693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20455 16:33:12.738984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20457 16:33:12.786272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20459 16:33:12.786533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20460 16:33:12.831911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20461 16:33:12.832199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20463 16:33:12.877770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20465 16:33:12.878069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20466 16:33:12.925249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20467 16:33:12.925681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20469 16:33:12.973267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20470 16:33:12.973589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20472 16:33:13.019569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20473 16:33:13.019859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20475 16:33:13.065526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20476 16:33:13.065815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20478 16:33:13.111783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20479 16:33:13.112074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20481 16:33:13.157247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20482 16:33:13.157510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20484 16:33:13.203684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20485 16:33:13.203950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20487 16:33:13.250255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20489 16:33:13.250595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20490 16:33:13.297253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20491 16:33:13.297642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20493 16:33:13.343868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20494 16:33:13.344221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20496 16:33:13.391169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20497 16:33:13.391456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20499 16:33:13.437492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20501 16:33:13.437787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20502 16:33:13.484314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20504 16:33:13.484600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20505 16:33:13.530739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20507 16:33:13.531032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20508 16:33:13.576298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20509 16:33:13.576579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20511 16:33:13.622245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20513 16:33:13.622617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20514 16:33:13.668616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20515 16:33:13.668909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20517 16:33:13.715655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20519 16:33:13.715949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20520 16:33:13.762200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20522 16:33:13.762512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20523 16:33:13.810106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20525 16:33:13.810728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20526 16:33:13.858797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20528 16:33:13.859110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20529 16:33:13.905876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20530 16:33:13.906245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20532 16:33:13.952361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20533 16:33:13.952654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20535 16:33:13.999984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20536 16:33:14.000253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20538 16:33:14.048763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20540 16:33:14.049092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20541 16:33:14.096597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20542 16:33:14.096889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20544 16:33:14.144072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20545 16:33:14.144486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20547 16:33:14.190184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20549 16:33:14.190537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20550 16:33:14.237414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20551 16:33:14.237676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20553 16:33:14.285143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20555 16:33:14.285434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20556 16:33:14.332029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20558 16:33:14.332328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20559 16:33:14.379458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20560 16:33:14.379744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20562 16:33:14.426354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20564 16:33:14.426744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20565 16:33:14.472503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20567 16:33:14.472796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20568 16:33:14.519525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20569 16:33:14.519819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20571 16:33:14.566268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20573 16:33:14.566556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20574 16:33:14.613173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20575 16:33:14.613460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20577 16:33:14.660519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20579 16:33:14.660815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20580 16:33:14.707709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20582 16:33:14.708004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20583 16:33:14.754852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20585 16:33:14.755144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20586 16:33:14.802410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20588 16:33:14.802876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20589 16:33:14.849197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20591 16:33:14.849487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20592 16:33:14.896790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20593 16:33:14.897083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20595 16:33:14.943815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20596 16:33:14.944113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20598 16:33:14.990318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20600 16:33:14.990654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20601 16:33:15.037076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20602 16:33:15.037364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20604 16:33:15.084173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20606 16:33:15.084497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20607 16:33:15.131352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20609 16:33:15.131672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20610 16:33:15.177245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20611 16:33:15.177539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20613 16:33:15.246360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20615 16:33:15.246787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20616 16:33:15.295774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20617 16:33:15.296175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20619 16:33:15.343470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20620 16:33:15.343771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20622 16:33:15.392131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20624 16:33:15.392459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20625 16:33:15.439775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20627 16:33:15.440075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20628 16:33:15.486278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20630 16:33:15.486616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20631 16:33:15.533679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20632 16:33:15.533968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20634 16:33:15.582446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20636 16:33:15.582921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20637 16:33:15.629711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20638 16:33:15.630114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20640 16:33:15.675994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20641 16:33:15.676402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20643 16:33:15.723442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20644 16:33:15.723852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20646 16:33:15.770919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20647 16:33:15.771336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20649 16:33:15.819526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20650 16:33:15.819959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20652 16:33:15.867115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20653 16:33:15.867539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20655 16:33:15.914163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20657 16:33:15.914641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20658 16:33:15.961678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20660 16:33:15.962134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20661 16:33:16.009245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20662 16:33:16.009676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20664 16:33:16.056452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20665 16:33:16.056855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20667 16:33:16.104322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20668 16:33:16.104733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20670 16:33:16.152600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20671 16:33:16.152999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20673 16:33:16.200445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20674 16:33:16.200873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20676 16:33:16.248504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20677 16:33:16.248900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20679 16:33:16.295797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20680 16:33:16.296210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20682 16:33:16.343657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20683 16:33:16.344071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20685 16:33:16.392651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20686 16:33:16.393033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20688 16:33:16.441182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20690 16:33:16.441595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20691 16:33:16.488421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20692 16:33:16.488846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20694 16:33:16.537692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20695 16:33:16.538127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20697 16:33:16.585714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20699 16:33:16.586148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20700 16:33:16.633303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20701 16:33:16.633685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20703 16:33:16.681249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20704 16:33:16.681665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20706 16:33:16.729360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20708 16:33:16.729815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20709 16:33:16.777377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20710 16:33:16.777794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20712 16:33:16.826008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20713 16:33:16.826435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20715 16:33:16.873963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20716 16:33:16.874385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20718 16:33:16.922277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
20720 16:33:16.922733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20721 16:33:16.969861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
20723 16:33:16.970336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
20724 16:33:17.016454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
20725 16:33:17.016878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
20727 16:33:17.064045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
20728 16:33:17.064457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
20730 16:33:17.112556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
20732 16:33:17.113047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
20733 16:33:17.160356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
20735 16:33:17.160784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
20736 16:33:17.208771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
20737 16:33:17.209166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
20739 16:33:17.256131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
20741 16:33:17.256579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
20742 16:33:17.303822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
20743 16:33:17.304227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
20745 16:33:17.352800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
20746 16:33:17.353220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
20748 16:33:17.400306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
20749 16:33:17.400715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
20751 16:33:17.448175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
20753 16:33:17.448609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
20754 16:33:17.496142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
20756 16:33:17.496583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
20757 16:33:17.543815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
20758 16:33:17.544231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
20760 16:33:17.592095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
20761 16:33:17.592518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
20763 16:33:17.639962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
20764 16:33:17.640375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
20766 16:33:17.687908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
20768 16:33:17.688343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
20769 16:33:17.735687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
20770 16:33:17.736099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
20772 16:33:17.783566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
20773 16:33:17.783924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
20775 16:33:17.830788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
20776 16:33:17.831190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
20778 16:33:17.879361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
20779 16:33:17.879777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
20781 16:33:17.926170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
20783 16:33:17.926771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
20784 16:33:17.975178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
20786 16:33:17.975623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
20787 16:33:18.022806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
20788 16:33:18.023208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
20790 16:33:18.070342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
20792 16:33:18.070773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
20793 16:33:18.116698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
20794 16:33:18.117099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
20796 16:33:18.163985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
20797 16:33:18.164414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
20799 16:33:18.211895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
20800 16:33:18.212300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
20802 16:33:18.259910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
20804 16:33:18.260336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
20805 16:33:18.307650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
20806 16:33:18.308070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
20808 16:33:18.355947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
20809 16:33:18.356376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
20811 16:33:18.403711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
20812 16:33:18.404115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
20814 16:33:18.451046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
20815 16:33:18.451452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
20817 16:33:18.499380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
20818 16:33:18.499790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
20820 16:33:18.547211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
20821 16:33:18.547616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
20823 16:33:18.601109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
20824 16:33:18.601518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
20826 16:33:18.649714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
20827 16:33:18.650138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
20829 16:33:18.697965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
20830 16:33:18.698392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
20832 16:33:18.745709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
20833 16:33:18.746126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
20835 16:33:18.793711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
20837 16:33:18.794194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
20838 16:33:18.841262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
20839 16:33:18.841643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
20841 16:33:18.889880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
20842 16:33:18.890297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
20844 16:33:18.937269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
20845 16:33:18.937686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
20847 16:33:18.984962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
20848 16:33:18.985404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
20850 16:33:19.032760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
20851 16:33:19.033150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
20853 16:33:19.080677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
20854 16:33:19.081051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
20856 16:33:19.128010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
20857 16:33:19.128418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
20859 16:33:19.175520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
20860 16:33:19.175943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
20862 16:33:19.222299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
20864 16:33:19.222760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
20865 16:33:19.270246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
20867 16:33:19.270742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
20868 16:33:19.317710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
20870 16:33:19.318143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
20871 16:33:19.365157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
20872 16:33:19.365567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
20874 16:33:19.413119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
20875 16:33:19.413548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
20877 16:33:19.461713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
20878 16:33:19.462153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
20880 16:33:19.510304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
20882 16:33:19.510765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
20883 16:33:19.557582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
20884 16:33:19.557998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
20886 16:33:19.605235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
20887 16:33:19.605634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
20889 16:33:19.652671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
20891 16:33:19.653103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
20892 16:33:19.699920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
20893 16:33:19.700344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
20895 16:33:19.747855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
20897 16:33:19.748325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
20898 16:33:19.796026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
20900 16:33:19.796492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
20901 16:33:19.841714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
20903 16:33:19.842194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
20904 16:33:19.890765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
20905 16:33:19.891166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
20907 16:33:19.938828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
20908 16:33:19.939233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
20910 16:33:19.985157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
20912 16:33:19.985605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
20913 16:33:20.033040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
20914 16:33:20.033451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
20916 16:33:20.080036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
20917 16:33:20.080450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
20919 16:33:20.126019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
20920 16:33:20.126441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
20922 16:33:20.175427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
20924 16:33:20.175861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
20925 16:33:20.222929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
20926 16:33:20.223336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
20928 16:33:20.275499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
20929 16:33:20.275936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
20931 16:33:20.353624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
20932 16:33:20.354034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
20934 16:33:20.410276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
20936 16:33:20.410635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
20937 16:33:20.460550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
20938 16:33:20.460978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
20940 16:33:20.508085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
20941 16:33:20.508495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
20943 16:33:20.556066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
20944 16:33:20.556480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
20946 16:33:20.603655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
20947 16:33:20.604041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
20949 16:33:20.651286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
20950 16:33:20.651694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
20952 16:33:20.698285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
20954 16:33:20.698795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
20955 16:33:20.748669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
20957 16:33:20.749111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
20958 16:33:20.796849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
20959 16:33:20.797265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
20961 16:33:20.844740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
20962 16:33:20.845153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
20964 16:33:20.892535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
20966 16:33:20.892995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
20967 16:33:20.940262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
20968 16:33:20.940692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
20970 16:33:20.988224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
20971 16:33:20.988639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
20973 16:33:21.035731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
20975 16:33:21.036207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
20976 16:33:21.084831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
20977 16:33:21.085257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
20979 16:33:21.132422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
20980 16:33:21.132809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
20982 16:33:21.180616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
20984 16:33:21.181082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
20985 16:33:21.228383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
20987 16:33:21.228789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
20988 16:33:21.275932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
20989 16:33:21.276352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
20991 16:33:21.324123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
20993 16:33:21.324578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
20994 16:33:21.372045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
20996 16:33:21.372443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
20997 16:33:21.419785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
20998 16:33:21.420192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21000 16:33:21.469077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21002 16:33:21.469519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21003 16:33:21.520011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21005 16:33:21.520456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21006 16:33:21.568588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21007 16:33:21.569004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21009 16:33:21.617596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21010 16:33:21.618042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21012 16:33:21.667823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21013 16:33:21.668266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21015 16:33:21.716143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21016 16:33:21.716519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21018 16:33:21.766543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21020 16:33:21.767006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21021 16:33:21.815148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21022 16:33:21.815564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21024 16:33:21.862458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21026 16:33:21.862944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21027 16:33:21.910004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21028 16:33:21.910411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21030 16:33:21.956419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21032 16:33:21.956861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21033 16:33:22.004874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21034 16:33:22.005242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21036 16:33:22.052599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21037 16:33:22.053006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21039 16:33:22.100079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21040 16:33:22.100456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21042 16:33:22.147425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21044 16:33:22.147828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21045 16:33:22.194894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21046 16:33:22.195281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21048 16:33:22.241065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21049 16:33:22.241486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21051 16:33:22.289262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21053 16:33:22.289714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21054 16:33:22.335665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21055 16:33:22.336079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21057 16:33:22.383616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21058 16:33:22.384028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21060 16:33:22.431247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21061 16:33:22.431659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21063 16:33:22.479130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21064 16:33:22.479555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21066 16:33:22.526319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21068 16:33:22.526739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21069 16:33:22.573633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21070 16:33:22.574040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21072 16:33:22.621562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21073 16:33:22.621973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21075 16:33:22.668830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21076 16:33:22.669236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21078 16:33:22.715991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21079 16:33:22.716416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21081 16:33:22.763896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21082 16:33:22.764302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21084 16:33:22.811482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21085 16:33:22.811886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21087 16:33:22.859595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21089 16:33:22.860020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21090 16:33:22.906932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21091 16:33:22.907346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21093 16:33:22.953919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21095 16:33:22.954367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21096 16:33:23.003590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21098 16:33:23.004099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21099 16:33:23.052835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21100 16:33:23.053272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21102 16:33:23.101665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21103 16:33:23.102100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21105 16:33:23.151797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21106 16:33:23.152217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21108 16:33:23.199243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21110 16:33:23.199679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21111 16:33:23.246753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21113 16:33:23.247212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21114 16:33:23.297156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21116 16:33:23.297597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21117 16:33:23.344608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21118 16:33:23.345025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21120 16:33:23.392046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21121 16:33:23.392422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21123 16:33:23.439508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21125 16:33:23.439909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21126 16:33:23.487045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21127 16:33:23.487434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21129 16:33:23.535844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21130 16:33:23.536248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21132 16:33:23.582052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21134 16:33:23.582489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21135 16:33:23.628953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21136 16:33:23.629328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21138 16:33:23.677421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21139 16:33:23.677837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21141 16:33:23.725608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21142 16:33:23.726051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21144 16:33:23.773315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21145 16:33:23.773688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21147 16:33:23.821190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21148 16:33:23.821595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21150 16:33:23.868589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21152 16:33:23.868940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21153 16:33:23.915950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21155 16:33:23.916247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21156 16:33:23.961499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21158 16:33:23.961808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21159 16:33:24.008979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21160 16:33:24.009269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21162 16:33:24.055428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21163 16:33:24.055715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21165 16:33:24.101480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21166 16:33:24.101771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21168 16:33:24.148727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21169 16:33:24.149017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21171 16:33:24.195662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21172 16:33:24.195952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21174 16:33:24.242231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21176 16:33:24.242549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21177 16:33:24.288671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21179 16:33:24.288963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21180 16:33:24.334961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21182 16:33:24.335254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21183 16:33:24.381168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21184 16:33:24.381459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21186 16:33:24.427802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21187 16:33:24.428090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21189 16:33:24.474239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21191 16:33:24.474556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21192 16:33:24.521527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21193 16:33:24.521851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21195 16:33:24.567925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21197 16:33:24.568212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21198 16:33:24.614745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21199 16:33:24.615032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21201 16:33:24.660815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21202 16:33:24.661103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21204 16:33:24.707085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21205 16:33:24.707372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21207 16:33:24.753082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21208 16:33:24.753364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21210 16:33:24.800806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21211 16:33:24.801094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21213 16:33:24.847608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21214 16:33:24.847878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21216 16:33:24.894263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21218 16:33:24.894608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21219 16:33:24.943150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21220 16:33:24.943448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21222 16:33:24.989420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21224 16:33:24.989728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21225 16:33:25.037137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21227 16:33:25.037371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21228 16:33:25.081216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21229 16:33:25.081505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21231 16:33:25.127710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21232 16:33:25.127998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21234 16:33:25.177471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21235 16:33:25.177761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21237 16:33:25.224702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21239 16:33:25.224998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21240 16:33:25.279756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21241 16:33:25.280045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21243 16:33:25.331293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21245 16:33:25.331697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21246 16:33:25.380878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21247 16:33:25.381174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21249 16:33:25.436041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21250 16:33:25.436335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21252 16:33:25.495209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21253 16:33:25.495503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21255 16:33:25.541316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21256 16:33:25.541613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21258 16:33:25.588064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21259 16:33:25.588358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21261 16:33:25.633953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21262 16:33:25.634248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21264 16:33:25.680874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21266 16:33:25.681137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21267 16:33:25.727600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21268 16:33:25.727894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21270 16:33:25.773570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21271 16:33:25.773991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21273 16:33:25.820915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21275 16:33:25.821362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21276 16:33:25.867706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21278 16:33:25.868141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21279 16:33:25.914367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21281 16:33:25.914753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21282 16:33:25.961445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21283 16:33:25.961863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21285 16:33:26.008076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21286 16:33:26.008478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21288 16:33:26.059886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21289 16:33:26.060306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21291 16:33:26.107171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21292 16:33:26.107586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21294 16:33:26.153815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21296 16:33:26.154267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21297 16:33:26.200743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21299 16:33:26.201136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21300 16:33:26.247467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21301 16:33:26.247878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21303 16:33:26.293775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21304 16:33:26.294181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21306 16:33:26.341965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21307 16:33:26.342385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21309 16:33:26.391980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21310 16:33:26.392390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21312 16:33:26.438371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21314 16:33:26.438806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21315 16:33:26.485435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21316 16:33:26.485849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21318 16:33:26.532554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21319 16:33:26.532975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21321 16:33:26.583685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21322 16:33:26.584054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21324 16:33:26.629847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21325 16:33:26.630136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21327 16:33:26.676530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21328 16:33:26.676824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21330 16:33:26.725340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21331 16:33:26.725770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21333 16:33:26.775972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21334 16:33:26.776381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21336 16:33:26.823573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21338 16:33:26.823863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21339 16:33:26.869472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21340 16:33:26.869759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21342 16:33:26.916509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21344 16:33:26.916797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21345 16:33:26.963068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21346 16:33:26.963360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21348 16:33:27.008964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21349 16:33:27.009271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21351 16:33:27.055540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21352 16:33:27.055815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21354 16:33:27.101977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21356 16:33:27.102209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21357 16:33:27.148574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21359 16:33:27.148861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21360 16:33:27.195416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21361 16:33:27.195708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21363 16:33:27.241446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21364 16:33:27.241738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21366 16:33:27.288313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21368 16:33:27.288603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21369 16:33:27.335747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21370 16:33:27.336027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21372 16:33:27.381968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21374 16:33:27.382404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21375 16:33:27.429173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21376 16:33:27.429578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21378 16:33:27.475925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21379 16:33:27.476257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21381 16:33:27.523457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21382 16:33:27.523865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21384 16:33:27.570274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21386 16:33:27.570692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21387 16:33:27.619881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21388 16:33:27.620300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21390 16:33:27.667460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21391 16:33:27.667836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21393 16:33:27.714474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21395 16:33:27.715260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21396 16:33:27.763078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21397 16:33:27.763492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21399 16:33:27.810831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21400 16:33:27.811240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21402 16:33:27.858477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21404 16:33:27.858972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21405 16:33:27.906905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21406 16:33:27.907310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21408 16:33:27.953711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21410 16:33:27.954197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21411 16:33:28.001461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21412 16:33:28.001876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21414 16:33:28.049379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21415 16:33:28.049758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21417 16:33:28.098899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21418 16:33:28.099311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21420 16:33:28.146871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21421 16:33:28.147283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21423 16:33:28.195091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21424 16:33:28.195500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21426 16:33:28.242386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21428 16:33:28.242849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21429 16:33:28.291157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21430 16:33:28.291532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21432 16:33:28.340683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21434 16:33:28.341259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21435 16:33:28.391984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21436 16:33:28.392405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21438 16:33:28.440067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21439 16:33:28.440478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21441 16:33:28.488393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21442 16:33:28.488806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21444 16:33:28.536408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21445 16:33:28.536823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21447 16:33:28.585228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21448 16:33:28.585595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21450 16:33:28.633386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21451 16:33:28.633806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21453 16:33:28.681976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21454 16:33:28.682411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21456 16:33:28.732446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21458 16:33:28.732812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21459 16:33:28.785129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21460 16:33:28.785552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21462 16:33:28.838043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21463 16:33:28.838431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21465 16:33:28.897294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21467 16:33:28.897785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21468 16:33:28.944135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21469 16:33:28.944556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21471 16:33:28.992121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21472 16:33:28.992548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21474 16:33:29.040761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21476 16:33:29.041161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21477 16:33:29.087873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21478 16:33:29.088259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21480 16:33:29.136885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21481 16:33:29.137303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21483 16:33:29.184782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21484 16:33:29.185196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21486 16:33:29.232397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21488 16:33:29.232859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21489 16:33:29.280523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21490 16:33:29.280914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21492 16:33:29.329680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21494 16:33:29.330135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21495 16:33:29.377849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21496 16:33:29.378256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21498 16:33:29.427290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21500 16:33:29.427762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21501 16:33:29.475002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21502 16:33:29.475404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21504 16:33:29.522368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21506 16:33:29.522930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21507 16:33:29.570433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21509 16:33:29.570869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21510 16:33:29.618450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21512 16:33:29.618880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21513 16:33:29.667739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21514 16:33:29.668150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21516 16:33:29.715399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21517 16:33:29.715803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21519 16:33:29.762994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21520 16:33:29.763395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21522 16:33:29.810889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21524 16:33:29.811312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21525 16:33:29.859137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21526 16:33:29.859548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21528 16:33:29.907846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21530 16:33:29.908300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21531 16:33:29.955517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21532 16:33:29.955923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21534 16:33:30.003544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21535 16:33:30.003955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21537 16:33:30.048829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21538 16:33:30.049239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21540 16:33:30.096601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21541 16:33:30.097003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21543 16:33:30.144507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21544 16:33:30.144917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21546 16:33:30.192230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21547 16:33:30.192633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21549 16:33:30.239789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21550 16:33:30.245444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21552 16:33:30.291984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21553 16:33:30.292431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21555 16:33:30.344416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21557 16:33:30.344911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21558 16:33:30.397097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21560 16:33:30.397535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21561 16:33:30.445553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21562 16:33:30.445987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21564 16:33:30.495396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21565 16:33:30.495814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21567 16:33:30.543458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21568 16:33:30.543850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21570 16:33:30.611317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21571 16:33:30.611760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21573 16:33:30.659466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21574 16:33:30.659883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21576 16:33:30.708169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21578 16:33:30.708607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21579 16:33:30.755945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21580 16:33:30.756320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21582 16:33:30.803467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21584 16:33:30.803891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21585 16:33:30.851272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21586 16:33:30.851694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21588 16:33:30.898804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21589 16:33:30.899211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21591 16:33:30.945909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21592 16:33:30.946331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21594 16:33:30.995282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21595 16:33:30.995687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21597 16:33:31.042481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21599 16:33:31.042910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21600 16:33:31.090026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21602 16:33:31.090453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21603 16:33:31.137085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21604 16:33:31.137436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21606 16:33:31.184630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21607 16:33:31.185039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21609 16:33:31.233314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21610 16:33:31.233688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21612 16:33:31.280911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21613 16:33:31.281330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21615 16:33:31.328956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21616 16:33:31.329363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21618 16:33:31.376081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21619 16:33:31.376489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21621 16:33:31.420975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21622 16:33:31.421392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21624 16:33:31.468574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21625 16:33:31.468985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21627 16:33:31.515878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21628 16:33:31.516281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21630 16:33:31.563660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21631 16:33:31.564069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21633 16:33:31.611188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21634 16:33:31.611601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21636 16:33:31.659249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21637 16:33:31.659664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21639 16:33:31.708322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21641 16:33:31.708776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21642 16:33:31.756909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21643 16:33:31.757326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21645 16:33:31.804948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21646 16:33:31.805351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21648 16:33:31.853621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21649 16:33:31.854045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21651 16:33:31.901553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21653 16:33:31.902010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21654 16:33:31.948099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21655 16:33:31.948459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21657 16:33:31.995871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21658 16:33:31.996254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21660 16:33:32.042901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21661 16:33:32.043328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21663 16:33:32.089925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21664 16:33:32.090354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21666 16:33:32.137129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21667 16:33:32.137537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21669 16:33:32.184192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21670 16:33:32.184606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21672 16:33:32.232857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21673 16:33:32.233287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21675 16:33:32.280072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21677 16:33:32.280540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21678 16:33:32.327287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21679 16:33:32.327709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21681 16:33:32.374009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21682 16:33:32.374424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21684 16:33:32.421488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21686 16:33:32.421964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21687 16:33:32.469116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21689 16:33:32.469562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21690 16:33:32.517352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21691 16:33:32.517770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21693 16:33:32.566260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21695 16:33:32.566730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21696 16:33:32.617237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21697 16:33:32.617659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21699 16:33:32.664440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21700 16:33:32.664869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21702 16:33:32.712311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21703 16:33:32.712742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21705 16:33:32.760074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21706 16:33:32.760487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21708 16:33:32.807236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21709 16:33:32.807648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21711 16:33:32.855716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21712 16:33:32.856127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21714 16:33:32.903295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21715 16:33:32.903669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21717 16:33:32.950478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
21719 16:33:32.950961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21720 16:33:32.997208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
21721 16:33:32.997615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
21723 16:33:33.043977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
21724 16:33:33.044419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
21726 16:33:33.090951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
21728 16:33:33.091442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
21729 16:33:33.137783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
21730 16:33:33.138192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
21732 16:33:33.184181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
21733 16:33:33.184602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
21735 16:33:33.231817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
21736 16:33:33.232209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
21738 16:33:33.279197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
21739 16:33:33.279567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
21741 16:33:33.325952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
21742 16:33:33.326363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
21744 16:33:33.374355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
21746 16:33:33.374867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
21747 16:33:33.421085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
21749 16:33:33.421576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
21750 16:33:33.468090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
21751 16:33:33.468522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
21753 16:33:33.514867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
21755 16:33:33.515310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
21756 16:33:33.561491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
21758 16:33:33.561941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
21759 16:33:33.607954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
21760 16:33:33.608368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
21762 16:33:33.655122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
21763 16:33:33.655506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
21765 16:33:33.701531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
21766 16:33:33.701970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
21768 16:33:33.750006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
21769 16:33:33.750397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
21771 16:33:33.797156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
21772 16:33:33.797574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
21774 16:33:33.844477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
21775 16:33:33.844885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
21777 16:33:33.891422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
21778 16:33:33.891844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
21780 16:33:33.937893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
21782 16:33:33.938330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
21783 16:33:33.986324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
21785 16:33:33.986807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
21786 16:33:34.032743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
21787 16:33:34.033156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
21789 16:33:34.083422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
21790 16:33:34.083848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
21792 16:33:34.130036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
21793 16:33:34.130453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
21795 16:33:34.177529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
21796 16:33:34.177920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
21798 16:33:34.224669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
21799 16:33:34.225075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
21801 16:33:34.272659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
21802 16:33:34.273072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
21804 16:33:34.320697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
21805 16:33:34.321130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
21807 16:33:34.368083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
21808 16:33:34.368496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
21810 16:33:34.417862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
21811 16:33:34.418232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
21813 16:33:34.465895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
21815 16:33:34.466397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
21816 16:33:34.513158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
21817 16:33:34.513580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
21819 16:33:34.560413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
21821 16:33:34.560849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
21822 16:33:34.607735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
21823 16:33:34.608163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
21825 16:33:34.655605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
21826 16:33:34.656021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
21828 16:33:34.702920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
21830 16:33:34.703387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
21831 16:33:34.749848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
21832 16:33:34.750264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
21834 16:33:34.797252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
21835 16:33:34.797669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
21837 16:33:34.844563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
21838 16:33:34.844975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
21840 16:33:34.892508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
21842 16:33:34.892977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
21843 16:33:34.939724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
21844 16:33:34.940102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
21846 16:33:34.986966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
21847 16:33:34.987395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
21849 16:33:35.035714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
21851 16:33:35.036206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
21852 16:33:35.082428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
21854 16:33:35.083007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
21855 16:33:35.129907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
21856 16:33:35.130351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
21858 16:33:35.177507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
21859 16:33:35.177947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
21861 16:33:35.226308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
21863 16:33:35.226781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
21864 16:33:35.274093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
21866 16:33:35.274539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
21867 16:33:35.323771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
21868 16:33:35.324214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
21870 16:33:35.371874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
21871 16:33:35.372279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
21873 16:33:35.419439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
21875 16:33:35.419877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
21876 16:33:35.466955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
21877 16:33:35.467391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
21879 16:33:35.513706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
21881 16:33:35.514060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
21882 16:33:35.562919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
21883 16:33:35.563334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
21885 16:33:35.611079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
21886 16:33:35.611514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
21888 16:33:35.658759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
21889 16:33:35.659170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
21891 16:33:35.728405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
21892 16:33:35.728821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
21894 16:33:35.776555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
21896 16:33:35.776990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
21897 16:33:35.824951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
21898 16:33:35.825361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
21900 16:33:35.873151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
21902 16:33:35.873588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
21903 16:33:35.920730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
21904 16:33:35.921132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
21906 16:33:35.968120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
21907 16:33:35.968538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
21909 16:33:36.014420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
21911 16:33:36.015111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
21912 16:33:36.063515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
21913 16:33:36.063935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
21915 16:33:36.113180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
21916 16:33:36.113621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
21918 16:33:36.163361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
21919 16:33:36.163784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
21921 16:33:36.212168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
21922 16:33:36.212587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
21924 16:33:36.261623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
21926 16:33:36.262085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
21927 16:33:36.311469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
21928 16:33:36.311893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
21930 16:33:36.360958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
21931 16:33:36.361385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
21933 16:33:36.414382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
21935 16:33:36.414878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
21936 16:33:36.463880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
21937 16:33:36.464302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
21939 16:33:36.513866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
21941 16:33:36.514301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
21942 16:33:36.561797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
21943 16:33:36.562234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
21945 16:33:36.610345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
21947 16:33:36.610732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
21948 16:33:36.657281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
21949 16:33:36.657688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
21951 16:33:36.704721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
21952 16:33:36.705128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
21954 16:33:36.751791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
21956 16:33:36.752215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
21957 16:33:36.798871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
21958 16:33:36.799293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
21960 16:33:36.846945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
21962 16:33:36.847382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
21963 16:33:36.893557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
21964 16:33:36.893985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
21966 16:33:36.940256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
21968 16:33:36.940694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
21969 16:33:36.988464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
21970 16:33:36.988884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
21972 16:33:37.035582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
21973 16:33:37.035996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
21975 16:33:37.082043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
21976 16:33:37.082463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
21978 16:33:37.130381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
21980 16:33:37.130811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
21981 16:33:37.177691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
21983 16:33:37.178159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
21984 16:33:37.224367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
21985 16:33:37.224776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
21987 16:33:37.271684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
21988 16:33:37.272096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
21990 16:33:37.319169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
21992 16:33:37.319598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
21993 16:33:37.367143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
21994 16:33:37.367563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
21996 16:33:37.413435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
21997 16:33:37.413850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
21999 16:33:37.461298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22001 16:33:37.461799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22002 16:33:37.508526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22003 16:33:37.508967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22005 16:33:37.553981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22006 16:33:37.554391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22008 16:33:37.600380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22010 16:33:37.600841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22011 16:33:37.648052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22012 16:33:37.648474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22014 16:33:37.697742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22015 16:33:37.698188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22017 16:33:37.745329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22018 16:33:37.745758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22020 16:33:37.792763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22021 16:33:37.793146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22023 16:33:37.839937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22025 16:33:37.840338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22026 16:33:37.888010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22028 16:33:37.888458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22029 16:33:37.935764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22031 16:33:37.936218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22032 16:33:37.985026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22033 16:33:37.985445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22035 16:33:38.034413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22037 16:33:38.034849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22038 16:33:38.083636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22040 16:33:38.084073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22041 16:33:38.131285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22042 16:33:38.131691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22044 16:33:38.179259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22045 16:33:38.179664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22047 16:33:38.226324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22049 16:33:38.226752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22050 16:33:38.273890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22051 16:33:38.274316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22053 16:33:38.321887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22054 16:33:38.322327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22056 16:33:38.370835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22058 16:33:38.371267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22059 16:33:38.417569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22060 16:33:38.417982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22062 16:33:38.465558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22064 16:33:38.465999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22065 16:33:38.515287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22067 16:33:38.515781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22068 16:33:38.565565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22070 16:33:38.566027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22071 16:33:38.617027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22072 16:33:38.617457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22074 16:33:38.664865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22075 16:33:38.665285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22077 16:33:38.713918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22078 16:33:38.714362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22080 16:33:38.764149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22081 16:33:38.764571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22083 16:33:38.813990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22084 16:33:38.814423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22086 16:33:38.861860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22087 16:33:38.862286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22089 16:33:38.911640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22091 16:33:38.912088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22092 16:33:38.957105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22093 16:33:38.957510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22095 16:33:39.005104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22096 16:33:39.005526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22098 16:33:39.055547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22099 16:33:39.055972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22101 16:33:39.104488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22103 16:33:39.104853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22104 16:33:39.153086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22105 16:33:39.153505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22107 16:33:39.201879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22108 16:33:39.202322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22110 16:33:39.253992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22111 16:33:39.254407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22113 16:33:39.303977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22114 16:33:39.304390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22116 16:33:39.351804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22118 16:33:39.352242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22119 16:33:39.401491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22120 16:33:39.401918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22122 16:33:39.452953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22123 16:33:39.453381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22125 16:33:39.503540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22126 16:33:39.503958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22128 16:33:39.554481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22130 16:33:39.554939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22131 16:33:39.604560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22132 16:33:39.604974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22134 16:33:39.655583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22135 16:33:39.656012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22137 16:33:39.705143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22138 16:33:39.705558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22140 16:33:39.752803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22141 16:33:39.753204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22143 16:33:39.800606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22144 16:33:39.801024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22146 16:33:39.848431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22147 16:33:39.848844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22149 16:33:39.896041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22150 16:33:39.896458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22152 16:33:39.944479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22154 16:33:39.944907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22155 16:33:39.991657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22156 16:33:39.992069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22158 16:33:40.039829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22159 16:33:40.040238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22161 16:33:40.087452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22162 16:33:40.087851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22164 16:33:40.134854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22165 16:33:40.135262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22167 16:33:40.183098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22168 16:33:40.183501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22170 16:33:40.231956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22171 16:33:40.232379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22173 16:33:40.279847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22174 16:33:40.280262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22176 16:33:40.328193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22177 16:33:40.328613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22179 16:33:40.376017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22181 16:33:40.376466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22182 16:33:40.422592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22183 16:33:40.422994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22185 16:33:40.470548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22187 16:33:40.471423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22188 16:33:40.518059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22189 16:33:40.518460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22191 16:33:40.566971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22192 16:33:40.567382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22194 16:33:40.614724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22195 16:33:40.615126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22197 16:33:40.663188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22198 16:33:40.663592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22200 16:33:40.709550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22201 16:33:40.709961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22203 16:33:40.757482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22204 16:33:40.757913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22206 16:33:40.830346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22208 16:33:40.830784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22209 16:33:40.879470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22210 16:33:40.879889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22212 16:33:40.927658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22214 16:33:40.928110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22215 16:33:40.974392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22217 16:33:40.974840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22218 16:33:41.021046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22219 16:33:41.021462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22221 16:33:41.067063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22222 16:33:41.067499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22224 16:33:41.113884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22225 16:33:41.114299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22227 16:33:41.163769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22229 16:33:41.164268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22230 16:33:41.211797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22231 16:33:41.212209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22233 16:33:41.259188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22234 16:33:41.259594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22236 16:33:41.306849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22237 16:33:41.307252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22239 16:33:41.355333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22240 16:33:41.355744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22242 16:33:41.402819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22243 16:33:41.403234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22245 16:33:41.450815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22246 16:33:41.451208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22248 16:33:41.499399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22249 16:33:41.499821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22251 16:33:41.547221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22253 16:33:41.547651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22254 16:33:41.595298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22255 16:33:41.595722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22257 16:33:41.643768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22258 16:33:41.644186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22260 16:33:41.692114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22262 16:33:41.692534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22263 16:33:41.741563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22264 16:33:41.741989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22266 16:33:41.791459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22267 16:33:41.791882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22269 16:33:41.839215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22270 16:33:41.839645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22272 16:33:41.887346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22273 16:33:41.887793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22275 16:33:41.936813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22276 16:33:41.937244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22278 16:33:41.988416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22279 16:33:41.988863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22281 16:33:42.039906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22282 16:33:42.040326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22284 16:33:42.089073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22285 16:33:42.089495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22287 16:33:42.139774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22288 16:33:42.140207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22290 16:33:42.189016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22291 16:33:42.189433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22293 16:33:42.239622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22294 16:33:42.240038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22296 16:33:42.288180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22297 16:33:42.288615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22299 16:33:42.338789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22300 16:33:42.339223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22302 16:33:42.389238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22303 16:33:42.389660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22305 16:33:42.440157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22306 16:33:42.440593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22308 16:33:42.491015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22309 16:33:42.491435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22311 16:33:42.539783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22312 16:33:42.540202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22314 16:33:42.587902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22315 16:33:42.588316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22317 16:33:42.637174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22318 16:33:42.637609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22320 16:33:42.689525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22322 16:33:42.690009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22323 16:33:42.739494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22324 16:33:42.739913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22326 16:33:42.789656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22327 16:33:42.790074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22329 16:33:42.840298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22330 16:33:42.840696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22332 16:33:42.888608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22334 16:33:42.889086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22335 16:33:42.937717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22336 16:33:42.938137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22338 16:33:42.985715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22339 16:33:42.986136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22341 16:33:43.034440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22343 16:33:43.034893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22344 16:33:43.082920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22345 16:33:43.083328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22347 16:33:43.131156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22349 16:33:43.131564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22350 16:33:43.177906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22351 16:33:43.178309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22353 16:33:43.224498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22354 16:33:43.224909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22356 16:33:43.272285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22358 16:33:43.272714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22359 16:33:43.320382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22360 16:33:43.320799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22362 16:33:43.369449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22363 16:33:43.369864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22365 16:33:43.417440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22366 16:33:43.417859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22368 16:33:43.466251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22370 16:33:43.466735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22371 16:33:43.514027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22372 16:33:43.514432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22374 16:33:43.561849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22375 16:33:43.562259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22377 16:33:43.611126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22378 16:33:43.611507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22380 16:33:43.657458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22381 16:33:43.657890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22383 16:33:43.705394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22384 16:33:43.705796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22386 16:33:43.753467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22388 16:33:43.753904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22389 16:33:43.801548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22390 16:33:43.801966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22392 16:33:43.848635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22393 16:33:43.849042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22395 16:33:43.896315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22396 16:33:43.896720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22398 16:33:43.944163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22399 16:33:43.944572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22401 16:33:43.992902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22403 16:33:43.993341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22404 16:33:44.039964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22406 16:33:44.040363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22407 16:33:44.085483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22408 16:33:44.085914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22410 16:33:44.134109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22412 16:33:44.134707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22413 16:33:44.180874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22414 16:33:44.181290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22416 16:33:44.230781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22417 16:33:44.231192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22419 16:33:44.279774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22420 16:33:44.280187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22422 16:33:44.328012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22423 16:33:44.328390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22425 16:33:44.375701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22427 16:33:44.376133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22428 16:33:44.423144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22429 16:33:44.423547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22431 16:33:44.471070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22432 16:33:44.471474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22434 16:33:44.517712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22436 16:33:44.518144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22437 16:33:44.566524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22439 16:33:44.566969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22440 16:33:44.614994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22441 16:33:44.615404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22443 16:33:44.662275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22445 16:33:44.662738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22446 16:33:44.710312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22448 16:33:44.710737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22449 16:33:44.758279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22451 16:33:44.758791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22452 16:33:44.804638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22453 16:33:44.805046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22455 16:33:44.852216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22456 16:33:44.852631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22458 16:33:44.900417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22460 16:33:44.900851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22461 16:33:44.947370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22462 16:33:44.947792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22464 16:33:44.994454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22466 16:33:44.994929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22467 16:33:45.042756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22468 16:33:45.043183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22470 16:33:45.090471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22472 16:33:45.090925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22473 16:33:45.139683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22474 16:33:45.140096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22476 16:33:45.187281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22477 16:33:45.187688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22479 16:33:45.235040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22480 16:33:45.235446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22482 16:33:45.283223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22483 16:33:45.288808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22485 16:33:45.333188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22487 16:33:45.333579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22488 16:33:45.380863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22490 16:33:45.381289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22491 16:33:45.427290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22492 16:33:45.427709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22494 16:33:45.472021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22496 16:33:45.472454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22497 16:33:45.520056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22499 16:33:45.520487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22500 16:33:45.567902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22502 16:33:45.568335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22503 16:33:45.615394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22505 16:33:45.615775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22506 16:33:45.663158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22508 16:33:45.663631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22509 16:33:45.710341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22511 16:33:45.710819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22512 16:33:45.759354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22514 16:33:45.759808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22515 16:33:45.807137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22516 16:33:45.807546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22518 16:33:45.855374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22519 16:33:45.855775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22521 16:33:45.902752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22522 16:33:45.903155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22524 16:33:45.971881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22525 16:33:45.972323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22527 16:33:46.019931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22528 16:33:46.020345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22530 16:33:46.065820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22531 16:33:46.066230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22533 16:33:46.114013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22534 16:33:46.114426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22536 16:33:46.163510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22537 16:33:46.163862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22539 16:33:46.210040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22540 16:33:46.210456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22542 16:33:46.257201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22543 16:33:46.257631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22545 16:33:46.306925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22546 16:33:46.307346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22548 16:33:46.355099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22549 16:33:46.355494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22551 16:33:46.403454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22552 16:33:46.403865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22554 16:33:46.452241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22555 16:33:46.452651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22557 16:33:46.500012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22558 16:33:46.500428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22560 16:33:46.548138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22562 16:33:46.548592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22563 16:33:46.596306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22565 16:33:46.596734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22566 16:33:46.643962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22567 16:33:46.644350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22569 16:33:46.692900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22570 16:33:46.693321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22572 16:33:46.742349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22574 16:33:46.742834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22575 16:33:46.792107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22576 16:33:46.792484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22578 16:33:46.840365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22580 16:33:46.840775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22581 16:33:46.889270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22582 16:33:46.889706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22584 16:33:46.940325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22585 16:33:46.940741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22587 16:33:46.988485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22588 16:33:46.988895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22590 16:33:47.036650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22591 16:33:47.037041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22593 16:33:47.084811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22594 16:33:47.085185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22596 16:33:47.132485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22597 16:33:47.132886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22599 16:33:47.180114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22601 16:33:47.180548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22602 16:33:47.227671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22603 16:33:47.228087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22605 16:33:47.275697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22606 16:33:47.276116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22608 16:33:47.324805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22610 16:33:47.325243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22611 16:33:47.372986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22612 16:33:47.373394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22614 16:33:47.420635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22616 16:33:47.421085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22617 16:33:47.468313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22618 16:33:47.468726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22620 16:33:47.516074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22622 16:33:47.516480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22623 16:33:47.563257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22624 16:33:47.563660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22626 16:33:47.609624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22627 16:33:47.610060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22629 16:33:47.658011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22630 16:33:47.658420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22632 16:33:47.705833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22633 16:33:47.706268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22635 16:33:47.753510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22636 16:33:47.753910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22638 16:33:47.801202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22639 16:33:47.801575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22641 16:33:47.849369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22643 16:33:47.849822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22644 16:33:47.896940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22645 16:33:47.897321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22647 16:33:47.944861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22648 16:33:47.945272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22650 16:33:47.993685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22651 16:33:47.994108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22653 16:33:48.042051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22654 16:33:48.042468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22656 16:33:48.089715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22657 16:33:48.090124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22659 16:33:48.137964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22660 16:33:48.138378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22662 16:33:48.188968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22664 16:33:48.189425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22665 16:33:48.238149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22667 16:33:48.238637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22668 16:33:48.285853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22669 16:33:48.286259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22671 16:33:48.333718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22672 16:33:48.334130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22674 16:33:48.381409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22675 16:33:48.381824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22677 16:33:48.429560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22679 16:33:48.430048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22680 16:33:48.477180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22681 16:33:48.477593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22683 16:33:48.525951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22684 16:33:48.526381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22686 16:33:48.574412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22687 16:33:48.574822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22689 16:33:48.623150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22690 16:33:48.623557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22692 16:33:48.671510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22693 16:33:48.671888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22695 16:33:48.717798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22696 16:33:48.718206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22698 16:33:48.767873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22699 16:33:48.768306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22701 16:33:48.819424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22702 16:33:48.819847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22704 16:33:48.872825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22705 16:33:48.873262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22707 16:33:48.921724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22709 16:33:48.922184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22710 16:33:48.969401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22711 16:33:48.969808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22713 16:33:49.017342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22714 16:33:49.017763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22716 16:33:49.065705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22717 16:33:49.066129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22719 16:33:49.114117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
22720 16:33:49.114551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
22722 16:33:49.162356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
22724 16:33:49.162977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
22725 16:33:49.211299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
22726 16:33:49.211713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
22728 16:33:49.260510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
22729 16:33:49.260924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
22731 16:33:49.308809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
22732 16:33:49.309219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
22734 16:33:49.356886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
22735 16:33:49.357302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
22737 16:33:49.405508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
22739 16:33:49.405975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
22740 16:33:49.454332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
22742 16:33:49.454767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
22743 16:33:49.500837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
22744 16:33:49.501244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
22746 16:33:49.549785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
22747 16:33:49.550196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
22749 16:33:49.598271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
22751 16:33:49.598698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
22752 16:33:49.645887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
22753 16:33:49.646309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
22755 16:33:49.695133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
22757 16:33:49.695580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
22758 16:33:49.743043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
22760 16:33:49.743489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
22761 16:33:49.791521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
22762 16:33:49.791943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
22764 16:33:49.838958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
22765 16:33:49.839369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
22767 16:33:49.886758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
22768 16:33:49.887164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
22770 16:33:49.935491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
22771 16:33:49.935896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
22773 16:33:49.985166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
22774 16:33:49.985579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
22776 16:33:50.033444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
22777 16:33:50.033870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
22779 16:33:50.081676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
22780 16:33:50.082088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
22782 16:33:50.130231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
22784 16:33:50.130665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
22785 16:33:50.178306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
22786 16:33:50.178711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
22788 16:33:50.226282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
22790 16:33:50.226739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
22791 16:33:50.274255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
22793 16:33:50.274713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
22794 16:33:50.321786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
22795 16:33:50.322222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
22797 16:33:50.372727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
22798 16:33:50.373143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
22800 16:33:50.422207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
22802 16:33:50.422639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
22803 16:33:50.468285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
22805 16:33:50.468714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
22806 16:33:50.516262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
22807 16:33:50.516689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
22809 16:33:50.563915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
22811 16:33:50.564409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
22812 16:33:50.611721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
22813 16:33:50.612138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
22815 16:33:50.659706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
22816 16:33:50.660131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
22818 16:33:50.707604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
22819 16:33:50.708032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
22821 16:33:50.756167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
22823 16:33:50.756646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
22824 16:33:50.805080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
22825 16:33:50.805497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
22827 16:33:50.853414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
22828 16:33:50.853821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
22830 16:33:50.901235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
22831 16:33:50.901643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
22833 16:33:50.949103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
22835 16:33:50.949572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
22836 16:33:50.996376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
22837 16:33:50.996781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
22839 16:33:51.065713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
22841 16:33:51.066162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
22842 16:33:51.115985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
22843 16:33:51.116433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
22845 16:33:51.163946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
22847 16:33:51.164387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
22848 16:33:51.211055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
22849 16:33:51.211453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
22851 16:33:51.258392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
22853 16:33:51.258776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
22854 16:33:51.305554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
22855 16:33:51.305981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
22857 16:33:51.353079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
22858 16:33:51.353494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
22860 16:33:51.400051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
22861 16:33:51.400424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
22863 16:33:51.447649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
22864 16:33:51.448082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
22866 16:33:51.495527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
22867 16:33:51.495951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
22869 16:33:51.543147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
22870 16:33:51.543561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
22872 16:33:51.589702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
22873 16:33:51.590112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
22875 16:33:51.637244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
22876 16:33:51.637631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
22878 16:33:51.684773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
22879 16:33:51.685205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
22881 16:33:51.731946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
22882 16:33:51.732354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
22884 16:33:51.779224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
22885 16:33:51.779640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
22887 16:33:51.825908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
22888 16:33:51.826333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
22890 16:33:51.873800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
22892 16:33:51.874290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
22893 16:33:51.923189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
22895 16:33:51.923642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
22896 16:33:51.933197 <47>[ 294.539335] systemd-journald[105]: Sent WATCHDOG=1 notification.
22897 16:33:51.981163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
22899 16:33:51.981616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
22900 16:33:52.029380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
22901 16:33:52.029797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
22903 16:33:52.076821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
22905 16:33:52.077304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
22906 16:33:52.124147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
22907 16:33:52.124560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
22909 16:33:52.171500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
22911 16:33:52.171878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
22912 16:33:52.218521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
22914 16:33:52.218959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
22915 16:33:52.265519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
22916 16:33:52.265944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
22918 16:33:52.313161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
22919 16:33:52.313574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
22921 16:33:52.361718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
22922 16:33:52.362137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
22924 16:33:52.409288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
22925 16:33:52.409670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
22927 16:33:52.457690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
22928 16:33:52.458109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
22930 16:33:52.505196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
22931 16:33:52.505608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
22933 16:33:52.552755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
22934 16:33:52.553184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
22936 16:33:52.600637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
22938 16:33:52.601076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
22939 16:33:52.648854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
22940 16:33:52.649232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
22942 16:33:52.696272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
22943 16:33:52.696689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
22945 16:33:52.743881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
22947 16:33:52.744284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
22948 16:33:52.791234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
22949 16:33:52.791647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
22951 16:33:52.838550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
22953 16:33:52.839034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
22954 16:33:52.887486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
22955 16:33:52.887918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
22957 16:33:52.934875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
22958 16:33:52.935302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
22960 16:33:52.981959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
22961 16:33:52.982368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
22963 16:33:53.029437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
22964 16:33:53.029865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
22966 16:33:53.077225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
22968 16:33:53.077672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
22969 16:33:53.124810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
22970 16:33:53.125218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
22972 16:33:53.171914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
22973 16:33:53.172288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
22975 16:33:53.220027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
22976 16:33:53.220464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
22978 16:33:53.267647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
22979 16:33:53.268041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
22981 16:33:53.315196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
22982 16:33:53.315571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
22984 16:33:53.362277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
22986 16:33:53.362704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
22987 16:33:53.409344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
22988 16:33:53.409763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
22990 16:33:53.456834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
22992 16:33:53.457275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
22993 16:33:53.505069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
22994 16:33:53.505448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
22996 16:33:53.552470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
22997 16:33:53.552879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
22999 16:33:53.601126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23000 16:33:53.601560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23002 16:33:53.648647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23003 16:33:53.648993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23005 16:33:53.696472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23007 16:33:53.696906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23008 16:33:53.743691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23009 16:33:53.744095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23011 16:33:53.791213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23012 16:33:53.791606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23014 16:33:53.837859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23016 16:33:53.838240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23017 16:33:53.885039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23018 16:33:53.885450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23020 16:33:53.932651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23021 16:33:53.933066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23023 16:33:53.980086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23024 16:33:53.980494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23026 16:33:54.028057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23027 16:33:54.028484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23029 16:33:54.075763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23030 16:33:54.076189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23032 16:33:54.123783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23033 16:33:54.124218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23035 16:33:54.173190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23036 16:33:54.173609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23038 16:33:54.221391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23039 16:33:54.221809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23041 16:33:54.268979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23042 16:33:54.269360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23044 16:33:54.317346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23045 16:33:54.317768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23047 16:33:54.364624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23048 16:33:54.365059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23050 16:33:54.413700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23051 16:33:54.414125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23053 16:33:54.461868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23054 16:33:54.462278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23056 16:33:54.509894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23058 16:33:54.510323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23059 16:33:54.557883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23060 16:33:54.558288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23062 16:33:54.605572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23063 16:33:54.605984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23065 16:33:54.652964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23066 16:33:54.653371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23068 16:33:54.701354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23069 16:33:54.701766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23071 16:33:54.749783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23072 16:33:54.750190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23074 16:33:54.797545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23075 16:33:54.797959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23077 16:33:54.843938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23078 16:33:54.844349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23080 16:33:54.891769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23081 16:33:54.892151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23083 16:33:54.939430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23084 16:33:54.939814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23086 16:33:54.985516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23087 16:33:54.985931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23089 16:33:55.033577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23090 16:33:55.034009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23092 16:33:55.082530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23094 16:33:55.082952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23095 16:33:55.130286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23096 16:33:55.130694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23098 16:33:55.177719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23099 16:33:55.178132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23101 16:33:55.226314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23103 16:33:55.226801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23104 16:33:55.272726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23105 16:33:55.273143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23107 16:33:55.320995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23108 16:33:55.321409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23110 16:33:55.368115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23111 16:33:55.368542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23113 16:33:55.417606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23114 16:33:55.418038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23116 16:33:55.465680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23117 16:33:55.466098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23119 16:33:55.514126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23120 16:33:55.514535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23122 16:33:55.562821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23123 16:33:55.563228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23125 16:33:55.609921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23127 16:33:55.610390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23128 16:33:55.657466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23130 16:33:55.657932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23131 16:33:55.705996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23133 16:33:55.706433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23134 16:33:55.753725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23135 16:33:55.754151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23137 16:33:55.800031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23138 16:33:55.800443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23140 16:33:55.847718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23141 16:33:55.848129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23143 16:33:55.895765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23144 16:33:55.896163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23146 16:33:55.943682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23147 16:33:55.944116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23149 16:33:55.991738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23151 16:33:55.992203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23152 16:33:56.039198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23153 16:33:56.039608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23155 16:33:56.086995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23156 16:33:56.087414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23158 16:33:56.132819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23159 16:33:56.133237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23161 16:33:56.203088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23162 16:33:56.203507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23164 16:33:56.250441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23166 16:33:56.250857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23167 16:33:56.298569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23169 16:33:56.299033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23170 16:33:56.345963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23171 16:33:56.346381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23173 16:33:56.393526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23175 16:33:56.393983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23176 16:33:56.440805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23177 16:33:56.441221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23179 16:33:56.491872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23181 16:33:56.492564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23182 16:33:56.541874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23183 16:33:56.542290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23185 16:33:56.590861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23187 16:33:56.591304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23188 16:33:56.638361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23190 16:33:56.638816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23191 16:33:56.685409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23192 16:33:56.685819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23194 16:33:56.732519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23195 16:33:56.732903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23197 16:33:56.780024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23198 16:33:56.780442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23200 16:33:56.827446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23201 16:33:56.827862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23203 16:33:56.874851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23204 16:33:56.875287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23206 16:33:56.921616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23207 16:33:56.922042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23209 16:33:56.969999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23211 16:33:56.970430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23212 16:33:57.017860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23213 16:33:57.018278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23215 16:33:57.065548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23216 16:33:57.065979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23218 16:33:57.113021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23219 16:33:57.113437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23221 16:33:57.160438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23223 16:33:57.160882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23224 16:33:57.207908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23225 16:33:57.208286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23227 16:33:57.256325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23228 16:33:57.256706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23230 16:33:57.301107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23231 16:33:57.301530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23233 16:33:57.349310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23234 16:33:57.349685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23236 16:33:57.397046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23237 16:33:57.397456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23239 16:33:57.444635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23240 16:33:57.445043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23242 16:33:57.492929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23243 16:33:57.493337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23245 16:33:57.540900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23246 16:33:57.541277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23248 16:33:57.589241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23250 16:33:57.589696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23251 16:33:57.636231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23253 16:33:57.636529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23254 16:33:57.683955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23256 16:33:57.684266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23257 16:33:57.731731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23258 16:33:57.732024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23260 16:33:57.780607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23261 16:33:57.780985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23263 16:33:57.829633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23264 16:33:57.830044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23266 16:33:57.877910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23268 16:33:57.878387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23269 16:33:57.924279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23270 16:33:57.924691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23272 16:33:57.971632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23273 16:33:57.972043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23275 16:33:58.019575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23276 16:33:58.019983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23278 16:33:58.067286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23279 16:33:58.067662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23281 16:33:58.115770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23283 16:33:58.116205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23284 16:33:58.163402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23285 16:33:58.163820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23287 16:33:58.209984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23288 16:33:58.210275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23290 16:33:58.257385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23291 16:33:58.257677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23293 16:33:58.304757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23295 16:33:58.305073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23296 16:33:58.352051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23297 16:33:58.352320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23299 16:33:58.399633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23300 16:33:58.400030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23302 16:33:58.447411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23303 16:33:58.447807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23305 16:33:58.495889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23306 16:33:58.496327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23308 16:33:58.544394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23309 16:33:58.544831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23311 16:33:58.592270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23312 16:33:58.592653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23314 16:33:58.639854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23315 16:33:58.640272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23317 16:33:58.687615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23318 16:33:58.688026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23320 16:33:58.735208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23322 16:33:58.735643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23323 16:33:58.783803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23325 16:33:58.784250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23326 16:33:58.831573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23327 16:33:58.831952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23329 16:33:58.879216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23330 16:33:58.879628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23332 16:33:58.927064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23333 16:33:58.927475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23335 16:33:58.975184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23336 16:33:58.975581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23338 16:33:59.023641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23339 16:33:59.024020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23341 16:33:59.071993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23342 16:33:59.072341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23344 16:33:59.120071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23346 16:33:59.120311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23347 16:33:59.168001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23349 16:33:59.168302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23350 16:33:59.215814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23351 16:33:59.216224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23353 16:33:59.263172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23354 16:33:59.263581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23356 16:33:59.311249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23357 16:33:59.311660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23359 16:33:59.360713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23361 16:33:59.361155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23362 16:33:59.408861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23363 16:33:59.409273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23365 16:33:59.459060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23366 16:33:59.459494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23368 16:33:59.506848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23370 16:33:59.507280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23371 16:33:59.553321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23372 16:33:59.553612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23374 16:33:59.600849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23376 16:33:59.601144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23377 16:33:59.648966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23379 16:33:59.649258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23380 16:33:59.696332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23381 16:33:59.696619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23383 16:33:59.744009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23385 16:33:59.744305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23386 16:33:59.791068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23387 16:33:59.791366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23389 16:33:59.835694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23390 16:33:59.835986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23392 16:33:59.882955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23393 16:33:59.883225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23395 16:33:59.929369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23396 16:33:59.929667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23398 16:33:59.976586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23399 16:33:59.976878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23401 16:34:00.024348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23402 16:34:00.024609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23404 16:34:00.071481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23405 16:34:00.071773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23407 16:34:00.119084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23408 16:34:00.119375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23410 16:34:00.165359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23412 16:34:00.165654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23413 16:34:00.212933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23415 16:34:00.213222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23416 16:34:00.259642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23417 16:34:00.259931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23419 16:34:00.308077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23420 16:34:00.308459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23422 16:34:00.355985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23423 16:34:00.356347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23425 16:34:00.403437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23426 16:34:00.403811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23428 16:34:00.451175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23429 16:34:00.451598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23431 16:34:00.499129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23432 16:34:00.499425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23434 16:34:00.547615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23435 16:34:00.547964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23437 16:34:00.595165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23439 16:34:00.595587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23440 16:34:00.642208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23442 16:34:00.642511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23443 16:34:00.690058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23444 16:34:00.690355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23446 16:34:00.737549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23447 16:34:00.737862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23449 16:34:00.785215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23451 16:34:00.785505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23452 16:34:00.833848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23454 16:34:00.834142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23455 16:34:00.881312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23457 16:34:00.881601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23458 16:34:00.928326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23459 16:34:00.928613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23461 16:34:00.975359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23462 16:34:00.975648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23464 16:34:01.022339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23466 16:34:01.022626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23467 16:34:01.069103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23468 16:34:01.069392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23470 16:34:01.116511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23471 16:34:01.116799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23473 16:34:01.164059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23474 16:34:01.164348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23476 16:34:01.211511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23478 16:34:01.211818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23479 16:34:01.257688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23480 16:34:01.257982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23482 16:34:01.327197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23483 16:34:01.327489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23485 16:34:01.375697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23487 16:34:01.375999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23488 16:34:01.423395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23489 16:34:01.423687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23491 16:34:01.470250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23493 16:34:01.470644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23494 16:34:01.517623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23495 16:34:01.518034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23497 16:34:01.567134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23499 16:34:01.567510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23500 16:34:01.613635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23501 16:34:01.613940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23503 16:34:01.661111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23504 16:34:01.661543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23506 16:34:01.708583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23507 16:34:01.708992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23509 16:34:01.753149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23510 16:34:01.753578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23512 16:34:01.801393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23513 16:34:01.801804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23515 16:34:01.850919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23517 16:34:01.851347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23518 16:34:01.898757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23519 16:34:01.899177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23521 16:34:01.945512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23523 16:34:01.945956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23524 16:34:01.993329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23525 16:34:01.993749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23527 16:34:02.040481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23528 16:34:02.040871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23530 16:34:02.088610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23531 16:34:02.089037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23533 16:34:02.135958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23534 16:34:02.136364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23536 16:34:02.183072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23537 16:34:02.183482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23539 16:34:02.229950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23540 16:34:02.230358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23542 16:34:02.277415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23543 16:34:02.277677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23545 16:34:02.325147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23547 16:34:02.325439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23548 16:34:02.372666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23550 16:34:02.373149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23551 16:34:02.420014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23552 16:34:02.420425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23554 16:34:02.467922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23555 16:34:02.468347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23557 16:34:02.515705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23559 16:34:02.516132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23560 16:34:02.563059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23562 16:34:02.563492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23563 16:34:02.609891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23564 16:34:02.610276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23566 16:34:02.657315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23568 16:34:02.657697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23569 16:34:02.705610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23571 16:34:02.706056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23572 16:34:02.753178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23574 16:34:02.753608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23575 16:34:02.800336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23576 16:34:02.800677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23578 16:34:02.847563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23579 16:34:02.847857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23581 16:34:02.896312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23582 16:34:02.896593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23584 16:34:02.943823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23586 16:34:02.944121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23587 16:34:02.990871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23588 16:34:02.991162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23590 16:34:03.040227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23591 16:34:03.040517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23593 16:34:03.089542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23594 16:34:03.089838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23596 16:34:03.136552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23598 16:34:03.136844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23599 16:34:03.183657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23600 16:34:03.183951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23602 16:34:03.231022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23603 16:34:03.231444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23605 16:34:03.277615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23606 16:34:03.278031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23608 16:34:03.325610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23610 16:34:03.326087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23611 16:34:03.373772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23613 16:34:03.374258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23614 16:34:03.421722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23615 16:34:03.422141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23617 16:34:03.469683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23618 16:34:03.470094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23620 16:34:03.517320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23621 16:34:03.517683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23623 16:34:03.565405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23624 16:34:03.565825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23626 16:34:03.614288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23628 16:34:03.614829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23629 16:34:03.661707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23631 16:34:03.662173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23632 16:34:03.708702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23633 16:34:03.709115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23635 16:34:03.755962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23636 16:34:03.756384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23638 16:34:03.803576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23639 16:34:03.804005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23641 16:34:03.850771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23642 16:34:03.851188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23644 16:34:03.899555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23646 16:34:03.900003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23647 16:34:03.947548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23648 16:34:03.947978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23650 16:34:03.994961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23651 16:34:03.995340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23653 16:34:04.042042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23655 16:34:04.042474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23656 16:34:04.089219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23657 16:34:04.089617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23659 16:34:04.136716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23660 16:34:04.137129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23662 16:34:04.184248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23663 16:34:04.184656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23665 16:34:04.232044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23666 16:34:04.232477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23668 16:34:04.279628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23669 16:34:04.280011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23671 16:34:04.327175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23672 16:34:04.327572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23674 16:34:04.376131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23675 16:34:04.376553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23677 16:34:04.423754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23678 16:34:04.424186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23680 16:34:04.471885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23681 16:34:04.472317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23683 16:34:04.519445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23684 16:34:04.519874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23686 16:34:04.567127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23688 16:34:04.567560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23689 16:34:04.616000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23691 16:34:04.616439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23692 16:34:04.664191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23693 16:34:04.664627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23695 16:34:04.712090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23696 16:34:04.712518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23698 16:34:04.759523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23699 16:34:04.759936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23701 16:34:04.806881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23702 16:34:04.807315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23704 16:34:04.854041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23706 16:34:04.854488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23707 16:34:04.902928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23708 16:34:04.903343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23710 16:34:04.950802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23711 16:34:04.951249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23713 16:34:04.997721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23714 16:34:04.998153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23716 16:34:05.045219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23717 16:34:05.045651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23719 16:34:05.093014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
23720 16:34:05.093430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
23722 16:34:05.141275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
23723 16:34:05.141630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
23725 16:34:05.188809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
23726 16:34:05.189267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
23728 16:34:05.236792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
23730 16:34:05.237233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
23731 16:34:05.284159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
23732 16:34:05.284555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
23734 16:34:05.332177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
23735 16:34:05.332586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
23737 16:34:05.379641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
23738 16:34:05.380068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
23740 16:34:05.426978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
23741 16:34:05.427390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
23743 16:34:05.477194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
23744 16:34:05.477570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
23746 16:34:05.528476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
23747 16:34:05.528922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
23749 16:34:05.578957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
23750 16:34:05.579382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
23752 16:34:05.627480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
23753 16:34:05.627845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
23755 16:34:05.675505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
23756 16:34:05.675916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
23758 16:34:05.723749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
23759 16:34:05.724172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
23761 16:34:05.772547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
23762 16:34:05.772956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
23764 16:34:05.820499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
23765 16:34:05.820904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
23767 16:34:05.869121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
23768 16:34:05.869537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
23770 16:34:05.918315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
23772 16:34:05.918700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
23773 16:34:05.963726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
23774 16:34:05.964139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
23776 16:34:06.011472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
23777 16:34:06.011887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
23779 16:34:06.059382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
23780 16:34:06.059798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
23782 16:34:06.107368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
23784 16:34:06.107857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
23785 16:34:06.155968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
23786 16:34:06.156338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
23788 16:34:06.204462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
23789 16:34:06.204881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
23791 16:34:06.252375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
23792 16:34:06.252749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
23794 16:34:06.303049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
23795 16:34:06.303478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
23797 16:34:06.350485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
23799 16:34:06.351001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
23800 16:34:06.423214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
23802 16:34:06.423675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
23803 16:34:06.473279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
23804 16:34:06.473678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
23806 16:34:06.521628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
23807 16:34:06.522055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
23809 16:34:06.570371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
23810 16:34:06.570790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
23812 16:34:06.619497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
23814 16:34:06.619996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
23815 16:34:06.667409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
23816 16:34:06.667825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
23818 16:34:06.717394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
23819 16:34:06.717813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
23821 16:34:06.767228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
23822 16:34:06.767659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
23824 16:34:06.815905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
23825 16:34:06.816354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
23827 16:34:06.864431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
23828 16:34:06.864856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
23830 16:34:06.912979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
23831 16:34:06.913403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
23833 16:34:06.961229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
23834 16:34:06.961588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
23836 16:34:07.008863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
23837 16:34:07.009297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
23839 16:34:07.057141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
23840 16:34:07.057557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
23842 16:34:07.108523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
23843 16:34:07.109470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
23845 16:34:07.159378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
23846 16:34:07.159795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
23848 16:34:07.207337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
23849 16:34:07.207738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
23851 16:34:07.253548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
23853 16:34:07.254000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
23854 16:34:07.301539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
23856 16:34:07.302000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
23857 16:34:07.350457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
23859 16:34:07.350992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
23860 16:34:07.399698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
23861 16:34:07.400117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
23863 16:34:07.448284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
23865 16:34:07.448723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
23866 16:34:07.496696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
23867 16:34:07.497130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
23869 16:34:07.546938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
23870 16:34:07.547364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
23872 16:34:07.595107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
23873 16:34:07.595481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
23875 16:34:07.644271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
23877 16:34:07.644764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
23878 16:34:07.692889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
23879 16:34:07.693271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
23881 16:34:07.741712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
23882 16:34:07.742128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
23884 16:34:07.790350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
23886 16:34:07.790811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
23887 16:34:07.838392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
23889 16:34:07.838843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
23890 16:34:07.887199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
23891 16:34:07.887614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
23893 16:34:07.935824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
23894 16:34:07.936241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
23896 16:34:07.983755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
23897 16:34:07.984171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
23899 16:34:08.033216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
23900 16:34:08.033622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
23902 16:34:08.081256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
23903 16:34:08.081644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
23905 16:34:08.128665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
23906 16:34:08.129030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
23908 16:34:08.176314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
23910 16:34:08.176766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
23911 16:34:08.224320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
23912 16:34:08.224733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
23914 16:34:08.273448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
23915 16:34:08.273873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
23917 16:34:08.321575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
23918 16:34:08.322000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
23920 16:34:08.369774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
23922 16:34:08.370237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
23923 16:34:08.419882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
23924 16:34:08.420307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
23926 16:34:08.468163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
23927 16:34:08.468583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
23929 16:34:08.516442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
23931 16:34:08.516893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
23932 16:34:08.564444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
23933 16:34:08.564862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
23935 16:34:08.612718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
23936 16:34:08.613092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
23938 16:34:08.660487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
23939 16:34:08.660857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
23941 16:34:08.707887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
23942 16:34:08.708306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
23944 16:34:08.755652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
23945 16:34:08.756041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
23947 16:34:08.804889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
23948 16:34:08.805293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
23950 16:34:08.857633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
23951 16:34:08.858038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
23953 16:34:08.912384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
23954 16:34:08.912768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
23956 16:34:08.964021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
23957 16:34:08.964397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
23959 16:34:09.011740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
23960 16:34:09.012128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
23962 16:34:09.059597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
23963 16:34:09.060017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
23965 16:34:09.106988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
23966 16:34:09.107353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
23968 16:34:09.154982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
23969 16:34:09.155356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
23971 16:34:09.201342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
23972 16:34:09.201754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
23974 16:34:09.249054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
23975 16:34:09.249467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
23977 16:34:09.294060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
23978 16:34:09.294476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
23980 16:34:09.341067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
23981 16:34:09.341489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
23983 16:34:09.389630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
23984 16:34:09.390057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
23986 16:34:09.438266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
23988 16:34:09.438680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
23989 16:34:09.485064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
23990 16:34:09.485476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
23992 16:34:09.533487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
23993 16:34:09.533914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
23995 16:34:09.583210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
23996 16:34:09.583636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
23998 16:34:09.631753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
23999 16:34:09.632098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24001 16:34:09.679963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24002 16:34:09.680376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24004 16:34:09.727793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24005 16:34:09.728209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24007 16:34:09.775837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24008 16:34:09.776217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24010 16:34:09.823794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24011 16:34:09.824169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24013 16:34:09.871203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24014 16:34:09.871624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24016 16:34:09.918447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24018 16:34:09.918940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24019 16:34:09.967031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24020 16:34:09.967403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24022 16:34:10.014812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24023 16:34:10.015182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24025 16:34:10.063878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24027 16:34:10.064316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24028 16:34:10.111547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24029 16:34:10.111954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24031 16:34:10.158955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24032 16:34:10.159364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24034 16:34:10.208232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24035 16:34:10.208639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24037 16:34:10.256357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24038 16:34:10.256772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24040 16:34:10.307356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24041 16:34:10.307771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24043 16:34:10.354613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24045 16:34:10.355080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24046 16:34:10.402944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24047 16:34:10.403327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24049 16:34:10.450791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24050 16:34:10.451195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24052 16:34:10.501278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24053 16:34:10.501694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24055 16:34:10.551082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24056 16:34:10.551499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24058 16:34:10.597621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24059 16:34:10.598064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24061 16:34:10.644279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24062 16:34:10.644623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24064 16:34:10.691656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24065 16:34:10.692066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24067 16:34:10.738390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24069 16:34:10.738837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24070 16:34:10.785422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24071 16:34:10.785837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24073 16:34:10.833589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24074 16:34:10.834009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24076 16:34:10.881819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24078 16:34:10.882301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24079 16:34:10.929483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24081 16:34:10.929921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24082 16:34:10.977086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24083 16:34:10.977497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24085 16:34:11.024047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24086 16:34:11.024474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24088 16:34:11.071651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24089 16:34:11.072027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24091 16:34:11.119742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24092 16:34:11.120171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24094 16:34:11.166489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24096 16:34:11.166947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24097 16:34:11.213717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24098 16:34:11.214131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24100 16:34:11.261025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24101 16:34:11.261434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24103 16:34:11.309714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24105 16:34:11.310203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24106 16:34:11.357456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24107 16:34:11.357878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24109 16:34:11.404724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24110 16:34:11.405155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24112 16:34:11.453388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24113 16:34:11.453813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24115 16:34:11.501348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24116 16:34:11.501768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24118 16:34:11.572308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24119 16:34:11.572699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24121 16:34:11.619501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24122 16:34:11.619876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24124 16:34:11.666467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24126 16:34:11.666911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24127 16:34:11.713525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24128 16:34:11.713946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24130 16:34:11.760745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24131 16:34:11.761153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24133 16:34:11.807784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24134 16:34:11.808158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24136 16:34:11.855383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24138 16:34:11.855824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24139 16:34:11.902048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24140 16:34:11.902451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24142 16:34:11.949589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24143 16:34:11.950023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24145 16:34:11.996921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24146 16:34:11.997348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24148 16:34:12.044388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24149 16:34:12.044816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24151 16:34:12.091983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24152 16:34:12.092397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24154 16:34:12.139324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24155 16:34:12.139742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24157 16:34:12.185909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24158 16:34:12.186347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24160 16:34:12.232907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24161 16:34:12.233342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24163 16:34:12.280377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24164 16:34:12.280785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24166 16:34:12.327538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24168 16:34:12.327973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24169 16:34:12.374936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24170 16:34:12.375350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24172 16:34:12.421309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24174 16:34:12.421782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24175 16:34:12.468711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24176 16:34:12.469121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24178 16:34:12.515952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24179 16:34:12.516376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24181 16:34:12.563259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24183 16:34:12.563699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24184 16:34:12.610017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24185 16:34:12.610449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24187 16:34:12.658483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24189 16:34:12.659115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24190 16:34:12.705379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24191 16:34:12.705799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24193 16:34:12.752050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24194 16:34:12.752469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24196 16:34:12.799230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24197 16:34:12.799602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24199 16:34:12.845932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24200 16:34:12.846335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24202 16:34:12.895056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24203 16:34:12.895469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24205 16:34:12.942039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24207 16:34:12.942526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24208 16:34:12.989679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24210 16:34:12.990149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24211 16:34:13.038818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24212 16:34:13.039238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24214 16:34:13.085517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24215 16:34:13.085950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24217 16:34:13.132743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24219 16:34:13.133180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24220 16:34:13.179891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24221 16:34:13.180306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24223 16:34:13.226481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24225 16:34:13.226962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24226 16:34:13.273465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24227 16:34:13.273858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24229 16:34:13.320578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24230 16:34:13.320984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24232 16:34:13.368365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24233 16:34:13.368764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24235 16:34:13.415766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24236 16:34:13.416186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24238 16:34:13.463665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24240 16:34:13.464058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24241 16:34:13.511889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24242 16:34:13.512320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24244 16:34:13.559842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24245 16:34:13.560248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24247 16:34:13.605326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24249 16:34:13.605766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24250 16:34:13.653641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24251 16:34:13.654063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24253 16:34:13.701479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24254 16:34:13.701901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24256 16:34:13.749585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24257 16:34:13.750000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24259 16:34:13.797304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24260 16:34:13.797686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24262 16:34:13.845296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24263 16:34:13.845684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24265 16:34:13.894227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24267 16:34:13.894804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24268 16:34:13.943235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24269 16:34:13.943650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24271 16:34:13.990379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24273 16:34:13.990857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24274 16:34:14.038658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24276 16:34:14.039109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24277 16:34:14.087544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24278 16:34:14.087953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24280 16:34:14.135582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24281 16:34:14.136008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24283 16:34:14.184588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24284 16:34:14.185014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24286 16:34:14.232487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24287 16:34:14.232866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24289 16:34:14.280176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24290 16:34:14.280586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24292 16:34:14.326856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24293 16:34:14.327272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24295 16:34:14.373502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24296 16:34:14.373902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24298 16:34:14.423588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24299 16:34:14.424005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24301 16:34:14.470311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24303 16:34:14.470781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24304 16:34:14.519396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24305 16:34:14.519815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24307 16:34:14.566383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24309 16:34:14.566941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24310 16:34:14.613234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24311 16:34:14.613688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24313 16:34:14.660290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24314 16:34:14.660700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24316 16:34:14.707795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24317 16:34:14.708208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24319 16:34:14.755013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24321 16:34:14.755450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24322 16:34:14.801287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24323 16:34:14.801685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24325 16:34:14.847786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24326 16:34:14.848215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24328 16:34:14.895219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24329 16:34:14.895644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24331 16:34:14.941561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24332 16:34:14.941995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24334 16:34:14.988502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24335 16:34:14.988877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24337 16:34:15.036063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24339 16:34:15.036445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24340 16:34:15.083498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24342 16:34:15.083986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24343 16:34:15.130345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24345 16:34:15.130784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24346 16:34:15.177851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24347 16:34:15.178263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24349 16:34:15.225197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24350 16:34:15.225621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24352 16:34:15.271951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24354 16:34:15.272376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24355 16:34:15.318987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24356 16:34:15.319397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24358 16:34:15.365288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24359 16:34:15.365685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24361 16:34:15.413406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24362 16:34:15.413818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24364 16:34:15.460625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24365 16:34:15.461017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24367 16:34:15.508199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24368 16:34:15.508631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24370 16:34:15.555640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24371 16:34:15.556046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24373 16:34:15.603608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24375 16:34:15.604038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24376 16:34:15.652165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24378 16:34:15.652589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24379 16:34:15.701085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24380 16:34:15.701500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24382 16:34:15.747970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24383 16:34:15.748400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24385 16:34:15.795084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24386 16:34:15.795497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24388 16:34:15.841726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24389 16:34:15.842136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24391 16:34:15.889819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24392 16:34:15.890250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24394 16:34:15.939432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24395 16:34:15.939873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24397 16:34:15.986431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24399 16:34:15.986839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24400 16:34:16.033380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24401 16:34:16.033765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24403 16:34:16.080542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24404 16:34:16.080940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24406 16:34:16.128051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24407 16:34:16.128463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24409 16:34:16.175257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24410 16:34:16.175666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24412 16:34:16.222444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24414 16:34:16.222917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24415 16:34:16.269551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24416 16:34:16.269982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24418 16:34:16.317122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24419 16:34:16.317501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24421 16:34:16.364372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24422 16:34:16.364755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24424 16:34:16.411686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24425 16:34:16.412084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24427 16:34:16.459170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24428 16:34:16.459535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24430 16:34:16.507155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24431 16:34:16.507562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24433 16:34:16.555795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24434 16:34:16.556212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24436 16:34:16.604396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24437 16:34:16.604774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24439 16:34:16.673955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24440 16:34:16.674376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24442 16:34:16.721946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24443 16:34:16.722360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24445 16:34:16.769591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24447 16:34:16.770071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24448 16:34:16.816055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24449 16:34:16.816454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24451 16:34:16.864019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24452 16:34:16.864440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24454 16:34:16.912118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24455 16:34:16.912493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24457 16:34:16.960969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24458 16:34:16.961386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24460 16:34:17.009240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24461 16:34:17.009655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24463 16:34:17.065807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24464 16:34:17.066225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24466 16:34:17.105667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24467 16:34:17.106077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24469 16:34:17.153683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24470 16:34:17.154117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24472 16:34:17.202023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24473 16:34:17.202450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24475 16:34:17.252418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24476 16:34:17.252839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24478 16:34:17.300461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24480 16:34:17.300892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24481 16:34:17.348589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24482 16:34:17.349005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24484 16:34:17.396745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24485 16:34:17.397143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24487 16:34:17.444874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24489 16:34:17.445301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24490 16:34:17.494010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24491 16:34:17.494425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24493 16:34:17.541911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24494 16:34:17.542319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24496 16:34:17.590112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24498 16:34:17.590547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24499 16:34:17.638168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24501 16:34:17.639049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24502 16:34:17.687439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24504 16:34:17.687876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24505 16:34:17.734405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24507 16:34:17.734837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24508 16:34:17.781156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24510 16:34:17.781559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24511 16:34:17.827928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24512 16:34:17.828354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24514 16:34:17.875457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24515 16:34:17.875874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24517 16:34:17.922882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24518 16:34:17.923291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24520 16:34:17.970996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24521 16:34:17.971411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24523 16:34:18.019408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24524 16:34:18.019820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24526 16:34:18.067259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24527 16:34:18.067662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24529 16:34:18.115152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24530 16:34:18.115576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24532 16:34:18.163144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24533 16:34:18.163547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24535 16:34:18.210401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24537 16:34:18.210805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24538 16:34:18.257576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24539 16:34:18.257992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24541 16:34:18.306204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24543 16:34:18.306637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24544 16:34:18.354010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24545 16:34:18.354422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24547 16:34:18.402329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24548 16:34:18.402732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24550 16:34:18.449846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24552 16:34:18.450290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24553 16:34:18.498999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24554 16:34:18.499350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24556 16:34:18.545558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24557 16:34:18.545989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24559 16:34:18.593322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24561 16:34:18.593776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24562 16:34:18.640667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24563 16:34:18.641072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24565 16:34:18.688369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24566 16:34:18.688801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24568 16:34:18.737025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24570 16:34:18.737475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24571 16:34:18.786358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24573 16:34:18.786854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24574 16:34:18.835056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24575 16:34:18.835466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24577 16:34:18.884856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24578 16:34:18.885262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24580 16:34:18.933221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24581 16:34:18.933630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24583 16:34:18.980625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24584 16:34:18.981036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24586 16:34:19.030163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24587 16:34:19.030569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24589 16:34:19.076943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24590 16:34:19.077343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24592 16:34:19.125077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24593 16:34:19.125497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24595 16:34:19.173533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24596 16:34:19.173948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24598 16:34:19.221498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24599 16:34:19.221914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24601 16:34:19.269003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24603 16:34:19.269488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24604 16:34:19.318931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24605 16:34:19.319342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24607 16:34:19.365475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24608 16:34:19.365883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24610 16:34:19.413360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24611 16:34:19.413763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24613 16:34:19.462266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24615 16:34:19.462695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24616 16:34:19.511564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24617 16:34:19.511974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24619 16:34:19.559642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24620 16:34:19.560050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24622 16:34:19.607171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24623 16:34:19.607573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24625 16:34:19.655765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24626 16:34:19.656173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24628 16:34:19.703923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24629 16:34:19.704328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24631 16:34:19.753715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24633 16:34:19.754169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24634 16:34:19.801603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24635 16:34:19.801903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24637 16:34:19.849354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24638 16:34:19.849651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24640 16:34:19.896609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24641 16:34:19.896901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24643 16:34:19.943907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24644 16:34:19.944208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24646 16:34:19.991291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24647 16:34:19.991562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24649 16:34:20.037680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24650 16:34:20.037971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24652 16:34:20.085171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24653 16:34:20.085463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24655 16:34:20.132310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24656 16:34:20.132598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24658 16:34:20.180026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24659 16:34:20.180294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24661 16:34:20.227458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24662 16:34:20.227747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24664 16:34:20.274877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24666 16:34:20.275174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24667 16:34:20.323630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24668 16:34:20.323919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24670 16:34:20.371886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24671 16:34:20.372180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24673 16:34:20.418865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24674 16:34:20.419275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24676 16:34:20.466542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24678 16:34:20.466997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24679 16:34:20.514985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24680 16:34:20.515402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24682 16:34:20.564012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24683 16:34:20.564423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24685 16:34:20.611712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24686 16:34:20.612121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24688 16:34:20.659277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24689 16:34:20.659686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24691 16:34:20.706462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24693 16:34:20.706937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24694 16:34:20.755755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24695 16:34:20.756164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24697 16:34:20.803283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24698 16:34:20.803698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24700 16:34:20.851181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24701 16:34:20.851594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24703 16:34:20.899106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24704 16:34:20.899489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24706 16:34:20.946193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24708 16:34:20.946657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24709 16:34:20.993955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24711 16:34:20.994390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24712 16:34:21.041527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24713 16:34:21.041937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24715 16:34:21.089380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24716 16:34:21.089763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24718 16:34:21.137377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24719 16:34:21.137768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
24721 16:34:21.185606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
24722 16:34:21.186036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
24724 16:34:21.233845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
24725 16:34:21.234262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
24727 16:34:21.281576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
24728 16:34:21.282002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
24730 16:34:21.330131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
24731 16:34:21.330538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
24733 16:34:21.377625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
24734 16:34:21.378063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
24736 16:34:21.425497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
24737 16:34:21.425908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
24739 16:34:21.473713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
24740 16:34:21.474121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
24742 16:34:21.521537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
24743 16:34:21.521952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
24745 16:34:21.571537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
24746 16:34:21.571955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
24748 16:34:21.619413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
24749 16:34:21.619836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
24751 16:34:21.666544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
24753 16:34:21.666983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
24754 16:34:21.712865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
24755 16:34:21.713281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
24757 16:34:21.783451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
24758 16:34:21.783889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
24760 16:34:21.832474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
24761 16:34:21.832857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
24763 16:34:21.881512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
24764 16:34:21.881936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
24766 16:34:21.930352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
24768 16:34:21.930856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
24769 16:34:21.977713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
24770 16:34:21.978132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
24772 16:34:22.025408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
24773 16:34:22.025812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
24775 16:34:22.073583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
24776 16:34:22.073993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
24778 16:34:22.122115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
24779 16:34:22.122538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
24781 16:34:22.170533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
24783 16:34:22.170982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
24784 16:34:22.218182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
24786 16:34:22.218679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
24787 16:34:22.266847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
24788 16:34:22.267265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
24790 16:34:22.314994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
24792 16:34:22.315416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
24793 16:34:22.363274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
24794 16:34:22.363706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
24796 16:34:22.411682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
24797 16:34:22.412059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
24799 16:34:22.459534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
24800 16:34:22.459946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
24802 16:34:22.507791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
24804 16:34:22.508251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
24805 16:34:22.555467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
24807 16:34:22.555949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
24808 16:34:22.603316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
24809 16:34:22.603741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
24811 16:34:22.659948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
24812 16:34:22.660381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
24814 16:34:22.700077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
24815 16:34:22.700481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
24817 16:34:22.748025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
24818 16:34:22.748431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
24820 16:34:22.793430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
24822 16:34:22.793857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
24823 16:34:22.841118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
24824 16:34:22.841529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
24826 16:34:22.889380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
24827 16:34:22.889799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
24829 16:34:22.938920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
24830 16:34:22.939320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
24832 16:34:22.988156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
24833 16:34:22.988583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
24835 16:34:23.035767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
24836 16:34:23.036050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
24838 16:34:23.083698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
24839 16:34:23.084029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
24841 16:34:23.125479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
24842 16:34:23.125887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
24844 16:34:23.169731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
24845 16:34:23.170159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
24847 16:34:23.204353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
24848 16:34:23.204731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
24850 16:34:23.248490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
24851 16:34:23.248845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
24853 16:34:23.281602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
24854 16:34:23.281988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
24856 16:34:23.323299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
24857 16:34:23.323730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
24859 16:34:23.368356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
24860 16:34:23.368734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
24862 16:34:23.406482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
24864 16:34:23.406920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
24865 16:34:23.441717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
24866 16:34:23.442114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
24868 16:34:23.487254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
24869 16:34:23.487630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
24871 16:34:23.531140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
24872 16:34:23.531536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
24874 16:34:23.567961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
24875 16:34:23.568366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
24877 16:34:23.606876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
24878 16:34:23.607286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
24880 16:34:23.639753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
24881 16:34:23.640143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
24883 16:34:23.672694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
24884 16:34:23.673123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
24886 16:34:23.705734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
24887 16:34:23.706156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
24889 16:34:23.743826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
24890 16:34:23.744244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
24892 16:34:23.787191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
24894 16:34:23.787625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
24895 16:34:23.830485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
24897 16:34:23.830927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
24898 16:34:23.875242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
24899 16:34:23.875655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
24901 16:34:23.919333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
24902 16:34:23.919745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
24904 16:34:23.970488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
24906 16:34:23.971194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
24907 16:34:24.017524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
24908 16:34:24.017919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
24910 16:34:24.052282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
24911 16:34:24.052661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
24913 16:34:24.085701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
24914 16:34:24.086070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
24916 16:34:24.118782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
24917 16:34:24.119176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
24919 16:34:24.150502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
24920 16:34:24.150784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
24922 16:34:24.183066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
24923 16:34:24.183525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
24925 16:34:24.217992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
24927 16:34:24.218752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
24928 16:34:24.252456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
24929 16:34:24.252989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
24931 16:34:24.287462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
24932 16:34:24.287863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
24934 16:34:24.320520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
24935 16:34:24.320977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
24937 16:34:24.352818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
24938 16:34:24.353290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
24940 16:34:24.384493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
24941 16:34:24.384966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
24943 16:34:24.416640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
24944 16:34:24.417083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
24946 16:34:24.448515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
24947 16:34:24.448976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
24949 16:34:24.480811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
24951 16:34:24.481258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
24952 16:34:24.514778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
24953 16:34:24.515203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
24955 16:34:24.549722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
24956 16:34:24.550154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
24958 16:34:24.587649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
24960 16:34:24.588083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
24961 16:34:24.619772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
24962 16:34:24.620052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
24964 16:34:24.651040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
24965 16:34:24.651323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
24967 16:34:24.681889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
24968 16:34:24.682166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
24970 16:34:24.713688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
24971 16:34:24.713967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
24973 16:34:24.745624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
24975 16:34:24.745908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
24976 16:34:24.777101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
24977 16:34:24.777455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
24979 16:34:24.810741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
24980 16:34:24.811116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
24982 16:34:24.844792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
24984 16:34:24.845311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
24985 16:34:24.877498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
24986 16:34:24.877992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
24988 16:34:24.909665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
24989 16:34:24.910044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
24991 16:34:24.941577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
24992 16:34:24.941930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
24994 16:34:24.972505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
24995 16:34:24.972783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
24997 16:34:25.003690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
24998 16:34:25.004044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25000 16:34:25.034928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25001 16:34:25.035280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25003 16:34:25.066195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25005 16:34:25.066643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25006 16:34:25.098961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25007 16:34:25.099330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25009 16:34:25.132766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25011 16:34:25.133195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25012 16:34:25.166266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25014 16:34:25.166779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25015 16:34:25.199978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25016 16:34:25.200408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25018 16:34:25.235696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25019 16:34:25.235977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25021 16:34:25.270438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25022 16:34:25.270719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25024 16:34:25.302132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25026 16:34:25.302412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25027 16:34:25.334178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25029 16:34:25.334453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25030 16:34:25.365827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25031 16:34:25.366179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25033 16:34:25.397214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25034 16:34:25.397491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25036 16:34:25.428537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25037 16:34:25.428814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25039 16:34:25.460003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25040 16:34:25.460268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25042 16:34:25.491260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25043 16:34:25.491524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25045 16:34:25.523336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25046 16:34:25.523886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25048 16:34:25.555252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25049 16:34:25.555793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25051 16:34:25.587434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25053 16:34:25.587850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25054 16:34:25.619175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25055 16:34:25.619458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25057 16:34:25.651330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25059 16:34:25.651817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25060 16:34:25.683608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25061 16:34:25.684081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25063 16:34:25.715265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25064 16:34:25.715689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25066 16:34:25.747226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25067 16:34:25.747592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25069 16:34:25.778708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25070 16:34:25.779084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25072 16:34:25.811298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25073 16:34:25.811716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25075 16:34:25.843046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25076 16:34:25.843504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25078 16:34:25.874968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25080 16:34:25.875599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25081 16:34:25.906049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25082 16:34:25.906497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25084 16:34:25.937407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25085 16:34:25.937881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25087 16:34:25.969129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25089 16:34:25.969574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25090 16:34:26.000706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25092 16:34:26.001133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25093 16:34:26.031935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25095 16:34:26.032412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25096 16:34:26.063120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25097 16:34:26.063470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25099 16:34:26.094559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25100 16:34:26.094913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25102 16:34:26.125842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25103 16:34:26.126212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25105 16:34:26.157206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25106 16:34:26.157573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25108 16:34:26.188352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25109 16:34:26.188634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25111 16:34:26.219445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25112 16:34:26.219803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25114 16:34:26.250305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25116 16:34:26.250738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25117 16:34:26.281554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25118 16:34:26.281884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25120 16:34:26.312997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25121 16:34:26.313346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25123 16:34:26.344069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25124 16:34:26.344420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25126 16:34:26.375787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25127 16:34:26.376173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25129 16:34:26.410286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25131 16:34:26.410753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25132 16:34:26.442185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25134 16:34:26.442461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25135 16:34:26.473897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25136 16:34:26.474172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25138 16:34:26.505600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25139 16:34:26.505867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25141 16:34:26.536568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25142 16:34:26.536828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25144 16:34:26.567507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25145 16:34:26.567786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25147 16:34:26.601995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25148 16:34:26.602393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25150 16:34:26.633785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25152 16:34:26.634221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25153 16:34:26.664875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25154 16:34:26.665241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25156 16:34:26.697060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25158 16:34:26.697362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25159 16:34:26.728332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25160 16:34:26.728604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25162 16:34:26.761111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25163 16:34:26.761446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25165 16:34:26.795746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25166 16:34:26.796064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25168 16:34:26.827358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25170 16:34:26.827800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25171 16:34:26.859404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25172 16:34:26.859878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25174 16:34:26.907020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25175 16:34:26.907392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25177 16:34:26.938861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25178 16:34:26.939207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25180 16:34:26.970505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25182 16:34:26.971039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25183 16:34:27.005756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25184 16:34:27.006121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25186 16:34:27.036808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25187 16:34:27.037082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25189 16:34:27.067563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25190 16:34:27.067837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25192 16:34:27.099829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25194 16:34:27.100395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25195 16:34:27.131823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25196 16:34:27.132232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25198 16:34:27.163461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25199 16:34:27.163894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25201 16:34:27.195261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25202 16:34:27.195608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25204 16:34:27.227013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25205 16:34:27.227370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25207 16:34:27.258174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25209 16:34:27.258601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25210 16:34:27.289241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25211 16:34:27.289591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25213 16:34:27.320676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25214 16:34:27.321005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25216 16:34:27.351569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25217 16:34:27.351845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25219 16:34:27.382984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25220 16:34:27.383257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25222 16:34:27.414236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25224 16:34:27.414511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25225 16:34:27.447485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25227 16:34:27.448126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25228 16:34:27.479297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25229 16:34:27.479807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25231 16:34:27.511328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25232 16:34:27.511723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25234 16:34:27.543518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25236 16:34:27.544075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25237 16:34:27.575328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25238 16:34:27.575728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25240 16:34:27.607431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25241 16:34:27.607908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25243 16:34:27.640184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25245 16:34:27.640738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25246 16:34:27.671705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25247 16:34:27.672184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25249 16:34:27.704226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25251 16:34:27.704774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25252 16:34:27.739269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25253 16:34:27.739730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25255 16:34:27.771178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25256 16:34:27.771619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25258 16:34:27.803365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25259 16:34:27.803778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25261 16:34:27.835183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25262 16:34:27.835590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25264 16:34:27.867412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25265 16:34:27.867869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25267 16:34:27.899905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25269 16:34:27.900526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25270 16:34:27.932316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25272 16:34:27.932936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25273 16:34:27.963825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25274 16:34:27.964287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25276 16:34:27.995369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25278 16:34:27.995988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25279 16:34:28.027195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25280 16:34:28.027658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25282 16:34:28.058973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25283 16:34:28.059439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25285 16:34:28.092154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25286 16:34:28.092631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25288 16:34:28.123968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25289 16:34:28.124430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25291 16:34:28.156120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25292 16:34:28.156592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25294 16:34:28.187345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25295 16:34:28.187825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25297 16:34:28.219281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25298 16:34:28.219646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25300 16:34:28.250434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25302 16:34:28.250898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25303 16:34:28.283553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25304 16:34:28.283925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25306 16:34:28.315698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25307 16:34:28.316147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25309 16:34:28.348535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25310 16:34:28.349014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25312 16:34:28.381104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25313 16:34:28.381655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25315 16:34:28.414533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25316 16:34:28.414982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25318 16:34:28.447237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25320 16:34:28.447869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25321 16:34:28.479552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25322 16:34:28.480014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25324 16:34:28.511781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25325 16:34:28.512233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25327 16:34:28.543515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25328 16:34:28.543964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25330 16:34:28.575154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25331 16:34:28.575613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25333 16:34:28.606740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25334 16:34:28.607191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25336 16:34:28.637997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25338 16:34:28.638602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25339 16:34:28.669942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25340 16:34:28.670397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25342 16:34:28.701681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25343 16:34:28.702135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25345 16:34:28.732826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25347 16:34:28.733438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25348 16:34:28.764900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25350 16:34:28.765487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25351 16:34:28.801056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25352 16:34:28.801519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25354 16:34:28.844736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25356 16:34:28.845380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25357 16:34:28.887544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25359 16:34:28.888137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25360 16:34:28.927620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25361 16:34:28.927899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25363 16:34:28.963343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25364 16:34:28.963692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25366 16:34:28.995847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25367 16:34:28.996194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25369 16:34:29.029219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25370 16:34:29.029569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25372 16:34:29.060734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25373 16:34:29.061082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25375 16:34:29.091612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25376 16:34:29.091958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25378 16:34:29.123051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25379 16:34:29.123512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25381 16:34:29.154496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25382 16:34:29.154956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25384 16:34:29.186044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25385 16:34:29.186508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25387 16:34:29.217923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25388 16:34:29.218394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25390 16:34:29.249304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25391 16:34:29.249753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25393 16:34:29.281227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25394 16:34:29.281690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25396 16:34:29.312878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25397 16:34:29.313353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25399 16:34:29.343742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25400 16:34:29.344170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25402 16:34:29.375379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25404 16:34:29.375989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25405 16:34:29.409720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25406 16:34:29.410216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25408 16:34:29.441415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25409 16:34:29.441892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25411 16:34:29.473992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25413 16:34:29.474559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25414 16:34:29.505718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25415 16:34:29.506195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25417 16:34:29.538612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25418 16:34:29.539080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25420 16:34:29.570024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25421 16:34:29.570465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25423 16:34:29.601463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25424 16:34:29.601836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25426 16:34:29.632652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25428 16:34:29.633168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25429 16:34:29.663435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25430 16:34:29.663786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25432 16:34:29.694644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25433 16:34:29.694921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25435 16:34:29.726914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25436 16:34:29.727196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25438 16:34:29.757793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25439 16:34:29.758170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25441 16:34:29.789210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25442 16:34:29.789688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25444 16:34:29.821104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25445 16:34:29.821554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25447 16:34:29.852673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25448 16:34:29.853118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25450 16:34:29.884414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25451 16:34:29.884860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25453 16:34:29.915661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25454 16:34:29.916108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25456 16:34:29.946951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25457 16:34:29.947390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25459 16:34:29.977949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25460 16:34:29.978386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25462 16:34:30.009696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25463 16:34:30.010175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25465 16:34:30.041276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25466 16:34:30.041755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25468 16:34:30.072953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25469 16:34:30.073383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25471 16:34:30.103959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25472 16:34:30.104407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25474 16:34:30.135325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25475 16:34:30.135773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25477 16:34:30.166603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25478 16:34:30.167049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25480 16:34:30.197779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25481 16:34:30.198237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25483 16:34:30.229084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25484 16:34:30.229536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25486 16:34:30.263025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25487 16:34:30.263570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25489 16:34:30.297155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25490 16:34:30.297622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25492 16:34:30.329243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25493 16:34:30.329696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25495 16:34:30.360514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25496 16:34:30.360945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25498 16:34:30.391981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25499 16:34:30.392435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25501 16:34:30.423280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25502 16:34:30.423721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25504 16:34:30.454636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25505 16:34:30.455074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25507 16:34:30.485719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25508 16:34:30.486161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25510 16:34:30.517004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25511 16:34:30.517431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25513 16:34:30.551237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25515 16:34:30.551822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25516 16:34:30.583243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25517 16:34:30.583686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25519 16:34:30.615273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25520 16:34:30.615714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25522 16:34:30.649808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25524 16:34:30.650392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25525 16:34:30.684134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25526 16:34:30.684626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25528 16:34:30.716995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25529 16:34:30.717446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25531 16:34:30.748780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25532 16:34:30.749247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25534 16:34:30.781424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25535 16:34:30.781872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25537 16:34:30.813538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25539 16:34:30.814045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25540 16:34:30.845197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25541 16:34:30.845591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25543 16:34:30.877170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25544 16:34:30.877591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25546 16:34:30.910312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25548 16:34:30.910836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25549 16:34:30.942519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25550 16:34:30.942945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25552 16:34:30.974994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25554 16:34:30.975515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25555 16:34:31.007341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25556 16:34:31.007766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25558 16:34:31.039831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25559 16:34:31.040276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25561 16:34:31.072746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25563 16:34:31.073282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25564 16:34:31.104522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25565 16:34:31.104958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25567 16:34:31.135850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25568 16:34:31.136310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25570 16:34:31.167267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25571 16:34:31.167737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25573 16:34:31.198871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25574 16:34:31.199328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25576 16:34:31.230587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25578 16:34:31.231200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25579 16:34:31.261879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25580 16:34:31.262337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25582 16:34:31.293547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25584 16:34:31.294172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25585 16:34:31.325218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25586 16:34:31.325699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25588 16:34:31.356400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25589 16:34:31.356858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25591 16:34:31.387689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25592 16:34:31.388138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25594 16:34:31.418996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25595 16:34:31.419456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25597 16:34:31.450743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25598 16:34:31.451199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25600 16:34:31.482005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25601 16:34:31.482476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25603 16:34:31.513564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25604 16:34:31.514032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25606 16:34:31.545282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25607 16:34:31.545748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25609 16:34:31.577097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25610 16:34:31.577572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25612 16:34:31.608260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25613 16:34:31.608720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25615 16:34:31.639404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25616 16:34:31.639859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25618 16:34:31.671169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25619 16:34:31.671624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25621 16:34:31.702519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25622 16:34:31.702976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25624 16:34:31.733628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25625 16:34:31.734113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25627 16:34:31.765330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25628 16:34:31.765793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25630 16:34:31.796840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25631 16:34:31.797313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25633 16:34:31.828118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25634 16:34:31.828572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25636 16:34:31.859359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25637 16:34:31.859811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25639 16:34:31.891414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25640 16:34:31.891880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25642 16:34:31.923523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25643 16:34:31.923982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25645 16:34:31.955024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25646 16:34:31.955483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25648 16:34:31.985927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25649 16:34:31.986383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25651 16:34:32.035923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25652 16:34:32.036402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25654 16:34:32.067879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25655 16:34:32.068350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25657 16:34:32.099977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25658 16:34:32.100439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25660 16:34:32.131919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25661 16:34:32.132372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25663 16:34:32.163918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25665 16:34:32.164446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25666 16:34:32.195908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25667 16:34:32.196350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25669 16:34:32.227898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25670 16:34:32.228350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25672 16:34:32.259406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25673 16:34:32.259844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25675 16:34:32.291676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25676 16:34:32.292133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25678 16:34:32.323860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25679 16:34:32.324310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25681 16:34:32.356347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25682 16:34:32.356790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25684 16:34:32.395089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25686 16:34:32.395644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25687 16:34:32.428208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25688 16:34:32.428603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25690 16:34:32.460293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25691 16:34:32.460746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25693 16:34:32.491856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25694 16:34:32.492321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25696 16:34:32.523346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25697 16:34:32.523818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25699 16:34:32.554868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25700 16:34:32.555328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25702 16:34:32.587054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25703 16:34:32.587519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25705 16:34:32.619964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25706 16:34:32.620425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25708 16:34:32.651682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25709 16:34:32.652152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25711 16:34:32.683836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25712 16:34:32.684347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25714 16:34:32.715487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25715 16:34:32.715928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25717 16:34:32.747832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25718 16:34:32.748281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
25720 16:34:32.779305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
25721 16:34:32.779746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
25723 16:34:32.811620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
25724 16:34:32.812021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
25726 16:34:32.843471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
25727 16:34:32.843869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
25729 16:34:32.875148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
25731 16:34:32.875575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
25732 16:34:32.906949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
25733 16:34:32.907392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
25735 16:34:32.939104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
25736 16:34:32.939502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
25738 16:34:32.970781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
25739 16:34:32.971058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
25741 16:34:33.001785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
25742 16:34:33.002154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
25744 16:34:33.032839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
25746 16:34:33.033296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
25747 16:34:33.063724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
25748 16:34:33.064085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
25750 16:34:33.095090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
25751 16:34:33.095449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
25753 16:34:33.126028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
25754 16:34:33.126386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
25756 16:34:33.157072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
25757 16:34:33.157434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
25759 16:34:33.187852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
25760 16:34:33.188214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
25762 16:34:33.218917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
25763 16:34:33.219275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
25765 16:34:33.249665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
25766 16:34:33.250024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
25768 16:34:33.280232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
25769 16:34:33.280591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
25771 16:34:33.311144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
25772 16:34:33.311508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
25774 16:34:33.341851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
25775 16:34:33.342211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
25777 16:34:33.373331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
25778 16:34:33.373687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
25780 16:34:33.404314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
25781 16:34:33.404589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
25783 16:34:33.435280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
25784 16:34:33.435570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
25786 16:34:33.466431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
25787 16:34:33.466794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
25789 16:34:33.497114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
25790 16:34:33.497487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
25792 16:34:33.528125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
25793 16:34:33.528484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
25795 16:34:33.559211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
25796 16:34:33.559576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
25798 16:34:33.590213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
25800 16:34:33.590739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
25801 16:34:33.622950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
25802 16:34:33.623322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
25804 16:34:33.654872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
25805 16:34:33.655247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
25807 16:34:33.687083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
25808 16:34:33.687462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
25810 16:34:33.718650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
25811 16:34:33.719026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
25813 16:34:33.750310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
25815 16:34:33.750833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
25816 16:34:33.782236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
25818 16:34:33.782760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
25819 16:34:33.815002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
25820 16:34:33.815376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
25822 16:34:33.846992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
25823 16:34:33.847361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
25825 16:34:33.878812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
25826 16:34:33.879184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
25828 16:34:33.910591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
25829 16:34:33.910968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
25831 16:34:33.942352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
25833 16:34:33.942812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
25834 16:34:33.975271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
25835 16:34:33.975632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
25837 16:34:34.006247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
25839 16:34:34.006707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
25840 16:34:34.037841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
25841 16:34:34.038198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
25843 16:34:34.069616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
25844 16:34:34.069984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
25846 16:34:34.105001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
25847 16:34:34.105407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
25849 16:34:34.136473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
25850 16:34:34.136831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
25852 16:34:34.168234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
25853 16:34:34.168594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
25855 16:34:34.200083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
25856 16:34:34.200445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
25858 16:34:34.231736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
25859 16:34:34.232101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
25861 16:34:34.263123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
25862 16:34:34.263489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
25864 16:34:34.295634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
25865 16:34:34.295980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
25867 16:34:34.327492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
25868 16:34:34.327853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
25870 16:34:34.359263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
25871 16:34:34.359623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
25873 16:34:34.391637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
25874 16:34:34.391983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
25876 16:34:34.423351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
25877 16:34:34.423703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
25879 16:34:34.455165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
25880 16:34:34.455443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
25882 16:34:34.487161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
25883 16:34:34.487520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
25885 16:34:34.519224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
25886 16:34:34.519568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
25888 16:34:34.550855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
25889 16:34:34.551214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
25891 16:34:34.581919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
25892 16:34:34.582367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
25894 16:34:34.613994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
25895 16:34:34.614449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
25897 16:34:34.646527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
25898 16:34:34.646977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
25900 16:34:34.677870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
25901 16:34:34.678325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
25903 16:34:34.709764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
25904 16:34:34.710234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
25906 16:34:34.741055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
25907 16:34:34.741484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
25909 16:34:34.772178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
25910 16:34:34.772618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
25912 16:34:34.803388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
25913 16:34:34.803912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
25915 16:34:34.836090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
25917 16:34:34.836634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
25918 16:34:34.867491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
25919 16:34:34.867927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
25921 16:34:34.899315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
25923 16:34:34.899846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
25924 16:34:34.930782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
25925 16:34:34.931245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
25927 16:34:34.963102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
25929 16:34:34.963633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
25930 16:34:34.995306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
25931 16:34:34.995783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
25933 16:34:35.026222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
25935 16:34:35.026501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
25936 16:34:35.058580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
25937 16:34:35.058937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
25939 16:34:35.090511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
25940 16:34:35.090854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
25942 16:34:35.123624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
25944 16:34:35.124188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
25945 16:34:35.155788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
25946 16:34:35.156257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
25948 16:34:35.188322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
25949 16:34:35.188786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
25951 16:34:35.220457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
25952 16:34:35.220857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
25954 16:34:35.252972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
25955 16:34:35.253417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
25957 16:34:35.284882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
25958 16:34:35.285274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
25960 16:34:35.317679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
25962 16:34:35.318136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
25963 16:34:35.350025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
25964 16:34:35.350441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
25966 16:34:35.383238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
25967 16:34:35.383644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
25969 16:34:35.415546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
25970 16:34:35.415975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
25972 16:34:35.447804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
25973 16:34:35.448206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
25975 16:34:35.480625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
25976 16:34:35.481047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
25978 16:34:35.513238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
25979 16:34:35.513638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
25981 16:34:35.545239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
25983 16:34:35.545680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
25984 16:34:35.578701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
25985 16:34:35.579165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
25987 16:34:35.610515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
25988 16:34:35.610970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
25990 16:34:35.642477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
25992 16:34:35.643051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
25993 16:34:35.675459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
25994 16:34:35.675927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
25996 16:34:35.707577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
25997 16:34:35.708046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
25999 16:34:35.740472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26000 16:34:35.740924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26002 16:34:35.773596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26003 16:34:35.774092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26005 16:34:35.805677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26007 16:34:35.806248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26008 16:34:35.837291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26009 16:34:35.837692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26011 16:34:35.869847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26012 16:34:35.870265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26014 16:34:35.902661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26016 16:34:35.903087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26017 16:34:35.934264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26019 16:34:35.934693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26020 16:34:35.966692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26022 16:34:35.967129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26023 16:34:35.998980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26024 16:34:35.999369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26026 16:34:36.031745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26027 16:34:36.032145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26029 16:34:36.063276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26031 16:34:36.063707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26032 16:34:36.095105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26034 16:34:36.095663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26035 16:34:36.126422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26037 16:34:36.126871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26038 16:34:36.158593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26039 16:34:36.158959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26041 16:34:36.189983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26042 16:34:36.190340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26044 16:34:36.221327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26045 16:34:36.221684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26047 16:34:36.252668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26048 16:34:36.253027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26050 16:34:36.283901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26051 16:34:36.284261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26053 16:34:36.316468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26054 16:34:36.316857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26056 16:34:36.347789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26057 16:34:36.348151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26059 16:34:36.379232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26060 16:34:36.379591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26062 16:34:36.410686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26063 16:34:36.411047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26065 16:34:36.442489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26066 16:34:36.442851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26068 16:34:36.473765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26069 16:34:36.474125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26071 16:34:36.505189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26072 16:34:36.505548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26074 16:34:36.536107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26075 16:34:36.536467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26077 16:34:36.567224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26079 16:34:36.567838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26080 16:34:36.599281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26081 16:34:36.599752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26083 16:34:36.630664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26084 16:34:36.631125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26086 16:34:36.662747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26087 16:34:36.663212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26089 16:34:36.694988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26091 16:34:36.695477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26092 16:34:36.726527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26093 16:34:36.726894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26095 16:34:36.757726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26096 16:34:36.758205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26098 16:34:36.792296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26100 16:34:36.792840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26101 16:34:36.824178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26102 16:34:36.824633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26104 16:34:36.855428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26105 16:34:36.855871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26107 16:34:36.888025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26108 16:34:36.888478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26110 16:34:36.919688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26111 16:34:36.920131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26113 16:34:36.951229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26114 16:34:36.951683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26116 16:34:36.983087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26117 16:34:36.983550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26119 16:34:37.014893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26120 16:34:37.015347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26122 16:34:37.046952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26123 16:34:37.047408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26125 16:34:37.077975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26126 16:34:37.078427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26128 16:34:37.123844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26129 16:34:37.124328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26131 16:34:37.161629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26132 16:34:37.162066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26134 16:34:37.193791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26135 16:34:37.194216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26137 16:34:37.225540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26138 16:34:37.225970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26140 16:34:37.256674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26141 16:34:37.257075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26143 16:34:37.288160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26144 16:34:37.288567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26146 16:34:37.320013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26147 16:34:37.320430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26149 16:34:37.351517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26150 16:34:37.351927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26152 16:34:37.382935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26153 16:34:37.383344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26155 16:34:37.414289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26157 16:34:37.414721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26158 16:34:37.445915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26159 16:34:37.446334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26161 16:34:37.477403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26162 16:34:37.477819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26164 16:34:37.508756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26165 16:34:37.509171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26167 16:34:37.540326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26168 16:34:37.540735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26170 16:34:37.571646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26171 16:34:37.572057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26173 16:34:37.603201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26174 16:34:37.603612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26176 16:34:37.634746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26177 16:34:37.635152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26179 16:34:37.666479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26180 16:34:37.666893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26182 16:34:37.698791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26183 16:34:37.699188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26185 16:34:37.731446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26186 16:34:37.731867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26188 16:34:37.763098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26189 16:34:37.763536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26191 16:34:37.794990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26192 16:34:37.795438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26194 16:34:37.826248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26196 16:34:37.826814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26197 16:34:37.857791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26198 16:34:37.858221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26200 16:34:37.888938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26201 16:34:37.889360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26203 16:34:37.921320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26204 16:34:37.921777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26206 16:34:37.953077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26207 16:34:37.953527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26209 16:34:37.984035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26210 16:34:37.984452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26212 16:34:38.016822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26214 16:34:38.017365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26215 16:34:38.048886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26216 16:34:38.049353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26218 16:34:38.081975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26219 16:34:38.082442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26221 16:34:38.113888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26223 16:34:38.114434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26224 16:34:38.145729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26225 16:34:38.146180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26227 16:34:38.177247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26228 16:34:38.177672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26230 16:34:38.208804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26231 16:34:38.209268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26233 16:34:38.240622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26235 16:34:38.241241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26236 16:34:38.272133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26237 16:34:38.272600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26239 16:34:38.304128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26240 16:34:38.304572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26242 16:34:38.335670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26243 16:34:38.336130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26245 16:34:38.367190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26246 16:34:38.367579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26248 16:34:38.398626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26249 16:34:38.398985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26251 16:34:38.429765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26252 16:34:38.430124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26254 16:34:38.460886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26255 16:34:38.461244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26257 16:34:38.492656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26258 16:34:38.493015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26260 16:34:38.523881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26261 16:34:38.524243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26263 16:34:38.555298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26264 16:34:38.555656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26266 16:34:38.586537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26267 16:34:38.586898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26269 16:34:38.617253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26270 16:34:38.617613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26272 16:34:38.648099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26273 16:34:38.648460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26275 16:34:38.679377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26276 16:34:38.679734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26278 16:34:38.710918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26279 16:34:38.711280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26281 16:34:38.742781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26282 16:34:38.743142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26284 16:34:38.773826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26285 16:34:38.774192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26287 16:34:38.804810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26288 16:34:38.805173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26290 16:34:38.835553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26291 16:34:38.835923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26293 16:34:38.866755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26294 16:34:38.867123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26296 16:34:38.897591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26297 16:34:38.897970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26299 16:34:38.929094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26300 16:34:38.929461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26302 16:34:38.960306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26303 16:34:38.960678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26305 16:34:38.991294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26306 16:34:38.991662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26308 16:34:39.021983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26309 16:34:39.022353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26311 16:34:39.053918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26312 16:34:39.054390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26314 16:34:39.086954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26316 16:34:39.087418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26317 16:34:39.118869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26319 16:34:39.119318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26320 16:34:39.150647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26321 16:34:39.151016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26323 16:34:39.182688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26324 16:34:39.183131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26326 16:34:39.215071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26327 16:34:39.215534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26329 16:34:39.247326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26330 16:34:39.247771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26332 16:34:39.279386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26333 16:34:39.279830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26335 16:34:39.311355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26336 16:34:39.311802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26338 16:34:39.343442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26339 16:34:39.343830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26341 16:34:39.375814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26342 16:34:39.376207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26344 16:34:39.408027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26346 16:34:39.408456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26347 16:34:39.440199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26348 16:34:39.440619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26350 16:34:39.472547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26351 16:34:39.472991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26353 16:34:39.506830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26355 16:34:39.507366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26356 16:34:39.539869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26358 16:34:39.540334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26359 16:34:39.571765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26360 16:34:39.572172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26362 16:34:39.604728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26363 16:34:39.605192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26365 16:34:39.637924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26367 16:34:39.638325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26368 16:34:39.670970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26370 16:34:39.671275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26371 16:34:39.702862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26372 16:34:39.703126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26374 16:34:39.735007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26376 16:34:39.735468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26377 16:34:39.767318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26378 16:34:39.767679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26380 16:34:39.798521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26381 16:34:39.798869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26383 16:34:39.829962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26384 16:34:39.830313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26386 16:34:39.862965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26388 16:34:39.863403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26389 16:34:39.894907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26391 16:34:39.895309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26392 16:34:39.926696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26394 16:34:39.926977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26395 16:34:39.958849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26396 16:34:39.959200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26398 16:34:39.990584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26399 16:34:39.990960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26401 16:34:40.021816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26402 16:34:40.022182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26404 16:34:40.053689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26405 16:34:40.054060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26407 16:34:40.085789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26408 16:34:40.086202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26410 16:34:40.118793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26411 16:34:40.119244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26413 16:34:40.150557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26414 16:34:40.151007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26416 16:34:40.182415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26418 16:34:40.182955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26419 16:34:40.214445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26421 16:34:40.214870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26422 16:34:40.246325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26424 16:34:40.246605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26425 16:34:40.277684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26426 16:34:40.277961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26428 16:34:40.309176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26429 16:34:40.309567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26431 16:34:40.341113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26432 16:34:40.341516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26434 16:34:40.373001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26435 16:34:40.373452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26437 16:34:40.405269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26438 16:34:40.405701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26440 16:34:40.438457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26442 16:34:40.439012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26443 16:34:40.470928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26444 16:34:40.471389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26446 16:34:40.502400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26448 16:34:40.502932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26449 16:34:40.534819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26450 16:34:40.535289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26452 16:34:40.566446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26454 16:34:40.567131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26455 16:34:40.599738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26457 16:34:40.600223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26458 16:34:40.632775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26460 16:34:40.633200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26461 16:34:40.665962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26462 16:34:40.666304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26464 16:34:40.699705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26465 16:34:40.700049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26467 16:34:40.733441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26468 16:34:40.733721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26470 16:34:40.767158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26472 16:34:40.767492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26473 16:34:40.801420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26475 16:34:40.801707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26476 16:34:40.832899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26477 16:34:40.833250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26479 16:34:40.864843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26480 16:34:40.865208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26482 16:34:40.898482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26484 16:34:40.899270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26485 16:34:40.931349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26486 16:34:40.931810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26488 16:34:40.963308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26489 16:34:40.963772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26491 16:34:40.996013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26492 16:34:40.996438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26494 16:34:41.027722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26496 16:34:41.028258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26497 16:34:41.059220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26498 16:34:41.059652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26500 16:34:41.090894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26501 16:34:41.091323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26503 16:34:41.122407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26505 16:34:41.122954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26506 16:34:41.155032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26508 16:34:41.155573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26509 16:34:41.186656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26510 16:34:41.187114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26512 16:34:41.218012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26514 16:34:41.218542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26515 16:34:41.250958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26517 16:34:41.251483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26518 16:34:41.283264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26519 16:34:41.283656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26521 16:34:41.315284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26522 16:34:41.315562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26524 16:34:41.347327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26525 16:34:41.347770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26527 16:34:41.380095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26528 16:34:41.380506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26530 16:34:41.411985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26531 16:34:41.412393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26533 16:34:41.444129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26534 16:34:41.444540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26536 16:34:41.476849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26537 16:34:41.477230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26539 16:34:41.508957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26540 16:34:41.509305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26542 16:34:41.540934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26543 16:34:41.541285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26545 16:34:41.573484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26546 16:34:41.573844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26548 16:34:41.605427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26549 16:34:41.605775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26551 16:34:41.637656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26552 16:34:41.638003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26554 16:34:41.670240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26556 16:34:41.670706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26557 16:34:41.701659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26558 16:34:41.702023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26560 16:34:41.732915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26562 16:34:41.733434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26563 16:34:41.767103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26565 16:34:41.767715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26566 16:34:41.799883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26567 16:34:41.800254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26569 16:34:41.832685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26570 16:34:41.833045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26572 16:34:41.864697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26574 16:34:41.865128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26575 16:34:41.896725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26576 16:34:41.897067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26578 16:34:41.928627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26579 16:34:41.928978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26581 16:34:41.960379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26582 16:34:41.960754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26584 16:34:41.992411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26585 16:34:41.992858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26587 16:34:42.026510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26588 16:34:42.026857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26590 16:34:42.058696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26591 16:34:42.058973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26593 16:34:42.090704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26594 16:34:42.090982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26596 16:34:42.122786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26597 16:34:42.123184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26599 16:34:42.155046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26600 16:34:42.155495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26602 16:34:42.188035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26603 16:34:42.188480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26605 16:34:42.220271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26607 16:34:42.220810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26608 16:34:42.277653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26609 16:34:42.278030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26611 16:34:42.310811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26612 16:34:42.311177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26614 16:34:42.343280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26615 16:34:42.343719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26617 16:34:42.375220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26618 16:34:42.375644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26620 16:34:42.407314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26621 16:34:42.407766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26623 16:34:42.439388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26624 16:34:42.439803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26626 16:34:42.471410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26627 16:34:42.471821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26629 16:34:42.503260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26630 16:34:42.503695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26632 16:34:42.535484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26633 16:34:42.535895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26635 16:34:42.567939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26636 16:34:42.568399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26638 16:34:42.600522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26639 16:34:42.600982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26641 16:34:42.633176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26642 16:34:42.633627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26644 16:34:42.665030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26645 16:34:42.665428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26647 16:34:42.697332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26648 16:34:42.697739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26650 16:34:42.729047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26651 16:34:42.729460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26653 16:34:42.760873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26655 16:34:42.761296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26656 16:34:42.792290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26658 16:34:42.792708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26659 16:34:42.824157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26660 16:34:42.824567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26662 16:34:42.856231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26663 16:34:42.856650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26665 16:34:42.888080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26666 16:34:42.888487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26668 16:34:42.919736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26669 16:34:42.920203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26671 16:34:42.952902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26672 16:34:42.953374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26674 16:34:42.984864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26675 16:34:42.985269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26677 16:34:43.017588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26679 16:34:43.018046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26680 16:34:43.049888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26681 16:34:43.050358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26683 16:34:43.084396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26685 16:34:43.084950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26686 16:34:43.117699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26687 16:34:43.118167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26689 16:34:43.150946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26691 16:34:43.151396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26692 16:34:43.183416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26693 16:34:43.183870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26695 16:34:43.216982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26696 16:34:43.217513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26698 16:34:43.251205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26699 16:34:43.251629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26701 16:34:43.284335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26702 16:34:43.284741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26704 16:34:43.317551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26705 16:34:43.318019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26707 16:34:43.351262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26709 16:34:43.351825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26710 16:34:43.384990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26711 16:34:43.385528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26713 16:34:43.417059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26714 16:34:43.417508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26716 16:34:43.449476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26717 16:34:43.449840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26719 16:34:43.483110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
26720 16:34:43.483464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
26722 16:34:43.515885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
26723 16:34:43.516347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
26725 16:34:43.547807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
26727 16:34:43.548364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
26728 16:34:43.579845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
26729 16:34:43.580285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
26731 16:34:43.611230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
26732 16:34:43.611679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
26734 16:34:43.642891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
26735 16:34:43.643351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
26737 16:34:43.674966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
26738 16:34:43.675410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
26740 16:34:43.706642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
26741 16:34:43.707021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
26743 16:34:43.737932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
26744 16:34:43.738379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
26746 16:34:43.770387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
26748 16:34:43.770957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
26749 16:34:43.801801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
26750 16:34:43.802227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
26752 16:34:43.833218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
26753 16:34:43.833677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
26755 16:34:43.864858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
26756 16:34:43.865325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
26758 16:34:43.896770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
26759 16:34:43.897235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
26761 16:34:43.928993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
26763 16:34:43.929602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
26764 16:34:43.960702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
26765 16:34:43.961157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
26767 16:34:43.992003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
26768 16:34:43.992458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
26770 16:34:44.023263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
26771 16:34:44.023705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
26773 16:34:44.057845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
26774 16:34:44.058294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
26776 16:34:44.104432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
26777 16:34:44.104794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
26779 16:34:44.136487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
26780 16:34:44.136837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
26782 16:34:44.167817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
26783 16:34:44.168162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
26785 16:34:44.201549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
26787 16:34:44.202131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
26788 16:34:44.233271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
26789 16:34:44.233740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
26791 16:34:44.264468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
26792 16:34:44.264919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
26794 16:34:44.296494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
26795 16:34:44.296939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
26797 16:34:44.327636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
26798 16:34:44.328035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
26800 16:34:44.359802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
26801 16:34:44.360190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
26803 16:34:44.391257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
26804 16:34:44.391617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
26806 16:34:44.422754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
26807 16:34:44.423117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
26809 16:34:44.453597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
26810 16:34:44.453968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
26812 16:34:44.484954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
26813 16:34:44.485306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
26815 16:34:44.515894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
26816 16:34:44.516244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
26818 16:34:44.547432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
26819 16:34:44.547714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
26821 16:34:44.578659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
26822 16:34:44.578936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
26824 16:34:44.609979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
26826 16:34:44.610254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
26827 16:34:44.643009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
26828 16:34:44.643272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
26830 16:34:44.674552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
26831 16:34:44.674812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
26833 16:34:44.706988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
26834 16:34:44.707247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
26836 16:34:44.738993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
26837 16:34:44.739253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
26839 16:34:44.771067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
26841 16:34:44.771324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
26842 16:34:44.802635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
26843 16:34:44.802908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
26845 16:34:44.834206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
26847 16:34:44.834477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
26848 16:34:44.866277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
26850 16:34:44.866577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
26851 16:34:44.899177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
26852 16:34:44.899625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
26854 16:34:44.931613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
26855 16:34:44.932027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
26857 16:34:44.964201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
26858 16:34:44.964644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
26860 16:34:44.995475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
26861 16:34:44.995844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
26863 16:34:45.026984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
26864 16:34:45.027338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
26866 16:34:45.058331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
26868 16:34:45.058824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
26869 16:34:45.090781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
26870 16:34:45.091246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
26872 16:34:45.122756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
26874 16:34:45.123380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
26875 16:34:45.155281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
26876 16:34:45.155685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
26878 16:34:45.187296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
26879 16:34:45.187710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
26881 16:34:45.218874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
26883 16:34:45.219302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
26884 16:34:45.250357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
26886 16:34:45.250777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
26887 16:34:45.281733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
26888 16:34:45.282086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
26890 16:34:45.314161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
26892 16:34:45.314618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
26893 16:34:45.345797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
26895 16:34:45.346212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
26896 16:34:45.377445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
26897 16:34:45.377794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
26899 16:34:45.409052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
26900 16:34:45.409421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
26902 16:34:45.440319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
26903 16:34:45.440685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
26905 16:34:45.471607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
26906 16:34:45.472074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
26908 16:34:45.503423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
26910 16:34:45.503970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
26911 16:34:45.535253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
26912 16:34:45.535703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
26914 16:34:45.567316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
26915 16:34:45.567715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
26917 16:34:45.600046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
26919 16:34:45.600485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
26920 16:34:45.632166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
26922 16:34:45.632730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
26923 16:34:45.663443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
26924 16:34:45.663834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
26926 16:34:45.695787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
26927 16:34:45.696234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
26929 16:34:45.727740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
26930 16:34:45.728182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
26932 16:34:45.759291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
26933 16:34:45.759729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
26935 16:34:45.791335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
26936 16:34:45.791714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
26938 16:34:45.823077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
26939 16:34:45.823362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
26941 16:34:45.854199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
26943 16:34:45.854460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
26944 16:34:45.886261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
26946 16:34:45.886716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
26947 16:34:45.918954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
26948 16:34:45.919304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
26950 16:34:45.951422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
26951 16:34:45.951701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
26953 16:34:45.984582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
26954 16:34:45.984990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
26956 16:34:46.017368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
26957 16:34:46.017771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
26959 16:34:46.050262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
26961 16:34:46.050727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
26962 16:34:46.082818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
26963 16:34:46.083288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
26965 16:34:46.116023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
26966 16:34:46.116485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
26968 16:34:46.147857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
26969 16:34:46.148322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
26971 16:34:46.180289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
26973 16:34:46.180855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
26974 16:34:46.211550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
26975 16:34:46.211903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
26977 16:34:46.243151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
26978 16:34:46.243502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
26980 16:34:46.275147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
26981 16:34:46.275499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
26983 16:34:46.307331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
26984 16:34:46.307675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
26986 16:34:46.339785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
26987 16:34:46.340134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
26989 16:34:46.371611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
26991 16:34:46.372151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
26992 16:34:46.403162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
26993 16:34:46.403635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
26995 16:34:46.434804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
26996 16:34:46.435085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
26998 16:34:46.466369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27000 16:34:46.466874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27001 16:34:46.499140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27002 16:34:46.499490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27004 16:34:46.531908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27005 16:34:46.532256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27007 16:34:46.563653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27008 16:34:46.563931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27010 16:34:46.595314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27011 16:34:46.595627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27013 16:34:46.627342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27015 16:34:46.627964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27016 16:34:46.658725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27017 16:34:46.659003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27019 16:34:46.690797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27020 16:34:46.691060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27022 16:34:46.722804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27024 16:34:46.723064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27025 16:34:46.755215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27026 16:34:46.755477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27028 16:34:46.788345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27029 16:34:46.788716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27031 16:34:46.821064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27033 16:34:46.821657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27034 16:34:46.853081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27035 16:34:46.853532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27037 16:34:46.885843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27038 16:34:46.886336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27040 16:34:46.918650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27042 16:34:46.919216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27043 16:34:46.950808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27044 16:34:46.951229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27046 16:34:46.982767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27047 16:34:46.983210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27049 16:34:47.015807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27050 16:34:47.016267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27052 16:34:47.047705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27053 16:34:47.048150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27055 16:34:47.080022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27057 16:34:47.080653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27058 16:34:47.111926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27059 16:34:47.112372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27061 16:34:47.143943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27063 16:34:47.144381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27064 16:34:47.175718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27065 16:34:47.176114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27067 16:34:47.208322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27069 16:34:47.208878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27070 16:34:47.239882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27071 16:34:47.240325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27073 16:34:47.271699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27074 16:34:47.272143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27076 16:34:47.303462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27077 16:34:47.303862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27079 16:34:47.335434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27080 16:34:47.335881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27082 16:34:47.384825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27084 16:34:47.385374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27085 16:34:47.416775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27086 16:34:47.417216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27088 16:34:47.448246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27089 16:34:47.448687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27091 16:34:47.479662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27092 16:34:47.480100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27094 16:34:47.511198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27095 16:34:47.511591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27097 16:34:47.542220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27099 16:34:47.542650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27100 16:34:47.573150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27101 16:34:47.573515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27103 16:34:47.604667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27104 16:34:47.604945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27106 16:34:47.636010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27107 16:34:47.636287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27109 16:34:47.667231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27110 16:34:47.667709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27112 16:34:47.699249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27113 16:34:47.699696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27115 16:34:47.731021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27116 16:34:47.731468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27118 16:34:47.762799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27120 16:34:47.763227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27121 16:34:47.795284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27123 16:34:47.795720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27124 16:34:47.827173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27125 16:34:47.827588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27127 16:34:47.858943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27129 16:34:47.859368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27130 16:34:47.890792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27132 16:34:47.891212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27133 16:34:47.923171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27134 16:34:47.923593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27136 16:34:47.955121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27137 16:34:47.955523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27139 16:34:47.987009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27141 16:34:47.987444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27142 16:34:48.018779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27143 16:34:48.019192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27145 16:34:48.050958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27146 16:34:48.051382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27148 16:34:48.083212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27149 16:34:48.083621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27151 16:34:48.114872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27152 16:34:48.115282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27154 16:34:48.146844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27156 16:34:48.147271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27157 16:34:48.178322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27159 16:34:48.178746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27160 16:34:48.210606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27161 16:34:48.211020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27163 16:34:48.243933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27164 16:34:48.244342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27166 16:34:48.278399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27168 16:34:48.278838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27169 16:34:48.310377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27171 16:34:48.310949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27172 16:34:48.341963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27173 16:34:48.342363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27175 16:34:48.373601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27176 16:34:48.374073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27178 16:34:48.405923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27179 16:34:48.406366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27181 16:34:48.437718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27183 16:34:48.438262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27184 16:34:48.469296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27185 16:34:48.469683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27187 16:34:48.500657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27189 16:34:48.501209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27190 16:34:48.531865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27191 16:34:48.532150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27193 16:34:48.563569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27195 16:34:48.564120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27196 16:34:48.596293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27197 16:34:48.596708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27199 16:34:48.627535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27200 16:34:48.627885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27202 16:34:48.660379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27203 16:34:48.660850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27205 16:34:48.691859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27206 16:34:48.692323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27208 16:34:48.723438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27209 16:34:48.723896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27211 16:34:48.755178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27212 16:34:48.755638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27214 16:34:48.786815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27215 16:34:48.787268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27217 16:34:48.819823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27218 16:34:48.820223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27220 16:34:48.853608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27221 16:34:48.853978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27223 16:34:48.887637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27224 16:34:48.887999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27226 16:34:48.921946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27227 16:34:48.922318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27229 16:34:48.956608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27230 16:34:48.956972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27232 16:34:48.991467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27234 16:34:48.992145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27235 16:34:49.025456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27237 16:34:49.026065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27238 16:34:49.060135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27240 16:34:49.060631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27241 16:34:49.095130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27242 16:34:49.095496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27244 16:34:49.127054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27245 16:34:49.127420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27247 16:34:49.158323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27249 16:34:49.158599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27250 16:34:49.189757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27251 16:34:49.190034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27253 16:34:49.220996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27254 16:34:49.221268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27256 16:34:49.252124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27257 16:34:49.252476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27259 16:34:49.284232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27261 16:34:49.284791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27262 16:34:49.315910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27263 16:34:49.316365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27265 16:34:49.347685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27266 16:34:49.348131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27268 16:34:49.379436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27269 16:34:49.379905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27271 16:34:49.411975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27272 16:34:49.412321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27274 16:34:49.443969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27275 16:34:49.444335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27277 16:34:49.475774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27278 16:34:49.476129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27280 16:34:49.507298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27281 16:34:49.507749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27283 16:34:49.539142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27285 16:34:49.539679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27286 16:34:49.570856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27287 16:34:49.571300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27289 16:34:49.602268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27291 16:34:49.602768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27292 16:34:49.635496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27293 16:34:49.635865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27295 16:34:49.666920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27296 16:34:49.667268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27298 16:34:49.698496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27299 16:34:49.698772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27301 16:34:49.729672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27302 16:34:49.729934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27304 16:34:49.761154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27305 16:34:49.761442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27307 16:34:49.793563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27308 16:34:49.793847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27310 16:34:49.825191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27311 16:34:49.825463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27313 16:34:49.857149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27315 16:34:49.857411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27316 16:34:49.888566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27317 16:34:49.889024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27319 16:34:49.920305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27320 16:34:49.920752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27322 16:34:49.951869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27323 16:34:49.952315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27325 16:34:49.984067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27326 16:34:49.984531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27328 16:34:50.016609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27329 16:34:50.017065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27331 16:34:50.048126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27332 16:34:50.048566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27334 16:34:50.079757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27336 16:34:50.080270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27337 16:34:50.111847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27338 16:34:50.112210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27340 16:34:50.143073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27341 16:34:50.143432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27343 16:34:50.174015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27344 16:34:50.174387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27346 16:34:50.205687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27347 16:34:50.206047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27349 16:34:50.236795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27350 16:34:50.237156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27352 16:34:50.267837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27353 16:34:50.268196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27355 16:34:50.300896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27356 16:34:50.301253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27358 16:34:50.332417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27359 16:34:50.332776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27361 16:34:50.363525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27362 16:34:50.363886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27364 16:34:50.395070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27365 16:34:50.395430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27367 16:34:50.426617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27368 16:34:50.426974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27370 16:34:50.458892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27371 16:34:50.459342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27373 16:34:50.490800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27374 16:34:50.491277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27376 16:34:50.523125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27378 16:34:50.523749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27379 16:34:50.554897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27380 16:34:50.555356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27382 16:34:50.586777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27383 16:34:50.587245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27385 16:34:50.619459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27387 16:34:50.620007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27388 16:34:50.651048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27389 16:34:50.651492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27391 16:34:50.683270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27392 16:34:50.683719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27394 16:34:50.715586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27395 16:34:50.716011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27397 16:34:50.747445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27398 16:34:50.747811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27400 16:34:50.780193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27401 16:34:50.780472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27403 16:34:50.812556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27404 16:34:50.812935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27406 16:34:50.845331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27407 16:34:50.845688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27409 16:34:50.877151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27410 16:34:50.877511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27412 16:34:50.908654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27413 16:34:50.909024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27415 16:34:50.940293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27416 16:34:50.940666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27418 16:34:50.972089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27419 16:34:50.972449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27421 16:34:51.004028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27422 16:34:51.004378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27424 16:34:51.035620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27425 16:34:51.036014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27427 16:34:51.068031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27428 16:34:51.068431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27430 16:34:51.100104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27431 16:34:51.100563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27433 16:34:51.132307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27435 16:34:51.132841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27436 16:34:51.164180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27437 16:34:51.164706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27439 16:34:51.196555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27441 16:34:51.197190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27442 16:34:51.228161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27443 16:34:51.228607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27445 16:34:51.259993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27446 16:34:51.260441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27448 16:34:51.291556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27449 16:34:51.291876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27451 16:34:51.323725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27452 16:34:51.323988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27454 16:34:51.355345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27455 16:34:51.355620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27457 16:34:51.386749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27458 16:34:51.387022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27460 16:34:51.417692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27461 16:34:51.418192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27463 16:34:51.449920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27465 16:34:51.450468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27466 16:34:51.482239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27468 16:34:51.482806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27469 16:34:51.514466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27470 16:34:51.514930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27472 16:34:51.546750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27473 16:34:51.547185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27475 16:34:51.578411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27477 16:34:51.578954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27478 16:34:51.609698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27479 16:34:51.610148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27481 16:34:51.641180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27482 16:34:51.641604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27484 16:34:51.673150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27485 16:34:51.673558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27487 16:34:51.705097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27488 16:34:51.705503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27490 16:34:51.736951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27491 16:34:51.737352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27493 16:34:51.769247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27494 16:34:51.769671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27496 16:34:51.801093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27497 16:34:51.801533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27499 16:34:51.832924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27500 16:34:51.833333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27502 16:34:51.864968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27503 16:34:51.865379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27505 16:34:51.897433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27506 16:34:51.897858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27508 16:34:51.929434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27509 16:34:51.929844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27511 16:34:51.969274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27512 16:34:51.969687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27514 16:34:52.001224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27515 16:34:52.001673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27517 16:34:52.033827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27518 16:34:52.034247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27520 16:34:52.065933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27521 16:34:52.066382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27523 16:34:52.097975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27524 16:34:52.098381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27526 16:34:52.129587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27527 16:34:52.129997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27529 16:34:52.161919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27530 16:34:52.162326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27532 16:34:52.194061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27533 16:34:52.194496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27535 16:34:52.226256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27537 16:34:52.226788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27538 16:34:52.258716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27540 16:34:52.259242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27541 16:34:52.290653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27542 16:34:52.291106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27544 16:34:52.322616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27545 16:34:52.323092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27547 16:34:52.354804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27548 16:34:52.355255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27550 16:34:52.386823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27551 16:34:52.387275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27553 16:34:52.419088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27555 16:34:52.419627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27556 16:34:52.451761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27558 16:34:52.452369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27559 16:34:52.500014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27560 16:34:52.500499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27562 16:34:52.533219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27564 16:34:52.533863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27565 16:34:52.565250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27566 16:34:52.565694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27568 16:34:52.597519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27570 16:34:52.597973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27571 16:34:52.629106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27572 16:34:52.629545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27574 16:34:52.660340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27576 16:34:52.660860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27577 16:34:52.691300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27578 16:34:52.691742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27580 16:34:52.723316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27581 16:34:52.723791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27583 16:34:52.755403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27584 16:34:52.755798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27586 16:34:52.788971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27587 16:34:52.789364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27589 16:34:52.820160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27590 16:34:52.820575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27592 16:34:52.851612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27593 16:34:52.852050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27595 16:34:52.882898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27597 16:34:52.883434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27598 16:34:52.914035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27600 16:34:52.914575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27601 16:34:52.945876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27602 16:34:52.946331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27604 16:34:52.976991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27605 16:34:52.977444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27607 16:34:53.008130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27608 16:34:53.008588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27610 16:34:53.039286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27611 16:34:53.039733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27613 16:34:53.070707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27614 16:34:53.071165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27616 16:34:53.101863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27617 16:34:53.102322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27619 16:34:53.133120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27620 16:34:53.133574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27622 16:34:53.164033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27623 16:34:53.164482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27625 16:34:53.195910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27626 16:34:53.196359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27628 16:34:53.227636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27629 16:34:53.228102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27631 16:34:53.258866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27633 16:34:53.259397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27634 16:34:53.289940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27635 16:34:53.290395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27637 16:34:53.321132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27638 16:34:53.321584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27640 16:34:53.351746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27641 16:34:53.352185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27643 16:34:53.383799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27644 16:34:53.384247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27646 16:34:53.415387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27647 16:34:53.415828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27649 16:34:53.446589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27650 16:34:53.447061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27652 16:34:53.477084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27653 16:34:53.477444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27655 16:34:53.507735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27656 16:34:53.508093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27658 16:34:53.539103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27659 16:34:53.539481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27661 16:34:53.571041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27662 16:34:53.571421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27664 16:34:53.602691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27666 16:34:53.602979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27667 16:34:53.633826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27668 16:34:53.634106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27670 16:34:53.664761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27671 16:34:53.665022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27673 16:34:53.695181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27674 16:34:53.695443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27676 16:34:53.725631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27677 16:34:53.726004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27679 16:34:53.756142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27680 16:34:53.756502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27682 16:34:53.787021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27683 16:34:53.787381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27685 16:34:53.817262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27686 16:34:53.817621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27688 16:34:53.847826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27689 16:34:53.848185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27691 16:34:53.878509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27692 16:34:53.878875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27694 16:34:53.909077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27695 16:34:53.909435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27697 16:34:53.940291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27698 16:34:53.940651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27700 16:34:53.971137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27701 16:34:53.971495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27703 16:34:54.001699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27704 16:34:54.002068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27706 16:34:54.032601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27707 16:34:54.032887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27709 16:34:54.063586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27710 16:34:54.063870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27712 16:34:54.094603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27713 16:34:54.094864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27715 16:34:54.125395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27716 16:34:54.125668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27718 16:34:54.156299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
27719 16:34:54.156564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
27721 16:34:54.187722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
27722 16:34:54.188006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
27724 16:34:54.218613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
27725 16:34:54.218869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
27727 16:34:54.249338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
27728 16:34:54.249593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
27730 16:34:54.280328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
27731 16:34:54.280608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
27733 16:34:54.311502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
27734 16:34:54.311760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
27736 16:34:54.342205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
27738 16:34:54.342463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
27739 16:34:54.373895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
27740 16:34:54.374172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
27742 16:34:54.405342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
27743 16:34:54.405614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
27745 16:34:54.436695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
27746 16:34:54.436977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
27748 16:34:54.468026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
27749 16:34:54.468306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
27751 16:34:54.499673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
27752 16:34:54.499951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
27754 16:34:54.531969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
27755 16:34:54.532248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
27757 16:34:54.563651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
27758 16:34:54.563909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
27760 16:34:54.595301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
27761 16:34:54.595675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
27763 16:34:54.627237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
27764 16:34:54.627604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
27766 16:34:54.658843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
27767 16:34:54.659200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
27769 16:34:54.690744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
27770 16:34:54.691105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
27772 16:34:54.721968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
27773 16:34:54.722326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
27775 16:34:54.753228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
27776 16:34:54.753587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
27778 16:34:54.785048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
27779 16:34:54.785406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
27781 16:34:54.816554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
27782 16:34:54.816919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
27784 16:34:54.847961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
27785 16:34:54.848325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
27787 16:34:54.879355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
27788 16:34:54.879713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
27790 16:34:54.911299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
27791 16:34:54.911673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
27793 16:34:54.943398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
27794 16:34:54.943768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
27796 16:34:54.975180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
27797 16:34:54.975551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
27799 16:34:55.007003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
27800 16:34:55.007371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
27802 16:34:55.039454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
27803 16:34:55.039877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
27805 16:34:55.071146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
27806 16:34:55.071519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
27808 16:34:55.103026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
27809 16:34:55.103396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
27811 16:34:55.134894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
27812 16:34:55.135264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
27814 16:34:55.166608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
27815 16:34:55.166978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
27817 16:34:55.199166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
27818 16:34:55.199537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
27820 16:34:55.230992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
27821 16:34:55.231364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
27823 16:34:55.262695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
27824 16:34:55.263066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
27826 16:34:55.294311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
27828 16:34:55.294824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
27829 16:34:55.325869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
27831 16:34:55.326380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
27832 16:34:55.357605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
27833 16:34:55.357988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
27835 16:34:55.390078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
27836 16:34:55.390442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
27838 16:34:55.421721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
27839 16:34:55.422087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
27841 16:34:55.453372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
27842 16:34:55.453737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
27844 16:34:55.485262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
27845 16:34:55.485626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
27847 16:34:55.519172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
27848 16:34:55.519465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
27850 16:34:55.552422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
27852 16:34:55.552707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
27853 16:34:55.585961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
27855 16:34:55.586240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
27856 16:34:55.619933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
27857 16:34:55.620211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
27859 16:34:55.655339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
27860 16:34:55.655753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
27862 16:34:55.688573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
27863 16:34:55.688895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
27865 16:34:55.722777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
27866 16:34:55.723060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
27868 16:34:55.756209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
27869 16:34:55.756493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
27871 16:34:55.793009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
27872 16:34:55.793341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
27874 16:34:55.838945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
27875 16:34:55.839389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
27877 16:34:55.877655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
27878 16:34:55.878036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
27880 16:34:55.911275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
27881 16:34:55.911598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
27883 16:34:55.944612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
27884 16:34:55.945049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
27886 16:34:55.977616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
27887 16:34:55.978154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
27889 16:34:56.012100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
27890 16:34:56.012639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
27892 16:34:56.045502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
27893 16:34:56.045972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
27895 16:34:56.080388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
27896 16:34:56.080860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
27898 16:34:56.114745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
27899 16:34:56.115139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
27901 16:34:56.148656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
27903 16:34:56.149117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
27904 16:34:56.182260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
27906 16:34:56.182700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
27907 16:34:56.216554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
27908 16:34:56.216916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
27910 16:34:56.250285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
27912 16:34:56.250804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
27913 16:34:56.285150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
27915 16:34:56.285660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
27916 16:34:56.319316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
27917 16:34:56.319590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
27919 16:34:56.356366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
27921 16:34:56.356803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
27922 16:34:56.390215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
27924 16:34:56.390716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
27925 16:34:56.423083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
27926 16:34:56.423362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
27928 16:34:56.457374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
27930 16:34:56.457808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
27931 16:34:56.495136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
27932 16:34:56.495622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
27934 16:34:56.532188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
27936 16:34:56.532674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
27937 16:34:56.565266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
27938 16:34:56.565615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
27940 16:34:56.598934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
27942 16:34:56.599371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
27943 16:34:56.632228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
27944 16:34:56.632577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
27946 16:34:56.664357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
27948 16:34:56.664773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
27949 16:34:56.695341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
27950 16:34:56.695617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
27952 16:34:56.725780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
27953 16:34:56.726159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
27955 16:34:56.756372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
27956 16:34:56.756736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
27958 16:34:56.787216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
27959 16:34:56.787580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
27961 16:34:56.817762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
27962 16:34:56.818124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
27964 16:34:56.848108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
27965 16:34:56.848384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
27967 16:34:56.879123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
27968 16:34:56.879486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
27970 16:34:56.909812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
27971 16:34:56.910173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
27973 16:34:56.940609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
27974 16:34:56.940959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
27976 16:34:56.971550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
27978 16:34:56.971977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
27979 16:34:57.003036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
27980 16:34:57.003399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
27982 16:34:57.033577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
27983 16:34:57.033942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
27985 16:34:57.064902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
27986 16:34:57.065268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
27988 16:34:57.095638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
27989 16:34:57.096002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
27991 16:34:57.126293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
27993 16:34:57.126791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
27994 16:34:57.156948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
27995 16:34:57.157224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
27997 16:34:57.187834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
27998 16:34:57.188191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28000 16:34:57.218590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28001 16:34:57.218949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28003 16:34:57.249113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28004 16:34:57.249394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28006 16:34:57.279725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28007 16:34:57.280005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28009 16:34:57.311263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28011 16:34:57.311541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28012 16:34:57.343573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28013 16:34:57.343924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28015 16:34:57.376020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28016 16:34:57.376341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28018 16:34:57.407696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28019 16:34:57.407972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28021 16:34:57.439098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28022 16:34:57.439376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28024 16:34:57.470283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28026 16:34:57.470562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28027 16:34:57.502746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28028 16:34:57.503120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28030 16:34:57.534859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28031 16:34:57.535221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28033 16:34:57.567825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28034 16:34:57.568225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28036 16:34:57.621901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28037 16:34:57.622261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28039 16:34:57.653175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28040 16:34:57.653529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28042 16:34:57.684559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28043 16:34:57.684906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28045 16:34:57.715594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28046 16:34:57.715923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28048 16:34:57.746590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28049 16:34:57.746967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28051 16:34:57.777467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28052 16:34:57.777743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28054 16:34:57.808311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28055 16:34:57.808676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28057 16:34:57.839209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28058 16:34:57.839554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28060 16:34:57.869950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28061 16:34:57.870302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28063 16:34:57.900978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28065 16:34:57.901408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28066 16:34:57.932091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28067 16:34:57.932439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28069 16:34:57.963104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28070 16:34:57.963449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28072 16:34:57.993494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28073 16:34:57.993849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28075 16:34:58.025094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28076 16:34:58.025462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28078 16:34:58.056334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28080 16:34:58.056749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28081 16:34:58.087644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28082 16:34:58.088062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28084 16:34:58.118802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28085 16:34:58.119080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28087 16:34:58.149708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28088 16:34:58.150057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28090 16:34:58.180713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28092 16:34:58.181141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28093 16:34:58.211572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28095 16:34:58.212037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28096 16:34:58.242704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28097 16:34:58.243052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28099 16:34:58.273506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28100 16:34:58.273874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28102 16:34:58.304607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28103 16:34:58.304954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28105 16:34:58.336292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28106 16:34:58.336568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28108 16:34:58.367134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28109 16:34:58.367485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28111 16:34:58.397760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28112 16:34:58.398124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28114 16:34:58.428653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28115 16:34:58.429001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28117 16:34:58.459175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28118 16:34:58.459521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28120 16:34:58.489712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28121 16:34:58.490071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28123 16:34:58.521232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28124 16:34:58.521578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28126 16:34:58.552032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28127 16:34:58.552309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28129 16:34:58.582555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28130 16:34:58.582934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28132 16:34:58.613387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28133 16:34:58.613756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28135 16:34:58.644877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28136 16:34:58.645153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28138 16:34:58.685596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28139 16:34:58.685876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28141 16:34:58.724446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28142 16:34:58.724818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28144 16:34:58.757235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28145 16:34:58.757605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28147 16:34:58.791040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28148 16:34:58.791411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28150 16:34:58.824060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28151 16:34:58.824379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28153 16:34:58.857820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28154 16:34:58.858179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28156 16:34:58.891190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28157 16:34:58.891546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28159 16:34:58.928169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28160 16:34:58.928528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28162 16:34:58.969239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28163 16:34:58.969613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28165 16:34:59.009082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28166 16:34:59.009544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28168 16:34:59.043229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28170 16:34:59.043690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28171 16:34:59.077258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28173 16:34:59.077719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28174 16:34:59.111230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28175 16:34:59.111508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28177 16:34:59.145452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28178 16:34:59.145803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28180 16:34:59.178938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28181 16:34:59.179282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28183 16:34:59.212252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28184 16:34:59.212625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28186 16:34:59.244444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28187 16:34:59.244803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28189 16:34:59.275463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28190 16:34:59.275816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28192 16:34:59.307014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28194 16:34:59.307477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28195 16:34:59.338566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28196 16:34:59.338932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28198 16:34:59.369674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28200 16:34:59.369958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28201 16:34:59.401945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28202 16:34:59.402293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28204 16:34:59.433597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28205 16:34:59.433957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28207 16:34:59.465217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28209 16:34:59.465700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28210 16:34:59.497990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28212 16:34:59.498489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28213 16:34:59.531836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28215 16:34:59.532384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28216 16:34:59.563245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28217 16:34:59.563622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28219 16:34:59.595573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28220 16:34:59.595879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28222 16:34:59.628506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28223 16:34:59.628881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28225 16:34:59.662247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28227 16:34:59.662715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28228 16:34:59.696415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28229 16:34:59.696879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28231 16:34:59.731445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28232 16:34:59.731970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28234 16:34:59.766995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28235 16:34:59.767402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28237 16:34:59.802094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28239 16:34:59.802551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28240 16:34:59.837464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28242 16:34:59.837793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28243 16:34:59.871902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28244 16:34:59.872278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28246 16:34:59.907226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28248 16:34:59.907652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28249 16:34:59.940055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28251 16:34:59.940498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28252 16:34:59.971720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28254 16:34:59.972175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28255 16:35:00.003672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28257 16:35:00.004105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28258 16:35:00.035193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28259 16:35:00.035479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28261 16:35:00.066814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28262 16:35:00.067163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28264 16:35:00.098776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28266 16:35:00.099240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28267 16:35:00.131398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28268 16:35:00.131751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28270 16:35:00.163039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28271 16:35:00.163321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28273 16:35:00.195733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28274 16:35:00.196108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28276 16:35:00.227404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28277 16:35:00.227776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28279 16:35:00.259151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28280 16:35:00.259429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28282 16:35:00.290657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28283 16:35:00.290938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28285 16:35:00.321969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28286 16:35:00.322343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28288 16:35:00.353284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28289 16:35:00.353657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28291 16:35:00.384249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28292 16:35:00.384592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28294 16:35:00.415883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28295 16:35:00.416241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28297 16:35:00.448120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28299 16:35:00.448560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28300 16:35:00.479983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28302 16:35:00.480654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28303 16:35:00.512564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28305 16:35:00.513033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28306 16:35:00.547125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28307 16:35:00.547522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28309 16:35:00.579547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28310 16:35:00.579931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28312 16:35:00.617429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28313 16:35:00.617819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28315 16:35:00.651411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28317 16:35:00.651683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28318 16:35:00.684371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28319 16:35:00.684834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28321 16:35:00.717391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28322 16:35:00.717760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28324 16:35:00.749808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28326 16:35:00.750092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28327 16:35:00.783363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28328 16:35:00.783668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28330 16:35:00.816480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28331 16:35:00.816761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28333 16:35:00.848383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28335 16:35:00.848657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28336 16:35:00.880711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28337 16:35:00.880984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28339 16:35:00.913437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28340 16:35:00.913800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28342 16:35:00.945374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28344 16:35:00.945840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28345 16:35:00.977399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28346 16:35:00.977828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28348 16:35:01.010312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28350 16:35:01.010804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28351 16:35:01.041757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28353 16:35:01.042272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28354 16:35:01.072785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28355 16:35:01.073147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28357 16:35:01.104023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28358 16:35:01.104385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28360 16:35:01.135276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28362 16:35:01.135734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28363 16:35:01.166609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28365 16:35:01.167093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28366 16:35:01.198274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28368 16:35:01.198720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28369 16:35:01.236119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28370 16:35:01.236486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28372 16:35:01.270140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28374 16:35:01.270649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28375 16:35:01.311425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28377 16:35:01.311864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28378 16:35:01.344979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28380 16:35:01.345259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28381 16:35:01.379181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28382 16:35:01.379457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28384 16:35:01.413948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28385 16:35:01.414224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28387 16:35:01.450519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28389 16:35:01.450955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28390 16:35:01.484109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28391 16:35:01.484461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28393 16:35:01.518782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28395 16:35:01.519225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28396 16:35:01.552938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28397 16:35:01.553292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28399 16:35:01.587087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28400 16:35:01.587363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28402 16:35:01.627262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28404 16:35:01.627535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28405 16:35:01.662247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28407 16:35:01.662559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28408 16:35:01.696639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28410 16:35:01.697130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28411 16:35:01.732656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28413 16:35:01.733142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28414 16:35:01.767548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28416 16:35:01.768059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28417 16:35:01.801412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28418 16:35:01.801793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28420 16:35:01.846192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28422 16:35:01.846664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28423 16:35:01.881314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28424 16:35:01.881742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28426 16:35:01.916572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28427 16:35:01.916915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28429 16:35:01.952434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28430 16:35:01.952860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28432 16:35:01.986832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28433 16:35:01.987312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28435 16:35:02.022984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28436 16:35:02.023417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28438 16:35:02.057481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28439 16:35:02.057892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28441 16:35:02.092242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28443 16:35:02.092717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28444 16:35:02.128233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28445 16:35:02.128634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28447 16:35:02.161309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28448 16:35:02.161679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28450 16:35:02.193390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28451 16:35:02.193793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28453 16:35:02.225075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28455 16:35:02.225637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28456 16:35:02.256348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28458 16:35:02.256827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28459 16:35:02.287978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28461 16:35:02.288428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28462 16:35:02.319796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28463 16:35:02.320257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28465 16:35:02.352779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28466 16:35:02.353230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28468 16:35:02.384809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28470 16:35:02.385255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28471 16:35:02.417061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28472 16:35:02.417471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28474 16:35:02.448903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28475 16:35:02.449222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28477 16:35:02.480290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28478 16:35:02.480655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28480 16:35:02.511360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28482 16:35:02.511809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28483 16:35:02.542498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28484 16:35:02.542871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28486 16:35:02.573409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28488 16:35:02.573867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28489 16:35:02.605158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28490 16:35:02.605434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28492 16:35:02.635860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28493 16:35:02.636138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28495 16:35:02.666777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28496 16:35:02.667039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28498 16:35:02.698012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28499 16:35:02.698273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28501 16:35:02.757884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28502 16:35:02.758158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28504 16:35:02.789665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28506 16:35:02.790142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28507 16:35:02.823426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28508 16:35:02.823838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28510 16:35:02.855537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28511 16:35:02.855935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28513 16:35:02.888576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28515 16:35:02.889064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28516 16:35:02.923848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28518 16:35:02.924289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28519 16:35:02.954603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28520 16:35:02.954963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28522 16:35:02.985772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28523 16:35:02.986135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28525 16:35:03.016647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28526 16:35:03.017000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28528 16:35:03.048180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28530 16:35:03.048609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28531 16:35:03.079391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28532 16:35:03.079739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28534 16:35:03.110620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28535 16:35:03.110975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28537 16:35:03.141368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28538 16:35:03.141683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28540 16:35:03.172744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28541 16:35:03.173022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28543 16:35:03.206407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28544 16:35:03.206815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28546 16:35:03.237606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28548 16:35:03.237843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28549 16:35:03.268528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28550 16:35:03.268896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28552 16:35:03.299727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28553 16:35:03.300102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28555 16:35:03.331137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28556 16:35:03.331532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28558 16:35:03.363737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28560 16:35:03.364195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28561 16:35:03.396357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28563 16:35:03.396931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28564 16:35:03.427716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28565 16:35:03.428188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28567 16:35:03.458953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28568 16:35:03.459442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28570 16:35:03.491019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28572 16:35:03.491634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28573 16:35:03.522519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28575 16:35:03.522841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28576 16:35:03.554899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28578 16:35:03.555271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28579 16:35:03.586179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28581 16:35:03.586455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28582 16:35:03.617814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28583 16:35:03.618140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28585 16:35:03.650591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28587 16:35:03.650850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28588 16:35:03.683010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28590 16:35:03.683287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28591 16:35:03.713994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28592 16:35:03.714289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28594 16:35:03.745385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28595 16:35:03.745769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28597 16:35:03.776551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28598 16:35:03.776886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28600 16:35:03.808205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28601 16:35:03.808548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28603 16:35:03.839923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28605 16:35:03.840341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28606 16:35:03.871576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28607 16:35:03.871906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28609 16:35:03.903204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28610 16:35:03.903558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28612 16:35:03.934655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28613 16:35:03.935027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28615 16:35:03.965328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28616 16:35:03.965692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28618 16:35:03.996610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28619 16:35:03.996989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28621 16:35:04.029714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28622 16:35:04.030110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28624 16:35:04.063145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28625 16:35:04.063608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28627 16:35:04.097710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28628 16:35:04.098222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28630 16:35:04.138077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28632 16:35:04.138498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28633 16:35:04.181273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28634 16:35:04.181660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28636 16:35:04.215751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28637 16:35:04.216153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28639 16:35:04.247351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28640 16:35:04.247631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28642 16:35:04.278590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28644 16:35:04.278876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28645 16:35:04.310046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28647 16:35:04.310551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28648 16:35:04.344344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28650 16:35:04.344854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28651 16:35:04.376790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28652 16:35:04.377219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28654 16:35:04.411724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28655 16:35:04.412094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28657 16:35:04.447489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28659 16:35:04.447886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28660 16:35:04.480527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28661 16:35:04.481003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28663 16:35:04.516026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28664 16:35:04.516448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28666 16:35:04.547751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28667 16:35:04.548114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28669 16:35:04.579768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28671 16:35:04.580265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28672 16:35:04.611297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28673 16:35:04.611675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28675 16:35:04.643341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28677 16:35:04.643805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28678 16:35:04.674783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28679 16:35:04.675134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28681 16:35:04.707614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28682 16:35:04.707969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28684 16:35:04.740202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28686 16:35:04.740642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28687 16:35:04.771812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28688 16:35:04.772157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28690 16:35:04.803392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28691 16:35:04.803736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28693 16:35:04.834834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28695 16:35:04.835138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28696 16:35:04.866411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28698 16:35:04.866999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28699 16:35:04.900038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28701 16:35:04.900632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28702 16:35:04.932805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28704 16:35:04.933368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28705 16:35:04.964584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28706 16:35:04.965033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28708 16:35:04.997249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28710 16:35:04.997904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28711 16:35:05.028941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28712 16:35:05.029420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28714 16:35:05.060668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28716 16:35:05.061162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28717 16:35:05.091965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
28718 16:35:05.092310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28720 16:35:05.123869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
28722 16:35:05.124287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
28723 16:35:05.155662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
28724 16:35:05.156005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
28726 16:35:05.187925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
28727 16:35:05.188286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
28729 16:35:05.220362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
28731 16:35:05.220782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
28732 16:35:05.252171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
28733 16:35:05.252533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
28735 16:35:05.283955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
28736 16:35:05.284431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
28738 16:35:05.315723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
28739 16:35:05.316194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
28741 16:35:05.348311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
28743 16:35:05.348691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
28744 16:35:05.380079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
28745 16:35:05.380389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
28747 16:35:05.411679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
28748 16:35:05.412032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
28750 16:35:05.443176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
28751 16:35:05.443541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
28753 16:35:05.475325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
28754 16:35:05.475677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
28756 16:35:05.508417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
28757 16:35:05.508701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
28759 16:35:05.539699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
28760 16:35:05.540072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
28762 16:35:05.571246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
28763 16:35:05.571594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
28765 16:35:05.601867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
28766 16:35:05.602214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
28768 16:35:05.633034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
28769 16:35:05.633481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
28771 16:35:05.664191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
28772 16:35:05.664565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
28774 16:35:05.696280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
28776 16:35:05.696689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
28777 16:35:05.728670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
28779 16:35:05.729419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
28780 16:35:05.760606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
28781 16:35:05.761015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
28783 16:35:05.793818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
28784 16:35:05.794236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
28786 16:35:05.827511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
28787 16:35:05.827977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
28789 16:35:05.862720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
28790 16:35:05.863149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
28792 16:35:05.895178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
28793 16:35:05.895633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
28795 16:35:05.927947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
28796 16:35:05.928403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
28798 16:35:05.959618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
28800 16:35:05.960195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
28801 16:35:05.991756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
28803 16:35:05.992192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
28804 16:35:06.025020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
28805 16:35:06.025433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
28807 16:35:06.058889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
28808 16:35:06.059298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
28810 16:35:06.092691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
28811 16:35:06.093151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
28813 16:35:06.125397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
28814 16:35:06.125866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
28816 16:35:06.157955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
28818 16:35:06.158510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
28819 16:35:06.191038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
28820 16:35:06.191539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
28822 16:35:06.223861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
28823 16:35:06.224351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
28825 16:35:06.256840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
28827 16:35:06.257415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
28828 16:35:06.289215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
28829 16:35:06.289697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
28831 16:35:06.321079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
28833 16:35:06.321685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
28834 16:35:06.353505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
28835 16:35:06.353978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
28837 16:35:06.385726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
28838 16:35:06.386194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
28840 16:35:06.419127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
28842 16:35:06.419713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
28843 16:35:06.451552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
28845 16:35:06.451987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
28846 16:35:06.482860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
28847 16:35:06.483333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
28849 16:35:06.515117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
28850 16:35:06.515639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
28852 16:35:06.547066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
28853 16:35:06.547476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
28855 16:35:06.579192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
28856 16:35:06.579617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
28858 16:35:06.612099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
28860 16:35:06.612747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
28861 16:35:06.644156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
28862 16:35:06.644559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
28864 16:35:06.675490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
28866 16:35:06.675786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
28867 16:35:06.706929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
28868 16:35:06.707210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
28870 16:35:06.738238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
28872 16:35:06.738524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
28873 16:35:06.772343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
28875 16:35:06.773057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
28876 16:35:06.806954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
28878 16:35:06.807529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
28879 16:35:06.839027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
28880 16:35:06.839480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
28882 16:35:06.872490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
28883 16:35:06.872987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
28885 16:35:06.905073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
28886 16:35:06.905485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
28888 16:35:06.937589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
28890 16:35:06.938131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
28891 16:35:06.977063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
28892 16:35:06.977538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
28894 16:35:07.009133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
28895 16:35:07.009593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
28897 16:35:07.045004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
28899 16:35:07.045353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
28900 16:35:07.075845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
28901 16:35:07.076196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
28903 16:35:07.107638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
28904 16:35:07.107928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
28906 16:35:07.144202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
28907 16:35:07.144491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
28909 16:35:07.175659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
28911 16:35:07.176308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
28912 16:35:07.208619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
28913 16:35:07.209140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
28915 16:35:07.241318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
28916 16:35:07.241775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
28918 16:35:07.273263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
28919 16:35:07.273686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
28921 16:35:07.305387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
28922 16:35:07.305902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
28924 16:35:07.337475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
28925 16:35:07.337947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
28927 16:35:07.368892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
28928 16:35:07.369371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
28930 16:35:07.401690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
28931 16:35:07.402059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
28933 16:35:07.433901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
28934 16:35:07.434186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
28936 16:35:07.465722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
28937 16:35:07.466186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
28939 16:35:07.499824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
28940 16:35:07.500243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
28942 16:35:07.532604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
28943 16:35:07.533045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
28945 16:35:07.564728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
28947 16:35:07.565275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
28948 16:35:07.597782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
28950 16:35:07.598161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
28951 16:35:07.629566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
28953 16:35:07.630155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
28954 16:35:07.661110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
28956 16:35:07.661676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
28957 16:35:07.693254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
28958 16:35:07.693621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
28960 16:35:07.724250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
28961 16:35:07.724617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
28963 16:35:07.755856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
28964 16:35:07.756135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
28966 16:35:07.788448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
28967 16:35:07.788923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
28969 16:35:07.820752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
28970 16:35:07.821209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
28972 16:35:07.892915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
28974 16:35:07.893473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
28975 16:35:07.935733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
28976 16:35:07.936216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
28978 16:35:07.975176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
28980 16:35:07.975756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
28981 16:35:08.007144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
28983 16:35:08.007732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
28984 16:35:08.039704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
28986 16:35:08.040281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
28987 16:35:08.072137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
28988 16:35:08.072511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
28990 16:35:08.103378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
28992 16:35:08.103676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
28993 16:35:08.135287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
28994 16:35:08.135572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
28996 16:35:08.167309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
28998 16:35:08.167596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
28999 16:35:08.197893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29001 16:35:08.198176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29002 16:35:08.239248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29003 16:35:08.239532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29005 16:35:08.277340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29006 16:35:08.277827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29008 16:35:08.319947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29010 16:35:08.320380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29011 16:35:08.354059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29012 16:35:08.354469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29014 16:35:08.392760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29016 16:35:08.393016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29017 16:35:08.426952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29019 16:35:08.427209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29020 16:35:08.461363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29021 16:35:08.461665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29023 16:35:08.496713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29025 16:35:08.497009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29026 16:35:08.530621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29028 16:35:08.531127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29029 16:35:08.563929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29031 16:35:08.564438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29032 16:35:08.598978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29034 16:35:08.599599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29035 16:35:08.630837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29036 16:35:08.631141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29038 16:35:08.664202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29040 16:35:08.664794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29041 16:35:08.702950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29042 16:35:08.703318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29044 16:35:08.740275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29045 16:35:08.740652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29047 16:35:08.772486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29049 16:35:08.772986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29050 16:35:08.803877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29052 16:35:08.804162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29053 16:35:08.840876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29055 16:35:08.841266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29056 16:35:08.885591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29057 16:35:08.885981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29059 16:35:08.926012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29060 16:35:08.926382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29062 16:35:08.967355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29063 16:35:08.967631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29065 16:35:09.008418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29066 16:35:09.008784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29068 16:35:09.046784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29069 16:35:09.047135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29071 16:35:09.082885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29073 16:35:09.083227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29074 16:35:09.115258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29075 16:35:09.115660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29077 16:35:09.148027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29078 16:35:09.148415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29080 16:35:09.179276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29081 16:35:09.179630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29083 16:35:09.215212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29084 16:35:09.215672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29086 16:35:09.248273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29088 16:35:09.248839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29089 16:35:09.280049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29091 16:35:09.280333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29092 16:35:09.315517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29094 16:35:09.315953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29095 16:35:09.347134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29096 16:35:09.347485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29098 16:35:09.379789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29100 16:35:09.380230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29101 16:35:09.412952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29102 16:35:09.413303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29104 16:35:09.444929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29105 16:35:09.445281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29107 16:35:09.478856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29108 16:35:09.479329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29110 16:35:09.511946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29112 16:35:09.512501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29113 16:35:09.544027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29114 16:35:09.544488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29116 16:35:09.578619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29118 16:35:09.579049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29119 16:35:09.610955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29120 16:35:09.611391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29122 16:35:09.643323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29123 16:35:09.643843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29125 16:35:09.677586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29126 16:35:09.678053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29128 16:35:09.709301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29129 16:35:09.709736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29131 16:35:09.742461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29133 16:35:09.743059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29134 16:35:09.775213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29136 16:35:09.775761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29137 16:35:09.808275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29138 16:35:09.808721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29140 16:35:09.840764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29141 16:35:09.841267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29143 16:35:09.873149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29145 16:35:09.873730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29146 16:35:09.905081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29148 16:35:09.905625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29149 16:35:09.943274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29150 16:35:09.943709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29152 16:35:09.992976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29153 16:35:09.993403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29155 16:35:10.034767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29157 16:35:10.035107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29158 16:35:10.066561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29159 16:35:10.067022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29161 16:35:10.098181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29163 16:35:10.098707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29164 16:35:10.129275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29165 16:35:10.129670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29167 16:35:10.160078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29169 16:35:10.160396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29170 16:35:10.190820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29172 16:35:10.191104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29173 16:35:10.222939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29174 16:35:10.223416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29176 16:35:10.254553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29177 16:35:10.255088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29179 16:35:10.286775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29180 16:35:10.287289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29182 16:35:10.318576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29183 16:35:10.318937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29185 16:35:10.350216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29187 16:35:10.350853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29188 16:35:10.381726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29189 16:35:10.382183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29191 16:35:10.412813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29192 16:35:10.413221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29194 16:35:10.444639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29195 16:35:10.445098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29197 16:35:10.475711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29198 16:35:10.476106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29200 16:35:10.506863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29201 16:35:10.507299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29203 16:35:10.539163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29204 16:35:10.539494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29206 16:35:10.569897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29207 16:35:10.570294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29209 16:35:10.600732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29211 16:35:10.601073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29212 16:35:10.631662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29214 16:35:10.631975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29215 16:35:10.664081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29217 16:35:10.664310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29218 16:35:10.697244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29219 16:35:10.697524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29221 16:35:10.731200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29222 16:35:10.731592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29224 16:35:10.764729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29225 16:35:10.765065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29227 16:35:10.813337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29228 16:35:10.813619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29230 16:35:10.856624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29231 16:35:10.856990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29233 16:35:10.892094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29234 16:35:10.892375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29236 16:35:10.925279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29238 16:35:10.925570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29239 16:35:10.957933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29240 16:35:10.958223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29242 16:35:10.991315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29243 16:35:10.991603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29245 16:35:11.025188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29246 16:35:11.025541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29248 16:35:11.059323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29249 16:35:11.059677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29251 16:35:11.094496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29253 16:35:11.094889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29254 16:35:11.128924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29256 16:35:11.129237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29257 16:35:11.161314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29258 16:35:11.161600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29260 16:35:11.193137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29262 16:35:11.193657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29263 16:35:11.224291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29264 16:35:11.224658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29266 16:35:11.255763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29268 16:35:11.256139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29269 16:35:11.287681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29270 16:35:11.288045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29272 16:35:11.319790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29274 16:35:11.320122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29275 16:35:11.351733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29276 16:35:11.352091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29278 16:35:11.383988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29280 16:35:11.384450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29281 16:35:11.417492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29283 16:35:11.417783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29284 16:35:11.450607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29285 16:35:11.450883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29287 16:35:11.483302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29288 16:35:11.483669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29290 16:35:11.516371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29292 16:35:11.516647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29293 16:35:11.549280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29294 16:35:11.549662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29296 16:35:11.580750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29297 16:35:11.581042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29299 16:35:11.611435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29300 16:35:11.611796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29302 16:35:11.642521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29303 16:35:11.642890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29305 16:35:11.673184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29306 16:35:11.673461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29308 16:35:11.703733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29309 16:35:11.704083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29311 16:35:11.736369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29312 16:35:11.736715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29314 16:35:11.770292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29316 16:35:11.770574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29317 16:35:11.804075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29318 16:35:11.804350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29320 16:35:11.838037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29322 16:35:11.838469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29323 16:35:11.869339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29324 16:35:11.869686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29326 16:35:11.900805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29327 16:35:11.901161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29329 16:35:11.933156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29330 16:35:11.933433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29332 16:35:11.964419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29334 16:35:11.964877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29335 16:35:11.996117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29337 16:35:11.996568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29338 16:35:12.028067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29340 16:35:12.028350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29341 16:35:12.059241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29342 16:35:12.059589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29344 16:35:12.090830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29345 16:35:12.091103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29347 16:35:12.122327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29349 16:35:12.122767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29350 16:35:12.153345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29351 16:35:12.153696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29353 16:35:12.187533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29355 16:35:12.187817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29356 16:35:12.220425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29357 16:35:12.220817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29359 16:35:12.254621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29361 16:35:12.255014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29362 16:35:12.287682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29363 16:35:12.288050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29365 16:35:12.321069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29366 16:35:12.321425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29368 16:35:12.353933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29369 16:35:12.354212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29371 16:35:12.387238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29372 16:35:12.387514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29374 16:35:12.418687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29375 16:35:12.418963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29377 16:35:12.450580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29379 16:35:12.451040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29380 16:35:12.482660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29381 16:35:12.483012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29383 16:35:12.516046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29384 16:35:12.516329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29386 16:35:12.547922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29387 16:35:12.548203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29389 16:35:12.579581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29391 16:35:12.580014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29392 16:35:12.611144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29393 16:35:12.611439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29395 16:35:12.642910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29396 16:35:12.643263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29398 16:35:12.675533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29400 16:35:12.675818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29401 16:35:12.709477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29402 16:35:12.709854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29404 16:35:12.743537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29405 16:35:12.743995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29407 16:35:12.777461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29408 16:35:12.777835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29410 16:35:12.811663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29411 16:35:12.811950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29413 16:35:12.845309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29414 16:35:12.845674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29416 16:35:12.879634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29417 16:35:12.879994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29419 16:35:12.914697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29421 16:35:12.914984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29422 16:35:12.959624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29423 16:35:12.959977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29425 16:35:13.028113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29426 16:35:13.028497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29428 16:35:13.061194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29430 16:35:13.061564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29431 16:35:13.095168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29432 16:35:13.095641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29434 16:35:13.129005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29436 16:35:13.129617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29437 16:35:13.161163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29438 16:35:13.161622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29440 16:35:13.192976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29442 16:35:13.193411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29443 16:35:13.224370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29444 16:35:13.224795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29446 16:35:13.256615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29447 16:35:13.257065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29449 16:35:13.289376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29451 16:35:13.289966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29452 16:35:13.321150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29453 16:35:13.321557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29455 16:35:13.352950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29456 16:35:13.353371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29458 16:35:13.384975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29460 16:35:13.385554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29461 16:35:13.416087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29462 16:35:13.416538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29464 16:35:13.447777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29465 16:35:13.448218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29467 16:35:13.479887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29468 16:35:13.480308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29470 16:35:13.511545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29471 16:35:13.511956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29473 16:35:13.543323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29474 16:35:13.543748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29476 16:35:13.575157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29477 16:35:13.575594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29479 16:35:13.607077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29480 16:35:13.607500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29482 16:35:13.639136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29483 16:35:13.639486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29485 16:35:13.670128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29487 16:35:13.670695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29488 16:35:13.701532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29489 16:35:13.701959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29491 16:35:13.732830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29492 16:35:13.733265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29494 16:35:13.764256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29496 16:35:13.764804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29497 16:35:13.796441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29499 16:35:13.796972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29500 16:35:13.828479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29501 16:35:13.828933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29503 16:35:13.860045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29504 16:35:13.860501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29506 16:35:13.891834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29508 16:35:13.892367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29509 16:35:13.926025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29510 16:35:13.926481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29512 16:35:13.957898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29513 16:35:13.958355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29515 16:35:13.989793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29516 16:35:13.990261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29518 16:35:14.022187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29520 16:35:14.022747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29521 16:35:14.054901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29523 16:35:14.055440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29524 16:35:14.086986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29525 16:35:14.087447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29527 16:35:14.119138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29529 16:35:14.119581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29530 16:35:14.150593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29531 16:35:14.150960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29533 16:35:14.181884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29534 16:35:14.182236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29536 16:35:14.213255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29538 16:35:14.213985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29539 16:35:14.244122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29540 16:35:14.244564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29542 16:35:14.275857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29544 16:35:14.276338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29545 16:35:14.308652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29546 16:35:14.309123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29548 16:35:14.340738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29549 16:35:14.341182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29551 16:35:14.372059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29553 16:35:14.372576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29554 16:35:14.403567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29556 16:35:14.404021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29557 16:35:14.435286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29558 16:35:14.435667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29560 16:35:14.466679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29562 16:35:14.467185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29563 16:35:14.499855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29564 16:35:14.500323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29566 16:35:14.532040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29567 16:35:14.532514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29569 16:35:14.563396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29570 16:35:14.563869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29572 16:35:14.595386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29574 16:35:14.595816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29575 16:35:14.627178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29576 16:35:14.627593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29578 16:35:14.659190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29579 16:35:14.659654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29581 16:35:14.691107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29582 16:35:14.691566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29584 16:35:14.722960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29585 16:35:14.723419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29587 16:35:14.755318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29588 16:35:14.755720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29590 16:35:14.787263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29592 16:35:14.787809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29593 16:35:14.819007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29594 16:35:14.819449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29596 16:35:14.851244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29598 16:35:14.851682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29599 16:35:14.883505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29601 16:35:14.883958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29602 16:35:14.915881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29603 16:35:14.916311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29605 16:35:14.948416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29607 16:35:14.949056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29608 16:35:14.981076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29609 16:35:14.981588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29611 16:35:15.013924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29612 16:35:15.014418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29614 16:35:15.046026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29616 16:35:15.046491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29617 16:35:15.080318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29618 16:35:15.080795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29620 16:35:15.116858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29621 16:35:15.117337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29623 16:35:15.148788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29624 16:35:15.149205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29626 16:35:15.181176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29628 16:35:15.181777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29629 16:35:15.213088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29631 16:35:15.213734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29632 16:35:15.244441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29634 16:35:15.244813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29635 16:35:15.275588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29637 16:35:15.276140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29638 16:35:15.307151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29639 16:35:15.307571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29641 16:35:15.339500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29642 16:35:15.339937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29644 16:35:15.371414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29646 16:35:15.371855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29647 16:35:15.404962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29649 16:35:15.405406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29650 16:35:15.437910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29652 16:35:15.438372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29653 16:35:15.470426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29655 16:35:15.470852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29656 16:35:15.502475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29658 16:35:15.502754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29659 16:35:15.535535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29661 16:35:15.536086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29662 16:35:15.567729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29664 16:35:15.568345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29665 16:35:15.599210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29666 16:35:15.599625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29668 16:35:15.631262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29670 16:35:15.631688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29671 16:35:15.665624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29673 16:35:15.666068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29674 16:35:15.699770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29675 16:35:15.700181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29677 16:35:15.736654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29679 16:35:15.737239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29680 16:35:15.774721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29682 16:35:15.775157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29683 16:35:15.809671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29685 16:35:15.810119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29686 16:35:15.843425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29687 16:35:15.843777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29689 16:35:15.876915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29690 16:35:15.877283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29692 16:35:15.908842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29694 16:35:15.909424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29695 16:35:15.940210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29696 16:35:15.940606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29698 16:35:15.972508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29700 16:35:15.973081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29701 16:35:16.004458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29702 16:35:16.004814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29704 16:35:16.036831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29705 16:35:16.037304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29707 16:35:16.068761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29709 16:35:16.069209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29710 16:35:16.100430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29712 16:35:16.101068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29713 16:35:16.133877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29714 16:35:16.134305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29716 16:35:16.167334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29717 16:35:16.167740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29719 16:35:16.199413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
29721 16:35:16.199821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
29722 16:35:16.231305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
29724 16:35:16.231736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
29725 16:35:16.263261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
29726 16:35:16.263735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
29728 16:35:16.295339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
29729 16:35:16.295815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
29731 16:35:16.327297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
29732 16:35:16.327773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
29734 16:35:16.359485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
29735 16:35:16.359886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
29737 16:35:16.392194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
29739 16:35:16.392614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
29740 16:35:16.423809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
29741 16:35:16.424261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
29743 16:35:16.455837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
29744 16:35:16.456289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
29746 16:35:16.487320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
29747 16:35:16.487780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
29749 16:35:16.519254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
29750 16:35:16.519711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
29752 16:35:16.551256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
29753 16:35:16.551706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
29755 16:35:16.583674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
29757 16:35:16.584093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
29758 16:35:16.615609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
29759 16:35:16.615994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
29761 16:35:16.647592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
29762 16:35:16.647952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
29764 16:35:16.679016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
29765 16:35:16.679466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
29767 16:35:16.710553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
29768 16:35:16.711011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
29770 16:35:16.743611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
29771 16:35:16.744077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
29773 16:35:16.775737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
29775 16:35:16.776307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
29776 16:35:16.807253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
29777 16:35:16.807716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
29779 16:35:16.838898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
29780 16:35:16.839358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
29782 16:35:16.869896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
29783 16:35:16.870302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
29785 16:35:16.901471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
29786 16:35:16.901877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
29788 16:35:16.933197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
29789 16:35:16.933597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
29791 16:35:16.964384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
29792 16:35:16.964803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
29794 16:35:16.996107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
29795 16:35:16.996507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
29797 16:35:17.027926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
29798 16:35:17.028369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
29800 16:35:17.059254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
29801 16:35:17.059676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
29803 16:35:17.091079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
29804 16:35:17.091565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
29806 16:35:17.123420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
29808 16:35:17.123960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
29809 16:35:17.155762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
29810 16:35:17.156153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
29812 16:35:17.187259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
29814 16:35:17.187707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
29815 16:35:17.218541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
29817 16:35:17.218996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
29818 16:35:17.250305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
29820 16:35:17.250772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
29821 16:35:17.281692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
29823 16:35:17.282204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
29824 16:35:17.312806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
29825 16:35:17.313166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
29827 16:35:17.343682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
29828 16:35:17.344039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
29830 16:35:17.374929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
29831 16:35:17.375277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
29833 16:35:17.406882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
29835 16:35:17.407165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
29836 16:35:17.437754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
29837 16:35:17.438030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
29839 16:35:17.468700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
29841 16:35:17.469148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
29842 16:35:17.499904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
29843 16:35:17.500177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
29845 16:35:17.531152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
29847 16:35:17.531653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
29848 16:35:17.562191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
29850 16:35:17.562703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
29851 16:35:17.594335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
29853 16:35:17.594908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
29854 16:35:17.625288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
29855 16:35:17.625657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
29857 16:35:17.656535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
29858 16:35:17.656903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
29860 16:35:17.688153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
29862 16:35:17.688610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
29863 16:35:17.719856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
29865 16:35:17.720430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
29866 16:35:17.751510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
29867 16:35:17.751904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
29869 16:35:17.782712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
29870 16:35:17.783066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
29872 16:35:17.813612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
29873 16:35:17.813963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
29875 16:35:17.845273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
29876 16:35:17.845619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
29878 16:35:17.876460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
29880 16:35:17.876745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
29881 16:35:17.907479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
29882 16:35:17.907755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
29884 16:35:17.938627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
29885 16:35:17.938905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
29887 16:35:17.970509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
29888 16:35:17.970778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
29890 16:35:18.001803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
29891 16:35:18.002077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
29893 16:35:18.033485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
29894 16:35:18.033758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
29896 16:35:18.065019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
29897 16:35:18.065432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
29899 16:35:18.117234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
29901 16:35:18.117825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
29902 16:35:18.148780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
29903 16:35:18.149176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
29905 16:35:18.180922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
29906 16:35:18.181318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
29908 16:35:18.212324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
29909 16:35:18.212785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
29911 16:35:18.243909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
29913 16:35:18.244355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
29914 16:35:18.276459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
29916 16:35:18.276896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
29917 16:35:18.308732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
29919 16:35:18.309162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
29920 16:35:18.340093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
29922 16:35:18.340531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
29923 16:35:18.371797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
29924 16:35:18.372187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
29926 16:35:18.403866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
29927 16:35:18.404342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
29929 16:35:18.436764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
29931 16:35:18.437310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
29932 16:35:18.468922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
29933 16:35:18.469369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
29935 16:35:18.500428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
29936 16:35:18.500913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
29938 16:35:18.531789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
29939 16:35:18.532155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
29941 16:35:18.563231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
29942 16:35:18.563592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
29944 16:35:18.594508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
29946 16:35:18.595026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
29947 16:35:18.628410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
29948 16:35:18.628790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
29950 16:35:18.663342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
29952 16:35:18.663753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
29953 16:35:18.694963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
29954 16:35:18.695238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
29956 16:35:18.726546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
29957 16:35:18.726822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
29959 16:35:18.757709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
29960 16:35:18.758075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
29962 16:35:18.790513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
29964 16:35:18.791012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
29965 16:35:18.822524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
29966 16:35:18.822921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
29968 16:35:18.861771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
29969 16:35:18.862177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
29971 16:35:18.895516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
29973 16:35:18.896072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
29974 16:35:18.927980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
29975 16:35:18.928387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
29977 16:35:18.960031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
29979 16:35:18.960508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
29980 16:35:18.991267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
29981 16:35:18.991627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
29983 16:35:19.022518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
29984 16:35:19.022880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
29986 16:35:19.053930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
29987 16:35:19.054286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
29989 16:35:19.087210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
29990 16:35:19.087586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
29992 16:35:19.121355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
29993 16:35:19.121750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
29995 16:35:19.153506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
29996 16:35:19.153893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
29998 16:35:19.184496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
29999 16:35:19.184845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30001 16:35:19.216706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30002 16:35:19.217063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30004 16:35:19.247811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30005 16:35:19.248269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30007 16:35:19.279827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30009 16:35:19.280378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30010 16:35:19.311068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30011 16:35:19.311475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30013 16:35:19.342966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30014 16:35:19.343362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30016 16:35:19.373926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30018 16:35:19.374537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30019 16:35:19.405710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30021 16:35:19.406250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30022 16:35:19.438630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30023 16:35:19.439035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30025 16:35:19.472216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30027 16:35:19.472641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30028 16:35:19.507082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30030 16:35:19.507524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30031 16:35:19.539700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30032 16:35:19.540088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30034 16:35:19.573599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30035 16:35:19.574065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30037 16:35:19.605669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30038 16:35:19.606062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30040 16:35:19.637919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30042 16:35:19.638231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30043 16:35:19.671396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30044 16:35:19.671689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30046 16:35:19.703281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30047 16:35:19.703704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30049 16:35:19.734835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30050 16:35:19.735140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30052 16:35:19.768492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30054 16:35:19.768771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30055 16:35:19.800408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30056 16:35:19.800771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30058 16:35:19.832324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30059 16:35:19.832679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30061 16:35:19.867212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30063 16:35:19.867552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30064 16:35:19.898805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30065 16:35:19.899118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30067 16:35:19.930518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30068 16:35:19.930973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30070 16:35:19.961675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30071 16:35:19.962096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30073 16:35:19.993317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30074 16:35:19.993764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30076 16:35:20.025368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30078 16:35:20.025969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30079 16:35:20.056250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30080 16:35:20.056710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30082 16:35:20.087487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30083 16:35:20.087852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30085 16:35:20.119996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30086 16:35:20.120324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30088 16:35:20.155352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30089 16:35:20.155726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30091 16:35:20.191520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30092 16:35:20.191915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30094 16:35:20.225620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30095 16:35:20.226048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30097 16:35:20.260257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30099 16:35:20.260703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30100 16:35:20.305690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30102 16:35:20.306327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30103 16:35:20.340944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30105 16:35:20.341405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30106 16:35:20.373578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30108 16:35:20.374343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30109 16:35:20.407148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30111 16:35:20.407611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30112 16:35:20.440765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30113 16:35:20.441199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30115 16:35:20.473680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30116 16:35:20.474118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30118 16:35:20.507562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30119 16:35:20.507938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30121 16:35:20.542666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30122 16:35:20.542958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30124 16:35:20.575623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30126 16:35:20.576148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30127 16:35:20.607313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30129 16:35:20.607888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30130 16:35:20.639082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30131 16:35:20.639446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30133 16:35:20.671005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30134 16:35:20.671375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30136 16:35:20.703504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30137 16:35:20.703909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30139 16:35:20.749584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30140 16:35:20.750054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30142 16:35:20.798853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30143 16:35:20.799252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30145 16:35:20.832475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30146 16:35:20.832864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30148 16:35:20.879014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30149 16:35:20.879369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30151 16:35:20.911967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30152 16:35:20.912383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30154 16:35:20.944511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30155 16:35:20.944952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30157 16:35:20.976433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30159 16:35:20.977102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30160 16:35:21.007892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30162 16:35:21.008364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30163 16:35:21.039300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30165 16:35:21.039857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30166 16:35:21.072372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30167 16:35:21.072830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30169 16:35:21.103643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30170 16:35:21.104114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30172 16:35:21.139893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30173 16:35:21.140321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30175 16:35:21.172945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30177 16:35:21.173572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30178 16:35:21.206821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30180 16:35:21.207277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30181 16:35:21.239399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30182 16:35:21.239832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30184 16:35:21.272036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30186 16:35:21.272494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30187 16:35:21.303550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30189 16:35:21.304045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30190 16:35:21.336166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30191 16:35:21.336581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30193 16:35:21.368842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30195 16:35:21.369281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30196 16:35:21.401637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30197 16:35:21.402072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30199 16:35:21.433875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30201 16:35:21.434306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30202 16:35:21.465717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30203 16:35:21.466134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30205 16:35:21.498570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30206 16:35:21.498998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30208 16:35:21.531613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30210 16:35:21.532063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30211 16:35:21.563329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30212 16:35:21.563744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30214 16:35:21.594445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30215 16:35:21.594739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30217 16:35:21.626844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30218 16:35:21.627296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30220 16:35:21.658722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30222 16:35:21.659163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30223 16:35:21.691321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30225 16:35:21.691734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30226 16:35:21.722635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30227 16:35:21.723105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30229 16:35:21.754417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30231 16:35:21.755131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30232 16:35:21.786871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30234 16:35:21.787315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30235 16:35:21.819207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30236 16:35:21.819597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30238 16:35:21.850643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30239 16:35:21.851108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30241 16:35:21.883302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30243 16:35:21.883893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30244 16:35:21.915207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30245 16:35:21.915687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30247 16:35:21.947283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30249 16:35:21.947719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30250 16:35:21.979304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30252 16:35:21.979818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30253 16:35:22.011245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30255 16:35:22.011579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30256 16:35:22.043077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30257 16:35:22.043522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30259 16:35:22.075018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30260 16:35:22.075473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30262 16:35:22.109008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30263 16:35:22.109464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30265 16:35:22.144390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30267 16:35:22.144828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30268 16:35:22.177022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30269 16:35:22.177427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30271 16:35:22.209404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30272 16:35:22.209835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30274 16:35:22.242853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30275 16:35:22.243266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30277 16:35:22.275467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30278 16:35:22.275881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30280 16:35:22.307718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30282 16:35:22.308289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30283 16:35:22.340093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30284 16:35:22.340543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30286 16:35:22.372456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30288 16:35:22.373036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30289 16:35:22.408012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30291 16:35:22.408597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30292 16:35:22.441448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30294 16:35:22.442074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30295 16:35:22.480843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30296 16:35:22.481273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30298 16:35:22.525256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30299 16:35:22.525645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30301 16:35:22.571305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30302 16:35:22.571671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30304 16:35:22.604072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30305 16:35:22.604506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30307 16:35:22.636324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30309 16:35:22.636838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30310 16:35:22.675736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30312 16:35:22.676160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30313 16:35:22.711454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30314 16:35:22.711810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30316 16:35:22.743961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30317 16:35:22.744395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30319 16:35:22.776801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30320 16:35:22.777241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30322 16:35:22.809019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30323 16:35:22.809459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30325 16:35:22.841175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30326 16:35:22.841600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30328 16:35:22.874129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30329 16:35:22.874536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30331 16:35:22.907676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30333 16:35:22.908108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30334 16:35:22.940185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30335 16:35:22.940588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30337 16:35:22.973504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30338 16:35:22.973985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30340 16:35:23.006260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30342 16:35:23.006675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30343 16:35:23.040675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30344 16:35:23.041079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30346 16:35:23.074156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30348 16:35:23.074693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30349 16:35:23.107356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30350 16:35:23.107709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30352 16:35:23.139663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30353 16:35:23.140018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30355 16:35:23.171999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30356 16:35:23.172384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30358 16:35:23.225751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30360 16:35:23.226206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30361 16:35:23.259161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30363 16:35:23.259593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30364 16:35:23.292138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30365 16:35:23.292489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30367 16:35:23.324470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30368 16:35:23.324817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30370 16:35:23.356122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30372 16:35:23.356563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30373 16:35:23.388524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30374 16:35:23.388902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30376 16:35:23.420947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30378 16:35:23.421417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30379 16:35:23.453808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30380 16:35:23.454229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30382 16:35:23.487977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30383 16:35:23.488389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30385 16:35:23.521608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30386 16:35:23.522038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30388 16:35:23.554793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30389 16:35:23.555128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30391 16:35:23.587499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30393 16:35:23.587810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30394 16:35:23.620163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30396 16:35:23.620465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30397 16:35:23.652597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30398 16:35:23.652973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30400 16:35:23.685361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30401 16:35:23.685644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30403 16:35:23.717232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30404 16:35:23.717510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30406 16:35:23.749681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30407 16:35:23.750089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30409 16:35:23.783931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30410 16:35:23.784360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30412 16:35:23.817143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30413 16:35:23.817541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30415 16:35:23.849274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30417 16:35:23.849715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30418 16:35:23.881977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30419 16:35:23.882382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30421 16:35:23.916107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30423 16:35:23.916744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30424 16:35:23.950713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30425 16:35:23.951110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30427 16:35:23.985831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30428 16:35:23.986273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30430 16:35:24.020684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30432 16:35:24.021139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30433 16:35:24.054652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30434 16:35:24.055076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30436 16:35:24.088845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30437 16:35:24.089291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30439 16:35:24.125020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30441 16:35:24.125578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30442 16:35:24.158838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30443 16:35:24.159269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30445 16:35:24.192426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30446 16:35:24.192841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30448 16:35:24.226952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30450 16:35:24.227374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30451 16:35:24.261210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30452 16:35:24.261658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30454 16:35:24.296783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30455 16:35:24.297194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30457 16:35:24.331508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30458 16:35:24.331926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30460 16:35:24.366712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30462 16:35:24.367181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30463 16:35:24.400906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30464 16:35:24.401313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30466 16:35:24.433487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30467 16:35:24.433890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30469 16:35:24.467131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30470 16:35:24.467516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30472 16:35:24.501204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30473 16:35:24.501588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30475 16:35:24.535234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30477 16:35:24.535684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30478 16:35:24.567974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30480 16:35:24.568409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30481 16:35:24.601409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30482 16:35:24.601884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30484 16:35:24.633927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30486 16:35:24.634408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30487 16:35:24.669592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30489 16:35:24.670065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30490 16:35:24.711509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30491 16:35:24.711903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30493 16:35:24.765488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30494 16:35:24.765921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30496 16:35:24.804653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30497 16:35:24.805060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30499 16:35:24.841010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30500 16:35:24.841385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30502 16:35:24.883399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30504 16:35:24.883857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30505 16:35:24.917007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30506 16:35:24.917440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30508 16:35:24.950693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30509 16:35:24.951110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30511 16:35:24.983566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30512 16:35:24.984038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30514 16:35:25.021132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30515 16:35:25.021606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30517 16:35:25.054368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30519 16:35:25.054751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30520 16:35:25.097183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30521 16:35:25.097698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30523 16:35:25.130925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30524 16:35:25.131336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30526 16:35:25.165712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30528 16:35:25.166182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30529 16:35:25.199353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30530 16:35:25.199853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30532 16:35:25.233593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30534 16:35:25.234044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30535 16:35:25.267972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30536 16:35:25.268399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30538 16:35:25.304995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30539 16:35:25.305418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30541 16:35:25.337727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30542 16:35:25.338152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30544 16:35:25.369691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30545 16:35:25.370097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30547 16:35:25.401752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30548 16:35:25.402187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30550 16:35:25.434941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30551 16:35:25.435416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30553 16:35:25.467775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30554 16:35:25.468247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30556 16:35:25.500581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30557 16:35:25.501089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30559 16:35:25.535201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30561 16:35:25.535735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30562 16:35:25.569687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30564 16:35:25.570153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30565 16:35:25.604132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30566 16:35:25.604568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30568 16:35:25.638377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30570 16:35:25.638824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30571 16:35:25.674335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30573 16:35:25.674764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30574 16:35:25.707282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30575 16:35:25.707707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30577 16:35:25.740915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30578 16:35:25.741287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30580 16:35:25.775664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30581 16:35:25.776041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30583 16:35:25.811430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30585 16:35:25.811828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30586 16:35:25.859136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30588 16:35:25.859583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30589 16:35:25.893047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30591 16:35:25.893818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30592 16:35:25.940301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30593 16:35:25.940655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30595 16:35:25.981951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30596 16:35:25.982316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30598 16:35:26.015262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30599 16:35:26.015564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30601 16:35:26.049418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30602 16:35:26.049816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30604 16:35:26.084027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30605 16:35:26.084475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30607 16:35:26.117426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30609 16:35:26.118103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30610 16:35:26.149424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30611 16:35:26.149867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30613 16:35:26.182027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30615 16:35:26.182499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30616 16:35:26.215202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30618 16:35:26.215642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30619 16:35:26.248534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30620 16:35:26.248955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30622 16:35:26.281762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30623 16:35:26.282163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30625 16:35:26.315095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30626 16:35:26.315519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30628 16:35:26.348128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30629 16:35:26.348583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30631 16:35:26.381354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30632 16:35:26.381774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30634 16:35:26.415730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30636 16:35:26.416188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30637 16:35:26.449303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30638 16:35:26.449748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30640 16:35:26.484278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30641 16:35:26.484681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30643 16:35:26.518392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30645 16:35:26.518846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30646 16:35:26.554434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30648 16:35:26.554880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30649 16:35:26.588711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30650 16:35:26.589140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30652 16:35:26.623688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30653 16:35:26.624139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30655 16:35:26.659736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30657 16:35:26.660172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30658 16:35:26.692221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30659 16:35:26.692607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30661 16:35:26.724163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30662 16:35:26.724612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30664 16:35:26.755935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30665 16:35:26.756396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30667 16:35:26.787525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30668 16:35:26.787985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30670 16:35:26.825772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30672 16:35:26.826246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30673 16:35:26.859412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30674 16:35:26.859852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30676 16:35:26.891840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30677 16:35:26.892279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30679 16:35:26.925396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30680 16:35:26.925824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30682 16:35:26.957569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30683 16:35:26.958060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30685 16:35:26.990313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30687 16:35:26.990944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30688 16:35:27.024095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30689 16:35:27.024507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30691 16:35:27.058198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30693 16:35:27.058769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30694 16:35:27.092060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30695 16:35:27.092477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30697 16:35:27.125076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30699 16:35:27.125524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30700 16:35:27.160010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30701 16:35:27.160426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30703 16:35:27.195434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30705 16:35:27.195869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30706 16:35:27.228239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30708 16:35:27.228670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30709 16:35:27.262377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30711 16:35:27.262846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30712 16:35:27.295801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30713 16:35:27.296263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30715 16:35:27.328712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30717 16:35:27.329160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30718 16:35:27.361032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
30719 16:35:27.361503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
30721 16:35:27.393140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
30722 16:35:27.393606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
30724 16:35:27.425352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
30725 16:35:27.425816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
30727 16:35:27.458109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
30729 16:35:27.458570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
30730 16:35:27.491257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
30731 16:35:27.491734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
30733 16:35:27.523676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
30734 16:35:27.524104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
30736 16:35:27.556534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
30737 16:35:27.557011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
30739 16:35:27.589968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
30741 16:35:27.590436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
30742 16:35:27.623211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
30744 16:35:27.623658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
30745 16:35:27.655442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
30746 16:35:27.655866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
30748 16:35:27.688312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
30750 16:35:27.688742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
30751 16:35:27.720756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
30752 16:35:27.721161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
30754 16:35:27.753158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
30756 16:35:27.753593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
30757 16:35:27.785420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
30759 16:35:27.785846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
30760 16:35:27.817704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
30761 16:35:27.818101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
30763 16:35:27.850719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
30765 16:35:27.851198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
30766 16:35:27.882838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
30767 16:35:27.883278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
30769 16:35:27.916040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
30770 16:35:27.916449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
30772 16:35:27.948854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
30774 16:35:27.949414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
30775 16:35:27.980941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
30777 16:35:27.981398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
30778 16:35:28.013087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
30779 16:35:28.013503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
30781 16:35:28.045050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
30783 16:35:28.045505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
30784 16:35:28.077132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
30785 16:35:28.077552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
30787 16:35:28.111565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
30788 16:35:28.111989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
30790 16:35:28.146490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
30792 16:35:28.146968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
30793 16:35:28.179805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
30794 16:35:28.180207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
30796 16:35:28.212146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
30797 16:35:28.212544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
30799 16:35:28.243557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
30800 16:35:28.243962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
30802 16:35:28.275944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
30804 16:35:28.276397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
30805 16:35:28.316296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
30806 16:35:28.316691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
30808 16:35:28.369681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
30809 16:35:28.370179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
30811 16:35:28.403524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
30812 16:35:28.404008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
30814 16:35:28.436969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
30815 16:35:28.437378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
30817 16:35:28.470222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
30819 16:35:28.470838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
30820 16:35:28.503166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
30822 16:35:28.503736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
30823 16:35:28.537156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
30824 16:35:28.537643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
30826 16:35:28.570417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
30828 16:35:28.571013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
30829 16:35:28.603377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
30830 16:35:28.603788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
30832 16:35:28.636778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
30833 16:35:28.637190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
30835 16:35:28.674553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
30836 16:35:28.674965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
30838 16:35:28.707465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
30839 16:35:28.707864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
30841 16:35:28.739965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
30843 16:35:28.740396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
30844 16:35:28.772004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
30845 16:35:28.772431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
30847 16:35:28.806398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
30849 16:35:28.806966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
30850 16:35:28.839135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
30852 16:35:28.839586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
30853 16:35:28.875817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
30854 16:35:28.876500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
30856 16:35:28.920193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
30858 16:35:28.920779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
30859 16:35:28.959490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
30861 16:35:28.960063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
30862 16:35:29.005085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
30864 16:35:29.005494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
30865 16:35:29.043340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
30866 16:35:29.043715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
30868 16:35:29.078320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
30870 16:35:29.078712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
30871 16:35:29.110964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
30872 16:35:29.111343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
30874 16:35:29.147932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
30875 16:35:29.148336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
30877 16:35:29.181185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
30879 16:35:29.181610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
30880 16:35:29.213058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
30882 16:35:29.213475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
30883 16:35:29.246472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
30884 16:35:29.246880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
30886 16:35:29.279708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
30887 16:35:29.280103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
30889 16:35:29.311942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
30891 16:35:29.312361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
30892 16:35:29.358251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
30894 16:35:29.358885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
30895 16:35:29.392839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
30897 16:35:29.393407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
30898 16:35:29.427432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
30899 16:35:29.427853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
30901 16:35:29.463106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
30902 16:35:29.463514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
30904 16:35:29.499554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
30905 16:35:29.499974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
30907 16:35:29.535467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
30908 16:35:29.535889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
30910 16:35:29.570828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
30912 16:35:29.571239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
30913 16:35:29.606734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
30914 16:35:29.607181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
30916 16:35:29.641576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
30918 16:35:29.642060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
30919 16:35:29.676316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
30920 16:35:29.676754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
30922 16:35:29.711139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
30923 16:35:29.711575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
30925 16:35:29.747190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
30927 16:35:29.747651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
30928 16:35:29.780148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
30929 16:35:29.780582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
30931 16:35:29.812564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
30933 16:35:29.812995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
30934 16:35:29.844169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
30935 16:35:29.844583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
30937 16:35:29.877365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
30939 16:35:29.877917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
30940 16:35:29.910680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
30942 16:35:29.911162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
30943 16:35:29.943022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
30945 16:35:29.943382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
30946 16:35:29.976677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
30948 16:35:29.977031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
30949 16:35:30.011450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
30951 16:35:30.011814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
30952 16:35:30.044809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
30954 16:35:30.045352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
30955 16:35:30.085099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
30956 16:35:30.085454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
30958 16:35:30.118798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
30959 16:35:30.119151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
30961 16:35:30.150735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
30962 16:35:30.151121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
30964 16:35:30.192195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
30965 16:35:30.192689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
30967 16:35:30.225321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
30969 16:35:30.225706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
30970 16:35:30.256835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
30972 16:35:30.257371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
30973 16:35:30.289381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
30974 16:35:30.289805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
30976 16:35:30.322617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
30977 16:35:30.323027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
30979 16:35:30.354552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
30980 16:35:30.354955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
30982 16:35:30.387982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
30983 16:35:30.388526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
30985 16:35:30.424248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
30986 16:35:30.424738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
30988 16:35:30.455558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
30989 16:35:30.455950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
30991 16:35:30.489099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
30992 16:35:30.489415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
30994 16:35:30.523394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
30995 16:35:30.523702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
30997 16:35:30.557625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
30999 16:35:30.557983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31000 16:35:30.592212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31001 16:35:30.592568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31003 16:35:30.627396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31004 16:35:30.627802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31006 16:35:30.663397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31008 16:35:30.663801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31009 16:35:30.698208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31011 16:35:30.698561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31012 16:35:30.733688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31013 16:35:30.734016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31015 16:35:30.779454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31016 16:35:30.779903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31018 16:35:30.833310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31019 16:35:30.833684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31021 16:35:30.876720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31022 16:35:30.877181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31024 16:35:30.911272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31026 16:35:30.911877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31027 16:35:30.946349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31029 16:35:30.946945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31030 16:35:30.979707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31031 16:35:30.980148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31033 16:35:31.012864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31035 16:35:31.013524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31036 16:35:31.048120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31038 16:35:31.048578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31039 16:35:31.082835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31040 16:35:31.083398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31042 16:35:31.119432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31044 16:35:31.119822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31045 16:35:31.153541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31046 16:35:31.153988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31048 16:35:31.185942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31050 16:35:31.186372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31051 16:35:31.217859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31052 16:35:31.218275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31054 16:35:31.250113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31056 16:35:31.250569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31057 16:35:31.283229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31058 16:35:31.283630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31060 16:35:31.315260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31062 16:35:31.315856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31063 16:35:31.347212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31065 16:35:31.347799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31066 16:35:31.379107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31067 16:35:31.379560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31069 16:35:31.410875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31070 16:35:31.411316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31072 16:35:31.442698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31074 16:35:31.443241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31075 16:35:31.474239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31077 16:35:31.474672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31078 16:35:31.507172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31079 16:35:31.507554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31081 16:35:31.539415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31082 16:35:31.539876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31084 16:35:31.571432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31085 16:35:31.571837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31087 16:35:31.604165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31088 16:35:31.604640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31090 16:35:31.649591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31091 16:35:31.650129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31093 16:35:31.682430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31095 16:35:31.682856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31096 16:35:31.714705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31098 16:35:31.715125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31099 16:35:31.747721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31101 16:35:31.748141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31102 16:35:31.779592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31103 16:35:31.780076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31105 16:35:31.811274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31107 16:35:31.811722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31108 16:35:31.843084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31109 16:35:31.843563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31111 16:35:31.874959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31112 16:35:31.875348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31114 16:35:31.907976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31115 16:35:31.908394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31117 16:35:31.942935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31118 16:35:31.943351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31120 16:35:31.977200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31122 16:35:31.977664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31123 16:35:32.011721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31124 16:35:32.012134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31126 16:35:32.045457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31128 16:35:32.045917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31129 16:35:32.076995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31130 16:35:32.077468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31132 16:35:32.110790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31133 16:35:32.111137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31135 16:35:32.147249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31136 16:35:32.147654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31138 16:35:32.180315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31139 16:35:32.180715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31141 16:35:32.213193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31142 16:35:32.213604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31144 16:35:32.245368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31145 16:35:32.245746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31147 16:35:32.277918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31148 16:35:32.278342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31150 16:35:32.309617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31151 16:35:32.310028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31153 16:35:32.342344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31155 16:35:32.342933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31156 16:35:32.378060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31158 16:35:32.378580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31159 16:35:32.411469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31161 16:35:32.411921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31162 16:35:32.444405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31163 16:35:32.444861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31165 16:35:32.476583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31166 16:35:32.477002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31168 16:35:32.508792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31169 16:35:32.509218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31171 16:35:32.543700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31173 16:35:32.544159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31174 16:35:32.576445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31175 16:35:32.576948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31177 16:35:32.609182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31178 16:35:32.609588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31180 16:35:32.642713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31182 16:35:32.643349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31183 16:35:32.674465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31185 16:35:32.675120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31186 16:35:32.708084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31187 16:35:32.708488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31189 16:35:32.740200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31190 16:35:32.740684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31192 16:35:32.771990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31193 16:35:32.772465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31195 16:35:32.804500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31197 16:35:32.805184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31198 16:35:32.835843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31199 16:35:32.836271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31201 16:35:32.868195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31202 16:35:32.868553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31204 16:35:32.899297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31205 16:35:32.899636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31207 16:35:32.930685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31208 16:35:32.931014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31210 16:35:32.963004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31211 16:35:32.963318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31213 16:35:32.994867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31214 16:35:32.995220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31216 16:35:33.026414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31218 16:35:33.026843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31219 16:35:33.059059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31221 16:35:33.059503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31222 16:35:33.090994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31223 16:35:33.091326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31225 16:35:33.123064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31226 16:35:33.123487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31228 16:35:33.155066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31229 16:35:33.155537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31231 16:35:33.187146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31233 16:35:33.187569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31234 16:35:33.218699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31236 16:35:33.219126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31237 16:35:33.251774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31239 16:35:33.252411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31240 16:35:33.283388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31242 16:35:33.283823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31243 16:35:33.315511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31244 16:35:33.315992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31246 16:35:33.347348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31247 16:35:33.347872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31249 16:35:33.380534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31251 16:35:33.380978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31252 16:35:33.412505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31253 16:35:33.412961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31255 16:35:33.479328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31257 16:35:33.479941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31258 16:35:33.510735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31259 16:35:33.511166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31261 16:35:33.544218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31262 16:35:33.544687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31264 16:35:33.578758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31266 16:35:33.579213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31267 16:35:33.611347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31269 16:35:33.611758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31270 16:35:33.643192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31272 16:35:33.643952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31273 16:35:33.675562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31274 16:35:33.676043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31276 16:35:33.707468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31277 16:35:33.707878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31279 16:35:33.739887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31281 16:35:33.740449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31282 16:35:33.776369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31283 16:35:33.776851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31285 16:35:33.815939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31287 16:35:33.816413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31288 16:35:33.850609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31290 16:35:33.851104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31291 16:35:33.882775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31293 16:35:33.883217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31294 16:35:33.914289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31296 16:35:33.914589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31297 16:35:33.947743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31298 16:35:33.948149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31300 16:35:33.979751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31301 16:35:33.980141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31303 16:35:34.011400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31304 16:35:34.011725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31306 16:35:34.044139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31307 16:35:34.044424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31309 16:35:34.076394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31310 16:35:34.076765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31312 16:35:34.108066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31313 16:35:34.108422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31315 16:35:34.139722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31316 16:35:34.140098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31318 16:35:34.172893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31319 16:35:34.173253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31321 16:35:34.203983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31322 16:35:34.204335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31324 16:35:34.235796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31325 16:35:34.236149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31327 16:35:34.267384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31328 16:35:34.267732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31330 16:35:34.299896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31332 16:35:34.300347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31333 16:35:34.331666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31334 16:35:34.332017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31336 16:35:34.363295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31337 16:35:34.363701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31339 16:35:34.395210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31341 16:35:34.395842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31342 16:35:34.427819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31344 16:35:34.428450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31345 16:35:34.460680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31346 16:35:34.461093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31348 16:35:34.495522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31349 16:35:34.495955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31351 16:35:34.529559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31352 16:35:34.529977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31354 16:35:34.562689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31355 16:35:34.563091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31357 16:35:34.596232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31359 16:35:34.596794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31360 16:35:34.631720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31362 16:35:34.632187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31363 16:35:34.673865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31364 16:35:34.674278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31366 16:35:34.711287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31368 16:35:34.711739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31369 16:35:34.744934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31371 16:35:34.745362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31372 16:35:34.777381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31374 16:35:34.777952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31375 16:35:34.811633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31377 16:35:34.812289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31378 16:35:34.844045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31380 16:35:34.844665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31381 16:35:34.877175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31383 16:35:34.877598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31384 16:35:34.910678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31386 16:35:34.911099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31387 16:35:34.944221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31388 16:35:34.944717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31390 16:35:34.976225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31391 16:35:34.976635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31393 16:35:35.007843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31394 16:35:35.008242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31396 16:35:35.040001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31398 16:35:35.040554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31399 16:35:35.072538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31401 16:35:35.073092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31402 16:35:35.105408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31404 16:35:35.106003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31405 16:35:35.137828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31407 16:35:35.138366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31408 16:35:35.170183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31410 16:35:35.170758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31411 16:35:35.202940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31412 16:35:35.203362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31414 16:35:35.235438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31416 16:35:35.236027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31417 16:35:35.267275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31418 16:35:35.267636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31420 16:35:35.299315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31421 16:35:35.299673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31423 16:35:35.331696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31424 16:35:35.332145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31426 16:35:35.363811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31427 16:35:35.364158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31429 16:35:35.396700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31431 16:35:35.397134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31432 16:35:35.430836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31433 16:35:35.431315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31435 16:35:35.464136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31437 16:35:35.464746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31438 16:35:35.497056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31439 16:35:35.497459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31441 16:35:35.531373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31442 16:35:35.531844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31444 16:35:35.563841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31445 16:35:35.564337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31447 16:35:35.597999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31448 16:35:35.598476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31450 16:35:35.631714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31452 16:35:35.632356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31453 16:35:35.663875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31455 16:35:35.664323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31456 16:35:35.695963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31458 16:35:35.696402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31459 16:35:35.728192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31460 16:35:35.728596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31462 16:35:35.760587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31463 16:35:35.760989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31465 16:35:35.794023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31467 16:35:35.794447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31468 16:35:35.826337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31470 16:35:35.826745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31471 16:35:35.858662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31472 16:35:35.859055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31474 16:35:35.892947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31476 16:35:35.893495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31477 16:35:35.924001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31478 16:35:35.924449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31480 16:35:35.956028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31482 16:35:35.956571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31483 16:35:35.988761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31484 16:35:35.989224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31486 16:35:36.020870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31487 16:35:36.021310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31489 16:35:36.053297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31490 16:35:36.053746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31492 16:35:36.085299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31494 16:35:36.085754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31495 16:35:36.117967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31496 16:35:36.118433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31498 16:35:36.150646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31499 16:35:36.151045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31501 16:35:36.183296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31503 16:35:36.183853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31504 16:35:36.215316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31505 16:35:36.215774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31507 16:35:36.247829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31508 16:35:36.248237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31510 16:35:36.279639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31511 16:35:36.280042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31513 16:35:36.311923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31515 16:35:36.312347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31516 16:35:36.343560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31517 16:35:36.344036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31519 16:35:36.375234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31520 16:35:36.375666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31522 16:35:36.406931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31523 16:35:36.407221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31525 16:35:36.439340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31526 16:35:36.439795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31528 16:35:36.470736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31529 16:35:36.471120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31531 16:35:36.502563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31532 16:35:36.502937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31534 16:35:36.533821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31535 16:35:36.534108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31537 16:35:36.565633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31539 16:35:36.566089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31540 16:35:36.597412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31541 16:35:36.597899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31543 16:35:36.629385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31545 16:35:36.629866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31546 16:35:36.660553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31547 16:35:36.660902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31549 16:35:36.691658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31550 16:35:36.692093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31552 16:35:36.723443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31553 16:35:36.723836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31555 16:35:36.755416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31556 16:35:36.755884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31558 16:35:36.787701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31559 16:35:36.788168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31561 16:35:36.820829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31562 16:35:36.821291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31564 16:35:36.853243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31566 16:35:36.853881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31567 16:35:36.885434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31568 16:35:36.885855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31570 16:35:36.917793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31572 16:35:36.918228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31573 16:35:36.949900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31575 16:35:36.950518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31576 16:35:36.981895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31578 16:35:36.982446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31579 16:35:37.014991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31580 16:35:37.015278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31582 16:35:37.047094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31584 16:35:37.047445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31585 16:35:37.079130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31586 16:35:37.079483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31588 16:35:37.111417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31589 16:35:37.111766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31591 16:35:37.143323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31592 16:35:37.143606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31594 16:35:37.175856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31596 16:35:37.176149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31597 16:35:37.208301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31598 16:35:37.208672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31600 16:35:37.239848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31602 16:35:37.240267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31603 16:35:37.271263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31604 16:35:37.271677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31606 16:35:37.303076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31607 16:35:37.303484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31609 16:35:37.335217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31611 16:35:37.335666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31612 16:35:37.367053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31614 16:35:37.367479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31615 16:35:37.399092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31617 16:35:37.399500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31618 16:35:37.430887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31619 16:35:37.431295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31621 16:35:37.463038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31622 16:35:37.463444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31624 16:35:37.495156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31625 16:35:37.495561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31627 16:35:37.527113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31629 16:35:37.527528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31630 16:35:37.558966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31631 16:35:37.559352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31633 16:35:37.591892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31635 16:35:37.592307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31636 16:35:37.623089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31637 16:35:37.623492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31639 16:35:37.655929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31641 16:35:37.656347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31642 16:35:37.687839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31643 16:35:37.688237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31645 16:35:37.719534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31647 16:35:37.719968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31648 16:35:37.751912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31650 16:35:37.752349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31651 16:35:37.783616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31653 16:35:37.784053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31654 16:35:37.815122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31655 16:35:37.815545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31657 16:35:37.848528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31659 16:35:37.848971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31660 16:35:37.881091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31661 16:35:37.881500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31663 16:35:37.913127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31664 16:35:37.913590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31666 16:35:37.945429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31667 16:35:37.945911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31669 16:35:37.977535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31670 16:35:37.977945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31672 16:35:38.009657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31674 16:35:38.010208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31675 16:35:38.041621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31676 16:35:38.041917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31678 16:35:38.074335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31680 16:35:38.074907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31681 16:35:38.106675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31682 16:35:38.107093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31684 16:35:38.139115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31686 16:35:38.139651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31687 16:35:38.171452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31688 16:35:38.171847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31690 16:35:38.203853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31692 16:35:38.204473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31693 16:35:38.235392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31694 16:35:38.235862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31696 16:35:38.267815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31698 16:35:38.268371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31699 16:35:38.299271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31700 16:35:38.299742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31702 16:35:38.332539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31703 16:35:38.332993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31705 16:35:38.364791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31707 16:35:38.365332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31708 16:35:38.396106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31709 16:35:38.396560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31711 16:35:38.427662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31712 16:35:38.428048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31714 16:35:38.459449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31715 16:35:38.459892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31717 16:35:38.490449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31718 16:35:38.490737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
31720 16:35:38.521776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
31721 16:35:38.522061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
31723 16:35:38.567612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
31725 16:35:38.568047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
31726 16:35:38.605714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
31728 16:35:38.606178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
31729 16:35:38.637915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
31731 16:35:38.638484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
31732 16:35:38.669977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
31733 16:35:38.670376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
31735 16:35:38.700931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
31736 16:35:38.701219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
31738 16:35:38.731860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
31739 16:35:38.732269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
31741 16:35:38.764429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
31743 16:35:38.764867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
31744 16:35:38.796323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
31746 16:35:38.796764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
31747 16:35:38.828285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
31749 16:35:38.828723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
31750 16:35:38.860441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
31752 16:35:38.860886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
31753 16:35:38.892876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
31754 16:35:38.893290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
31756 16:35:38.924019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
31757 16:35:38.924386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
31759 16:35:38.955414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
31760 16:35:38.955814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
31762 16:35:38.986943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
31764 16:35:38.987244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
31765 16:35:39.018240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
31767 16:35:39.018650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
31768 16:35:39.060172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
31769 16:35:39.060451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
31771 16:35:39.094211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
31773 16:35:39.094751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
31774 16:35:39.126817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
31775 16:35:39.127226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
31777 16:35:39.159474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
31778 16:35:39.159884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
31780 16:35:39.192023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
31782 16:35:39.192559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
31783 16:35:39.224203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
31784 16:35:39.224568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
31786 16:35:39.257167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
31788 16:35:39.257673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
31789 16:35:39.288520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
31790 16:35:39.288872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
31792 16:35:39.320305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
31793 16:35:39.320654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
31795 16:35:39.352428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
31797 16:35:39.352852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
31798 16:35:39.385019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
31800 16:35:39.385463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
31801 16:35:39.416456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
31802 16:35:39.416821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
31804 16:35:39.448593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
31806 16:35:39.449019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
31807 16:35:39.480205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
31809 16:35:39.480621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
31810 16:35:39.515077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
31811 16:35:39.515428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
31813 16:35:39.552292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
31814 16:35:39.552659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
31816 16:35:39.585117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
31817 16:35:39.585485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
31819 16:35:39.620426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
31820 16:35:39.620825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
31822 16:35:39.664446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
31823 16:35:39.664732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
31825 16:35:39.696430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
31826 16:35:39.696707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
31828 16:35:39.728763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
31829 16:35:39.729132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
31831 16:35:39.760504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
31832 16:35:39.760869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
31834 16:35:39.792194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
31835 16:35:39.792552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
31837 16:35:39.823907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
31838 16:35:39.824364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
31840 16:35:39.855918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
31841 16:35:39.856368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
31843 16:35:39.887710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
31844 16:35:39.888166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
31846 16:35:39.920707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
31847 16:35:39.921172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
31849 16:35:39.953524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
31850 16:35:39.954016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
31852 16:35:39.985086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
31854 16:35:39.985540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
31855 16:35:40.016427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
31856 16:35:40.016827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
31858 16:35:40.048484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
31859 16:35:40.048887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
31861 16:35:40.081284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
31863 16:35:40.081740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
31864 16:35:40.113274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
31865 16:35:40.113753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
31867 16:35:40.145965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
31868 16:35:40.146316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
31870 16:35:40.177710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
31871 16:35:40.178060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
31873 16:35:40.209488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
31874 16:35:40.209767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
31876 16:35:40.241431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
31877 16:35:40.241780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
31879 16:35:40.274405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
31880 16:35:40.274752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
31882 16:35:40.307213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
31883 16:35:40.307561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
31885 16:35:40.339376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
31886 16:35:40.339829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
31888 16:35:40.371451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
31890 16:35:40.372023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
31891 16:35:40.403881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
31893 16:35:40.404453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
31894 16:35:40.436291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
31895 16:35:40.436606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
31897 16:35:40.468338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
31898 16:35:40.468611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
31900 16:35:40.500271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
31901 16:35:40.500633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
31903 16:35:40.531894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
31904 16:35:40.532252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
31906 16:35:40.563236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
31908 16:35:40.563515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
31909 16:35:40.595291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
31910 16:35:40.595567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
31912 16:35:40.628099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
31913 16:35:40.628470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
31915 16:35:40.660023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
31916 16:35:40.660389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
31918 16:35:40.691944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
31919 16:35:40.692361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
31921 16:35:40.724945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
31922 16:35:40.725349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
31924 16:35:40.757071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
31926 16:35:40.757514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
31927 16:35:40.790802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
31928 16:35:40.791266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
31930 16:35:40.823622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
31932 16:35:40.824362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
31933 16:35:40.855412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
31934 16:35:40.855888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
31936 16:35:40.887325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
31937 16:35:40.887814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
31939 16:35:40.920090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
31940 16:35:40.920610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
31942 16:35:40.951918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
31944 16:35:40.952452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
31945 16:35:40.985194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
31946 16:35:40.985714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
31948 16:35:41.017816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
31949 16:35:41.018296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
31951 16:35:41.049427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
31952 16:35:41.049846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
31954 16:35:41.081953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
31955 16:35:41.082385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
31957 16:35:41.114161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
31959 16:35:41.114623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
31960 16:35:41.147219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
31961 16:35:41.147692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
31963 16:35:41.180558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
31964 16:35:41.181018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
31966 16:35:41.212952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
31968 16:35:41.213496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
31969 16:35:41.244887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
31970 16:35:41.245210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
31972 16:35:41.276253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
31973 16:35:41.276530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
31975 16:35:41.307391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
31976 16:35:41.307745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
31978 16:35:41.340194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
31979 16:35:41.340470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
31981 16:35:41.372101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
31982 16:35:41.372377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
31984 16:35:41.404059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
31985 16:35:41.404453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
31987 16:35:41.435929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
31989 16:35:41.436472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
31990 16:35:41.468146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
31991 16:35:41.468610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
31993 16:35:41.500159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
31994 16:35:41.500532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
31996 16:35:41.532027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
31997 16:35:41.532369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
31999 16:35:41.564285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32000 16:35:41.564642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32002 16:35:41.596067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32003 16:35:41.596548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32005 16:35:41.627614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32006 16:35:41.628023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32008 16:35:41.659682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32010 16:35:41.660131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32011 16:35:41.692088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32012 16:35:41.692543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32014 16:35:41.724043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32015 16:35:41.724486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32017 16:35:41.756508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32018 16:35:41.756918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32020 16:35:41.788179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32021 16:35:41.788584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32023 16:35:41.820211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32024 16:35:41.820675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32026 16:35:41.852470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32028 16:35:41.853187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32029 16:35:41.884700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32030 16:35:41.885154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32032 16:35:41.917922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32033 16:35:41.918369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32035 16:35:41.932171 <47>[ 404.538278] systemd-journald[105]: Sent WATCHDOG=1 notification.
32036 16:35:41.955467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32037 16:35:41.955915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32039 16:35:41.988143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32041 16:35:41.988678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32042 16:35:42.019963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32044 16:35:42.020572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32045 16:35:42.053043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32046 16:35:42.053495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32048 16:35:42.084785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32050 16:35:42.085310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32051 16:35:42.116515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32052 16:35:42.116994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32054 16:35:42.147923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32055 16:35:42.148303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32057 16:35:42.179520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32058 16:35:42.179867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32060 16:35:42.212313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32061 16:35:42.212663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32063 16:35:42.244385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32065 16:35:42.244811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32066 16:35:42.276366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32067 16:35:42.276718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32069 16:35:42.307336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32071 16:35:42.307765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32072 16:35:42.339063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32073 16:35:42.339417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32075 16:35:42.371311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32076 16:35:42.371658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32078 16:35:42.403479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32080 16:35:42.403901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32081 16:35:42.435667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32082 16:35:42.436125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32084 16:35:42.467157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32086 16:35:42.467599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32087 16:35:42.498160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32089 16:35:42.498666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32090 16:35:42.529366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32091 16:35:42.529709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32093 16:35:42.560793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32094 16:35:42.561135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32096 16:35:42.592880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32098 16:35:42.593374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32099 16:35:42.624410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32101 16:35:42.624908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32102 16:35:42.655817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32103 16:35:42.656225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32105 16:35:42.687686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32106 16:35:42.688006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32108 16:35:42.719999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32109 16:35:42.720277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32111 16:35:42.751985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32112 16:35:42.752335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32114 16:35:42.783514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32115 16:35:42.783859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32117 16:35:42.815169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32119 16:35:42.815583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32120 16:35:42.846318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32122 16:35:42.846814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32123 16:35:42.877739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32124 16:35:42.878095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32126 16:35:42.909578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32127 16:35:42.909957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32129 16:35:42.941639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32130 16:35:42.942017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32132 16:35:42.972873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32134 16:35:42.973302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32135 16:35:43.004805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32137 16:35:43.005255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32138 16:35:43.036112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32139 16:35:43.036470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32141 16:35:43.067047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32142 16:35:43.067397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32144 16:35:43.099116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32146 16:35:43.099558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32147 16:35:43.131180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32148 16:35:43.131538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32150 16:35:43.162497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32152 16:35:43.162923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32153 16:35:43.193627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32154 16:35:43.193994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32156 16:35:43.225695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32158 16:35:43.226196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32159 16:35:43.256926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32161 16:35:43.257420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32162 16:35:43.289198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32163 16:35:43.289564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32165 16:35:43.321900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32167 16:35:43.322352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32168 16:35:43.354689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32169 16:35:43.355098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32171 16:35:43.387852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32173 16:35:43.388409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32174 16:35:43.419880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32175 16:35:43.420335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32177 16:35:43.452224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32178 16:35:43.452636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32180 16:35:43.484707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32181 16:35:43.485076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32183 16:35:43.516177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32184 16:35:43.516640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32186 16:35:43.547267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32187 16:35:43.547706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32189 16:35:43.578660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32190 16:35:43.579069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32192 16:35:43.610752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32193 16:35:43.611161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32195 16:35:43.643838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32196 16:35:43.644247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32198 16:35:43.709915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32199 16:35:43.710396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32201 16:35:43.764767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32202 16:35:43.765138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32204 16:35:43.796907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32205 16:35:43.797365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32207 16:35:43.830346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32209 16:35:43.830814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32210 16:35:43.862860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32211 16:35:43.863224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32213 16:35:43.895911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32215 16:35:43.896453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32216 16:35:43.927852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32218 16:35:43.928292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32219 16:35:43.960640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32220 16:35:43.961052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32222 16:35:43.992539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32224 16:35:43.993029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32225 16:35:44.025259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32226 16:35:44.025677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32228 16:35:44.058006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32229 16:35:44.058429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32231 16:35:44.090531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32232 16:35:44.090927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32234 16:35:44.121906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32235 16:35:44.122265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32237 16:35:44.154386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32239 16:35:44.154893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32240 16:35:44.188202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32242 16:35:44.188764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32243 16:35:44.220305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32244 16:35:44.220717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32246 16:35:44.252794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32247 16:35:44.253207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32249 16:35:44.285058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32250 16:35:44.285462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32252 16:35:44.317467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32253 16:35:44.317890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32255 16:35:44.351292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32257 16:35:44.351734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32258 16:35:44.383909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32259 16:35:44.384372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32261 16:35:44.416224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32263 16:35:44.416774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32264 16:35:44.448023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32265 16:35:44.448380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32267 16:35:44.479350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32269 16:35:44.479789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32270 16:35:44.511356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32271 16:35:44.511723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32273 16:35:44.544171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32274 16:35:44.544531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32276 16:35:44.577008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32277 16:35:44.577381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32279 16:35:44.609734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32280 16:35:44.610116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32282 16:35:44.641577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32283 16:35:44.641967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32285 16:35:44.674314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32287 16:35:44.674815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32288 16:35:44.706915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32289 16:35:44.707312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32291 16:35:44.739717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32293 16:35:44.740167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32294 16:35:44.772274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32295 16:35:44.772688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32297 16:35:44.805133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32298 16:35:44.805507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32300 16:35:44.837347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32301 16:35:44.837817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32303 16:35:44.870227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32305 16:35:44.870650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32306 16:35:44.902985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32307 16:35:44.903253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32309 16:35:44.936126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32310 16:35:44.936480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32312 16:35:44.968430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32314 16:35:44.968864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32315 16:35:45.000228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32317 16:35:45.000656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32318 16:35:45.031841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32319 16:35:45.032189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32321 16:35:45.065392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32322 16:35:45.065799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32324 16:35:45.098444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32326 16:35:45.099050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32327 16:35:45.131039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32328 16:35:45.131499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32330 16:35:45.163388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32331 16:35:45.163858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32333 16:35:45.195528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32334 16:35:45.195997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32336 16:35:45.227443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32337 16:35:45.228011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32339 16:35:45.259579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32340 16:35:45.260057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32342 16:35:45.291025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32344 16:35:45.291572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32345 16:35:45.321899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32347 16:35:45.322425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32348 16:35:45.352680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32349 16:35:45.353131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32351 16:35:45.383687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32352 16:35:45.384147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32354 16:35:45.415056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32356 16:35:45.415601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32357 16:35:45.447842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32358 16:35:45.448286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32360 16:35:45.479509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32361 16:35:45.479885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32363 16:35:45.511196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32365 16:35:45.511485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32366 16:35:45.543054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32367 16:35:45.543499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32369 16:35:45.573941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32370 16:35:45.574376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32372 16:35:45.607114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32373 16:35:45.607569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32375 16:35:45.639082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32376 16:35:45.639523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32378 16:35:45.671215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32379 16:35:45.671658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32381 16:35:45.703196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32382 16:35:45.703592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32384 16:35:45.735230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32385 16:35:45.735688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32387 16:35:45.767344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32388 16:35:45.767800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32390 16:35:45.799796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32391 16:35:45.800277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32393 16:35:45.833045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32394 16:35:45.833503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32396 16:35:45.865381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32397 16:35:45.865859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32399 16:35:45.897460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32401 16:35:45.897923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32402 16:35:45.929404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32403 16:35:45.929674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32405 16:35:45.963405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32406 16:35:45.963782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32408 16:35:45.995787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32409 16:35:45.996209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32411 16:35:46.029137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32412 16:35:46.029508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32414 16:35:46.061284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32415 16:35:46.061561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32417 16:35:46.093054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32418 16:35:46.093331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32420 16:35:46.124989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32422 16:35:46.125265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32423 16:35:46.156974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32424 16:35:46.157251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32426 16:35:46.188345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32427 16:35:46.188632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32429 16:35:46.220112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32430 16:35:46.220470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32432 16:35:46.252438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32434 16:35:46.252737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32435 16:35:46.283702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32436 16:35:46.283986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32438 16:35:46.316096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32439 16:35:46.316539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32441 16:35:46.348113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32442 16:35:46.348439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32444 16:35:46.379756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32446 16:35:46.380204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32447 16:35:46.411290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32448 16:35:46.411569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32450 16:35:46.443629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32451 16:35:46.443967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32453 16:35:46.482172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32455 16:35:46.482525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32456 16:35:46.514693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32457 16:35:46.515000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32459 16:35:46.546709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32460 16:35:46.547159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32462 16:35:46.578885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32463 16:35:46.579220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32465 16:35:46.611144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32467 16:35:46.611446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32468 16:35:46.643978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32469 16:35:46.644394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32471 16:35:46.676259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32472 16:35:46.676697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32474 16:35:46.708491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32476 16:35:46.709052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32477 16:35:46.741110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32478 16:35:46.741563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32480 16:35:46.772915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32482 16:35:46.773459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32483 16:35:46.805825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32484 16:35:46.806253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32486 16:35:46.840034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32487 16:35:46.840449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32489 16:35:46.872195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32490 16:35:46.872599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32492 16:35:46.904231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32493 16:35:46.904685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32495 16:35:46.936055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32496 16:35:46.936496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32498 16:35:46.969612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32499 16:35:46.970077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32501 16:35:47.002731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32502 16:35:47.003176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32504 16:35:47.038383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32506 16:35:47.038831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32507 16:35:47.071340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32508 16:35:47.071747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32510 16:35:47.104020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32511 16:35:47.104507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32513 16:35:47.136527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32514 16:35:47.136931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32516 16:35:47.168529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32517 16:35:47.168810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32519 16:35:47.205056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32520 16:35:47.205502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32522 16:35:47.237158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32523 16:35:47.237596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32525 16:35:47.269422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32526 16:35:47.269878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32528 16:35:47.301663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32529 16:35:47.302084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32531 16:35:47.333782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32532 16:35:47.334229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32534 16:35:47.368433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32536 16:35:47.369126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32537 16:35:47.401915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32538 16:35:47.402409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32540 16:35:47.433836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32541 16:35:47.434217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32543 16:35:47.465786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32544 16:35:47.466249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32546 16:35:47.497462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32547 16:35:47.497918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32549 16:35:47.529917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32550 16:35:47.530390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32552 16:35:47.567796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32553 16:35:47.568247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32555 16:35:47.603007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32556 16:35:47.603372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32558 16:35:47.645496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32559 16:35:47.645881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32561 16:35:47.678604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32562 16:35:47.678978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32564 16:35:47.710631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32565 16:35:47.711056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32567 16:35:47.754440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32569 16:35:47.754958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32570 16:35:47.787971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32571 16:35:47.788357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32573 16:35:47.820196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32575 16:35:47.820716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32576 16:35:47.852204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32577 16:35:47.852557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32579 16:35:47.885353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32580 16:35:47.885679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32582 16:35:47.919202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32584 16:35:47.919704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32585 16:35:47.952451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32586 16:35:47.952799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32588 16:35:47.986252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32590 16:35:47.986712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32591 16:35:48.019442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32592 16:35:48.019805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32594 16:35:48.051323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32595 16:35:48.051689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32597 16:35:48.085581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32598 16:35:48.085965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32600 16:35:48.119544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32601 16:35:48.120027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32603 16:35:48.152869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32604 16:35:48.153152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32606 16:35:48.186316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32608 16:35:48.186599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32609 16:35:48.219670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32610 16:35:48.220140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32612 16:35:48.253400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32613 16:35:48.253791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32615 16:35:48.287592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32616 16:35:48.287975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32618 16:35:48.320530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32620 16:35:48.321061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32621 16:35:48.352996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32622 16:35:48.353302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32624 16:35:48.385554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32625 16:35:48.385856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32627 16:35:48.419233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32628 16:35:48.419757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32630 16:35:48.453309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32632 16:35:48.454041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32633 16:35:48.486961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32634 16:35:48.487375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32636 16:35:48.520383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32637 16:35:48.520798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32639 16:35:48.553410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32641 16:35:48.553868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32642 16:35:48.586153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32644 16:35:48.586778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32645 16:35:48.619445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32646 16:35:48.619882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32648 16:35:48.652629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32650 16:35:48.653157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32651 16:35:48.685952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32652 16:35:48.686309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32654 16:35:48.718827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32655 16:35:48.719296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32657 16:35:48.751681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32658 16:35:48.752076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32660 16:35:48.784407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32661 16:35:48.784893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32663 16:35:48.844973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32665 16:35:48.845422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32666 16:35:48.880730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32667 16:35:48.881164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32669 16:35:48.914095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32670 16:35:48.914567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32672 16:35:48.946665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32674 16:35:48.947168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32675 16:35:48.992181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32676 16:35:48.992670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32678 16:35:49.025227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32680 16:35:49.025817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32681 16:35:49.057538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32682 16:35:49.058019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32684 16:35:49.089934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32685 16:35:49.090367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32687 16:35:49.123252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32688 16:35:49.123714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32690 16:35:49.157276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32691 16:35:49.157752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32693 16:35:49.191995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32695 16:35:49.192490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32696 16:35:49.225299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32698 16:35:49.225630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32699 16:35:49.257227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32700 16:35:49.257551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32702 16:35:49.288780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32704 16:35:49.289099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32705 16:35:49.320084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32706 16:35:49.320744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32708 16:35:49.352645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32709 16:35:49.353164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32711 16:35:49.385385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32713 16:35:49.386044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32714 16:35:49.418817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32716 16:35:49.419493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32717 16:35:49.452359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32719 16:35:49.453071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
32720 16:35:49.485274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
32721 16:35:49.485700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
32723 16:35:49.518190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
32725 16:35:49.518724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
32726 16:35:49.551282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
32727 16:35:49.551731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
32729 16:35:49.583830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
32730 16:35:49.584332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
32732 16:35:49.617937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
32733 16:35:49.618404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
32735 16:35:49.651573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
32737 16:35:49.652118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
32738 16:35:49.684947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
32740 16:35:49.685492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
32741 16:35:49.719498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
32743 16:35:49.720041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
32744 16:35:49.753652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
32745 16:35:49.754080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
32747 16:35:49.787476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
32748 16:35:49.787906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
32750 16:35:49.821961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
32751 16:35:49.822416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
32753 16:35:49.855824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
32755 16:35:49.856383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
32756 16:35:49.890224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
32758 16:35:49.890873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
32759 16:35:49.923277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
32760 16:35:49.923663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
32762 16:35:49.956253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
32763 16:35:49.956535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
32765 16:35:49.989835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
32767 16:35:49.990113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
32768 16:35:50.023420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
32769 16:35:50.023728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
32771 16:35:50.056978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
32772 16:35:50.057350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
32774 16:35:50.089356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
32775 16:35:50.089767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
32777 16:35:50.121755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
32778 16:35:50.122276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
32780 16:35:50.154316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
32782 16:35:50.154916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
32783 16:35:50.187245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
32784 16:35:50.187735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
32786 16:35:50.220595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
32788 16:35:50.221165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
32789 16:35:50.256814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
32790 16:35:50.257222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
32792 16:35:50.290286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
32794 16:35:50.290891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
32795 16:35:50.323330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
32797 16:35:50.323977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
32798 16:35:50.355460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
32800 16:35:50.356032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
32801 16:35:50.388098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
32802 16:35:50.388616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
32804 16:35:50.420573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
32805 16:35:50.421134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
32807 16:35:50.452314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
32808 16:35:50.452755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
32810 16:35:50.484270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
32812 16:35:50.484770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
32813 16:35:50.515997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
32815 16:35:50.516629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
32816 16:35:50.549399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
32818 16:35:50.549948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
32819 16:35:50.585827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
32820 16:35:50.586308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
32822 16:35:50.618948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
32824 16:35:50.619545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
32825 16:35:50.651879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
32826 16:35:50.652344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
32828 16:35:50.685438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
32830 16:35:50.685891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
32831 16:35:50.717466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
32832 16:35:50.717898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
32834 16:35:50.755252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
32835 16:35:50.755657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
32837 16:35:50.789499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
32838 16:35:50.789931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
32840 16:35:50.823011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
32841 16:35:50.823395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
32843 16:35:50.858212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
32845 16:35:50.858794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
32846 16:35:50.892123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
32847 16:35:50.892626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
32849 16:35:50.931445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
32850 16:35:50.931941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
32852 16:35:50.967695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
32854 16:35:50.968301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
32855 16:35:51.006758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
32856 16:35:51.007206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
32858 16:35:51.040139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
32859 16:35:51.040633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
32861 16:35:51.071939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
32863 16:35:51.072579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
32864 16:35:51.104158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
32865 16:35:51.104632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
32867 16:35:51.136587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
32868 16:35:51.137054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
32870 16:35:51.168960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
32872 16:35:51.169597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
32873 16:35:51.201332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
32875 16:35:51.201776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
32876 16:35:51.233162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
32877 16:35:51.233482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
32879 16:35:51.265158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
32881 16:35:51.265464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
32882 16:35:51.300920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
32883 16:35:51.301209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
32885 16:35:51.333124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
32886 16:35:51.333419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
32888 16:35:51.364814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
32889 16:35:51.365095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
32891 16:35:51.396392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
32892 16:35:51.396790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
32894 16:35:51.427684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
32895 16:35:51.428075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
32897 16:35:51.465087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
32898 16:35:51.465431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
32900 16:35:51.497449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
32902 16:35:51.497765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
32903 16:35:51.529545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
32904 16:35:51.529960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
32906 16:35:51.562539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
32908 16:35:51.563169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
32909 16:35:51.595437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
32911 16:35:51.595900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
32912 16:35:51.630193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
32913 16:35:51.630648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
32915 16:35:51.664695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
32917 16:35:51.665257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
32918 16:35:51.696987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
32920 16:35:51.697425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
32921 16:35:51.729037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
32922 16:35:51.729452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
32924 16:35:51.761040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
32926 16:35:51.761601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
32927 16:35:51.793174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
32928 16:35:51.793619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
32930 16:35:51.831543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
32932 16:35:51.832100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
32933 16:35:51.863960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
32934 16:35:51.864431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
32936 16:35:51.896686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
32937 16:35:51.897150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
32939 16:35:51.928459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
32941 16:35:51.929050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
32942 16:35:51.965666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
32943 16:35:51.966150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
32945 16:35:52.004107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
32947 16:35:52.004697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
32948 16:35:52.036360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
32949 16:35:52.036816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
32951 16:35:52.068214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
32952 16:35:52.068684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
32954 16:35:52.100132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
32955 16:35:52.100607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
32957 16:35:52.132381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
32959 16:35:52.133004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
32960 16:35:52.170767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
32962 16:35:52.171325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
32963 16:35:52.203254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
32964 16:35:52.203659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
32966 16:35:52.235746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
32967 16:35:52.236146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
32969 16:35:52.268359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
32970 16:35:52.268813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
32972 16:35:52.300600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
32974 16:35:52.301220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
32975 16:35:52.332969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
32976 16:35:52.333429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
32978 16:35:52.371746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
32980 16:35:52.372293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
32981 16:35:52.404634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
32983 16:35:52.405190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
32984 16:35:52.437502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
32986 16:35:52.437970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
32987 16:35:52.469434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
32988 16:35:52.469911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
32990 16:35:52.500686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
32991 16:35:52.501147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
32993 16:35:52.534994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
32994 16:35:52.535458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
32996 16:35:52.567864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
32998 16:35:52.568447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
32999 16:35:52.599570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33000 16:35:52.599971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33002 16:35:52.631859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33004 16:35:52.632422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33005 16:35:52.664274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33006 16:35:52.664700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33008 16:35:52.698932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33009 16:35:52.699338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33011 16:35:52.731188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33012 16:35:52.731672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33014 16:35:52.763499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33015 16:35:52.763974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33017 16:35:52.796146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33018 16:35:52.796629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33020 16:35:52.828324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33021 16:35:52.828791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33023 16:35:52.860517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33024 16:35:52.860980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33026 16:35:52.894661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33027 16:35:52.895135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33029 16:35:52.927284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33030 16:35:52.927745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33032 16:35:52.959266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33034 16:35:52.959704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33035 16:35:52.991313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33036 16:35:52.991722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33038 16:35:53.023567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33039 16:35:53.023971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33041 16:35:53.057810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33042 16:35:53.058221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33044 16:35:53.096036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33045 16:35:53.096509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33047 16:35:53.128165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33048 16:35:53.128625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33050 16:35:53.160299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33051 16:35:53.160758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33053 16:35:53.192257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33054 16:35:53.192738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33056 16:35:53.225579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33058 16:35:53.226316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33059 16:35:53.259313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33060 16:35:53.259794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33062 16:35:53.291338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33064 16:35:53.291894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33065 16:35:53.323384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33067 16:35:53.323934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33068 16:35:53.355416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33069 16:35:53.355865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33071 16:35:53.387333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33072 16:35:53.387784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33074 16:35:53.421491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33075 16:35:53.421967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33077 16:35:53.454117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33079 16:35:53.454664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33080 16:35:53.486804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33081 16:35:53.487256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33083 16:35:53.518655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33084 16:35:53.519125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33086 16:35:53.550321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33088 16:35:53.550894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33089 16:35:53.584099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33090 16:35:53.584476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33092 16:35:53.619496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33093 16:35:53.619902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33095 16:35:53.651894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33096 16:35:53.652294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33098 16:35:53.684389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33099 16:35:53.684860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33101 16:35:53.717067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33102 16:35:53.717494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33104 16:35:53.749714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33106 16:35:53.750285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33107 16:35:53.782780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33108 16:35:53.783244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33110 16:35:53.815422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33111 16:35:53.815827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33113 16:35:53.847956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33114 16:35:53.848353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33116 16:35:53.880480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33117 16:35:53.880953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33119 16:35:53.927634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33121 16:35:53.928212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33122 16:35:53.973581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33124 16:35:53.974173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33125 16:35:54.006372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33127 16:35:54.007001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33128 16:35:54.038679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33129 16:35:54.039155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33131 16:35:54.070867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33133 16:35:54.071430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33134 16:35:54.102129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33135 16:35:54.102542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33137 16:35:54.135233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33138 16:35:54.135716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33140 16:35:54.168095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33142 16:35:54.168659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33143 16:35:54.199880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33144 16:35:54.200303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33146 16:35:54.231974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33147 16:35:54.232443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33149 16:35:54.264190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33150 16:35:54.264659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33152 16:35:54.296588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33153 16:35:54.297032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33155 16:35:54.328739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33156 16:35:54.329209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33158 16:35:54.360607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33159 16:35:54.361014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33161 16:35:54.393019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33163 16:35:54.393659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33164 16:35:54.425098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33165 16:35:54.425549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33167 16:35:54.456659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33168 16:35:54.457195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33170 16:35:54.489931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33171 16:35:54.490371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33173 16:35:54.522637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33175 16:35:54.523268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33176 16:35:54.553991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33177 16:35:54.554475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33179 16:35:54.585623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33180 16:35:54.586060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33182 16:35:54.618308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33184 16:35:54.618826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33185 16:35:54.657654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33186 16:35:54.658016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33188 16:35:54.689164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33189 16:35:54.689507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33191 16:35:54.739512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33192 16:35:54.739899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33194 16:35:54.772481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33195 16:35:54.772949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33197 16:35:54.805422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33198 16:35:54.805862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33200 16:35:54.844253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33201 16:35:54.844731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33203 16:35:54.876894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33204 16:35:54.877366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33206 16:35:54.911480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33208 16:35:54.912112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33209 16:35:54.945120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33210 16:35:54.945601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33212 16:35:54.976732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33213 16:35:54.977204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33215 16:35:55.009384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33216 16:35:55.009872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33218 16:35:55.041472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33219 16:35:55.041949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33221 16:35:55.074408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33223 16:35:55.074863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33224 16:35:55.107269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33225 16:35:55.107731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33227 16:35:55.140851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33228 16:35:55.141322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33230 16:35:55.174017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33231 16:35:55.174553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33233 16:35:55.206792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33234 16:35:55.207273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33236 16:35:55.239780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33237 16:35:55.240253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33239 16:35:55.277246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33240 16:35:55.277666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33242 16:35:55.309339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33243 16:35:55.309796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33245 16:35:55.341879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33246 16:35:55.342338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33248 16:35:55.374571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33249 16:35:55.375051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33251 16:35:55.406867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33252 16:35:55.407348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33254 16:35:55.438028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33255 16:35:55.438485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33257 16:35:55.469140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33258 16:35:55.469585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33260 16:35:55.500950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33262 16:35:55.501502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33263 16:35:55.533023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33264 16:35:55.533531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33266 16:35:55.569103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33267 16:35:55.569573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33269 16:35:55.603671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33270 16:35:55.604139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33272 16:35:55.635276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33273 16:35:55.635753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33275 16:35:55.667116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33276 16:35:55.667597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33278 16:35:55.699231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33279 16:35:55.699688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33281 16:35:55.737422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33282 16:35:55.737838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33284 16:35:55.770227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33286 16:35:55.770689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33287 16:35:55.802937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33288 16:35:55.803340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33290 16:35:55.836050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33291 16:35:55.836506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33293 16:35:55.871481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33294 16:35:55.872033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33296 16:35:55.907006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33297 16:35:55.907417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33299 16:35:55.942792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33301 16:35:55.943395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33302 16:35:55.979912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33303 16:35:55.980338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33305 16:35:56.015888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33307 16:35:56.016329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33308 16:35:56.049410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33309 16:35:56.049912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33311 16:35:56.085181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33312 16:35:56.085571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33314 16:35:56.118151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33316 16:35:56.118561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33317 16:35:56.151093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33318 16:35:56.151497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33320 16:35:56.183212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33321 16:35:56.183670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33323 16:35:56.215427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33324 16:35:56.215835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33326 16:35:56.251362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33327 16:35:56.251812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33329 16:35:56.285600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33330 16:35:56.286023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33332 16:35:56.317927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33333 16:35:56.318377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33335 16:35:56.350302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33337 16:35:56.350843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33338 16:35:56.383105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33339 16:35:56.383574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33341 16:35:56.415160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33342 16:35:56.415613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33344 16:35:56.448713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33345 16:35:56.449166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33347 16:35:56.481532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33348 16:35:56.482011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33350 16:35:56.513543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33351 16:35:56.514030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33353 16:35:56.545935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33355 16:35:56.546541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33356 16:35:56.578205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33358 16:35:56.578670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33359 16:35:56.611435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33360 16:35:56.611847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33362 16:35:56.644561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33363 16:35:56.645014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33365 16:35:56.677273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33367 16:35:56.677715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33368 16:35:56.708738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33369 16:35:56.709022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33371 16:35:56.740900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33373 16:35:56.741402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33374 16:35:56.772936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33375 16:35:56.773328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33377 16:35:56.806389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33378 16:35:56.806808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33380 16:35:56.838899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33381 16:35:56.839335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33383 16:35:56.871125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33385 16:35:56.871670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33386 16:35:56.903079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33388 16:35:56.903624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33389 16:35:56.935325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33391 16:35:56.935760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33392 16:35:56.968845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33393 16:35:56.969315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33395 16:35:57.001498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33397 16:35:57.002059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33398 16:35:57.033566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33399 16:35:57.034042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33401 16:35:57.065724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33403 16:35:57.066305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33404 16:35:57.097860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33406 16:35:57.098410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33407 16:35:57.130011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33408 16:35:57.130479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33410 16:35:57.163505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33411 16:35:57.163906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33413 16:35:57.196616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33414 16:35:57.197083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33416 16:35:57.229058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33417 16:35:57.229459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33419 16:35:57.261148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33421 16:35:57.261721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33422 16:35:57.292118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33423 16:35:57.292540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33425 16:35:57.324475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33427 16:35:57.325005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33428 16:35:57.357760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33429 16:35:57.358057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33431 16:35:57.390686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33433 16:35:57.391328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33434 16:35:57.422182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33436 16:35:57.422788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33437 16:35:57.454883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33438 16:35:57.455353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33440 16:35:57.487575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33441 16:35:57.488022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33443 16:35:57.520775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33445 16:35:57.521325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33446 16:35:57.553027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33447 16:35:57.553431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33449 16:35:57.584452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33451 16:35:57.584999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33452 16:35:57.615471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33453 16:35:57.615934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33455 16:35:57.646817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33456 16:35:57.647267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33458 16:35:57.679201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33459 16:35:57.679791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33461 16:35:57.711729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33462 16:35:57.712190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33464 16:35:57.743221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33465 16:35:57.743572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33467 16:35:57.774426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33469 16:35:57.774950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33470 16:35:57.805607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33471 16:35:57.806087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33473 16:35:57.837344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33474 16:35:57.837806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33476 16:35:57.870651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33477 16:35:57.871099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33479 16:35:57.902916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33481 16:35:57.903465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33482 16:35:57.934732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33483 16:35:57.935127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33485 16:35:57.966223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33487 16:35:57.966647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33488 16:35:57.998705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33489 16:35:57.999156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33491 16:35:58.031287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33492 16:35:58.031691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33494 16:35:58.065303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33495 16:35:58.065697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33497 16:35:58.098389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33499 16:35:58.098875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33500 16:35:58.129839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33501 16:35:58.130195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33503 16:35:58.162774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33504 16:35:58.163157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33506 16:35:58.194628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33508 16:35:58.195090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33509 16:35:58.227967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33510 16:35:58.228321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33512 16:35:58.259716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33513 16:35:58.260110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33515 16:35:58.290764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33516 16:35:58.291117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33518 16:35:58.322303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33520 16:35:58.322762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33521 16:35:58.353267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33522 16:35:58.353617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33524 16:35:58.385457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33525 16:35:58.385809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33527 16:35:58.417033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33528 16:35:58.417312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33530 16:35:58.448139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33531 16:35:58.448415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33533 16:35:58.479465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33534 16:35:58.479820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33536 16:35:58.510952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33537 16:35:58.511304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33539 16:35:58.541838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33540 16:35:58.542183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33542 16:35:58.573967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33543 16:35:58.574313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33545 16:35:58.605705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33546 16:35:58.606050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33548 16:35:58.636838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33549 16:35:58.637188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33551 16:35:58.667988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33552 16:35:58.668334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33554 16:35:58.699144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33555 16:35:58.699485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33557 16:35:58.731344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33558 16:35:58.731706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33560 16:35:58.764196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33561 16:35:58.764603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33563 16:35:58.795884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33565 16:35:58.796326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33566 16:35:58.826970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33567 16:35:58.827316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33569 16:35:58.858782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33570 16:35:58.859139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33572 16:35:58.890613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33573 16:35:58.890873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33575 16:35:58.923076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33577 16:35:58.923629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33578 16:35:58.955300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33579 16:35:58.955750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33581 16:35:58.987123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33583 16:35:58.987677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33584 16:35:59.019498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33585 16:35:59.019944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33587 16:35:59.072390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33589 16:35:59.072935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33590 16:35:59.104955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33591 16:35:59.105419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33593 16:35:59.137491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33594 16:35:59.137949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33596 16:35:59.169190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33597 16:35:59.169631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33599 16:35:59.200836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33600 16:35:59.201287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33602 16:35:59.232125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33603 16:35:59.232521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33605 16:35:59.264217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33607 16:35:59.264504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33608 16:35:59.296861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33609 16:35:59.297124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33611 16:35:59.329494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33613 16:35:59.329938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33614 16:35:59.360940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33615 16:35:59.361284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33617 16:35:59.392639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33618 16:35:59.392993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33620 16:35:59.424311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33621 16:35:59.424657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33623 16:35:59.457117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33624 16:35:59.457503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33626 16:35:59.489478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33627 16:35:59.489851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33629 16:35:59.522571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33630 16:35:59.522981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33632 16:35:59.554930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33633 16:35:59.555231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33635 16:35:59.586266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33637 16:35:59.586822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33638 16:35:59.624865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33639 16:35:59.625233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33641 16:35:59.662013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33642 16:35:59.662468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33644 16:35:59.695109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33645 16:35:59.695614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33647 16:35:59.727193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33648 16:35:59.727676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33650 16:35:59.758292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33652 16:35:59.758740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33653 16:35:59.791208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33654 16:35:59.791660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33656 16:35:59.829727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33657 16:35:59.830103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33659 16:35:59.861165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33660 16:35:59.861465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33662 16:35:59.893523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33663 16:35:59.893912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33665 16:35:59.925879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33667 16:35:59.926280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33668 16:35:59.957970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33669 16:35:59.958349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33671 16:35:59.991580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33672 16:35:59.991986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33674 16:36:00.023997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33675 16:36:00.024448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33677 16:36:00.055947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33678 16:36:00.056386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33680 16:36:00.087919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33682 16:36:00.088267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33683 16:36:00.119322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33685 16:36:00.119663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33686 16:36:00.151304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33687 16:36:00.151748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33689 16:36:00.185451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33690 16:36:00.185813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33692 16:36:00.216997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33693 16:36:00.217319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33695 16:36:00.248113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33696 16:36:00.248517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33698 16:36:00.279691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33699 16:36:00.280088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33701 16:36:00.311610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33702 16:36:00.312007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33704 16:36:00.344843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33706 16:36:00.345337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33707 16:36:00.379828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33708 16:36:00.380240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33710 16:36:00.411971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33712 16:36:00.412419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33713 16:36:00.443731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33714 16:36:00.444190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33716 16:36:00.475657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33717 16:36:00.476048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33719 16:36:00.508671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33721 16:36:00.509143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33722 16:36:00.542216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33724 16:36:00.542506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33725 16:36:00.573847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33726 16:36:00.574202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
33728 16:36:00.604733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33729 16:36:00.605103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33731 16:36:00.635779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33732 16:36:00.636157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33734 16:36:00.666836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33735 16:36:00.667237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
33737 16:36:00.700152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33738 16:36:00.700576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33740 16:36:00.732751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33742 16:36:00.733189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33743 16:36:00.764297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33744 16:36:00.764614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
33746 16:36:00.795223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33747 16:36:00.795592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33749 16:36:00.827540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33750 16:36:00.827906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33752 16:36:00.860596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
33754 16:36:00.860874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33755 16:36:00.893413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33757 16:36:00.893971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33758 16:36:00.926000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
33760 16:36:00.926641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
33761 16:36:00.958450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33762 16:36:00.958885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33764 16:36:00.991074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33765 16:36:00.991479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
33767 16:36:01.025772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33769 16:36:01.026229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33770 16:36:01.061509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33772 16:36:01.061984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33773 16:36:01.099566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33774 16:36:01.099978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
33776 16:36:01.133367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33777 16:36:01.133771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33779 16:36:01.165526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33780 16:36:01.165936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33782 16:36:01.201629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33783 16:36:01.202051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
33785 16:36:01.233677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33786 16:36:01.234051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33788 16:36:01.265683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33790 16:36:01.266017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33791 16:36:01.296719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33792 16:36:01.297067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
33794 16:36:01.327696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33795 16:36:01.328058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33797 16:36:01.359761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33798 16:36:01.360117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33800 16:36:01.391217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33801 16:36:01.391569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
33803 16:36:01.421852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33804 16:36:01.422205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33806 16:36:01.453134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
33807 16:36:01.453484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
33809 16:36:01.484096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33810 16:36:01.484441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33812 16:36:01.515910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33813 16:36:01.516267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
33815 16:36:01.547564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33816 16:36:01.548024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33818 16:36:01.579415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33819 16:36:01.579872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33821 16:36:01.610891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33822 16:36:01.611345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
33824 16:36:01.642695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33825 16:36:01.643090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33827 16:36:01.674888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33828 16:36:01.675301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33830 16:36:01.706782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33831 16:36:01.707199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
33833 16:36:01.738796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33834 16:36:01.739340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33836 16:36:01.769652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33837 16:36:01.770095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33839 16:36:01.800889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33840 16:36:01.801269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
33842 16:36:01.832119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33844 16:36:01.832826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33845 16:36:01.864231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33846 16:36:01.864595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33848 16:36:01.896241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
33850 16:36:01.896802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33851 16:36:01.927957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33853 16:36:01.928512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33854 16:36:01.959142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
33855 16:36:01.959604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
33857 16:36:01.991108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33859 16:36:01.991670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33860 16:36:02.022947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33861 16:36:02.023409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
33863 16:36:02.054722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33865 16:36:02.055257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33866 16:36:02.087365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33867 16:36:02.087815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33869 16:36:02.120030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33870 16:36:02.120480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
33872 16:36:02.152786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33873 16:36:02.153209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33875 16:36:02.188360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33876 16:36:02.188832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33878 16:36:02.219898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33879 16:36:02.220364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
33881 16:36:02.252023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33882 16:36:02.252377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33884 16:36:02.284469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33885 16:36:02.284842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33887 16:36:02.316707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
33889 16:36:02.316999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33890 16:36:02.349032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33891 16:36:02.349405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33893 16:36:02.388137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33894 16:36:02.388500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33896 16:36:02.422672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
33898 16:36:02.423321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33899 16:36:02.454656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33901 16:36:02.455061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33902 16:36:02.487782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
33903 16:36:02.488202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
33905 16:36:02.520967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33906 16:36:02.521359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33908 16:36:02.556305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33909 16:36:02.556697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
33911 16:36:02.591179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33913 16:36:02.591560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33914 16:36:02.623465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33916 16:36:02.623863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33917 16:36:02.659574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
33919 16:36:02.660004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33920 16:36:02.691859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33922 16:36:02.692149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33923 16:36:02.724238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33924 16:36:02.724518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33926 16:36:02.756914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33927 16:36:02.757194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
33929 16:36:02.788540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33930 16:36:02.788987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33932 16:36:02.820887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33933 16:36:02.821339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33935 16:36:02.853055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
33937 16:36:02.853610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33938 16:36:02.885160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33939 16:36:02.885606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33941 16:36:02.917155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33942 16:36:02.917520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33944 16:36:02.949485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33945 16:36:02.949769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
33947 16:36:02.980977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33948 16:36:02.981253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33950 16:36:03.013117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
33951 16:36:03.013470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
33953 16:36:03.044568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33954 16:36:03.044915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33956 16:36:03.076312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
33958 16:36:03.076621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33959 16:36:03.108165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33960 16:36:03.108452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33962 16:36:03.141531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33964 16:36:03.142004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33965 16:36:03.175375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33966 16:36:03.175659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
33968 16:36:03.208191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33969 16:36:03.208542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33971 16:36:03.240348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33972 16:36:03.240634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33974 16:36:03.271697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33975 16:36:03.271983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
33977 16:36:03.303334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33978 16:36:03.303617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33980 16:36:03.334887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33981 16:36:03.335238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33983 16:36:03.367204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
33985 16:36:03.367608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33986 16:36:03.398975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33987 16:36:03.399328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33989 16:36:03.431544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33990 16:36:03.431821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33992 16:36:03.464935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33993 16:36:03.465285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
33995 16:36:03.496544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33996 16:36:03.496892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33998 16:36:03.528156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
33999 16:36:03.528516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34001 16:36:03.559590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34002 16:36:03.559940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34004 16:36:03.591934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34006 16:36:03.592414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34007 16:36:03.623525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34008 16:36:03.623812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34010 16:36:03.655287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34011 16:36:03.655567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34013 16:36:03.687349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34014 16:36:03.687627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34016 16:36:03.719245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34017 16:36:03.719520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34019 16:36:03.751168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34020 16:36:03.751446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34022 16:36:03.783031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34023 16:36:03.783307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34025 16:36:03.815134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34026 16:36:03.815513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34028 16:36:03.847178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34029 16:36:03.847465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34031 16:36:03.879321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34032 16:36:03.879613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34034 16:36:03.911392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34036 16:36:03.911673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34037 16:36:03.943880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34038 16:36:03.944161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34040 16:36:03.975651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34041 16:36:03.975924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34043 16:36:04.007171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34044 16:36:04.007456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34046 16:36:04.038616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34047 16:36:04.038996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34049 16:36:04.070318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34051 16:36:04.070783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34052 16:36:04.102138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34054 16:36:04.102416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34055 16:36:04.133290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34057 16:36:04.133816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34058 16:36:04.189224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34059 16:36:04.189630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34061 16:36:04.221569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34063 16:36:04.221985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34064 16:36:04.253894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34065 16:36:04.254367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34067 16:36:04.285611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34069 16:36:04.286041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34070 16:36:04.317169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34071 16:36:04.317634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34073 16:36:04.349212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34074 16:36:04.349675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34076 16:36:04.381101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34078 16:36:04.381554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34079 16:36:04.412868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34080 16:36:04.413334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34082 16:36:04.444469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34083 16:36:04.444845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34085 16:36:04.477196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34086 16:36:04.477605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34088 16:36:04.509072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34089 16:36:04.509499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34091 16:36:04.541264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34092 16:36:04.541690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34094 16:36:04.573288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34095 16:36:04.573752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34097 16:36:04.604994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34098 16:36:04.605459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34100 16:36:04.640279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34101 16:36:04.640682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34103 16:36:04.673159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34104 16:36:04.673570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34106 16:36:04.705358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34107 16:36:04.705760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34109 16:36:04.737442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34110 16:36:04.737852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34112 16:36:04.769260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34113 16:36:04.769697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34115 16:36:04.801571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34116 16:36:04.802047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34118 16:36:04.833485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34120 16:36:04.833801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34121 16:36:04.864878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34122 16:36:04.865233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34124 16:36:04.896353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34125 16:36:04.896641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34127 16:36:04.928069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34128 16:36:04.928422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34130 16:36:04.960192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34131 16:36:04.960558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34133 16:36:04.992565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34134 16:36:04.993021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34136 16:36:05.023903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34137 16:36:05.024338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34139 16:36:05.055381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34140 16:36:05.055781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34142 16:36:05.087305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34143 16:36:05.087770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34145 16:36:05.118882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34146 16:36:05.119338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34148 16:36:05.150392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34150 16:36:05.151027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34151 16:36:05.182292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34153 16:36:05.182939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34154 16:36:05.219084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34155 16:36:05.219486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34157 16:36:05.251180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34158 16:36:05.251551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34160 16:36:05.284144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34161 16:36:05.284600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34163 16:36:05.316545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34164 16:36:05.316991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34166 16:36:05.349016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34167 16:36:05.349470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34169 16:36:05.381509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34170 16:36:05.382005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34172 16:36:05.417967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34174 16:36:05.418429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34175 16:36:05.455126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34176 16:36:05.455512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34178 16:36:05.495483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34179 16:36:05.495919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34181 16:36:05.556999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34182 16:36:05.557457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34184 16:36:05.601583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34185 16:36:05.602067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34187 16:36:05.638191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34189 16:36:05.638641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34190 16:36:05.672954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34192 16:36:05.673410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34193 16:36:05.709528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34194 16:36:05.709922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34196 16:36:05.745703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34198 16:36:05.746128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34199 16:36:05.782164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34201 16:36:05.782523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34202 16:36:05.815771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34203 16:36:05.816149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34205 16:36:05.852733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34206 16:36:05.853127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34208 16:36:05.889423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34209 16:36:05.889906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34211 16:36:05.929076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34213 16:36:05.929451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34214 16:36:05.965844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34215 16:36:05.966427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34217 16:36:06.001070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34218 16:36:06.001472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34220 16:36:06.034375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34222 16:36:06.034823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34223 16:36:06.068932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34224 16:36:06.069342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34226 16:36:06.103047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34227 16:36:06.103529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34229 16:36:06.136820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34230 16:36:06.137285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34232 16:36:06.169810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34233 16:36:06.170262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34235 16:36:06.203133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34236 16:36:06.203586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34238 16:36:06.238208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34240 16:36:06.238667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34241 16:36:06.275007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34242 16:36:06.275429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34244 16:36:06.307904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34245 16:36:06.308327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34247 16:36:06.340581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34248 16:36:06.340997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34250 16:36:06.372845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34251 16:36:06.373258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34253 16:36:06.405712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34254 16:36:06.406131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34256 16:36:06.439505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34257 16:36:06.439925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34259 16:36:06.472839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34261 16:36:06.473293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34262 16:36:06.508137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34263 16:36:06.508557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34265 16:36:06.542259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34267 16:36:06.542848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34268 16:36:06.574738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34269 16:36:06.575133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34271 16:36:06.606975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34272 16:36:06.607297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34274 16:36:06.639615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34275 16:36:06.640000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34277 16:36:06.672623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34278 16:36:06.673060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34280 16:36:06.707288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34281 16:36:06.707612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34283 16:36:06.739743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34284 16:36:06.740030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34286 16:36:06.772371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34288 16:36:06.772750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34289 16:36:06.805284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34290 16:36:06.805752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34292 16:36:06.838215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34294 16:36:06.838544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34295 16:36:06.870757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34296 16:36:06.871301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34298 16:36:06.903351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34299 16:36:06.903745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34301 16:36:06.935680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34302 16:36:06.935963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34304 16:36:06.967959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34305 16:36:06.968343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34307 16:36:07.000479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34308 16:36:07.000759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34310 16:36:07.038718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34312 16:36:07.039155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34313 16:36:07.070855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34314 16:36:07.071136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34316 16:36:07.103058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34317 16:36:07.103488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34319 16:36:07.139845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34320 16:36:07.140163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34322 16:36:07.178975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34323 16:36:07.179257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34325 16:36:07.211830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34327 16:36:07.212487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34328 16:36:07.244056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34329 16:36:07.244468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34331 16:36:07.277546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34333 16:36:07.278014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34334 16:36:07.310233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34335 16:36:07.310647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34337 16:36:07.344446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34339 16:36:07.344897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34340 16:36:07.377023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34342 16:36:07.377472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34343 16:36:07.411610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34344 16:36:07.412128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34346 16:36:07.444374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34347 16:36:07.444772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34349 16:36:07.476715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34350 16:36:07.476992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34352 16:36:07.512179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34353 16:36:07.512466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34355 16:36:07.515215 + set +x
34356 16:36:07.515424 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 556488_1.1.3.5>
34357 16:36:07.515698 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 556488_1.1.3.5
34358 16:36:07.515799 Ending use of test pattern.
34359 16:36:07.515884 Ending test lava.1_kselftest-arm64_qemu (556488_1.1.3.5), duration 407.87
34361 16:36:07.518753 ok: lava_test_shell seems to have completed
34362 16:36:07.577047 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34363 16:36:07.580189 end: 3.1 lava-test-shell (duration 00:06:49) [common]
34364 16:36:07.580286 end: 3 lava-test-retry (duration 00:06:49) [common]
34365 16:36:07.580379 start: 4 finalize (timeout 00:01:57) [common]
34366 16:36:07.580468 start: 4.1 power-off (timeout 00:00:30) [common]
34367 16:36:07.580552 end: 4.1 power-off (duration 00:00:00) [common]
34368 16:36:07.580634 start: 4.2 read-feedback (timeout 00:01:57) [common]
34370 16:36:07.581093 Listened to connection for namespace 'common' for up to 1s
34371 16:36:08.585746 Finalising connection for namespace 'common'
34373 16:36:08.686721 / # poweroff
34374 16:36:08.687292 Already disconnected
34375 16:36:08.687496 poweroff
34376 16:36:09.089808 end: 4.2 read-feedback (duration 00:00:02) [common]
34377 16:36:09.090084 Already disconnected
34378 16:36:09.090291 end: 4 finalize (duration 00:00:02) [common]
34379 16:36:09.090488 Cleaning after the job
34380 16:36:09.090678 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/556488/deployimages-35vl0guj/kernel
34381 16:36:09.097820 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/556488/deployimages-35vl0guj/ramdisk
34382 16:36:09.114100 Stopping the qemu container lava-docker-qemu-556488-2.1.1-eyki0152z4
34383 16:36:09.937047 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/556488
34384 16:36:10.027907 Job finished correctly