Boot log: qemu_arm64-virt-gicv3
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
1 10:53:14.456747 lava-dispatcher, installed at version: 2023.01
2 10:53:14.457029 start: 0 validate
3 10:53:14.457195 Start time: 2023-06-05 10:53:14.457184+00:00 (UTC)
4 10:53:14.458787 Validating that http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image exists
5 10:53:14.843024 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 10:53:15.022545 cmd: ['docker', 'pull', 'kernelci/qemu']
7 10:53:15.022808 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 10:53:15.194349 >> Using default tag: latest
9 10:53:16.475719 >> latest: Pulling from kernelci/qemu
10 10:53:16.946391 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 10:53:16.946659 >> Status: Image is up to date for kernelci/qemu:latest
12 10:53:17.190870 >> docker.io/kernelci/qemu:latest
13 10:53:17.194257 Returned 0 in 2 seconds
14 10:53:17.332316 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 10:53:17.332684 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 10:53:19.847232 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 10:53:19.847676 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 10:53:21.655736 Returned 0 in 4 seconds
19 10:53:21.757013 validate duration: 7.30
21 10:53:21.757577 start: 1 deployimages (timeout 00:03:00) [common]
22 10:53:21.757785 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 10:53:21.758267 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey
24 10:53:21.758531 makedir: /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin
25 10:53:21.758739 makedir: /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/tests
26 10:53:21.758942 makedir: /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/results
27 10:53:21.759150 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-add-keys
28 10:53:21.759418 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-add-sources
29 10:53:21.759666 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-background-process-start
30 10:53:21.759915 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-background-process-stop
31 10:53:21.760155 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-common-functions
32 10:53:21.760387 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-echo-ipv4
33 10:53:21.760627 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-install-packages
34 10:53:21.760866 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-installed-packages
35 10:53:21.761099 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-os-build
36 10:53:21.761335 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-probe-channel
37 10:53:21.761569 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-probe-ip
38 10:53:21.761835 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-target-ip
39 10:53:21.762071 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-target-mac
40 10:53:21.762304 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-target-storage
41 10:53:21.762542 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-test-case
42 10:53:21.762777 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-test-event
43 10:53:21.763011 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-test-feedback
44 10:53:21.763248 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-test-raise
45 10:53:21.763488 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-test-reference
46 10:53:21.763722 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-test-runner
47 10:53:21.763952 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-test-set
48 10:53:21.764184 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-test-shell
49 10:53:21.764423 Updating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-install-packages (oe)
50 10:53:21.764720 Updating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/bin/lava-installed-packages (oe)
51 10:53:21.764956 Creating /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/environment
52 10:53:21.765153 LAVA metadata
53 10:53:21.765291 - LAVA_JOB_ID=562569
54 10:53:21.765422 - LAVA_DISPATCHER_IP=172.27.0.2
55 10:53:21.765617 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 10:53:21.765775 skipped lava-vland-overlay
57 10:53:21.765927 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 10:53:21.766086 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 10:53:21.766214 skipped lava-multinode-overlay
60 10:53:21.766359 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 10:53:21.766520 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 10:53:21.766672 Loading test definitions
63 10:53:21.766856 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 10:53:21.767004 Using /lava-562569 at stage 0
65 10:53:21.767605 uuid=562569_1.1.3.1 testdef=None
66 10:53:21.767785 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 10:53:21.767947 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 10:53:21.768836 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 10:53:21.769310 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 10:53:21.770410 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 10:53:21.770901 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 10:53:21.771914 runner path: /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/0/tests/0_timesync-off test_uuid 562569_1.1.3.1
75 10:53:21.772201 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 10:53:21.772675 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 10:53:21.772812 Using /lava-562569 at stage 0
79 10:53:21.773004 Fetching tests from https://github.com/kernelci/test-definitions.git
80 10:53:21.773153 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/0/tests/1_kselftest-arm64_qemu'
81 10:53:26.569874 Running '/usr/bin/git checkout kernelci.org
82 10:53:26.736671 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 10:53:26.737318 uuid=562569_1.1.3.5 testdef=None
84 10:53:26.737454 end: 1.1.3.5 git-repo-action (duration 00:00:05) [common]
86 10:53:26.737714 start: 1.1.3.6 test-overlay (timeout 00:02:55) [common]
87 10:53:26.738529 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 10:53:26.738781 start: 1.1.3.7 test-install-overlay (timeout 00:02:55) [common]
90 10:53:26.739881 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 10:53:26.740152 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:55) [common]
93 10:53:26.741219 runner path: /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/0/tests/1_kselftest-arm64_qemu test_uuid 562569_1.1.3.5
94 10:53:26.741312 BOARD='qemu_arm64-virt-gicv3'
95 10:53:26.741379 BRANCH='cip-gitlab'
96 10:53:26.741441 SKIPFILE='/dev/null'
97 10:53:26.741503 SKIP_INSTALL='True'
98 10:53:26.741564 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
99 10:53:26.741628 TST_CASENAME=''
100 10:53:26.741694 TST_CMDFILES='arm64'
101 10:53:26.741835 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 10:53:26.742072 Creating lava-test-runner.conf files
104 10:53:26.742144 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/562569/lava-overlay-wr_rvtey/lava-562569/0 for stage 0
105 10:53:26.742239 - 0_timesync-off
106 10:53:26.742312 - 1_kselftest-arm64_qemu
107 10:53:26.742407 end: 1.1.3 test-definition (duration 00:00:05) [common]
108 10:53:26.742494 start: 1.1.4 compress-overlay (timeout 00:02:55) [common]
109 10:53:35.505927 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 10:53:35.506118 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:46) [common]
111 10:53:35.506207 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 10:53:35.506309 end: 1.1 lava-overlay (duration 00:00:14) [common]
113 10:53:35.506399 start: 1.2 apply-overlay-guest (timeout 00:02:46) [common]
114 10:53:35.506476 Overlay: /var/lib/lava/dispatcher/tmp/562569/compress-overlay-und659l7/overlay-1.1.4.tar.gz
115 10:53:50.321660 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 10:53:50.322470 start: 1.3 deploy-device-env (timeout 00:02:31) [common]
118 10:53:50.322659 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 10:53:50.322834 start: 1.4 download-retry (timeout 00:02:31) [common]
120 10:53:50.323016 start: 1.4.1 http-download (timeout 00:02:31) [common]
121 10:53:50.323348 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
122 10:53:50.323508 saving as /var/lib/lava/dispatcher/tmp/562569/deployimages-i9ddb_1e/kernel/Image
123 10:53:50.323632 total size: 45746688 (43MB)
124 10:53:50.323754 No compression specified
125 10:53:50.680739 progress 0% (0MB)
126 10:53:51.749047 progress 5% (2MB)
127 10:53:52.108786 progress 10% (4MB)
128 10:53:52.295113 progress 15% (6MB)
129 10:53:52.655421 progress 20% (8MB)
130 10:53:52.833863 progress 25% (10MB)
131 10:53:53.016910 progress 30% (13MB)
132 10:53:53.363165 progress 35% (15MB)
133 10:53:53.546027 progress 40% (17MB)
134 10:53:53.737812 progress 45% (19MB)
135 10:53:54.073116 progress 50% (21MB)
136 10:53:54.255126 progress 55% (24MB)
137 10:53:54.447529 progress 60% (26MB)
138 10:53:54.633833 progress 65% (28MB)
139 10:53:54.965988 progress 70% (30MB)
140 10:53:55.147647 progress 75% (32MB)
141 10:53:55.335141 progress 80% (34MB)
142 10:53:55.522543 progress 85% (37MB)
143 10:53:55.852399 progress 90% (39MB)
144 10:53:56.044016 progress 95% (41MB)
145 10:53:56.225339 progress 100% (43MB)
146 10:53:56.225701 43MB downloaded in 5.90s (7.39MB/s)
147 10:53:56.226028 end: 1.4.1 http-download (duration 00:00:06) [common]
149 10:53:56.226595 end: 1.4 download-retry (duration 00:00:06) [common]
150 10:53:56.226794 start: 1.5 download-retry (timeout 00:02:26) [common]
151 10:53:56.226982 start: 1.5.1 http-download (timeout 00:02:26) [common]
152 10:53:56.227288 Not decompressing ramdisk as can be used compressed.
153 10:53:56.227499 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 10:53:56.227649 saving as /var/lib/lava/dispatcher/tmp/562569/deployimages-i9ddb_1e/ramdisk/rootfs.cpio.gz
155 10:53:56.227804 total size: 88976554 (84MB)
156 10:53:56.227958 No compression specified
157 10:53:56.407397 progress 0% (0MB)
158 10:53:56.767813 progress 5% (4MB)
159 10:53:57.142385 progress 10% (8MB)
160 10:53:57.502511 progress 15% (12MB)
161 10:53:58.020092 progress 20% (17MB)
162 10:53:58.383145 progress 25% (21MB)
163 10:53:58.742982 progress 30% (25MB)
164 10:53:59.104305 progress 35% (29MB)
165 10:53:59.624799 progress 40% (33MB)
166 10:53:59.993869 progress 45% (38MB)
167 10:54:00.528542 progress 50% (42MB)
168 10:54:01.062258 progress 55% (46MB)
169 10:54:01.593623 progress 60% (50MB)
170 10:54:02.122594 progress 65% (55MB)
171 10:54:02.644103 progress 70% (59MB)
172 10:54:03.014570 progress 75% (63MB)
173 10:54:03.536038 progress 80% (67MB)
174 10:54:03.912274 progress 85% (72MB)
175 10:54:04.422134 progress 90% (76MB)
176 10:54:04.807559 progress 95% (80MB)
177 10:54:05.168980 progress 100% (84MB)
178 10:54:05.169307 84MB downloaded in 8.94s (9.49MB/s)
179 10:54:05.169524 end: 1.5.1 http-download (duration 00:00:09) [common]
181 10:54:05.169941 end: 1.5 download-retry (duration 00:00:09) [common]
182 10:54:05.170064 end: 1 deployimages (duration 00:00:43) [common]
183 10:54:05.170188 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 10:54:05.170307 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 10:54:05.170420 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 10:54:05.170714 Extending command line for qcow2 test overlay
187 10:54:05.171170 Pulling docker image
188 10:54:05.171289 cmd: ['docker', 'pull', 'kernelci/qemu']
189 10:54:05.171387 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 10:54:05.333408 >> Using default tag: latest
191 10:54:06.513473 >> latest: Pulling from kernelci/qemu
192 10:54:06.545299 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 10:54:06.545698 >> Status: Image is up to date for kernelci/qemu:latest
194 10:54:06.578563 >> docker.io/kernelci/qemu:latest
195 10:54:06.581811 Returned 0 in 1 seconds
196 10:54:06.716746 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-562569-2.1.1-wjht5aez69 --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/562569/deployimages-i9ddb_1e/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/562569/deployimages-i9ddb_1e/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/562569/apply-overlay-guest-jd_70v3o/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 10:54:06.861986 started a shell command
198 10:54:06.862624 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 10:54:06.862826 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 10:54:06.863017 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 10:54:06.863246 Setting prompt string to ['Linux version [0-9]']
202 10:54:06.863447 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 10:54:08.498674 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 10:54:08.499552 start: 2.2.1 login-action (timeout 00:04:57) [common]
205 10:54:08.499780 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
206 10:54:08.500009 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
207 10:54:08.500182 Using line separator: #'\n'#
208 10:54:08.500317 No login prompt set.
209 10:54:08.500460 Parsing kernel messages
210 10:54:08.500582 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
211 10:54:08.500816 [login-action] Waiting for messages, (timeout 00:04:57)
212 10:54:08.502145 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
213 10:54:08.502305 [ 0.000000] random: crng init done
214 10:54:08.502430 [ 0.000000] Machine model: linux,dummy-virt
215 10:54:08.502547 [ 0.000000] efi: UEFI not found.
216 10:54:08.502664 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
217 10:54:08.502845 [ 0.000000] printk: bootconsole [pl11] enabled
218 10:54:08.503627 [ 0.000000] NUMA: No NUMA configuration found
219 10:54:08.503877 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 10:54:08.504301 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf2a00-0x7fdf4fff]
221 10:54:08.506650 [ 0.000000] Zone ranges:
222 10:54:08.507341 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 10:54:08.507467 [ 0.000000] DMA32 empty
224 10:54:08.507580 [ 0.000000] Normal empty
225 10:54:08.507694 [ 0.000000] Movable zone start for each node
226 10:54:08.507806 [ 0.000000] Early memory node ranges
227 10:54:08.508104 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 10:54:08.508622 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 10:54:08.523613 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 10:54:08.524625 [ 0.000000] psci: probing for conduit method from DT.
231 10:54:08.525193 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 10:54:08.525415 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 10:54:08.525632 [ 0.000000] psci: Trusted OS migration not required
234 10:54:08.525800 [ 0.000000] psci: SMC Calling Convention v1.0
235 10:54:08.527864 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
236 10:54:08.528348 [ 0.000000] pcpu-alloc: s45224 r8192 d32600 u86016 alloc=21*4096
237 10:54:08.528584 [ 0.000000] pcpu-alloc: [0] 0
238 10:54:08.530133 [ 0.000000] Detected PIPT I-cache on CPU0
239 10:54:08.535491 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 10:54:08.536282 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 10:54:08.536616 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 10:54:08.536740 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 10:54:08.537033 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 10:54:08.537490 [ 0.000000] CPU features: detected: Spectre-v4
245 10:54:08.542109 [ 0.000000] alternatives: applying boot alternatives
246 10:54:08.545861 [ 0.000000] Fallback order for Node 0: 0
247 10:54:08.546184 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 10:54:08.546283 [ 0.000000] Policy zone: DMA
249 10:54:08.546900 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 10:54:08.549956 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 10:54:08.553615 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 10:54:08.554067 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 10:54:08.554587 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 10:54:08.567292 <6>[ 0.000000] Memory: 862476K/1048576K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 153332K reserved, 32768K cma-reserved)
255 10:54:08.574564 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 10:54:08.583101 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 10:54:08.583261 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 10:54:08.583386 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 10:54:08.583589 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 10:54:08.583737 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 10:54:08.584181 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 10:54:08.584359 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 10:54:08.585326 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 10:54:08.593500 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 10:54:08.593889 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 10:54:08.595356 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 10:54:08.595721 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 10:54:08.596387 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 10:54:08.601132 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 10:54:08.602086 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @43030000 (indirect, esz 8, psz 64K, shr 1)
271 10:54:08.602248 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @43040000 (flat, esz 8, psz 64K, shr 1)
272 10:54:08.603021 <6>[ 0.000000] GICv3: using LPI property table @0x0000000043050000
273 10:54:08.603781 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000043060000
274 10:54:08.605038 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 10:54:08.614124 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 10:54:08.614541 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 10:54:08.615266 <6>[ 0.000076] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 10:54:08.633450 <6>[ 0.015655] Console: colour dummy device 80x25
279 10:54:08.638327 <6>[ 0.022345] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 10:54:08.638535 <6>[ 0.023609] pid_max: default: 32768 minimum: 301
281 10:54:08.639975 <6>[ 0.024902] LSM: Security Framework initializing
282 10:54:08.644510 <6>[ 0.029398] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 10:54:08.644835 <6>[ 0.029687] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 10:54:08.679452 <4>[ 0.064317] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 10:54:08.686013 <6>[ 0.070874] cblist_init_generic: Setting adjustable number of callback queues.
286 10:54:08.686167 <6>[ 0.071188] cblist_init_generic: Setting shift to 0 and lim to 1.
287 10:54:08.686818 <6>[ 0.071744] cblist_init_generic: Setting shift to 0 and lim to 1.
288 10:54:08.688653 <6>[ 0.073565] rcu: Hierarchical SRCU implementation.
289 10:54:08.688762 <6>[ 0.073736] rcu: Max phase no-delay instances is 1000.
290 10:54:08.693768 <6>[ 0.078848] Platform MSI: its@8080000 domain created
291 10:54:08.694727 <6>[ 0.079448] PCI/MSI: /intc@8000000/its@8080000 domain created
292 10:54:08.695100 <6>[ 0.080050] fsl-mc MSI: its@8080000 domain created
293 10:54:08.698483 <6>[ 0.083587] EFI services will not be available.
294 10:54:08.699559 <6>[ 0.084474] smp: Bringing up secondary CPUs ...
295 10:54:08.699723 <6>[ 0.084685] smp: Brought up 1 node, 1 CPU
296 10:54:08.699821 <6>[ 0.084821] SMP: Total of 1 processors activated.
297 10:54:08.700111 <6>[ 0.085160] CPU features: detected: Branch Target Identification
298 10:54:08.700433 <6>[ 0.085383] CPU features: detected: 32-bit EL0 Support
299 10:54:08.701163 <6>[ 0.085559] CPU features: detected: 32-bit EL1 Support
300 10:54:08.701362 <6>[ 0.086144] CPU features: detected: ARMv8.4 Translation Table Level
301 10:54:08.701585 <6>[ 0.086334] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 10:54:08.701816 <6>[ 0.086573] CPU features: detected: Common not Private translations
303 10:54:08.702102 <6>[ 0.086725] CPU features: detected: CRC32 instructions
304 10:54:08.702298 <6>[ 0.086855] CPU features: detected: E0PD
305 10:54:08.702522 <6>[ 0.087062] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 10:54:08.702747 <6>[ 0.087206] CPU features: detected: RCpc load-acquire (LDAPR)
307 10:54:08.703016 <6>[ 0.087333] CPU features: detected: LSE atomic instructions
308 10:54:08.703226 <6>[ 0.087456] CPU features: detected: Privileged Access Never
309 10:54:08.703448 <6>[ 0.087595] CPU features: detected: RAS Extension Support
310 10:54:08.703661 <6>[ 0.087740] CPU features: detected: Random Number Generator
311 10:54:08.703854 <6>[ 0.087899] CPU features: detected: Speculation barrier (SB)
312 10:54:08.703993 <6>[ 0.088034] CPU features: detected: Stage-2 Force Write-Back
313 10:54:08.704146 <6>[ 0.088172] CPU features: detected: TLB range maintenance instructions
314 10:54:08.704274 <6>[ 0.088389] CPU features: detected: Scalable Matrix Extension
315 10:54:08.704402 <6>[ 0.088534] CPU features: detected: FA64
316 10:54:08.704519 <6>[ 0.088662] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 10:54:08.704636 <6>[ 0.088841] CPU features: detected: Scalable Vector Extension
318 10:54:08.716359 <6>[ 0.098578] SVE: maximum available vector length 256 bytes per vector
319 10:54:08.716811 <6>[ 0.101824] SVE: default vector length 64 bytes per vector
320 10:54:08.718996 <6>[ 0.103720] SME: minimum available vector length 16 bytes per vector
321 10:54:08.719178 <6>[ 0.103948] SME: maximum available vector length 256 bytes per vector
322 10:54:08.719390 <6>[ 0.104167] SME: default vector length 32 bytes per vector
323 10:54:08.719566 <6>[ 0.104625] CPU: All CPU(s) started at EL1
324 10:54:08.719941 <6>[ 0.104988] alternatives: applying system-wide alternatives
325 10:54:08.775391 <6>[ 0.160131] devtmpfs: initialized
326 10:54:08.796212 <6>[ 0.180816] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 10:54:08.797553 <6>[ 0.182395] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 10:54:08.802739 <6>[ 0.187796] pinctrl core: initialized pinctrl subsystem
329 10:54:08.814738 <6>[ 0.199726] DMI not present or invalid.
330 10:54:08.824255 <6>[ 0.209277] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 10:54:08.836733 <6>[ 0.221355] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 10:54:08.837500 <6>[ 0.222324] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 10:54:08.837931 <6>[ 0.222769] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 10:54:08.838361 <6>[ 0.223244] audit: initializing netlink subsys (disabled)
335 10:54:08.846195 <5>[ 0.231003] audit: type=2000 audit(0.188:1): state=initialized audit_enabled=0 res=1
336 10:54:08.846828 <6>[ 0.231637] thermal_sys: Registered thermal governor 'step_wise'
337 10:54:08.847459 <6>[ 0.231708] thermal_sys: Registered thermal governor 'power_allocator'
338 10:54:08.847581 <6>[ 0.232314] cpuidle: using governor menu
339 10:54:08.848313 <6>[ 0.233227] NET: Registered PF_QIPCRTR protocol family
340 10:54:08.851428 <6>[ 0.236269] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
341 10:54:08.851844 <6>[ 0.236886] ASID allocator initialised with 65536 entries
342 10:54:08.858080 <6>[ 0.242961] Serial: AMBA PL011 UART driver
343 10:54:08.909458 <6>[ 0.294459] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
344 10:54:08.911158 <6>[ 0.296172] printk: console [ttyAMA0] enabled
345 10:54:08.911591 <6>[ 0.296172] printk: console [ttyAMA0] enabled
346 10:54:08.911719 <6>[ 0.296584] printk: bootconsole [pl11] disabled
347 10:54:08.911818 <6>[ 0.296584] printk: bootconsole [pl11] disabled
348 10:54:08.922635 <6>[ 0.307746] KASLR enabled
349 10:54:08.958992 <6>[ 0.343893] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
350 10:54:08.959594 <6>[ 0.344107] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
351 10:54:08.959755 <6>[ 0.344256] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
352 10:54:08.959902 <6>[ 0.344401] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
353 10:54:08.960040 <6>[ 0.344533] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
354 10:54:08.960186 <6>[ 0.344672] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
355 10:54:08.960310 <6>[ 0.344841] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
356 10:54:08.960409 <6>[ 0.345138] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
357 10:54:08.970094 <6>[ 0.355080] ACPI: Interpreter disabled.
358 10:54:08.978497 <6>[ 0.363546] iommu: Default domain type: Translated
359 10:54:08.978887 <6>[ 0.363720] iommu: DMA domain TLB invalidation policy: strict mode
360 10:54:08.980703 <5>[ 0.365598] SCSI subsystem initialized
361 10:54:08.981653 <7>[ 0.366546] libata version 3.00 loaded.
362 10:54:08.983058 <6>[ 0.367981] usbcore: registered new interface driver usbfs
363 10:54:08.983577 <6>[ 0.368404] usbcore: registered new interface driver hub
364 10:54:08.983751 <6>[ 0.368741] usbcore: registered new device driver usb
365 10:54:08.987788 <6>[ 0.372615] pps_core: LinuxPPS API ver. 1 registered
366 10:54:08.987984 <6>[ 0.372815] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
367 10:54:08.988156 <6>[ 0.373192] PTP clock support registered
368 10:54:08.989004 <6>[ 0.373898] EDAC MC: Ver: 3.0.0
369 10:54:08.995205 <6>[ 0.380264] FPGA manager framework
370 10:54:08.996272 <6>[ 0.381140] Advanced Linux Sound Architecture Driver Initialized.
371 10:54:09.005549 <6>[ 0.390619] vgaarb: loaded
372 10:54:09.009610 <6>[ 0.394605] clocksource: Switched to clocksource arch_sys_counter
373 10:54:09.011097 <5>[ 0.395928] VFS: Disk quotas dquot_6.6.0
374 10:54:09.011228 <6>[ 0.396195] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
375 10:54:09.012564 <6>[ 0.397669] pnp: PnP ACPI: disabled
376 10:54:09.033093 <6>[ 0.418047] NET: Registered PF_INET protocol family
377 10:54:09.035612 <6>[ 0.420450] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
378 10:54:09.040752 <6>[ 0.425542] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
379 10:54:09.041107 <6>[ 0.425899] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
380 10:54:09.041229 <6>[ 0.426268] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
381 10:54:09.041889 <6>[ 0.426684] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
382 10:54:09.042341 <6>[ 0.427282] TCP: Hash tables configured (established 8192 bind 8192)
383 10:54:09.043653 <6>[ 0.428506] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
384 10:54:09.044148 <6>[ 0.428905] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
385 10:54:09.045331 <6>[ 0.430155] NET: Registered PF_UNIX/PF_LOCAL protocol family
386 10:54:09.047809 <6>[ 0.432646] RPC: Registered named UNIX socket transport module.
387 10:54:09.048014 <6>[ 0.432920] RPC: Registered udp transport module.
388 10:54:09.048222 <6>[ 0.433093] RPC: Registered tcp transport module.
389 10:54:09.048387 <6>[ 0.433259] RPC: Registered tcp NFSv4.1 backchannel transport module.
390 10:54:09.048551 <6>[ 0.433566] PCI: CLS 0 bytes, default 64
391 10:54:09.053247 <6>[ 0.438023] Unpacking initramfs...
392 10:54:09.065999 <6>[ 0.450707] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
393 10:54:09.066560 <6>[ 0.451603] kvm [1]: HYP mode not available
394 10:54:09.075084 <5>[ 0.459919] Initialise system trusted keyrings
395 10:54:09.076530 <6>[ 0.461423] workingset: timestamp_bits=42 max_order=18 bucket_order=0
396 10:54:09.113376 <6>[ 0.498151] squashfs: version 4.0 (2009/01/31) Phillip Lougher
397 10:54:09.122917 <5>[ 0.507865] NFS: Registering the id_resolver key type
398 10:54:09.123517 <5>[ 0.508372] Key type id_resolver registered
399 10:54:09.123633 <5>[ 0.508565] Key type id_legacy registered
400 10:54:09.124379 <6>[ 0.509249] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
401 10:54:09.124755 <6>[ 0.509550] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
402 10:54:09.130004 <6>[ 0.514841] 9p: Installing v9fs 9p2000 file system support
403 10:54:09.195899 <5>[ 0.580739] Key type asymmetric registered
404 10:54:09.196544 <5>[ 0.581005] Asymmetric key parser 'x509' registered
405 10:54:09.196719 <6>[ 0.581513] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
406 10:54:09.196912 <6>[ 0.581885] io scheduler mq-deadline registered
407 10:54:09.197098 <6>[ 0.582101] io scheduler kyber registered
408 10:54:09.273989 <6>[ 0.658777] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
409 10:54:09.289741 <6>[ 0.674567] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
410 10:54:09.290998 <6>[ 0.675597] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
411 10:54:09.291516 <6>[ 0.676417] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
412 10:54:09.292007 <6>[ 0.676760] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
413 10:54:09.292750 <4>[ 0.677541] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
414 10:54:09.298108 <6>[ 0.682524] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
415 10:54:09.299330 <6>[ 0.684230] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
416 10:54:09.299675 <6>[ 0.684699] pci_bus 0000:00: root bus resource [bus 00-ff]
417 10:54:09.300058 <6>[ 0.684942] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
418 10:54:09.300552 <6>[ 0.685261] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
419 10:54:09.300676 <6>[ 0.685522] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
420 10:54:09.306617 <6>[ 0.691376] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
421 10:54:09.314244 <6>[ 0.699199] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
422 10:54:09.314840 <6>[ 0.699671] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
423 10:54:09.315043 <6>[ 0.699941] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
424 10:54:09.315543 <6>[ 0.700232] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
425 10:54:09.315671 <6>[ 0.700546] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
426 10:54:09.316546 <6>[ 0.701433] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
427 10:54:09.316929 <6>[ 0.701706] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
428 10:54:09.317038 <6>[ 0.701933] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
429 10:54:09.321510 <6>[ 0.706440] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
430 10:54:09.324984 <6>[ 0.709817] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
431 10:54:09.329796 <6>[ 0.714525] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
432 10:54:09.330129 <6>[ 0.714957] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
433 10:54:09.330329 <6>[ 0.715262] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
434 10:54:09.330514 <6>[ 0.715557] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
435 10:54:09.330709 <6>[ 0.715745] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
436 10:54:09.330918 <6>[ 0.715946] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
437 10:54:09.350538 <6>[ 0.735489] EINJ: ACPI disabled.
438 10:54:09.449041 <6>[ 0.833969] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
439 10:54:09.456193 <6>[ 0.840878] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
440 10:54:09.488330 <6>[ 0.873249] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
441 10:54:09.504003 <6>[ 0.888985] SuperH (H)SCI(F) driver initialized
442 10:54:09.509710 <6>[ 0.894734] msm_serial: driver initialized
443 10:54:09.544147 <4>[ 0.929054] cacheinfo: Unable to detect cache hierarchy for CPU 0
444 10:54:09.575604 <6>[ 0.960539] loop: module loaded
445 10:54:09.576696 <6>[ 0.961531] virtio_blk virtio1: 1/0/0 default/read/poll queues
446 10:54:09.598307 <5>[ 0.983231] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
447 10:54:09.632123 <6>[ 1.017061] megasas: 07.719.03.00-rc1
448 10:54:09.646678 <5>[ 1.031580] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
449 10:54:09.648342 <6>[ 1.033187] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
450 10:54:09.648849 <6>[ 1.033891] Intel/Sharp Extended Query Table at 0x0031
451 10:54:09.657802 <6>[ 1.042837] Using buffer write method
452 10:54:09.658321 <7>[ 1.043299] erase region 0: offset=0x0,size=0x40000,blocks=256
453 10:54:09.658795 <5>[ 1.043699] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
454 10:54:09.659662 <6>[ 1.044432] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
455 10:54:09.659772 <6>[ 1.044759] Intel/Sharp Extended Query Table at 0x0031
456 10:54:09.660448 <6>[ 1.045370] Using buffer write method
457 10:54:09.660577 <7>[ 1.045544] erase region 0: offset=0x0,size=0x40000,blocks=256
458 10:54:09.660691 <5>[ 1.045799] Concatenating MTD devices:
459 10:54:09.661028 <5>[ 1.045981] (0): \"0.flash\"
460 10:54:09.661139 <5>[ 1.046064] (1): \"0.flash\"
461 10:54:09.661245 <5>[ 1.046166] into device \"0.flash\"
462 10:54:14.379379 <6>[ 5.764263] Freeing initrd memory: 86888K
463 10:54:14.492741 <6>[ 5.877650] tun: Universal TUN/TAP device driver, 1.6
464 10:54:14.502842 <6>[ 5.887822] thunder_xcv, ver 1.0
465 10:54:14.505762 <6>[ 5.888109] thunder_bgx, ver 1.0
466 10:54:14.505961 <6>[ 5.888399] nicpf, ver 1.0
467 10:54:14.508268 <6>[ 5.893035] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
468 10:54:14.508420 <6>[ 5.893314] hns3: Copyright (c) 2017 Huawei Corporation.
469 10:54:14.508753 <6>[ 5.893827] hclge is initializing
470 10:54:14.509086 <6>[ 5.894097] e1000: Intel(R) PRO/1000 Network Driver
471 10:54:14.509440 <6>[ 5.894402] e1000: Copyright (c) 1999-2006 Intel Corporation.
472 10:54:14.509927 <6>[ 5.894756] e1000e: Intel(R) PRO/1000 Network Driver
473 10:54:14.510237 <6>[ 5.894959] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
474 10:54:14.510407 <6>[ 5.895287] igb: Intel(R) Gigabit Ethernet Network Driver
475 10:54:14.510530 <6>[ 5.895509] igb: Copyright (c) 2007-2014 Intel Corporation.
476 10:54:14.511045 <6>[ 5.895833] igbvf: Intel(R) Gigabit Virtual Function Network Driver
477 10:54:14.511133 <6>[ 5.896052] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
478 10:54:14.512213 <6>[ 5.897138] sky2: driver version 1.30
479 10:54:14.515996 <6>[ 5.901054] VFIO - User Level meta-driver version: 0.3
480 10:54:14.525411 <6>[ 5.910454] usbcore: registered new interface driver usb-storage
481 10:54:14.526344 <6>[ 5.911281] usbcore: registered new device driver onboard-usb-hub
482 10:54:14.535765 <6>[ 5.920670] rtc-pl031 9010000.pl031: registered as rtc0
483 10:54:14.536822 <6>[ 5.921440] rtc-pl031 9010000.pl031: setting system clock to 2023-06-05T10:54:14 UTC (1685962454)
484 10:54:14.539045 <6>[ 5.923950] i2c_dev: i2c /dev entries driver
485 10:54:14.557905 <6>[ 5.942697] sdhci: Secure Digital Host Controller Interface driver
486 10:54:14.558157 <6>[ 5.942876] sdhci: Copyright(c) Pierre Ossman
487 10:54:14.560019 <6>[ 5.945044] Synopsys Designware Multimedia Card Interface Driver
488 10:54:14.562723 <6>[ 5.947619] sdhci-pltfm: SDHCI platform and OF driver helper
489 10:54:14.568402 <6>[ 5.953209] ledtrig-cpu: registered to indicate activity on CPUs
490 10:54:14.574353 <6>[ 5.959153] usbcore: registered new interface driver usbhid
491 10:54:14.574630 <6>[ 5.959313] usbhid: USB HID core driver
492 10:54:14.599046 <6>[ 5.984013] NET: Registered PF_PACKET protocol family
493 10:54:14.600229 <6>[ 5.985143] 9pnet: Installing 9P2000 support
494 10:54:14.600439 <5>[ 5.985539] Key type dns_resolver registered
495 10:54:14.602096 <6>[ 5.986922] registered taskstats version 1
496 10:54:14.602523 <5>[ 5.987398] Loading compiled-in X.509 certificates
497 10:54:14.623734 <6>[ 6.008460] input: gpio-keys as /devices/platform/gpio-keys/input/input0
498 10:54:14.630308 <6>[ 6.015407] ALSA device list:
499 10:54:14.630760 <6>[ 6.015556] No soundcards found.
500 10:54:14.633250 <6>[ 6.018107] uart-pl011 9000000.pl011: no DMA platform data
501 10:54:14.689877 <6>[ 6.074809] Freeing unused kernel memory: 8384K
502 10:54:14.690960 <6>[ 6.075832] Run /init as init process
503 10:54:14.691081 <7>[ 6.075986] with arguments:
504 10:54:14.691179 <7>[ 6.076119] /init
505 10:54:14.691289 <7>[ 6.076221] verbose
506 10:54:14.691380 <7>[ 6.076309] with environment:
507 10:54:14.691468 <7>[ 6.076407] HOME=/
508 10:54:14.691566 <7>[ 6.076485] TERM=linux
509 10:54:14.827499 <30>[ 6.211832] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
510 10:54:14.828235 <31>[ 6.213138] systemd[1]: No virtualization found in DMI
511 10:54:14.829160 <31>[ 6.214062] systemd[1]: UML virtualization not found in /proc/cpuinfo.
512 10:54:14.829818 <31>[ 6.214681] systemd[1]: No virtualization found in CPUID
513 10:54:14.829956 <31>[ 6.215036] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
514 10:54:14.831217 <31>[ 6.216109] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
515 10:54:14.831561 <31>[ 6.216484] systemd[1]: Found VM virtualization qemu
516 10:54:14.831671 <30>[ 6.216730] systemd[1]: Detected virtualization qemu.
517 10:54:14.832022 <30>[ 6.217073] systemd[1]: Detected architecture arm64.
518 10:54:14.832581 <31>[ 6.217445] systemd[1]: Detected initialized system, this is not the first boot.
519 10:54:14.836512
520 10:54:14.836874 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
521 10:54:14.836984
522 10:54:14.838946 <30>[ 6.223884] systemd[1]: Set hostname to <debian-bullseye-arm64>.
523 10:54:14.858287 <31>[ 6.242988] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
524 10:54:14.859304 <31>[ 6.244190] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
525 10:54:14.859735 <31>[ 6.244682] systemd[1]: Successfully brought loopback interface up
526 10:54:14.864386 <31>[ 6.249414] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
527 10:54:14.877373 <31>[ 6.262116] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
528 10:54:14.877732 <31>[ 6.262719] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
529 10:54:14.918211 <31>[ 6.302848] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
530 10:54:14.919348 <31>[ 6.304219] systemd[1]: Controller 'cpu' supported: yes
531 10:54:14.919455 <31>[ 6.304404] systemd[1]: Controller 'cpuacct' supported: no
532 10:54:14.919551 <31>[ 6.304588] systemd[1]: Controller 'cpuset' supported: yes
533 10:54:14.919868 <31>[ 6.304758] systemd[1]: Controller 'io' supported: yes
534 10:54:14.919966 <31>[ 6.304933] systemd[1]: Controller 'blkio' supported: no
535 10:54:14.920057 <31>[ 6.305095] systemd[1]: Controller 'memory' supported: yes
536 10:54:14.920235 <31>[ 6.305300] systemd[1]: Controller 'devices' supported: no
537 10:54:14.920460 <31>[ 6.305490] systemd[1]: Controller 'pids' supported: yes
538 10:54:14.920665 <31>[ 6.305659] systemd[1]: Controller 'bpf-firewall' supported: yes
539 10:54:14.920843 <31>[ 6.305844] systemd[1]: Controller 'bpf-devices' supported: yes
540 10:54:14.922212 <31>[ 6.307225] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
541 10:54:14.922641 <31>[ 6.307590] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
542 10:54:14.923084 <31>[ 6.308066] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
543 10:54:14.930631 <31>[ 6.315395] systemd[1]: Enabling (yes) showing of status (commandline).
544 10:54:14.938716 <31>[ 6.323481] systemd[1]: Successfully forked off '(sd-executor)' as PID 98.
545 10:54:14.947319 <31>[ 6.332321] systemd[98]: Successfully forked off '(direxec)' as PID 99.
546 10:54:14.949256 <31>[ 6.334164] systemd[98]: Successfully forked off '(direxec)' as PID 100.
547 10:54:14.951460 <31>[ 6.336330] systemd[98]: Successfully forked off '(direxec)' as PID 101.
548 10:54:14.963666 <31>[ 6.348383] systemd[98]: Successfully forked off '(direxec)' as PID 102.
549 10:54:14.979303 <31>[ 6.363989] systemd[98]: Successfully forked off '(direxec)' as PID 103.
550 10:54:15.134547 <31>[ 6.519469] systemd-bless-boot-generator[99]: Skipping generator, not an EFI boot.
551 10:54:15.139893 <31>[ 6.524685] systemd-fstab-generator[100]: Parsing /etc/fstab...
552 10:54:15.148544 <31>[ 6.533301] systemd-getty-generator[101]: Automatically adding serial getty for /dev/ttyAMA0.
553 10:54:15.150454 <31>[ 6.535267] systemd-fstab-generator[100]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
554 10:54:15.153171 <31>[ 6.537948] systemd-fstab-generator[100]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
555 10:54:15.154557 <31>[ 6.539455] systemd[98]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
556 10:54:15.155223 <31>[ 6.539959] systemd[98]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
557 10:54:15.157642 <31>[ 6.542435] systemd-getty-generator[101]: SELinux enabled state cached to: disabled
558 10:54:15.164705 <31>[ 6.549399] systemd-fstab-generator[100]: SELinux enabled state cached to: disabled
559 10:54:15.170458 <31>[ 6.554875] systemd[98]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
560 10:54:15.172352 <31>[ 6.557147] systemd[98]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
561 10:54:15.172625 <31>[ 6.557534] systemd[98]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
562 10:54:15.175515 <31>[ 6.560572] systemd[1]: (sd-executor) succeeded.
563 10:54:15.177271 <31>[ 6.562109] systemd[1]: Looking for unit files in (higher priority first):
564 10:54:15.178177 <31>[ 6.563086] systemd[1]: /etc/systemd/system.control
565 10:54:15.178289 <31>[ 6.563243] systemd[1]: /run/systemd/system.control
566 10:54:15.178402 <31>[ 6.563380] systemd[1]: /run/systemd/transient
567 10:54:15.178513 <31>[ 6.563564] systemd[1]: /run/systemd/generator.early
568 10:54:15.178845 <31>[ 6.563781] systemd[1]: /etc/systemd/system
569 10:54:15.178946 <31>[ 6.563953] systemd[1]: /etc/systemd/system.attached
570 10:54:15.179054 <31>[ 6.564094] systemd[1]: /run/systemd/system
571 10:54:15.179387 <31>[ 6.564288] systemd[1]: /run/systemd/system.attached
572 10:54:15.179498 <31>[ 6.564493] systemd[1]: /run/systemd/generator
573 10:54:15.179608 <31>[ 6.564628] systemd[1]: /usr/local/lib/systemd/system
574 10:54:15.179742 <31>[ 6.564831] systemd[1]: /lib/systemd/system
575 10:54:15.180071 <31>[ 6.565026] systemd[1]: /usr/lib/systemd/system
576 10:54:15.180173 <31>[ 6.565198] systemd[1]: /run/systemd/generator.late
577 10:54:15.216080 <31>[ 6.600982] systemd[1]: Modification times have changed, need to update cache.
578 10:54:15.218276 <31>[ 6.603142] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
579 10:54:15.219915 <31>[ 6.604282] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
580 10:54:15.220510 <31>[ 6.605039] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
581 10:54:15.220932 <31>[ 6.605936] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
582 10:54:15.222303 <31>[ 6.607105] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
583 10:54:15.222478 <31>[ 6.607435] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
584 10:54:15.222939 <31>[ 6.607743] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
585 10:54:15.223137 <31>[ 6.608042] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
586 10:54:15.223378 <31>[ 6.608345] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
587 10:54:15.223904 <31>[ 6.608671] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
588 10:54:15.224114 <31>[ 6.609004] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
589 10:54:15.224921 <31>[ 6.609692] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
590 10:54:15.225148 <31>[ 6.610092] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
591 10:54:15.225944 <31>[ 6.610813] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
592 10:54:15.226555 <31>[ 6.611459] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
593 10:54:15.226931 <31>[ 6.611799] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
594 10:54:15.227364 <31>[ 6.612140] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
595 10:54:15.227712 <31>[ 6.612504] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
596 10:54:15.227845 <31>[ 6.612805] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
597 10:54:15.228500 <31>[ 6.613387] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
598 10:54:15.228905 <31>[ 6.613752] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
599 10:54:15.229941 <31>[ 6.614678] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
600 10:54:15.230175 <31>[ 6.615027] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
601 10:54:15.230416 <31>[ 6.615323] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
602 10:54:15.230660 <31>[ 6.615646] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
603 10:54:15.231191 <31>[ 6.616006] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
604 10:54:15.231470 <31>[ 6.616351] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
605 10:54:15.232284 <31>[ 6.617044] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
606 10:54:15.232875 <31>[ 6.617691] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
607 10:54:15.233141 <31>[ 6.618109] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
608 10:54:15.234009 <31>[ 6.618735] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
609 10:54:15.234236 <31>[ 6.619185] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
610 10:54:15.234808 <31>[ 6.619543] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
611 10:54:15.235042 <31>[ 6.619879] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
612 10:54:15.235286 <31>[ 6.620228] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
613 10:54:15.235649 <31>[ 6.620581] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
614 10:54:15.236248 <31>[ 6.620950] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
615 10:54:15.236473 <31>[ 6.621292] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
616 10:54:15.236715 <31>[ 6.621606] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
617 10:54:15.236922 <31>[ 6.621882] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
618 10:54:15.237416 <31>[ 6.622326] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
619 10:54:15.238055 <31>[ 6.622718] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
620 10:54:15.238280 <31>[ 6.623062] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
621 10:54:15.238475 <31>[ 6.623396] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
622 10:54:15.238977 <31>[ 6.623762] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
623 10:54:15.239572 <31>[ 6.624344] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
624 10:54:15.239811 <31>[ 6.624670] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
625 10:54:15.240377 <31>[ 6.625330] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
626 10:54:15.240951 <31>[ 6.625641] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
627 10:54:15.241151 <31>[ 6.626051] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
628 10:54:15.241631 <31>[ 6.626554] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
629 10:54:15.242163 <31>[ 6.626841] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
630 10:54:15.242725 <31>[ 6.627478] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
631 10:54:15.242998 <31>[ 6.627734] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
632 10:54:15.243212 <31>[ 6.628034] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
633 10:54:15.243418 <31>[ 6.628358] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
634 10:54:15.243934 <31>[ 6.628914] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
635 10:54:15.244518 <31>[ 6.629226] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
636 10:54:15.244708 <31>[ 6.629562] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
637 10:54:15.245354 <31>[ 6.630160] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
638 10:54:15.245973 <31>[ 6.630750] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
639 10:54:15.246353 <31>[ 6.631151] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
640 10:54:15.246479 <31>[ 6.631447] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
641 10:54:15.246813 <31>[ 6.631738] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
642 10:54:15.247360 <31>[ 6.632053] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
643 10:54:15.247590 <31>[ 6.632380] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
644 10:54:15.247799 <31>[ 6.632679] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
645 10:54:15.248332 <31>[ 6.633024] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
646 10:54:15.248529 <31>[ 6.633408] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
647 10:54:15.249052 <31>[ 6.633770] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
648 10:54:15.249227 <31>[ 6.634071] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
649 10:54:15.250025 <31>[ 6.634675] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
650 10:54:15.250222 <31>[ 6.635055] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
651 10:54:15.250419 <31>[ 6.635391] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
652 10:54:15.251230 <31>[ 6.635963] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
653 10:54:15.251357 <31>[ 6.636241] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
654 10:54:15.251729 <31>[ 6.636575] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
655 10:54:15.252317 <31>[ 6.637147] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
656 10:54:15.252701 <31>[ 6.637558] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
657 10:54:15.253081 <31>[ 6.637878] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
658 10:54:15.253698 <31>[ 6.638531] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
659 10:54:15.254135 <31>[ 6.639055] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
660 10:54:15.255069 <31>[ 6.639724] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
661 10:54:15.255260 <31>[ 6.640145] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
662 10:54:15.255858 <31>[ 6.640466] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
663 10:54:15.256068 <31>[ 6.640863] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
664 10:54:15.256259 <31>[ 6.641204] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
665 10:54:15.256820 <31>[ 6.641535] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
666 10:54:15.257017 <31>[ 6.641842] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
667 10:54:15.257300 <31>[ 6.642175] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
668 10:54:15.257793 <31>[ 6.642745] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
669 10:54:15.258447 <31>[ 6.643103] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
670 10:54:15.258651 <31>[ 6.643482] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
671 10:54:15.258887 <31>[ 6.643812] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
672 10:54:15.259506 <31>[ 6.644141] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
673 10:54:15.259739 <31>[ 6.644454] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
674 10:54:15.259941 <31>[ 6.644799] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
675 10:54:15.260487 <31>[ 6.645264] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
676 10:54:15.260697 <31>[ 6.645620] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
677 10:54:15.261204 <31>[ 6.645975] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
678 10:54:15.262179 <31>[ 6.646954] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
679 10:54:15.262406 <31>[ 6.647366] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
680 10:54:15.262872 <31>[ 6.647699] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
681 10:54:15.263348 <31>[ 6.648087] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
682 10:54:15.263550 <31>[ 6.648492] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
683 10:54:15.263992 <31>[ 6.648846] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
684 10:54:15.264555 <31>[ 6.649179] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
685 10:54:15.264772 <31>[ 6.649536] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
686 10:54:15.265276 <31>[ 6.649925] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
687 10:54:15.265817 <31>[ 6.650579] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
688 10:54:15.266040 <31>[ 6.650958] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
689 10:54:15.266583 <31>[ 6.651337] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
690 10:54:15.266827 <31>[ 6.651666] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
691 10:54:15.267045 <31>[ 6.651958] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
692 10:54:15.267556 <31>[ 6.652268] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
693 10:54:15.267753 <31>[ 6.652624] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
694 10:54:15.268295 <31>[ 6.652981] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
695 10:54:15.268481 <31>[ 6.653325] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
696 10:54:15.269020 <31>[ 6.653687] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
697 10:54:15.269210 <31>[ 6.654094] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
698 10:54:15.269679 <31>[ 6.654657] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
699 10:54:15.270233 <31>[ 6.654982] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
700 10:54:15.270450 <31>[ 6.655340] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
701 10:54:15.270654 <31>[ 6.655678] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
702 10:54:15.271165 <31>[ 6.655956] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
703 10:54:15.271397 <31>[ 6.656292] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
704 10:54:15.271916 <31>[ 6.656661] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
705 10:54:15.272117 <31>[ 6.657020] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
706 10:54:15.272340 <31>[ 6.657306] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
707 10:54:15.272550 <31>[ 6.657569] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
708 10:54:15.273325 <31>[ 6.658031] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
709 10:54:15.273889 <31>[ 6.658664] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
710 10:54:15.274455 <31>[ 6.659379] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
711 10:54:15.274980 <31>[ 6.659760] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
712 10:54:15.275193 <31>[ 6.660067] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
713 10:54:15.275384 <31>[ 6.660352] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
714 10:54:15.275827 <31>[ 6.660677] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
715 10:54:15.276049 <31>[ 6.660960] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
716 10:54:15.276362 <31>[ 6.661271] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
717 10:54:15.276564 <31>[ 6.661575] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
718 10:54:15.277088 <31>[ 6.661852] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
719 10:54:15.277248 <31>[ 6.662145] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
720 10:54:15.277892 <31>[ 6.662732] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
721 10:54:15.278329 <31>[ 6.663240] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
722 10:54:15.279248 <31>[ 6.663780] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
723 10:54:15.279810 <31>[ 6.664205] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
724 10:54:15.279997 <31>[ 6.664528] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
725 10:54:15.280200 <31>[ 6.664939] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
726 10:54:15.280391 <31>[ 6.665271] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
727 10:54:15.280941 <31>[ 6.665598] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
728 10:54:15.281139 <31>[ 6.665927] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
729 10:54:15.686411 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
730 10:54:15.690951 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
731 10:54:15.694479 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
732 10:54:15.697880 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
733 10:54:15.701404 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
734 10:54:15.702915 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
735 10:54:15.704990 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
736 10:54:15.706227 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
737 10:54:15.707011 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
738 10:54:15.707474 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
739 10:54:15.708457 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
740 10:54:15.712014 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
741 10:54:15.716051 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
742 10:54:15.718741 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
743 10:54:15.720887 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
744 10:54:15.723356 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
745 10:54:15.726067 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
746 10:54:15.728035 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
747 10:54:15.755405 Mounting [0;1;39mHuge Pages File System[0m...
748 10:54:15.778473 Mounting [0;1;39mPOSIX Message Queue File System[0m...
749 10:54:15.815221 Mounting [0;1;39mKernel Debug File System[0m...
750 10:54:15.868064 Starting [0;1;39mLoad Kernel Module configfs[0m...
751 10:54:15.923596 Starting [0;1;39mLoad Kernel Module drm[0m...
752 10:54:15.979164 Starting [0;1;39mJournal Service[0m...
753 10:54:16.010922 Starting [0;1;39mLoad Kernel Modules[0m...
754 10:54:16.043311 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
755 10:54:16.107200 Starting [0;1;39mColdplug All udev Devices[0m...
756 10:54:16.196892 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
757 10:54:16.211659 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
758 10:54:16.220508 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
759 10:54:16.270725 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
760 10:54:16.326378 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
761 10:54:16.350195 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
762 10:54:16.426665 Mounting [0;1;39mKernel Configuration File System[0m...
763 10:54:16.543740 Starting [0;1;39mApply Kernel Variables[0m...
764 10:54:16.606519 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
765 10:54:16.636553 <47>[ 8.021461] systemd-journald[109]: SELinux enabled state cached to: disabled
766 10:54:16.652027 <47>[ 8.036977] systemd-journald[109]: Auditing in kernel turned off.
767 10:54:16.681831 <47>[ 8.066729] systemd-journald[109]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
768 10:54:16.738648 <47>[ 8.123309] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
769 10:54:16.741144 <47>[ 8.125945] systemd-journald[109]: Fixed min_use=3.8M max_use=19.3M max_size=2.4M min_size=512.0K keep_free=9.6M n_max_files=100
770 10:54:16.758981 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
771 10:54:16.763242 <47>[ 8.148003] systemd-journald[109]: Reserving 333 entries in field hash table.
772 10:54:16.766157 See 'systemctl status systemd-remount-fs.service' for details.
773 10:54:16.799870 <47>[ 8.184766] systemd-journald[109]: Reserving 4408 entries in data hash table.
774 10:54:16.803683 Starting [0;1;39mLoad/Save Random Seed[0m...
775 10:54:16.804834 <47>[ 8.189870] systemd-journald[109]: Vacuuming...
776 10:54:16.806080 <47>[ 8.190906] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
777 10:54:16.806568 <47>[ 8.191626] systemd-journald[109]: Flushing /dev/kmsg...
778 10:54:16.871022 Starting [0;1;39mCreate System Users[0m...
779 10:54:16.902549 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
780 10:54:17.034533 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
781 10:54:17.195250 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
782 10:54:17.223309 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
783 10:54:17.365255 <47>[ 8.749927] systemd-journald[109]: systemd-journald running as PID 109 for the system.
784 10:54:17.379452 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
785 10:54:17.393652 <47>[ 8.778606] systemd-journald[109]: Sent READY=1 notification.
786 10:54:17.394264 <47>[ 8.779071] systemd-journald[109]: Sent WATCHDOG=1 notification.
787 10:54:17.431255 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
788 10:54:17.436368 <47>[ 8.821080] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
789 10:54:17.469652 <47>[ 8.854576] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
790 10:54:17.477722 <47>[ 8.862575] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
791 10:54:17.494052 <47>[ 8.878672] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
792 10:54:17.502641 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
793 10:54:17.506852 <47>[ 8.891635] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
794 10:54:17.515801 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
795 10:54:17.526497 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
796 10:54:17.526974 <47>[ 8.911885] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
797 10:54:17.534931 <47>[ 8.919840] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
798 10:54:17.565579 <47>[ 8.950462] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
799 10:54:17.568191 <47>[ 8.952915] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
800 10:54:17.582649 <47>[ 8.967541] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
801 10:54:17.584684 <47>[ 8.969543] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
802 10:54:17.598684 <47>[ 8.983431] systemd-journald[109]: n/a: New incoming connection.
803 10:54:17.599135 <47>[ 8.984150] systemd-journald[109]: varlink-21: varlink: setting state idle-server
804 10:54:17.614705 <47>[ 8.999363] systemd-journald[109]: varlink-21: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
805 10:54:17.616652 <47>[ 9.001428] systemd-journald[109]: varlink-21: varlink: changing state idle-server → processing-method
806 10:54:17.617144 <46>[ 9.001890] systemd-journald[109]: Received client request to flush runtime journal.
807 10:54:17.623553 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
808 10:54:17.638396 <47>[ 9.023067] systemd-journald[109]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
809 10:54:17.639148 <47>[ 9.024012] systemd-journald[109]: Vacuuming...
810 10:54:17.639851 <47>[ 9.024486] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
811 10:54:17.641137 <47>[ 9.025925] systemd-journald[109]: varlink-21: Sending message: {\"parameters\":{}}
812 10:54:17.652048 <47>[ 9.036401] systemd-journald[109]: varlink-21: varlink: changing state processing-method → processed-method
813 10:54:17.652238 <47>[ 9.036934] systemd-journald[109]: varlink-21: varlink: changing state processed-method → idle-server
814 10:54:17.663356 <47>[ 9.048198] systemd-journald[109]: varlink-21: varlink: changing state idle-server → pending-disconnect
815 10:54:17.663836 <47>[ 9.048633] systemd-journald[109]: varlink-21: varlink: changing state pending-disconnect → processing-disconnect
816 10:54:17.664207 <47>[ 9.049012] systemd-journald[109]: varlink-21: varlink: changing state processing-disconnect → disconnected
817 10:54:17.683988 <47>[ 9.068717] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
818 10:54:17.690486 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
819 10:54:17.695821 <47>[ 9.080523] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
820 10:54:17.711826 <47>[ 9.096567] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
821 10:54:17.719417 <47>[ 9.104198] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
822 10:54:17.759607 Starting [0;1;39mCreate Volatile Files and Directories[0m...
823 10:54:17.772058 <47>[ 9.156767] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
824 10:54:18.203411 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
825 10:54:18.300619 Starting [0;1;39mNetwork Service[0m...
826 10:54:18.331780 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
827 10:54:18.348847 <47>[ 9.733757] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
828 10:54:18.435825 Starting [0;1;39mNetwork Time Synchronization[0m...
829 10:54:18.468984 <47>[ 9.853881] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
830 10:54:18.503134 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
831 10:54:18.519351 <47>[ 9.904257] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
832 10:54:18.948845 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
833 10:54:19.875322 <47>[ 11.259597] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.1 (3309 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
834 10:54:19.875688 <47>[ 11.260306] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
835 10:54:19.877800 <47>[ 11.260801] systemd-journald[109]: Rotating...
836 10:54:19.877963 <47>[ 11.261795] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
837 10:54:19.890766 <47>[ 11.275689] systemd-journald[109]: Reserving 333 entries in field hash table.
838 10:54:19.899051 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
839 10:54:19.931714 <47>[ 11.316384] systemd-journald[109]: Reserving 4408 entries in data hash table.
840 10:54:19.946978 <47>[ 11.331722] systemd-journald[109]: Vacuuming...
841 10:54:19.948699 <47>[ 11.333554] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
842 10:54:19.979313 Starting [0;1;39mNetwork Name Resolution[0m...
843 10:54:20.021901 <47>[ 11.406561] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
844 10:54:20.351653 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
845 10:54:20.353736 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
846 10:54:20.358176 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
847 10:54:20.958826 <47>[ 12.343462] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
848 10:54:22.061390 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
849 10:54:22.067212 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
850 10:54:22.068431 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
851 10:54:22.116182 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
852 10:54:22.123551 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
853 10:54:22.140818 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
854 10:54:22.155334 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
855 10:54:22.163850 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
856 10:54:22.171861 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
857 10:54:22.203725 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
858 10:54:22.204469 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
859 10:54:22.205109 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
860 10:54:22.290229 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
861 10:54:22.303557 <47>[ 13.688154] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
862 10:54:22.443016 <47>[ 13.827594] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
863 10:54:22.446442 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
864 10:54:22.655974 Starting [0;1;39mUser Login Management[0m...
865 10:54:22.666979 <47>[ 14.051640] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
866 10:54:22.738944 Starting [0;1;39mPermit User Sessions[0m...
867 10:54:22.763855 <47>[ 14.148516] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
868 10:54:23.042584 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
869 10:54:23.124606 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
870 10:54:23.378520 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
871 10:54:23.850546 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
872 10:54:26.050030 [[0m[0;31m* [0m] A start job is running for /dev/ttyAMA0 (10s / 1min 30s)
873 10:54:26.421466 M[K[[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
874 10:54:26.511128 [K[[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
875 10:54:26.530118 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
876 10:54:26.546564 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
877 10:54:26.560339 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
878 10:54:26.614146 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
879 10:54:26.619104 <47>[ 18.003838] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
880 10:54:26.845029 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
881 10:54:26.949124 <47>[ 18.333708] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
882 10:54:26.962031 <47>[ 18.346635] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
883 10:54:27.035239
884 10:54:27.035452 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
885 10:54:27.035527
886 10:54:27.035882 debian-bullseye-arm64 login: root (automatic login)
887 10:54:27.035994
888 10:54:27.115871 <6>[ 18.500662] virtio_net virtio0 enp0s1: renamed from eth0
889 10:54:27.381451 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
890 10:54:27.382180
891 10:54:27.382714 The programs included with the Debian GNU/Linux system are free software;
892 10:54:27.382907 the exact distribution terms for each program are described in the
893 10:54:27.383068 individual files in /usr/share/doc/*/copyright.
894 10:54:27.383204
895 10:54:27.383335 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
896 10:54:27.383464 permitted by applicable law.
897 10:54:27.863721 <47>[ 19.248634] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
898 10:54:27.959184 <47>[ 19.343730] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3307 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
899 10:54:27.959554 <47>[ 19.344391] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
900 10:54:27.959784 <47>[ 19.344811] systemd-journald[109]: Rotating...
901 10:54:27.970038 <47>[ 19.354758] systemd-journald[109]: Reserving 333 entries in field hash table.
902 10:54:28.002227 <47>[ 19.387129] systemd-journald[109]: Reserving 4408 entries in data hash table.
903 10:54:28.005332 <47>[ 19.390137] systemd-journald[109]: Vacuuming...
904 10:54:28.032705 <47>[ 19.417382] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
905 10:54:28.140270 <47>[ 19.525190] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
906 10:54:29.869920 <47>[ 21.254780] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
907 10:54:30.326307 Matched prompt #10: / #
909 10:54:30.326901 Setting prompt string to ['/ #']
910 10:54:30.327085 end: 2.2.1 login-action (duration 00:00:22) [common]
912 10:54:30.327505 end: 2.2 auto-login-action (duration 00:00:23) [common]
913 10:54:30.327678 start: 2.3 expect-shell-connection (timeout 00:04:35) [common]
914 10:54:30.327818 Setting prompt string to ['/ #']
915 10:54:30.327941 Forcing a shell prompt, looking for ['/ #']
917 10:54:30.378497 / #
918 10:54:30.378827 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
919 10:54:30.379034 Waiting using forced prompt support (timeout 00:02:30)
920 10:54:30.380549
921 10:54:30.388128 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
922 10:54:30.388420 start: 2.4 export-device-env (timeout 00:04:35) [common]
923 10:54:30.388610 end: 2.4 export-device-env (duration 00:00:00) [common]
924 10:54:30.388775 end: 2 boot-image-retry (duration 00:00:25) [common]
925 10:54:30.389003 start: 3 lava-test-retry (timeout 00:08:51) [common]
926 10:54:30.389268 start: 3.1 lava-test-shell (timeout 00:08:51) [common]
927 10:54:30.389493 Using namespace: common
929 10:54:30.490553 / # #
930 10:54:30.490881 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
931 10:54:30.491355 #
933 10:54:30.600039 / # mkdir /lava-562569
934 10:54:30.600884 mkdir /lava-562569
936 10:54:30.730604 / # mount /dev/disk/by-uuid/571872f8-40c3-4617-a1e0-5924afc007d9 -t ext2 /lava-562569
937 10:54:30.731437 mount /dev/disk/by-uuid/571872f8-40c3-4617-a1e0-5924afc007d9 -t ext2 /lava-562569
938 10:54:30.770896 <4>[ 22.155490] ext2 filesystem being mounted at /lava-562569 supports timestamps until 2038 (0x7fffffff)
940 10:54:30.923178 / # ls -la /lava-562569/bin/lava-test-runner
941 10:54:30.924069 ls -la /lava-562569/bin/lava-test-runner
942 10:54:30.963355 -rwxr-xr-x 1 root root 1039 Jun 5 10:53 /lava-562569/bin/lava-test-runner
943 10:54:30.974781 Using /lava-562569
945 10:54:31.075799 / # export SHELL=/bin/sh
946 10:54:31.077090 export SHELL=/bin/sh
948 10:54:31.185710 / # . /lava-562569/environment
949 10:54:31.186714 . /lava-562569/environment
951 10:54:31.297710 / # /lava-562569/bin/lava-test-runner /lava-562569/0
952 10:54:31.298041 Test shell timeout: 10s (minimum of the action and connection timeout)
953 10:54:31.298829 /lava-562569/bin/lava-test-runner /lava-562569/0
954 10:54:31.460535 + export TESTRUN_ID=0_timesync-off
955 10:54:31.460908 + cd /lava-562569/0/tests/0_timesync-off
956 10:54:31.462859 + cat uuid
957 10:54:31.470950 + UUID=562569_1.1.3.1
958 10:54:31.471260 + set +x
959 10:54:31.471437 <LAVA_SIGNAL_STARTRUN 0_timesync-off 562569_1.1.3.1>
960 10:54:31.471807 Received signal: <STARTRUN> 0_timesync-off 562569_1.1.3.1
961 10:54:31.471963 Starting test lava.0_timesync-off (562569_1.1.3.1)
962 10:54:31.472129 Skipping test definition patterns.
963 10:54:31.472334 + systemctl stop systemd-timesyncd
964 10:54:31.714926 + set +x
965 10:54:31.715411 <LAVA_SIGNAL_ENDRUN 0_timesync-off 562569_1.1.3.1>
966 10:54:31.715773 Received signal: <ENDRUN> 0_timesync-off 562569_1.1.3.1
967 10:54:31.715939 Ending use of test pattern.
968 10:54:31.716067 Ending test lava.0_timesync-off (562569_1.1.3.1), duration 0.24
970 10:54:31.757734 + export TESTRUN_ID=1_kselftest-arm64_qemu
971 10:54:31.758003 + cd /lava-562569/0/tests/1_kselftest-arm64_qemu
972 10:54:31.759916 + cat uuid
973 10:54:31.767600 + UUID=562569_1.1.3.5
974 10:54:31.767920 + set +x
975 10:54:31.768142 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 562569_1.1.3.5>
976 10:54:31.768557 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 562569_1.1.3.5
977 10:54:31.768707 Starting test lava.1_kselftest-arm64_qemu (562569_1.1.3.5)
978 10:54:31.768868 Skipping test definition patterns.
979 10:54:31.769078 + cd ./automated/linux/kselftest/
980 10:54:31.773179 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip-gitlab -e -p /opt/kselftests/mainline/ -n 1 -i 1
981 10:54:31.866988 INFO: install_deps skipped
982 10:54:31.901032 --2023-06-05 10:54:31-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
983 10:54:31.993202 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
984 10:54:32.203816 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
985 10:54:32.397470 HTTP request sent, awaiting response... 200 OK
986 10:54:32.400132 Length: 2712696 (2.6M) [application/octet-stream]
987 10:54:32.401571 Saving to: 'kselftest.tar.xz'
988 10:54:32.402941
989 10:54:33.683501 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 147KB/s kselftest.tar.xz 8%[> ] 219.84K 316KB/s kselftest.tar.xz 27%[====> ] 726.09K 811KB/s kselftest.tar.xz 57%[==========> ] 1.48M 1.35MB/s kselftest.tar.xz 100%[===================>] 2.59M 2.02MB/s in 1.3s
990 10:54:33.683732
991 10:54:33.689002 2023-06-05 10:54:33 (2.02 MB/s) - 'kselftest.tar.xz' saved [2712696/2712696]
992 10:54:33.689176
993 10:54:36.684644 skiplist:
994 10:54:36.684926 ========================================
995 10:54:36.685274 ========================================
996 10:54:36.735964 arm64:tags_test
997 10:54:36.736217 arm64:run_tags_test.sh
998 10:54:36.736548 arm64:fake_sigreturn_bad_magic
999 10:54:36.736659 arm64:fake_sigreturn_bad_size
1000 10:54:36.736757 arm64:fake_sigreturn_bad_size_for_magic0
1001 10:54:36.736852 arm64:fake_sigreturn_duplicated_fpsimd
1002 10:54:36.736944 arm64:fake_sigreturn_misaligned_sp
1003 10:54:36.737037 arm64:fake_sigreturn_missing_fpsimd
1004 10:54:36.737126 arm64:fake_sigreturn_sme_change_vl
1005 10:54:36.737215 arm64:fake_sigreturn_sve_change_vl
1006 10:54:36.737536 arm64:mangle_pstate_invalid_compat_toggle
1007 10:54:36.737653 arm64:mangle_pstate_invalid_daif_bits
1008 10:54:36.737749 arm64:mangle_pstate_invalid_mode_el1h
1009 10:54:36.737845 arm64:mangle_pstate_invalid_mode_el1t
1010 10:54:36.737938 arm64:mangle_pstate_invalid_mode_el2h
1011 10:54:36.738028 arm64:mangle_pstate_invalid_mode_el2t
1012 10:54:36.738118 arm64:mangle_pstate_invalid_mode_el3h
1013 10:54:36.738208 arm64:mangle_pstate_invalid_mode_el3t
1014 10:54:36.738299 arm64:sme_trap_no_sm
1015 10:54:36.738388 arm64:sme_trap_non_streaming
1016 10:54:36.738478 arm64:sme_trap_za
1017 10:54:36.738567 arm64:sme_vl
1018 10:54:36.738657 arm64:ssve_regs
1019 10:54:36.738748 arm64:sve_regs
1020 10:54:36.738840 arm64:sve_vl
1021 10:54:36.738929 arm64:za_no_regs
1022 10:54:36.739019 arm64:za_regs
1023 10:54:36.739107 arm64:pac
1024 10:54:36.739196 arm64:fp-stress
1025 10:54:36.739293 arm64:sve-ptrace
1026 10:54:36.739385 arm64:sve-probe-vls
1027 10:54:36.739476 arm64:vec-syscfg
1028 10:54:36.739567 arm64:za-fork
1029 10:54:36.739676 arm64:za-ptrace
1030 10:54:36.739768 arm64:check_buffer_fill
1031 10:54:36.739862 arm64:check_child_memory
1032 10:54:36.739950 arm64:check_gcr_el1_cswitch
1033 10:54:36.740039 arm64:check_ksm_options
1034 10:54:36.740127 arm64:check_mmap_options
1035 10:54:36.740216 arm64:check_prctl
1036 10:54:36.740303 arm64:check_tags_inclusion
1037 10:54:36.740392 arm64:check_user_mem
1038 10:54:36.740481 arm64:btitest
1039 10:54:36.740569 arm64:nobtitest
1040 10:54:36.740657 arm64:hwcap
1041 10:54:36.740746 arm64:ptrace
1042 10:54:36.740838 arm64:syscall-abi
1043 10:54:36.740929 arm64:tpidr2
1044 10:54:36.749687 ============== Tests to run ===============
1045 10:54:36.754120 arm64:tags_test
1046 10:54:36.754335 arm64:run_tags_test.sh
1047 10:54:36.754699 arm64:fake_sigreturn_bad_magic
1048 10:54:36.754904 arm64:fake_sigreturn_bad_size
1049 10:54:36.755115 arm64:fake_sigreturn_bad_size_for_magic0
1050 10:54:36.755331 arm64:fake_sigreturn_duplicated_fpsimd
1051 10:54:36.755548 arm64:fake_sigreturn_misaligned_sp
1052 10:54:36.755752 arm64:fake_sigreturn_missing_fpsimd
1053 10:54:36.755949 arm64:fake_sigreturn_sme_change_vl
1054 10:54:36.756205 arm64:fake_sigreturn_sve_change_vl
1055 10:54:36.756397 arm64:mangle_pstate_invalid_compat_toggle
1056 10:54:36.756613 arm64:mangle_pstate_invalid_daif_bits
1057 10:54:36.756778 arm64:mangle_pstate_invalid_mode_el1h
1058 10:54:36.756901 arm64:mangle_pstate_invalid_mode_el1t
1059 10:54:36.757017 arm64:mangle_pstate_invalid_mode_el2h
1060 10:54:36.757132 arm64:mangle_pstate_invalid_mode_el2t
1061 10:54:36.757283 arm64:mangle_pstate_invalid_mode_el3h
1062 10:54:36.757419 arm64:mangle_pstate_invalid_mode_el3t
1063 10:54:36.757550 arm64:sme_trap_no_sm
1064 10:54:36.757699 arm64:sme_trap_non_streaming
1065 10:54:36.757907 arm64:sme_trap_za
1066 10:54:36.758096 arm64:sme_vl
1067 10:54:36.758280 arm64:ssve_regs
1068 10:54:36.758426 arm64:sve_regs
1069 10:54:36.758571 arm64:sve_vl
1070 10:54:36.758714 arm64:za_no_regs
1071 10:54:36.758861 arm64:za_regs
1072 10:54:36.759006 arm64:pac
1073 10:54:36.759149 arm64:fp-stress
1074 10:54:36.759291 arm64:sve-ptrace
1075 10:54:36.759433 arm64:sve-probe-vls
1076 10:54:36.759576 arm64:vec-syscfg
1077 10:54:36.759719 arm64:za-fork
1078 10:54:36.759904 arm64:za-ptrace
1079 10:54:36.760041 arm64:check_buffer_fill
1080 10:54:36.760184 arm64:check_child_memory
1081 10:54:36.760328 arm64:check_gcr_el1_cswitch
1082 10:54:36.760470 arm64:check_ksm_options
1083 10:54:36.760613 arm64:check_mmap_options
1084 10:54:36.760757 arm64:check_prctl
1085 10:54:36.760902 arm64:check_tags_inclusion
1086 10:54:36.761045 arm64:check_user_mem
1087 10:54:36.761187 arm64:btitest
1088 10:54:36.761329 arm64:nobtitest
1089 10:54:36.761472 arm64:hwcap
1090 10:54:36.761615 arm64:ptrace
1091 10:54:36.761767 arm64:syscall-abi
1092 10:54:36.761914 arm64:tpidr2
1093 10:54:36.762057 ===========End Tests to run ===============
1094 10:54:37.698795 <12>[ 29.083688] kselftest: Running tests in arm64
1095 10:54:37.727393 TAP version 13
1096 10:54:37.745437 1..48
1097 10:54:37.792706 # selftests: arm64: tags_test
1098 10:54:37.846783 ok 1 selftests: arm64: tags_test
1099 10:54:37.894728 # selftests: arm64: run_tags_test.sh
1100 10:54:37.946921 # --------------------
1101 10:54:37.947163 # running tags test
1102 10:54:37.947256 # --------------------
1103 10:54:37.947543 # [PASS]
1104 10:54:37.954902 ok 2 selftests: arm64: run_tags_test.sh
1105 10:54:38.000057 # selftests: arm64: fake_sigreturn_bad_magic
1106 10:54:38.051779 # Registered handlers for all signals.
1107 10:54:38.052017 # Detected MINSTKSIGSZ:10000
1108 10:54:38.052116 # Testcase initialized.
1109 10:54:38.052208 # uc context validated.
1110 10:54:38.052312 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1111 10:54:38.052403 # Handled SIG_COPYCTX
1112 10:54:38.052491 # Available space:3536
1113 10:54:38.052577 # Using badly built context - ERR: BAD MAGIC !
1114 10:54:38.052682 # SIG_OK -- SP:0xFFFFE660CFB0 si_addr@:0xffffe660cfb0 si_code:2 token@:0xffffe660bd50 offset:-4704
1115 10:54:38.052774 # ==>> completed. PASS(1)
1116 10:54:38.052877 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1117 10:54:38.052967 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE660BD50
1118 10:54:38.061454 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1119 10:54:38.106653 # selftests: arm64: fake_sigreturn_bad_size
1120 10:54:38.156630 # Registered handlers for all signals.
1121 10:54:38.157199 # Detected MINSTKSIGSZ:10000
1122 10:54:38.157311 # Testcase initialized.
1123 10:54:38.157399 # uc context validated.
1124 10:54:38.157486 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1125 10:54:38.157571 # Handled SIG_COPYCTX
1126 10:54:38.157664 # Available space:3536
1127 10:54:38.157748 # uc context validated.
1128 10:54:38.157848 # Using badly built context - ERR: Bad size for esr_context
1129 10:54:38.158139 # SIG_OK -- SP:0xFFFFF625A670 si_addr@:0xfffff625a670 si_code:2 token@:0xfffff6259410 offset:-4704
1130 10:54:38.158245 # ==>> completed. PASS(1)
1131 10:54:38.158330 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1132 10:54:38.158414 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF6259410
1133 10:54:38.166245 ok 4 selftests: arm64: fake_sigreturn_bad_size
1134 10:54:38.212759 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1135 10:54:38.263281 # Registered handlers for all signals.
1136 10:54:38.263542 # Detected MINSTKSIGSZ:10000
1137 10:54:38.263637 # Testcase initialized.
1138 10:54:38.263947 # uc context validated.
1139 10:54:38.264044 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1140 10:54:38.264115 # Handled SIG_COPYCTX
1141 10:54:38.264176 # Available space:3536
1142 10:54:38.264253 # Using badly built context - ERR: Bad size for terminator
1143 10:54:38.267202 # SIG_OK -- SP:0xFFFFE16449A0 si_addr@:0xffffe16449a0 si_code:2 token@:0xffffe1643740 offset:-4704
1144 10:54:38.267529 # ==>> completed. PASS(1)
1145 10:54:38.268134 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1146 10:54:38.268227 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE1643740
1147 10:54:38.274817 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1148 10:54:38.320587 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1149 10:54:38.371015 # Registered handlers for all signals.
1150 10:54:38.371248 # Detected MINSTKSIGSZ:10000
1151 10:54:38.371345 # Testcase initialized.
1152 10:54:38.371437 # uc context validated.
1153 10:54:38.371750 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1154 10:54:38.371855 # Handled SIG_COPYCTX
1155 10:54:38.371947 # Available space:3536
1156 10:54:38.372039 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1157 10:54:38.372132 # SIG_OK -- SP:0xFFFFD82E6850 si_addr@:0xffffd82e6850 si_code:2 token@:0xffffd82e55f0 offset:-4704
1158 10:54:38.372224 # ==>> completed. PASS(1)
1159 10:54:38.372527 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1160 10:54:38.379463 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD82E55F0
1161 10:54:38.379801 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1162 10:54:38.424317 # selftests: arm64: fake_sigreturn_misaligned_sp
1163 10:54:38.474051 # Registered handlers for all signals.
1164 10:54:38.474526 # Detected MINSTKSIGSZ:10000
1165 10:54:38.474634 # Testcase initialized.
1166 10:54:38.474722 # uc context validated.
1167 10:54:38.474807 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1168 10:54:38.474891 # Handled SIG_COPYCTX
1169 10:54:38.474995 # SIG_OK -- SP:0xFFFFD3E85C83 si_addr@:0xffffd3e85c83 si_code:2 token@:0xffffd3e85c83 offset:0
1170 10:54:38.475087 # ==>> completed. PASS(1)
1171 10:54:38.475175 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1172 10:54:38.475263 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD3E85C83
1173 10:54:38.482694 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1174 10:54:38.528044 # selftests: arm64: fake_sigreturn_missing_fpsimd
1175 10:54:38.577851 # Registered handlers for all signals.
1176 10:54:38.578388 # Detected MINSTKSIGSZ:10000
1177 10:54:38.578508 # Testcase initialized.
1178 10:54:38.578600 # uc context validated.
1179 10:54:38.578686 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1180 10:54:38.578773 # Handled SIG_COPYCTX
1181 10:54:38.578858 # Mangling template header. Spare space:4096
1182 10:54:38.578943 # Using badly built context - ERR: Missing FPSIMD
1183 10:54:38.579049 # SIG_OK -- SP:0xFFFFDB3446B0 si_addr@:0xffffdb3446b0 si_code:2 token@:0xffffdb343450 offset:-4704
1184 10:54:38.579141 # ==>> completed. PASS(1)
1185 10:54:38.579227 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1186 10:54:38.579331 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDB343450
1187 10:54:38.586846 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1188 10:54:38.632187 # selftests: arm64: fake_sigreturn_sme_change_vl
1189 10:54:38.681982 # Registered handlers for all signals.
1190 10:54:38.682220 # Detected MINSTKSIGSZ:10000
1191 10:54:38.682314 # Required Features: [ SME ] supported
1192 10:54:38.682400 # Incompatible Features: [] absent
1193 10:54:38.682502 # Testcase initialized.
1194 10:54:38.682588 # uc context validated.
1195 10:54:38.682671 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1196 10:54:38.682757 # Handled SIG_COPYCTX
1197 10:54:38.682841 # Attempting to change VL from 16 to 256
1198 10:54:38.682943 # SIG_OK -- SP:0xFFFFFAE4C500 si_addr@:0xfffffae4c500 si_code:2 token@:0xfffffae4b2a0 offset:-4704
1199 10:54:38.683033 # ==>> completed. PASS(1)
1200 10:54:38.683132 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1201 10:54:38.683237 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFAE4B2A0
1202 10:54:38.691118 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1203 10:54:38.736160 # selftests: arm64: fake_sigreturn_sve_change_vl
1204 10:54:38.785845 # Registered handlers for all signals.
1205 10:54:38.786081 # Detected MINSTKSIGSZ:10000
1206 10:54:38.786173 # Required Features: [ SVE ] supported
1207 10:54:38.786260 # Incompatible Features: [] absent
1208 10:54:38.786363 # Testcase initialized.
1209 10:54:38.786452 # uc context validated.
1210 10:54:38.786539 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1211 10:54:38.786625 # Handled SIG_COPYCTX
1212 10:54:38.786712 # Attempting to change VL from 16 to 256
1213 10:54:38.786814 # SIG_OK -- SP:0xFFFFFA661F50 si_addr@:0xfffffa661f50 si_code:2 token@:0xfffffa660cf0 offset:-4704
1214 10:54:38.786906 # ==>> completed. PASS(1)
1215 10:54:38.786992 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1216 10:54:38.787100 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFA660CF0
1217 10:54:38.794709 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1218 10:54:38.841226 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1219 10:54:38.891349 # Registered handlers for all signals.
1220 10:54:38.891609 # Detected MINSTKSIGSZ:10000
1221 10:54:38.892739 # Testcase initialized.
1222 10:54:38.892858 # uc context validated.
1223 10:54:38.893116 # Handled SIG_TRIG
1224 10:54:38.893221 # SIG_OK -- SP:0xFFFFE1587620 si_addr@:0xffffe1587620 si_code:2 token@:(nil) offset:-281474462414368
1225 10:54:38.893330 # ==>> completed. PASS(1)
1226 10:54:38.893433 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1227 10:54:38.900614 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1228 10:54:38.945927 # selftests: arm64: mangle_pstate_invalid_daif_bits
1229 10:54:38.994374 # Registered handlers for all signals.
1230 10:54:38.994841 # Detected MINSTKSIGSZ:10000
1231 10:54:38.995027 # Testcase initialized.
1232 10:54:38.995156 # uc context validated.
1233 10:54:38.995274 # Handled SIG_TRIG
1234 10:54:38.995390 # SIG_OK -- SP:0xFFFFCCC65370 si_addr@:0xffffccc65370 si_code:2 token@:(nil) offset:-281474117292912
1235 10:54:38.995530 # ==>> completed. PASS(1)
1236 10:54:38.996987 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1237 10:54:39.002920 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1238 10:54:39.049073 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1239 10:54:39.097820 # Registered handlers for all signals.
1240 10:54:39.098159 # Detected MINSTKSIGSZ:10000
1241 10:54:39.098311 # Testcase initialized.
1242 10:54:39.098660 # uc context validated.
1243 10:54:39.098790 # Handled SIG_TRIG
1244 10:54:39.098909 # SIG_OK -- SP:0xFFFFE8BC75E0 si_addr@:0xffffe8bc75e0 si_code:2 token@:(nil) offset:-281474586408416
1245 10:54:39.099027 # ==>> completed. PASS(1)
1246 10:54:39.099143 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1247 10:54:39.106315 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1248 10:54:39.153039 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1249 10:54:39.205006 # Registered handlers for all signals.
1250 10:54:39.205154 # Detected MINSTKSIGSZ:10000
1251 10:54:39.205251 # Testcase initialized.
1252 10:54:39.205342 # uc context validated.
1253 10:54:39.205431 # Handled SIG_TRIG
1254 10:54:39.205544 # SIG_OK -- SP:0xFFFFDB442580 si_addr@:0xffffdb442580 si_code:2 token@:(nil) offset:-281474360419712
1255 10:54:39.205840 # ==>> completed. PASS(1)
1256 10:54:39.205948 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1257 10:54:39.212271 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1258 10:54:39.257336 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1259 10:54:39.305722 # Registered handlers for all signals.
1260 10:54:39.306060 # Detected MINSTKSIGSZ:10000
1261 10:54:39.306464 # Testcase initialized.
1262 10:54:39.306608 # uc context validated.
1263 10:54:39.306735 # Handled SIG_TRIG
1264 10:54:39.306853 # SIG_OK -- SP:0xFFFFC8BA68F0 si_addr@:0xffffc8ba68f0 si_code:2 token@:(nil) offset:-281474049403120
1265 10:54:39.306974 # ==>> completed. PASS(1)
1266 10:54:39.307093 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1267 10:54:39.314109 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1268 10:54:39.360525 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1269 10:54:39.408767 # Registered handlers for all signals.
1270 10:54:39.409268 # Detected MINSTKSIGSZ:10000
1271 10:54:39.409447 # Testcase initialized.
1272 10:54:39.409573 # uc context validated.
1273 10:54:39.409709 # Handled SIG_TRIG
1274 10:54:39.409830 # SIG_OK -- SP:0xFFFFE9DCB390 si_addr@:0xffffe9dcb390 si_code:2 token@:(nil) offset:-281474605298576
1275 10:54:39.409949 # ==>> completed. PASS(1)
1276 10:54:39.410087 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1277 10:54:39.417080 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1278 10:54:39.462765 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1279 10:54:39.513731 # Registered handlers for all signals.
1280 10:54:39.514241 # Detected MINSTKSIGSZ:10000
1281 10:54:39.514466 # Testcase initialized.
1282 10:54:39.514615 # uc context validated.
1283 10:54:39.514740 # Handled SIG_TRIG
1284 10:54:39.514858 # SIG_OK -- SP:0xFFFFE07E6CF0 si_addr@:0xffffe07e6cf0 si_code:2 token@:(nil) offset:-281474448125168
1285 10:54:39.515002 # ==>> completed. PASS(1)
1286 10:54:39.515125 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1287 10:54:39.523010 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1288 10:54:39.569030 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1289 10:54:39.617744 # Registered handlers for all signals.
1290 10:54:39.618215 # Detected MINSTKSIGSZ:10000
1291 10:54:39.618325 # Testcase initialized.
1292 10:54:39.618419 # uc context validated.
1293 10:54:39.618509 # Handled SIG_TRIG
1294 10:54:39.618614 # SIG_OK -- SP:0xFFFFF23EE3B0 si_addr@:0xfffff23ee3b0 si_code:2 token@:(nil) offset:-281474745951152
1295 10:54:39.620453 # ==>> completed. PASS(1)
1296 10:54:39.620759 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1297 10:54:39.627274 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1298 10:54:39.672147 # selftests: arm64: sme_trap_no_sm
1299 10:54:39.789669 # Registered handlers for all signals.
1300 10:54:39.790109 # Detected MINSTKSIGSZ:10000
1301 10:54:39.790220 # Required Features: [ SME ] supported
1302 10:54:39.792223 # Incompatible Features: [] absent
1303 10:54:39.792528 # Testcase initialized.
1304 10:54:39.792652 # SIG_OK -- SP:0xFFFFD1FF18B0 si_addr@:0xaaaad3412514 si_code:1 token@:(nil) offset:-187650665424148
1305 10:54:39.792745 # ==>> completed. PASS(1)
1306 10:54:39.793043 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1307 10:54:39.810989 ok 19 selftests: arm64: sme_trap_no_sm
1308 10:54:39.904492 # selftests: arm64: sme_trap_non_streaming
1309 10:54:39.964820 # Registered handlers for all signals.
1310 10:54:39.965157 # Detected MINSTKSIGSZ:10000
1311 10:54:39.965569 # Required Features: [] NOT supported
1312 10:54:39.965750 # Incompatible Features: [] supported
1313 10:54:39.965927 # ==>> completed. SKIP.
1314 10:54:39.966080 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1315 10:54:39.973081 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1316 10:54:40.022365 # selftests: arm64: sme_trap_za
1317 10:54:40.070086 # Registered handlers for all signals.
1318 10:54:40.070418 # Detected MINSTKSIGSZ:10000
1319 10:54:40.070824 # Testcase initialized.
1320 10:54:40.070964 # SIG_OK -- SP:0xFFFFE404BB30 si_addr@:0xaaaab71a2510 si_code:1 token@:(nil) offset:-187650193106192
1321 10:54:40.071087 # ==>> completed. PASS(1)
1322 10:54:40.071204 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1323 10:54:40.079607 ok 21 selftests: arm64: sme_trap_za
1324 10:54:40.125411 # selftests: arm64: sme_vl
1325 10:54:40.176302 # Registered handlers for all signals.
1326 10:54:40.176793 # Detected MINSTKSIGSZ:10000
1327 10:54:40.176901 # Required Features: [ SME ] supported
1328 10:54:40.176991 # Incompatible Features: [] absent
1329 10:54:40.177074 # Testcase initialized.
1330 10:54:40.177155 # uc context validated.
1331 10:54:40.177236 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1332 10:54:40.177317 # Handled SIG_COPYCTX
1333 10:54:40.177413 # got expected VL 32
1334 10:54:40.177495 # ==>> completed. PASS(1)
1335 10:54:40.177575 # # SME VL :: Check that we get the right SME VL reported
1336 10:54:40.184782 ok 22 selftests: arm64: sme_vl
1337 10:54:40.231870 # selftests: arm64: ssve_regs
1338 10:54:40.421628 # Registered handlers for all signals.
1339 10:54:40.421899 # Detected MINSTKSIGSZ:10000
1340 10:54:40.422206 # Required Features: [ SME FA64 ] supported
1341 10:54:40.422314 # Incompatible Features: [] absent
1342 10:54:40.422405 # Testcase initialized.
1343 10:54:40.422492 # Testing VL 256
1344 10:54:40.422578 # Validating EXTRA...
1345 10:54:40.422664 # uc context validated.
1346 10:54:40.422750 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1347 10:54:40.422860 # Handled SIG_COPYCTX
1348 10:54:40.422952 # Got expected size 8752 and VL 256
1349 10:54:40.423040 # Testing VL 128
1350 10:54:40.423123 # Validating EXTRA...
1351 10:54:40.423209 # uc context validated.
1352 10:54:40.423295 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1353 10:54:40.423382 # Handled SIG_COPYCTX
1354 10:54:40.423486 # Got expected size 4384 and VL 128
1355 10:54:40.423575 # Testing VL 64
1356 10:54:40.423661 # uc context validated.
1357 10:54:40.423747 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1358 10:54:40.423834 # Handled SIG_COPYCTX
1359 10:54:40.423922 # Got expected size 2208 and VL 64
1360 10:54:40.424029 # Testing VL 32
1361 10:54:40.424117 # uc context validated.
1362 10:54:40.424203 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1363 10:54:40.424290 # Handled SIG_COPYCTX
1364 10:54:40.424373 # Got expected size 1120 and VL 32
1365 10:54:40.424475 # Testing VL 16
1366 10:54:40.424563 # uc context validated.
1367 10:54:40.424648 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1368 10:54:40.424732 # Handled SIG_COPYCTX
1369 10:54:40.424840 # Got expected size 576 and VL 16
1370 10:54:40.424929 # ==>> completed. PASS(1)
1371 10:54:40.425014 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1372 10:54:40.434573 ok 23 selftests: arm64: ssve_regs
1373 10:54:40.479721 # selftests: arm64: sve_regs
1374 10:54:40.893125 # Registered handlers for all signals.
1375 10:54:40.893387 # Detected MINSTKSIGSZ:10000
1376 10:54:40.894323 # Required Features: [ SVE ] supported
1377 10:54:40.894597 # Incompatible Features: [] absent
1378 10:54:40.894797 # Testcase initialized.
1379 10:54:40.894939 # Testing VL 256
1380 10:54:40.895061 # Validating EXTRA...
1381 10:54:40.895195 # uc context validated.
1382 10:54:40.895396 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1383 10:54:40.895573 # Handled SIG_COPYCTX
1384 10:54:40.895729 # Got expected size 8752 and VL 256
1385 10:54:40.895882 # Testing VL 240
1386 10:54:40.896021 # Validating EXTRA...
1387 10:54:40.896157 # uc context validated.
1388 10:54:40.896285 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1389 10:54:40.896413 # Handled SIG_COPYCTX
1390 10:54:40.896624 # Got expected size 8208 and VL 240
1391 10:54:40.896772 # Testing VL 224
1392 10:54:40.896893 # Validating EXTRA...
1393 10:54:40.897011 # uc context validated.
1394 10:54:40.897128 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1395 10:54:40.897245 # Handled SIG_COPYCTX
1396 10:54:40.897360 # Got expected size 7664 and VL 224
1397 10:54:40.897476 # Testing VL 208
1398 10:54:40.897590 # Validating EXTRA...
1399 10:54:40.897771 # uc context validated.
1400 10:54:40.897969 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1401 10:54:40.898155 # Handled SIG_COPYCTX
1402 10:54:40.898339 # Got expected size 7120 and VL 208
1403 10:54:40.898511 # Testing VL 192
1404 10:54:40.898655 # Validating EXTRA...
1405 10:54:40.898804 # uc context validated.
1406 10:54:40.898948 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1407 10:54:40.899092 # Handled SIG_COPYCTX
1408 10:54:40.899235 # Got expected size 6576 and VL 192
1409 10:54:40.899380 # Testing VL 176
1410 10:54:40.899523 # Validating EXTRA...
1411 10:54:40.899667 # uc context validated.
1412 10:54:40.899811 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1413 10:54:40.899956 # Handled SIG_COPYCTX
1414 10:54:40.900099 # Got expected size 6032 and VL 176
1415 10:54:40.900243 # Testing VL 160
1416 10:54:40.900387 # Validating EXTRA...
1417 10:54:40.900534 # uc context validated.
1418 10:54:40.907275 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1419 10:54:40.907662 # Handled SIG_COPYCTX
1420 10:54:40.907845 # Got expected size 5488 and VL 160
1421 10:54:40.908044 # Testing VL 144
1422 10:54:40.908262 # Validating EXTRA...
1423 10:54:40.908467 # uc context validated.
1424 10:54:40.908678 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1425 10:54:40.908834 # Handled SIG_COPYCTX
1426 10:54:40.908959 # Got expected size 4944 and VL 144
1427 10:54:40.909081 # Testing VL 128
1428 10:54:40.909199 # Validating EXTRA...
1429 10:54:40.909317 # uc context validated.
1430 10:54:40.909435 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1431 10:54:40.909604 # Handled SIG_COPYCTX
1432 10:54:40.909767 # Got expected size 4384 and VL 128
1433 10:54:40.909906 # Testing VL 112
1434 10:54:40.910093 # Validating EXTRA...
1435 10:54:40.910330 # uc context validated.
1436 10:54:40.910518 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1437 10:54:40.910677 # Handled SIG_COPYCTX
1438 10:54:40.910852 # Got expected size 3840 and VL 112
1439 10:54:40.911000 # Testing VL 96
1440 10:54:40.911144 # uc context validated.
1441 10:54:40.911326 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1442 10:54:40.911465 # Handled SIG_COPYCTX
1443 10:54:40.911610 # Got expected size 3296 and VL 96
1444 10:54:40.911754 # Testing VL 80
1445 10:54:40.911904 # uc context validated.
1446 10:54:40.912047 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1447 10:54:40.912191 # Handled SIG_COPYCTX
1448 10:54:40.912335 # Got expected size 2752 and VL 80
1449 10:54:40.912517 # Testing VL 64
1450 10:54:40.912704 # uc context validated.
1451 10:54:40.912891 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1452 10:54:40.913020 # Handled SIG_COPYCTX
1453 10:54:40.913142 # Got expected size 2208 and VL 64
1454 10:54:40.913260 # Testing VL 48
1455 10:54:40.913379 # uc context validated.
1456 10:54:40.913496 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1457 10:54:40.913615 # Handled SIG_COPYCTX
1458 10:54:40.913751 # Got expected size 1664 and VL 48
1459 10:54:40.913870 # Testing VL 32
1460 10:54:40.913987 # uc context validated.
1461 10:54:40.914105 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1462 10:54:40.914225 # Handled SIG_COPYCTX
1463 10:54:40.914343 # Got expected size 1120 and VL 32
1464 10:54:40.914462 # Testing VL 16
1465 10:54:40.916961 # uc context validated.
1466 10:54:40.917115 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1467 10:54:40.917262 # Handled SIG_COPYCTX
1468 10:54:40.917386 # Got expected size 576 and VL 16
1469 10:54:40.917508 # ==>> completed. PASS(1)
1470 10:54:40.917662 # # SVE registers :: Check that we get the right SVE registers reported
1471 10:54:40.917822 ok 24 selftests: arm64: sve_regs
1472 10:54:40.960925 # selftests: arm64: sve_vl
1473 10:54:41.012139 # Registered handlers for all signals.
1474 10:54:41.012468 # Detected MINSTKSIGSZ:10000
1475 10:54:41.012577 # Required Features: [ SVE ] supported
1476 10:54:41.012673 # Incompatible Features: [] absent
1477 10:54:41.014093 # Testcase initialized.
1478 10:54:41.014293 # uc context validated.
1479 10:54:41.014687 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1480 10:54:41.014853 # Handled SIG_COPYCTX
1481 10:54:41.014985 # got expected VL 64
1482 10:54:41.015110 # ==>> completed. PASS(1)
1483 10:54:41.015237 # # SVE VL :: Check that we get the right SVE VL reported
1484 10:54:41.021325 ok 25 selftests: arm64: sve_vl
1485 10:54:41.064753 # selftests: arm64: za_no_regs
1486 10:54:41.137600 # Registered handlers for all signals.
1487 10:54:41.138215 # Detected MINSTKSIGSZ:10000
1488 10:54:41.138414 # Required Features: [ SME ] supported
1489 10:54:41.138584 # Incompatible Features: [] absent
1490 10:54:41.138733 # Testcase initialized.
1491 10:54:41.138943 # Testing VL 256
1492 10:54:41.139133 # uc context validated.
1493 10:54:41.139315 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1494 10:54:41.139495 # Handled SIG_COPYCTX
1495 10:54:41.139636 # Got expected size 16 and VL 256
1496 10:54:41.139765 # Testing VL 128
1497 10:54:41.139950 # uc context validated.
1498 10:54:41.140129 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1499 10:54:41.140324 # Handled SIG_COPYCTX
1500 10:54:41.140498 # Got expected size 16 and VL 128
1501 10:54:41.140646 # Testing VL 64
1502 10:54:41.140789 # uc context validated.
1503 10:54:41.140933 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1504 10:54:41.141078 # Handled SIG_COPYCTX
1505 10:54:41.141224 # Got expected size 16 and VL 64
1506 10:54:41.141368 # Testing VL 32
1507 10:54:41.141511 # uc context validated.
1508 10:54:41.141664 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1509 10:54:41.141812 # Handled SIG_COPYCTX
1510 10:54:41.141954 # Got expected size 16 and VL 32
1511 10:54:41.142098 # Testing VL 16
1512 10:54:41.142261 # uc context validated.
1513 10:54:41.142428 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1514 10:54:41.142567 # Handled SIG_COPYCTX
1515 10:54:41.142686 # Got expected size 16 and VL 16
1516 10:54:41.142804 # ==>> completed. PASS(1)
1517 10:54:41.142949 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1518 10:54:41.162981 ok 26 selftests: arm64: za_no_regs
1519 10:54:41.236690 # selftests: arm64: za_regs
1520 10:54:41.410683 # Registered handlers for all signals.
1521 10:54:41.411008 # Detected MINSTKSIGSZ:10000
1522 10:54:41.411417 # Required Features: [ SME ] supported
1523 10:54:41.411519 # Incompatible Features: [] absent
1524 10:54:41.411607 # Testcase initialized.
1525 10:54:41.411683 # Testing VL 256
1526 10:54:41.411766 # Validating EXTRA...
1527 10:54:41.411842 # uc context validated.
1528 10:54:41.411919 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1529 10:54:41.411997 # Handled SIG_COPYCTX
1530 10:54:41.412073 # Got expected size 65552 and VL 256
1531 10:54:41.412150 # Testing VL 128
1532 10:54:41.412243 # Validating EXTRA...
1533 10:54:41.412324 # uc context validated.
1534 10:54:41.412402 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1535 10:54:41.412481 # Handled SIG_COPYCTX
1536 10:54:41.412557 # Got expected size 16400 and VL 128
1537 10:54:41.412640 # Testing VL 64
1538 10:54:41.412717 # Validating EXTRA...
1539 10:54:41.412795 # uc context validated.
1540 10:54:41.419233 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1541 10:54:41.419822 # Handled SIG_COPYCTX
1542 10:54:41.420008 # Got expected size 4112 and VL 64
1543 10:54:41.420169 # Testing VL 32
1544 10:54:41.420294 # uc context validated.
1545 10:54:41.420413 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1546 10:54:41.420530 # Handled SIG_COPYCTX
1547 10:54:41.420648 # Got expected size 1040 and VL 32
1548 10:54:41.420773 # Testing VL 16
1549 10:54:41.421023 # uc context validated.
1550 10:54:41.421211 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1551 10:54:41.421341 # Handled SIG_COPYCTX
1552 10:54:41.421499 # Got expected size 272 and VL 16
1553 10:54:41.421631 # ==>> completed. PASS(1)
1554 10:54:41.421809 # # ZA register :: Check that we get the right ZA registers reported
1555 10:54:41.421967 ok 27 selftests: arm64: za_regs
1556 10:54:41.465987 # selftests: arm64: pac
1557 10:54:41.615826 # TAP version 13
1558 10:54:41.616102 # 1..7
1559 10:54:41.617975 # # Starting 7 tests from 1 test cases.
1560 10:54:41.618184 # # RUN global.corrupt_pac ...
1561 10:54:41.618401 # # OK global.corrupt_pac
1562 10:54:41.618563 # ok 1 global.corrupt_pac
1563 10:54:41.618712 # # RUN global.pac_instructions_not_nop ...
1564 10:54:41.618874 # # OK global.pac_instructions_not_nop
1565 10:54:41.619065 # ok 2 global.pac_instructions_not_nop
1566 10:54:41.619317 # # RUN global.pac_instructions_not_nop_generic ...
1567 10:54:41.619497 # # OK global.pac_instructions_not_nop_generic
1568 10:54:41.619681 # ok 3 global.pac_instructions_not_nop_generic
1569 10:54:41.619828 # # RUN global.single_thread_different_keys ...
1570 10:54:41.619953 # # OK global.single_thread_different_keys
1571 10:54:41.620071 # ok 4 global.single_thread_different_keys
1572 10:54:41.620188 # # RUN global.exec_changed_keys ...
1573 10:54:41.620332 # # OK global.exec_changed_keys
1574 10:54:41.620458 # ok 5 global.exec_changed_keys
1575 10:54:41.620578 # # RUN global.context_switch_keep_keys ...
1576 10:54:41.628555 # # OK global.context_switch_keep_keys
1577 10:54:41.628848 # ok 6 global.context_switch_keep_keys
1578 10:54:41.629311 # # RUN global.context_switch_keep_keys_generic ...
1579 10:54:41.629486 # # OK global.context_switch_keep_keys_generic
1580 10:54:41.629614 # ok 7 global.context_switch_keep_keys_generic
1581 10:54:41.629749 # # PASSED: 7 / 7 tests passed.
1582 10:54:41.629868 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1583 10:54:41.630009 ok 28 selftests: arm64: pac
1584 10:54:41.678553 # selftests: arm64: fp-stress
1585 10:54:56.752544 # TAP version 13
1586 10:54:56.753011 # 1..27
1587 10:54:56.758204 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1588 10:54:56.758738 # # Will run for 10s
1589 10:54:56.758928 # # Started FPSIMD-0-0
1590 10:54:56.759091 # # Started SVE-VL-256-0
1591 10:54:56.759249 # # Started SVE-VL-240-0
1592 10:54:56.759437 # # Started SVE-VL-224-0
1593 10:54:56.759630 # # Started SVE-VL-208-0
1594 10:54:56.759808 # # Started SVE-VL-192-0
1595 10:54:56.759955 # # Started SVE-VL-176-0
1596 10:54:56.760080 # # Started SVE-VL-160-0
1597 10:54:56.760207 # # Started SVE-VL-144-0
1598 10:54:56.760332 # # Started SVE-VL-128-0
1599 10:54:56.760491 # # Started SVE-VL-112-0
1600 10:54:56.760624 # # Started SVE-VL-96-0
1601 10:54:56.760746 # # Started SVE-VL-80-0
1602 10:54:56.760861 # # Started SVE-VL-64-0
1603 10:54:56.760976 # # Started SVE-VL-48-0
1604 10:54:56.761091 # # Started SVE-VL-32-0
1605 10:54:56.761203 # # Started SVE-VL-16-0
1606 10:54:56.761317 # # Started SSVE-VL-256-0
1607 10:54:56.761469 # # Started ZA-VL-256-0
1608 10:54:56.761598 # # Started SSVE-VL-128-0
1609 10:54:56.761733 # # Started ZA-VL-128-0
1610 10:54:56.761850 # # Started SSVE-VL-64-0
1611 10:54:56.761966 # # Started ZA-VL-64-0
1612 10:54:56.762079 # # Started SSVE-VL-32-0
1613 10:54:56.762194 # # Started ZA-VL-32-0
1614 10:54:56.762308 # # Started SSVE-VL-16-0
1615 10:54:56.762423 # # Started ZA-VL-16-0
1616 10:54:56.762536 # # SVE-VL-256-0: Vector length: 2048 bits
1617 10:54:56.762652 # # FPSIMD-0-0: Vector length: 128 bits
1618 10:54:56.762767 # # FPSIMD-0-0: PID: 912
1619 10:54:56.762880 # # SVE-VL-256-0: PID: 913
1620 10:54:56.762993 # # SVE-VL-208-0: Vector length: 1664 bits
1621 10:54:56.763107 # # SVE-VL-208-0: PID: 916
1622 10:54:56.763274 # # SVE-VL-224-0: Vector length: 1792 bits
1623 10:54:56.763418 # # SVE-VL-224-0: PID: 915
1624 10:54:56.763536 # # SVE-VL-240-0: Vector length: 1920 bits
1625 10:54:56.773739 # # SVE-VL-240-0: PID: 914
1626 10:54:56.774228 # # SVE-VL-192-0: Vector length: 1536 bits
1627 10:54:56.774375 # # SVE-VL-192-0: PID: 917
1628 10:54:56.774507 # # SVE-VL-144-0: Vector length: 1152 bits
1629 10:54:56.774636 # # SVE-VL-144-0: PID: 920
1630 10:54:56.774765 # # SVE-VL-80-0: Vector length: 640 bits
1631 10:54:56.774891 # # SVE-VL-80-0: PID: 924
1632 10:54:56.775063 # # SVE-VL-128-0: Vector length: 1024 bits
1633 10:54:56.775223 # # SVE-VL-128-0: PID: 921
1634 10:54:56.775368 # # SVE-VL-112-0: Vector length: 896 bits
1635 10:54:56.775499 # # SVE-VL-112-0: PID: 922
1636 10:54:56.775618 # # SVE-VL-32-0: Vector length: 256 bits
1637 10:54:56.775758 # # SVE-VL-32-0: PID: 927
1638 10:54:56.775883 # # SVE-VL-176-0: Vector length: 1408 bits
1639 10:54:56.776018 # # SVE-VL-176-0: PID: 918
1640 10:54:56.776160 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1641 10:54:56.776356 # # SSVE-VL-64-0: PID: 933
1642 10:54:56.776555 # # SVE-VL-160-0: Vector length: 1280 bits
1643 10:54:56.776733 # # SVE-VL-160-0: PID: 919
1644 10:54:56.776925 # # SVE-VL-96-0: Vector length: 768 bits
1645 10:54:56.777064 # # SVE-VL-96-0: PID: 923
1646 10:54:56.777209 # # SVE-VL-48-0: Vector length: 384 bits
1647 10:54:56.777353 # # SVE-VL-48-0: PID: 926
1648 10:54:56.777497 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1649 10:54:56.777641 # # SSVE-VL-16-0: PID: 937
1650 10:54:56.777801 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1651 10:54:56.777945 # # SVE-VL-16-0: Vector length: 128 bits
1652 10:54:56.778089 # # SVE-VL-16-0: PID: 928
1653 10:54:56.778232 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1654 10:54:56.778375 # # SSVE-VL-32-0: PID: 935
1655 10:54:56.778516 # # ZA-VL-128-0: PID: 932
1656 10:54:56.778660 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1657 10:54:56.778803 # # SSVE-VL-128-0: PID: 931
1658 10:54:56.795190 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1659 10:54:56.795425 # # SSVE-VL-256-0: PID: 929
1660 10:54:56.795736 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1661 10:54:56.795832 # # ZA-VL-256-0: PID: 930
1662 10:54:56.795937 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1663 10:54:56.796051 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1664 10:54:56.796148 # # SVE-VL-64-0: Vector length: 512 bits
1665 10:54:56.796249 # # SVE-VL-64-0: PID: 925
1666 10:54:56.796343 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1667 10:54:56.796423 # # ZA-VL-16-0: PID: 938
1668 10:54:56.796490 # # ZA-VL-64-0: PID: 934
1669 10:54:56.796576 # # ZA-VL-32-0: PID: 936
1670 10:54:56.796663 # # Finishing up...
1671 10:54:56.796730 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=2827, signals=9
1672 10:54:56.796794 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=2996, signals=9
1673 10:54:56.801839 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=3708, signals=9
1674 10:54:56.802214 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2531, signals=9
1675 10:54:56.802305 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1685, signals=10
1676 10:54:56.802415 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=1114, signals=10
1677 10:54:56.802508 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=6874, signals=9
1678 10:54:56.802618 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=3638, signals=9
1679 10:54:56.802916 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=696, signals=10
1680 10:54:56.803004 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=8978, signals=9
1681 10:54:56.803112 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=4778, signals=10
1682 10:54:56.803208 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=3936, signals=9
1683 10:54:56.803319 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=3671, signals=10
1684 10:54:56.803783 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=11503, signals=10
1685 10:54:56.803870 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=9107, signals=10
1686 10:54:56.803953 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1579, signals=10
1687 10:54:56.896463 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=4612, signals=9
1688 10:54:56.896672 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3209, signals=9
1689 10:54:56.896799 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=160, signals=10
1690 10:54:56.903357 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=4478, signals=9
1691 10:54:56.903952 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=2799, signals=9
1692 10:54:56.904115 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=5164, signals=10
1693 10:54:56.904254 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2339, signals=9
1694 10:54:56.904413 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=5809, signals=10
1695 10:54:56.904550 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=11576, signals=9
1696 10:54:56.904700 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2096, signals=9
1697 10:54:56.914981 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2547, signals=9
1698 10:54:56.915290 # ok 1 FPSIMD-0-0
1699 10:54:56.915664 # ok 2 SVE-VL-256-0
1700 10:54:56.915819 # ok 3 SVE-VL-240-0
1701 10:54:56.915950 # ok 4 SVE-VL-224-0
1702 10:54:56.916075 # ok 5 SVE-VL-208-0
1703 10:54:56.916202 # ok 6 SVE-VL-192-0
1704 10:54:56.916328 # ok 7 SVE-VL-176-0
1705 10:54:56.916454 # ok 8 SVE-VL-160-0
1706 10:54:56.916583 # ok 9 SVE-VL-144-0
1707 10:54:56.916707 # ok 10 SVE-VL-128-0
1708 10:54:56.916828 # ok 11 SVE-VL-112-0
1709 10:54:56.916981 # ok 12 SVE-VL-96-0
1710 10:54:56.917111 # ok 13 SVE-VL-80-0
1711 10:54:56.917237 # ok 14 SVE-VL-64-0
1712 10:54:56.917362 # ok 15 SVE-VL-48-0
1713 10:54:56.917485 # ok 16 SVE-VL-32-0
1714 10:54:56.917608 # ok 17 SVE-VL-16-0
1715 10:54:56.917742 # ok 18 SSVE-VL-256-0
1716 10:54:56.917860 # ok 19 ZA-VL-256-0
1717 10:54:56.917977 # ok 20 SSVE-VL-128-0
1718 10:54:56.918100 # ok 21 ZA-VL-128-0
1719 10:54:56.918227 # ok 22 SSVE-VL-64-0
1720 10:54:56.918353 # ok 23 ZA-VL-64-0
1721 10:54:56.918477 # ok 24 SSVE-VL-32-0
1722 10:54:56.918600 # ok 25 ZA-VL-32-0
1723 10:54:56.926202 # ok 26 SSVE-VL-16-0
1724 10:54:56.926445 # ok 27 ZA-VL-16-0
1725 10:54:56.926757 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1726 10:54:56.926865 ok 29 selftests: arm64: fp-stress
1727 10:54:57.116450 # selftests: arm64: sve-ptrace
1728 10:54:57.279328 # TAP version 13
1729 10:54:57.279680 # 1..4104
1730 10:54:57.279854 # # Parent is 955, child is 956
1731 10:54:57.280277 # ok 1 SVE FPSIMD set via SVE: 0
1732 10:54:57.280392 # ok 2 SVE get_fpsimd() gave same state
1733 10:54:57.280486 # ok 3 SVE SVE_PT_VL_INHERIT set
1734 10:54:57.280572 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1735 10:54:57.280655 # ok 5 Set SVE VL 16
1736 10:54:57.280741 # ok 6 Set and get SVE data for VL 16
1737 10:54:57.280822 # ok 7 Set and get FPSIMD data for SVE VL 16
1738 10:54:57.280904 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1739 10:54:57.280984 # ok 9 Set SVE VL 32
1740 10:54:57.281064 # ok 10 Set and get SVE data for VL 32
1741 10:54:57.281152 # ok 11 Set and get FPSIMD data for SVE VL 32
1742 10:54:57.281260 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1743 10:54:57.281354 # ok 13 Set SVE VL 48
1744 10:54:57.281442 # ok 14 Set and get SVE data for VL 48
1745 10:54:57.281767 # ok 15 Set and get FPSIMD data for SVE VL 48
1746 10:54:57.281889 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1747 10:54:57.281998 # ok 17 Set SVE VL 64
1748 10:54:57.282090 # ok 18 Set and get SVE data for VL 64
1749 10:54:57.282196 # ok 19 Set and get FPSIMD data for SVE VL 64
1750 10:54:57.282288 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1751 10:54:57.282395 # ok 21 Set SVE VL 80
1752 10:54:57.282488 # ok 22 Set and get SVE data for VL 80
1753 10:54:57.282593 # ok 23 Set and get FPSIMD data for SVE VL 80
1754 10:54:57.282684 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1755 10:54:57.282788 # ok 25 Set SVE VL 96
1756 10:54:57.282893 # ok 26 Set and get SVE data for VL 96
1757 10:54:57.282984 # ok 27 Set and get FPSIMD data for SVE VL 96
1758 10:54:57.283090 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1759 10:54:57.283182 # ok 29 Set SVE VL 112
1760 10:54:57.283288 # ok 30 Set and get SVE data for VL 112
1761 10:54:57.283391 # ok 31 Set and get FPSIMD data for SVE VL 112
1762 10:54:57.283497 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1763 10:54:57.283585 # ok 33 Set SVE VL 128
1764 10:54:57.283684 # ok 34 Set and get SVE data for VL 128
1765 10:54:57.283792 # ok 35 Set and get FPSIMD data for SVE VL 128
1766 10:54:57.283893 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1767 10:54:57.284172 # ok 37 Set SVE VL 144
1768 10:54:57.284447 # ok 38 Set and get SVE data for VL 144
1769 10:54:57.284534 # ok 39 Set and get FPSIMD data for SVE VL 144
1770 10:54:57.284616 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1771 10:54:57.284696 # ok 41 Set SVE VL 160
1772 10:54:57.290509 # ok 42 Set and get SVE data for VL 160
1773 10:54:57.290620 # ok 43 Set and get FPSIMD data for SVE VL 160
1774 10:54:57.290942 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1775 10:54:57.291151 # ok 45 Set SVE VL 176
1776 10:54:57.291329 # ok 46 Set and get SVE data for VL 176
1777 10:54:57.291481 # ok 47 Set and get FPSIMD data for SVE VL 176
1778 10:54:57.291663 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1779 10:54:57.291840 # ok 49 Set SVE VL 192
1780 10:54:57.292025 # ok 50 Set and get SVE data for VL 192
1781 10:54:57.292208 # ok 51 Set and get FPSIMD data for SVE VL 192
1782 10:54:57.292354 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1783 10:54:57.292536 # ok 53 Set SVE VL 208
1784 10:54:57.292667 # ok 54 Set and get SVE data for VL 208
1785 10:54:57.292785 # ok 55 Set and get FPSIMD data for SVE VL 208
1786 10:54:57.292902 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1787 10:54:57.293017 # ok 57 Set SVE VL 224
1788 10:54:57.293133 # ok 58 Set and get SVE data for VL 224
1789 10:54:57.293250 # ok 59 Set and get FPSIMD data for SVE VL 224
1790 10:54:57.293365 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1791 10:54:57.293482 # ok 61 Set SVE VL 240
1792 10:54:57.293809 # ok 62 Set and get SVE data for VL 240
1793 10:54:57.293920 # ok 63 Set and get FPSIMD data for SVE VL 240
1794 10:54:57.294015 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1795 10:54:57.294105 # ok 65 Set SVE VL 256
1796 10:54:57.294193 # ok 66 Set and get SVE data for VL 256
1797 10:54:57.294296 # ok 67 Set and get FPSIMD data for SVE VL 256
1798 10:54:57.294385 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1799 10:54:57.294473 # ok 69 Set SVE VL 272
1800 10:54:57.294564 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1801 10:54:57.294667 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1802 10:54:57.294756 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1803 10:54:57.294843 # ok 73 Set SVE VL 288
1804 10:54:57.294944 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1805 10:54:57.295033 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1806 10:54:57.295121 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1807 10:54:57.295224 # ok 77 Set SVE VL 304
1808 10:54:57.295312 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1809 10:54:57.295414 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1810 10:54:57.295516 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1811 10:54:57.295605 # ok 81 Set SVE VL 320
1812 10:54:57.295704 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1813 10:54:57.295803 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1814 10:54:57.295900 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1815 10:54:57.295981 # ok 85 Set SVE VL 336
1816 10:54:57.296380 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1817 10:54:57.296487 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1818 10:54:57.296579 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1819 10:54:57.296683 # ok 89 Set SVE VL 352
1820 10:54:57.306533 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1821 10:54:57.307113 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1822 10:54:57.307339 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1823 10:54:57.307546 # ok 93 Set SVE VL 368
1824 10:54:57.307737 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1825 10:54:57.307877 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1826 10:54:57.308029 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1827 10:54:57.308154 # ok 97 Set SVE VL 384
1828 10:54:57.308271 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1829 10:54:57.308394 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1830 10:54:57.308508 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1831 10:54:57.308621 # ok 101 Set SVE VL 400
1832 10:54:57.310127 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1833 10:54:57.310658 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1834 10:54:57.310879 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1835 10:54:57.311072 # ok 105 Set SVE VL 416
1836 10:54:57.311281 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1837 10:54:57.311457 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1838 10:54:57.311618 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1839 10:54:57.311753 # ok 109 Set SVE VL 432
1840 10:54:57.311891 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1841 10:54:57.312015 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1842 10:54:57.312200 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1843 10:54:57.312427 # ok 113 Set SVE VL 448
1844 10:54:57.312583 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1845 10:54:57.312708 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1846 10:54:57.312827 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1847 10:54:57.312942 # ok 117 Set SVE VL 464
1848 10:54:57.313055 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1849 10:54:57.313168 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1850 10:54:57.313307 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1851 10:54:57.313428 # ok 121 Set SVE VL 480
1852 10:54:57.325674 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1853 10:54:57.326283 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1854 10:54:57.326523 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1855 10:54:57.326746 # ok 125 Set SVE VL 496
1856 10:54:57.326960 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1857 10:54:57.327172 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1858 10:54:57.327427 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1859 10:54:57.327643 # ok 129 Set SVE VL 512
1860 10:54:57.327846 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1861 10:54:57.328030 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1862 10:54:57.328221 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1863 10:54:57.328418 # ok 133 Set SVE VL 528
1864 10:54:57.328621 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1865 10:54:57.328770 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1866 10:54:57.328894 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1867 10:54:57.329011 # ok 137 Set SVE VL 544
1868 10:54:57.329159 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1869 10:54:57.329290 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1870 10:54:57.329416 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1871 10:54:57.329541 # ok 141 Set SVE VL 560
1872 10:54:57.330104 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1873 10:54:57.330289 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1874 10:54:57.330437 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1875 10:54:57.330582 # ok 145 Set SVE VL 576
1876 10:54:57.330725 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1877 10:54:57.334478 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1878 10:54:57.335013 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1879 10:54:57.335304 # ok 149 Set SVE VL 592
1880 10:54:57.335489 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1881 10:54:57.335658 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1882 10:54:57.335858 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1883 10:54:57.336026 # ok 153 Set SVE VL 608
1884 10:54:57.336187 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1885 10:54:57.336368 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1886 10:54:57.336550 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1887 10:54:57.336683 # ok 157 Set SVE VL 624
1888 10:54:57.336801 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1889 10:54:57.336947 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1890 10:54:57.337069 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1891 10:54:57.337239 # ok 161 Set SVE VL 640
1892 10:54:57.337422 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1893 10:54:57.337582 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1894 10:54:57.337784 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1895 10:54:57.337928 # ok 165 Set SVE VL 656
1896 10:54:57.338073 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1897 10:54:57.338232 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1898 10:54:57.338383 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1899 10:54:57.338546 # ok 169 Set SVE VL 672
1900 10:54:57.338706 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1901 10:54:57.338922 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1902 10:54:57.339112 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1903 10:54:57.339287 # ok 173 Set SVE VL 688
1904 10:54:57.339474 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1905 10:54:57.339633 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1906 10:54:57.339891 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1907 10:54:57.340098 # ok 177 Set SVE VL 704
1908 10:54:57.340309 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1909 10:54:57.340504 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1910 10:54:57.340669 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1911 10:54:57.340802 # ok 181 Set SVE VL 720
1912 10:54:57.340920 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1913 10:54:57.341034 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1914 10:54:57.341148 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1915 10:54:57.341262 # ok 185 Set SVE VL 736
1916 10:54:57.341409 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1917 10:54:57.341534 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1918 10:54:57.341667 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1919 10:54:57.341787 # ok 189 Set SVE VL 752
1920 10:54:57.341901 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1921 10:54:57.350070 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1922 10:54:57.350388 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1923 10:54:57.350796 # ok 193 Set SVE VL 768
1924 10:54:57.350973 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1925 10:54:57.351148 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1926 10:54:57.351321 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1927 10:54:57.351540 # ok 197 Set SVE VL 784
1928 10:54:57.351739 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1929 10:54:57.351941 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1930 10:54:57.352121 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1931 10:54:57.352284 # ok 201 Set SVE VL 800
1932 10:54:57.352439 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1933 10:54:57.352578 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1934 10:54:57.352699 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1935 10:54:57.352816 # ok 205 Set SVE VL 816
1936 10:54:57.352932 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1937 10:54:57.353048 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1938 10:54:57.353190 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1939 10:54:57.353312 # ok 209 Set SVE VL 832
1940 10:54:57.353430 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1941 10:54:57.353547 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1942 10:54:57.353688 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1943 10:54:57.361254 # ok 213 Set SVE VL 848
1944 10:54:57.361720 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1945 10:54:57.361954 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1946 10:54:57.362192 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1947 10:54:57.362445 # ok 217 Set SVE VL 864
1948 10:54:57.362670 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1949 10:54:57.362890 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1950 10:54:57.363084 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1951 10:54:57.363290 # ok 221 Set SVE VL 880
1952 10:54:57.363565 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1953 10:54:57.363790 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1954 10:54:57.364005 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1955 10:54:57.364235 # ok 225 Set SVE VL 896
1956 10:54:57.364450 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1957 10:54:57.364610 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1958 10:54:57.364742 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1959 10:54:57.364863 # ok 229 Set SVE VL 912
1960 10:54:57.365011 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1961 10:54:57.365154 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1962 10:54:57.365273 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1963 10:54:57.365398 # ok 233 Set SVE VL 928
1964 10:54:57.365545 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1965 10:54:57.366124 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1966 10:54:57.366283 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1967 10:54:57.366428 # ok 237 Set SVE VL 944
1968 10:54:57.366588 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1969 10:54:57.366745 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1970 10:54:57.372995 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1971 10:54:57.373188 # ok 241 Set SVE VL 960
1972 10:54:57.373600 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1973 10:54:57.373772 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1974 10:54:57.373910 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1975 10:54:57.374069 # ok 245 Set SVE VL 976
1976 10:54:57.374260 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1977 10:54:57.374400 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1978 10:54:57.374593 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1979 10:54:57.374771 # ok 249 Set SVE VL 992
1980 10:54:57.374977 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1981 10:54:57.375156 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1982 10:54:57.375363 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1983 10:54:57.375584 # ok 253 Set SVE VL 1008
1984 10:54:57.375753 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1985 10:54:57.375876 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1986 10:54:57.376025 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1987 10:54:57.376171 # ok 257 Set SVE VL 1024
1988 10:54:57.376328 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1989 10:54:57.376465 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1990 10:54:57.376585 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1991 10:54:57.376701 # ok 261 Set SVE VL 1040
1992 10:54:57.376819 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1993 10:54:57.376949 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1994 10:54:57.377107 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1995 10:54:57.377257 # ok 265 Set SVE VL 1056
1996 10:54:57.377382 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1997 10:54:57.377502 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1998 10:54:57.380125 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1999 10:54:57.380241 # ok 269 Set SVE VL 1072
2000 10:54:57.380350 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
2001 10:54:57.380456 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
2002 10:54:57.381161 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2003 10:54:57.381494 # ok 273 Set SVE VL 1088
2004 10:54:57.381722 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2005 10:54:57.381947 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2006 10:54:57.382126 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2007 10:54:57.382299 # ok 277 Set SVE VL 1104
2008 10:54:57.382452 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2009 10:54:57.382630 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2010 10:54:57.382815 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2011 10:54:57.383005 # ok 281 Set SVE VL 1120
2012 10:54:57.383175 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2013 10:54:57.383343 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2014 10:54:57.383540 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2015 10:54:57.383682 # ok 285 Set SVE VL 1136
2016 10:54:57.383815 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2017 10:54:57.383967 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2018 10:54:57.384090 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2019 10:54:57.384208 # ok 289 Set SVE VL 1152
2020 10:54:57.384325 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2021 10:54:57.384441 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2022 10:54:57.384583 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2023 10:54:57.394054 # ok 293 Set SVE VL 1168
2024 10:54:57.394285 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2025 10:54:57.394495 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2026 10:54:57.394686 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2027 10:54:57.394880 # ok 297 Set SVE VL 1184
2028 10:54:57.395105 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2029 10:54:57.395348 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2030 10:54:57.395532 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2031 10:54:57.395735 # ok 301 Set SVE VL 1200
2032 10:54:57.395925 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2033 10:54:57.396107 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2034 10:54:57.396292 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2035 10:54:57.396436 # ok 305 Set SVE VL 1216
2036 10:54:57.396590 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2037 10:54:57.396716 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2038 10:54:57.396836 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2039 10:54:57.396955 # ok 309 Set SVE VL 1232
2040 10:54:57.397070 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2041 10:54:57.397185 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2042 10:54:57.397300 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2043 10:54:57.397417 # ok 313 Set SVE VL 1248
2044 10:54:57.403812 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2045 10:54:57.404218 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2046 10:54:57.404409 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2047 10:54:57.404603 # ok 317 Set SVE VL 1264
2048 10:54:57.404811 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2049 10:54:57.405190 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2050 10:54:57.405428 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2051 10:54:57.405690 # ok 321 Set SVE VL 1280
2052 10:54:57.405884 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2053 10:54:57.406072 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2054 10:54:57.406284 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2055 10:54:57.406454 # ok 325 Set SVE VL 1296
2056 10:54:57.406650 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2057 10:54:57.406844 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2058 10:54:57.407075 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2059 10:54:57.407265 # ok 329 Set SVE VL 1312
2060 10:54:57.407425 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2061 10:54:57.407562 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2062 10:54:57.407762 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2063 10:54:57.407915 # ok 333 Set SVE VL 1328
2064 10:54:57.408061 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2065 10:54:57.408290 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2066 10:54:57.408476 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2067 10:54:57.408653 # ok 337 Set SVE VL 1344
2068 10:54:57.408804 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2069 10:54:57.408950 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2070 10:54:57.409094 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2071 10:54:57.409238 # ok 341 Set SVE VL 1360
2072 10:54:57.409416 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2073 10:54:57.409557 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2074 10:54:57.409713 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2075 10:54:57.416616 # ok 345 Set SVE VL 1376
2076 10:54:57.417064 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2077 10:54:57.417258 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2078 10:54:57.417403 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2079 10:54:57.417528 # ok 349 Set SVE VL 1392
2080 10:54:57.417746 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2081 10:54:57.417930 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2082 10:54:57.418071 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2083 10:54:57.418216 # ok 353 Set SVE VL 1408
2084 10:54:57.418371 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2085 10:54:57.418525 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2086 10:54:57.418711 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2087 10:54:57.418879 # ok 357 Set SVE VL 1424
2088 10:54:57.419048 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2089 10:54:57.419208 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2090 10:54:57.419360 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2091 10:54:57.419574 # ok 361 Set SVE VL 1440
2092 10:54:57.419754 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2093 10:54:57.419903 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2094 10:54:57.420082 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2095 10:54:57.420242 # ok 365 Set SVE VL 1456
2096 10:54:57.420389 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2097 10:54:57.420507 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2098 10:54:57.420621 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2099 10:54:57.420736 # ok 369 Set SVE VL 1472
2100 10:54:57.420892 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2101 10:54:57.421020 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2102 10:54:57.421133 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2103 10:54:57.421247 # ok 373 Set SVE VL 1488
2104 10:54:57.421360 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2105 10:54:57.421474 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2106 10:54:57.421596 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2107 10:54:57.421778 # ok 377 Set SVE VL 1504
2108 10:54:57.421911 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2109 10:54:57.422072 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2110 10:54:57.422224 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2111 10:54:57.424376 # ok 381 Set SVE VL 1520
2112 10:54:57.425034 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2113 10:54:57.425228 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2114 10:54:57.425467 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2115 10:54:57.425679 # ok 385 Set SVE VL 1536
2116 10:54:57.425872 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2117 10:54:57.426063 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2118 10:54:57.426273 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2119 10:54:57.426444 # ok 389 Set SVE VL 1552
2120 10:54:57.426603 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2121 10:54:57.426759 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2122 10:54:57.426914 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2123 10:54:57.427098 # ok 393 Set SVE VL 1568
2124 10:54:57.427294 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2125 10:54:57.427518 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2126 10:54:57.427692 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2127 10:54:57.427826 # ok 397 Set SVE VL 1584
2128 10:54:57.428024 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2129 10:54:57.428232 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2130 10:54:57.428434 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2131 10:54:57.428570 # ok 401 Set SVE VL 1600
2132 10:54:57.428686 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2133 10:54:57.428870 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2134 10:54:57.429009 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2135 10:54:57.429132 # ok 405 Set SVE VL 1616
2136 10:54:57.429255 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2137 10:54:57.429417 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2138 10:54:57.429573 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2139 10:54:57.430238 # ok 409 Set SVE VL 1632
2140 10:54:57.430409 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2141 10:54:57.430583 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2142 10:54:57.430706 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2143 10:54:57.430822 # ok 413 Set SVE VL 1648
2144 10:54:57.430956 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2145 10:54:57.431131 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2146 10:54:57.431256 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2147 10:54:57.431391 # ok 417 Set SVE VL 1664
2148 10:54:57.431547 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2149 10:54:57.437090 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2150 10:54:57.437520 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2151 10:54:57.437725 # ok 421 Set SVE VL 1680
2152 10:54:57.437892 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2153 10:54:57.438056 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2154 10:54:57.438251 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2155 10:54:57.438406 # ok 425 Set SVE VL 1696
2156 10:54:57.438568 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2157 10:54:57.438734 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2158 10:54:57.438939 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2159 10:54:57.439230 # ok 429 Set SVE VL 1712
2160 10:54:57.439526 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2161 10:54:57.439740 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2162 10:54:57.439943 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2163 10:54:57.440149 # ok 433 Set SVE VL 1728
2164 10:54:57.440355 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2165 10:54:57.440529 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2166 10:54:57.440679 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2167 10:54:57.440824 # ok 437 Set SVE VL 1744
2168 10:54:57.440968 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2169 10:54:57.441110 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2170 10:54:57.441255 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2171 10:54:57.441399 # ok 441 Set SVE VL 1760
2172 10:54:57.441542 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2173 10:54:57.441699 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2174 10:54:57.441846 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2175 10:54:57.441990 # ok 445 Set SVE VL 1776
2176 10:54:57.442133 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2177 10:54:57.442276 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2178 10:54:57.442499 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2179 10:54:57.442688 # ok 449 Set SVE VL 1792
2180 10:54:57.442847 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2181 10:54:57.443004 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2182 10:54:57.445453 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2183 10:54:57.445994 # ok 453 Set SVE VL 1808
2184 10:54:57.446209 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2185 10:54:57.446393 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2186 10:54:57.446557 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2187 10:54:57.446720 # ok 457 Set SVE VL 1824
2188 10:54:57.446922 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2189 10:54:57.447092 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2190 10:54:57.447251 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2191 10:54:57.447455 # ok 461 Set SVE VL 1840
2192 10:54:57.447622 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2193 10:54:57.447785 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2194 10:54:57.447940 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2195 10:54:57.448078 # ok 465 Set SVE VL 1856
2196 10:54:57.448230 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2197 10:54:57.448402 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2198 10:54:57.448525 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2199 10:54:57.448642 # ok 469 Set SVE VL 1872
2200 10:54:57.448755 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2201 10:54:57.448870 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2202 10:54:57.448983 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2203 10:54:57.449101 # ok 473 Set SVE VL 1888
2204 10:54:57.449216 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2205 10:54:57.449329 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2206 10:54:57.449443 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2207 10:54:57.449558 # ok 477 Set SVE VL 1904
2208 10:54:57.449707 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2209 10:54:57.449915 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2210 10:54:57.456399 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2211 10:54:57.456563 # ok 481 Set SVE VL 1920
2212 10:54:57.456988 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2213 10:54:57.457454 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2214 10:54:57.457669 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2215 10:54:57.457847 # ok 485 Set SVE VL 1936
2216 10:54:57.458013 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2217 10:54:57.458172 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2218 10:54:57.458356 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2219 10:54:57.458523 # ok 489 Set SVE VL 1952
2220 10:54:57.458684 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2221 10:54:57.458845 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2222 10:54:57.459008 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2223 10:54:57.459172 # ok 493 Set SVE VL 1968
2224 10:54:57.459331 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2225 10:54:57.459491 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2226 10:54:57.459692 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2227 10:54:57.459858 # ok 497 Set SVE VL 1984
2228 10:54:57.460015 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2229 10:54:57.460181 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2230 10:54:57.460362 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2231 10:54:57.460574 # ok 501 Set SVE VL 2000
2232 10:54:57.460755 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2233 10:54:57.460921 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2234 10:54:57.461087 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2235 10:54:57.461242 # ok 505 Set SVE VL 2016
2236 10:54:57.461392 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2237 10:54:57.461551 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2238 10:54:57.462408 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2239 10:54:57.462620 # ok 509 Set SVE VL 2032
2240 10:54:57.462815 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2241 10:54:57.462998 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2242 10:54:57.463178 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2243 10:54:57.463406 # ok 513 Set SVE VL 2048
2244 10:54:57.463593 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2245 10:54:57.463745 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2246 10:54:57.463864 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2247 10:54:57.463980 # ok 517 Set SVE VL 2064
2248 10:54:57.464096 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2249 10:54:57.464212 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2250 10:54:57.465488 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2251 10:54:57.465703 # ok 521 Set SVE VL 2080
2252 10:54:57.466109 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2253 10:54:57.466262 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2254 10:54:57.466390 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2255 10:54:57.466513 # ok 525 Set SVE VL 2096
2256 10:54:57.466640 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2257 10:54:57.466773 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2258 10:54:57.466927 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2259 10:54:57.467057 # ok 529 Set SVE VL 2112
2260 10:54:57.467181 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2261 10:54:57.467298 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2262 10:54:57.467444 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2263 10:54:57.467576 # ok 533 Set SVE VL 2128
2264 10:54:57.467697 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2265 10:54:57.467814 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2266 10:54:57.467928 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2267 10:54:57.468074 # ok 537 Set SVE VL 2144
2268 10:54:57.468194 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2269 10:54:57.468312 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2270 10:54:57.468438 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2271 10:54:57.468555 # ok 541 Set SVE VL 2160
2272 10:54:57.468674 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2273 10:54:57.468805 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2274 10:54:57.468934 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2275 10:54:57.469075 # ok 545 Set SVE VL 2176
2276 10:54:57.469232 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2277 10:54:57.469375 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2278 10:54:57.469526 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2279 10:54:57.469726 # ok 549 Set SVE VL 2192
2280 10:54:57.469890 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2281 10:54:57.470082 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2282 10:54:57.470201 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2283 10:54:57.470319 # ok 553 Set SVE VL 2208
2284 10:54:57.470421 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2285 10:54:57.473309 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2286 10:54:57.473436 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2287 10:54:57.473542 # ok 557 Set SVE VL 2224
2288 10:54:57.473667 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2289 10:54:57.473808 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2290 10:54:57.473919 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2291 10:54:57.474051 # ok 561 Set SVE VL 2240
2292 10:54:57.474158 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2293 10:54:57.474227 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2294 10:54:57.474309 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2295 10:54:57.474410 # ok 565 Set SVE VL 2256
2296 10:54:57.474497 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2297 10:54:57.474593 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2298 10:54:57.474698 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2299 10:54:57.474794 # ok 569 Set SVE VL 2272
2300 10:54:57.474933 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2301 10:54:57.475043 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2302 10:54:57.475150 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2303 10:54:57.475239 # ok 573 Set SVE VL 2288
2304 10:54:57.475325 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2305 10:54:57.475456 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2306 10:54:57.475564 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2307 10:54:57.475650 # ok 577 Set SVE VL 2304
2308 10:54:57.475729 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2309 10:54:57.475818 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2310 10:54:57.475927 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2311 10:54:57.476021 # ok 581 Set SVE VL 2320
2312 10:54:57.476109 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2313 10:54:57.476215 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2314 10:54:57.476342 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2315 10:54:57.476445 # ok 585 Set SVE VL 2336
2316 10:54:57.476542 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2317 10:54:57.476653 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2318 10:54:57.476760 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2319 10:54:57.481377 # ok 589 Set SVE VL 2352
2320 10:54:57.481635 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2321 10:54:57.481753 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2322 10:54:57.481863 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2323 10:54:57.481975 # ok 593 Set SVE VL 2368
2324 10:54:57.482286 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2325 10:54:57.482422 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2326 10:54:57.482511 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2327 10:54:57.482595 # ok 597 Set SVE VL 2384
2328 10:54:57.482675 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2329 10:54:57.482775 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2330 10:54:57.482869 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2331 10:54:57.482951 # ok 601 Set SVE VL 2400
2332 10:54:57.483032 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2333 10:54:57.483115 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2334 10:54:57.483195 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2335 10:54:57.483275 # ok 605 Set SVE VL 2416
2336 10:54:57.483390 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2337 10:54:57.483495 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2338 10:54:57.483593 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2339 10:54:57.483688 # ok 609 Set SVE VL 2432
2340 10:54:57.483777 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2341 10:54:57.483866 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2342 10:54:57.483941 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2343 10:54:57.484037 # ok 613 Set SVE VL 2448
2344 10:54:57.484147 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2345 10:54:57.484260 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2346 10:54:57.484358 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2347 10:54:57.484448 # ok 617 Set SVE VL 2464
2348 10:54:57.484523 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2349 10:54:57.484586 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2350 10:54:57.484664 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2351 10:54:57.484749 # ok 621 Set SVE VL 2480
2352 10:54:57.484820 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2353 10:54:57.484888 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2354 10:54:57.484952 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2355 10:54:57.485013 # ok 625 Set SVE VL 2496
2356 10:54:57.485074 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2357 10:54:57.485135 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2358 10:54:57.485203 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2359 10:54:57.485295 # ok 629 Set SVE VL 2512
2360 10:54:57.485371 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2361 10:54:57.485446 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2362 10:54:57.489142 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2363 10:54:57.489461 # ok 633 Set SVE VL 2528
2364 10:54:57.489568 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2365 10:54:57.489685 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2366 10:54:57.489792 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2367 10:54:57.489882 # ok 637 Set SVE VL 2544
2368 10:54:57.489969 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2369 10:54:57.490071 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2370 10:54:57.490161 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2371 10:54:57.490247 # ok 641 Set SVE VL 2560
2372 10:54:57.490349 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2373 10:54:57.490438 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2374 10:54:57.490539 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2375 10:54:57.490628 # ok 645 Set SVE VL 2576
2376 10:54:57.490725 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2377 10:54:57.490819 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2378 10:54:57.490912 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2379 10:54:57.491005 # ok 649 Set SVE VL 2592
2380 10:54:57.491104 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2381 10:54:57.491208 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2382 10:54:57.491308 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2383 10:54:57.491409 # ok 653 Set SVE VL 2608
2384 10:54:57.491514 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2385 10:54:57.491617 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2386 10:54:57.492107 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2387 10:54:57.492223 # ok 657 Set SVE VL 2624
2388 10:54:57.492313 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2389 10:54:57.492413 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2390 10:54:57.492498 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2391 10:54:57.496685 # ok 661 Set SVE VL 2640
2392 10:54:57.496989 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2393 10:54:57.497086 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2394 10:54:57.497193 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2395 10:54:57.497279 # ok 665 Set SVE VL 2656
2396 10:54:57.497371 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2397 10:54:57.521085 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2398 10:54:57.521194 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2399 10:54:57.521283 # ok 669 Set SVE VL 2672
2400 10:54:57.521378 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2401 10:54:57.521463 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2402 10:54:57.521557 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2403 10:54:57.521641 # ok 673 Set SVE VL 2688
2404 10:54:57.521765 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2405 10:54:57.521849 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2406 10:54:57.521943 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2407 10:54:57.522026 # ok 677 Set SVE VL 2704
2408 10:54:57.522120 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2409 10:54:57.522216 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2410 10:54:57.522313 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2411 10:54:57.522395 # ok 681 Set SVE VL 2720
2412 10:54:57.522489 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2413 10:54:57.522586 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2414 10:54:57.522882 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2415 10:54:57.523104 # ok 685 Set SVE VL 2736
2416 10:54:57.523276 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2417 10:54:57.523542 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2418 10:54:57.523761 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2419 10:54:57.523939 # ok 689 Set SVE VL 2752
2420 10:54:57.524102 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2421 10:54:57.524249 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2422 10:54:57.524432 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2423 10:54:57.524600 # ok 693 Set SVE VL 2768
2424 10:54:57.524767 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2425 10:54:57.524931 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2426 10:54:57.525099 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2427 10:54:57.525260 # ok 697 Set SVE VL 2784
2428 10:54:57.525404 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2429 10:54:57.525540 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2430 10:54:57.525724 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2431 10:54:57.525894 # ok 701 Set SVE VL 2800
2432 10:54:57.526056 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2433 10:54:57.526224 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2434 10:54:57.526424 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2435 10:54:57.526608 # ok 705 Set SVE VL 2816
2436 10:54:57.526778 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2437 10:54:57.526942 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2438 10:54:57.527107 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2439 10:54:57.527310 # ok 709 Set SVE VL 2832
2440 10:54:57.527489 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2441 10:54:57.527655 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2442 10:54:57.527847 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2443 10:54:57.528050 # ok 713 Set SVE VL 2848
2444 10:54:57.528256 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2445 10:54:57.528432 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2446 10:54:57.528603 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2447 10:54:57.528764 # ok 717 Set SVE VL 2864
2448 10:54:57.528921 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2449 10:54:57.529076 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2450 10:54:57.529257 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2451 10:54:57.529544 # ok 721 Set SVE VL 2880
2452 10:54:57.530889 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2453 10:54:57.531088 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2454 10:54:57.531306 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2455 10:54:57.531502 # ok 725 Set SVE VL 2896
2456 10:54:57.531670 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2457 10:54:57.531826 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2458 10:54:57.532284 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2459 10:54:57.532485 # ok 729 Set SVE VL 2912
2460 10:54:57.532656 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2461 10:54:57.532869 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2462 10:54:57.533045 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2463 10:54:57.533169 # ok 733 Set SVE VL 2928
2464 10:54:57.533325 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2465 10:54:57.533488 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2466 10:54:57.533661 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2467 10:54:57.533824 # ok 737 Set SVE VL 2944
2468 10:54:57.533981 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2469 10:54:57.534128 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2470 10:54:57.534282 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2471 10:54:57.534435 # ok 741 Set SVE VL 2960
2472 10:54:57.534579 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2473 10:54:57.534731 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2474 10:54:57.534880 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2475 10:54:57.535038 # ok 745 Set SVE VL 2976
2476 10:54:57.535203 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2477 10:54:57.535360 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2478 10:54:57.535509 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2479 10:54:57.535663 # ok 749 Set SVE VL 2992
2480 10:54:57.535815 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2481 10:54:57.535965 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2482 10:54:57.536120 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2483 10:54:57.536275 # ok 753 Set SVE VL 3008
2484 10:54:57.536429 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2485 10:54:57.536580 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2486 10:54:57.536717 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2487 10:54:57.536872 # ok 757 Set SVE VL 3024
2488 10:54:57.537040 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2489 10:54:57.537210 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2490 10:54:57.537378 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2491 10:54:57.537543 # ok 761 Set SVE VL 3040
2492 10:54:57.538576 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2493 10:54:57.538770 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2494 10:54:57.538983 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2495 10:54:57.539133 # ok 765 Set SVE VL 3056
2496 10:54:57.539284 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2497 10:54:57.539448 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2498 10:54:57.539589 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2499 10:54:57.539712 # ok 769 Set SVE VL 3072
2500 10:54:57.539858 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2501 10:54:57.540021 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2502 10:54:57.540438 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2503 10:54:57.540646 # ok 773 Set SVE VL 3088
2504 10:54:57.540852 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2505 10:54:57.541064 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2506 10:54:57.541237 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2507 10:54:57.541364 # ok 777 Set SVE VL 3104
2508 10:54:57.541477 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2509 10:54:57.541567 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2510 10:54:57.541664 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2511 10:54:57.541754 # ok 781 Set SVE VL 3120
2512 10:54:57.541840 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2513 10:54:57.541929 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2514 10:54:57.542018 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2515 10:54:57.542107 # ok 785 Set SVE VL 3136
2516 10:54:57.542196 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2517 10:54:57.542289 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2518 10:54:57.542377 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2519 10:54:57.542465 # ok 789 Set SVE VL 3152
2520 10:54:57.542554 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2521 10:54:57.542642 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2522 10:54:57.542730 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2523 10:54:57.542818 # ok 793 Set SVE VL 3168
2524 10:54:57.542906 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2525 10:54:57.542996 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2526 10:54:57.543085 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2527 10:54:57.543173 # ok 797 Set SVE VL 3184
2528 10:54:57.543261 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2529 10:54:57.543349 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2530 10:54:57.543438 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2531 10:54:57.543527 # ok 801 Set SVE VL 3200
2532 10:54:57.543616 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2533 10:54:57.543722 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2534 10:54:57.543813 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2535 10:54:57.543902 # ok 805 Set SVE VL 3216
2536 10:54:57.543991 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2537 10:54:57.544080 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2538 10:54:57.544169 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2539 10:54:57.544258 # ok 809 Set SVE VL 3232
2540 10:54:57.544346 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2541 10:54:57.544435 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2542 10:54:57.544524 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2543 10:54:57.544613 # ok 813 Set SVE VL 3248
2544 10:54:57.544702 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2545 10:54:57.544789 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2546 10:54:57.545086 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2547 10:54:57.545187 # ok 817 Set SVE VL 3264
2548 10:54:57.545278 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2549 10:54:57.545367 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2550 10:54:57.545456 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2551 10:54:57.545544 # ok 821 Set SVE VL 3280
2552 10:54:57.545633 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2553 10:54:57.545733 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2554 10:54:57.545824 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2555 10:54:57.545913 # ok 825 Set SVE VL 3296
2556 10:54:57.546001 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2557 10:54:57.546090 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2558 10:54:57.546179 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2559 10:54:57.546273 # ok 829 Set SVE VL 3312
2560 10:54:57.546361 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2561 10:54:57.546450 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2562 10:54:57.546538 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2563 10:54:57.546626 # ok 833 Set SVE VL 3328
2564 10:54:57.546715 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2565 10:54:57.546803 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2566 10:54:57.546892 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2567 10:54:57.546981 # ok 837 Set SVE VL 3344
2568 10:54:57.547069 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2569 10:54:57.547158 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2570 10:54:57.547248 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2571 10:54:57.547336 # ok 841 Set SVE VL 3360
2572 10:54:57.547430 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2573 10:54:57.547566 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2574 10:54:57.547730 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2575 10:54:57.547862 # ok 845 Set SVE VL 3376
2576 10:54:57.547985 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2577 10:54:57.548108 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2578 10:54:57.548230 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2579 10:54:57.548355 # ok 849 Set SVE VL 3392
2580 10:54:57.548462 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2581 10:54:57.548552 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2582 10:54:57.548641 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2583 10:54:57.548789 # ok 853 Set SVE VL 3408
2584 10:54:57.548941 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2585 10:54:57.549126 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2586 10:54:57.549297 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2587 10:54:57.549437 # ok 857 Set SVE VL 3424
2588 10:54:57.549563 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2589 10:54:57.549947 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2590 10:54:57.550176 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2591 10:54:57.550355 # ok 861 Set SVE VL 3440
2592 10:54:57.550527 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2593 10:54:57.550698 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2594 10:54:57.550866 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2595 10:54:57.551022 # ok 865 Set SVE VL 3456
2596 10:54:57.551179 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2597 10:54:57.551338 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2598 10:54:57.551521 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2599 10:54:57.551698 # ok 869 Set SVE VL 3472
2600 10:54:57.551862 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2601 10:54:57.552026 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2602 10:54:57.552191 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2603 10:54:57.552363 # ok 873 Set SVE VL 3488
2604 10:54:57.552529 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2605 10:54:57.552694 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2606 10:54:57.552905 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2607 10:54:57.553082 # ok 877 Set SVE VL 3504
2608 10:54:57.553243 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2609 10:54:57.553404 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2610 10:54:57.553561 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2611 10:54:57.553767 # ok 881 Set SVE VL 3520
2612 10:54:57.553997 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2613 10:54:57.554212 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2614 10:54:57.554389 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2615 10:54:57.554559 # ok 885 Set SVE VL 3536
2616 10:54:57.554722 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2617 10:54:57.554880 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2618 10:54:57.555051 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2619 10:54:57.555210 # ok 889 Set SVE VL 3552
2620 10:54:57.555372 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2621 10:54:57.555522 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2622 10:54:57.555672 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2623 10:54:57.555817 # ok 893 Set SVE VL 3568
2624 10:54:57.555940 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2625 10:54:57.556077 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2626 10:54:57.556214 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2627 10:54:57.556372 # ok 897 Set SVE VL 3584
2628 10:54:57.556525 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2629 10:54:57.556695 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2630 10:54:57.556874 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2631 10:54:57.557038 # ok 901 Set SVE VL 3600
2632 10:54:57.557239 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2633 10:54:57.557614 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2634 10:54:57.557711 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2635 10:54:57.557775 # ok 905 Set SVE VL 3616
2636 10:54:57.557835 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2637 10:54:57.557895 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2638 10:54:57.557954 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2639 10:54:57.558024 # ok 909 Set SVE VL 3632
2640 10:54:57.558101 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2641 10:54:57.558176 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2642 10:54:57.558249 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2643 10:54:57.558342 # ok 913 Set SVE VL 3648
2644 10:54:57.558443 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2645 10:54:57.558537 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2646 10:54:57.558628 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2647 10:54:57.558700 # ok 917 Set SVE VL 3664
2648 10:54:57.558781 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2649 10:54:57.558845 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2650 10:54:57.558906 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2651 10:54:57.558999 # ok 921 Set SVE VL 3680
2652 10:54:57.559091 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2653 10:54:57.559171 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2654 10:54:57.559271 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2655 10:54:57.559352 # ok 925 Set SVE VL 3696
2656 10:54:57.559426 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2657 10:54:57.559515 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2658 10:54:57.559600 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2659 10:54:57.559679 # ok 929 Set SVE VL 3712
2660 10:54:57.559756 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2661 10:54:57.559828 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2662 10:54:57.559905 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2663 10:54:57.559980 # ok 933 Set SVE VL 3728
2664 10:54:57.560056 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2665 10:54:57.560133 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2666 10:54:57.560206 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2667 10:54:57.560302 # ok 937 Set SVE VL 3744
2668 10:54:57.560387 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2669 10:54:57.560455 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2670 10:54:57.560530 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2671 10:54:57.560635 # ok 941 Set SVE VL 3760
2672 10:54:57.560727 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2673 10:54:57.560819 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2674 10:54:57.560911 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2675 10:54:57.561003 # ok 945 Set SVE VL 3776
2676 10:54:57.561086 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2677 10:54:57.561354 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2678 10:54:57.561430 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2679 10:54:57.561503 # ok 949 Set SVE VL 3792
2680 10:54:57.561577 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2681 10:54:57.561660 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2682 10:54:57.561729 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2683 10:54:57.561801 # ok 953 Set SVE VL 3808
2684 10:54:57.561905 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2685 10:54:57.562004 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2686 10:54:57.562082 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2687 10:54:57.562155 # ok 957 Set SVE VL 3824
2688 10:54:57.562226 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2689 10:54:57.562305 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2690 10:54:57.562381 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2691 10:54:57.562457 # ok 961 Set SVE VL 3840
2692 10:54:57.562548 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2693 10:54:57.562638 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2694 10:54:57.562729 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2695 10:54:57.562805 # ok 965 Set SVE VL 3856
2696 10:54:57.562879 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2697 10:54:57.562956 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2698 10:54:57.563033 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2699 10:54:57.563108 # ok 969 Set SVE VL 3872
2700 10:54:57.563186 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2701 10:54:57.563261 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2702 10:54:57.563337 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2703 10:54:57.563413 # ok 973 Set SVE VL 3888
2704 10:54:57.563489 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2705 10:54:57.563580 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2706 10:54:57.563671 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2707 10:54:57.563772 # ok 977 Set SVE VL 3904
2708 10:54:57.563874 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2709 10:54:57.563971 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2710 10:54:57.564053 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2711 10:54:57.564132 # ok 981 Set SVE VL 3920
2712 10:54:57.564221 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2713 10:54:57.564318 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2714 10:54:57.564394 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2715 10:54:57.564459 # ok 985 Set SVE VL 3936
2716 10:54:57.564519 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2717 10:54:57.564632 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2718 10:54:57.564721 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2719 10:54:57.564800 # ok 989 Set SVE VL 3952
2720 10:54:57.564890 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2721 10:54:57.565193 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2722 10:54:57.565303 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2723 10:54:57.565391 # ok 993 Set SVE VL 3968
2724 10:54:57.565468 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2725 10:54:57.565566 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2726 10:54:57.565654 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2727 10:54:57.565733 # ok 997 Set SVE VL 3984
2728 10:54:57.565812 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2729 10:54:57.565889 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2730 10:54:57.565973 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2731 10:54:57.566055 # ok 1001 Set SVE VL 4000
2732 10:54:57.566136 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2733 10:54:57.566216 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2734 10:54:57.566297 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2735 10:54:57.566357 # ok 1005 Set SVE VL 4016
2736 10:54:57.566422 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2737 10:54:57.566494 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2738 10:54:57.566560 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2739 10:54:57.566663 # ok 1009 Set SVE VL 4032
2740 10:54:57.566743 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2741 10:54:57.566836 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2742 10:54:57.566941 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2743 10:54:57.567045 # ok 1013 Set SVE VL 4048
2744 10:54:57.567141 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2745 10:54:57.567226 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2746 10:54:57.567325 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2747 10:54:57.567408 # ok 1017 Set SVE VL 4064
2748 10:54:57.567486 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2749 10:54:57.567566 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2750 10:54:57.567645 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2751 10:54:57.567724 # ok 1021 Set SVE VL 4080
2752 10:54:57.567805 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2753 10:54:57.567883 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2754 10:54:57.567959 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2755 10:54:57.568035 # ok 1025 Set SVE VL 4096
2756 10:54:57.568112 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2757 10:54:57.568191 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2758 10:54:57.568270 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2759 10:54:57.568347 # ok 1029 Set SVE VL 4112
2760 10:54:57.573747 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2761 10:54:57.573870 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2762 10:54:57.573964 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2763 10:54:57.574052 # ok 1033 Set SVE VL 4128
2764 10:54:57.574141 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2765 10:54:57.574228 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2766 10:54:57.574322 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2767 10:54:57.574410 # ok 1037 Set SVE VL 4144
2768 10:54:57.574498 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2769 10:54:57.574586 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2770 10:54:57.574674 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2771 10:54:57.576250 # ok 1041 Set SVE VL 4160
2772 10:54:57.576359 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2773 10:54:57.576468 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2774 10:54:57.577542 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2775 10:54:57.577657 # ok 1045 Set SVE VL 4176
2776 10:54:57.577954 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2777 10:54:57.578057 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2778 10:54:57.578163 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2779 10:54:57.578252 # ok 1049 Set SVE VL 4192
2780 10:54:57.578343 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2781 10:54:57.578444 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2782 10:54:57.578546 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2783 10:54:57.578635 # ok 1053 Set SVE VL 4208
2784 10:54:57.578734 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2785 10:54:57.579057 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2786 10:54:57.579164 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2787 10:54:57.579247 # ok 1057 Set SVE VL 4224
2788 10:54:57.579339 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2789 10:54:57.579421 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2790 10:54:57.579512 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2791 10:54:57.579593 # ok 1061 Set SVE VL 4240
2792 10:54:57.579684 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2793 10:54:57.579777 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2794 10:54:57.579857 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2795 10:54:57.580152 # ok 1065 Set SVE VL 4256
2796 10:54:57.580257 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2797 10:54:57.580345 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2798 10:54:57.580429 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2799 10:54:57.580502 # ok 1069 Set SVE VL 4272
2800 10:54:57.580596 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2801 10:54:57.580723 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2802 10:54:57.580844 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2803 10:54:57.580976 # ok 1073 Set SVE VL 4288
2804 10:54:57.581089 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2805 10:54:57.581208 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2806 10:54:57.581307 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2807 10:54:57.581417 # ok 1077 Set SVE VL 4304
2808 10:54:57.581507 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2809 10:54:57.581597 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2810 10:54:57.581715 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2811 10:54:57.581817 # ok 1081 Set SVE VL 4320
2812 10:54:57.581912 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2813 10:54:57.582010 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2814 10:54:57.582092 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2815 10:54:57.582172 # ok 1085 Set SVE VL 4336
2816 10:54:57.582251 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2817 10:54:57.582348 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2818 10:54:57.582441 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2819 10:54:57.582522 # ok 1089 Set SVE VL 4352
2820 10:54:57.582601 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2821 10:54:57.582693 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2822 10:54:57.582773 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2823 10:54:57.582852 # ok 1093 Set SVE VL 4368
2824 10:54:57.582943 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2825 10:54:57.583024 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2826 10:54:57.583115 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2827 10:54:57.583208 # ok 1097 Set SVE VL 4384
2828 10:54:57.583305 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2829 10:54:57.583386 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2830 10:54:57.583477 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2831 10:54:57.583559 # ok 1101 Set SVE VL 4400
2832 10:54:57.583649 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2833 10:54:57.583730 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2834 10:54:57.583821 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2835 10:54:57.583913 # ok 1105 Set SVE VL 4416
2836 10:54:57.584004 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2837 10:54:57.584381 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2838 10:54:57.584509 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2839 10:54:57.584597 # ok 1109 Set SVE VL 4432
2840 10:54:57.584890 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2841 10:54:57.585044 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2842 10:54:57.585194 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2843 10:54:57.585310 # ok 1113 Set SVE VL 4448
2844 10:54:57.585394 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2845 10:54:57.585473 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2846 10:54:57.585566 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2847 10:54:57.585654 # ok 1117 Set SVE VL 4464
2848 10:54:57.585735 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2849 10:54:57.585826 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2850 10:54:57.585920 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2851 10:54:57.586000 # ok 1121 Set SVE VL 4480
2852 10:54:57.586090 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2853 10:54:57.586418 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2854 10:54:57.586520 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2855 10:54:57.586816 # ok 1125 Set SVE VL 4496
2856 10:54:57.586916 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2857 10:54:57.586997 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2858 10:54:57.587089 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2859 10:54:57.587169 # ok 1129 Set SVE VL 4512
2860 10:54:57.587248 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2861 10:54:57.587339 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2862 10:54:57.587432 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2863 10:54:57.587513 # ok 1133 Set SVE VL 4528
2864 10:54:57.587792 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2865 10:54:57.587892 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2866 10:54:57.587985 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2867 10:54:57.588066 # ok 1137 Set SVE VL 4544
2868 10:54:57.588157 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2869 10:54:57.588257 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2870 10:54:57.588556 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2871 10:54:57.588658 # ok 1141 Set SVE VL 4560
2872 10:54:57.588752 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2873 10:54:57.588832 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2874 10:54:57.588925 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2875 10:54:57.589006 # ok 1145 Set SVE VL 4576
2876 10:54:57.589097 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2877 10:54:57.589178 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2878 10:54:57.589270 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2879 10:54:57.589350 # ok 1149 Set SVE VL 4592
2880 10:54:57.589429 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2881 10:54:57.589520 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2882 10:54:57.589600 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2883 10:54:57.589689 # ok 1153 Set SVE VL 4608
2884 10:54:57.589781 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2885 10:54:57.589861 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2886 10:54:57.589953 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2887 10:54:57.590034 # ok 1157 Set SVE VL 4624
2888 10:54:57.590111 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2889 10:54:57.590208 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2890 10:54:57.590293 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2891 10:54:57.590387 # ok 1161 Set SVE VL 4640
2892 10:54:57.590468 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2893 10:54:57.590546 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2894 10:54:57.590638 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2895 10:54:57.590719 # ok 1165 Set SVE VL 4656
2896 10:54:57.590797 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2897 10:54:57.590889 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2898 10:54:57.590969 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2899 10:54:57.591047 # ok 1169 Set SVE VL 4672
2900 10:54:57.591138 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2901 10:54:57.591219 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2902 10:54:57.591297 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2903 10:54:57.591389 # ok 1173 Set SVE VL 4688
2904 10:54:57.591469 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2905 10:54:57.591547 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2906 10:54:57.591625 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2907 10:54:57.591717 # ok 1177 Set SVE VL 4704
2908 10:54:57.591797 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2909 10:54:57.591875 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2910 10:54:57.591967 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2911 10:54:57.592048 # ok 1181 Set SVE VL 4720
2912 10:54:57.592127 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2913 10:54:57.592514 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2914 10:54:57.592622 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2915 10:54:57.592716 # ok 1185 Set SVE VL 4736
2916 10:54:57.593003 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2917 10:54:57.593118 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2918 10:54:57.593201 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2919 10:54:57.593280 # ok 1189 Set SVE VL 4752
2920 10:54:57.593371 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2921 10:54:57.593669 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2922 10:54:57.593771 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2923 10:54:57.593851 # ok 1193 Set SVE VL 4768
2924 10:54:57.593944 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2925 10:54:57.594024 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2926 10:54:57.594103 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2927 10:54:57.594195 # ok 1197 Set SVE VL 4784
2928 10:54:57.594275 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2929 10:54:57.594358 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2930 10:54:57.594449 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2931 10:54:57.594529 # ok 1201 Set SVE VL 4800
2932 10:54:57.594620 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2933 10:54:57.594701 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2934 10:54:57.594779 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2935 10:54:57.594857 # ok 1205 Set SVE VL 4816
2936 10:54:57.594950 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2937 10:54:57.595030 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2938 10:54:57.595109 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2939 10:54:57.595188 # ok 1209 Set SVE VL 4832
2940 10:54:57.595280 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2941 10:54:57.595362 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2942 10:54:57.595441 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2943 10:54:57.595519 # ok 1213 Set SVE VL 4848
2944 10:54:57.595612 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2945 10:54:57.595693 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2946 10:54:57.595773 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2947 10:54:57.595851 # ok 1217 Set SVE VL 4864
2948 10:54:57.595930 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2949 10:54:57.596008 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2950 10:54:57.596100 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2951 10:54:57.596181 # ok 1221 Set SVE VL 4880
2952 10:54:57.596259 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2953 10:54:57.596337 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2954 10:54:57.607109 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2955 10:54:57.607208 # ok 1225 Set SVE VL 4896
2956 10:54:57.607301 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2957 10:54:57.607404 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2958 10:54:57.607744 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2959 10:54:57.607943 # ok 1229 Set SVE VL 4912
2960 10:54:57.608144 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2961 10:54:57.608315 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2962 10:54:57.608481 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2963 10:54:57.608647 # ok 1233 Set SVE VL 4928
2964 10:54:57.608876 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2965 10:54:57.609055 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2966 10:54:57.609226 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2967 10:54:57.609368 # ok 1237 Set SVE VL 4944
2968 10:54:57.609509 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2969 10:54:57.609694 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2970 10:54:57.609949 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2971 10:54:57.610155 # ok 1241 Set SVE VL 4960
2972 10:54:57.610331 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2973 10:54:57.610443 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2974 10:54:57.610561 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2975 10:54:57.610675 # ok 1245 Set SVE VL 4976
2976 10:54:57.610791 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2977 10:54:57.610913 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2978 10:54:57.611031 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2979 10:54:57.611151 # ok 1249 Set SVE VL 4992
2980 10:54:57.611296 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2981 10:54:57.611425 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2982 10:54:57.613850 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2983 10:54:57.614051 # ok 1253 Set SVE VL 5008
2984 10:54:57.614258 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2985 10:54:57.614434 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2986 10:54:57.614576 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2987 10:54:57.614717 # ok 1257 Set SVE VL 5024
2988 10:54:57.614868 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2989 10:54:57.615011 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2990 10:54:57.615173 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2991 10:54:57.615302 # ok 1261 Set SVE VL 5040
2992 10:54:57.615400 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2993 10:54:57.615510 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2994 10:54:57.615604 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2995 10:54:57.615693 # ok 1265 Set SVE VL 5056
2996 10:54:57.616712 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2997 10:54:57.617046 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2998 10:54:57.617136 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2999 10:54:57.617217 # ok 1269 Set SVE VL 5072
3000 10:54:57.617319 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
3001 10:54:57.617431 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
3002 10:54:57.617541 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3003 10:54:57.617632 # ok 1273 Set SVE VL 5088
3004 10:54:57.617732 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3005 10:54:57.617830 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3006 10:54:57.617918 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3007 10:54:57.618024 # ok 1277 Set SVE VL 5104
3008 10:54:57.618307 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3009 10:54:57.618412 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3010 10:54:57.618514 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3011 10:54:57.618600 # ok 1281 Set SVE VL 5120
3012 10:54:57.618693 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3013 10:54:57.618789 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3014 10:54:57.619097 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3015 10:54:57.619199 # ok 1285 Set SVE VL 5136
3016 10:54:57.619304 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3017 10:54:57.619421 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3018 10:54:57.619510 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3019 10:54:57.619608 # ok 1289 Set SVE VL 5152
3020 10:54:57.619682 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3021 10:54:57.619804 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3022 10:54:57.619887 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3023 10:54:57.619986 # ok 1293 Set SVE VL 5168
3024 10:54:57.620082 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3025 10:54:57.620181 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3026 10:54:57.621269 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3027 10:54:57.621561 # ok 1297 Set SVE VL 5184
3028 10:54:57.621682 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3029 10:54:57.621806 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3030 10:54:57.621907 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3031 10:54:57.622004 # ok 1301 Set SVE VL 5200
3032 10:54:57.622094 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3033 10:54:57.622178 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3034 10:54:57.622275 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3035 10:54:57.622363 # ok 1305 Set SVE VL 5216
3036 10:54:57.622445 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3037 10:54:57.622546 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3038 10:54:57.622646 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3039 10:54:57.622740 # ok 1309 Set SVE VL 5232
3040 10:54:57.622837 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3041 10:54:57.622936 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3042 10:54:57.623040 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3043 10:54:57.623141 # ok 1313 Set SVE VL 5248
3044 10:54:57.623234 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3045 10:54:57.623600 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3046 10:54:57.623806 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3047 10:54:57.624031 # ok 1317 Set SVE VL 5264
3048 10:54:57.624214 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3049 10:54:57.624402 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3050 10:54:57.624530 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3051 10:54:57.624646 # ok 1321 Set SVE VL 5280
3052 10:54:57.624759 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3053 10:54:57.625325 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3054 10:54:57.625657 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3055 10:54:57.625754 # ok 1325 Set SVE VL 5296
3056 10:54:57.625890 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3057 10:54:57.626035 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3058 10:54:57.626124 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3059 10:54:57.626228 # ok 1329 Set SVE VL 5312
3060 10:54:57.626358 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3061 10:54:57.626454 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3062 10:54:57.626556 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3063 10:54:57.626634 # ok 1333 Set SVE VL 5328
3064 10:54:57.626719 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3065 10:54:57.626814 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3066 10:54:57.626902 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3067 10:54:57.626972 # ok 1337 Set SVE VL 5344
3068 10:54:57.627061 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3069 10:54:57.627764 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3070 10:54:57.627971 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3071 10:54:57.628150 # ok 1341 Set SVE VL 5360
3072 10:54:57.628328 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3073 10:54:57.628485 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3074 10:54:57.628647 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3075 10:54:57.628841 # ok 1345 Set SVE VL 5376
3076 10:54:57.629018 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3077 10:54:57.629197 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3078 10:54:57.629381 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3079 10:54:57.629504 # ok 1349 Set SVE VL 5392
3080 10:54:57.629615 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3081 10:54:57.629749 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3082 10:54:57.629873 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3083 10:54:57.630024 # ok 1353 Set SVE VL 5408
3084 10:54:57.630158 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3085 10:54:57.630284 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3086 10:54:57.630396 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3087 10:54:57.630475 # ok 1357 Set SVE VL 5424
3088 10:54:57.630557 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3089 10:54:57.630647 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3090 10:54:57.630727 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3091 10:54:57.630842 # ok 1361 Set SVE VL 5440
3092 10:54:57.630951 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3093 10:54:57.631084 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3094 10:54:57.631193 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3095 10:54:57.631303 # ok 1365 Set SVE VL 5456
3096 10:54:57.631420 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3097 10:54:57.631537 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3098 10:54:57.631642 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3099 10:54:57.631725 # ok 1369 Set SVE VL 5472
3100 10:54:57.631810 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3101 10:54:57.631913 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3102 10:54:57.631997 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3103 10:54:57.632097 # ok 1373 Set SVE VL 5488
3104 10:54:57.632190 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3105 10:54:57.632279 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3106 10:54:57.632361 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3107 10:54:57.632484 # ok 1377 Set SVE VL 5504
3108 10:54:57.632599 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3109 10:54:57.632699 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3110 10:54:57.632832 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3111 10:54:57.632937 # ok 1381 Set SVE VL 5520
3112 10:54:57.633951 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3113 10:54:57.634064 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3114 10:54:57.634178 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3115 10:54:57.634279 # ok 1385 Set SVE VL 5536
3116 10:54:57.634373 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3117 10:54:57.634478 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3118 10:54:57.634597 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3119 10:54:57.634699 # ok 1389 Set SVE VL 5552
3120 10:54:57.634784 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3121 10:54:57.634872 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3122 10:54:57.634975 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3123 10:54:57.635050 # ok 1393 Set SVE VL 5568
3124 10:54:57.635127 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3125 10:54:57.635209 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3126 10:54:57.635316 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3127 10:54:57.635406 # ok 1397 Set SVE VL 5584
3128 10:54:57.635469 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3129 10:54:57.635530 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3130 10:54:57.635589 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3131 10:54:57.635649 # ok 1401 Set SVE VL 5600
3132 10:54:57.635707 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3133 10:54:57.635766 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3134 10:54:57.635825 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3135 10:54:57.635885 # ok 1405 Set SVE VL 5616
3136 10:54:57.635943 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3137 10:54:57.643340 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3138 10:54:57.643445 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3139 10:54:57.643770 # ok 1409 Set SVE VL 5632
3140 10:54:57.643891 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3141 10:54:57.643986 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3142 10:54:57.644091 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3143 10:54:57.644198 # ok 1413 Set SVE VL 5648
3144 10:54:57.644302 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3145 10:54:57.644389 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3146 10:54:57.644475 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3147 10:54:57.644540 # ok 1417 Set SVE VL 5664
3148 10:54:57.681699 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3149 10:54:57.682118 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3150 10:54:57.682292 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3151 10:54:57.682422 # ok 1421 Set SVE VL 5680
3152 10:54:57.682584 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3153 10:54:57.682721 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3154 10:54:57.683086 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3155 10:54:57.683249 # ok 1425 Set SVE VL 5696
3156 10:54:57.683381 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3157 10:54:57.683534 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3158 10:54:57.683673 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3159 10:54:57.683825 # ok 1429 Set SVE VL 5712
3160 10:54:57.683978 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3161 10:54:57.684181 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3162 10:54:57.684377 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3163 10:54:57.684545 # ok 1433 Set SVE VL 5728
3164 10:54:57.684690 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3165 10:54:57.684829 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3166 10:54:57.684968 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3167 10:54:57.685107 # ok 1437 Set SVE VL 5744
3168 10:54:57.685245 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3169 10:54:57.685382 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3170 10:54:57.685522 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3171 10:54:57.685710 # ok 1441 Set SVE VL 5760
3172 10:54:57.687525 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3173 10:54:57.687959 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3174 10:54:57.688154 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3175 10:54:57.688308 # ok 1445 Set SVE VL 5776
3176 10:54:57.688429 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3177 10:54:57.688595 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3178 10:54:57.688765 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3179 10:54:57.702093 # ok 1449 Set SVE VL 5792
3180 10:54:57.702476 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3181 10:54:57.702649 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3182 10:54:57.702827 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3183 10:54:57.702986 # ok 1453 Set SVE VL 5808
3184 10:54:57.703163 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3185 10:54:57.703320 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3186 10:54:57.703731 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3187 10:54:57.703979 # ok 1457 Set SVE VL 5824
3188 10:54:57.704261 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3189 10:54:57.704463 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3190 10:54:57.704644 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3191 10:54:57.704818 # ok 1461 Set SVE VL 5840
3192 10:54:57.704988 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3193 10:54:57.705147 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3194 10:54:57.705340 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3195 10:54:57.705515 # ok 1465 Set SVE VL 5856
3196 10:54:57.705733 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3197 10:54:57.705899 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3198 10:54:57.717701 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3199 10:54:57.717864 # ok 1469 Set SVE VL 5872
3200 10:54:57.717986 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3201 10:54:57.718102 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3202 10:54:57.718419 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3203 10:54:57.718542 # ok 1473 Set SVE VL 5888
3204 10:54:57.718840 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3205 10:54:57.718947 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3206 10:54:57.719047 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3207 10:54:57.719132 # ok 1477 Set SVE VL 5904
3208 10:54:57.719226 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3209 10:54:57.719320 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3210 10:54:57.719607 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3211 10:54:57.719712 # ok 1481 Set SVE VL 5920
3212 10:54:57.719812 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3213 10:54:57.720142 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3214 10:54:57.720305 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3215 10:54:57.720395 # ok 1485 Set SVE VL 5936
3216 10:54:57.720494 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3217 10:54:57.720584 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3218 10:54:57.722454 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3219 10:54:57.722766 # ok 1489 Set SVE VL 5952
3220 10:54:57.722941 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3221 10:54:57.723122 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3222 10:54:57.723222 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3223 10:54:57.723314 # ok 1493 Set SVE VL 5968
3224 10:54:57.723405 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3225 10:54:57.723493 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3226 10:54:57.723609 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3227 10:54:57.723717 # ok 1497 Set SVE VL 5984
3228 10:54:57.723834 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3229 10:54:57.723967 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3230 10:54:57.724071 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3231 10:54:57.724155 # ok 1501 Set SVE VL 6000
3232 10:54:57.724262 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3233 10:54:57.724335 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3234 10:54:57.725639 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3235 10:54:57.725977 # ok 1505 Set SVE VL 6016
3236 10:54:57.726165 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3237 10:54:57.726401 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3238 10:54:57.726589 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3239 10:54:57.726723 # ok 1509 Set SVE VL 6032
3240 10:54:57.726844 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3241 10:54:57.726992 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3242 10:54:57.727125 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3243 10:54:57.727253 # ok 1513 Set SVE VL 6048
3244 10:54:57.727372 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3245 10:54:57.727512 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3246 10:54:57.727607 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3247 10:54:57.727681 # ok 1517 Set SVE VL 6064
3248 10:54:57.727770 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3249 10:54:57.727881 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3250 10:54:57.727972 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3251 10:54:57.728059 # ok 1521 Set SVE VL 6080
3252 10:54:57.728186 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3253 10:54:57.728282 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3254 10:54:57.728388 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3255 10:54:57.728482 # ok 1525 Set SVE VL 6096
3256 10:54:57.729587 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3257 10:54:57.729903 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3258 10:54:57.730040 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3259 10:54:57.730180 # ok 1529 Set SVE VL 6112
3260 10:54:57.730267 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3261 10:54:57.730555 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3262 10:54:57.730644 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3263 10:54:57.730749 # ok 1533 Set SVE VL 6128
3264 10:54:57.730872 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3265 10:54:57.730973 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3266 10:54:57.731073 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3267 10:54:57.731143 # ok 1537 Set SVE VL 6144
3268 10:54:57.731229 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3269 10:54:57.731318 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3270 10:54:57.731652 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3271 10:54:57.731841 # ok 1541 Set SVE VL 6160
3272 10:54:57.732070 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3273 10:54:57.732280 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3274 10:54:57.732419 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3275 10:54:57.732539 # ok 1545 Set SVE VL 6176
3276 10:54:57.733931 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3277 10:54:57.734308 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3278 10:54:57.734430 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3279 10:54:57.734526 # ok 1549 Set SVE VL 6192
3280 10:54:57.734779 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3281 10:54:57.734866 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3282 10:54:57.734976 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3283 10:54:57.735085 # ok 1553 Set SVE VL 6208
3284 10:54:57.735158 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3285 10:54:57.735442 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3286 10:54:57.735542 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3287 10:54:57.735655 # ok 1557 Set SVE VL 6224
3288 10:54:57.735752 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3289 10:54:57.735836 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3290 10:54:57.735922 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3291 10:54:57.736214 # ok 1561 Set SVE VL 6240
3292 10:54:57.736293 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3293 10:54:57.737330 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3294 10:54:57.737582 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3295 10:54:57.737675 # ok 1565 Set SVE VL 6256
3296 10:54:57.737946 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3297 10:54:57.738024 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3298 10:54:57.738273 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3299 10:54:57.738346 # ok 1569 Set SVE VL 6272
3300 10:54:57.738412 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3301 10:54:57.738480 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3302 10:54:57.738557 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3303 10:54:57.738636 # ok 1573 Set SVE VL 6288
3304 10:54:57.738883 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3305 10:54:57.738954 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3306 10:54:57.739031 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3307 10:54:57.739117 # ok 1577 Set SVE VL 6304
3308 10:54:57.739372 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3309 10:54:57.739443 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3310 10:54:57.739520 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3311 10:54:57.739602 # ok 1581 Set SVE VL 6320
3312 10:54:57.739696 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3313 10:54:57.739951 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3314 10:54:57.740023 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3315 10:54:57.740100 # ok 1585 Set SVE VL 6336
3316 10:54:57.740367 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3317 10:54:57.740452 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3318 10:54:57.740885 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3319 10:54:57.740971 # ok 1589 Set SVE VL 6352
3320 10:54:57.745298 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3321 10:54:57.745422 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3322 10:54:57.745685 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3323 10:54:57.745782 # ok 1593 Set SVE VL 6368
3324 10:54:57.745879 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3325 10:54:57.746140 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3326 10:54:57.746229 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3327 10:54:57.746323 # ok 1597 Set SVE VL 6384
3328 10:54:57.746401 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3329 10:54:57.746476 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3330 10:54:57.746710 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3331 10:54:57.746834 # ok 1601 Set SVE VL 6400
3332 10:54:57.747141 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3333 10:54:57.747234 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3334 10:54:57.747328 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3335 10:54:57.747422 # ok 1605 Set SVE VL 6416
3336 10:54:57.747684 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3337 10:54:57.747758 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3338 10:54:57.747836 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3339 10:54:57.747914 # ok 1609 Set SVE VL 6432
3340 10:54:57.748163 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3341 10:54:57.748237 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3342 10:54:57.748320 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3343 10:54:57.748629 # ok 1613 Set SVE VL 6448
3344 10:54:57.748883 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3345 10:54:57.748956 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3346 10:54:57.749210 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3347 10:54:57.749280 # ok 1617 Set SVE VL 6464
3348 10:54:57.749359 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3349 10:54:57.749437 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3350 10:54:57.749515 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3351 10:54:57.749773 # ok 1621 Set SVE VL 6480
3352 10:54:57.749856 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3353 10:54:57.750103 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3354 10:54:57.750226 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3355 10:54:57.750315 # ok 1625 Set SVE VL 6496
3356 10:54:57.750420 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3357 10:54:57.750547 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3358 10:54:57.750647 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3359 10:54:57.750756 # ok 1629 Set SVE VL 6512
3360 10:54:57.750883 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3361 10:54:57.750982 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3362 10:54:57.751310 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3363 10:54:57.751415 # ok 1633 Set SVE VL 6528
3364 10:54:57.751525 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3365 10:54:57.751638 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3366 10:54:57.751763 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3367 10:54:57.751884 # ok 1637 Set SVE VL 6544
3368 10:54:57.751988 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3369 10:54:57.752084 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3370 10:54:57.752186 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3371 10:54:57.752477 # ok 1641 Set SVE VL 6560
3372 10:54:57.752597 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3373 10:54:57.752711 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3374 10:54:57.753033 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3375 10:54:57.753132 # ok 1645 Set SVE VL 6576
3376 10:54:57.753238 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3377 10:54:57.753540 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3378 10:54:57.753690 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3379 10:54:57.753785 # ok 1649 Set SVE VL 6592
3380 10:54:57.753879 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3381 10:54:57.753971 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3382 10:54:57.754056 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3383 10:54:57.754130 # ok 1653 Set SVE VL 6608
3384 10:54:57.754242 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3385 10:54:57.754364 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3386 10:54:57.754658 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3387 10:54:57.754742 # ok 1657 Set SVE VL 6624
3388 10:54:57.754846 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3389 10:54:57.754945 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3390 10:54:57.755044 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3391 10:54:57.755134 # ok 1661 Set SVE VL 6640
3392 10:54:57.755222 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3393 10:54:57.755490 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3394 10:54:57.755745 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3395 10:54:57.755818 # ok 1665 Set SVE VL 6656
3396 10:54:57.756180 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3397 10:54:57.756308 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3398 10:54:57.756420 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3399 10:54:57.756523 # ok 1669 Set SVE VL 6672
3400 10:54:57.756805 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3401 10:54:57.757114 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3402 10:54:57.757218 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3403 10:54:57.757324 # ok 1673 Set SVE VL 6688
3404 10:54:57.757444 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3405 10:54:57.757564 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3406 10:54:57.757918 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3407 10:54:57.758019 # ok 1677 Set SVE VL 6704
3408 10:54:57.758127 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3409 10:54:57.758217 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3410 10:54:57.758345 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3411 10:54:57.758462 # ok 1681 Set SVE VL 6720
3412 10:54:57.758560 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3413 10:54:57.758665 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3414 10:54:57.758762 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3415 10:54:57.758832 # ok 1685 Set SVE VL 6736
3416 10:54:57.758957 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3417 10:54:57.759050 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3418 10:54:57.759149 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3419 10:54:57.759260 # ok 1689 Set SVE VL 6752
3420 10:54:57.759355 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3421 10:54:57.759462 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3422 10:54:57.759964 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3423 10:54:57.760076 # ok 1693 Set SVE VL 6768
3424 10:54:57.760167 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3425 10:54:57.760251 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3426 10:54:57.760335 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3427 10:54:57.760400 # ok 1697 Set SVE VL 6784
3428 10:54:57.762196 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3429 10:54:57.762522 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3430 10:54:57.762661 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3431 10:54:57.762746 # ok 1701 Set SVE VL 6800
3432 10:54:57.762846 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3433 10:54:57.762948 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3434 10:54:57.763069 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3435 10:54:57.763169 # ok 1705 Set SVE VL 6816
3436 10:54:57.763297 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3437 10:54:57.763414 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3438 10:54:57.763707 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3439 10:54:57.763804 # ok 1709 Set SVE VL 6832
3440 10:54:57.763902 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3441 10:54:57.763989 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3442 10:54:57.764306 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3443 10:54:57.764405 # ok 1713 Set SVE VL 6848
3444 10:54:57.765264 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3445 10:54:57.765570 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3446 10:54:57.765693 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3447 10:54:57.765803 # ok 1717 Set SVE VL 6864
3448 10:54:57.765889 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3449 10:54:57.765990 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3450 10:54:57.766098 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3451 10:54:57.766213 # ok 1721 Set SVE VL 6880
3452 10:54:57.766521 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3453 10:54:57.766624 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3454 10:54:57.766718 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3455 10:54:57.766813 # ok 1725 Set SVE VL 6896
3456 10:54:57.766895 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3457 10:54:57.766985 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3458 10:54:57.767077 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3459 10:54:57.767173 # ok 1729 Set SVE VL 6912
3460 10:54:57.767265 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3461 10:54:57.767457 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3462 10:54:57.767572 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3463 10:54:57.767672 # ok 1733 Set SVE VL 6928
3464 10:54:57.767768 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3465 10:54:57.767860 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3466 10:54:57.768146 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3467 10:54:57.768232 # ok 1737 Set SVE VL 6944
3468 10:54:57.768506 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3469 10:54:57.768605 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3470 10:54:57.768708 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3471 10:54:57.768800 # ok 1741 Set SVE VL 6960
3472 10:54:57.769098 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3473 10:54:57.769198 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3474 10:54:57.769291 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3475 10:54:57.769384 # ok 1745 Set SVE VL 6976
3476 10:54:57.769474 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3477 10:54:57.769758 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3478 10:54:57.769873 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3479 10:54:57.769954 # ok 1749 Set SVE VL 6992
3480 10:54:57.770043 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3481 10:54:57.770354 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3482 10:54:57.770453 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3483 10:54:57.770548 # ok 1753 Set SVE VL 7008
3484 10:54:57.770627 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3485 10:54:57.770717 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3486 10:54:57.771002 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3487 10:54:57.771106 # ok 1757 Set SVE VL 7024
3488 10:54:57.771248 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3489 10:54:57.771384 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3490 10:54:57.771502 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3491 10:54:57.771586 # ok 1761 Set SVE VL 7040
3492 10:54:57.771723 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3493 10:54:57.772020 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3494 10:54:57.772119 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3495 10:54:57.772205 # ok 1765 Set SVE VL 7056
3496 10:54:57.772300 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3497 10:54:57.772416 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3498 10:54:57.772537 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3499 10:54:57.772632 # ok 1769 Set SVE VL 7072
3500 10:54:57.772726 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3501 10:54:57.772802 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3502 10:54:57.773557 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3503 10:54:57.777732 # ok 1773 Set SVE VL 7088
3504 10:54:57.777945 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3505 10:54:57.778059 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3506 10:54:57.778164 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3507 10:54:57.778258 # ok 1777 Set SVE VL 7104
3508 10:54:57.778363 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3509 10:54:57.778443 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3510 10:54:57.778537 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3511 10:54:57.778642 # ok 1781 Set SVE VL 7120
3512 10:54:57.778754 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3513 10:54:57.779083 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3514 10:54:57.779192 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3515 10:54:57.779485 # ok 1785 Set SVE VL 7136
3516 10:54:57.779580 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3517 10:54:57.779668 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3518 10:54:57.779788 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3519 10:54:57.779890 # ok 1789 Set SVE VL 7152
3520 10:54:57.780019 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3521 10:54:57.780139 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3522 10:54:57.780270 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3523 10:54:57.780368 # ok 1793 Set SVE VL 7168
3524 10:54:57.780689 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3525 10:54:57.780786 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3526 10:54:57.780878 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3527 10:54:57.780984 # ok 1797 Set SVE VL 7184
3528 10:54:57.781099 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3529 10:54:57.781200 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3530 10:54:57.781322 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3531 10:54:57.781434 # ok 1801 Set SVE VL 7200
3532 10:54:57.781555 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3533 10:54:57.781658 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3534 10:54:57.781972 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3535 10:54:57.782078 # ok 1805 Set SVE VL 7216
3536 10:54:57.782174 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3537 10:54:57.782270 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3538 10:54:57.782388 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3539 10:54:57.782474 # ok 1809 Set SVE VL 7232
3540 10:54:57.782567 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3541 10:54:57.782657 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3542 10:54:57.782787 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3543 10:54:57.782885 # ok 1813 Set SVE VL 7248
3544 10:54:57.782992 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3545 10:54:57.783106 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3546 10:54:57.783205 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3547 10:54:57.783322 # ok 1817 Set SVE VL 7264
3548 10:54:57.783413 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3549 10:54:57.783516 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3550 10:54:57.783786 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3551 10:54:57.783887 # ok 1821 Set SVE VL 7280
3552 10:54:57.784006 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3553 10:54:57.784088 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3554 10:54:57.784178 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3555 10:54:57.784259 # ok 1825 Set SVE VL 7296
3556 10:54:57.784529 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3557 10:54:57.784615 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3558 10:54:57.784883 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3559 10:54:57.784956 # ok 1829 Set SVE VL 7312
3560 10:54:57.785073 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3561 10:54:57.785196 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3562 10:54:57.785290 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3563 10:54:57.785378 # ok 1833 Set SVE VL 7328
3564 10:54:57.785654 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3565 10:54:57.785745 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3566 10:54:57.785995 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3567 10:54:57.786073 # ok 1837 Set SVE VL 7344
3568 10:54:57.786163 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3569 10:54:57.786254 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3570 10:54:57.786553 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3571 10:54:57.786646 # ok 1841 Set SVE VL 7360
3572 10:54:57.786766 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3573 10:54:57.786861 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3574 10:54:57.786977 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3575 10:54:57.787091 # ok 1845 Set SVE VL 7376
3576 10:54:57.787197 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3577 10:54:57.787498 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3578 10:54:57.787603 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3579 10:54:57.787729 # ok 1849 Set SVE VL 7392
3580 10:54:57.787830 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3581 10:54:57.787949 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3582 10:54:57.788049 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3583 10:54:57.788170 # ok 1853 Set SVE VL 7408
3584 10:54:57.788282 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3585 10:54:57.788396 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3586 10:54:57.788523 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3587 10:54:57.788633 # ok 1857 Set SVE VL 7424
3588 10:54:57.788740 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3589 10:54:57.789030 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3590 10:54:57.789430 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3591 10:54:57.789547 # ok 1861 Set SVE VL 7440
3592 10:54:57.789659 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3593 10:54:57.790103 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3594 10:54:57.790215 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3595 10:54:57.790316 # ok 1865 Set SVE VL 7456
3596 10:54:57.790415 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3597 10:54:57.790512 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3598 10:54:57.790610 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3599 10:54:57.790708 # ok 1869 Set SVE VL 7472
3600 10:54:57.791009 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3601 10:54:57.791119 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3602 10:54:57.791219 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3603 10:54:57.791313 # ok 1873 Set SVE VL 7488
3604 10:54:57.791380 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3605 10:54:57.791474 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3606 10:54:57.791579 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3607 10:54:57.791677 # ok 1877 Set SVE VL 7504
3608 10:54:57.791793 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3609 10:54:57.791884 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3610 10:54:57.791960 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3611 10:54:57.792036 # ok 1881 Set SVE VL 7520
3612 10:54:57.792112 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3613 10:54:57.792200 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3614 10:54:57.792284 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3615 10:54:57.792350 # ok 1885 Set SVE VL 7536
3616 10:54:57.792443 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3617 10:54:57.792528 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3618 10:54:57.792628 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3619 10:54:57.792730 # ok 1889 Set SVE VL 7552
3620 10:54:57.792834 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3621 10:54:57.792919 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3622 10:54:57.793017 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3623 10:54:57.793110 # ok 1893 Set SVE VL 7568
3624 10:54:57.793200 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3625 10:54:57.793485 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3626 10:54:57.793584 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3627 10:54:57.793697 # ok 1897 Set SVE VL 7584
3628 10:54:57.793816 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3629 10:54:57.793921 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3630 10:54:57.794021 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3631 10:54:57.794161 # ok 1901 Set SVE VL 7600
3632 10:54:57.794273 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3633 10:54:57.794605 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3634 10:54:57.794705 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3635 10:54:57.794808 # ok 1905 Set SVE VL 7616
3636 10:54:57.794912 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3637 10:54:57.795036 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3638 10:54:57.795182 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3639 10:54:57.795315 # ok 1909 Set SVE VL 7632
3640 10:54:57.795434 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3641 10:54:57.795546 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3642 10:54:57.795631 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3643 10:54:57.795717 # ok 1913 Set SVE VL 7648
3644 10:54:57.796011 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3645 10:54:57.796138 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3646 10:54:57.796249 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3647 10:54:57.796329 # ok 1917 Set SVE VL 7664
3648 10:54:57.797044 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3649 10:54:57.797146 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3650 10:54:57.797228 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3651 10:54:57.797302 # ok 1921 Set SVE VL 7680
3652 10:54:57.797388 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3653 10:54:57.797476 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3654 10:54:57.797825 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3655 10:54:57.797930 # ok 1925 Set SVE VL 7696
3656 10:54:57.798038 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3657 10:54:57.798125 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3658 10:54:57.798221 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3659 10:54:57.798307 # ok 1929 Set SVE VL 7712
3660 10:54:57.798436 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3661 10:54:57.798585 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3662 10:54:57.798684 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3663 10:54:57.798796 # ok 1933 Set SVE VL 7728
3664 10:54:57.798903 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3665 10:54:57.799018 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3666 10:54:57.799113 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3667 10:54:57.799199 # ok 1937 Set SVE VL 7744
3668 10:54:57.799286 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3669 10:54:57.799370 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3670 10:54:57.799470 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3671 10:54:57.799557 # ok 1941 Set SVE VL 7760
3672 10:54:57.799642 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3673 10:54:57.799745 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3674 10:54:57.799833 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3675 10:54:57.799915 # ok 1945 Set SVE VL 7776
3676 10:54:57.800016 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3677 10:54:57.800100 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3678 10:54:57.800196 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3679 10:54:57.800544 # ok 1949 Set SVE VL 7792
3680 10:54:57.800868 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3681 10:54:57.800970 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3682 10:54:57.801064 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3683 10:54:57.801151 # ok 1953 Set SVE VL 7808
3684 10:54:57.801253 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3685 10:54:57.801342 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3686 10:54:57.806838 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3687 10:54:57.806933 # ok 1957 Set SVE VL 7824
3688 10:54:57.807030 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3689 10:54:57.807127 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3690 10:54:57.807256 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3691 10:54:57.807374 # ok 1961 Set SVE VL 7840
3692 10:54:57.807503 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3693 10:54:57.807626 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3694 10:54:57.807888 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3695 10:54:57.807996 # ok 1965 Set SVE VL 7856
3696 10:54:57.808085 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3697 10:54:57.808171 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3698 10:54:57.809096 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3699 10:54:57.809360 # ok 1969 Set SVE VL 7872
3700 10:54:57.809619 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3701 10:54:57.809724 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3702 10:54:57.809813 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3703 10:54:57.809878 # ok 1973 Set SVE VL 7888
3704 10:54:57.811009 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3705 10:54:57.811148 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3706 10:54:57.811271 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3707 10:54:57.811406 # ok 1977 Set SVE VL 7904
3708 10:54:57.811545 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3709 10:54:57.811657 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3710 10:54:57.811750 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3711 10:54:57.811837 # ok 1981 Set SVE VL 7920
3712 10:54:57.811922 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3713 10:54:57.812205 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3714 10:54:57.812358 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3715 10:54:57.812447 # ok 1985 Set SVE VL 7936
3716 10:54:57.812527 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3717 10:54:57.812590 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3718 10:54:57.812674 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3719 10:54:57.812749 # ok 1989 Set SVE VL 7952
3720 10:54:57.812810 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3721 10:54:57.812871 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3722 10:54:57.813231 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3723 10:54:57.813361 # ok 1993 Set SVE VL 7968
3724 10:54:57.813451 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3725 10:54:57.813530 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3726 10:54:57.813596 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3727 10:54:57.813862 # ok 1997 Set SVE VL 7984
3728 10:54:57.813952 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3729 10:54:57.814027 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3730 10:54:57.814105 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3731 10:54:57.814184 # ok 2001 Set SVE VL 8000
3732 10:54:57.814274 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3733 10:54:57.814375 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3734 10:54:57.814477 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3735 10:54:57.814553 # ok 2005 Set SVE VL 8016
3736 10:54:57.814673 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3737 10:54:57.814780 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3738 10:54:57.814887 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3739 10:54:57.814978 # ok 2009 Set SVE VL 8032
3740 10:54:57.815082 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3741 10:54:57.815186 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3742 10:54:57.815310 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3743 10:54:57.815418 # ok 2013 Set SVE VL 8048
3744 10:54:57.815540 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3745 10:54:57.815842 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3746 10:54:57.815958 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3747 10:54:57.816044 # ok 2017 Set SVE VL 8064
3748 10:54:57.816138 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3749 10:54:57.816486 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3750 10:54:57.816726 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3751 10:54:57.816816 # ok 2021 Set SVE VL 8080
3752 10:54:57.816899 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3753 10:54:57.816998 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3754 10:54:57.817091 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3755 10:54:57.817186 # ok 2025 Set SVE VL 8096
3756 10:54:57.817280 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3757 10:54:57.817376 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3758 10:54:57.817827 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3759 10:54:57.817985 # ok 2029 Set SVE VL 8112
3760 10:54:57.818483 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3761 10:54:57.818573 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3762 10:54:57.818653 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3763 10:54:57.818736 # ok 2033 Set SVE VL 8128
3764 10:54:57.818819 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3765 10:54:57.819267 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3766 10:54:57.819386 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3767 10:54:57.819486 # ok 2037 Set SVE VL 8144
3768 10:54:57.819581 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3769 10:54:57.819886 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3770 10:54:57.819999 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3771 10:54:57.820097 # ok 2041 Set SVE VL 8160
3772 10:54:57.820185 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3773 10:54:57.820277 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3774 10:54:57.820371 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3775 10:54:57.820472 # ok 2045 Set SVE VL 8176
3776 10:54:57.820566 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3777 10:54:57.820680 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3778 10:54:57.820782 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3779 10:54:57.820877 # ok 2049 Set SVE VL 8192
3780 10:54:57.820970 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3781 10:54:57.821065 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3782 10:54:57.821176 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3783 10:54:57.821272 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3784 10:54:57.821367 # ok 2054 Streaming SVE get_fpsimd() gave same state
3785 10:54:57.821478 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3786 10:54:57.821575 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3787 10:54:57.821696 # ok 2057 Set Streaming SVE VL 16
3788 10:54:57.821799 # ok 2058 Set and get Streaming SVE data for VL 16
3789 10:54:57.821910 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3790 10:54:57.822023 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3791 10:54:57.822134 # ok 2061 Set Streaming SVE VL 32
3792 10:54:57.822245 # ok 2062 Set and get Streaming SVE data for VL 32
3793 10:54:57.822565 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3794 10:54:57.822683 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3795 10:54:57.822795 # ok 2065 Set Streaming SVE VL 48
3796 10:54:57.823094 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3797 10:54:57.823210 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3798 10:54:57.823509 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3799 10:54:57.823610 # ok 2069 Set Streaming SVE VL 64
3800 10:54:57.823721 # ok 2070 Set and get Streaming SVE data for VL 64
3801 10:54:57.823833 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3802 10:54:57.824149 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3803 10:54:57.824440 # ok 2073 Set Streaming SVE VL 80
3804 10:54:57.824553 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3805 10:54:57.824848 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3806 10:54:57.824948 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3807 10:54:57.825042 # ok 2077 Set Streaming SVE VL 96
3808 10:54:57.825338 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3809 10:54:57.825432 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3810 10:54:57.825541 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3811 10:54:57.825658 # ok 2081 Set Streaming SVE VL 112
3812 10:54:57.825768 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3813 10:54:57.826073 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3814 10:54:57.826190 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3815 10:54:57.826293 # ok 2085 Set Streaming SVE VL 128
3816 10:54:57.826581 # ok 2086 Set and get Streaming SVE data for VL 128
3817 10:54:57.826676 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3818 10:54:57.826957 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3819 10:54:57.827047 # ok 2089 Set Streaming SVE VL 144
3820 10:54:57.827149 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3821 10:54:57.827223 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3822 10:54:57.827683 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3823 10:54:57.827773 # ok 2093 Set Streaming SVE VL 160
3824 10:54:57.831703 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3825 10:54:57.831904 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3826 10:54:57.832023 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3827 10:54:57.832134 # ok 2097 Set Streaming SVE VL 176
3828 10:54:57.832236 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3829 10:54:57.832334 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3830 10:54:57.832431 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3831 10:54:57.832529 # ok 2101 Set Streaming SVE VL 192
3832 10:54:57.832627 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3833 10:54:57.832731 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3834 10:54:57.832834 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3835 10:54:57.832930 # ok 2105 Set Streaming SVE VL 208
3836 10:54:57.833026 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3837 10:54:57.833124 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3838 10:54:57.833222 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3839 10:54:57.833319 # ok 2109 Set Streaming SVE VL 224
3840 10:54:57.833415 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3841 10:54:57.833513 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3842 10:54:57.833612 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3843 10:54:57.833723 # ok 2113 Set Streaming SVE VL 240
3844 10:54:57.833829 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3845 10:54:57.833927 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3846 10:54:57.834025 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3847 10:54:57.834124 # ok 2117 Set Streaming SVE VL 256
3848 10:54:57.834222 # ok 2118 Set and get Streaming SVE data for VL 256
3849 10:54:57.834321 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3850 10:54:57.834419 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3851 10:54:57.834517 # ok 2121 Set Streaming SVE VL 272
3852 10:54:57.834615 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3853 10:54:57.834714 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3854 10:54:57.834817 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3855 10:54:57.834915 # ok 2125 Set Streaming SVE VL 288
3856 10:54:57.835222 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3857 10:54:57.835629 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3858 10:54:57.835724 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3859 10:54:57.835825 # ok 2129 Set Streaming SVE VL 304
3860 10:54:57.835910 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3861 10:54:57.836197 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3862 10:54:57.836313 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3863 10:54:57.836417 # ok 2133 Set Streaming SVE VL 320
3864 10:54:57.837206 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3865 10:54:57.837526 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3866 10:54:57.837777 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3867 10:54:57.837886 # ok 2137 Set Streaming SVE VL 336
3868 10:54:57.838003 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3869 10:54:57.838105 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3870 10:54:57.838288 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3871 10:54:57.838393 # ok 2141 Set Streaming SVE VL 352
3872 10:54:57.838481 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3873 10:54:57.838584 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3874 10:54:57.838664 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3875 10:54:57.838749 # ok 2145 Set Streaming SVE VL 368
3876 10:54:57.838844 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3877 10:54:57.838937 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3878 10:54:57.839046 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3879 10:54:57.839131 # ok 2149 Set Streaming SVE VL 384
3880 10:54:57.839439 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3881 10:54:57.839535 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3882 10:54:57.839648 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3883 10:54:57.839737 # ok 2153 Set Streaming SVE VL 400
3884 10:54:57.839824 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3885 10:54:57.840115 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3886 10:54:57.840211 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3887 10:54:57.840509 # ok 2157 Set Streaming SVE VL 416
3888 10:54:57.840609 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3889 10:54:57.840893 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3890 10:54:57.841184 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3891 10:54:57.841299 # ok 2161 Set Streaming SVE VL 432
3892 10:54:57.841480 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3893 10:54:57.841599 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3894 10:54:57.841714 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3895 10:54:57.841828 # ok 2165 Set Streaming SVE VL 448
3896 10:54:57.841933 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3897 10:54:57.842207 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3898 10:54:57.842319 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3899 10:54:57.842441 # ok 2169 Set Streaming SVE VL 464
3900 10:54:57.842560 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3901 10:54:57.842681 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3902 10:54:57.842798 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3903 10:54:57.842919 # ok 2173 Set Streaming SVE VL 480
3904 10:54:57.843206 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3905 10:54:57.843330 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3906 10:54:57.843712 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3907 10:54:57.843825 # ok 2177 Set Streaming SVE VL 496
3908 10:54:57.843927 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3909 10:54:57.844026 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3910 10:54:57.844126 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3911 10:54:57.844212 # ok 2181 Set Streaming SVE VL 512
3912 10:54:57.844656 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3913 10:54:57.844758 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3914 10:54:57.845044 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3915 10:54:57.845148 # ok 2185 Set Streaming SVE VL 528
3916 10:54:57.845232 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3917 10:54:57.845328 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3918 10:54:57.845601 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3919 10:54:57.845709 # ok 2189 Set Streaming SVE VL 544
3920 10:54:57.845801 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3921 10:54:57.845908 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3922 10:54:57.845996 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3923 10:54:57.846098 # ok 2193 Set Streaming SVE VL 560
3924 10:54:57.846203 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3925 10:54:57.846312 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3926 10:54:57.846412 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3927 10:54:57.846509 # ok 2197 Set Streaming SVE VL 576
3928 10:54:57.846631 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3929 10:54:57.846739 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3930 10:54:57.846850 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3931 10:54:57.847143 # ok 2201 Set Streaming SVE VL 592
3932 10:54:57.847435 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3933 10:54:57.847534 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3934 10:54:57.847638 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3935 10:54:57.847730 # ok 2205 Set Streaming SVE VL 608
3936 10:54:57.847828 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3937 10:54:57.848118 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3938 10:54:57.848212 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3939 10:54:57.848485 # ok 2209 Set Streaming SVE VL 624
3940 10:54:57.848606 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3941 10:54:57.848897 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3942 10:54:57.848987 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3943 10:54:57.849084 # ok 2213 Set Streaming SVE VL 640
3944 10:54:57.849355 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3945 10:54:57.849439 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3946 10:54:57.849691 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3947 10:54:57.849791 # ok 2217 Set Streaming SVE VL 656
3948 10:54:57.849888 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3949 10:54:57.850007 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3950 10:54:57.850304 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3951 10:54:57.850415 # ok 2221 Set Streaming SVE VL 672
3952 10:54:57.850510 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3953 10:54:57.850815 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3954 10:54:57.850934 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3955 10:54:57.851015 # ok 2225 Set Streaming SVE VL 688
3956 10:54:57.851267 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3957 10:54:57.851525 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3958 10:54:57.851804 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3959 10:54:57.851901 # ok 2229 Set Streaming SVE VL 704
3960 10:54:57.852026 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3961 10:54:57.852126 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3962 10:54:57.852244 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3963 10:54:57.852533 # ok 2233 Set Streaming SVE VL 720
3964 10:54:57.852663 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3965 10:54:57.852761 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3966 10:54:57.852940 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3967 10:54:57.853089 # ok 2237 Set Streaming SVE VL 736
3968 10:54:57.853457 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3969 10:54:57.853570 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3970 10:54:57.853674 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3971 10:54:57.853780 # ok 2241 Set Streaming SVE VL 752
3972 10:54:57.853867 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3973 10:54:57.853969 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3974 10:54:57.854055 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3975 10:54:57.854132 # ok 2245 Set Streaming SVE VL 768
3976 10:54:57.854209 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3977 10:54:57.854299 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3978 10:54:57.854390 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3979 10:54:57.854499 # ok 2249 Set Streaming SVE VL 784
3980 10:54:57.854592 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3981 10:54:57.854682 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3982 10:54:57.854772 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3983 10:54:57.854879 # ok 2253 Set Streaming SVE VL 800
3984 10:54:57.854972 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3985 10:54:57.855076 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3986 10:54:57.855171 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3987 10:54:57.855261 # ok 2257 Set Streaming SVE VL 816
3988 10:54:57.855375 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3989 10:54:57.855469 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3990 10:54:57.855574 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3991 10:54:57.855668 # ok 2261 Set Streaming SVE VL 832
3992 10:54:57.855775 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3993 10:54:57.855882 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3994 10:54:57.855991 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3995 10:54:57.856081 # ok 2265 Set Streaming SVE VL 848
3996 10:54:57.856182 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3997 10:54:57.856292 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3998 10:54:57.856397 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3999 10:54:57.856505 # ok 2269 Set Streaming SVE VL 864
4000 10:54:57.856598 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
4001 10:54:57.856897 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
4002 10:54:57.857008 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4003 10:54:57.857101 # ok 2273 Set Streaming SVE VL 880
4004 10:54:57.857206 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4005 10:54:57.857299 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4006 10:54:57.857391 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4007 10:54:57.857483 # ok 2277 Set Streaming SVE VL 896
4008 10:54:57.857587 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4009 10:54:57.859890 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4010 10:54:57.860017 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4011 10:54:57.860307 # ok 2281 Set Streaming SVE VL 912
4012 10:54:57.863239 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4013 10:54:57.863341 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4014 10:54:57.863435 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4015 10:54:57.863525 # ok 2285 Set Streaming SVE VL 928
4016 10:54:57.863616 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4017 10:54:57.863703 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4018 10:54:57.863793 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4019 10:54:57.863887 # ok 2289 Set Streaming SVE VL 944
4020 10:54:57.863975 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4021 10:54:57.864064 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4022 10:54:57.864153 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4023 10:54:57.864243 # ok 2293 Set Streaming SVE VL 960
4024 10:54:57.864332 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4025 10:54:57.864420 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4026 10:54:57.864509 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4027 10:54:57.864598 # ok 2297 Set Streaming SVE VL 976
4028 10:54:57.864686 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4029 10:54:57.864777 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4030 10:54:57.864870 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4031 10:54:57.864960 # ok 2301 Set Streaming SVE VL 992
4032 10:54:57.865247 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4033 10:54:57.865349 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4034 10:54:57.865445 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4035 10:54:57.865539 # ok 2305 Set Streaming SVE VL 1008
4036 10:54:57.865633 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4037 10:54:57.865744 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4038 10:54:57.865845 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4039 10:54:57.865940 # ok 2309 Set Streaming SVE VL 1024
4040 10:54:57.866035 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4041 10:54:57.866127 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4042 10:54:57.866223 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4043 10:54:57.866318 # ok 2313 Set Streaming SVE VL 1040
4044 10:54:57.866412 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4045 10:54:57.866507 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4046 10:54:57.866603 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4047 10:54:57.866698 # ok 2317 Set Streaming SVE VL 1056
4048 10:54:57.866792 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4049 10:54:57.866916 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4050 10:54:57.867014 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4051 10:54:57.867109 # ok 2321 Set Streaming SVE VL 1072
4052 10:54:57.867204 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4053 10:54:57.867299 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4054 10:54:57.867394 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4055 10:54:57.867489 # ok 2325 Set Streaming SVE VL 1088
4056 10:54:57.867584 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4057 10:54:57.867679 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4058 10:54:57.867774 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4059 10:54:57.867873 # ok 2329 Set Streaming SVE VL 1104
4060 10:54:57.867968 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4061 10:54:57.868062 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4062 10:54:57.868159 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4063 10:54:57.868255 # ok 2333 Set Streaming SVE VL 1120
4064 10:54:57.868349 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4065 10:54:57.868462 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4066 10:54:57.868560 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4067 10:54:57.868655 # ok 2337 Set Streaming SVE VL 1136
4068 10:54:57.868962 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4069 10:54:57.869078 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4070 10:54:57.869188 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4071 10:54:57.869284 # ok 2341 Set Streaming SVE VL 1152
4072 10:54:57.869372 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4073 10:54:57.869450 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4074 10:54:57.869552 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4075 10:54:57.869668 # ok 2345 Set Streaming SVE VL 1168
4076 10:54:57.869776 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4077 10:54:57.869875 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4078 10:54:57.869964 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4079 10:54:57.870041 # ok 2349 Set Streaming SVE VL 1184
4080 10:54:57.870115 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4081 10:54:57.870187 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4082 10:54:57.870249 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4083 10:54:57.870320 # ok 2353 Set Streaming SVE VL 1200
4084 10:54:57.870420 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4085 10:54:57.870503 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4086 10:54:57.870583 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4087 10:54:57.870654 # ok 2357 Set Streaming SVE VL 1216
4088 10:54:57.870727 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4089 10:54:57.870806 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4090 10:54:57.870889 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4091 10:54:57.870956 # ok 2361 Set Streaming SVE VL 1232
4092 10:54:57.871046 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4093 10:54:57.871125 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4094 10:54:57.871186 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4095 10:54:57.871248 # ok 2365 Set Streaming SVE VL 1248
4096 10:54:57.871307 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4097 10:54:57.871382 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4098 10:54:57.871445 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4099 10:54:57.871506 # ok 2369 Set Streaming SVE VL 1264
4100 10:54:57.871566 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4101 10:54:57.871625 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4102 10:54:57.871684 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4103 10:54:57.871946 # ok 2373 Set Streaming SVE VL 1280
4104 10:54:57.872065 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4105 10:54:57.872163 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4106 10:54:57.872259 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4107 10:54:57.872355 # ok 2377 Set Streaming SVE VL 1296
4108 10:54:57.872449 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4109 10:54:57.872543 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4110 10:54:57.872638 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4111 10:54:57.872751 # ok 2381 Set Streaming SVE VL 1312
4112 10:54:57.872854 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4113 10:54:57.872949 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4114 10:54:57.873044 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4115 10:54:57.873139 # ok 2385 Set Streaming SVE VL 1328
4116 10:54:57.873234 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4117 10:54:57.873350 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4118 10:54:57.873449 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4119 10:54:57.873545 # ok 2389 Set Streaming SVE VL 1344
4120 10:54:57.873639 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4121 10:54:57.873743 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4122 10:54:57.873842 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4123 10:54:57.873938 # ok 2393 Set Streaming SVE VL 1360
4124 10:54:57.874053 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4125 10:54:57.874152 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4126 10:54:57.874247 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4127 10:54:57.874343 # ok 2397 Set Streaming SVE VL 1376
4128 10:54:57.884178 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4129 10:54:57.884355 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4130 10:54:57.884443 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4131 10:54:57.884539 # ok 2401 Set Streaming SVE VL 1392
4132 10:54:57.884605 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4133 10:54:57.884669 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4134 10:54:57.884732 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4135 10:54:57.884794 # ok 2405 Set Streaming SVE VL 1408
4136 10:54:57.884861 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4137 10:54:57.884924 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4138 10:54:57.885184 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4139 10:54:57.885276 # ok 2409 Set Streaming SVE VL 1424
4140 10:54:57.885359 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4141 10:54:57.885430 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4142 10:54:57.885494 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4143 10:54:57.885558 # ok 2413 Set Streaming SVE VL 1440
4144 10:54:57.885626 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4145 10:54:57.885708 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4146 10:54:57.885816 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4147 10:54:57.885917 # ok 2417 Set Streaming SVE VL 1456
4148 10:54:57.886019 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4149 10:54:57.886113 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4150 10:54:57.886195 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4151 10:54:57.886273 # ok 2421 Set Streaming SVE VL 1472
4152 10:54:57.886339 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4153 10:54:57.886420 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4154 10:54:57.886491 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4155 10:54:57.886552 # ok 2425 Set Streaming SVE VL 1488
4156 10:54:57.886614 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4157 10:54:57.886675 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4158 10:54:57.886736 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4159 10:54:57.886799 # ok 2429 Set Streaming SVE VL 1504
4160 10:54:57.886864 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4161 10:54:57.886933 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4162 10:54:57.887010 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4163 10:54:57.887089 # ok 2433 Set Streaming SVE VL 1520
4164 10:54:57.887163 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4165 10:54:57.887260 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4166 10:54:57.887349 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4167 10:54:57.887438 # ok 2437 Set Streaming SVE VL 1536
4168 10:54:57.887518 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4169 10:54:57.887600 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4170 10:54:57.887675 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4171 10:54:57.887748 # ok 2441 Set Streaming SVE VL 1552
4172 10:54:57.887819 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4173 10:54:57.888107 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4174 10:54:57.888224 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4175 10:54:57.888324 # ok 2445 Set Streaming SVE VL 1568
4176 10:54:57.888421 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4177 10:54:57.888517 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4178 10:54:57.888614 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4179 10:54:57.888710 # ok 2449 Set Streaming SVE VL 1584
4180 10:54:57.888806 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4181 10:54:57.888902 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4182 10:54:57.888998 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4183 10:54:57.889094 # ok 2453 Set Streaming SVE VL 1600
4184 10:54:57.889189 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4185 10:54:57.889285 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4186 10:54:57.889381 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4187 10:54:57.889477 # ok 2457 Set Streaming SVE VL 1616
4188 10:54:57.889572 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4189 10:54:57.889680 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4190 10:54:57.889778 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4191 10:54:57.889874 # ok 2461 Set Streaming SVE VL 1632
4192 10:54:57.889969 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4193 10:54:57.890065 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4194 10:54:57.890161 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4195 10:54:57.890256 # ok 2465 Set Streaming SVE VL 1648
4196 10:54:57.890352 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4197 10:54:57.890448 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4198 10:54:57.890544 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4199 10:54:57.890639 # ok 2469 Set Streaming SVE VL 1664
4200 10:54:57.890735 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4201 10:54:57.890830 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4202 10:54:57.890931 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4203 10:54:57.891026 # ok 2473 Set Streaming SVE VL 1680
4204 10:54:57.891122 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4205 10:54:57.891217 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4206 10:54:57.891314 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4207 10:54:57.891410 # ok 2477 Set Streaming SVE VL 1696
4208 10:54:57.891505 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4209 10:54:57.891819 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4210 10:54:57.891932 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4211 10:54:57.892030 # ok 2481 Set Streaming SVE VL 1712
4212 10:54:57.892126 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4213 10:54:57.892223 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4214 10:54:57.892319 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4215 10:54:57.892415 # ok 2485 Set Streaming SVE VL 1728
4216 10:54:57.892511 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4217 10:54:57.892610 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4218 10:54:57.892702 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4219 10:54:57.892786 # ok 2489 Set Streaming SVE VL 1744
4220 10:54:57.892854 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4221 10:54:57.892941 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4222 10:54:57.893025 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4223 10:54:57.893113 # ok 2493 Set Streaming SVE VL 1760
4224 10:54:57.893197 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4225 10:54:57.893283 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4226 10:54:57.893367 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4227 10:54:57.893455 # ok 2497 Set Streaming SVE VL 1776
4228 10:54:57.893544 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4229 10:54:57.893627 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4230 10:54:57.893718 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4231 10:54:57.893798 # ok 2501 Set Streaming SVE VL 1792
4232 10:54:57.893876 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4233 10:54:57.893959 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4234 10:54:57.894068 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4235 10:54:57.894168 # ok 2505 Set Streaming SVE VL 1808
4236 10:54:57.894264 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4237 10:54:57.894377 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4238 10:54:57.894471 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4239 10:54:57.894559 # ok 2509 Set Streaming SVE VL 1824
4240 10:54:57.894640 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4241 10:54:57.894747 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4242 10:54:57.894846 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4243 10:54:57.894940 # ok 2513 Set Streaming SVE VL 1840
4244 10:54:57.895211 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4245 10:54:57.895299 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4246 10:54:57.895392 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4247 10:54:57.895476 # ok 2517 Set Streaming SVE VL 1856
4248 10:54:57.895586 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4249 10:54:57.895675 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4250 10:54:57.895764 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4251 10:54:57.895842 # ok 2521 Set Streaming SVE VL 1872
4252 10:54:57.895903 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4253 10:54:57.895967 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4254 10:54:57.896036 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4255 10:54:57.896122 # ok 2525 Set Streaming SVE VL 1888
4256 10:54:57.896191 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4257 10:54:57.896271 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4258 10:54:57.896348 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4259 10:54:57.896437 # ok 2529 Set Streaming SVE VL 1904
4260 10:54:57.896533 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4261 10:54:57.896622 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4262 10:54:57.896696 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4263 10:54:57.896787 # ok 2533 Set Streaming SVE VL 1920
4264 10:54:57.896862 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4265 10:54:57.896956 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4266 10:54:57.897028 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4267 10:54:57.897094 # ok 2537 Set Streaming SVE VL 1936
4268 10:54:57.897163 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4269 10:54:57.897234 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4270 10:54:57.897306 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4271 10:54:57.897369 # ok 2541 Set Streaming SVE VL 1952
4272 10:54:57.897435 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4273 10:54:57.897505 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4274 10:54:57.897567 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4275 10:54:57.897636 # ok 2545 Set Streaming SVE VL 1968
4276 10:54:57.897738 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4277 10:54:57.897816 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4278 10:54:57.897881 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4279 10:54:57.898150 # ok 2549 Set Streaming SVE VL 1984
4280 10:54:57.898263 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4281 10:54:57.898364 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4282 10:54:57.898468 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4283 10:54:57.898571 # ok 2553 Set Streaming SVE VL 2000
4284 10:54:57.898672 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4285 10:54:57.898773 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4286 10:54:57.898878 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4287 10:54:57.898978 # ok 2557 Set Streaming SVE VL 2016
4288 10:54:57.899077 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4289 10:54:57.899178 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4290 10:54:57.899275 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4291 10:54:57.899374 # ok 2561 Set Streaming SVE VL 2032
4292 10:54:57.899471 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4293 10:54:57.899570 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4294 10:54:57.899676 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4295 10:54:57.899780 # ok 2565 Set Streaming SVE VL 2048
4296 10:54:57.899877 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4297 10:54:57.899956 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4298 10:54:57.900018 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4299 10:54:57.900079 # ok 2569 Set Streaming SVE VL 2064
4300 10:54:57.900138 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4301 10:54:57.900198 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4302 10:54:57.900273 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4303 10:54:57.900338 # ok 2573 Set Streaming SVE VL 2080
4304 10:54:57.900399 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4305 10:54:57.900460 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4306 10:54:57.900521 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4307 10:54:57.900581 # ok 2577 Set Streaming SVE VL 2096
4308 10:54:57.900640 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4309 10:54:57.902007 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4310 10:54:57.902148 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4311 10:54:57.902281 # ok 2581 Set Streaming SVE VL 2112
4312 10:54:57.902430 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4313 10:54:57.902572 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4314 10:54:57.902702 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4315 10:54:57.902809 # ok 2585 Set Streaming SVE VL 2128
4316 10:54:57.902922 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4317 10:54:57.903016 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4318 10:54:57.903096 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4319 10:54:57.903185 # ok 2589 Set Streaming SVE VL 2144
4320 10:54:57.903290 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4321 10:54:57.903385 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4322 10:54:57.903688 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4323 10:54:57.903806 # ok 2593 Set Streaming SVE VL 2160
4324 10:54:57.903942 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4325 10:54:57.904049 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4326 10:54:57.904169 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4327 10:54:57.904276 # ok 2597 Set Streaming SVE VL 2176
4328 10:54:57.905034 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4329 10:54:57.905138 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4330 10:54:57.905417 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4331 10:54:57.905521 # ok 2601 Set Streaming SVE VL 2192
4332 10:54:57.905595 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4333 10:54:57.905721 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4334 10:54:57.905799 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4335 10:54:57.905885 # ok 2605 Set Streaming SVE VL 2208
4336 10:54:57.905954 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4337 10:54:57.906221 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4338 10:54:57.906336 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4339 10:54:57.906423 # ok 2609 Set Streaming SVE VL 2224
4340 10:54:57.906515 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4341 10:54:57.906802 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4342 10:54:57.906906 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4343 10:54:57.907027 # ok 2613 Set Streaming SVE VL 2240
4344 10:54:57.907110 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4345 10:54:57.907198 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4346 10:54:57.907477 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4347 10:54:57.907570 # ok 2617 Set Streaming SVE VL 2256
4348 10:54:57.907692 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4349 10:54:57.907801 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4350 10:54:57.907912 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4351 10:54:57.907999 # ok 2621 Set Streaming SVE VL 2272
4352 10:54:57.908094 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4353 10:54:57.908178 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4354 10:54:57.908474 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4355 10:54:57.908754 # ok 2625 Set Streaming SVE VL 2288
4356 10:54:57.908866 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4357 10:54:57.908971 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4358 10:54:57.909070 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4359 10:54:57.909153 # ok 2629 Set Streaming SVE VL 2304
4360 10:54:57.909254 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4361 10:54:57.909546 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4362 10:54:57.909664 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4363 10:54:57.909768 # ok 2633 Set Streaming SVE VL 2320
4364 10:54:57.909860 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4365 10:54:57.909949 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4366 10:54:57.910037 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4367 10:54:57.910146 # ok 2637 Set Streaming SVE VL 2336
4368 10:54:57.910247 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4369 10:54:57.910324 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4370 10:54:57.910399 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4371 10:54:57.910493 # ok 2641 Set Streaming SVE VL 2352
4372 10:54:57.910576 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4373 10:54:57.910675 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4374 10:54:57.910772 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4375 10:54:57.910856 # ok 2645 Set Streaming SVE VL 2368
4376 10:54:57.910972 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4377 10:54:57.911096 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4378 10:54:57.911501 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4379 10:54:57.911585 # ok 2649 Set Streaming SVE VL 2384
4380 10:54:57.911666 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4381 10:54:57.911787 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4382 10:54:57.911893 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4383 10:54:57.912013 # ok 2653 Set Streaming SVE VL 2400
4384 10:54:57.912118 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4385 10:54:57.912216 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4386 10:54:57.912325 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4387 10:54:57.912411 # ok 2657 Set Streaming SVE VL 2416
4388 10:54:57.912523 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4389 10:54:57.912820 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4390 10:54:57.912942 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4391 10:54:57.913046 # ok 2661 Set Streaming SVE VL 2432
4392 10:54:57.913162 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4393 10:54:57.913265 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4394 10:54:57.913372 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4395 10:54:57.913485 # ok 2665 Set Streaming SVE VL 2448
4396 10:54:57.913574 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4397 10:54:57.913686 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4398 10:54:57.913790 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4399 10:54:57.913899 # ok 2669 Set Streaming SVE VL 2464
4400 10:54:57.913988 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4401 10:54:57.914081 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4402 10:54:57.914178 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4403 10:54:57.914282 # ok 2673 Set Streaming SVE VL 2480
4404 10:54:57.914374 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4405 10:54:57.914478 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4406 10:54:57.914575 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4407 10:54:57.914699 # ok 2677 Set Streaming SVE VL 2496
4408 10:54:57.914796 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4409 10:54:57.914898 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4410 10:54:57.914990 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4411 10:54:57.915130 # ok 2681 Set Streaming SVE VL 2512
4412 10:54:57.915236 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4413 10:54:57.915325 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4414 10:54:57.915424 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4415 10:54:57.915511 # ok 2685 Set Streaming SVE VL 2528
4416 10:54:57.915597 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4417 10:54:57.915713 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4418 10:54:57.915808 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4419 10:54:57.915939 # ok 2689 Set Streaming SVE VL 2544
4420 10:54:57.916042 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4421 10:54:57.916162 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4422 10:54:57.916789 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4423 10:54:57.916904 # ok 2693 Set Streaming SVE VL 2560
4424 10:54:57.917024 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4425 10:54:57.917125 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4426 10:54:57.917241 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4427 10:54:57.917342 # ok 2697 Set Streaming SVE VL 2576
4428 10:54:57.917443 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4429 10:54:57.917538 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4430 10:54:57.917642 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4431 10:54:57.917781 # ok 2701 Set Streaming SVE VL 2592
4432 10:54:57.917878 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4433 10:54:57.917999 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4434 10:54:57.918076 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4435 10:54:57.918164 # ok 2705 Set Streaming SVE VL 2608
4436 10:54:57.918284 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4437 10:54:57.918388 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4438 10:54:57.918716 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4439 10:54:57.918820 # ok 2709 Set Streaming SVE VL 2624
4440 10:54:57.918941 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4441 10:54:57.919033 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4442 10:54:57.919146 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4443 10:54:57.919255 # ok 2713 Set Streaming SVE VL 2640
4444 10:54:57.919354 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4445 10:54:57.919662 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4446 10:54:57.919786 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4447 10:54:57.920129 # ok 2717 Set Streaming SVE VL 2656
4448 10:54:57.920231 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4449 10:54:57.920335 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4450 10:54:57.920451 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4451 10:54:57.920539 # ok 2721 Set Streaming SVE VL 2672
4452 10:54:57.920672 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4453 10:54:57.920799 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4454 10:54:57.921103 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4455 10:54:57.921209 # ok 2725 Set Streaming SVE VL 2688
4456 10:54:57.921297 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4457 10:54:57.921416 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4458 10:54:57.925320 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4459 10:54:57.925470 # ok 2729 Set Streaming SVE VL 2704
4460 10:54:57.925609 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4461 10:54:57.925732 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4462 10:54:57.925854 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4463 10:54:57.925977 # ok 2733 Set Streaming SVE VL 2720
4464 10:54:57.926091 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4465 10:54:57.926395 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4466 10:54:57.926505 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4467 10:54:57.926585 # ok 2737 Set Streaming SVE VL 2736
4468 10:54:57.926701 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4469 10:54:57.926801 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4470 10:54:57.927090 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4471 10:54:57.927175 # ok 2741 Set Streaming SVE VL 2752
4472 10:54:57.927273 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4473 10:54:57.927554 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4474 10:54:57.927647 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4475 10:54:57.929809 # ok 2745 Set Streaming SVE VL 2768
4476 10:54:57.929942 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4477 10:54:57.930062 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4478 10:54:57.930179 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4479 10:54:57.930282 # ok 2749 Set Streaming SVE VL 2784
4480 10:54:57.930381 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4481 10:54:57.930478 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4482 10:54:57.930575 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4483 10:54:57.930671 # ok 2753 Set Streaming SVE VL 2800
4484 10:54:57.930770 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4485 10:54:57.930867 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4486 10:54:57.930973 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4487 10:54:57.931078 # ok 2757 Set Streaming SVE VL 2816
4488 10:54:57.931181 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4489 10:54:57.931264 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4490 10:54:57.931360 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4491 10:54:57.931438 # ok 2761 Set Streaming SVE VL 2832
4492 10:54:57.931504 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4493 10:54:57.931778 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4494 10:54:57.931882 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4495 10:54:57.931992 # ok 2765 Set Streaming SVE VL 2848
4496 10:54:57.932089 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4497 10:54:57.932167 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4498 10:54:57.932237 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4499 10:54:57.932334 # ok 2769 Set Streaming SVE VL 2864
4500 10:54:57.932427 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4501 10:54:57.932533 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4502 10:54:57.932611 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4503 10:54:57.932695 # ok 2773 Set Streaming SVE VL 2880
4504 10:54:57.932805 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4505 10:54:57.932911 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4506 10:54:57.933009 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4507 10:54:57.933098 # ok 2777 Set Streaming SVE VL 2896
4508 10:54:57.933191 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4509 10:54:57.933276 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4510 10:54:57.933371 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4511 10:54:57.933456 # ok 2781 Set Streaming SVE VL 2912
4512 10:54:57.933526 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4513 10:54:57.933608 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4514 10:54:57.933730 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4515 10:54:57.933836 # ok 2785 Set Streaming SVE VL 2928
4516 10:54:57.933926 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4517 10:54:57.934016 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4518 10:54:57.934091 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4519 10:54:57.934183 # ok 2789 Set Streaming SVE VL 2944
4520 10:54:57.934279 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4521 10:54:57.934362 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4522 10:54:57.934440 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4523 10:54:57.934539 # ok 2793 Set Streaming SVE VL 2960
4524 10:54:57.934639 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4525 10:54:57.934726 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4526 10:54:57.934805 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4527 10:54:57.934896 # ok 2797 Set Streaming SVE VL 2976
4528 10:54:57.935166 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4529 10:54:57.935255 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4530 10:54:57.935375 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4531 10:54:57.935466 # ok 2801 Set Streaming SVE VL 2992
4532 10:54:57.935537 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4533 10:54:57.939477 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4534 10:54:57.939587 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4535 10:54:57.939679 # ok 2805 Set Streaming SVE VL 3008
4536 10:54:57.939762 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4537 10:54:57.939839 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4538 10:54:57.939926 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4539 10:54:57.940016 # ok 2809 Set Streaming SVE VL 3024
4540 10:54:57.940097 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4541 10:54:57.940195 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4542 10:54:57.940282 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4543 10:54:57.940372 # ok 2813 Set Streaming SVE VL 3040
4544 10:54:57.940458 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4545 10:54:57.940560 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4546 10:54:57.940660 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4547 10:54:57.940750 # ok 2817 Set Streaming SVE VL 3056
4548 10:54:57.940829 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4549 10:54:57.940907 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4550 10:54:57.941009 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4551 10:54:57.941112 # ok 2821 Set Streaming SVE VL 3072
4552 10:54:57.941213 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4553 10:54:57.941317 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4554 10:54:57.941417 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4555 10:54:57.941533 # ok 2825 Set Streaming SVE VL 3088
4556 10:54:57.941641 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4557 10:54:57.941744 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4558 10:54:57.941829 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4559 10:54:57.941910 # ok 2829 Set Streaming SVE VL 3104
4560 10:54:57.941995 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4561 10:54:57.942083 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4562 10:54:57.942189 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4563 10:54:57.942293 # ok 2833 Set Streaming SVE VL 3120
4564 10:54:57.942374 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4565 10:54:57.942450 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4566 10:54:57.942531 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4567 10:54:57.942610 # ok 2837 Set Streaming SVE VL 3136
4568 10:54:57.942888 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4569 10:54:57.942983 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4570 10:54:57.943056 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4571 10:54:57.943120 # ok 2841 Set Streaming SVE VL 3152
4572 10:54:57.943197 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4573 10:54:57.943273 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4574 10:54:57.943350 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4575 10:54:57.943426 # ok 2845 Set Streaming SVE VL 3168
4576 10:54:57.943502 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4577 10:54:57.943581 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4578 10:54:57.943644 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4579 10:54:57.943705 # ok 2849 Set Streaming SVE VL 3184
4580 10:54:57.943766 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4581 10:54:57.943827 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4582 10:54:57.943887 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4583 10:54:57.943948 # ok 2853 Set Streaming SVE VL 3200
4584 10:54:57.944011 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4585 10:54:57.944071 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4586 10:54:57.944131 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4587 10:54:57.944190 # ok 2857 Set Streaming SVE VL 3216
4588 10:54:57.944249 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4589 10:54:57.944308 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4590 10:54:57.944367 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4591 10:54:57.944425 # ok 2861 Set Streaming SVE VL 3232
4592 10:54:57.944484 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4593 10:54:57.944543 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4594 10:54:57.944601 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4595 10:54:57.944660 # ok 2865 Set Streaming SVE VL 3248
4596 10:54:57.944719 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4597 10:54:57.944792 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4598 10:54:57.944855 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4599 10:54:57.944914 # ok 2869 Set Streaming SVE VL 3264
4600 10:54:57.944974 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4601 10:54:57.945037 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4602 10:54:57.945099 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4603 10:54:57.945158 # ok 2873 Set Streaming SVE VL 3280
4604 10:54:57.945399 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4605 10:54:57.945466 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4606 10:54:57.945526 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4607 10:54:57.945586 # ok 2877 Set Streaming SVE VL 3296
4608 10:54:57.974619 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4609 10:54:57.974833 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4610 10:54:57.974936 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4611 10:54:57.975029 # ok 2881 Set Streaming SVE VL 3312
4612 10:54:57.975327 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4613 10:54:57.975442 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4614 10:54:57.975551 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4615 10:54:57.975641 # ok 2885 Set Streaming SVE VL 3328
4616 10:54:57.975748 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4617 10:54:57.975856 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4618 10:54:57.976165 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4619 10:54:57.978038 # ok 2889 Set Streaming SVE VL 3344
4620 10:54:57.978335 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4621 10:54:57.978447 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4622 10:54:57.978557 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4623 10:54:57.978670 # ok 2893 Set Streaming SVE VL 3360
4624 10:54:57.978785 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4625 10:54:57.979070 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4626 10:54:57.979181 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4627 10:54:57.979290 # ok 2897 Set Streaming SVE VL 3376
4628 10:54:57.979397 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4629 10:54:57.979503 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4630 10:54:57.979819 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4631 10:54:57.979969 # ok 2901 Set Streaming SVE VL 3392
4632 10:54:57.980081 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4633 10:54:57.980186 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4634 10:54:57.981333 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4635 10:54:57.981464 # ok 2905 Set Streaming SVE VL 3408
4636 10:54:57.981578 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4637 10:54:57.981969 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4638 10:54:57.982182 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4639 10:54:57.982368 # ok 2909 Set Streaming SVE VL 3424
4640 10:54:57.982576 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4641 10:54:57.982763 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4642 10:54:57.982950 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4643 10:54:57.983125 # ok 2913 Set Streaming SVE VL 3440
4644 10:54:57.983338 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4645 10:54:57.983582 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4646 10:54:57.983774 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4647 10:54:57.983963 # ok 2917 Set Streaming SVE VL 3456
4648 10:54:57.984133 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4649 10:54:57.984294 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4650 10:54:57.984419 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4651 10:54:57.984537 # ok 2921 Set Streaming SVE VL 3472
4652 10:54:57.984654 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4653 10:54:57.993857 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4654 10:54:57.994257 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4655 10:54:57.994401 # ok 2925 Set Streaming SVE VL 3488
4656 10:54:57.994558 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4657 10:54:57.994747 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4658 10:54:57.994908 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4659 10:54:57.995052 # ok 2929 Set Streaming SVE VL 3504
4660 10:54:57.995235 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4661 10:54:57.995386 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4662 10:54:57.995525 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4663 10:54:57.995673 # ok 2933 Set Streaming SVE VL 3520
4664 10:54:57.995837 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4665 10:54:57.995989 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4666 10:54:57.996186 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4667 10:54:57.996354 # ok 2937 Set Streaming SVE VL 3536
4668 10:54:57.996512 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4669 10:54:57.996665 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4670 10:54:57.996815 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4671 10:54:58.002235 # ok 2941 Set Streaming SVE VL 3552
4672 10:54:58.002651 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4673 10:54:58.002742 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4674 10:54:58.002820 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4675 10:54:58.002886 # ok 2945 Set Streaming SVE VL 3568
4676 10:54:58.003001 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4677 10:54:58.003103 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4678 10:54:58.003237 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4679 10:54:58.003355 # ok 2949 Set Streaming SVE VL 3584
4680 10:54:58.003651 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4681 10:54:58.003756 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4682 10:54:58.004080 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4683 10:54:58.004195 # ok 2953 Set Streaming SVE VL 3600
4684 10:54:58.005724 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4685 10:54:58.010290 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4686 10:54:58.010585 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4687 10:54:58.010681 # ok 2957 Set Streaming SVE VL 3616
4688 10:54:58.010764 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4689 10:54:58.010844 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4690 10:54:58.011109 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4691 10:54:58.011193 # ok 2961 Set Streaming SVE VL 3632
4692 10:54:58.011293 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4693 10:54:58.011392 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4694 10:54:58.011695 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4695 10:54:58.011792 # ok 2965 Set Streaming SVE VL 3648
4696 10:54:58.011861 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4697 10:54:58.011940 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4698 10:54:58.012018 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4699 10:54:58.012140 # ok 2969 Set Streaming SVE VL 3664
4700 10:54:58.017286 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4701 10:54:58.017605 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4702 10:54:58.017733 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4703 10:54:58.018042 # ok 2973 Set Streaming SVE VL 3680
4704 10:54:58.018162 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4705 10:54:58.018250 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4706 10:54:58.018353 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4707 10:54:58.018443 # ok 2977 Set Streaming SVE VL 3696
4708 10:54:58.018543 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4709 10:54:58.018640 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4710 10:54:58.018758 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4711 10:54:58.018875 # ok 2981 Set Streaming SVE VL 3712
4712 10:54:58.018985 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4713 10:54:58.019303 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4714 10:54:58.019418 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4715 10:54:58.019519 # ok 2985 Set Streaming SVE VL 3728
4716 10:54:58.019617 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4717 10:54:58.019894 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4718 10:54:58.020002 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4719 10:54:58.020118 # ok 2989 Set Streaming SVE VL 3744
4720 10:54:58.023378 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4721 10:54:58.023663 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4722 10:54:58.023780 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4723 10:54:58.023885 # ok 2993 Set Streaming SVE VL 3760
4724 10:54:58.024028 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4725 10:54:58.025396 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4726 10:54:58.025696 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4727 10:54:58.025798 # ok 2997 Set Streaming SVE VL 3776
4728 10:54:58.025881 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4729 10:54:58.025987 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4730 10:54:58.026113 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4731 10:54:58.026214 # ok 3001 Set Streaming SVE VL 3792
4732 10:54:58.026311 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4733 10:54:58.026409 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4734 10:54:58.026537 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4735 10:54:58.026637 # ok 3005 Set Streaming SVE VL 3808
4736 10:54:58.026760 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4737 10:54:58.026868 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4738 10:54:58.027164 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4739 10:54:58.027279 # ok 3009 Set Streaming SVE VL 3824
4740 10:54:58.027401 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4741 10:54:58.027501 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4742 10:54:58.027616 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4743 10:54:58.027732 # ok 3013 Set Streaming SVE VL 3840
4744 10:54:58.027846 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4745 10:54:58.027972 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4746 10:54:58.028091 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4747 10:54:58.035733 # ok 3017 Set Streaming SVE VL 3856
4748 10:54:58.035878 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4749 10:54:58.036001 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4750 10:54:58.036115 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4751 10:54:58.046043 # ok 3021 Set Streaming SVE VL 3872
4752 10:54:58.046367 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4753 10:54:58.046473 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4754 10:54:58.046748 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4755 10:54:58.046820 # ok 3025 Set Streaming SVE VL 3888
4756 10:54:58.046895 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4757 10:54:58.055136 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4758 10:54:58.055425 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4759 10:54:58.055512 # ok 3029 Set Streaming SVE VL 3904
4760 10:54:58.055607 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4761 10:54:58.056096 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4762 10:54:58.056222 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4763 10:54:58.056323 # ok 3033 Set Streaming SVE VL 3920
4764 10:54:58.056619 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4765 10:54:58.057235 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4766 10:54:58.057571 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4767 10:54:58.057690 # ok 3037 Set Streaming SVE VL 3936
4768 10:54:58.057807 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4769 10:54:58.058210 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4770 10:54:58.058340 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4771 10:54:58.058434 # ok 3041 Set Streaming SVE VL 3952
4772 10:54:58.058519 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4773 10:54:58.058610 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4774 10:54:58.060475 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4775 10:54:58.060562 # ok 3045 Set Streaming SVE VL 3968
4776 10:54:58.060627 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4777 10:54:58.060689 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4778 10:54:58.060750 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4779 10:54:58.060811 # ok 3049 Set Streaming SVE VL 3984
4780 10:54:58.060872 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4781 10:54:58.060932 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4782 10:54:58.060992 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4783 10:54:58.061052 # ok 3053 Set Streaming SVE VL 4000
4784 10:54:58.061112 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4785 10:54:58.061172 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4786 10:54:58.065948 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4787 10:54:58.066249 # ok 3057 Set Streaming SVE VL 4016
4788 10:54:58.066356 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4789 10:54:58.066474 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4790 10:54:58.066784 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4791 10:54:58.066874 # ok 3061 Set Streaming SVE VL 4032
4792 10:54:58.066948 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4793 10:54:58.067042 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4794 10:54:58.067113 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4795 10:54:58.067228 # ok 3065 Set Streaming SVE VL 4048
4796 10:54:58.067539 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4797 10:54:58.067643 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4798 10:54:58.067731 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4799 10:54:58.067821 # ok 3069 Set Streaming SVE VL 4064
4800 10:54:58.068105 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4801 10:54:58.073638 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4802 10:54:58.073973 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4803 10:54:58.074202 # ok 3073 Set Streaming SVE VL 4080
4804 10:54:58.074381 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4805 10:54:58.074581 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4806 10:54:58.074749 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4807 10:54:58.074909 # ok 3077 Set Streaming SVE VL 4096
4808 10:54:58.075045 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4809 10:54:58.075198 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4810 10:54:58.075332 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4811 10:54:58.075483 # ok 3081 Set Streaming SVE VL 4112
4812 10:54:58.075620 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4813 10:54:58.075762 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4814 10:54:58.075902 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4815 10:54:58.076022 # ok 3085 Set Streaming SVE VL 4128
4816 10:54:58.076156 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4817 10:54:58.081734 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4818 10:54:58.082120 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4819 10:54:58.082229 # ok 3089 Set Streaming SVE VL 4144
4820 10:54:58.082511 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4821 10:54:58.082838 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4822 10:54:58.082972 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4823 10:54:58.083274 # ok 3093 Set Streaming SVE VL 4160
4824 10:54:58.083578 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4825 10:54:58.083687 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4826 10:54:58.084003 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4827 10:54:58.084115 # ok 3097 Set Streaming SVE VL 4176
4828 10:54:58.089296 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4829 10:54:58.089688 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4830 10:54:58.089857 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4831 10:54:58.090012 # ok 3101 Set Streaming SVE VL 4192
4832 10:54:58.090180 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4833 10:54:58.090355 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4834 10:54:58.090552 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4835 10:54:58.090736 # ok 3105 Set Streaming SVE VL 4208
4836 10:54:58.090944 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4837 10:54:58.091171 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4838 10:54:58.091367 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4839 10:54:58.091583 # ok 3109 Set Streaming SVE VL 4224
4840 10:54:58.091787 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4841 10:54:58.091979 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4842 10:54:58.092209 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4843 10:54:58.092408 # ok 3113 Set Streaming SVE VL 4240
4844 10:54:58.092599 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4845 10:54:58.092788 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4846 10:54:58.092979 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4847 10:54:58.093167 # ok 3117 Set Streaming SVE VL 4256
4848 10:54:58.093359 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4849 10:54:58.098007 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4850 10:54:58.098459 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4851 10:54:58.098650 # ok 3121 Set Streaming SVE VL 4272
4852 10:54:58.098860 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4853 10:54:58.099061 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4854 10:54:58.099231 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4855 10:54:58.099396 # ok 3125 Set Streaming SVE VL 4288
4856 10:54:58.099564 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4857 10:54:58.099756 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4858 10:54:58.099954 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4859 10:54:58.100156 # ok 3129 Set Streaming SVE VL 4304
4860 10:54:58.100332 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4861 10:54:58.100497 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4862 10:54:58.100714 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4863 10:54:58.100901 # ok 3133 Set Streaming SVE VL 4320
4864 10:54:58.101043 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4865 10:54:58.103743 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4866 10:54:58.103985 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4867 10:54:58.104191 # ok 3137 Set Streaming SVE VL 4336
4868 10:54:58.104365 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4869 10:54:58.107798 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4870 10:54:58.108251 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4871 10:54:58.108459 # ok 3141 Set Streaming SVE VL 4352
4872 10:54:58.115040 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4873 10:54:58.115504 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4874 10:54:58.115657 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4875 10:54:58.115813 # ok 3145 Set Streaming SVE VL 4368
4876 10:54:58.115972 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4877 10:54:58.116215 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4878 10:54:58.116363 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4879 10:54:58.116520 # ok 3149 Set Streaming SVE VL 4384
4880 10:54:58.116657 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4881 10:54:58.117922 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4882 10:54:58.118224 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4883 10:54:58.118348 # ok 3153 Set Streaming SVE VL 4400
4884 10:54:58.118440 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4885 10:54:58.118544 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4886 10:54:58.118648 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4887 10:54:58.118755 # ok 3157 Set Streaming SVE VL 4416
4888 10:54:58.118880 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4889 10:54:58.119172 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4890 10:54:58.119490 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4891 10:54:58.119647 # ok 3161 Set Streaming SVE VL 4432
4892 10:54:58.119750 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4893 10:54:58.119902 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4894 10:54:58.120048 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4895 10:54:58.120187 # ok 3165 Set Streaming SVE VL 4448
4896 10:54:58.120323 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4897 10:54:58.125948 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4898 10:54:58.126275 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4899 10:54:58.126769 # ok 3169 Set Streaming SVE VL 4464
4900 10:54:58.126858 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4901 10:54:58.126958 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4902 10:54:58.127057 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4903 10:54:58.127349 # ok 3173 Set Streaming SVE VL 4480
4904 10:54:58.127437 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4905 10:54:58.127529 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4906 10:54:58.127607 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4907 10:54:58.137832 # ok 3177 Set Streaming SVE VL 4496
4908 10:54:58.138226 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4909 10:54:58.138337 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4910 10:54:58.138439 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4911 10:54:58.138523 # ok 3181 Set Streaming SVE VL 4512
4912 10:54:58.138617 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4913 10:54:58.138700 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4914 10:54:58.138792 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4915 10:54:58.138886 # ok 3185 Set Streaming SVE VL 4528
4916 10:54:58.138979 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4917 10:54:58.139273 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4918 10:54:58.139380 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4919 10:54:58.139475 # ok 3189 Set Streaming SVE VL 4544
4920 10:54:58.139572 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4921 10:54:58.139862 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4922 10:54:58.139978 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4923 10:54:58.140078 # ok 3193 Set Streaming SVE VL 4560
4924 10:54:58.150351 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4925 10:54:58.150798 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4926 10:54:58.150915 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4927 10:54:58.151015 # ok 3197 Set Streaming SVE VL 4576
4928 10:54:58.151100 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4929 10:54:58.151200 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4930 10:54:58.151288 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4931 10:54:58.151368 # ok 3201 Set Streaming SVE VL 4592
4932 10:54:58.151463 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4933 10:54:58.151544 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4934 10:54:58.151640 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4935 10:54:58.151736 # ok 3205 Set Streaming SVE VL 4608
4936 10:54:58.151816 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4937 10:54:58.151906 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4938 10:54:58.151993 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4939 10:54:58.152086 # ok 3209 Set Streaming SVE VL 4624
4940 10:54:58.152167 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4941 10:54:58.152681 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4942 10:54:58.152793 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4943 10:54:58.152903 # ok 3213 Set Streaming SVE VL 4640
4944 10:54:58.170168 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4945 10:54:58.170464 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4946 10:54:58.170637 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4947 10:54:58.171090 # ok 3217 Set Streaming SVE VL 4656
4948 10:54:58.171294 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4949 10:54:58.171479 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4950 10:54:58.171632 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4951 10:54:58.171797 # ok 3221 Set Streaming SVE VL 4672
4952 10:54:58.171984 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4953 10:54:58.172159 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4954 10:54:58.172318 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4955 10:54:58.172441 # ok 3225 Set Streaming SVE VL 4688
4956 10:54:58.172555 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4957 10:54:58.172669 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4958 10:54:58.172783 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4959 10:54:58.172896 # ok 3229 Set Streaming SVE VL 4704
4960 10:54:58.173008 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4961 10:54:58.181319 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4962 10:54:58.181716 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4963 10:54:58.181822 # ok 3233 Set Streaming SVE VL 4720
4964 10:54:58.181908 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4965 10:54:58.182006 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4966 10:54:58.182104 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4967 10:54:58.182202 # ok 3237 Set Streaming SVE VL 4736
4968 10:54:58.182519 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4969 10:54:58.182624 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4970 10:54:58.182722 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4971 10:54:58.183118 # ok 3241 Set Streaming SVE VL 4752
4972 10:54:58.183222 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4973 10:54:58.183306 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4974 10:54:58.183402 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4975 10:54:58.183487 # ok 3245 Set Streaming SVE VL 4768
4976 10:54:58.183581 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4977 10:54:58.184001 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4978 10:54:58.184111 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4979 10:54:58.184195 # ok 3249 Set Streaming SVE VL 4784
4980 10:54:58.184515 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4981 10:54:58.184792 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4982 10:54:58.201754 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4983 10:54:58.202105 # ok 3253 Set Streaming SVE VL 4800
4984 10:54:58.202300 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4985 10:54:58.202507 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4986 10:54:58.202687 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4987 10:54:58.202865 # ok 3257 Set Streaming SVE VL 4816
4988 10:54:58.203035 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4989 10:54:58.203256 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4990 10:54:58.203483 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4991 10:54:58.203697 # ok 3261 Set Streaming SVE VL 4832
4992 10:54:58.203918 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4993 10:54:58.204161 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4994 10:54:58.204321 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4995 10:54:58.204468 # ok 3265 Set Streaming SVE VL 4848
4996 10:54:58.204612 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4997 10:54:58.204796 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4998 10:54:58.204936 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4999 10:54:58.205115 # ok 3269 Set Streaming SVE VL 4864
5000 10:54:58.205320 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
5001 10:54:58.205496 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
5002 10:54:58.205708 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5003 10:54:58.205887 # ok 3273 Set Streaming SVE VL 4880
5004 10:54:58.214965 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5005 10:54:58.215372 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5006 10:54:58.215515 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5007 10:54:58.215638 # ok 3277 Set Streaming SVE VL 4896
5008 10:54:58.215738 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5009 10:54:58.215853 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5010 10:54:58.215951 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5011 10:54:58.216046 # ok 3281 Set Streaming SVE VL 4912
5012 10:54:58.216362 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5013 10:54:58.216479 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5014 10:54:58.216583 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5015 10:54:58.216678 # ok 3285 Set Streaming SVE VL 4928
5016 10:54:58.216790 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5017 10:54:58.225888 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5018 10:54:58.226275 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5019 10:54:58.226422 # ok 3289 Set Streaming SVE VL 4944
5020 10:54:58.227735 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5021 10:54:58.227904 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5022 10:54:58.228057 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5023 10:54:58.228207 # ok 3293 Set Streaming SVE VL 4960
5024 10:54:58.228355 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5025 10:54:58.228485 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5026 10:54:58.228581 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5027 10:54:58.228695 # ok 3297 Set Streaming SVE VL 4976
5028 10:54:58.228790 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5029 10:54:58.228881 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5030 10:54:58.228971 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5031 10:54:58.229061 # ok 3301 Set Streaming SVE VL 4992
5032 10:54:58.229151 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5033 10:54:58.229438 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5034 10:54:58.229539 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5035 10:54:58.229630 # ok 3305 Set Streaming SVE VL 5008
5036 10:54:58.242307 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5037 10:54:58.242720 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5038 10:54:58.242841 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5039 10:54:58.242936 # ok 3309 Set Streaming SVE VL 5024
5040 10:54:58.243045 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5041 10:54:58.243160 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5042 10:54:58.243284 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5043 10:54:58.243390 # ok 3313 Set Streaming SVE VL 5040
5044 10:54:58.243527 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5045 10:54:58.243644 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5046 10:54:58.243815 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5047 10:54:58.243941 # ok 3317 Set Streaming SVE VL 5056
5048 10:54:58.244055 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5049 10:54:58.244226 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5050 10:54:58.247382 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5051 10:54:58.247767 # ok 3321 Set Streaming SVE VL 5072
5052 10:54:58.247910 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5053 10:54:58.248024 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5054 10:54:58.248121 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5055 10:54:58.248230 # ok 3325 Set Streaming SVE VL 5088
5056 10:54:58.248324 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5057 10:54:58.255699 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5058 10:54:58.255997 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5059 10:54:58.256096 # ok 3329 Set Streaming SVE VL 5104
5060 10:54:58.256171 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5061 10:54:58.263023 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5062 10:54:58.263314 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5063 10:54:58.263421 # ok 3333 Set Streaming SVE VL 5120
5064 10:54:58.263525 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5065 10:54:58.263624 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5066 10:54:58.263737 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5067 10:54:58.263839 # ok 3337 Set Streaming SVE VL 5136
5068 10:54:58.263950 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5069 10:54:58.264045 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5070 10:54:58.265137 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5071 10:54:58.265410 # ok 3341 Set Streaming SVE VL 5152
5072 10:54:58.265493 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5073 10:54:58.265576 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5074 10:54:58.265702 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5075 10:54:58.265806 # ok 3345 Set Streaming SVE VL 5168
5076 10:54:58.265892 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5077 10:54:58.266207 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5078 10:54:58.266314 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5079 10:54:58.266416 # ok 3349 Set Streaming SVE VL 5184
5080 10:54:58.266502 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5081 10:54:58.266605 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5082 10:54:58.266887 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5083 10:54:58.266977 # ok 3353 Set Streaming SVE VL 5200
5084 10:54:58.267074 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5085 10:54:58.267171 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5086 10:54:58.267460 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5087 10:54:58.267574 # ok 3357 Set Streaming SVE VL 5216
5088 10:54:58.267666 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5089 10:54:58.267758 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5090 10:54:58.267851 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5091 10:54:58.267953 # ok 3361 Set Streaming SVE VL 5232
5092 10:54:58.268051 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5093 10:54:58.268207 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5094 10:54:58.273830 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5095 10:54:58.274214 # ok 3365 Set Streaming SVE VL 5248
5096 10:54:58.274324 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5097 10:54:58.274432 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5098 10:54:58.274559 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5099 10:54:58.274668 # ok 3369 Set Streaming SVE VL 5264
5100 10:54:58.275059 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5101 10:54:58.275153 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5102 10:54:58.275265 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5103 10:54:58.275366 # ok 3373 Set Streaming SVE VL 5280
5104 10:54:58.275658 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5105 10:54:58.275773 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5106 10:54:58.275872 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5107 10:54:58.275975 # ok 3377 Set Streaming SVE VL 5296
5108 10:54:58.276068 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5109 10:54:58.276169 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5110 10:54:58.281746 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5111 10:54:58.282098 # ok 3381 Set Streaming SVE VL 5312
5112 10:54:58.282196 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5113 10:54:58.282320 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5114 10:54:58.282636 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5115 10:54:58.282761 # ok 3385 Set Streaming SVE VL 5328
5116 10:54:58.282863 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5117 10:54:58.282975 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5118 10:54:58.283074 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5119 10:54:58.283157 # ok 3389 Set Streaming SVE VL 5344
5120 10:54:58.283239 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5121 10:54:58.283322 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5122 10:54:58.283585 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5123 10:54:58.283676 # ok 3393 Set Streaming SVE VL 5360
5124 10:54:58.283743 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5125 10:54:58.283819 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5126 10:54:58.284082 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5127 10:54:58.284169 # ok 3397 Set Streaming SVE VL 5376
5128 10:54:58.289942 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5129 10:54:58.290228 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5130 10:54:58.290339 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5131 10:54:58.290420 # ok 3401 Set Streaming SVE VL 5392
5132 10:54:58.290710 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5133 10:54:58.290812 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5134 10:54:58.291064 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5135 10:54:58.291145 # ok 3405 Set Streaming SVE VL 5408
5136 10:54:58.291251 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5137 10:54:58.291545 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5138 10:54:58.291641 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5139 10:54:58.291712 # ok 3409 Set Streaming SVE VL 5424
5140 10:54:58.291785 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5141 10:54:58.292072 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5142 10:54:58.292576 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5143 10:54:58.292830 # ok 3413 Set Streaming SVE VL 5440
5144 10:54:58.292909 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5145 10:54:58.293161 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5146 10:54:58.293229 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5147 10:54:58.293303 # ok 3417 Set Streaming SVE VL 5456
5148 10:54:58.293376 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5149 10:54:58.293636 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5150 10:54:58.293725 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5151 10:54:58.293978 # ok 3421 Set Streaming SVE VL 5472
5152 10:54:58.294045 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5153 10:54:58.294292 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5154 10:54:58.294358 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5155 10:54:58.294432 # ok 3425 Set Streaming SVE VL 5488
5156 10:54:58.294682 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5157 10:54:58.294760 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5158 10:54:58.295012 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5159 10:54:58.295089 # ok 3429 Set Streaming SVE VL 5504
5160 10:54:58.295162 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5161 10:54:58.295410 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5162 10:54:58.295487 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5163 10:54:58.295565 # ok 3433 Set Streaming SVE VL 5520
5164 10:54:58.295819 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5165 10:54:58.295928 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5166 10:54:58.296040 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5167 10:54:58.303809 # ok 3437 Set Streaming SVE VL 5536
5168 10:54:58.304163 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5169 10:54:58.309010 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5170 10:54:58.309371 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5171 10:54:58.309476 # ok 3441 Set Streaming SVE VL 5552
5172 10:54:58.309564 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5173 10:54:58.309680 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5174 10:54:58.309785 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5175 10:54:58.309886 # ok 3445 Set Streaming SVE VL 5568
5176 10:54:58.310186 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5177 10:54:58.310289 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5178 10:54:58.310393 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5179 10:54:58.310496 # ok 3449 Set Streaming SVE VL 5584
5180 10:54:58.310802 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5181 10:54:58.310918 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5182 10:54:58.311025 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5183 10:54:58.311125 # ok 3453 Set Streaming SVE VL 5600
5184 10:54:58.311428 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5185 10:54:58.311545 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5186 10:54:58.311645 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5187 10:54:58.311968 # ok 3457 Set Streaming SVE VL 5616
5188 10:54:58.312092 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5189 10:54:58.315724 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5190 10:54:58.316141 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5191 10:54:58.316249 # ok 3461 Set Streaming SVE VL 5632
5192 10:54:58.326160 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5193 10:54:58.326590 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5194 10:54:58.326710 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5195 10:54:58.326815 # ok 3465 Set Streaming SVE VL 5648
5196 10:54:58.326912 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5197 10:54:58.327029 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5198 10:54:58.327137 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5199 10:54:58.327232 # ok 3469 Set Streaming SVE VL 5664
5200 10:54:58.327352 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5201 10:54:58.327444 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5202 10:54:58.327560 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5203 10:54:58.327671 # ok 3473 Set Streaming SVE VL 5680
5204 10:54:58.327782 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5205 10:54:58.327893 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5206 10:54:58.334469 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5207 10:54:58.334684 # ok 3477 Set Streaming SVE VL 5696
5208 10:54:58.334802 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5209 10:54:58.334927 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5210 10:54:58.335039 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5211 10:54:58.335173 # ok 3481 Set Streaming SVE VL 5712
5212 10:54:58.335281 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5213 10:54:58.335407 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5214 10:54:58.335535 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5215 10:54:58.335669 # ok 3485 Set Streaming SVE VL 5728
5216 10:54:58.336125 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5217 10:54:58.336212 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5218 10:54:58.336711 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5219 10:54:58.337051 # ok 3489 Set Streaming SVE VL 5744
5220 10:54:58.337149 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5221 10:54:58.337268 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5222 10:54:58.337378 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5223 10:54:58.337511 # ok 3493 Set Streaming SVE VL 5760
5224 10:54:58.337623 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5225 10:54:58.337936 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5226 10:54:58.338091 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5227 10:54:58.338217 # ok 3497 Set Streaming SVE VL 5776
5228 10:54:58.338302 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5229 10:54:58.338395 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5230 10:54:58.338482 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5231 10:54:58.338569 # ok 3501 Set Streaming SVE VL 5792
5232 10:54:58.338661 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5233 10:54:58.338934 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5234 10:54:58.339027 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5235 10:54:58.339102 # ok 3505 Set Streaming SVE VL 5808
5236 10:54:58.339192 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5237 10:54:58.339280 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5238 10:54:58.339544 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5239 10:54:58.339643 # ok 3509 Set Streaming SVE VL 5824
5240 10:54:58.339743 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5241 10:54:58.339844 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5242 10:54:58.339960 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5243 10:54:58.340046 # ok 3513 Set Streaming SVE VL 5840
5244 10:54:58.340135 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5245 10:54:58.340226 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5246 10:54:58.340318 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5247 10:54:58.340409 # ok 3517 Set Streaming SVE VL 5856
5248 10:54:58.340499 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5249 10:54:58.340587 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5250 10:54:58.340678 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5251 10:54:58.340768 # ok 3521 Set Streaming SVE VL 5872
5252 10:54:58.340856 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5253 10:54:58.340933 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5254 10:54:58.341022 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5255 10:54:58.341123 # ok 3525 Set Streaming SVE VL 5888
5256 10:54:58.341241 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5257 10:54:58.349067 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5258 10:54:58.349271 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5259 10:54:58.349380 # ok 3529 Set Streaming SVE VL 5904
5260 10:54:58.349486 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5261 10:54:58.349589 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5262 10:54:58.349722 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5263 10:54:58.349816 # ok 3533 Set Streaming SVE VL 5920
5264 10:54:58.349914 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5265 10:54:58.350036 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5266 10:54:58.350123 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5267 10:54:58.350197 # ok 3537 Set Streaming SVE VL 5936
5268 10:54:58.350322 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5269 10:54:58.350428 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5270 10:54:58.350508 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5271 10:54:58.350818 # ok 3541 Set Streaming SVE VL 5952
5272 10:54:58.350922 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5273 10:54:58.351009 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5274 10:54:58.351103 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5275 10:54:58.351188 # ok 3545 Set Streaming SVE VL 5968
5276 10:54:58.351266 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5277 10:54:58.351358 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5278 10:54:58.351453 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5279 10:54:58.351528 # ok 3549 Set Streaming SVE VL 5984
5280 10:54:58.351617 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5281 10:54:58.351738 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5282 10:54:58.352052 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5283 10:54:58.352136 # ok 3553 Set Streaming SVE VL 6000
5284 10:54:58.352202 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5285 10:54:58.361426 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5286 10:54:58.361842 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5287 10:54:58.361947 # ok 3557 Set Streaming SVE VL 6016
5288 10:54:58.362035 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5289 10:54:58.362137 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5290 10:54:58.362241 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5291 10:54:58.362342 # ok 3561 Set Streaming SVE VL 6032
5292 10:54:58.362640 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5293 10:54:58.362744 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5294 10:54:58.362850 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5295 10:54:58.362938 # ok 3565 Set Streaming SVE VL 6048
5296 10:54:58.363264 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5297 10:54:58.363370 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5298 10:54:58.363473 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5299 10:54:58.363573 # ok 3569 Set Streaming SVE VL 6064
5300 10:54:58.363892 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5301 10:54:58.364212 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5302 10:54:58.371212 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5303 10:54:58.371708 # ok 3573 Set Streaming SVE VL 6080
5304 10:54:58.371821 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5305 10:54:58.371907 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5306 10:54:58.371988 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5307 10:54:58.372083 # ok 3577 Set Streaming SVE VL 6096
5308 10:54:58.372166 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5309 10:54:58.374867 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5310 10:54:58.375267 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5311 10:54:58.375373 # ok 3581 Set Streaming SVE VL 6112
5312 10:54:58.375458 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5313 10:54:58.375556 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5314 10:54:58.375641 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5315 10:54:58.375737 # ok 3585 Set Streaming SVE VL 6128
5316 10:54:58.375823 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5317 10:54:58.375918 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5318 10:54:58.381275 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5319 10:54:58.381485 # ok 3589 Set Streaming SVE VL 6144
5320 10:54:58.381573 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5321 10:54:58.381679 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5322 10:54:58.381766 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5323 10:54:58.381850 # ok 3593 Set Streaming SVE VL 6160
5324 10:54:58.381945 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5325 10:54:58.382026 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5326 10:54:58.382117 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5327 10:54:58.382209 # ok 3597 Set Streaming SVE VL 6176
5328 10:54:58.382300 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5329 10:54:58.382600 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5330 10:54:58.382732 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5331 10:54:58.382831 # ok 3601 Set Streaming SVE VL 6192
5332 10:54:58.382914 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5333 10:54:58.383208 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5334 10:54:58.383302 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5335 10:54:58.383375 # ok 3605 Set Streaming SVE VL 6208
5336 10:54:58.383465 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5337 10:54:58.383561 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5338 10:54:58.383833 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5339 10:54:58.383959 # ok 3609 Set Streaming SVE VL 6224
5340 10:54:58.384047 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5341 10:54:58.393161 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5342 10:54:58.393566 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5343 10:54:58.393677 # ok 3613 Set Streaming SVE VL 6240
5344 10:54:58.393778 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5345 10:54:58.393888 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5346 10:54:58.393965 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5347 10:54:58.394057 # ok 3617 Set Streaming SVE VL 6256
5348 10:54:58.394146 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5349 10:54:58.394392 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5350 10:54:58.394526 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5351 10:54:58.394649 # ok 3621 Set Streaming SVE VL 6272
5352 10:54:58.394784 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5353 10:54:58.394911 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5354 10:54:58.395209 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5355 10:54:58.395292 # ok 3625 Set Streaming SVE VL 6288
5356 10:54:58.409818 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5357 10:54:58.410045 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5358 10:54:58.410140 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5359 10:54:58.410241 # ok 3629 Set Streaming SVE VL 6304
5360 10:54:58.410342 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5361 10:54:58.410448 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5362 10:54:58.410746 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5363 10:54:58.410867 # ok 3633 Set Streaming SVE VL 6320
5364 10:54:58.411168 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5365 10:54:58.411272 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5366 10:54:58.411378 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5367 10:54:58.411479 # ok 3637 Set Streaming SVE VL 6336
5368 10:54:58.411812 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5369 10:54:58.411952 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5370 10:54:58.422804 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5371 10:54:58.423048 # ok 3641 Set Streaming SVE VL 6352
5372 10:54:58.423158 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5373 10:54:58.423264 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5374 10:54:58.423400 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5375 10:54:58.423520 # ok 3645 Set Streaming SVE VL 6368
5376 10:54:58.423631 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5377 10:54:58.423742 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5378 10:54:58.423854 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5379 10:54:58.423963 # ok 3649 Set Streaming SVE VL 6384
5380 10:54:58.424072 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5381 10:54:58.424418 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5382 10:54:58.424545 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5383 10:54:58.424679 # ok 3653 Set Streaming SVE VL 6400
5384 10:54:58.424791 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5385 10:54:58.424901 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5386 10:54:58.425013 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5387 10:54:58.425122 # ok 3657 Set Streaming SVE VL 6416
5388 10:54:58.425231 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5389 10:54:58.425341 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5390 10:54:58.425449 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5391 10:54:58.425559 # ok 3661 Set Streaming SVE VL 6432
5392 10:54:58.432927 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5393 10:54:58.433602 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5394 10:54:58.433757 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5395 10:54:58.433878 # ok 3665 Set Streaming SVE VL 6448
5396 10:54:58.434013 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5397 10:54:58.434153 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5398 10:54:58.434262 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5399 10:54:58.434373 # ok 3669 Set Streaming SVE VL 6464
5400 10:54:58.434486 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5401 10:54:58.434621 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5402 10:54:58.434727 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5403 10:54:58.434838 # ok 3673 Set Streaming SVE VL 6480
5404 10:54:58.434951 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5405 10:54:58.435060 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5406 10:54:58.435198 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5407 10:54:58.435302 # ok 3677 Set Streaming SVE VL 6496
5408 10:54:58.435412 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5409 10:54:58.435524 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5410 10:54:58.435636 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5411 10:54:58.435771 # ok 3681 Set Streaming SVE VL 6512
5412 10:54:58.435876 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5413 10:54:58.435986 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5414 10:54:58.436097 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5415 10:54:58.436207 # ok 3685 Set Streaming SVE VL 6528
5416 10:54:58.436340 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5417 10:54:58.436448 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5418 10:54:58.436559 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5419 10:54:58.445346 # ok 3689 Set Streaming SVE VL 6544
5420 10:54:58.445549 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5421 10:54:58.445688 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5422 10:54:58.445782 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5423 10:54:58.445871 # ok 3693 Set Streaming SVE VL 6560
5424 10:54:58.445972 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5425 10:54:58.446266 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5426 10:54:58.446359 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5427 10:54:58.446460 # ok 3697 Set Streaming SVE VL 6576
5428 10:54:58.446561 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5429 10:54:58.446663 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5430 10:54:58.446951 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5431 10:54:58.447060 # ok 3701 Set Streaming SVE VL 6592
5432 10:54:58.447147 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5433 10:54:58.447253 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5434 10:54:58.447355 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5435 10:54:58.447655 # ok 3705 Set Streaming SVE VL 6608
5436 10:54:58.447762 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5437 10:54:58.447851 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5438 10:54:58.455783 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5439 10:54:58.456227 # ok 3709 Set Streaming SVE VL 6624
5440 10:54:58.461432 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5441 10:54:58.461846 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5442 10:54:58.461952 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5443 10:54:58.462058 # ok 3713 Set Streaming SVE VL 6640
5444 10:54:58.462148 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5445 10:54:58.462398 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5446 10:54:58.462567 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5447 10:54:58.462692 # ok 3717 Set Streaming SVE VL 6656
5448 10:54:58.462785 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5449 10:54:58.462889 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5450 10:54:58.463179 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5451 10:54:58.463270 # ok 3721 Set Streaming SVE VL 6672
5452 10:54:58.463369 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5453 10:54:58.463644 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5454 10:54:58.463733 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5455 10:54:58.463833 # ok 3725 Set Streaming SVE VL 6688
5456 10:54:58.463996 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5457 10:54:58.469305 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5458 10:54:58.469707 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5459 10:54:58.469818 # ok 3729 Set Streaming SVE VL 6704
5460 10:54:58.469905 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5461 10:54:58.469987 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5462 10:54:58.470087 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5463 10:54:58.470173 # ok 3733 Set Streaming SVE VL 6720
5464 10:54:58.470257 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5465 10:54:58.470353 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5466 10:54:58.470451 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5467 10:54:58.470783 # ok 3737 Set Streaming SVE VL 6736
5468 10:54:58.470990 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5469 10:54:58.471147 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5470 10:54:58.471352 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5471 10:54:58.471524 # ok 3741 Set Streaming SVE VL 6752
5472 10:54:58.471915 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5473 10:54:58.472097 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5474 10:54:58.472337 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5475 10:54:58.472516 # ok 3745 Set Streaming SVE VL 6768
5476 10:54:58.472691 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5477 10:54:58.472883 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5478 10:54:58.473098 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5479 10:54:58.473309 # ok 3749 Set Streaming SVE VL 6784
5480 10:54:58.473494 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5481 10:54:58.473657 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5482 10:54:58.473830 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5483 10:54:58.474040 # ok 3753 Set Streaming SVE VL 6800
5484 10:54:58.474245 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5485 10:54:58.474454 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5486 10:54:58.474620 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5487 10:54:58.474773 # ok 3757 Set Streaming SVE VL 6816
5488 10:54:58.477035 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5489 10:54:58.477465 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5490 10:54:58.477634 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5491 10:54:58.477837 # ok 3761 Set Streaming SVE VL 6832
5492 10:54:58.478056 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5493 10:54:58.478193 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5494 10:54:58.478336 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5495 10:54:58.478477 # ok 3765 Set Streaming SVE VL 6848
5496 10:54:58.478595 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5497 10:54:58.478694 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5498 10:54:58.478814 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5499 10:54:58.478917 # ok 3769 Set Streaming SVE VL 6864
5500 10:54:58.479014 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5501 10:54:58.479103 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5502 10:54:58.479193 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5503 10:54:58.479283 # ok 3773 Set Streaming SVE VL 6880
5504 10:54:58.479372 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5505 10:54:58.480002 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5506 10:54:58.480101 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5507 10:54:58.491829 # ok 3777 Set Streaming SVE VL 6896
5508 10:54:58.492246 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5509 10:54:58.502123 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5510 10:54:58.502507 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5511 10:54:58.502615 # ok 3781 Set Streaming SVE VL 6912
5512 10:54:58.502705 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5513 10:54:58.502820 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5514 10:54:58.502941 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5515 10:54:58.503030 # ok 3785 Set Streaming SVE VL 6928
5516 10:54:58.503317 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5517 10:54:58.503411 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5518 10:54:58.503513 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5519 10:54:58.503616 # ok 3789 Set Streaming SVE VL 6944
5520 10:54:58.503912 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5521 10:54:58.504029 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5522 10:54:58.504996 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5523 10:54:58.505304 # ok 3793 Set Streaming SVE VL 6960
5524 10:54:58.505406 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5525 10:54:58.505507 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5526 10:54:58.505608 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5527 10:54:58.505716 # ok 3797 Set Streaming SVE VL 6976
5528 10:54:58.506013 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5529 10:54:58.506116 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5530 10:54:58.506216 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5531 10:54:58.506318 # ok 3801 Set Streaming SVE VL 6992
5532 10:54:58.506622 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5533 10:54:58.506739 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5534 10:54:58.506843 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5535 10:54:58.507140 # ok 3805 Set Streaming SVE VL 7008
5536 10:54:58.507262 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5537 10:54:58.507361 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5538 10:54:58.507455 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5539 10:54:58.507549 # ok 3809 Set Streaming SVE VL 7024
5540 10:54:58.507643 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5541 10:54:58.507947 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5542 10:54:58.514316 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5543 10:54:58.517176 # ok 3813 Set Streaming SVE VL 7040
5544 10:54:58.517438 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5545 10:54:58.517602 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5546 10:54:58.517769 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5547 10:54:58.517929 # ok 3817 Set Streaming SVE VL 7056
5548 10:54:58.518085 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5549 10:54:58.518280 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5550 10:54:58.518439 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5551 10:54:58.518649 # ok 3821 Set Streaming SVE VL 7072
5552 10:54:58.518897 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5553 10:54:58.519054 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5554 10:54:58.519262 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5555 10:54:58.519511 # ok 3825 Set Streaming SVE VL 7088
5556 10:54:58.519652 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5557 10:54:58.519890 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5558 10:54:58.520125 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5559 10:54:58.525872 # ok 3829 Set Streaming SVE VL 7104
5560 10:54:58.526607 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5561 10:54:58.526708 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5562 10:54:58.526813 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5563 10:54:58.526916 # ok 3833 Set Streaming SVE VL 7120
5564 10:54:58.527203 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5565 10:54:58.527296 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5566 10:54:58.527398 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5567 10:54:58.527501 # ok 3837 Set Streaming SVE VL 7136
5568 10:54:58.527791 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5569 10:54:58.527883 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5570 10:54:58.528977 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5571 10:54:58.529259 # ok 3841 Set Streaming SVE VL 7152
5572 10:54:58.529363 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5573 10:54:58.529468 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5574 10:54:58.529788 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5575 10:54:58.530096 # ok 3845 Set Streaming SVE VL 7168
5576 10:54:58.530202 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5577 10:54:58.530287 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5578 10:54:58.530386 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5579 10:54:58.530481 # ok 3849 Set Streaming SVE VL 7184
5580 10:54:58.531509 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5581 10:54:58.531826 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5582 10:54:58.531969 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5583 10:54:58.532127 # ok 3853 Set Streaming SVE VL 7200
5584 10:54:58.541593 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5585 10:54:58.542579 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5586 10:54:58.542683 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5587 10:54:58.542786 # ok 3857 Set Streaming SVE VL 7216
5588 10:54:58.542887 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5589 10:54:58.543204 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5590 10:54:58.543306 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5591 10:54:58.543408 # ok 3861 Set Streaming SVE VL 7232
5592 10:54:58.543507 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5593 10:54:58.543764 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5594 10:54:58.543884 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5595 10:54:58.550029 # ok 3865 Set Streaming SVE VL 7248
5596 10:54:58.550770 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5597 10:54:58.550877 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5598 10:54:58.550982 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5599 10:54:58.551083 # ok 3869 Set Streaming SVE VL 7264
5600 10:54:58.551369 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5601 10:54:58.551463 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5602 10:54:58.551562 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5603 10:54:58.551662 # ok 3873 Set Streaming SVE VL 7280
5604 10:54:58.551786 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5605 10:54:58.559272 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5606 10:54:58.559858 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5607 10:54:58.559967 # ok 3877 Set Streaming SVE VL 7296
5608 10:54:58.560240 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5609 10:54:58.560396 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5610 10:54:58.560512 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5611 10:54:58.560610 # ok 3881 Set Streaming SVE VL 7312
5612 10:54:58.560705 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5613 10:54:58.560799 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5614 10:54:58.561086 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5615 10:54:58.561190 # ok 3885 Set Streaming SVE VL 7328
5616 10:54:58.561285 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5617 10:54:58.561561 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5618 10:54:58.562256 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5619 10:54:58.562432 # ok 3889 Set Streaming SVE VL 7344
5620 10:54:58.562801 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5621 10:54:58.562952 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5622 10:54:58.563104 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5623 10:54:58.563274 # ok 3893 Set Streaming SVE VL 7360
5624 10:54:58.563444 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5625 10:54:58.563591 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5626 10:54:58.563766 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5627 10:54:58.563868 # ok 3897 Set Streaming SVE VL 7376
5628 10:54:58.563969 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5629 10:54:58.568511 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5630 10:54:58.568894 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5631 10:54:58.569265 # ok 3901 Set Streaming SVE VL 7392
5632 10:54:58.569420 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5633 10:54:58.569585 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5634 10:54:58.569780 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5635 10:54:58.569954 # ok 3905 Set Streaming SVE VL 7408
5636 10:54:58.570150 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5637 10:54:58.570322 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5638 10:54:58.570466 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5639 10:54:58.570635 # ok 3909 Set Streaming SVE VL 7424
5640 10:54:58.570836 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5641 10:54:58.571003 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5642 10:54:58.571152 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5643 10:54:58.571330 # ok 3913 Set Streaming SVE VL 7440
5644 10:54:58.571509 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5645 10:54:58.571663 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5646 10:54:58.571798 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5647 10:54:58.571921 # ok 3917 Set Streaming SVE VL 7456
5648 10:54:58.572010 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5649 10:54:58.576410 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5650 10:54:58.576962 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5651 10:54:58.577150 # ok 3921 Set Streaming SVE VL 7472
5652 10:54:58.577312 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5653 10:54:58.577438 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5654 10:54:58.577537 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5655 10:54:58.614291 # ok 3925 Set Streaming SVE VL 7488
5656 10:54:58.614783 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5657 10:54:58.614889 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5658 10:54:58.614986 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5659 10:54:58.615079 # ok 3929 Set Streaming SVE VL 7504
5660 10:54:58.615188 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5661 10:54:58.615287 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5662 10:54:58.615610 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5663 10:54:58.615720 # ok 3933 Set Streaming SVE VL 7520
5664 10:54:58.615820 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5665 10:54:58.615928 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5666 10:54:58.616229 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5667 10:54:58.616343 # ok 3937 Set Streaming SVE VL 7536
5668 10:54:58.616437 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5669 10:54:58.616528 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5670 10:54:58.622118 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5671 10:54:58.622291 # ok 3941 Set Streaming SVE VL 7552
5672 10:54:58.622599 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5673 10:54:58.622727 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5674 10:54:58.622823 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5675 10:54:58.622907 # ok 3945 Set Streaming SVE VL 7568
5676 10:54:58.623215 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5677 10:54:58.623334 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5678 10:54:58.623436 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5679 10:54:58.623541 # ok 3949 Set Streaming SVE VL 7584
5680 10:54:58.624159 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5681 10:54:58.624271 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5682 10:54:58.624353 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5683 10:54:58.624433 # ok 3953 Set Streaming SVE VL 7600
5684 10:54:58.627944 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5685 10:54:58.628741 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5686 10:54:58.629023 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5687 10:54:58.629123 # ok 3957 Set Streaming SVE VL 7616
5688 10:54:58.629406 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5689 10:54:58.629494 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5690 10:54:58.629577 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5691 10:54:58.629668 # ok 3961 Set Streaming SVE VL 7632
5692 10:54:58.629764 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5693 10:54:58.630157 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5694 10:54:58.630273 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5695 10:54:58.630356 # ok 3965 Set Streaming SVE VL 7648
5696 10:54:58.630436 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5697 10:54:58.630516 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5698 10:54:58.630800 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5699 10:54:58.630905 # ok 3969 Set Streaming SVE VL 7664
5700 10:54:58.630994 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5701 10:54:58.631074 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5702 10:54:58.631168 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5703 10:54:58.631459 # ok 3973 Set Streaming SVE VL 7680
5704 10:54:58.631561 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5705 10:54:58.631646 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5706 10:54:58.631742 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5707 10:54:58.631826 # ok 3977 Set Streaming SVE VL 7696
5708 10:54:58.633051 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5709 10:54:58.633144 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5710 10:54:58.646068 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5711 10:54:58.646543 # ok 3981 Set Streaming SVE VL 7712
5712 10:54:58.646651 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5713 10:54:58.646741 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5714 10:54:58.647036 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5715 10:54:58.647133 # ok 3985 Set Streaming SVE VL 7728
5716 10:54:58.647208 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5717 10:54:58.647275 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5718 10:54:58.647886 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5719 10:54:58.647988 # ok 3989 Set Streaming SVE VL 7744
5720 10:54:58.648070 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5721 10:54:58.648148 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5722 10:54:58.648229 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5723 10:54:58.648320 # ok 3993 Set Streaming SVE VL 7760
5724 10:54:58.648429 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5725 10:54:58.655230 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5726 10:54:58.655772 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5727 10:54:58.655877 # ok 3997 Set Streaming SVE VL 7776
5728 10:54:58.655959 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5729 10:54:58.656037 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5730 10:54:58.656131 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5731 10:54:58.656211 # ok 4001 Set Streaming SVE VL 7792
5732 10:54:58.656301 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5733 10:54:58.656399 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5734 10:54:58.656689 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5735 10:54:58.659473 # ok 4005 Set Streaming SVE VL 7808
5736 10:54:58.659913 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5737 10:54:58.660018 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5738 10:54:58.661024 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5739 10:54:58.661351 # ok 4009 Set Streaming SVE VL 7824
5740 10:54:58.661467 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5741 10:54:58.661603 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5742 10:54:58.661781 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5743 10:54:58.661895 # ok 4013 Set Streaming SVE VL 7840
5744 10:54:58.662015 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5745 10:54:58.662152 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5746 10:54:58.662484 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5747 10:54:58.662596 # ok 4017 Set Streaming SVE VL 7856
5748 10:54:58.662697 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5749 10:54:58.662794 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5750 10:54:58.662891 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5751 10:54:58.663181 # ok 4021 Set Streaming SVE VL 7872
5752 10:54:58.663321 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5753 10:54:58.663434 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5754 10:54:58.663551 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5755 10:54:58.663674 # ok 4025 Set Streaming SVE VL 7888
5756 10:54:58.663802 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5757 10:54:58.679166 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5758 10:54:58.679627 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5759 10:54:58.679719 # ok 4029 Set Streaming SVE VL 7904
5760 10:54:58.679800 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5761 10:54:58.679896 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5762 10:54:58.679980 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5763 10:54:58.691824 # ok 4033 Set Streaming SVE VL 7920
5764 10:54:58.692622 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5765 10:54:58.692948 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5766 10:54:58.693064 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5767 10:54:58.693388 # ok 4037 Set Streaming SVE VL 7936
5768 10:54:58.693489 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5769 10:54:58.693573 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5770 10:54:58.693877 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5771 10:54:58.693978 # ok 4041 Set Streaming SVE VL 7952
5772 10:54:58.694074 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5773 10:54:58.694157 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5774 10:54:58.694435 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5775 10:54:58.694521 # ok 4045 Set Streaming SVE VL 7968
5776 10:54:58.694616 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5777 10:54:58.694893 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5778 10:54:58.694978 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5779 10:54:58.695649 # ok 4049 Set Streaming SVE VL 7984
5780 10:54:58.695736 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5781 10:54:58.695817 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5782 10:54:58.695897 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5783 10:54:58.696161 # ok 4053 Set Streaming SVE VL 8000
5784 10:54:58.696246 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5785 10:54:58.704456 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5786 10:54:58.704892 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5787 10:54:58.704996 # ok 4057 Set Streaming SVE VL 8016
5788 10:54:58.705079 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5789 10:54:58.705173 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5790 10:54:58.705257 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5791 10:54:58.705350 # ok 4061 Set Streaming SVE VL 8032
5792 10:54:58.705446 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5793 10:54:58.705540 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5794 10:54:58.705799 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5795 10:54:58.705918 # ok 4065 Set Streaming SVE VL 8048
5796 10:54:58.706014 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5797 10:54:58.706307 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5798 10:54:58.706414 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5799 10:54:58.706513 # ok 4069 Set Streaming SVE VL 8064
5800 10:54:58.706596 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5801 10:54:58.706691 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5802 10:54:58.706786 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5803 10:54:58.706881 # ok 4073 Set Streaming SVE VL 8080
5804 10:54:58.706976 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5805 10:54:58.712670 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5806 10:54:58.712819 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5807 10:54:58.712906 # ok 4077 Set Streaming SVE VL 8096
5808 10:54:58.713001 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5809 10:54:58.713097 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5810 10:54:58.713193 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5811 10:54:58.713289 # ok 4081 Set Streaming SVE VL 8112
5812 10:54:58.713383 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5813 10:54:58.713492 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5814 10:54:58.713786 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5815 10:54:58.713891 # ok 4085 Set Streaming SVE VL 8128
5816 10:54:58.714176 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5817 10:54:58.714280 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5818 10:54:58.714363 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5819 10:54:58.714460 # ok 4089 Set Streaming SVE VL 8144
5820 10:54:58.714544 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5821 10:54:58.714639 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5822 10:54:58.714735 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5823 10:54:58.714830 # ok 4093 Set Streaming SVE VL 8160
5824 10:54:58.714925 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5825 10:54:58.715267 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5826 10:54:58.715375 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5827 10:54:58.715472 # ok 4097 Set Streaming SVE VL 8176
5828 10:54:58.715555 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5829 10:54:58.715650 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5830 10:54:58.715747 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5831 10:54:58.716037 # ok 4101 Set Streaming SVE VL 8192
5832 10:54:58.720152 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5833 10:54:58.720490 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5834 10:54:58.720596 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5835 10:54:58.720700 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5836 10:54:58.720803 ok 30 selftests: arm64: sve-ptrace
5837 10:54:58.720907 # selftests: arm64: sve-probe-vls
5838 10:54:58.721008 # TAP version 13
5839 10:54:58.721097 # 1..2
5840 10:54:58.721198 # ok 1 Enumerated 16 vector lengths
5841 10:54:58.721286 # ok 2 All vector lengths valid
5842 10:54:58.721372 # # 16
5843 10:54:58.721473 # # 32
5844 10:54:58.721563 # # 48
5845 10:54:58.721656 # # 64
5846 10:54:58.721745 # # 80
5847 10:54:58.721829 # # 96
5848 10:54:58.721911 # # 112
5849 10:54:58.721994 # # 128
5850 10:54:58.722077 # # 144
5851 10:54:58.722175 # # 160
5852 10:54:58.722258 # # 176
5853 10:54:58.722345 # # 192
5854 10:54:58.722428 # # 208
5855 10:54:58.722519 # # 224
5856 10:54:58.722604 # # 240
5857 10:54:58.722688 # # 256
5858 10:54:58.722771 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5859 10:54:58.722855 ok 31 selftests: arm64: sve-probe-vls
5860 10:54:58.857455 # selftests: arm64: vec-syscfg
5861 10:54:59.690330 # TAP version 13
5862 10:54:59.690745 # 1..20
5863 10:54:59.690865 # ok 1 SVE default vector length 64
5864 10:54:59.690949 # ok 2 SVE minimum vector length 16
5865 10:54:59.691018 # ok 3 SVE maximum vector length 256
5866 10:54:59.691133 # ok 4 SVE current VL is 64
5867 10:54:59.691217 # ok 5 SVE set VL 64 and have VL 64
5868 10:54:59.691319 # ok 6 SVE prctl() set min/max
5869 10:54:59.691425 # ok 7 SVE vector length used default
5870 10:54:59.691509 # ok 8 SVE vector length was inherited
5871 10:54:59.691588 # ok 9 SVE vector length set on exec
5872 10:54:59.697151 # ok 10 SVE prctl() set all VLs, 0 errors
5873 10:54:59.697446 # ok 11 SME default vector length 32
5874 10:54:59.697860 # ok 12 SME minimum vector length 16
5875 10:54:59.697965 # ok 13 SME maximum vector length 256
5876 10:54:59.698058 # ok 14 SME current VL is 32
5877 10:54:59.698147 # ok 15 SME set VL 32 and have VL 32
5878 10:54:59.698237 # ok 16 SME prctl() set min/max
5879 10:54:59.698324 # ok 17 SME vector length used default
5880 10:54:59.698400 # ok 18 SME vector length was inherited
5881 10:54:59.698472 # ok 19 SME vector length set on exec
5882 10:54:59.698548 # ok 20 SME prctl() set all VLs, 0 errors
5883 10:54:59.698637 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5884 10:54:59.731428 ok 32 selftests: arm64: vec-syscfg
5885 10:54:59.939101 # selftests: arm64: za-fork
5886 10:55:00.153399 # TAP version 13
5887 10:55:00.153831 # 1..1
5888 10:55:00.153938 # # PID: 1019
5889 10:55:00.154032 # ok 1 fork_test
5890 10:55:00.154122 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5891 10:55:00.176332 ok 33 selftests: arm64: za-fork
5892 10:55:00.288288 # selftests: arm64: za-ptrace
5893 10:55:00.406082 # TAP version 13
5894 10:55:00.406341 # 1..1536
5895 10:55:00.406437 # # Parent is 1037, child is 1038
5896 10:55:00.406770 # ok 1 Set VL 16
5897 10:55:00.406876 # ok 2 Disabled ZA for VL 16
5898 10:55:00.406962 # ok 3 Data match for VL 16
5899 10:55:00.407050 # ok 4 Set VL 32
5900 10:55:00.407134 # ok 5 Disabled ZA for VL 32
5901 10:55:00.407217 # ok 6 Data match for VL 32
5902 10:55:00.407297 # ok 7 Set VL 48
5903 10:55:00.407376 # ok 8 # SKIP Disabled ZA for VL 48
5904 10:55:00.407468 # ok 9 # SKIP Get and set data for VL 48
5905 10:55:00.407547 # ok 10 Set VL 64
5906 10:55:00.407624 # ok 11 Disabled ZA for VL 64
5907 10:55:00.407699 # ok 12 Data match for VL 64
5908 10:55:00.407773 # ok 13 Set VL 80
5909 10:55:00.407850 # ok 14 # SKIP Disabled ZA for VL 80
5910 10:55:00.408502 # ok 15 # SKIP Get and set data for VL 80
5911 10:55:00.408665 # ok 16 Set VL 96
5912 10:55:00.408779 # ok 17 # SKIP Disabled ZA for VL 96
5913 10:55:00.409078 # ok 18 # SKIP Get and set data for VL 96
5914 10:55:00.409185 # ok 19 Set VL 112
5915 10:55:00.409270 # ok 20 # SKIP Disabled ZA for VL 112
5916 10:55:00.409352 # ok 21 # SKIP Get and set data for VL 112
5917 10:55:00.409433 # ok 22 Set VL 128
5918 10:55:00.409528 # ok 23 Disabled ZA for VL 128
5919 10:55:00.409612 # ok 24 Data match for VL 128
5920 10:55:00.409706 # ok 25 Set VL 144
5921 10:55:00.409788 # ok 26 # SKIP Disabled ZA for VL 144
5922 10:55:00.409869 # ok 27 # SKIP Get and set data for VL 144
5923 10:55:00.409965 # ok 28 Set VL 160
5924 10:55:00.410048 # ok 29 # SKIP Disabled ZA for VL 160
5925 10:55:00.410129 # ok 30 # SKIP Get and set data for VL 160
5926 10:55:00.410209 # ok 31 Set VL 176
5927 10:55:00.410289 # ok 32 # SKIP Disabled ZA for VL 176
5928 10:55:00.410385 # ok 33 # SKIP Get and set data for VL 176
5929 10:55:00.410468 # ok 34 Set VL 192
5930 10:55:00.410548 # ok 35 # SKIP Disabled ZA for VL 192
5931 10:55:00.410628 # ok 36 # SKIP Get and set data for VL 192
5932 10:55:00.410707 # ok 37 Set VL 208
5933 10:55:00.410787 # ok 38 # SKIP Disabled ZA for VL 208
5934 10:55:00.410884 # ok 39 # SKIP Get and set data for VL 208
5935 10:55:00.410967 # ok 40 Set VL 224
5936 10:55:00.411047 # ok 41 # SKIP Disabled ZA for VL 224
5937 10:55:00.411126 # ok 42 # SKIP Get and set data for VL 224
5938 10:55:00.411206 # ok 43 Set VL 240
5939 10:55:00.411284 # ok 44 # SKIP Disabled ZA for VL 240
5940 10:55:00.411364 # ok 45 # SKIP Get and set data for VL 240
5941 10:55:00.411443 # ok 46 Set VL 256
5942 10:55:00.411523 # ok 47 Disabled ZA for VL 256
5943 10:55:00.411619 # ok 48 Data match for VL 256
5944 10:55:00.411702 # ok 49 Set VL 272
5945 10:55:00.411782 # ok 50 # SKIP Disabled ZA for VL 272
5946 10:55:00.411862 # ok 51 # SKIP Get and set data for VL 272
5947 10:55:00.411942 # ok 52 Set VL 288
5948 10:55:00.414686 # ok 53 # SKIP Disabled ZA for VL 288
5949 10:55:00.415158 # ok 54 # SKIP Get and set data for VL 288
5950 10:55:00.415353 # ok 55 Set VL 304
5951 10:55:00.415488 # ok 56 # SKIP Disabled ZA for VL 304
5952 10:55:00.415638 # ok 57 # SKIP Get and set data for VL 304
5953 10:55:00.415913 # ok 58 Set VL 320
5954 10:55:00.416122 # ok 59 # SKIP Disabled ZA for VL 320
5955 10:55:00.416290 # ok 60 # SKIP Get and set data for VL 320
5956 10:55:00.416446 # ok 61 Set VL 336
5957 10:55:00.416605 # ok 62 # SKIP Disabled ZA for VL 336
5958 10:55:00.416837 # ok 63 # SKIP Get and set data for VL 336
5959 10:55:00.417063 # ok 64 Set VL 352
5960 10:55:00.417308 # ok 65 # SKIP Disabled ZA for VL 352
5961 10:55:00.417589 # ok 66 # SKIP Get and set data for VL 352
5962 10:55:00.417828 # ok 67 Set VL 368
5963 10:55:00.418040 # ok 68 # SKIP Disabled ZA for VL 368
5964 10:55:00.418250 # ok 69 # SKIP Get and set data for VL 368
5965 10:55:00.418449 # ok 70 Set VL 384
5966 10:55:00.418647 # ok 71 # SKIP Disabled ZA for VL 384
5967 10:55:00.418837 # ok 72 # SKIP Get and set data for VL 384
5968 10:55:00.419028 # ok 73 Set VL 400
5969 10:55:00.419231 # ok 74 # SKIP Disabled ZA for VL 400
5970 10:55:00.419407 # ok 75 # SKIP Get and set data for VL 400
5971 10:55:00.419544 # ok 76 Set VL 416
5972 10:55:00.419704 # ok 77 # SKIP Disabled ZA for VL 416
5973 10:55:00.419831 # ok 78 # SKIP Get and set data for VL 416
5974 10:55:00.419952 # ok 79 Set VL 432
5975 10:55:00.420070 # ok 80 # SKIP Disabled ZA for VL 432
5976 10:55:00.420189 # ok 81 # SKIP Get and set data for VL 432
5977 10:55:00.420307 # ok 82 Set VL 448
5978 10:55:00.420425 # ok 83 # SKIP Disabled ZA for VL 448
5979 10:55:00.420542 # ok 84 # SKIP Get and set data for VL 448
5980 10:55:00.420661 # ok 85 Set VL 464
5981 10:55:00.420780 # ok 86 # SKIP Disabled ZA for VL 464
5982 10:55:00.420896 # ok 87 # SKIP Get and set data for VL 464
5983 10:55:00.421014 # ok 88 Set VL 480
5984 10:55:00.421130 # ok 89 # SKIP Disabled ZA for VL 480
5985 10:55:00.421247 # ok 90 # SKIP Get and set data for VL 480
5986 10:55:00.421365 # ok 91 Set VL 496
5987 10:55:00.421483 # ok 92 # SKIP Disabled ZA for VL 496
5988 10:55:00.421600 # ok 93 # SKIP Get and set data for VL 496
5989 10:55:00.421729 # ok 94 Set VL 512
5990 10:55:00.421848 # ok 95 # SKIP Disabled ZA for VL 512
5991 10:55:00.421963 # ok 96 # SKIP Get and set data for VL 512
5992 10:55:00.422077 # ok 97 Set VL 528
5993 10:55:00.422199 # ok 98 # SKIP Disabled ZA for VL 528
5994 10:55:00.422318 # ok 99 # SKIP Get and set data for VL 528
5995 10:55:00.422436 # ok 100 Set VL 544
5996 10:55:00.422553 # ok 101 # SKIP Disabled ZA for VL 544
5997 10:55:00.422673 # ok 102 # SKIP Get and set data for VL 544
5998 10:55:00.422791 # ok 103 Set VL 560
5999 10:55:00.422907 # ok 104 # SKIP Disabled ZA for VL 560
6000 10:55:00.423025 # ok 105 # SKIP Get and set data for VL 560
6001 10:55:00.423150 # ok 106 Set VL 576
6002 10:55:00.423330 # ok 107 # SKIP Disabled ZA for VL 576
6003 10:55:00.423478 # ok 108 # SKIP Get and set data for VL 576
6004 10:55:00.425667 # ok 109 Set VL 592
6005 10:55:00.425873 # ok 110 # SKIP Disabled ZA for VL 592
6006 10:55:00.426260 # ok 111 # SKIP Get and set data for VL 592
6007 10:55:00.426368 # ok 112 Set VL 608
6008 10:55:00.426459 # ok 113 # SKIP Disabled ZA for VL 608
6009 10:55:00.426547 # ok 114 # SKIP Get and set data for VL 608
6010 10:55:00.426634 # ok 115 Set VL 624
6011 10:55:00.426721 # ok 116 # SKIP Disabled ZA for VL 624
6012 10:55:00.426808 # ok 117 # SKIP Get and set data for VL 624
6013 10:55:00.426896 # ok 118 Set VL 640
6014 10:55:00.426999 # ok 119 # SKIP Disabled ZA for VL 640
6015 10:55:00.427082 # ok 120 # SKIP Get and set data for VL 640
6016 10:55:00.427168 # ok 121 Set VL 656
6017 10:55:00.427251 # ok 122 # SKIP Disabled ZA for VL 656
6018 10:55:00.427330 # ok 123 # SKIP Get and set data for VL 656
6019 10:55:00.427409 # ok 124 Set VL 672
6020 10:55:00.440379 # ok 125 # SKIP Disabled ZA for VL 672
6021 10:55:00.440662 # ok 126 # SKIP Get and set data for VL 672
6022 10:55:00.441164 # ok 127 Set VL 688
6023 10:55:00.441370 # ok 128 # SKIP Disabled ZA for VL 688
6024 10:55:00.441581 # ok 129 # SKIP Get and set data for VL 688
6025 10:55:00.441838 # ok 130 Set VL 704
6026 10:55:00.442078 # ok 131 # SKIP Disabled ZA for VL 704
6027 10:55:00.442367 # ok 132 # SKIP Get and set data for VL 704
6028 10:55:00.442566 # ok 133 Set VL 720
6029 10:55:00.442754 # ok 134 # SKIP Disabled ZA for VL 720
6030 10:55:00.443027 # ok 135 # SKIP Get and set data for VL 720
6031 10:55:00.443239 # ok 136 Set VL 736
6032 10:55:00.443387 # ok 137 # SKIP Disabled ZA for VL 736
6033 10:55:00.443551 # ok 138 # SKIP Get and set data for VL 736
6034 10:55:00.443685 # ok 139 Set VL 752
6035 10:55:00.443802 # ok 140 # SKIP Disabled ZA for VL 752
6036 10:55:00.443920 # ok 141 # SKIP Get and set data for VL 752
6037 10:55:00.444035 # ok 142 Set VL 768
6038 10:55:00.444151 # ok 143 # SKIP Disabled ZA for VL 768
6039 10:55:00.444265 # ok 144 # SKIP Get and set data for VL 768
6040 10:55:00.444380 # ok 145 Set VL 784
6041 10:55:00.444494 # ok 146 # SKIP Disabled ZA for VL 784
6042 10:55:00.444608 # ok 147 # SKIP Get and set data for VL 784
6043 10:55:00.444725 # ok 148 Set VL 800
6044 10:55:00.444841 # ok 149 # SKIP Disabled ZA for VL 800
6045 10:55:00.444982 # ok 150 # SKIP Get and set data for VL 800
6046 10:55:00.445106 # ok 151 Set VL 816
6047 10:55:00.445222 # ok 152 # SKIP Disabled ZA for VL 816
6048 10:55:00.445337 # ok 153 # SKIP Get and set data for VL 816
6049 10:55:00.449533 # ok 154 Set VL 832
6050 10:55:00.449885 # ok 155 # SKIP Disabled ZA for VL 832
6051 10:55:00.450060 # ok 156 # SKIP Get and set data for VL 832
6052 10:55:00.450268 # ok 157 Set VL 848
6053 10:55:00.450514 # ok 158 # SKIP Disabled ZA for VL 848
6054 10:55:00.450709 # ok 159 # SKIP Get and set data for VL 848
6055 10:55:00.450902 # ok 160 Set VL 864
6056 10:55:00.451070 # ok 161 # SKIP Disabled ZA for VL 864
6057 10:55:00.451268 # ok 162 # SKIP Get and set data for VL 864
6058 10:55:00.451416 # ok 163 Set VL 880
6059 10:55:00.451586 # ok 164 # SKIP Disabled ZA for VL 880
6060 10:55:00.451787 # ok 165 # SKIP Get and set data for VL 880
6061 10:55:00.451943 # ok 166 Set VL 896
6062 10:55:00.452089 # ok 167 # SKIP Disabled ZA for VL 896
6063 10:55:00.452235 # ok 168 # SKIP Get and set data for VL 896
6064 10:55:00.452404 # ok 169 Set VL 912
6065 10:55:00.452564 # ok 170 # SKIP Disabled ZA for VL 912
6066 10:55:00.452716 # ok 171 # SKIP Get and set data for VL 912
6067 10:55:00.452857 # ok 172 Set VL 928
6068 10:55:00.453017 # ok 173 # SKIP Disabled ZA for VL 928
6069 10:55:00.453189 # ok 174 # SKIP Get and set data for VL 928
6070 10:55:00.453364 # ok 175 Set VL 944
6071 10:55:00.453528 # ok 176 # SKIP Disabled ZA for VL 944
6072 10:55:00.454183 # ok 177 # SKIP Get and set data for VL 944
6073 10:55:00.454376 # ok 178 Set VL 960
6074 10:55:00.454541 # ok 179 # SKIP Disabled ZA for VL 960
6075 10:55:00.454698 # ok 180 # SKIP Get and set data for VL 960
6076 10:55:00.454857 # ok 181 Set VL 976
6077 10:55:00.455018 # ok 182 # SKIP Disabled ZA for VL 976
6078 10:55:00.455191 # ok 183 # SKIP Get and set data for VL 976
6079 10:55:00.455391 # ok 184 Set VL 992
6080 10:55:00.455544 # ok 185 # SKIP Disabled ZA for VL 992
6081 10:55:00.455666 # ok 186 # SKIP Get and set data for VL 992
6082 10:55:00.455784 # ok 187 Set VL 1008
6083 10:55:00.455900 # ok 188 # SKIP Disabled ZA for VL 1008
6084 10:55:00.456017 # ok 189 # SKIP Get and set data for VL 1008
6085 10:55:00.456134 # ok 190 Set VL 1024
6086 10:55:00.456249 # ok 191 # SKIP Disabled ZA for VL 1024
6087 10:55:00.456364 # ok 192 # SKIP Get and set data for VL 1024
6088 10:55:00.456481 # ok 193 Set VL 1040
6089 10:55:00.456596 # ok 194 # SKIP Disabled ZA for VL 1040
6090 10:55:00.456710 # ok 195 # SKIP Get and set data for VL 1040
6091 10:55:00.456828 # ok 196 Set VL 1056
6092 10:55:00.456943 # ok 197 # SKIP Disabled ZA for VL 1056
6093 10:55:00.457059 # ok 198 # SKIP Get and set data for VL 1056
6094 10:55:00.457174 # ok 199 Set VL 1072
6095 10:55:00.457288 # ok 200 # SKIP Disabled ZA for VL 1072
6096 10:55:00.457405 # ok 201 # SKIP Get and set data for VL 1072
6097 10:55:00.457519 # ok 202 Set VL 1088
6098 10:55:00.457634 # ok 203 # SKIP Disabled ZA for VL 1088
6099 10:55:00.457911 # ok 204 # SKIP Get and set data for VL 1088
6100 10:55:00.458112 # ok 205 Set VL 1104
6101 10:55:00.458300 # ok 206 # SKIP Disabled ZA for VL 1104
6102 10:55:00.458486 # ok 207 # SKIP Get and set data for VL 1104
6103 10:55:00.458673 # ok 208 Set VL 1120
6104 10:55:00.459054 # ok 209 # SKIP Disabled ZA for VL 1120
6105 10:55:00.459202 # ok 210 # SKIP Get and set data for VL 1120
6106 10:55:00.459351 # ok 211 Set VL 1136
6107 10:55:00.459496 # ok 212 # SKIP Disabled ZA for VL 1136
6108 10:55:00.459640 # ok 213 # SKIP Get and set data for VL 1136
6109 10:55:00.459784 # ok 214 Set VL 1152
6110 10:55:00.459928 # ok 215 # SKIP Disabled ZA for VL 1152
6111 10:55:00.460072 # ok 216 # SKIP Get and set data for VL 1152
6112 10:55:00.460218 # ok 217 Set VL 1168
6113 10:55:00.460362 # ok 218 # SKIP Disabled ZA for VL 1168
6114 10:55:00.460506 # ok 219 # SKIP Get and set data for VL 1168
6115 10:55:00.463844 # ok 220 Set VL 1184
6116 10:55:00.464162 # ok 221 # SKIP Disabled ZA for VL 1184
6117 10:55:00.464270 # ok 222 # SKIP Get and set data for VL 1184
6118 10:55:00.464356 # ok 223 Set VL 1200
6119 10:55:00.464451 # ok 224 # SKIP Disabled ZA for VL 1200
6120 10:55:00.464535 # ok 225 # SKIP Get and set data for VL 1200
6121 10:55:00.464631 # ok 226 Set VL 1216
6122 10:55:00.464714 # ok 227 # SKIP Disabled ZA for VL 1216
6123 10:55:00.464809 # ok 228 # SKIP Get and set data for VL 1216
6124 10:55:00.464905 # ok 229 Set VL 1232
6125 10:55:00.464987 # ok 230 # SKIP Disabled ZA for VL 1232
6126 10:55:00.465276 # ok 231 # SKIP Get and set data for VL 1232
6127 10:55:00.465383 # ok 232 Set VL 1248
6128 10:55:00.465468 # ok 233 # SKIP Disabled ZA for VL 1248
6129 10:55:00.465549 # ok 234 # SKIP Get and set data for VL 1248
6130 10:55:00.465633 # ok 235 Set VL 1264
6131 10:55:00.465754 # ok 236 # SKIP Disabled ZA for VL 1264
6132 10:55:00.465840 # ok 237 # SKIP Get and set data for VL 1264
6133 10:55:00.465923 # ok 238 Set VL 1280
6134 10:55:00.466003 # ok 239 # SKIP Disabled ZA for VL 1280
6135 10:55:00.466083 # ok 240 # SKIP Get and set data for VL 1280
6136 10:55:00.466163 # ok 241 Set VL 1296
6137 10:55:00.466258 # ok 242 # SKIP Disabled ZA for VL 1296
6138 10:55:00.466341 # ok 243 # SKIP Get and set data for VL 1296
6139 10:55:00.466422 # ok 244 Set VL 1312
6140 10:55:00.466502 # ok 245 # SKIP Disabled ZA for VL 1312
6141 10:55:00.466582 # ok 246 # SKIP Get and set data for VL 1312
6142 10:55:00.466677 # ok 247 Set VL 1328
6143 10:55:00.466764 # ok 248 # SKIP Disabled ZA for VL 1328
6144 10:55:00.466844 # ok 249 # SKIP Get and set data for VL 1328
6145 10:55:00.466924 # ok 250 Set VL 1344
6146 10:55:00.467004 # ok 251 # SKIP Disabled ZA for VL 1344
6147 10:55:00.467100 # ok 252 # SKIP Get and set data for VL 1344
6148 10:55:00.467188 # ok 253 Set VL 1360
6149 10:55:00.467269 # ok 254 # SKIP Disabled ZA for VL 1360
6150 10:55:00.467348 # ok 255 # SKIP Get and set data for VL 1360
6151 10:55:00.467428 # ok 256 Set VL 1376
6152 10:55:00.467523 # ok 257 # SKIP Disabled ZA for VL 1376
6153 10:55:00.467606 # ok 258 # SKIP Get and set data for VL 1376
6154 10:55:00.473141 # ok 259 Set VL 1392
6155 10:55:00.473427 # ok 260 # SKIP Disabled ZA for VL 1392
6156 10:55:00.473604 # ok 261 # SKIP Get and set data for VL 1392
6157 10:55:00.473784 # ok 262 Set VL 1408
6158 10:55:00.473973 # ok 263 # SKIP Disabled ZA for VL 1408
6159 10:55:00.474130 # ok 264 # SKIP Get and set data for VL 1408
6160 10:55:00.474279 # ok 265 Set VL 1424
6161 10:55:00.474416 # ok 266 # SKIP Disabled ZA for VL 1424
6162 10:55:00.474561 # ok 267 # SKIP Get and set data for VL 1424
6163 10:55:00.474731 # ok 268 Set VL 1440
6164 10:55:00.474901 # ok 269 # SKIP Disabled ZA for VL 1440
6165 10:55:00.475059 # ok 270 # SKIP Get and set data for VL 1440
6166 10:55:00.475210 # ok 271 Set VL 1456
6167 10:55:00.475378 # ok 272 # SKIP Disabled ZA for VL 1456
6168 10:55:00.475502 # ok 273 # SKIP Get and set data for VL 1456
6169 10:55:00.475673 # ok 274 Set VL 1472
6170 10:55:00.475806 # ok 275 # SKIP Disabled ZA for VL 1472
6171 10:55:00.475927 # ok 276 # SKIP Get and set data for VL 1472
6172 10:55:00.476045 # ok 277 Set VL 1488
6173 10:55:00.476164 # ok 278 # SKIP Disabled ZA for VL 1488
6174 10:55:00.476281 # ok 279 # SKIP Get and set data for VL 1488
6175 10:55:00.476399 # ok 280 Set VL 1504
6176 10:55:00.476517 # ok 281 # SKIP Disabled ZA for VL 1504
6177 10:55:00.476636 # ok 282 # SKIP Get and set data for VL 1504
6178 10:55:00.476752 # ok 283 Set VL 1520
6179 10:55:00.476872 # ok 284 # SKIP Disabled ZA for VL 1520
6180 10:55:00.476989 # ok 285 # SKIP Get and set data for VL 1520
6181 10:55:00.477107 # ok 286 Set VL 1536
6182 10:55:00.477224 # ok 287 # SKIP Disabled ZA for VL 1536
6183 10:55:00.477341 # ok 288 # SKIP Get and set data for VL 1536
6184 10:55:00.477460 # ok 289 Set VL 1552
6185 10:55:00.477576 # ok 290 # SKIP Disabled ZA for VL 1552
6186 10:55:00.477770 # ok 291 # SKIP Get and set data for VL 1552
6187 10:55:00.477968 # ok 292 Set VL 1568
6188 10:55:00.478125 # ok 293 # SKIP Disabled ZA for VL 1568
6189 10:55:00.478302 # ok 294 # SKIP Get and set data for VL 1568
6190 10:55:00.478440 # ok 295 Set VL 1584
6191 10:55:00.478563 # ok 296 # SKIP Disabled ZA for VL 1584
6192 10:55:00.478741 # ok 297 # SKIP Get and set data for VL 1584
6193 10:55:00.478897 # ok 298 Set VL 1600
6194 10:55:00.479060 # ok 299 # SKIP Disabled ZA for VL 1600
6195 10:55:00.479230 # ok 300 # SKIP Get and set data for VL 1600
6196 10:55:00.479367 # ok 301 Set VL 1616
6197 10:55:00.479487 # ok 302 # SKIP Disabled ZA for VL 1616
6198 10:55:00.479656 # ok 303 # SKIP Get and set data for VL 1616
6199 10:55:00.479784 # ok 304 Set VL 1632
6200 10:55:00.479930 # ok 305 # SKIP Disabled ZA for VL 1632
6201 10:55:00.480082 # ok 306 # SKIP Get and set data for VL 1632
6202 10:55:00.480229 # ok 307 Set VL 1648
6203 10:55:00.480392 # ok 308 # SKIP Disabled ZA for VL 1648
6204 10:55:00.480517 # ok 309 # SKIP Get and set data for VL 1648
6205 10:55:00.480635 # ok 310 Set VL 1664
6206 10:55:00.480752 # ok 311 # SKIP Disabled ZA for VL 1664
6207 10:55:00.518888 # ok 312 # SKIP Get and set data for VL 1664
6208 10:55:00.519127 # ok 313 Set VL 1680
6209 10:55:00.519215 # ok 314 # SKIP Disabled ZA for VL 1680
6210 10:55:00.519509 # ok 315 # SKIP Get and set data for VL 1680
6211 10:55:00.519614 # ok 316 Set VL 1696
6212 10:55:00.519700 # ok 317 # SKIP Disabled ZA for VL 1696
6213 10:55:00.547089 # ok 318 # SKIP Get and set data for VL 1696
6214 10:55:00.547318 # ok 319 Set VL 1712
6215 10:55:00.547629 # ok 320 # SKIP Disabled ZA for VL 1712
6216 10:55:00.548406 # ok 321 # SKIP Get and set data for VL 1712
6217 10:55:00.548722 # ok 322 Set VL 1728
6218 10:55:00.548831 # ok 323 # SKIP Disabled ZA for VL 1728
6219 10:55:00.548919 # ok 324 # SKIP Get and set data for VL 1728
6220 10:55:00.549090 # ok 325 Set VL 1744
6221 10:55:00.549209 # ok 326 # SKIP Disabled ZA for VL 1744
6222 10:55:00.549387 # ok 327 # SKIP Get and set data for VL 1744
6223 10:55:00.549553 # ok 328 Set VL 1760
6224 10:55:00.549652 # ok 329 # SKIP Disabled ZA for VL 1760
6225 10:55:00.549737 # ok 330 # SKIP Get and set data for VL 1760
6226 10:55:00.549820 # ok 331 Set VL 1776
6227 10:55:00.549927 # ok 332 # SKIP Disabled ZA for VL 1776
6228 10:55:00.550012 # ok 333 # SKIP Get and set data for VL 1776
6229 10:55:00.550093 # ok 334 Set VL 1792
6230 10:55:00.550173 # ok 335 # SKIP Disabled ZA for VL 1792
6231 10:55:00.550253 # ok 336 # SKIP Get and set data for VL 1792
6232 10:55:00.550332 # ok 337 Set VL 1808
6233 10:55:00.550412 # ok 338 # SKIP Disabled ZA for VL 1808
6234 10:55:00.550492 # ok 339 # SKIP Get and set data for VL 1808
6235 10:55:00.550572 # ok 340 Set VL 1824
6236 10:55:00.550670 # ok 341 # SKIP Disabled ZA for VL 1824
6237 10:55:00.550753 # ok 342 # SKIP Get and set data for VL 1824
6238 10:55:00.550834 # ok 343 Set VL 1840
6239 10:55:00.550917 # ok 344 # SKIP Disabled ZA for VL 1840
6240 10:55:00.550999 # ok 345 # SKIP Get and set data for VL 1840
6241 10:55:00.551079 # ok 346 Set VL 1856
6242 10:55:00.551158 # ok 347 # SKIP Disabled ZA for VL 1856
6243 10:55:00.551238 # ok 348 # SKIP Get and set data for VL 1856
6244 10:55:00.551318 # ok 349 Set VL 1872
6245 10:55:00.551402 # ok 350 # SKIP Disabled ZA for VL 1872
6246 10:55:00.551501 # ok 351 # SKIP Get and set data for VL 1872
6247 10:55:00.551586 # ok 352 Set VL 1888
6248 10:55:00.551666 # ok 353 # SKIP Disabled ZA for VL 1888
6249 10:55:00.551746 # ok 354 # SKIP Get and set data for VL 1888
6250 10:55:00.551826 # ok 355 Set VL 1904
6251 10:55:00.551906 # ok 356 # SKIP Disabled ZA for VL 1904
6252 10:55:00.551986 # ok 357 # SKIP Get and set data for VL 1904
6253 10:55:00.552066 # ok 358 Set VL 1920
6254 10:55:00.557204 # ok 359 # SKIP Disabled ZA for VL 1920
6255 10:55:00.557330 # ok 360 # SKIP Get and set data for VL 1920
6256 10:55:00.557416 # ok 361 Set VL 1936
6257 10:55:00.557512 # ok 362 # SKIP Disabled ZA for VL 1936
6258 10:55:00.557595 # ok 363 # SKIP Get and set data for VL 1936
6259 10:55:00.557685 # ok 364 Set VL 1952
6260 10:55:00.557780 # ok 365 # SKIP Disabled ZA for VL 1952
6261 10:55:00.557864 # ok 366 # SKIP Get and set data for VL 1952
6262 10:55:00.557949 # ok 367 Set VL 1968
6263 10:55:00.558029 # ok 368 # SKIP Disabled ZA for VL 1968
6264 10:55:00.558125 # ok 369 # SKIP Get and set data for VL 1968
6265 10:55:00.558214 # ok 370 Set VL 1984
6266 10:55:00.558294 # ok 371 # SKIP Disabled ZA for VL 1984
6267 10:55:00.558390 # ok 372 # SKIP Get and set data for VL 1984
6268 10:55:00.558472 # ok 373 Set VL 2000
6269 10:55:00.558552 # ok 374 # SKIP Disabled ZA for VL 2000
6270 10:55:00.558646 # ok 375 # SKIP Get and set data for VL 2000
6271 10:55:00.558728 # ok 376 Set VL 2016
6272 10:55:00.558809 # ok 377 # SKIP Disabled ZA for VL 2016
6273 10:55:00.558904 # ok 378 # SKIP Get and set data for VL 2016
6274 10:55:00.558987 # ok 379 Set VL 2032
6275 10:55:00.559068 # ok 380 # SKIP Disabled ZA for VL 2032
6276 10:55:00.559163 # ok 381 # SKIP Get and set data for VL 2032
6277 10:55:00.559246 # ok 382 Set VL 2048
6278 10:55:00.559340 # ok 383 # SKIP Disabled ZA for VL 2048
6279 10:55:00.564344 # ok 384 # SKIP Get and set data for VL 2048
6280 10:55:00.564548 # ok 385 Set VL 2064
6281 10:55:00.564917 # ok 386 # SKIP Disabled ZA for VL 2064
6282 10:55:00.565098 # ok 387 # SKIP Get and set data for VL 2064
6283 10:55:00.565260 # ok 388 Set VL 2080
6284 10:55:00.565426 # ok 389 # SKIP Disabled ZA for VL 2080
6285 10:55:00.565605 # ok 390 # SKIP Get and set data for VL 2080
6286 10:55:00.565793 # ok 391 Set VL 2096
6287 10:55:00.565937 # ok 392 # SKIP Disabled ZA for VL 2096
6288 10:55:00.566069 # ok 393 # SKIP Get and set data for VL 2096
6289 10:55:00.566287 # ok 394 Set VL 2112
6290 10:55:00.566470 # ok 395 # SKIP Disabled ZA for VL 2112
6291 10:55:00.566640 # ok 396 # SKIP Get and set data for VL 2112
6292 10:55:00.566810 # ok 397 Set VL 2128
6293 10:55:00.567014 # ok 398 # SKIP Disabled ZA for VL 2128
6294 10:55:00.567209 # ok 399 # SKIP Get and set data for VL 2128
6295 10:55:00.567401 # ok 400 Set VL 2144
6296 10:55:00.567539 # ok 401 # SKIP Disabled ZA for VL 2144
6297 10:55:00.567661 # ok 402 # SKIP Get and set data for VL 2144
6298 10:55:00.567776 # ok 403 Set VL 2160
6299 10:55:00.567922 # ok 404 # SKIP Disabled ZA for VL 2160
6300 10:55:00.568045 # ok 405 # SKIP Get and set data for VL 2160
6301 10:55:00.568162 # ok 406 Set VL 2176
6302 10:55:00.568277 # ok 407 # SKIP Disabled ZA for VL 2176
6303 10:55:00.568394 # ok 408 # SKIP Get and set data for VL 2176
6304 10:55:00.568510 # ok 409 Set VL 2192
6305 10:55:00.568624 # ok 410 # SKIP Disabled ZA for VL 2192
6306 10:55:00.568739 # ok 411 # SKIP Get and set data for VL 2192
6307 10:55:00.568853 # ok 412 Set VL 2208
6308 10:55:00.568968 # ok 413 # SKIP Disabled ZA for VL 2208
6309 10:55:00.569082 # ok 414 # SKIP Get and set data for VL 2208
6310 10:55:00.569198 # ok 415 Set VL 2224
6311 10:55:00.569313 # ok 416 # SKIP Disabled ZA for VL 2224
6312 10:55:00.572503 # ok 417 # SKIP Get and set data for VL 2224
6313 10:55:00.572823 # ok 418 Set VL 2240
6314 10:55:00.572937 # ok 419 # SKIP Disabled ZA for VL 2240
6315 10:55:00.573032 # ok 420 # SKIP Get and set data for VL 2240
6316 10:55:00.573118 # ok 421 Set VL 2256
6317 10:55:00.573220 # ok 422 # SKIP Disabled ZA for VL 2256
6318 10:55:00.573307 # ok 423 # SKIP Get and set data for VL 2256
6319 10:55:00.573395 # ok 424 Set VL 2272
6320 10:55:00.573476 # ok 425 # SKIP Disabled ZA for VL 2272
6321 10:55:00.573573 # ok 426 # SKIP Get and set data for VL 2272
6322 10:55:00.573690 # ok 427 Set VL 2288
6323 10:55:00.573797 # ok 428 # SKIP Disabled ZA for VL 2288
6324 10:55:00.573888 # ok 429 # SKIP Get and set data for VL 2288
6325 10:55:00.573975 # ok 430 Set VL 2304
6326 10:55:00.574082 # ok 431 # SKIP Disabled ZA for VL 2304
6327 10:55:00.574171 # ok 432 # SKIP Get and set data for VL 2304
6328 10:55:00.574257 # ok 433 Set VL 2320
6329 10:55:00.574346 # ok 434 # SKIP Disabled ZA for VL 2320
6330 10:55:00.574432 # ok 435 # SKIP Get and set data for VL 2320
6331 10:55:00.574538 # ok 436 Set VL 2336
6332 10:55:00.574629 # ok 437 # SKIP Disabled ZA for VL 2336
6333 10:55:00.574719 # ok 438 # SKIP Get and set data for VL 2336
6334 10:55:00.574808 # ok 439 Set VL 2352
6335 10:55:00.574911 # ok 440 # SKIP Disabled ZA for VL 2352
6336 10:55:00.574998 # ok 441 # SKIP Get and set data for VL 2352
6337 10:55:00.575085 # ok 442 Set VL 2368
6338 10:55:00.575169 # ok 443 # SKIP Disabled ZA for VL 2368
6339 10:55:00.575274 # ok 444 # SKIP Get and set data for VL 2368
6340 10:55:00.575369 # ok 445 Set VL 2384
6341 10:55:00.575461 # ok 446 # SKIP Disabled ZA for VL 2384
6342 10:55:00.575553 # ok 447 # SKIP Get and set data for VL 2384
6343 10:55:00.577968 # ok 448 Set VL 2400
6344 10:55:00.578296 # ok 449 # SKIP Disabled ZA for VL 2400
6345 10:55:00.578402 # ok 450 # SKIP Get and set data for VL 2400
6346 10:55:00.578492 # ok 451 Set VL 2416
6347 10:55:00.578594 # ok 452 # SKIP Disabled ZA for VL 2416
6348 10:55:00.578683 # ok 453 # SKIP Get and set data for VL 2416
6349 10:55:00.578768 # ok 454 Set VL 2432
6350 10:55:00.578855 # ok 455 # SKIP Disabled ZA for VL 2432
6351 10:55:00.578943 # ok 456 # SKIP Get and set data for VL 2432
6352 10:55:00.579048 # ok 457 Set VL 2448
6353 10:55:00.579135 # ok 458 # SKIP Disabled ZA for VL 2448
6354 10:55:00.579222 # ok 459 # SKIP Get and set data for VL 2448
6355 10:55:00.579309 # ok 460 Set VL 2464
6356 10:55:00.579395 # ok 461 # SKIP Disabled ZA for VL 2464
6357 10:55:00.579498 # ok 462 # SKIP Get and set data for VL 2464
6358 10:55:00.579590 # ok 463 Set VL 2480
6359 10:55:00.579677 # ok 464 # SKIP Disabled ZA for VL 2480
6360 10:55:00.583070 # ok 465 # SKIP Get and set data for VL 2480
6361 10:55:00.583483 # ok 466 Set VL 2496
6362 10:55:00.583622 # ok 467 # SKIP Disabled ZA for VL 2496
6363 10:55:00.584023 # ok 468 # SKIP Get and set data for VL 2496
6364 10:55:00.584135 # ok 469 Set VL 2512
6365 10:55:00.584438 # ok 470 # SKIP Disabled ZA for VL 2512
6366 10:55:00.584545 # ok 471 # SKIP Get and set data for VL 2512
6367 10:55:00.584634 # ok 472 Set VL 2528
6368 10:55:00.584720 # ok 473 # SKIP Disabled ZA for VL 2528
6369 10:55:00.584818 # ok 474 # SKIP Get and set data for VL 2528
6370 10:55:00.584905 # ok 475 Set VL 2544
6371 10:55:00.584992 # ok 476 # SKIP Disabled ZA for VL 2544
6372 10:55:00.585078 # ok 477 # SKIP Get and set data for VL 2544
6373 10:55:00.585163 # ok 478 Set VL 2560
6374 10:55:00.585249 # ok 479 # SKIP Disabled ZA for VL 2560
6375 10:55:00.585335 # ok 480 # SKIP Get and set data for VL 2560
6376 10:55:00.585440 # ok 481 Set VL 2576
6377 10:55:00.585531 # ok 482 # SKIP Disabled ZA for VL 2576
6378 10:55:00.585620 # ok 483 # SKIP Get and set data for VL 2576
6379 10:55:00.585717 # ok 484 Set VL 2592
6380 10:55:00.585803 # ok 485 # SKIP Disabled ZA for VL 2592
6381 10:55:00.585889 # ok 486 # SKIP Get and set data for VL 2592
6382 10:55:00.585980 # ok 487 Set VL 2608
6383 10:55:00.586085 # ok 488 # SKIP Disabled ZA for VL 2608
6384 10:55:00.586172 # ok 489 # SKIP Get and set data for VL 2608
6385 10:55:00.586259 # ok 490 Set VL 2624
6386 10:55:00.586345 # ok 491 # SKIP Disabled ZA for VL 2624
6387 10:55:00.586434 # ok 492 # SKIP Get and set data for VL 2624
6388 10:55:00.586521 # ok 493 Set VL 2640
6389 10:55:00.586609 # ok 494 # SKIP Disabled ZA for VL 2640
6390 10:55:00.586717 # ok 495 # SKIP Get and set data for VL 2640
6391 10:55:00.586809 # ok 496 Set VL 2656
6392 10:55:00.586897 # ok 497 # SKIP Disabled ZA for VL 2656
6393 10:55:00.586984 # ok 498 # SKIP Get and set data for VL 2656
6394 10:55:00.587078 # ok 499 Set VL 2672
6395 10:55:00.587167 # ok 500 # SKIP Disabled ZA for VL 2672
6396 10:55:00.587254 # ok 501 # SKIP Get and set data for VL 2672
6397 10:55:00.587360 # ok 502 Set VL 2688
6398 10:55:00.587453 # ok 503 # SKIP Disabled ZA for VL 2688
6399 10:55:00.587543 # ok 504 # SKIP Get and set data for VL 2688
6400 10:55:00.587634 # ok 505 Set VL 2704
6401 10:55:00.592292 # ok 506 # SKIP Disabled ZA for VL 2704
6402 10:55:00.592741 # ok 507 # SKIP Get and set data for VL 2704
6403 10:55:00.592919 # ok 508 Set VL 2720
6404 10:55:00.593077 # ok 509 # SKIP Disabled ZA for VL 2720
6405 10:55:00.593252 # ok 510 # SKIP Get and set data for VL 2720
6406 10:55:00.593426 # ok 511 Set VL 2736
6407 10:55:00.593873 # ok 512 # SKIP Disabled ZA for VL 2736
6408 10:55:00.594166 # ok 513 # SKIP Get and set data for VL 2736
6409 10:55:00.594373 # ok 514 Set VL 2752
6410 10:55:00.594580 # ok 515 # SKIP Disabled ZA for VL 2752
6411 10:55:00.594796 # ok 516 # SKIP Get and set data for VL 2752
6412 10:55:00.594988 # ok 517 Set VL 2768
6413 10:55:00.595153 # ok 518 # SKIP Disabled ZA for VL 2768
6414 10:55:00.595281 # ok 519 # SKIP Get and set data for VL 2768
6415 10:55:00.595400 # ok 520 Set VL 2784
6416 10:55:00.595516 # ok 521 # SKIP Disabled ZA for VL 2784
6417 10:55:00.595632 # ok 522 # SKIP Get and set data for VL 2784
6418 10:55:00.595748 # ok 523 Set VL 2800
6419 10:55:00.595864 # ok 524 # SKIP Disabled ZA for VL 2800
6420 10:55:00.595979 # ok 525 # SKIP Get and set data for VL 2800
6421 10:55:00.596098 # ok 526 Set VL 2816
6422 10:55:00.596213 # ok 527 # SKIP Disabled ZA for VL 2816
6423 10:55:00.596328 # ok 528 # SKIP Get and set data for VL 2816
6424 10:55:00.596476 # ok 529 Set VL 2832
6425 10:55:00.596598 # ok 530 # SKIP Disabled ZA for VL 2832
6426 10:55:00.596717 # ok 531 # SKIP Get and set data for VL 2832
6427 10:55:00.596833 # ok 532 Set VL 2848
6428 10:55:00.596948 # ok 533 # SKIP Disabled ZA for VL 2848
6429 10:55:00.597067 # ok 534 # SKIP Get and set data for VL 2848
6430 10:55:00.597183 # ok 535 Set VL 2864
6431 10:55:00.597298 # ok 536 # SKIP Disabled ZA for VL 2864
6432 10:55:00.597414 # ok 537 # SKIP Get and set data for VL 2864
6433 10:55:00.597531 # ok 538 Set VL 2880
6434 10:55:00.597679 # ok 539 # SKIP Disabled ZA for VL 2880
6435 10:55:00.597902 # ok 540 # SKIP Get and set data for VL 2880
6436 10:55:00.598095 # ok 541 Set VL 2896
6437 10:55:00.600511 # ok 542 # SKIP Disabled ZA for VL 2896
6438 10:55:00.600623 # ok 543 # SKIP Get and set data for VL 2896
6439 10:55:00.600734 # ok 544 Set VL 2912
6440 10:55:00.600827 # ok 545 # SKIP Disabled ZA for VL 2912
6441 10:55:00.600927 # ok 546 # SKIP Get and set data for VL 2912
6442 10:55:00.601015 # ok 547 Set VL 2928
6443 10:55:00.601103 # ok 548 # SKIP Disabled ZA for VL 2928
6444 10:55:00.601209 # ok 549 # SKIP Get and set data for VL 2928
6445 10:55:00.601299 # ok 550 Set VL 2944
6446 10:55:00.601385 # ok 551 # SKIP Disabled ZA for VL 2944
6447 10:55:00.601486 # ok 552 # SKIP Get and set data for VL 2944
6448 10:55:00.601574 # ok 553 Set VL 2960
6449 10:55:00.601666 # ok 554 # SKIP Disabled ZA for VL 2960
6450 10:55:00.602029 # ok 555 # SKIP Get and set data for VL 2960
6451 10:55:00.602138 # ok 556 Set VL 2976
6452 10:55:00.602229 # ok 557 # SKIP Disabled ZA for VL 2976
6453 10:55:00.602314 # ok 558 # SKIP Get and set data for VL 2976
6454 10:55:00.602400 # ok 559 Set VL 2992
6455 10:55:00.602485 # ok 560 # SKIP Disabled ZA for VL 2992
6456 10:55:00.602572 # ok 561 # SKIP Get and set data for VL 2992
6457 10:55:00.602679 # ok 562 Set VL 3008
6458 10:55:00.602767 # ok 563 # SKIP Disabled ZA for VL 3008
6459 10:55:00.602851 # ok 564 # SKIP Get and set data for VL 3008
6460 10:55:00.602937 # ok 565 Set VL 3024
6461 10:55:00.603024 # ok 566 # SKIP Disabled ZA for VL 3024
6462 10:55:00.603112 # ok 567 # SKIP Get and set data for VL 3024
6463 10:55:00.603201 # ok 568 Set VL 3040
6464 10:55:00.603290 # ok 569 # SKIP Disabled ZA for VL 3040
6465 10:55:00.603379 # ok 570 # SKIP Get and set data for VL 3040
6466 10:55:00.603467 # ok 571 Set VL 3056
6467 10:55:00.603573 # ok 572 # SKIP Disabled ZA for VL 3056
6468 10:55:00.603665 # ok 573 # SKIP Get and set data for VL 3056
6469 10:55:00.603753 # ok 574 Set VL 3072
6470 10:55:00.603838 # ok 575 # SKIP Disabled ZA for VL 3072
6471 10:55:00.603923 # ok 576 # SKIP Get and set data for VL 3072
6472 10:55:00.604008 # ok 577 Set VL 3088
6473 10:55:00.606800 # ok 578 # SKIP Disabled ZA for VL 3088
6474 10:55:00.606935 # ok 579 # SKIP Get and set data for VL 3088
6475 10:55:00.607033 # ok 580 Set VL 3104
6476 10:55:00.607322 # ok 581 # SKIP Disabled ZA for VL 3104
6477 10:55:00.607431 # ok 582 # SKIP Get and set data for VL 3104
6478 10:55:00.607524 # ok 583 Set VL 3120
6479 10:55:00.608294 # ok 584 # SKIP Disabled ZA for VL 3120
6480 10:55:00.608598 # ok 585 # SKIP Get and set data for VL 3120
6481 10:55:00.608707 # ok 586 Set VL 3136
6482 10:55:00.608801 # ok 587 # SKIP Disabled ZA for VL 3136
6483 10:55:00.608911 # ok 588 # SKIP Get and set data for VL 3136
6484 10:55:00.609006 # ok 589 Set VL 3152
6485 10:55:00.609545 # ok 590 # SKIP Disabled ZA for VL 3152
6486 10:55:00.609877 # ok 591 # SKIP Get and set data for VL 3152
6487 10:55:00.609985 # ok 592 Set VL 3168
6488 10:55:00.610077 # ok 593 # SKIP Disabled ZA for VL 3168
6489 10:55:00.610180 # ok 594 # SKIP Get and set data for VL 3168
6490 10:55:00.610272 # ok 595 Set VL 3184
6491 10:55:00.610362 # ok 596 # SKIP Disabled ZA for VL 3184
6492 10:55:00.610470 # ok 597 # SKIP Get and set data for VL 3184
6493 10:55:00.610562 # ok 598 Set VL 3200
6494 10:55:00.610651 # ok 599 # SKIP Disabled ZA for VL 3200
6495 10:55:00.610740 # ok 600 # SKIP Get and set data for VL 3200
6496 10:55:00.610828 # ok 601 Set VL 3216
6497 10:55:00.610932 # ok 602 # SKIP Disabled ZA for VL 3216
6498 10:55:00.611027 # ok 603 # SKIP Get and set data for VL 3216
6499 10:55:00.611117 # ok 604 Set VL 3232
6500 10:55:00.611204 # ok 605 # SKIP Disabled ZA for VL 3232
6501 10:55:00.611290 # ok 606 # SKIP Get and set data for VL 3232
6502 10:55:00.611377 # ok 607 Set VL 3248
6503 10:55:00.611466 # ok 608 # SKIP Disabled ZA for VL 3248
6504 10:55:00.611572 # ok 609 # SKIP Get and set data for VL 3248
6505 10:55:00.611664 # ok 610 Set VL 3264
6506 10:55:00.611752 # ok 611 # SKIP Disabled ZA for VL 3264
6507 10:55:00.614192 # ok 612 # SKIP Get and set data for VL 3264
6508 10:55:00.614377 # ok 613 Set VL 3280
6509 10:55:00.614512 # ok 614 # SKIP Disabled ZA for VL 3280
6510 10:55:00.614647 # ok 615 # SKIP Get and set data for VL 3280
6511 10:55:00.615108 # ok 616 Set VL 3296
6512 10:55:00.615256 # ok 617 # SKIP Disabled ZA for VL 3296
6513 10:55:00.615382 # ok 618 # SKIP Get and set data for VL 3296
6514 10:55:00.615504 # ok 619 Set VL 3312
6515 10:55:00.615623 # ok 620 # SKIP Disabled ZA for VL 3312
6516 10:55:00.615742 # ok 621 # SKIP Get and set data for VL 3312
6517 10:55:00.615859 # ok 622 Set VL 3328
6518 10:55:00.615978 # ok 623 # SKIP Disabled ZA for VL 3328
6519 10:55:00.616097 # ok 624 # SKIP Get and set data for VL 3328
6520 10:55:00.616216 # ok 625 Set VL 3344
6521 10:55:00.616335 # ok 626 # SKIP Disabled ZA for VL 3344
6522 10:55:00.619088 # ok 627 # SKIP Get and set data for VL 3344
6523 10:55:00.619479 # ok 628 Set VL 3360
6524 10:55:00.620009 # ok 629 # SKIP Disabled ZA for VL 3360
6525 10:55:00.620425 # ok 630 # SKIP Get and set data for VL 3360
6526 10:55:00.620587 # ok 631 Set VL 3376
6527 10:55:00.620714 # ok 632 # SKIP Disabled ZA for VL 3376
6528 10:55:00.620837 # ok 633 # SKIP Get and set data for VL 3376
6529 10:55:00.620956 # ok 634 Set VL 3392
6530 10:55:00.621098 # ok 635 # SKIP Disabled ZA for VL 3392
6531 10:55:00.621241 # ok 636 # SKIP Get and set data for VL 3392
6532 10:55:00.621386 # ok 637 Set VL 3408
6533 10:55:00.621524 # ok 638 # SKIP Disabled ZA for VL 3408
6534 10:55:00.621669 # ok 639 # SKIP Get and set data for VL 3408
6535 10:55:00.621857 # ok 640 Set VL 3424
6536 10:55:00.622023 # ok 641 # SKIP Disabled ZA for VL 3424
6537 10:55:00.622177 # ok 642 # SKIP Get and set data for VL 3424
6538 10:55:00.622357 # ok 643 Set VL 3440
6539 10:55:00.622556 # ok 644 # SKIP Disabled ZA for VL 3440
6540 10:55:00.622788 # ok 645 # SKIP Get and set data for VL 3440
6541 10:55:00.623065 # ok 646 Set VL 3456
6542 10:55:00.623239 # ok 647 # SKIP Disabled ZA for VL 3456
6543 10:55:00.623367 # ok 648 # SKIP Get and set data for VL 3456
6544 10:55:00.623484 # ok 649 Set VL 3472
6545 10:55:00.623601 # ok 650 # SKIP Disabled ZA for VL 3472
6546 10:55:00.623718 # ok 651 # SKIP Get and set data for VL 3472
6547 10:55:00.623834 # ok 652 Set VL 3488
6548 10:55:00.623950 # ok 653 # SKIP Disabled ZA for VL 3488
6549 10:55:00.624065 # ok 654 # SKIP Get and set data for VL 3488
6550 10:55:00.624181 # ok 655 Set VL 3504
6551 10:55:00.624296 # ok 656 # SKIP Disabled ZA for VL 3504
6552 10:55:00.624412 # ok 657 # SKIP Get and set data for VL 3504
6553 10:55:00.624528 # ok 658 Set VL 3520
6554 10:55:00.624643 # ok 659 # SKIP Disabled ZA for VL 3520
6555 10:55:00.624784 # ok 660 # SKIP Get and set data for VL 3520
6556 10:55:00.624907 # ok 661 Set VL 3536
6557 10:55:00.628267 # ok 662 # SKIP Disabled ZA for VL 3536
6558 10:55:00.628484 # ok 663 # SKIP Get and set data for VL 3536
6559 10:55:00.628655 # ok 664 Set VL 3552
6560 10:55:00.629044 # ok 665 # SKIP Disabled ZA for VL 3552
6561 10:55:00.629276 # ok 666 # SKIP Get and set data for VL 3552
6562 10:55:00.629491 # ok 667 Set VL 3568
6563 10:55:00.629715 # ok 668 # SKIP Disabled ZA for VL 3568
6564 10:55:00.629938 # ok 669 # SKIP Get and set data for VL 3568
6565 10:55:00.630154 # ok 670 Set VL 3584
6566 10:55:00.630343 # ok 671 # SKIP Disabled ZA for VL 3584
6567 10:55:00.630538 # ok 672 # SKIP Get and set data for VL 3584
6568 10:55:00.630737 # ok 673 Set VL 3600
6569 10:55:00.630915 # ok 674 # SKIP Disabled ZA for VL 3600
6570 10:55:00.631139 # ok 675 # SKIP Get and set data for VL 3600
6571 10:55:00.631316 # ok 676 Set VL 3616
6572 10:55:00.631448 # ok 677 # SKIP Disabled ZA for VL 3616
6573 10:55:00.631567 # ok 678 # SKIP Get and set data for VL 3616
6574 10:55:00.631683 # ok 679 Set VL 3632
6575 10:55:00.631798 # ok 680 # SKIP Disabled ZA for VL 3632
6576 10:55:00.631914 # ok 681 # SKIP Get and set data for VL 3632
6577 10:55:00.632029 # ok 682 Set VL 3648
6578 10:55:00.632143 # ok 683 # SKIP Disabled ZA for VL 3648
6579 10:55:00.632258 # ok 684 # SKIP Get and set data for VL 3648
6580 10:55:00.632373 # ok 685 Set VL 3664
6581 10:55:00.632487 # ok 686 # SKIP Disabled ZA for VL 3664
6582 10:55:00.632603 # ok 687 # SKIP Get and set data for VL 3664
6583 10:55:00.632719 # ok 688 Set VL 3680
6584 10:55:00.632834 # ok 689 # SKIP Disabled ZA for VL 3680
6585 10:55:00.632950 # ok 690 # SKIP Get and set data for VL 3680
6586 10:55:00.633068 # ok 691 Set VL 3696
6587 10:55:00.633183 # ok 692 # SKIP Disabled ZA for VL 3696
6588 10:55:00.633298 # ok 693 # SKIP Get and set data for VL 3696
6589 10:55:00.633413 # ok 694 Set VL 3712
6590 10:55:00.633529 # ok 695 # SKIP Disabled ZA for VL 3712
6591 10:55:00.633644 # ok 696 # SKIP Get and set data for VL 3712
6592 10:55:00.633897 # ok 697 Set VL 3728
6593 10:55:00.644076 # ok 698 # SKIP Disabled ZA for VL 3728
6594 10:55:00.644380 # ok 699 # SKIP Get and set data for VL 3728
6595 10:55:00.644545 # ok 700 Set VL 3744
6596 10:55:00.645017 # ok 701 # SKIP Disabled ZA for VL 3744
6597 10:55:00.645213 # ok 702 # SKIP Get and set data for VL 3744
6598 10:55:00.645379 # ok 703 Set VL 3760
6599 10:55:00.645538 # ok 704 # SKIP Disabled ZA for VL 3760
6600 10:55:00.645725 # ok 705 # SKIP Get and set data for VL 3760
6601 10:55:00.645894 # ok 706 Set VL 3776
6602 10:55:00.646043 # ok 707 # SKIP Disabled ZA for VL 3776
6603 10:55:00.646191 # ok 708 # SKIP Get and set data for VL 3776
6604 10:55:00.646318 # ok 709 Set VL 3792
6605 10:55:00.646444 # ok 710 # SKIP Disabled ZA for VL 3792
6606 10:55:00.646568 # ok 711 # SKIP Get and set data for VL 3792
6607 10:55:00.646722 # ok 712 Set VL 3808
6608 10:55:00.646852 # ok 713 # SKIP Disabled ZA for VL 3808
6609 10:55:00.646987 # ok 714 # SKIP Get and set data for VL 3808
6610 10:55:00.647170 # ok 715 Set VL 3824
6611 10:55:00.647299 # ok 716 # SKIP Disabled ZA for VL 3824
6612 10:55:00.647422 # ok 717 # SKIP Get and set data for VL 3824
6613 10:55:00.647548 # ok 718 Set VL 3840
6614 10:55:00.647670 # ok 719 # SKIP Disabled ZA for VL 3840
6615 10:55:00.647794 # ok 720 # SKIP Get and set data for VL 3840
6616 10:55:00.647920 # ok 721 Set VL 3856
6617 10:55:00.648042 # ok 722 # SKIP Disabled ZA for VL 3856
6618 10:55:00.648164 # ok 723 # SKIP Get and set data for VL 3856
6619 10:55:00.648285 # ok 724 Set VL 3872
6620 10:55:00.648401 # ok 725 # SKIP Disabled ZA for VL 3872
6621 10:55:00.648522 # ok 726 # SKIP Get and set data for VL 3872
6622 10:55:00.648637 # ok 727 Set VL 3888
6623 10:55:00.648784 # ok 728 # SKIP Disabled ZA for VL 3888
6624 10:55:00.648932 # ok 729 # SKIP Get and set data for VL 3888
6625 10:55:00.649103 # ok 730 Set VL 3904
6626 10:55:00.649235 # ok 731 # SKIP Disabled ZA for VL 3904
6627 10:55:00.649352 # ok 732 # SKIP Get and set data for VL 3904
6628 10:55:00.649467 # ok 733 Set VL 3920
6629 10:55:00.649589 # ok 734 # SKIP Disabled ZA for VL 3920
6630 10:55:00.649719 # ok 735 # SKIP Get and set data for VL 3920
6631 10:55:00.649834 # ok 736 Set VL 3936
6632 10:55:00.649949 # ok 737 # SKIP Disabled ZA for VL 3936
6633 10:55:00.650065 # ok 738 # SKIP Get and set data for VL 3936
6634 10:55:00.650184 # ok 739 Set VL 3952
6635 10:55:00.650298 # ok 740 # SKIP Disabled ZA for VL 3952
6636 10:55:00.650414 # ok 741 # SKIP Get and set data for VL 3952
6637 10:55:00.650529 # ok 742 Set VL 3968
6638 10:55:00.650642 # ok 743 # SKIP Disabled ZA for VL 3968
6639 10:55:00.650758 # ok 744 # SKIP Get and set data for VL 3968
6640 10:55:00.660695 # ok 745 Set VL 3984
6641 10:55:00.661131 # ok 746 # SKIP Disabled ZA for VL 3984
6642 10:55:00.661223 # ok 747 # SKIP Get and set data for VL 3984
6643 10:55:00.661300 # ok 748 Set VL 4000
6644 10:55:00.661366 # ok 749 # SKIP Disabled ZA for VL 4000
6645 10:55:00.661447 # ok 750 # SKIP Get and set data for VL 4000
6646 10:55:00.661529 # ok 751 Set VL 4016
6647 10:55:00.661610 # ok 752 # SKIP Disabled ZA for VL 4016
6648 10:55:00.661699 # ok 753 # SKIP Get and set data for VL 4016
6649 10:55:00.661804 # ok 754 Set VL 4032
6650 10:55:00.661892 # ok 755 # SKIP Disabled ZA for VL 4032
6651 10:55:00.661974 # ok 756 # SKIP Get and set data for VL 4032
6652 10:55:00.662052 # ok 757 Set VL 4048
6653 10:55:00.662121 # ok 758 # SKIP Disabled ZA for VL 4048
6654 10:55:00.662203 # ok 759 # SKIP Get and set data for VL 4048
6655 10:55:00.662290 # ok 760 Set VL 4064
6656 10:55:00.662398 # ok 761 # SKIP Disabled ZA for VL 4064
6657 10:55:00.662504 # ok 762 # SKIP Get and set data for VL 4064
6658 10:55:00.662606 # ok 763 Set VL 4080
6659 10:55:00.662710 # ok 764 # SKIP Disabled ZA for VL 4080
6660 10:55:00.662819 # ok 765 # SKIP Get and set data for VL 4080
6661 10:55:00.662936 # ok 766 Set VL 4096
6662 10:55:00.663056 # ok 767 # SKIP Disabled ZA for VL 4096
6663 10:55:00.663171 # ok 768 # SKIP Get and set data for VL 4096
6664 10:55:00.663266 # ok 769 Set VL 4112
6665 10:55:00.663345 # ok 770 # SKIP Disabled ZA for VL 4112
6666 10:55:00.663423 # ok 771 # SKIP Get and set data for VL 4112
6667 10:55:00.663492 # ok 772 Set VL 4128
6668 10:55:00.663555 # ok 773 # SKIP Disabled ZA for VL 4128
6669 10:55:00.676238 # ok 774 # SKIP Get and set data for VL 4128
6670 10:55:00.676492 # ok 775 Set VL 4144
6671 10:55:00.676784 # ok 776 # SKIP Disabled ZA for VL 4144
6672 10:55:00.676871 # ok 777 # SKIP Get and set data for VL 4144
6673 10:55:00.676951 # ok 778 Set VL 4160
6674 10:55:00.677030 # ok 779 # SKIP Disabled ZA for VL 4160
6675 10:55:00.677107 # ok 780 # SKIP Get and set data for VL 4160
6676 10:55:00.677185 # ok 781 Set VL 4176
6677 10:55:00.677261 # ok 782 # SKIP Disabled ZA for VL 4176
6678 10:55:00.677342 # ok 783 # SKIP Get and set data for VL 4176
6679 10:55:00.677438 # ok 784 Set VL 4192
6680 10:55:00.677519 # ok 785 # SKIP Disabled ZA for VL 4192
6681 10:55:00.677597 # ok 786 # SKIP Get and set data for VL 4192
6682 10:55:00.677683 # ok 787 Set VL 4208
6683 10:55:00.677761 # ok 788 # SKIP Disabled ZA for VL 4208
6684 10:55:00.677839 # ok 789 # SKIP Get and set data for VL 4208
6685 10:55:00.677917 # ok 790 Set VL 4224
6686 10:55:00.677993 # ok 791 # SKIP Disabled ZA for VL 4224
6687 10:55:00.678071 # ok 792 # SKIP Get and set data for VL 4224
6688 10:55:00.678167 # ok 793 Set VL 4240
6689 10:55:00.678250 # ok 794 # SKIP Disabled ZA for VL 4240
6690 10:55:00.678328 # ok 795 # SKIP Get and set data for VL 4240
6691 10:55:00.678405 # ok 796 Set VL 4256
6692 10:55:00.678482 # ok 797 # SKIP Disabled ZA for VL 4256
6693 10:55:00.678559 # ok 798 # SKIP Get and set data for VL 4256
6694 10:55:00.678637 # ok 799 Set VL 4272
6695 10:55:00.678714 # ok 800 # SKIP Disabled ZA for VL 4272
6696 10:55:00.678791 # ok 801 # SKIP Get and set data for VL 4272
6697 10:55:00.678885 # ok 802 Set VL 4288
6698 10:55:00.678965 # ok 803 # SKIP Disabled ZA for VL 4288
6699 10:55:00.679043 # ok 804 # SKIP Get and set data for VL 4288
6700 10:55:00.679126 # ok 805 Set VL 4304
6701 10:55:00.679203 # ok 806 # SKIP Disabled ZA for VL 4304
6702 10:55:00.679280 # ok 807 # SKIP Get and set data for VL 4304
6703 10:55:00.679358 # ok 808 Set VL 4320
6704 10:55:00.679451 # ok 809 # SKIP Disabled ZA for VL 4320
6705 10:55:00.679531 # ok 810 # SKIP Get and set data for VL 4320
6706 10:55:00.679609 # ok 811 Set VL 4336
6707 10:55:00.679686 # ok 812 # SKIP Disabled ZA for VL 4336
6708 10:55:00.679763 # ok 813 # SKIP Get and set data for VL 4336
6709 10:55:00.679841 # ok 814 Set VL 4352
6710 10:55:00.695311 # ok 815 # SKIP Disabled ZA for VL 4352
6711 10:55:00.696411 # ok 816 # SKIP Get and set data for VL 4352
6712 10:55:00.696527 # ok 817 Set VL 4368
6713 10:55:00.696609 # ok 818 # SKIP Disabled ZA for VL 4368
6714 10:55:00.696702 # ok 819 # SKIP Get and set data for VL 4368
6715 10:55:00.696784 # ok 820 Set VL 4384
6716 10:55:00.696863 # ok 821 # SKIP Disabled ZA for VL 4384
6717 10:55:00.697695 # ok 822 # SKIP Get and set data for VL 4384
6718 10:55:00.697809 # ok 823 Set VL 4400
6719 10:55:00.697893 # ok 824 # SKIP Disabled ZA for VL 4400
6720 10:55:00.697972 # ok 825 # SKIP Get and set data for VL 4400
6721 10:55:00.698063 # ok 826 Set VL 4416
6722 10:55:00.698143 # ok 827 # SKIP Disabled ZA for VL 4416
6723 10:55:00.698227 # ok 828 # SKIP Get and set data for VL 4416
6724 10:55:00.698318 # ok 829 Set VL 4432
6725 10:55:00.698398 # ok 830 # SKIP Disabled ZA for VL 4432
6726 10:55:00.698488 # ok 831 # SKIP Get and set data for VL 4432
6727 10:55:00.698569 # ok 832 Set VL 4448
6728 10:55:00.698661 # ok 833 # SKIP Disabled ZA for VL 4448
6729 10:55:00.698741 # ok 834 # SKIP Get and set data for VL 4448
6730 10:55:00.699009 # ok 835 Set VL 4464
6731 10:55:00.699091 # ok 836 # SKIP Disabled ZA for VL 4464
6732 10:55:00.699170 # ok 837 # SKIP Get and set data for VL 4464
6733 10:55:00.699248 # ok 838 Set VL 4480
6734 10:55:00.699325 # ok 839 # SKIP Disabled ZA for VL 4480
6735 10:55:00.699403 # ok 840 # SKIP Get and set data for VL 4480
6736 10:55:00.699481 # ok 841 Set VL 4496
6737 10:55:00.699572 # ok 842 # SKIP Disabled ZA for VL 4496
6738 10:55:00.699652 # ok 843 # SKIP Get and set data for VL 4496
6739 10:55:00.702879 # ok 844 Set VL 4512
6740 10:55:00.703039 # ok 845 # SKIP Disabled ZA for VL 4512
6741 10:55:00.703309 # ok 846 # SKIP Get and set data for VL 4512
6742 10:55:00.703378 # ok 847 Set VL 4528
6743 10:55:00.703438 # ok 848 # SKIP Disabled ZA for VL 4528
6744 10:55:00.705612 # ok 849 # SKIP Get and set data for VL 4528
6745 10:55:00.705732 # ok 850 Set VL 4544
6746 10:55:00.706186 # ok 851 # SKIP Disabled ZA for VL 4544
6747 10:55:00.706271 # ok 852 # SKIP Get and set data for VL 4544
6748 10:55:00.706350 # ok 853 Set VL 4560
6749 10:55:00.706427 # ok 854 # SKIP Disabled ZA for VL 4560
6750 10:55:00.706505 # ok 855 # SKIP Get and set data for VL 4560
6751 10:55:00.706584 # ok 856 Set VL 4576
6752 10:55:00.706677 # ok 857 # SKIP Disabled ZA for VL 4576
6753 10:55:00.706758 # ok 858 # SKIP Get and set data for VL 4576
6754 10:55:00.706837 # ok 859 Set VL 4592
6755 10:55:00.706916 # ok 860 # SKIP Disabled ZA for VL 4592
6756 10:55:00.706998 # ok 861 # SKIP Get and set data for VL 4592
6757 10:55:00.707115 # ok 862 Set VL 4608
6758 10:55:00.707208 # ok 863 # SKIP Disabled ZA for VL 4608
6759 10:55:00.707308 # ok 864 # SKIP Get and set data for VL 4608
6760 10:55:00.707390 # ok 865 Set VL 4624
6761 10:55:00.707470 # ok 866 # SKIP Disabled ZA for VL 4624
6762 10:55:00.707549 # ok 867 # SKIP Get and set data for VL 4624
6763 10:55:00.707628 # ok 868 Set VL 4640
6764 10:55:00.707706 # ok 869 # SKIP Disabled ZA for VL 4640
6765 10:55:00.707784 # ok 870 # SKIP Get and set data for VL 4640
6766 10:55:00.707862 # ok 871 Set VL 4656
6767 10:55:00.711196 # ok 872 # SKIP Disabled ZA for VL 4656
6768 10:55:00.716992 # ok 873 # SKIP Get and set data for VL 4656
6769 10:55:00.717232 # ok 874 Set VL 4672
6770 10:55:00.717529 # ok 875 # SKIP Disabled ZA for VL 4672
6771 10:55:00.717624 # ok 876 # SKIP Get and set data for VL 4672
6772 10:55:00.717722 # ok 877 Set VL 4688
6773 10:55:00.717810 # ok 878 # SKIP Disabled ZA for VL 4688
6774 10:55:00.717898 # ok 879 # SKIP Get and set data for VL 4688
6775 10:55:00.717999 # ok 880 Set VL 4704
6776 10:55:00.718088 # ok 881 # SKIP Disabled ZA for VL 4704
6777 10:55:00.718171 # ok 882 # SKIP Get and set data for VL 4704
6778 10:55:00.718256 # ok 883 Set VL 4720
6779 10:55:00.718339 # ok 884 # SKIP Disabled ZA for VL 4720
6780 10:55:00.718442 # ok 885 # SKIP Get and set data for VL 4720
6781 10:55:00.718529 # ok 886 Set VL 4736
6782 10:55:00.718612 # ok 887 # SKIP Disabled ZA for VL 4736
6783 10:55:00.718697 # ok 888 # SKIP Get and set data for VL 4736
6784 10:55:00.718799 # ok 889 Set VL 4752
6785 10:55:00.718886 # ok 890 # SKIP Disabled ZA for VL 4752
6786 10:55:00.718970 # ok 891 # SKIP Get and set data for VL 4752
6787 10:55:00.719061 # ok 892 Set VL 4768
6788 10:55:00.719160 # ok 893 # SKIP Disabled ZA for VL 4768
6789 10:55:00.719244 # ok 894 # SKIP Get and set data for VL 4768
6790 10:55:00.724581 # ok 895 Set VL 4784
6791 10:55:00.725041 # ok 896 # SKIP Disabled ZA for VL 4784
6792 10:55:00.725144 # ok 897 # SKIP Get and set data for VL 4784
6793 10:55:00.725234 # ok 898 Set VL 4800
6794 10:55:00.725322 # ok 899 # SKIP Disabled ZA for VL 4800
6795 10:55:00.725412 # ok 900 # SKIP Get and set data for VL 4800
6796 10:55:00.725498 # ok 901 Set VL 4816
6797 10:55:00.725602 # ok 902 # SKIP Disabled ZA for VL 4816
6798 10:55:00.725700 # ok 903 # SKIP Get and set data for VL 4816
6799 10:55:00.725783 # ok 904 Set VL 4832
6800 10:55:00.725863 # ok 905 # SKIP Disabled ZA for VL 4832
6801 10:55:00.725946 # ok 906 # SKIP Get and set data for VL 4832
6802 10:55:00.726051 # ok 907 Set VL 4848
6803 10:55:00.726137 # ok 908 # SKIP Disabled ZA for VL 4848
6804 10:55:00.726218 # ok 909 # SKIP Get and set data for VL 4848
6805 10:55:00.726325 # ok 910 Set VL 4864
6806 10:55:00.726412 # ok 911 # SKIP Disabled ZA for VL 4864
6807 10:55:00.726494 # ok 912 # SKIP Get and set data for VL 4864
6808 10:55:00.726591 # ok 913 Set VL 4880
6809 10:55:00.726691 # ok 914 # SKIP Disabled ZA for VL 4880
6810 10:55:00.726796 # ok 915 # SKIP Get and set data for VL 4880
6811 10:55:00.726882 # ok 916 Set VL 4896
6812 10:55:00.727181 # ok 917 # SKIP Disabled ZA for VL 4896
6813 10:55:00.727283 # ok 918 # SKIP Get and set data for VL 4896
6814 10:55:00.727365 # ok 919 Set VL 4912
6815 10:55:00.732562 # ok 920 # SKIP Disabled ZA for VL 4912
6816 10:55:00.732797 # ok 921 # SKIP Get and set data for VL 4912
6817 10:55:00.732890 # ok 922 Set VL 4928
6818 10:55:00.732997 # ok 923 # SKIP Disabled ZA for VL 4928
6819 10:55:00.733086 # ok 924 # SKIP Get and set data for VL 4928
6820 10:55:00.733173 # ok 925 Set VL 4944
6821 10:55:00.733260 # ok 926 # SKIP Disabled ZA for VL 4944
6822 10:55:00.733365 # ok 927 # SKIP Get and set data for VL 4944
6823 10:55:00.733456 # ok 928 Set VL 4960
6824 10:55:00.733541 # ok 929 # SKIP Disabled ZA for VL 4960
6825 10:55:00.733626 # ok 930 # SKIP Get and set data for VL 4960
6826 10:55:00.733721 # ok 931 Set VL 4976
6827 10:55:00.733824 # ok 932 # SKIP Disabled ZA for VL 4976
6828 10:55:00.733914 # ok 933 # SKIP Get and set data for VL 4976
6829 10:55:00.734001 # ok 934 Set VL 4992
6830 10:55:00.734082 # ok 935 # SKIP Disabled ZA for VL 4992
6831 10:55:00.734182 # ok 936 # SKIP Get and set data for VL 4992
6832 10:55:00.734270 # ok 937 Set VL 5008
6833 10:55:00.734371 # ok 938 # SKIP Disabled ZA for VL 5008
6834 10:55:00.734484 # ok 939 # SKIP Get and set data for VL 5008
6835 10:55:00.734585 # ok 940 Set VL 5024
6836 10:55:00.734685 # ok 941 # SKIP Disabled ZA for VL 5024
6837 10:55:00.734784 # ok 942 # SKIP Get and set data for VL 5024
6838 10:55:00.734871 # ok 943 Set VL 5040
6839 10:55:00.734969 # ok 944 # SKIP Disabled ZA for VL 5040
6840 10:55:00.735254 # ok 945 # SKIP Get and set data for VL 5040
6841 10:55:00.735346 # ok 946 Set VL 5056
6842 10:55:00.740636 # ok 947 # SKIP Disabled ZA for VL 5056
6843 10:55:00.741202 # ok 948 # SKIP Get and set data for VL 5056
6844 10:55:00.741457 # ok 949 Set VL 5072
6845 10:55:00.741601 # ok 950 # SKIP Disabled ZA for VL 5072
6846 10:55:00.741743 # ok 951 # SKIP Get and set data for VL 5072
6847 10:55:00.741874 # ok 952 Set VL 5088
6848 10:55:00.742000 # ok 953 # SKIP Disabled ZA for VL 5088
6849 10:55:00.742158 # ok 954 # SKIP Get and set data for VL 5088
6850 10:55:00.742299 # ok 955 Set VL 5104
6851 10:55:00.742425 # ok 956 # SKIP Disabled ZA for VL 5104
6852 10:55:00.742553 # ok 957 # SKIP Get and set data for VL 5104
6853 10:55:00.742682 # ok 958 Set VL 5120
6854 10:55:00.742805 # ok 959 # SKIP Disabled ZA for VL 5120
6855 10:55:00.742928 # ok 960 # SKIP Get and set data for VL 5120
6856 10:55:00.743112 # ok 961 Set VL 5136
6857 10:55:00.743272 # ok 962 # SKIP Disabled ZA for VL 5136
6858 10:55:00.743395 # ok 963 # SKIP Get and set data for VL 5136
6859 10:55:00.743512 # ok 964 Set VL 5152
6860 10:55:00.743676 # ok 965 # SKIP Disabled ZA for VL 5152
6861 10:55:00.743804 # ok 966 # SKIP Get and set data for VL 5152
6862 10:55:00.743919 # ok 967 Set VL 5168
6863 10:55:00.744034 # ok 968 # SKIP Disabled ZA for VL 5168
6864 10:55:00.744176 # ok 969 # SKIP Get and set data for VL 5168
6865 10:55:00.744303 # ok 970 Set VL 5184
6866 10:55:00.746556 # ok 971 # SKIP Disabled ZA for VL 5184
6867 10:55:00.747131 # ok 972 # SKIP Get and set data for VL 5184
6868 10:55:00.747300 # ok 973 Set VL 5200
6869 10:55:00.747422 # ok 974 # SKIP Disabled ZA for VL 5200
6870 10:55:00.747561 # ok 975 # SKIP Get and set data for VL 5200
6871 10:55:00.747705 # ok 976 Set VL 5216
6872 10:55:00.747823 # ok 977 # SKIP Disabled ZA for VL 5216
6873 10:55:00.747970 # ok 978 # SKIP Get and set data for VL 5216
6874 10:55:00.748179 # ok 979 Set VL 5232
6875 10:55:00.748317 # ok 980 # SKIP Disabled ZA for VL 5232
6876 10:55:00.748449 # ok 981 # SKIP Get and set data for VL 5232
6877 10:55:00.748638 # ok 982 Set VL 5248
6878 10:55:00.748804 # ok 983 # SKIP Disabled ZA for VL 5248
6879 10:55:00.748955 # ok 984 # SKIP Get and set data for VL 5248
6880 10:55:00.749125 # ok 985 Set VL 5264
6881 10:55:00.749326 # ok 986 # SKIP Disabled ZA for VL 5264
6882 10:55:00.749465 # ok 987 # SKIP Get and set data for VL 5264
6883 10:55:00.749583 # ok 988 Set VL 5280
6884 10:55:00.749717 # ok 989 # SKIP Disabled ZA for VL 5280
6885 10:55:00.749835 # ok 990 # SKIP Get and set data for VL 5280
6886 10:55:00.749951 # ok 991 Set VL 5296
6887 10:55:00.750066 # ok 992 # SKIP Disabled ZA for VL 5296
6888 10:55:00.750181 # ok 993 # SKIP Get and set data for VL 5296
6889 10:55:00.750297 # ok 994 Set VL 5312
6890 10:55:00.750438 # ok 995 # SKIP Disabled ZA for VL 5312
6891 10:55:00.750560 # ok 996 # SKIP Get and set data for VL 5312
6892 10:55:00.750682 # ok 997 Set VL 5328
6893 10:55:00.750798 # ok 998 # SKIP Disabled ZA for VL 5328
6894 10:55:00.750913 # ok 999 # SKIP Get and set data for VL 5328
6895 10:55:00.751029 # ok 1000 Set VL 5344
6896 10:55:00.751199 # ok 1001 # SKIP Disabled ZA for VL 5344
6897 10:55:00.751328 # ok 1002 # SKIP Get and set data for VL 5344
6898 10:55:00.751458 # ok 1003 Set VL 5360
6899 10:55:00.751604 # ok 1004 # SKIP Disabled ZA for VL 5360
6900 10:55:00.751730 # ok 1005 # SKIP Get and set data for VL 5360
6901 10:55:00.751849 # ok 1006 Set VL 5376
6902 10:55:00.751966 # ok 1007 # SKIP Disabled ZA for VL 5376
6903 10:55:00.752084 # ok 1008 # SKIP Get and set data for VL 5376
6904 10:55:00.752201 # ok 1009 Set VL 5392
6905 10:55:00.752316 # ok 1010 # SKIP Disabled ZA for VL 5392
6906 10:55:00.754358 # ok 1011 # SKIP Get and set data for VL 5392
6907 10:55:00.754606 # ok 1012 Set VL 5408
6908 10:55:00.754996 # ok 1013 # SKIP Disabled ZA for VL 5408
6909 10:55:00.755101 # ok 1014 # SKIP Get and set data for VL 5408
6910 10:55:00.755191 # ok 1015 Set VL 5424
6911 10:55:00.755277 # ok 1016 # SKIP Disabled ZA for VL 5424
6912 10:55:00.755365 # ok 1017 # SKIP Get and set data for VL 5424
6913 10:55:00.755450 # ok 1018 Set VL 5440
6914 10:55:00.755552 # ok 1019 # SKIP Disabled ZA for VL 5440
6915 10:55:00.761601 # ok 1020 # SKIP Get and set data for VL 5440
6916 10:55:00.762057 # ok 1021 Set VL 5456
6917 10:55:00.762159 # ok 1022 # SKIP Disabled ZA for VL 5456
6918 10:55:00.762243 # ok 1023 # SKIP Get and set data for VL 5456
6919 10:55:00.762323 # ok 1024 Set VL 5472
6920 10:55:00.762403 # ok 1025 # SKIP Disabled ZA for VL 5472
6921 10:55:00.762482 # ok 1026 # SKIP Get and set data for VL 5472
6922 10:55:00.762577 # ok 1027 Set VL 5488
6923 10:55:00.762659 # ok 1028 # SKIP Disabled ZA for VL 5488
6924 10:55:00.762740 # ok 1029 # SKIP Get and set data for VL 5488
6925 10:55:00.762820 # ok 1030 Set VL 5504
6926 10:55:00.762900 # ok 1031 # SKIP Disabled ZA for VL 5504
6927 10:55:00.762996 # ok 1032 # SKIP Get and set data for VL 5504
6928 10:55:00.763079 # ok 1033 Set VL 5520
6929 10:55:00.763159 # ok 1034 # SKIP Disabled ZA for VL 5520
6930 10:55:00.763237 # ok 1035 # SKIP Get and set data for VL 5520
6931 10:55:00.763334 # ok 1036 Set VL 5536
6932 10:55:00.766991 # ok 1037 # SKIP Disabled ZA for VL 5536
6933 10:55:00.767379 # ok 1038 # SKIP Get and set data for VL 5536
6934 10:55:00.767472 # ok 1039 Set VL 5552
6935 10:55:00.768283 # ok 1040 # SKIP Disabled ZA for VL 5552
6936 10:55:00.768608 # ok 1041 # SKIP Get and set data for VL 5552
6937 10:55:00.768711 # ok 1042 Set VL 5568
6938 10:55:00.768800 # ok 1043 # SKIP Disabled ZA for VL 5568
6939 10:55:00.768901 # ok 1044 # SKIP Get and set data for VL 5568
6940 10:55:00.769002 # ok 1045 Set VL 5584
6941 10:55:00.769122 # ok 1046 # SKIP Disabled ZA for VL 5584
6942 10:55:00.769229 # ok 1047 # SKIP Get and set data for VL 5584
6943 10:55:00.769320 # ok 1048 Set VL 5600
6944 10:55:00.769408 # ok 1049 # SKIP Disabled ZA for VL 5600
6945 10:55:00.769494 # ok 1050 # SKIP Get and set data for VL 5600
6946 10:55:00.769596 # ok 1051 Set VL 5616
6947 10:55:00.769693 # ok 1052 # SKIP Disabled ZA for VL 5616
6948 10:55:00.770876 # ok 1053 # SKIP Get and set data for VL 5616
6949 10:55:00.771190 # ok 1054 Set VL 5632
6950 10:55:00.771608 # ok 1055 # SKIP Disabled ZA for VL 5632
6951 10:55:00.771770 # ok 1056 # SKIP Get and set data for VL 5632
6952 10:55:00.771918 # ok 1057 Set VL 5648
6953 10:55:00.775979 # ok 1058 # SKIP Disabled ZA for VL 5648
6954 10:55:00.776508 # ok 1059 # SKIP Get and set data for VL 5648
6955 10:55:00.776680 # ok 1060 Set VL 5664
6956 10:55:00.776806 # ok 1061 # SKIP Disabled ZA for VL 5664
6957 10:55:00.778136 # ok 1062 # SKIP Get and set data for VL 5664
6958 10:55:00.778334 # ok 1063 Set VL 5680
6959 10:55:00.778481 # ok 1064 # SKIP Disabled ZA for VL 5680
6960 10:55:00.778617 # ok 1065 # SKIP Get and set data for VL 5680
6961 10:55:00.778762 # ok 1066 Set VL 5696
6962 10:55:00.778932 # ok 1067 # SKIP Disabled ZA for VL 5696
6963 10:55:00.779116 # ok 1068 # SKIP Get and set data for VL 5696
6964 10:55:00.779299 # ok 1069 Set VL 5712
6965 10:55:00.779457 # ok 1070 # SKIP Disabled ZA for VL 5712
6966 10:55:00.779610 # ok 1071 # SKIP Get and set data for VL 5712
6967 10:55:00.779762 # ok 1072 Set VL 5728
6968 10:55:00.779915 # ok 1073 # SKIP Disabled ZA for VL 5728
6969 10:55:00.780069 # ok 1074 # SKIP Get and set data for VL 5728
6970 10:55:00.780225 # ok 1075 Set VL 5744
6971 10:55:00.780375 # ok 1076 # SKIP Disabled ZA for VL 5744
6972 10:55:00.780524 # ok 1077 # SKIP Get and set data for VL 5744
6973 10:55:00.780671 # ok 1078 Set VL 5760
6974 10:55:00.781018 # ok 1079 # SKIP Disabled ZA for VL 5760
6975 10:55:00.781100 # ok 1080 # SKIP Get and set data for VL 5760
6976 10:55:00.781164 # ok 1081 Set VL 5776
6977 10:55:00.781225 # ok 1082 # SKIP Disabled ZA for VL 5776
6978 10:55:00.781285 # ok 1083 # SKIP Get and set data for VL 5776
6979 10:55:00.781345 # ok 1084 Set VL 5792
6980 10:55:00.781405 # ok 1085 # SKIP Disabled ZA for VL 5792
6981 10:55:00.781464 # ok 1086 # SKIP Get and set data for VL 5792
6982 10:55:00.781524 # ok 1087 Set VL 5808
6983 10:55:00.781585 # ok 1088 # SKIP Disabled ZA for VL 5808
6984 10:55:00.781654 # ok 1089 # SKIP Get and set data for VL 5808
6985 10:55:00.781719 # ok 1090 Set VL 5824
6986 10:55:00.781779 # ok 1091 # SKIP Disabled ZA for VL 5824
6987 10:55:00.781839 # ok 1092 # SKIP Get and set data for VL 5824
6988 10:55:00.781900 # ok 1093 Set VL 5840
6989 10:55:00.781961 # ok 1094 # SKIP Disabled ZA for VL 5840
6990 10:55:00.782022 # ok 1095 # SKIP Get and set data for VL 5840
6991 10:55:00.782082 # ok 1096 Set VL 5856
6992 10:55:00.782143 # ok 1097 # SKIP Disabled ZA for VL 5856
6993 10:55:00.782204 # ok 1098 # SKIP Get and set data for VL 5856
6994 10:55:00.782264 # ok 1099 Set VL 5872
6995 10:55:00.786189 # ok 1100 # SKIP Disabled ZA for VL 5872
6996 10:55:00.786566 # ok 1101 # SKIP Get and set data for VL 5872
6997 10:55:00.786671 # ok 1102 Set VL 5888
6998 10:55:00.786755 # ok 1103 # SKIP Disabled ZA for VL 5888
6999 10:55:00.786836 # ok 1104 # SKIP Get and set data for VL 5888
7000 10:55:00.786930 # ok 1105 Set VL 5904
7001 10:55:00.787132 # ok 1106 # SKIP Disabled ZA for VL 5904
7002 10:55:00.787257 # ok 1107 # SKIP Get and set data for VL 5904
7003 10:55:00.787344 # ok 1108 Set VL 5920
7004 10:55:00.787426 # ok 1109 # SKIP Disabled ZA for VL 5920
7005 10:55:00.787795 # ok 1110 # SKIP Get and set data for VL 5920
7006 10:55:00.788020 # ok 1111 Set VL 5936
7007 10:55:00.788281 # ok 1112 # SKIP Disabled ZA for VL 5936
7008 10:55:00.788494 # ok 1113 # SKIP Get and set data for VL 5936
7009 10:55:00.788712 # ok 1114 Set VL 5952
7010 10:55:00.788935 # ok 1115 # SKIP Disabled ZA for VL 5952
7011 10:55:00.789149 # ok 1116 # SKIP Get and set data for VL 5952
7012 10:55:00.789408 # ok 1117 Set VL 5968
7013 10:55:00.789640 # ok 1118 # SKIP Disabled ZA for VL 5968
7014 10:55:00.789866 # ok 1119 # SKIP Get and set data for VL 5968
7015 10:55:00.790112 # ok 1120 Set VL 5984
7016 10:55:00.790304 # ok 1121 # SKIP Disabled ZA for VL 5984
7017 10:55:00.790532 # ok 1122 # SKIP Get and set data for VL 5984
7018 10:55:00.790738 # ok 1123 Set VL 6000
7019 10:55:00.790958 # ok 1124 # SKIP Disabled ZA for VL 6000
7020 10:55:00.791177 # ok 1125 # SKIP Get and set data for VL 6000
7021 10:55:00.791328 # ok 1126 Set VL 6016
7022 10:55:00.791450 # ok 1127 # SKIP Disabled ZA for VL 6016
7023 10:55:00.791570 # ok 1128 # SKIP Get and set data for VL 6016
7024 10:55:00.791719 # ok 1129 Set VL 6032
7025 10:55:00.791844 # ok 1130 # SKIP Disabled ZA for VL 6032
7026 10:55:00.791962 # ok 1131 # SKIP Get and set data for VL 6032
7027 10:55:00.792078 # ok 1132 Set VL 6048
7028 10:55:00.792195 # ok 1133 # SKIP Disabled ZA for VL 6048
7029 10:55:00.792342 # ok 1134 # SKIP Get and set data for VL 6048
7030 10:55:00.792515 # ok 1135 Set VL 6064
7031 10:55:00.792641 # ok 1136 # SKIP Disabled ZA for VL 6064
7032 10:55:00.792758 # ok 1137 # SKIP Get and set data for VL 6064
7033 10:55:00.792874 # ok 1138 Set VL 6080
7034 10:55:00.792989 # ok 1139 # SKIP Disabled ZA for VL 6080
7035 10:55:00.793103 # ok 1140 # SKIP Get and set data for VL 6080
7036 10:55:00.793220 # ok 1141 Set VL 6096
7037 10:55:00.793336 # ok 1142 # SKIP Disabled ZA for VL 6096
7038 10:55:00.793451 # ok 1143 # SKIP Get and set data for VL 6096
7039 10:55:00.793566 # ok 1144 Set VL 6112
7040 10:55:00.794248 # ok 1145 # SKIP Disabled ZA for VL 6112
7041 10:55:00.801323 # ok 1146 # SKIP Get and set data for VL 6112
7042 10:55:00.801692 # ok 1147 Set VL 6128
7043 10:55:00.802202 # ok 1148 # SKIP Disabled ZA for VL 6128
7044 10:55:00.802424 # ok 1149 # SKIP Get and set data for VL 6128
7045 10:55:00.802617 # ok 1150 Set VL 6144
7046 10:55:00.802790 # ok 1151 # SKIP Disabled ZA for VL 6144
7047 10:55:00.802942 # ok 1152 # SKIP Get and set data for VL 6144
7048 10:55:00.803106 # ok 1153 Set VL 6160
7049 10:55:00.803252 # ok 1154 # SKIP Disabled ZA for VL 6160
7050 10:55:00.803374 # ok 1155 # SKIP Get and set data for VL 6160
7051 10:55:00.803493 # ok 1156 Set VL 6176
7052 10:55:00.803605 # ok 1157 # SKIP Disabled ZA for VL 6176
7053 10:55:00.803752 # ok 1158 # SKIP Get and set data for VL 6176
7054 10:55:00.803874 # ok 1159 Set VL 6192
7055 10:55:00.803988 # ok 1160 # SKIP Disabled ZA for VL 6192
7056 10:55:00.804102 # ok 1161 # SKIP Get and set data for VL 6192
7057 10:55:00.804215 # ok 1162 Set VL 6208
7058 10:55:00.804327 # ok 1163 # SKIP Disabled ZA for VL 6208
7059 10:55:00.804440 # ok 1164 # SKIP Get and set data for VL 6208
7060 10:55:00.804553 # ok 1165 Set VL 6224
7061 10:55:00.804666 # ok 1166 # SKIP Disabled ZA for VL 6224
7062 10:55:00.812334 # ok 1167 # SKIP Get and set data for VL 6224
7063 10:55:00.812574 # ok 1168 Set VL 6240
7064 10:55:00.812660 # ok 1169 # SKIP Disabled ZA for VL 6240
7065 10:55:00.812951 # ok 1170 # SKIP Get and set data for VL 6240
7066 10:55:00.813055 # ok 1171 Set VL 6256
7067 10:55:00.813135 # ok 1172 # SKIP Disabled ZA for VL 6256
7068 10:55:00.813214 # ok 1173 # SKIP Get and set data for VL 6256
7069 10:55:00.813294 # ok 1174 Set VL 6272
7070 10:55:00.813390 # ok 1175 # SKIP Disabled ZA for VL 6272
7071 10:55:00.813473 # ok 1176 # SKIP Get and set data for VL 6272
7072 10:55:00.813552 # ok 1177 Set VL 6288
7073 10:55:00.813631 # ok 1178 # SKIP Disabled ZA for VL 6288
7074 10:55:00.813718 # ok 1179 # SKIP Get and set data for VL 6288
7075 10:55:00.813799 # ok 1180 Set VL 6304
7076 10:55:00.813892 # ok 1181 # SKIP Disabled ZA for VL 6304
7077 10:55:00.813972 # ok 1182 # SKIP Get and set data for VL 6304
7078 10:55:00.814050 # ok 1183 Set VL 6320
7079 10:55:00.814127 # ok 1184 # SKIP Disabled ZA for VL 6320
7080 10:55:00.814218 # ok 1185 # SKIP Get and set data for VL 6320
7081 10:55:00.814298 # ok 1186 Set VL 6336
7082 10:55:00.814375 # ok 1187 # SKIP Disabled ZA for VL 6336
7083 10:55:00.814460 # ok 1188 # SKIP Get and set data for VL 6336
7084 10:55:00.814538 # ok 1189 Set VL 6352
7085 10:55:00.814615 # ok 1190 # SKIP Disabled ZA for VL 6352
7086 10:55:00.814709 # ok 1191 # SKIP Get and set data for VL 6352
7087 10:55:00.814791 # ok 1192 Set VL 6368
7088 10:55:00.814868 # ok 1193 # SKIP Disabled ZA for VL 6368
7089 10:55:00.814947 # ok 1194 # SKIP Get and set data for VL 6368
7090 10:55:00.815024 # ok 1195 Set VL 6384
7091 10:55:00.815116 # ok 1196 # SKIP Disabled ZA for VL 6384
7092 10:55:00.815197 # ok 1197 # SKIP Get and set data for VL 6384
7093 10:55:00.815274 # ok 1198 Set VL 6400
7094 10:55:00.815351 # ok 1199 # SKIP Disabled ZA for VL 6400
7095 10:55:00.824287 # ok 1200 # SKIP Get and set data for VL 6400
7096 10:55:00.824889 # ok 1201 Set VL 6416
7097 10:55:00.825078 # ok 1202 # SKIP Disabled ZA for VL 6416
7098 10:55:00.825263 # ok 1203 # SKIP Get and set data for VL 6416
7099 10:55:00.825481 # ok 1204 Set VL 6432
7100 10:55:00.825716 # ok 1205 # SKIP Disabled ZA for VL 6432
7101 10:55:00.825902 # ok 1206 # SKIP Get and set data for VL 6432
7102 10:55:00.826111 # ok 1207 Set VL 6448
7103 10:55:00.826284 # ok 1208 # SKIP Disabled ZA for VL 6448
7104 10:55:00.826454 # ok 1209 # SKIP Get and set data for VL 6448
7105 10:55:00.826620 # ok 1210 Set VL 6464
7106 10:55:00.826783 # ok 1211 # SKIP Disabled ZA for VL 6464
7107 10:55:00.826951 # ok 1212 # SKIP Get and set data for VL 6464
7108 10:55:00.827118 # ok 1213 Set VL 6480
7109 10:55:00.827252 # ok 1214 # SKIP Disabled ZA for VL 6480
7110 10:55:00.827369 # ok 1215 # SKIP Get and set data for VL 6480
7111 10:55:00.827487 # ok 1216 Set VL 6496
7112 10:55:00.827631 # ok 1217 # SKIP Disabled ZA for VL 6496
7113 10:55:00.827755 # ok 1218 # SKIP Get and set data for VL 6496
7114 10:55:00.827872 # ok 1219 Set VL 6512
7115 10:55:00.827987 # ok 1220 # SKIP Disabled ZA for VL 6512
7116 10:55:00.828105 # ok 1221 # SKIP Get and set data for VL 6512
7117 10:55:00.828221 # ok 1222 Set VL 6528
7118 10:55:00.828335 # ok 1223 # SKIP Disabled ZA for VL 6528
7119 10:55:00.828450 # ok 1224 # SKIP Get and set data for VL 6528
7120 10:55:00.828565 # ok 1225 Set VL 6544
7121 10:55:00.828681 # ok 1226 # SKIP Disabled ZA for VL 6544
7122 10:55:00.835806 # ok 1227 # SKIP Get and set data for VL 6544
7123 10:55:00.836119 # ok 1228 Set VL 6560
7124 10:55:00.836547 # ok 1229 # SKIP Disabled ZA for VL 6560
7125 10:55:00.836748 # ok 1230 # SKIP Get and set data for VL 6560
7126 10:55:00.836924 # ok 1231 Set VL 6576
7127 10:55:00.837103 # ok 1232 # SKIP Disabled ZA for VL 6576
7128 10:55:00.837274 # ok 1233 # SKIP Get and set data for VL 6576
7129 10:55:00.837447 # ok 1234 Set VL 6592
7130 10:55:00.837622 # ok 1235 # SKIP Disabled ZA for VL 6592
7131 10:55:00.837860 # ok 1236 # SKIP Get and set data for VL 6592
7132 10:55:00.838111 # ok 1237 Set VL 6608
7133 10:55:00.838346 # ok 1238 # SKIP Disabled ZA for VL 6608
7134 10:55:00.838564 # ok 1239 # SKIP Get and set data for VL 6608
7135 10:55:00.838773 # ok 1240 Set VL 6624
7136 10:55:00.839042 # ok 1241 # SKIP Disabled ZA for VL 6624
7137 10:55:00.839312 # ok 1242 # SKIP Get and set data for VL 6624
7138 10:55:00.839465 # ok 1243 Set VL 6640
7139 10:55:00.839586 # ok 1244 # SKIP Disabled ZA for VL 6640
7140 10:55:00.839699 # ok 1245 # SKIP Get and set data for VL 6640
7141 10:55:00.839812 # ok 1246 Set VL 6656
7142 10:55:00.839925 # ok 1247 # SKIP Disabled ZA for VL 6656
7143 10:55:00.840039 # ok 1248 # SKIP Get and set data for VL 6656
7144 10:55:00.840154 # ok 1249 Set VL 6672
7145 10:55:00.840266 # ok 1250 # SKIP Disabled ZA for VL 6672
7146 10:55:00.840379 # ok 1251 # SKIP Get and set data for VL 6672
7147 10:55:00.840492 # ok 1252 Set VL 6688
7148 10:55:00.840604 # ok 1253 # SKIP Disabled ZA for VL 6688
7149 10:55:00.840718 # ok 1254 # SKIP Get and set data for VL 6688
7150 10:55:00.840864 # ok 1255 Set VL 6704
7151 10:55:00.840983 # ok 1256 # SKIP Disabled ZA for VL 6704
7152 10:55:00.841097 # ok 1257 # SKIP Get and set data for VL 6704
7153 10:55:00.841212 # ok 1258 Set VL 6720
7154 10:55:00.841325 # ok 1259 # SKIP Disabled ZA for VL 6720
7155 10:55:00.841439 # ok 1260 # SKIP Get and set data for VL 6720
7156 10:55:00.841551 # ok 1261 Set VL 6736
7157 10:55:00.841725 # ok 1262 # SKIP Disabled ZA for VL 6736
7158 10:55:00.841939 # ok 1263 # SKIP Get and set data for VL 6736
7159 10:55:00.842128 # ok 1264 Set VL 6752
7160 10:55:00.842316 # ok 1265 # SKIP Disabled ZA for VL 6752
7161 10:55:00.848123 # ok 1266 # SKIP Get and set data for VL 6752
7162 10:55:00.848437 # ok 1267 Set VL 6768
7163 10:55:00.848602 # ok 1268 # SKIP Disabled ZA for VL 6768
7164 10:55:00.849026 # ok 1269 # SKIP Get and set data for VL 6768
7165 10:55:00.849192 # ok 1270 Set VL 6784
7166 10:55:00.849317 # ok 1271 # SKIP Disabled ZA for VL 6784
7167 10:55:00.849439 # ok 1272 # SKIP Get and set data for VL 6784
7168 10:55:00.849557 # ok 1273 Set VL 6800
7169 10:55:00.849688 # ok 1274 # SKIP Disabled ZA for VL 6800
7170 10:55:00.849839 # ok 1275 # SKIP Get and set data for VL 6800
7171 10:55:00.850005 # ok 1276 Set VL 6816
7172 10:55:00.850184 # ok 1277 # SKIP Disabled ZA for VL 6816
7173 10:55:00.850401 # ok 1278 # SKIP Get and set data for VL 6816
7174 10:55:00.850619 # ok 1279 Set VL 6832
7175 10:55:00.850829 # ok 1280 # SKIP Disabled ZA for VL 6832
7176 10:55:00.851022 # ok 1281 # SKIP Get and set data for VL 6832
7177 10:55:00.851212 # ok 1282 Set VL 6848
7178 10:55:00.851397 # ok 1283 # SKIP Disabled ZA for VL 6848
7179 10:55:00.851562 # ok 1284 # SKIP Get and set data for VL 6848
7180 10:55:00.851688 # ok 1285 Set VL 6864
7181 10:55:00.851808 # ok 1286 # SKIP Disabled ZA for VL 6864
7182 10:55:00.851926 # ok 1287 # SKIP Get and set data for VL 6864
7183 10:55:00.852044 # ok 1288 Set VL 6880
7184 10:55:00.852162 # ok 1289 # SKIP Disabled ZA for VL 6880
7185 10:55:00.852281 # ok 1290 # SKIP Get and set data for VL 6880
7186 10:55:00.852401 # ok 1291 Set VL 6896
7187 10:55:00.852520 # ok 1292 # SKIP Disabled ZA for VL 6896
7188 10:55:00.852639 # ok 1293 # SKIP Get and set data for VL 6896
7189 10:55:00.852756 # ok 1294 Set VL 6912
7190 10:55:00.859005 # ok 1295 # SKIP Disabled ZA for VL 6912
7191 10:55:00.859170 # ok 1296 # SKIP Get and set data for VL 6912
7192 10:55:00.859276 # ok 1297 Set VL 6928
7193 10:55:00.866769 # ok 1298 # SKIP Disabled ZA for VL 6928
7194 10:55:00.867006 # ok 1299 # SKIP Get and set data for VL 6928
7195 10:55:00.867101 # ok 1300 Set VL 6944
7196 10:55:00.867172 # ok 1301 # SKIP Disabled ZA for VL 6944
7197 10:55:00.867235 # ok 1302 # SKIP Get and set data for VL 6944
7198 10:55:00.867298 # ok 1303 Set VL 6960
7199 10:55:00.867374 # ok 1304 # SKIP Disabled ZA for VL 6960
7200 10:55:00.867466 # ok 1305 # SKIP Get and set data for VL 6960
7201 10:55:00.867552 # ok 1306 Set VL 6976
7202 10:55:00.867618 # ok 1307 # SKIP Disabled ZA for VL 6976
7203 10:55:00.867681 # ok 1308 # SKIP Get and set data for VL 6976
7204 10:55:00.867743 # ok 1309 Set VL 6992
7205 10:55:00.867805 # ok 1310 # SKIP Disabled ZA for VL 6992
7206 10:55:00.867866 # ok 1311 # SKIP Get and set data for VL 6992
7207 10:55:00.867928 # ok 1312 Set VL 7008
7208 10:55:00.867989 # ok 1313 # SKIP Disabled ZA for VL 7008
7209 10:55:00.868051 # ok 1314 # SKIP Get and set data for VL 7008
7210 10:55:00.868113 # ok 1315 Set VL 7024
7211 10:55:00.868173 # ok 1316 # SKIP Disabled ZA for VL 7024
7212 10:55:00.868233 # ok 1317 # SKIP Get and set data for VL 7024
7213 10:55:00.868295 # ok 1318 Set VL 7040
7214 10:55:00.868357 # ok 1319 # SKIP Disabled ZA for VL 7040
7215 10:55:00.868417 # ok 1320 # SKIP Get and set data for VL 7040
7216 10:55:00.868479 # ok 1321 Set VL 7056
7217 10:55:00.868539 # ok 1322 # SKIP Disabled ZA for VL 7056
7218 10:55:00.868600 # ok 1323 # SKIP Get and set data for VL 7056
7219 10:55:00.868660 # ok 1324 Set VL 7072
7220 10:55:00.868721 # ok 1325 # SKIP Disabled ZA for VL 7072
7221 10:55:00.868782 # ok 1326 # SKIP Get and set data for VL 7072
7222 10:55:00.868843 # ok 1327 Set VL 7088
7223 10:55:00.868905 # ok 1328 # SKIP Disabled ZA for VL 7088
7224 10:55:00.869187 # ok 1329 # SKIP Get and set data for VL 7088
7225 10:55:00.869301 # ok 1330 Set VL 7104
7226 10:55:00.869399 # ok 1331 # SKIP Disabled ZA for VL 7104
7227 10:55:00.869493 # ok 1332 # SKIP Get and set data for VL 7104
7228 10:55:00.869588 # ok 1333 Set VL 7120
7229 10:55:00.872277 # ok 1334 # SKIP Disabled ZA for VL 7120
7230 10:55:00.872463 # ok 1335 # SKIP Get and set data for VL 7120
7231 10:55:00.872555 # ok 1336 Set VL 7136
7232 10:55:00.872660 # ok 1337 # SKIP Disabled ZA for VL 7136
7233 10:55:00.872767 # ok 1338 # SKIP Get and set data for VL 7136
7234 10:55:00.872857 # ok 1339 Set VL 7152
7235 10:55:00.872961 # ok 1340 # SKIP Disabled ZA for VL 7152
7236 10:55:00.873247 # ok 1341 # SKIP Get and set data for VL 7152
7237 10:55:00.873346 # ok 1342 Set VL 7168
7238 10:55:00.873430 # ok 1343 # SKIP Disabled ZA for VL 7168
7239 10:55:00.873534 # ok 1344 # SKIP Get and set data for VL 7168
7240 10:55:00.873620 # ok 1345 Set VL 7184
7241 10:55:00.873717 # ok 1346 # SKIP Disabled ZA for VL 7184
7242 10:55:00.873816 # ok 1347 # SKIP Get and set data for VL 7184
7243 10:55:00.873899 # ok 1348 Set VL 7200
7244 10:55:00.873994 # ok 1349 # SKIP Disabled ZA for VL 7200
7245 10:55:00.874076 # ok 1350 # SKIP Get and set data for VL 7200
7246 10:55:00.874155 # ok 1351 Set VL 7216
7247 10:55:00.874246 # ok 1352 # SKIP Disabled ZA for VL 7216
7248 10:55:00.874333 # ok 1353 # SKIP Get and set data for VL 7216
7249 10:55:00.874434 # ok 1354 Set VL 7232
7250 10:55:00.874523 # ok 1355 # SKIP Disabled ZA for VL 7232
7251 10:55:00.874630 # ok 1356 # SKIP Get and set data for VL 7232
7252 10:55:00.874730 # ok 1357 Set VL 7248
7253 10:55:00.875026 # ok 1358 # SKIP Disabled ZA for VL 7248
7254 10:55:00.875121 # ok 1359 # SKIP Get and set data for VL 7248
7255 10:55:00.875224 # ok 1360 Set VL 7264
7256 10:55:00.894234 # ok 1361 # SKIP Disabled ZA for VL 7264
7257 10:55:00.894692 # ok 1362 # SKIP Get and set data for VL 7264
7258 10:55:00.894800 # ok 1363 Set VL 7280
7259 10:55:00.895095 # ok 1364 # SKIP Disabled ZA for VL 7280
7260 10:55:00.895201 # ok 1365 # SKIP Get and set data for VL 7280
7261 10:55:00.895288 # ok 1366 Set VL 7296
7262 10:55:00.895372 # ok 1367 # SKIP Disabled ZA for VL 7296
7263 10:55:00.895455 # ok 1368 # SKIP Get and set data for VL 7296
7264 10:55:00.895539 # ok 1369 Set VL 7312
7265 10:55:00.895629 # ok 1370 # SKIP Disabled ZA for VL 7312
7266 10:55:00.895711 # ok 1371 # SKIP Get and set data for VL 7312
7267 10:55:00.895794 # ok 1372 Set VL 7328
7268 10:55:00.895877 # ok 1373 # SKIP Disabled ZA for VL 7328
7269 10:55:00.895976 # ok 1374 # SKIP Get and set data for VL 7328
7270 10:55:00.896061 # ok 1375 Set VL 7344
7271 10:55:00.896144 # ok 1376 # SKIP Disabled ZA for VL 7344
7272 10:55:00.896226 # ok 1377 # SKIP Get and set data for VL 7344
7273 10:55:00.896325 # ok 1378 Set VL 7360
7274 10:55:00.896411 # ok 1379 # SKIP Disabled ZA for VL 7360
7275 10:55:00.896494 # ok 1380 # SKIP Get and set data for VL 7360
7276 10:55:00.896578 # ok 1381 Set VL 7376
7277 10:55:00.896661 # ok 1382 # SKIP Disabled ZA for VL 7376
7278 10:55:00.896759 # ok 1383 # SKIP Get and set data for VL 7376
7279 10:55:00.896844 # ok 1384 Set VL 7392
7280 10:55:00.896926 # ok 1385 # SKIP Disabled ZA for VL 7392
7281 10:55:00.897022 # ok 1386 # SKIP Get and set data for VL 7392
7282 10:55:00.897136 # ok 1387 Set VL 7408
7283 10:55:00.897259 # ok 1388 # SKIP Disabled ZA for VL 7408
7284 10:55:00.897345 # ok 1389 # SKIP Get and set data for VL 7408
7285 10:55:00.897440 # ok 1390 Set VL 7424
7286 10:55:00.897535 # ok 1391 # SKIP Disabled ZA for VL 7424
7287 10:55:00.897835 # ok 1392 # SKIP Get and set data for VL 7424
7288 10:55:00.897943 # ok 1393 Set VL 7440
7289 10:55:00.898044 # ok 1394 # SKIP Disabled ZA for VL 7440
7290 10:55:00.898130 # ok 1395 # SKIP Get and set data for VL 7440
7291 10:55:00.898227 # ok 1396 Set VL 7456
7292 10:55:00.898523 # ok 1397 # SKIP Disabled ZA for VL 7456
7293 10:55:00.898629 # ok 1398 # SKIP Get and set data for VL 7456
7294 10:55:00.898717 # ok 1399 Set VL 7472
7295 10:55:00.898929 # ok 1400 # SKIP Disabled ZA for VL 7472
7296 10:55:00.899025 # ok 1401 # SKIP Get and set data for VL 7472
7297 10:55:00.899110 # ok 1402 Set VL 7488
7298 10:55:00.899207 # ok 1403 # SKIP Disabled ZA for VL 7488
7299 10:55:00.899308 # ok 1404 # SKIP Get and set data for VL 7488
7300 10:55:00.899407 # ok 1405 Set VL 7504
7301 10:55:00.899505 # ok 1406 # SKIP Disabled ZA for VL 7504
7302 10:55:00.899602 # ok 1407 # SKIP Get and set data for VL 7504
7303 10:55:00.899700 # ok 1408 Set VL 7520
7304 10:55:00.899798 # ok 1409 # SKIP Disabled ZA for VL 7520
7305 10:55:00.900083 # ok 1410 # SKIP Get and set data for VL 7520
7306 10:55:00.900174 # ok 1411 Set VL 7536
7307 10:55:00.900452 # ok 1412 # SKIP Disabled ZA for VL 7536
7308 10:55:00.900541 # ok 1413 # SKIP Get and set data for VL 7536
7309 10:55:00.900624 # ok 1414 Set VL 7552
7310 10:55:00.900720 # ok 1415 # SKIP Disabled ZA for VL 7552
7311 10:55:00.900818 # ok 1416 # SKIP Get and set data for VL 7552
7312 10:55:00.900916 # ok 1417 Set VL 7568
7313 10:55:00.901014 # ok 1418 # SKIP Disabled ZA for VL 7568
7314 10:55:00.901112 # ok 1419 # SKIP Get and set data for VL 7568
7315 10:55:00.901197 # ok 1420 Set VL 7584
7316 10:55:00.901294 # ok 1421 # SKIP Disabled ZA for VL 7584
7317 10:55:00.901391 # ok 1422 # SKIP Get and set data for VL 7584
7318 10:55:00.901672 # ok 1423 Set VL 7600
7319 10:55:00.901762 # ok 1424 # SKIP Disabled ZA for VL 7600
7320 10:55:00.901860 # ok 1425 # SKIP Get and set data for VL 7600
7321 10:55:00.901947 # ok 1426 Set VL 7616
7322 10:55:00.902028 # ok 1427 # SKIP Disabled ZA for VL 7616
7323 10:55:00.902122 # ok 1428 # SKIP Get and set data for VL 7616
7324 10:55:00.902205 # ok 1429 Set VL 7632
7325 10:55:00.902300 # ok 1430 # SKIP Disabled ZA for VL 7632
7326 10:55:00.902382 # ok 1431 # SKIP Get and set data for VL 7632
7327 10:55:00.902462 # ok 1432 Set VL 7648
7328 10:55:00.902556 # ok 1433 # SKIP Disabled ZA for VL 7648
7329 10:55:00.902651 # ok 1434 # SKIP Get and set data for VL 7648
7330 10:55:00.902734 # ok 1435 Set VL 7664
7331 10:55:00.902827 # ok 1436 # SKIP Disabled ZA for VL 7664
7332 10:55:00.902922 # ok 1437 # SKIP Get and set data for VL 7664
7333 10:55:00.903017 # ok 1438 Set VL 7680
7334 10:55:00.903369 # ok 1439 # SKIP Disabled ZA for VL 7680
7335 10:55:00.903477 # ok 1440 # SKIP Get and set data for VL 7680
7336 10:55:00.903576 # ok 1441 Set VL 7696
7337 10:55:00.903659 # ok 1442 # SKIP Disabled ZA for VL 7696
7338 10:55:00.903758 # ok 1443 # SKIP Get and set data for VL 7696
7339 10:55:00.903842 # ok 1444 Set VL 7712
7340 10:55:00.903924 # ok 1445 # SKIP Disabled ZA for VL 7712
7341 10:55:00.904004 # ok 1446 # SKIP Get and set data for VL 7712
7342 10:55:00.904100 # ok 1447 Set VL 7728
7343 10:55:00.904184 # ok 1448 # SKIP Disabled ZA for VL 7728
7344 10:55:00.904265 # ok 1449 # SKIP Get and set data for VL 7728
7345 10:55:00.904346 # ok 1450 Set VL 7744
7346 10:55:00.904441 # ok 1451 # SKIP Disabled ZA for VL 7744
7347 10:55:00.904525 # ok 1452 # SKIP Get and set data for VL 7744
7348 10:55:00.904606 # ok 1453 Set VL 7760
7349 10:55:00.904700 # ok 1454 # SKIP Disabled ZA for VL 7760
7350 10:55:00.904784 # ok 1455 # SKIP Get and set data for VL 7760
7351 10:55:00.904866 # ok 1456 Set VL 7776
7352 10:55:00.904960 # ok 1457 # SKIP Disabled ZA for VL 7776
7353 10:55:00.905044 # ok 1458 # SKIP Get and set data for VL 7776
7354 10:55:00.905125 # ok 1459 Set VL 7792
7355 10:55:00.905218 # ok 1460 # SKIP Disabled ZA for VL 7792
7356 10:55:00.905613 # ok 1461 # SKIP Get and set data for VL 7792
7357 10:55:00.905778 # ok 1462 Set VL 7808
7358 10:55:00.905890 # ok 1463 # SKIP Disabled ZA for VL 7808
7359 10:55:00.905977 # ok 1464 # SKIP Get and set data for VL 7808
7360 10:55:00.906061 # ok 1465 Set VL 7824
7361 10:55:00.906142 # ok 1466 # SKIP Disabled ZA for VL 7824
7362 10:55:00.906224 # ok 1467 # SKIP Get and set data for VL 7824
7363 10:55:00.906305 # ok 1468 Set VL 7840
7364 10:55:00.906387 # ok 1469 # SKIP Disabled ZA for VL 7840
7365 10:55:00.906470 # ok 1470 # SKIP Get and set data for VL 7840
7366 10:55:00.906550 # ok 1471 Set VL 7856
7367 10:55:00.906646 # ok 1472 # SKIP Disabled ZA for VL 7856
7368 10:55:00.906729 # ok 1473 # SKIP Get and set data for VL 7856
7369 10:55:00.906809 # ok 1474 Set VL 7872
7370 10:55:00.906888 # ok 1475 # SKIP Disabled ZA for VL 7872
7371 10:55:00.906968 # ok 1476 # SKIP Get and set data for VL 7872
7372 10:55:00.907047 # ok 1477 Set VL 7888
7373 10:55:00.907126 # ok 1478 # SKIP Disabled ZA for VL 7888
7374 10:55:00.907205 # ok 1479 # SKIP Get and set data for VL 7888
7375 10:55:00.907300 # ok 1480 Set VL 7904
7376 10:55:00.907383 # ok 1481 # SKIP Disabled ZA for VL 7904
7377 10:55:00.907463 # ok 1482 # SKIP Get and set data for VL 7904
7378 10:55:00.907542 # ok 1483 Set VL 7920
7379 10:55:00.907622 # ok 1484 # SKIP Disabled ZA for VL 7920
7380 10:55:00.907718 # ok 1485 # SKIP Get and set data for VL 7920
7381 10:55:00.907802 # ok 1486 Set VL 7936
7382 10:55:00.907882 # ok 1487 # SKIP Disabled ZA for VL 7936
7383 10:55:00.907962 # ok 1488 # SKIP Get and set data for VL 7936
7384 10:55:00.908042 # ok 1489 Set VL 7952
7385 10:55:00.908123 # ok 1490 # SKIP Disabled ZA for VL 7952
7386 10:55:00.908415 # ok 1491 # SKIP Get and set data for VL 7952
7387 10:55:00.908570 # ok 1492 Set VL 7968
7388 10:55:00.908695 # ok 1493 # SKIP Disabled ZA for VL 7968
7389 10:55:00.908801 # ok 1494 # SKIP Get and set data for VL 7968
7390 10:55:00.908887 # ok 1495 Set VL 7984
7391 10:55:00.908952 # ok 1496 # SKIP Disabled ZA for VL 7984
7392 10:55:00.909014 # ok 1497 # SKIP Get and set data for VL 7984
7393 10:55:00.909089 # ok 1498 Set VL 8000
7394 10:55:00.909153 # ok 1499 # SKIP Disabled ZA for VL 8000
7395 10:55:00.909214 # ok 1500 # SKIP Get and set data for VL 8000
7396 10:55:00.909274 # ok 1501 Set VL 8016
7397 10:55:00.909334 # ok 1502 # SKIP Disabled ZA for VL 8016
7398 10:55:00.909838 # ok 1503 # SKIP Get and set data for VL 8016
7399 10:55:00.910148 # ok 1504 Set VL 8032
7400 10:55:00.910262 # ok 1505 # SKIP Disabled ZA for VL 8032
7401 10:55:00.910344 # ok 1506 # SKIP Get and set data for VL 8032
7402 10:55:00.910481 # ok 1507 Set VL 8048
7403 10:55:00.910577 # ok 1508 # SKIP Disabled ZA for VL 8048
7404 10:55:00.910665 # ok 1509 # SKIP Get and set data for VL 8048
7405 10:55:00.910737 # ok 1510 Set VL 8064
7406 10:55:00.910814 # ok 1511 # SKIP Disabled ZA for VL 8064
7407 10:55:00.910900 # ok 1512 # SKIP Get and set data for VL 8064
7408 10:55:00.910985 # ok 1513 Set VL 8080
7409 10:55:00.911051 # ok 1514 # SKIP Disabled ZA for VL 8080
7410 10:55:00.911171 # ok 1515 # SKIP Get and set data for VL 8080
7411 10:55:00.911241 # ok 1516 Set VL 8096
7412 10:55:00.911303 # ok 1517 # SKIP Disabled ZA for VL 8096
7413 10:55:00.911375 # ok 1518 # SKIP Get and set data for VL 8096
7414 10:55:00.911453 # ok 1519 Set VL 8112
7415 10:55:00.917788 # ok 1520 # SKIP Disabled ZA for VL 8112
7416 10:55:00.918089 # ok 1521 # SKIP Get and set data for VL 8112
7417 10:55:00.918189 # ok 1522 Set VL 8128
7418 10:55:00.918280 # ok 1523 # SKIP Disabled ZA for VL 8128
7419 10:55:00.918389 # ok 1524 # SKIP Get and set data for VL 8128
7420 10:55:00.918481 # ok 1525 Set VL 8144
7421 10:55:00.918572 # ok 1526 # SKIP Disabled ZA for VL 8144
7422 10:55:00.918786 # ok 1527 # SKIP Get and set data for VL 8144
7423 10:55:00.918884 # ok 1528 Set VL 8160
7424 10:55:00.918976 # ok 1529 # SKIP Disabled ZA for VL 8160
7425 10:55:00.919084 # ok 1530 # SKIP Get and set data for VL 8160
7426 10:55:00.919185 # ok 1531 Set VL 8176
7427 10:55:00.919280 # ok 1532 # SKIP Disabled ZA for VL 8176
7428 10:55:00.919360 # ok 1533 # SKIP Get and set data for VL 8176
7429 10:55:00.919445 # ok 1534 Set VL 8192
7430 10:55:00.919566 # ok 1535 # SKIP Disabled ZA for VL 8192
7431 10:55:00.919678 # ok 1536 # SKIP Get and set data for VL 8192
7432 10:55:00.919969 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7433 10:55:00.920056 ok 34 selftests: arm64: za-ptrace
7434 10:55:00.920148 # selftests: arm64: check_buffer_fill
7435 10:55:01.446923 # 1..20
7436 10:55:01.447382 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7437 10:55:01.453857 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7438 10:55:01.454000 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7439 10:55:01.454090 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7440 10:55:01.454177 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7441 10:55:01.454262 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7442 10:55:01.454549 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 10:55:01.454668 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7444 10:55:01.454754 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7445 10:55:01.454836 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7446 10:55:01.454933 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7447 10:55:01.455017 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7448 10:55:01.457334 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7449 10:55:01.457864 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7450 10:55:01.458068 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7451 10:55:01.458335 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7452 10:55:01.458529 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7453 10:55:01.458732 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7454 10:55:01.458909 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7455 10:55:01.459101 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7456 10:55:01.464610 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7457 10:55:01.474852 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7458 10:55:01.585403 # selftests: arm64: check_child_memory
7459 10:55:02.018963 # 1..12
7460 10:55:02.025017 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7461 10:55:02.025452 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7462 10:55:02.025564 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7463 10:55:02.025660 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7464 10:55:02.025761 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7465 10:55:02.025860 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7466 10:55:02.026135 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7467 10:55:02.026224 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7468 10:55:02.026320 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7469 10:55:02.026418 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7470 10:55:02.026713 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7471 10:55:02.028599 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7472 10:55:02.028884 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7473 10:55:02.041531 not ok 36 selftests: arm64: check_child_memory # exit=1
7474 10:55:02.153491 # selftests: arm64: check_gcr_el1_cswitch
7475 10:55:47.419768 <47>[ 98.802659] systemd-journald[109]: Sent WATCHDOG=1 notification.
7476 10:55:47.829509 <47>[ 99.214153] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3308 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
7477 10:55:47.829895 <47>[ 99.214692] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7478 10:55:47.830071 <47>[ 99.215049] systemd-journald[109]: Rotating...
7479 10:55:47.858592 <47>[ 99.243341] systemd-journald[109]: Reserving 333 entries in field hash table.
7480 10:55:47.904106 <47>[ 99.288859] systemd-journald[109]: Reserving 4408 entries in data hash table.
7481 10:55:47.924958 <47>[ 99.309883] systemd-journald[109]: Vacuuming...
7482 10:55:47.940073 <47>[ 99.324827] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7483 10:55:48.723748 # 1..1
7484 10:55:48.724096 # 1..1
7485 10:55:48.724528 # 1..1
7486 10:55:48.724721 # 1..1
7487 10:55:48.724884 # 1..1
7488 10:55:48.725037 # 1..1
7489 10:55:48.725206 # 1..1
7490 10:55:48.725366 # 1..1
7491 10:55:48.725531 # 1..1
7492 10:55:48.725706 # 1..1
7493 10:55:48.725882 # 1..1
7494 10:55:48.726048 # 1..1
7495 10:55:48.726198 # 1..1
7496 10:55:48.726318 # 1..1
7497 10:55:48.726434 # 1..1
7498 10:55:48.726549 # 1..1
7499 10:55:48.726662 # 1..1
7500 10:55:48.726776 # 1..1
7501 10:55:48.726890 # 1..1
7502 10:55:48.727004 # 1..1
7503 10:55:48.727118 # 1..1
7504 10:55:48.727231 # 1..1
7505 10:55:48.727349 # 1..1
7506 10:55:48.727520 # 1..1
7507 10:55:48.727650 # 1..1
7508 10:55:48.727766 # 1..1
7509 10:55:48.727881 # 1..1
7510 10:55:48.727995 # 1..1
7511 10:55:48.728109 # 1..1
7512 10:55:48.728221 # 1..1
7513 10:55:48.728376 # 1..1
7514 10:55:48.728498 # 1..1
7515 10:55:48.728614 # 1..1
7516 10:55:48.728728 # 1..1
7517 10:55:48.728842 # 1..1
7518 10:55:48.728954 # 1..1
7519 10:55:48.729067 # 1..1
7520 10:55:48.729179 # 1..1
7521 10:55:48.729291 # 1..1
7522 10:55:48.729404 # 1..1
7523 10:55:48.729516 # 1..1
7524 10:55:48.729628 # 1..1
7525 10:55:48.729864 # 1..1
7526 10:55:48.730061 # 1..1
7527 10:55:48.730247 # 1..1
7528 10:55:48.730434 # 1..1
7529 10:55:48.730618 # 1..1
7530 10:55:48.730802 # 1..1
7531 10:55:48.730986 # 1..1
7532 10:55:48.731135 # 1..1
7533 10:55:48.731281 # 1..1
7534 10:55:48.731433 # 1..1
7535 10:55:48.731578 # 1..1
7536 10:55:48.731722 # 1..1
7537 10:55:48.731868 # 1..1
7538 10:55:48.732012 # 1..1
7539 10:55:48.732156 # 1..1
7540 10:55:48.732302 # 1..1
7541 10:55:48.732447 # 1..1
7542 10:55:48.732591 # 1..1
7543 10:55:48.732735 # 1..1
7544 10:55:48.732879 # 1..1
7545 10:55:48.733023 # 1..1
7546 10:55:48.733169 # 1..1
7547 10:55:48.733316 # 1..1
7548 10:55:48.733459 # 1..1
7549 10:55:48.733604 # 1..1
7550 10:55:48.733759 # 1..1
7551 10:55:48.733904 # 1..1
7552 10:55:48.734048 # 1..1
7553 10:55:48.734192 # 1..1
7554 10:55:48.734337 # 1..1
7555 10:55:48.734481 # 1..1
7556 10:55:48.734623 # 1..1
7557 10:55:48.734766 # 1..1
7558 10:55:48.734910 # 1..1
7559 10:55:48.735054 # 1..1
7560 10:55:48.735199 # 1..1
7561 10:55:48.735343 # 1..1
7562 10:55:48.735487 # 1..1
7563 10:55:48.735630 # 1..1
7564 10:55:48.735774 # 1..1
7565 10:55:48.735919 # 1..1
7566 10:55:48.736063 # 1..1
7567 10:55:48.736206 # 1..1
7568 10:55:48.736350 # 1..1
7569 10:55:48.736492 # 1..1
7570 10:55:48.736635 # 1..1
7571 10:55:48.736778 # 1..1
7572 10:55:48.736922 # 1..1
7573 10:55:48.737065 # 1..1
7574 10:55:48.737208 # 1..1
7575 10:55:48.737354 # 1..1
7576 10:55:48.737498 # 1..1
7577 10:55:48.737641 # 1..1
7578 10:55:48.737814 # 1..1
7579 10:55:48.737957 # 1..1
7580 10:55:48.738100 # 1..1
7581 10:55:48.738242 # 1..1
7582 10:55:48.738390 # 1..1
7583 10:55:48.738534 # 1..1
7584 10:55:48.738678 # 1..1
7585 10:55:48.738822 # 1..1
7586 10:55:48.738967 # 1..1
7587 10:55:48.778088 # 1..1
7588 10:55:48.778395 # 1..1
7589 10:55:48.778582 # 1..1
7590 10:55:48.778734 # 1..1
7591 10:55:48.778880 # 1..1
7592 10:55:48.779024 # 1..1
7593 10:55:48.779405 # 1..1
7594 10:55:48.779547 # 1..1
7595 10:55:48.779698 # 1..1
7596 10:55:48.779844 # 1..1
7597 10:55:48.779990 # 1..1
7598 10:55:48.780135 # 1..1
7599 10:55:48.780280 # 1..1
7600 10:55:48.780425 # 1..1
7601 10:55:48.791369 # 1..1
7602 10:55:48.791700 # 1..1
7603 10:55:48.791868 # 1..1
7604 10:55:48.792062 # 1..1
7605 10:55:48.792251 # 1..1
7606 10:55:48.792463 # 1..1
7607 10:55:48.792923 # 1..1
7608 10:55:48.793128 # 1..1
7609 10:55:48.793295 # 1..1
7610 10:55:48.793509 # 1..1
7611 10:55:48.793684 # 1..1
7612 10:55:48.793832 # 1..1
7613 10:55:48.793965 # 1..1
7614 10:55:48.794093 # 1..1
7615 10:55:48.794217 # 1..1
7616 10:55:48.794335 # 1..1
7617 10:55:48.794460 # 1..1
7618 10:55:48.794577 # 1..1
7619 10:55:48.794693 # 1..1
7620 10:55:48.794810 # 1..1
7621 10:55:48.794925 # 1..1
7622 10:55:48.795041 # 1..1
7623 10:55:48.795157 # 1..1
7624 10:55:48.795274 # 1..1
7625 10:55:48.795391 # 1..1
7626 10:55:48.795512 # 1..1
7627 10:55:48.795628 # 1..1
7628 10:55:48.795745 # 1..1
7629 10:55:48.795862 # 1..1
7630 10:55:48.795979 # 1..1
7631 10:55:48.796097 # 1..1
7632 10:55:48.796214 # 1..1
7633 10:55:48.796329 # 1..1
7634 10:55:48.796446 # 1..1
7635 10:55:48.796562 # 1..1
7636 10:55:48.796680 # 1..1
7637 10:55:48.796797 # 1..1
7638 10:55:48.796914 # 1..1
7639 10:55:48.797031 # 1..1
7640 10:55:48.797147 # 1..1
7641 10:55:48.797265 # 1..1
7642 10:55:48.797381 # 1..1
7643 10:55:48.797497 # 1..1
7644 10:55:48.797614 # 1..1
7645 10:55:48.797746 # 1..1
7646 10:55:48.797864 # 1..1
7647 10:55:48.797982 # 1..1
7648 10:55:48.798099 # 1..1
7649 10:55:48.798216 # 1..1
7650 10:55:48.798332 # 1..1
7651 10:55:48.798450 # 1..1
7652 10:55:48.798566 # 1..1
7653 10:55:48.798683 # 1..1
7654 10:55:48.798802 # 1..1
7655 10:55:48.798920 # 1..1
7656 10:55:48.799037 # 1..1
7657 10:55:48.799154 # 1..1
7658 10:55:48.799270 # 1..1
7659 10:55:48.799396 # 1..1
7660 10:55:48.799577 # 1..1
7661 10:55:48.799726 # 1..1
7662 10:55:48.799871 # 1..1
7663 10:55:48.800018 # 1..1
7664 10:55:48.800204 # 1..1
7665 10:55:48.800355 # 1..1
7666 10:55:48.800501 # 1..1
7667 10:55:48.800647 # 1..1
7668 10:55:48.800792 # 1..1
7669 10:55:48.800936 # 1..1
7670 10:55:48.801135 # 1..1
7671 10:55:48.801274 # 1..1
7672 10:55:48.801421 # 1..1
7673 10:55:48.801566 # 1..1
7674 10:55:48.801726 # 1..1
7675 10:55:48.801872 # 1..1
7676 10:55:48.802015 # 1..1
7677 10:55:48.802159 # 1..1
7678 10:55:48.802303 # 1..1
7679 10:55:48.802449 # 1..1
7680 10:55:48.802593 # 1..1
7681 10:55:48.802736 # 1..1
7682 10:55:48.802880 # 1..1
7683 10:55:48.803024 # 1..1
7684 10:55:48.803167 # 1..1
7685 10:55:48.803310 # 1..1
7686 10:55:48.803454 # 1..1
7687 10:55:48.803597 # 1..1
7688 10:55:48.803740 # 1..1
7689 10:55:48.803883 # 1..1
7690 10:55:48.804026 # 1..1
7691 10:55:48.804170 # 1..1
7692 10:55:48.804314 # 1..1
7693 10:55:48.804458 # 1..1
7694 10:55:48.804600 # 1..1
7695 10:55:48.804743 # 1..1
7696 10:55:48.804887 # 1..1
7697 10:55:48.805030 # 1..1
7698 10:55:48.805173 # 1..1
7699 10:55:48.805317 # 1..1
7700 10:55:48.805463 # 1..1
7701 10:55:48.805608 # 1..1
7702 10:55:48.805765 # 1..1
7703 10:55:48.805910 # 1..1
7704 10:55:48.806055 # 1..1
7705 10:55:48.806197 # 1..1
7706 10:55:48.806342 # 1..1
7707 10:55:48.806485 # 1..1
7708 10:55:48.806628 # 1..1
7709 10:55:48.806771 # 1..1
7710 10:55:48.806915 # 1..1
7711 10:55:48.807058 # 1..1
7712 10:55:48.807201 # 1..1
7713 10:55:48.807345 # 1..1
7714 10:55:48.813005 # 1..1
7715 10:55:48.813290 # 1..1
7716 10:55:48.813495 # 1..1
7717 10:55:48.813690 # 1..1
7718 10:55:48.813868 # 1..1
7719 10:55:48.814017 # 1..1
7720 10:55:48.814164 # 1..1
7721 10:55:48.814307 # 1..1
7722 10:55:48.814693 # 1..1
7723 10:55:48.814857 # 1..1
7724 10:55:48.815009 # 1..1
7725 10:55:48.815154 # 1..1
7726 10:55:48.815299 # 1..1
7727 10:55:48.815446 # 1..1
7728 10:55:48.815589 # 1..1
7729 10:55:48.815734 # 1..1
7730 10:55:48.815877 # 1..1
7731 10:55:48.816022 # 1..1
7732 10:55:48.816166 # 1..1
7733 10:55:48.816311 # 1..1
7734 10:55:48.816455 # 1..1
7735 10:55:48.816598 # 1..1
7736 10:55:48.816742 # 1..1
7737 10:55:48.816887 # 1..1
7738 10:55:48.817031 # 1..1
7739 10:55:48.817174 # 1..1
7740 10:55:48.817317 # 1..1
7741 10:55:48.817460 # 1..1
7742 10:55:48.817603 # 1..1
7743 10:55:48.817763 # 1..1
7744 10:55:48.817908 # 1..1
7745 10:55:48.818052 # 1..1
7746 10:55:48.818195 # 1..1
7747 10:55:48.818339 # 1..1
7748 10:55:48.818486 # 1..1
7749 10:55:48.818630 # 1..1
7750 10:55:48.818774 # 1..1
7751 10:55:48.818919 # 1..1
7752 10:55:48.819063 # 1..1
7753 10:55:48.819206 # 1..1
7754 10:55:48.819351 # 1..1
7755 10:55:48.819497 # 1..1
7756 10:55:48.819644 # 1..1
7757 10:55:48.819788 # 1..1
7758 10:55:48.819933 # 1..1
7759 10:55:48.820078 # 1..1
7760 10:55:48.820254 # 1..1
7761 10:55:48.820463 # 1..1
7762 10:55:48.820605 # 1..1
7763 10:55:48.820727 # 1..1
7764 10:55:48.820845 # 1..1
7765 10:55:48.820962 # 1..1
7766 10:55:48.821079 # 1..1
7767 10:55:48.821197 # 1..1
7768 10:55:48.821315 # 1..1
7769 10:55:48.821435 # 1..1
7770 10:55:48.836063 # 1..1
7771 10:55:48.836335 # 1..1
7772 10:55:48.836509 # 1..1
7773 10:55:48.836657 # 1..1
7774 10:55:48.836832 # 1..1
7775 10:55:48.837233 # 1..1
7776 10:55:48.837412 # 1..1
7777 10:55:48.837579 # 1..1
7778 10:55:48.837752 # 1..1
7779 10:55:48.837912 # 1..1
7780 10:55:48.838058 # 1..1
7781 10:55:48.838232 # 1..1
7782 10:55:48.838368 # 1..1
7783 10:55:48.838491 # 1..1
7784 10:55:48.838607 # 1..1
7785 10:55:48.838723 # 1..1
7786 10:55:48.838840 # 1..1
7787 10:55:48.838956 # 1..1
7788 10:55:48.839072 # 1..1
7789 10:55:48.839187 # 1..1
7790 10:55:48.839304 # 1..1
7791 10:55:48.839419 # 1..1
7792 10:55:48.839535 # 1..1
7793 10:55:48.839651 # 1..1
7794 10:55:48.839766 # 1..1
7795 10:55:48.839880 # 1..1
7796 10:55:48.839996 # 1..1
7797 10:55:48.840110 # 1..1
7798 10:55:48.840225 # 1..1
7799 10:55:48.840379 # 1..1
7800 10:55:48.840510 # 1..1
7801 10:55:48.840629 # 1..1
7802 10:55:48.840745 # 1..1
7803 10:55:48.840862 # 1..1
7804 10:55:48.840979 # 1..1
7805 10:55:48.841094 # 1..1
7806 10:55:48.841208 # 1..1
7807 10:55:48.841324 # 1..1
7808 10:55:48.841439 # 1..1
7809 10:55:48.841555 # 1..1
7810 10:55:48.841728 # 1..1
7811 10:55:48.841942 # 1..1
7812 10:55:48.842128 # 1..1
7813 10:55:48.842314 # 1..1
7814 10:55:48.842502 # 1..1
7815 10:55:48.842687 # 1..1
7816 10:55:48.842871 # 1..1
7817 10:55:48.843057 # 1..1
7818 10:55:48.843203 # 1..1
7819 10:55:48.843347 # 1..1
7820 10:55:48.843490 # 1..1
7821 10:55:48.843634 # 1..1
7822 10:55:48.843777 # 1..1
7823 10:55:48.843921 # 1..1
7824 10:55:48.844064 # 1..1
7825 10:55:48.844208 # 1..1
7826 10:55:48.844351 # 1..1
7827 10:55:48.844496 # 1..1
7828 10:55:48.844692 # 1..1
7829 10:55:48.844829 # 1..1
7830 10:55:48.844972 # 1..1
7831 10:55:48.845115 # 1..1
7832 10:55:48.845258 # 1..1
7833 10:55:48.845401 # 1..1
7834 10:55:48.845563 # 1..1
7835 10:55:48.845797 # 1..1
7836 10:55:48.845990 # 1..1
7837 10:55:48.846180 # 1..1
7838 10:55:48.846384 # 1..1
7839 10:55:48.846579 # 1..1
7840 10:55:48.846772 # 1..1
7841 10:55:48.846959 # 1..1
7842 10:55:48.847109 # 1..1
7843 10:55:48.847236 # 1..1
7844 10:55:48.847382 # 1..1
7845 10:55:48.847535 # 1..1
7846 10:55:48.847679 # 1..1
7847 10:55:48.847827 # 1..1
7848 10:55:48.848007 # 1..1
7849 10:55:48.848154 # 1..1
7850 10:55:48.848298 # 1..1
7851 10:55:48.848424 # 1..1
7852 10:55:48.848562 # 1..1
7853 10:55:48.848696 # 1..1
7854 10:55:48.848830 # 1..1
7855 10:55:48.848961 # 1..1
7856 10:55:48.849096 # 1..1
7857 10:55:48.849243 # 1..1
7858 10:55:48.849398 # 1..1
7859 10:55:48.849546 # 1..1
7860 10:55:48.849703 # 1..1
7861 10:55:48.849845 # 1..1
7862 10:55:48.849979 # 1..1
7863 10:55:48.850129 # 1..1
7864 10:55:48.850320 # 1..1
7865 10:55:48.850568 # 1..1
7866 10:55:48.850722 # 1..1
7867 10:55:48.850882 # 1..1
7868 10:55:48.851040 # 1..1
7869 10:55:48.851199 # 1..1
7870 10:55:48.851356 # 1..1
7871 10:55:48.851514 # 1..1
7872 10:55:48.851670 # 1..1
7873 10:55:48.851827 # 1..1
7874 10:55:48.851984 # 1..1
7875 10:55:48.852141 # 1..1
7876 10:55:48.852300 # 1..1
7877 10:55:48.852457 # 1..1
7878 10:55:48.852616 # 1..1
7879 10:55:48.852772 # 1..1
7880 10:55:48.852929 # 1..1
7881 10:55:48.853085 # 1..1
7882 10:55:48.853242 # 1..1
7883 10:55:48.853401 # 1..1
7884 10:55:48.853562 # 1..1
7885 10:55:48.853735 # 1..1
7886 10:55:48.853897 # 1..1
7887 10:55:48.854055 # 1..1
7888 10:55:48.854214 # 1..1
7889 10:55:48.854372 # 1..1
7890 10:55:48.854531 # 1..1
7891 10:55:48.854675 # 1..1
7892 10:55:48.854817 # 1..1
7893 10:55:48.854959 # 1..1
7894 10:55:48.855101 # 1..1
7895 10:55:48.855242 # 1..1
7896 10:55:48.855384 # 1..1
7897 10:55:48.855526 # 1..1
7898 10:55:48.855668 # 1..1
7899 10:55:48.855811 # 1..1
7900 10:55:48.855952 # 1..1
7901 10:55:48.856095 # 1..1
7902 10:55:48.856238 # 1..1
7903 10:55:48.856381 # 1..1
7904 10:55:48.856526 # 1..1
7905 10:55:48.856668 # 1..1
7906 10:55:48.856812 # 1..1
7907 10:55:48.856955 # 1..1
7908 10:55:48.857097 # 1..1
7909 10:55:48.857239 # 1..1
7910 10:55:48.857382 # 1..1
7911 10:55:48.857525 # 1..1
7912 10:55:48.857678 # 1..1
7913 10:55:48.857824 # 1..1
7914 10:55:48.857968 # 1..1
7915 10:55:48.858112 # 1..1
7916 10:55:48.858255 # 1..1
7917 10:55:48.858398 # 1..1
7918 10:55:48.858541 # 1..1
7919 10:55:48.858683 # 1..1
7920 10:55:48.858825 # 1..1
7921 10:55:48.858966 # 1..1
7922 10:55:48.859108 # 1..1
7923 10:55:48.859251 # 1..1
7924 10:55:48.859396 # 1..1
7925 10:55:48.859539 # 1..1
7926 10:55:48.859683 # 1..1
7927 10:55:48.859825 # 1..1
7928 10:55:48.859968 # 1..1
7929 10:55:48.860111 # 1..1
7930 10:55:48.860253 # 1..1
7931 10:55:48.860395 # 1..1
7932 10:55:48.860537 # 1..1
7933 10:55:48.860679 # 1..1
7934 10:55:48.860820 # 1..1
7935 10:55:48.860963 # 1..1
7936 10:55:48.861104 # 1..1
7937 10:55:48.861246 # 1..1
7938 10:55:48.861388 # 1..1
7939 10:55:48.861530 # 1..1
7940 10:55:48.861686 # 1..1
7941 10:55:48.861833 # 1..1
7942 10:55:48.861977 # 1..1
7943 10:55:48.872046 # 1..1
7944 10:55:48.872307 # 1..1
7945 10:55:48.872409 # 1..1
7946 10:55:48.872501 # 1..1
7947 10:55:48.872590 # 1..1
7948 10:55:48.872896 # 1..1
7949 10:55:48.872996 # 1..1
7950 10:55:48.873083 # 1..1
7951 10:55:48.873173 # 1..1
7952 10:55:48.873267 # 1..1
7953 10:55:48.873358 # 1..1
7954 10:55:48.873449 # 1..1
7955 10:55:48.873542 # 1..1
7956 10:55:48.873635 # 1..1
7957 10:55:48.873733 # 1..1
7958 10:55:48.873823 # 1..1
7959 10:55:48.873913 # 1..1
7960 10:55:48.874002 # 1..1
7961 10:55:48.874090 # 1..1
7962 10:55:48.874178 # 1..1
7963 10:55:48.874269 # 1..1
7964 10:55:48.874358 # 1..1
7965 10:55:48.874446 # 1..1
7966 10:55:48.874527 # 1..1
7967 10:55:48.874620 # 1..1
7968 10:55:48.874709 # 1..1
7969 10:55:48.874797 # 1..1
7970 10:55:48.874884 # 1..1
7971 10:55:48.874970 # 1..1
7972 10:55:48.875055 # 1..1
7973 10:55:48.875141 # 1..1
7974 10:55:48.875232 # 1..1
7975 10:55:48.875322 # 1..1
7976 10:55:48.875410 # 1..1
7977 10:55:48.875499 # 1..1
7978 10:55:48.875587 # 1..1
7979 10:55:48.875676 # 1..1
7980 10:55:48.875764 # 1..1
7981 10:55:48.875854 # 1..1
7982 10:55:48.875962 #
7983 10:55:48.876056 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
7984 10:55:49.120027 # selftests: arm64: check_ksm_options
7985 10:55:49.457524 # 1..4
7986 10:55:49.457786 # # Invalid MTE synchronous exception caught!
7987 10:55:49.509523 not ok 38 selftests: arm64: check_ksm_options # exit=1
7988 10:55:49.808581 # selftests: arm64: check_mmap_options
7989 10:55:50.657385 # 1..22
7990 10:55:50.657634 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
7991 10:55:50.657949 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
7992 10:55:50.658065 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
7993 10:55:50.658162 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
7994 10:55:50.658270 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
7995 10:55:50.672156 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7996 10:55:50.672682 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
7997 10:55:50.672791 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7998 10:55:50.672879 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
7999 10:55:50.672978 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8000 10:55:50.673263 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8001 10:55:50.673587 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8002 10:55:50.673924 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8003 10:55:50.674045 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8004 10:55:50.674343 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8005 10:55:50.681940 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8006 10:55:50.682119 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8007 10:55:50.682899 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8008 10:55:50.683247 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8009 10:55:50.683451 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8010 10:55:50.683641 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8011 10:55:50.683824 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8012 10:55:50.683957 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8013 10:55:50.725959 not ok 39 selftests: arm64: check_mmap_options # exit=1
8014 10:55:51.013384 # selftests: arm64: check_prctl
8015 10:55:51.307296 # TAP version 13
8016 10:55:51.307548 # 1..5
8017 10:55:51.307637 # ok 1 check_basic_read
8018 10:55:51.307721 # ok 2 NONE
8019 10:55:51.308007 # ok 3 SYNC
8020 10:55:51.308095 # ok 4 ASYNC
8021 10:55:51.308177 # ok 5 SYNC+ASYNC
8022 10:55:51.308257 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8023 10:55:51.351524 ok 40 selftests: arm64: check_prctl
8024 10:55:51.633642 # selftests: arm64: check_tags_inclusion
8025 10:55:51.972714 # 1..4
8026 10:55:51.973074 # # Unexpected fault recorded for 0x700ffffb572b000-0x700ffffb572b050 in mode 1
8027 10:55:51.973596 # not ok 1 Check an included tag value with sync mode
8028 10:55:51.973803 # # Unexpected fault recorded for 0x600ffffb572b000-0x600ffffb572b050 in mode 1
8029 10:55:51.973938 # not ok 2 Check different included tags value with sync mode
8030 10:55:51.974060 # ok 3 Check none included tags value with sync mode
8031 10:55:51.974180 # # Unexpected fault recorded for 0xe00ffffb572b000-0xe00ffffb572b050 in mode 1
8032 10:55:51.974324 # not ok 4 Check all included tags value with sync mode
8033 10:55:51.974448 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8034 10:55:52.024987 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8035 10:55:52.241610 # selftests: arm64: check_user_mem
8036 10:56:00.301783 # 1..64
8037 10:56:00.302063 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8038 10:56:00.302423 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8039 10:56:00.302561 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8040 10:56:00.303363 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8041 10:56:00.303820 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8042 10:56:00.304034 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8043 10:56:00.304238 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8044 10:56:00.304469 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8045 10:56:00.304687 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8046 10:56:00.304897 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8047 10:56:00.305084 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8048 10:56:00.305307 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8049 10:56:00.305471 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8050 10:56:00.305671 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8051 10:56:00.305824 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8052 10:56:00.305994 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8053 10:56:00.306142 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8054 10:56:00.306271 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8055 10:56:00.306435 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8056 10:56:00.311587 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8057 10:56:00.312064 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8058 10:56:00.312275 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8059 10:56:00.312484 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8060 10:56:00.312655 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8061 10:56:00.312849 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8062 10:56:00.313024 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8063 10:56:00.313194 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8064 10:56:00.313378 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8065 10:56:00.313582 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8066 10:56:00.313799 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8067 10:56:00.314049 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8068 10:56:00.314227 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8069 10:56:00.314358 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8070 10:56:00.314574 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8071 10:56:00.314835 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8072 10:56:00.315089 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8073 10:56:00.315315 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8074 10:56:00.316071 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8075 10:56:00.316252 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8076 10:56:00.316429 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8077 10:56:00.316599 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8078 10:56:00.316756 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8079 10:56:00.316944 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8080 10:56:00.317159 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8081 10:56:00.317533 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8082 10:56:00.317635 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8083 10:56:00.317728 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8084 10:56:00.317809 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8085 10:56:00.317888 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8086 10:56:00.317964 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8087 10:56:00.318044 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8088 10:56:01.907965 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8089 10:56:01.908600 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8090 10:56:01.908811 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8091 10:56:01.908993 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8092 10:56:01.909167 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8093 10:56:01.909374 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8094 10:56:01.909546 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8095 10:56:01.909731 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8096 10:56:01.909931 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8097 10:56:01.910098 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8098 10:56:01.910315 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8099 10:56:01.918206 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8100 10:56:01.930180 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8101 10:56:01.936966 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8102 10:56:01.937368 ok 42 selftests: arm64: check_user_mem
8103 10:56:02.060876 # selftests: arm64: btitest
8104 10:56:02.164188 # TAP version 13
8105 10:56:02.164441 # 1..18
8106 10:56:02.164537 # # HWCAP_PACA present
8107 10:56:02.164841 # # HWCAP2_BTI present
8108 10:56:02.164948 # # Test binary built for BTI
8109 10:56:02.165038 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8110 10:56:02.165124 # ok 1 nohint_func/call_using_br_x0
8111 10:56:02.165227 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8112 10:56:02.165316 # ok 2 nohint_func/call_using_br_x16
8113 10:56:02.165414 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8114 10:56:02.165521 # ok 3 nohint_func/call_using_blr
8115 10:56:02.165865 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8116 10:56:02.166062 # ok 4 bti_none_func/call_using_br_x0
8117 10:56:02.166240 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8118 10:56:02.166426 # ok 5 bti_none_func/call_using_br_x16
8119 10:56:02.168739 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8120 10:56:02.169000 # ok 6 bti_none_func/call_using_blr
8121 10:56:02.169448 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8122 10:56:02.169689 # ok 7 bti_c_func/call_using_br_x0
8123 10:56:02.169890 # ok 8 bti_c_func/call_using_br_x16
8124 10:56:02.170061 # ok 9 bti_c_func/call_using_blr
8125 10:56:02.170191 # ok 10 bti_j_func/call_using_br_x0
8126 10:56:02.170305 # ok 11 bti_j_func/call_using_br_x16
8127 10:56:02.170450 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8128 10:56:02.170582 # ok 12 bti_j_func/call_using_blr
8129 10:56:02.170698 # ok 13 bti_jc_func/call_using_br_x0
8130 10:56:02.170814 # ok 14 bti_jc_func/call_using_br_x16
8131 10:56:02.170930 # ok 15 bti_jc_func/call_using_blr
8132 10:56:02.171044 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8133 10:56:02.171159 # ok 16 paciasp_func/call_using_br_x0
8134 10:56:02.173567 # ok 17 paciasp_func/call_using_br_x16
8135 10:56:02.174006 # ok 18 paciasp_func/call_using_blr
8136 10:56:02.174162 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8137 10:56:02.189843 ok 43 selftests: arm64: btitest
8138 10:56:02.291681 # selftests: arm64: nobtitest
8139 10:56:02.411770 # TAP version 13
8140 10:56:02.412052 # 1..18
8141 10:56:02.412409 # # HWCAP_PACA present
8142 10:56:02.412575 # # HWCAP2_BTI present
8143 10:56:02.412720 # # Test binary not built for BTI
8144 10:56:02.412902 # ok 1 nohint_func/call_using_br_x0
8145 10:56:02.413082 # ok 2 nohint_func/call_using_br_x16
8146 10:56:02.413235 # ok 3 nohint_func/call_using_blr
8147 10:56:02.413380 # ok 4 bti_none_func/call_using_br_x0
8148 10:56:02.413524 # ok 5 bti_none_func/call_using_br_x16
8149 10:56:02.413682 # ok 6 bti_none_func/call_using_blr
8150 10:56:02.413830 # ok 7 bti_c_func/call_using_br_x0
8151 10:56:02.414017 # ok 8 bti_c_func/call_using_br_x16
8152 10:56:02.414156 # ok 9 bti_c_func/call_using_blr
8153 10:56:02.414305 # ok 10 bti_j_func/call_using_br_x0
8154 10:56:02.414451 # ok 11 bti_j_func/call_using_br_x16
8155 10:56:02.414595 # ok 12 bti_j_func/call_using_blr
8156 10:56:02.414739 # ok 13 bti_jc_func/call_using_br_x0
8157 10:56:02.414882 # ok 14 bti_jc_func/call_using_br_x16
8158 10:56:02.415025 # ok 15 bti_jc_func/call_using_blr
8159 10:56:02.415167 # ok 16 paciasp_func/call_using_br_x0
8160 10:56:02.415309 # ok 17 paciasp_func/call_using_br_x16
8161 10:56:02.415459 # ok 18 paciasp_func/call_using_blr
8162 10:56:02.415604 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8163 10:56:02.436113 ok 44 selftests: arm64: nobtitest
8164 10:56:02.560118 # selftests: arm64: hwcap
8165 10:56:02.720789 # TAP version 13
8166 10:56:02.721053 # 1..28
8167 10:56:02.721438 # # RNG present
8168 10:56:02.721645 # ok 1 cpuinfo_match_RNG
8169 10:56:02.721832 # ok 2 sigill_RNG
8170 10:56:02.722003 # # SME present
8171 10:56:02.722154 # ok 3 cpuinfo_match_SME
8172 10:56:02.722278 # ok 4 sigill_SME
8173 10:56:02.722397 # # SVE present
8174 10:56:02.722515 # ok 5 cpuinfo_match_SVE
8175 10:56:02.722633 # ok 6 sigill_SVE
8176 10:56:02.722750 # # SVE 2 present
8177 10:56:02.722871 # ok 7 cpuinfo_match_SVE 2
8178 10:56:02.722988 # ok 8 sigill_SVE 2
8179 10:56:02.723105 # # SVE AES present
8180 10:56:02.723253 # ok 9 cpuinfo_match_SVE AES
8181 10:56:02.723385 # ok 10 sigill_SVE AES
8182 10:56:02.723504 # # SVE2 PMULL present
8183 10:56:02.723623 # ok 11 cpuinfo_match_SVE2 PMULL
8184 10:56:02.723741 # ok 12 sigill_SVE2 PMULL
8185 10:56:02.723861 # # SVE2 BITPERM present
8186 10:56:02.723978 # ok 13 cpuinfo_match_SVE2 BITPERM
8187 10:56:02.724097 # ok 14 sigill_SVE2 BITPERM
8188 10:56:02.724215 # # SVE2 SHA3 present
8189 10:56:02.728128 # ok 15 cpuinfo_match_SVE2 SHA3
8190 10:56:02.728346 # ok 16 sigill_SVE2 SHA3
8191 10:56:02.728713 # # SVE2 SM4 present
8192 10:56:02.728844 # ok 17 cpuinfo_match_SVE2 SM4
8193 10:56:02.728962 # ok 18 sigill_SVE2 SM4
8194 10:56:02.729074 # # SVE2 I8MM present
8195 10:56:02.729186 # ok 19 cpuinfo_match_SVE2 I8MM
8196 10:56:02.729297 # ok 20 sigill_SVE2 I8MM
8197 10:56:02.729410 # # SVE2 F32MM present
8198 10:56:02.729524 # ok 21 cpuinfo_match_SVE2 F32MM
8199 10:56:02.729675 # ok 22 sigill_SVE2 F32MM
8200 10:56:02.729798 # # SVE2 F64MM present
8201 10:56:02.729918 # ok 23 cpuinfo_match_SVE2 F64MM
8202 10:56:02.730032 # ok 24 sigill_SVE2 F64MM
8203 10:56:02.730147 # # SVE2 BF16 present
8204 10:56:02.730261 # ok 25 cpuinfo_match_SVE2 BF16
8205 10:56:02.730373 # ok 26 sigill_SVE2 BF16
8206 10:56:02.730485 # ok 27 cpuinfo_match_SVE2 EBF16
8207 10:56:02.730596 # ok 28 # SKIP sigill_SVE2 EBF16
8208 10:56:02.730708 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8209 10:56:02.755498 ok 45 selftests: arm64: hwcap
8210 10:56:02.952619 # selftests: arm64: ptrace
8211 10:56:03.147834 # TAP version 13
8212 10:56:03.148195 # 1..7
8213 10:56:03.148420 # # Parent is 4268, child is 4269
8214 10:56:03.148565 # ok 1 read_tpidr_one
8215 10:56:03.148692 # ok 2 write_tpidr_one
8216 10:56:03.149050 # ok 3 verify_tpidr_one
8217 10:56:03.149210 # ok 4 count_tpidrs
8218 10:56:03.149335 # ok 5 tpidr2_write
8219 10:56:03.149456 # ok 6 tpidr2_read
8220 10:56:03.149573 # ok 7 write_tpidr_only
8221 10:56:03.149709 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8222 10:56:03.184011 ok 46 selftests: arm64: ptrace
8223 10:56:03.332551 # selftests: arm64: syscall-abi
8224 10:56:06.035985 # TAP version 13
8225 10:56:06.036562 # 1..514
8226 10:56:06.036754 # # SME with FA64
8227 10:56:06.036944 # ok 1 getpid() FPSIMD
8228 10:56:06.037112 # ok 2 getpid() SVE VL 256
8229 10:56:06.037270 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8230 10:56:06.037421 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8231 10:56:06.037581 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8232 10:56:06.037796 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8233 10:56:06.037957 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8234 10:56:06.038117 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8235 10:56:06.038276 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8236 10:56:06.038440 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8237 10:56:06.038600 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8238 10:56:06.038750 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8239 10:56:06.038910 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8240 10:56:06.039072 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8241 10:56:06.039232 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8242 10:56:06.039389 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8243 10:56:06.039581 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8244 10:56:06.039728 # ok 18 getpid() SVE VL 240
8245 10:56:06.039886 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8246 10:56:06.040047 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8247 10:56:06.043025 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8248 10:56:06.043449 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8249 10:56:06.043616 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8250 10:56:06.043797 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8251 10:56:06.043969 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8252 10:56:06.044176 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8253 10:56:06.044388 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8254 10:56:06.044564 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8255 10:56:06.044732 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8256 10:56:06.044885 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8257 10:56:06.045052 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8258 10:56:06.045218 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8259 10:56:06.045368 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8260 10:56:06.045538 # ok 34 getpid() SVE VL 224
8261 10:56:06.045714 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8262 10:56:06.045910 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8263 10:56:06.046094 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8264 10:56:06.046256 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8265 10:56:06.046417 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8266 10:56:06.046593 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8267 10:56:06.046747 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8268 10:56:06.046910 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8269 10:56:06.047087 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8270 10:56:06.047242 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8271 10:56:06.047410 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8272 10:56:06.047579 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8273 10:56:06.047735 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8274 10:56:06.047906 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8275 10:56:06.054444 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8276 10:56:06.054887 # ok 50 getpid() SVE VL 208
8277 10:56:06.055000 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8278 10:56:06.055094 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8279 10:56:06.055187 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8280 10:56:06.055279 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8281 10:56:06.055393 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8282 10:56:06.055486 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8283 10:56:06.055574 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8284 10:56:06.055662 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8285 10:56:06.055747 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8286 10:56:06.055854 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8287 10:56:06.055946 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8288 10:56:06.056035 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8289 10:56:06.056127 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8290 10:56:06.056240 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8291 10:56:06.056332 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8292 10:56:06.056419 # ok 66 getpid() SVE VL 192
8293 10:56:06.056508 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8294 10:56:06.056597 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8295 10:56:06.056702 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8296 10:56:06.056792 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8297 10:56:06.056881 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8298 10:56:06.056968 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8299 10:56:06.057054 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8300 10:56:06.057158 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8301 10:56:06.057247 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8302 10:56:06.057332 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8303 10:56:06.057421 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8304 10:56:06.057508 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8305 10:56:06.057593 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8306 10:56:06.057706 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8307 10:56:06.057796 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8308 10:56:06.057880 # ok 82 getpid() SVE VL 176
8309 10:56:06.057966 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8310 10:56:06.058051 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8311 10:56:06.058138 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8312 10:56:06.058224 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8313 10:56:06.058327 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8314 10:56:06.058420 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8315 10:56:06.058512 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8316 10:56:06.058597 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8317 10:56:06.058685 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8318 10:56:06.058790 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8319 10:56:06.058883 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8320 10:56:06.058989 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8321 10:56:06.059278 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8322 10:56:06.059377 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8323 10:56:06.059468 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8324 10:56:06.059557 # ok 98 getpid() SVE VL 160
8325 10:56:08.565523 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8326 10:56:08.566046 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8327 10:56:08.566154 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8328 10:56:08.566247 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8329 10:56:08.566336 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8330 10:56:08.566658 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8331 10:56:08.568391 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8332 10:56:08.568643 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8333 10:56:08.568830 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8334 10:56:08.568977 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8335 10:56:08.569343 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8336 10:56:08.569449 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8337 10:56:08.569539 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8338 10:56:08.569623 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8339 10:56:08.569717 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8340 10:56:08.569803 # ok 114 getpid() SVE VL 144
8341 10:56:08.569886 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8342 10:56:08.569976 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8343 10:56:08.570065 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8344 10:56:08.570143 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8345 10:56:08.570237 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8346 10:56:08.570315 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8347 10:56:08.570389 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8348 10:56:08.570460 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8349 10:56:08.570533 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8350 10:56:08.570604 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8351 10:56:08.575208 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8352 10:56:08.575617 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8353 10:56:08.575720 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8354 10:56:08.575807 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8355 10:56:08.575909 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8356 10:56:08.575996 # ok 130 getpid() SVE VL 128
8357 10:56:08.576080 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8358 10:56:08.576178 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8359 10:56:08.576266 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8360 10:56:08.576365 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8361 10:56:08.576476 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8362 10:56:08.576564 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8363 10:56:08.576664 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8364 10:56:08.576961 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8365 10:56:08.577063 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8366 10:56:08.577353 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8367 10:56:08.577455 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8368 10:56:08.577557 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8369 10:56:08.577654 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8370 10:56:08.577740 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8371 10:56:08.577835 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8372 10:56:08.577918 # ok 146 getpid() SVE VL 112
8373 10:56:08.578208 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8374 10:56:08.583070 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8375 10:56:08.583665 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8376 10:56:08.583868 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8377 10:56:08.584048 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8378 10:56:08.584193 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8379 10:56:08.584396 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8380 10:56:08.584570 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8381 10:56:08.584732 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8382 10:56:08.584892 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8383 10:56:08.585065 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8384 10:56:08.585215 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8385 10:56:08.585368 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8386 10:56:08.585507 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8387 10:56:08.585678 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8388 10:56:08.585835 # ok 162 getpid() SVE VL 96
8389 10:56:08.585973 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8390 10:56:08.586112 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8391 10:56:08.586243 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8392 10:56:08.586359 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8393 10:56:08.586477 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8394 10:56:08.586591 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8395 10:56:08.586707 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8396 10:56:08.586822 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8397 10:56:08.586939 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8398 10:56:08.587086 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8399 10:56:08.587206 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8400 10:56:08.587321 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8401 10:56:08.587440 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8402 10:56:08.587554 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8403 10:56:08.587669 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8404 10:56:08.591102 # ok 178 getpid() SVE VL 80
8405 10:56:08.591559 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8406 10:56:08.591704 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8407 10:56:08.591819 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8408 10:56:08.591920 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8409 10:56:08.592033 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8410 10:56:08.592127 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8411 10:56:08.592233 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8412 10:56:08.592337 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8413 10:56:08.592433 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8414 10:56:08.592532 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8415 10:56:08.592647 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8416 10:56:08.592739 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8417 10:56:08.592846 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8418 10:56:08.592938 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8419 10:56:08.593024 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8420 10:56:08.593134 # ok 194 getpid() SVE VL 64
8421 10:56:08.593226 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8422 10:56:10.887861 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8423 10:56:10.888394 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8424 10:56:10.888582 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8425 10:56:10.888753 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8426 10:56:10.888920 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8427 10:56:10.889095 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8428 10:56:10.889296 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8429 10:56:10.889510 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8430 10:56:10.889698 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8431 10:56:10.889889 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8432 10:56:10.890090 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8433 10:56:10.890265 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8434 10:56:10.890414 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8435 10:56:10.890596 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8436 10:56:10.890737 # ok 210 getpid() SVE VL 48
8437 10:56:10.890881 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8438 10:56:10.891026 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8439 10:56:10.891169 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8440 10:56:10.891311 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8441 10:56:10.891454 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8442 10:56:10.894684 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8443 10:56:10.895137 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8444 10:56:10.895351 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8445 10:56:10.895570 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8446 10:56:10.895765 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8447 10:56:10.895930 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8448 10:56:10.896099 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8449 10:56:10.896262 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8450 10:56:10.896428 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8451 10:56:10.896582 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8452 10:56:10.896769 # ok 226 getpid() SVE VL 32
8453 10:56:10.896963 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8454 10:56:10.897136 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8455 10:56:10.897293 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8456 10:56:10.897435 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8457 10:56:10.897554 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8458 10:56:10.897752 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8459 10:56:10.897960 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8460 10:56:10.898149 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8461 10:56:10.898319 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8462 10:56:10.898470 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8463 10:56:10.898615 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8464 10:56:10.898758 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8465 10:56:10.898901 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8466 10:56:10.899045 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8467 10:56:10.899188 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8468 10:56:10.899329 # ok 242 getpid() SVE VL 16
8469 10:56:10.899476 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8470 10:56:10.899620 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8471 10:56:10.899762 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8472 10:56:10.899943 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8473 10:56:10.900083 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8474 10:56:10.902833 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8475 10:56:10.903276 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8476 10:56:10.903463 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8477 10:56:10.903642 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8478 10:56:10.903827 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8479 10:56:10.903969 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8480 10:56:10.904131 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8481 10:56:10.904322 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8482 10:56:10.904494 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8483 10:56:10.904698 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8484 10:56:10.904869 # ok 258 sched_yield() FPSIMD
8485 10:56:10.905028 # ok 259 sched_yield() SVE VL 256
8486 10:56:10.905149 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8487 10:56:10.905267 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8488 10:56:10.905387 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8489 10:56:10.905503 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8490 10:56:10.905656 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8491 10:56:10.905785 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8492 10:56:10.905903 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8493 10:56:10.906016 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8494 10:56:10.906131 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8495 10:56:10.906244 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8496 10:56:10.906381 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8497 10:56:10.906499 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8498 10:56:10.906613 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8499 10:56:10.910675 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8500 10:56:10.911072 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8501 10:56:10.911278 # ok 275 sched_yield() SVE VL 240
8502 10:56:10.911479 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8503 10:56:10.911650 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8504 10:56:10.911816 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8505 10:56:10.911982 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8506 10:56:10.912180 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8507 10:56:10.912347 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8508 10:56:10.912513 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8509 10:56:10.912673 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8510 10:56:10.912835 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8511 10:56:10.912985 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8512 10:56:10.913106 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8513 10:56:10.913224 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8514 10:56:10.913339 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8515 10:56:10.913455 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8516 10:56:12.987310 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8517 10:56:12.987783 # ok 291 sched_yield() SVE VL 224
8518 10:56:12.987986 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8519 10:56:12.988170 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8520 10:56:12.988338 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8521 10:56:12.988534 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8522 10:56:12.988666 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8523 10:56:12.988813 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8524 10:56:12.988959 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8525 10:56:12.989126 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8526 10:56:12.989290 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8527 10:56:12.989432 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8528 10:56:12.989615 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8529 10:56:12.989801 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8530 10:56:12.989971 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8531 10:56:12.990108 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8532 10:56:12.990228 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8533 10:56:12.990345 # ok 307 sched_yield() SVE VL 208
8534 10:56:12.990462 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8535 10:56:12.990577 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8536 10:56:12.990692 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8537 10:56:12.990809 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8538 10:56:12.990951 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8539 10:56:12.991074 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8540 10:56:12.991192 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8541 10:56:12.991309 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8542 10:56:12.994675 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8543 10:56:12.995117 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8544 10:56:12.995330 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8545 10:56:12.995514 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8546 10:56:12.995679 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8547 10:56:12.995867 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8548 10:56:12.996008 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8549 10:56:12.996220 # ok 323 sched_yield() SVE VL 192
8550 10:56:12.996401 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8551 10:56:12.996555 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8552 10:56:12.996678 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8553 10:56:12.996848 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8554 10:56:12.997065 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8555 10:56:12.997274 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8556 10:56:12.997499 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8557 10:56:12.997710 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8558 10:56:12.997913 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8559 10:56:12.998078 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8560 10:56:12.998201 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8561 10:56:12.998316 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8562 10:56:12.998463 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8563 10:56:12.998584 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8564 10:56:12.998699 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8565 10:56:12.998812 # ok 339 sched_yield() SVE VL 176
8566 10:56:12.998926 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8567 10:56:12.999040 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8568 10:56:12.999153 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8569 10:56:12.999266 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8570 10:56:12.999379 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8571 10:56:13.002577 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8572 10:56:13.003162 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8573 10:56:13.003331 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8574 10:56:13.003458 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8575 10:56:13.003646 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8576 10:56:13.003807 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8577 10:56:13.003997 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8578 10:56:13.004176 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8579 10:56:13.004335 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8580 10:56:13.004500 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8581 10:56:13.004665 # ok 355 sched_yield() SVE VL 160
8582 10:56:13.004835 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8583 10:56:13.004991 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8584 10:56:13.005151 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8585 10:56:13.005358 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8586 10:56:13.005528 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8587 10:56:13.005701 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8588 10:56:13.005856 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8589 10:56:13.005982 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8590 10:56:13.006102 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8591 10:56:13.006221 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8592 10:56:13.006340 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8593 10:56:13.006458 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8594 10:56:13.006575 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8595 10:56:13.006694 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8596 10:56:13.006811 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8597 10:56:13.006929 # ok 371 sched_yield() SVE VL 144
8598 10:56:13.007045 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8599 10:56:13.007161 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8600 10:56:13.007310 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8601 10:56:13.007440 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8602 10:56:13.007561 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8603 10:56:15.148281 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8604 10:56:15.148525 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8605 10:56:15.148613 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8606 10:56:15.148707 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8607 10:56:15.148786 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8608 10:56:15.148860 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8609 10:56:15.148933 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8610 10:56:15.149020 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8611 10:56:15.149096 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8612 10:56:15.149169 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8613 10:56:15.149241 # ok 387 sched_yield() SVE VL 128
8614 10:56:15.149328 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8615 10:56:15.149416 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8616 10:56:15.149491 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8617 10:56:15.149564 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8618 10:56:15.149637 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8619 10:56:15.149741 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8620 10:56:15.149817 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8621 10:56:15.149904 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8622 10:56:15.149979 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8623 10:56:15.150052 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8624 10:56:15.150138 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8625 10:56:15.150213 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8626 10:56:15.158367 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8627 10:56:15.158852 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8628 10:56:15.158962 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8629 10:56:15.159050 # ok 403 sched_yield() SVE VL 112
8630 10:56:15.159134 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8631 10:56:15.159233 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8632 10:56:15.159317 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8633 10:56:15.159400 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8634 10:56:15.159480 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8635 10:56:15.159776 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8636 10:56:15.159883 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8637 10:56:15.159968 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8638 10:56:15.160049 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8639 10:56:15.160149 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8640 10:56:15.160233 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8641 10:56:15.160313 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8642 10:56:15.160415 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8643 10:56:15.160498 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8644 10:56:15.160579 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8645 10:56:15.160673 # ok 419 sched_yield() SVE VL 96
8646 10:56:15.161180 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8647 10:56:15.161284 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8648 10:56:15.161368 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8649 10:56:15.161468 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8650 10:56:15.161564 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8651 10:56:15.161886 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8652 10:56:15.161989 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8653 10:56:15.162272 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8654 10:56:15.162614 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8655 10:56:15.162705 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8656 10:56:15.164180 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8657 10:56:15.164283 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8658 10:56:15.164367 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8659 10:56:15.164448 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8660 10:56:15.164529 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8661 10:56:15.164609 # ok 435 sched_yield() SVE VL 80
8662 10:56:15.164688 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8663 10:56:15.164767 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8664 10:56:15.164846 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8665 10:56:15.164932 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8666 10:56:15.165012 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8667 10:56:15.165091 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8668 10:56:15.165171 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8669 10:56:15.165250 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8670 10:56:15.165329 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8671 10:56:15.165408 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8672 10:56:15.165488 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8673 10:56:15.165567 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8674 10:56:15.165857 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8675 10:56:15.165948 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8676 10:56:15.166030 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8677 10:56:15.166110 # ok 451 sched_yield() SVE VL 64
8678 10:56:15.166189 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8679 10:56:15.166269 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8680 10:56:15.166348 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8681 10:56:15.166428 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8682 10:56:15.166515 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8683 10:56:15.166595 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8684 10:56:15.166674 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8685 10:56:15.166754 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8686 10:56:15.166833 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8687 10:56:15.166912 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8688 10:56:15.166991 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8689 10:56:15.167069 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8690 10:56:15.836298 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8691 10:56:15.836622 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8692 10:56:15.837043 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8693 10:56:15.837244 # ok 467 sched_yield() SVE VL 48
8694 10:56:15.837431 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8695 10:56:15.837621 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8696 10:56:15.837817 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8697 10:56:15.837975 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8698 10:56:15.838143 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8699 10:56:15.838282 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8700 10:56:15.838435 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8701 10:56:15.838563 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8702 10:56:15.838684 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8703 10:56:15.838802 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8704 10:56:15.838920 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8705 10:56:15.839039 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8706 10:56:15.839157 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8707 10:56:15.839274 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8708 10:56:15.839422 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8709 10:56:15.845705 # ok 483 sched_yield() SVE VL 32
8710 10:56:15.846168 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8711 10:56:15.846329 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8712 10:56:15.846454 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8713 10:56:15.846912 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8714 10:56:15.847308 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8715 10:56:15.847488 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8716 10:56:15.847660 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8717 10:56:15.847833 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8718 10:56:15.847968 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8719 10:56:15.848087 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8720 10:56:15.848204 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8721 10:56:15.848322 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8722 10:56:15.848439 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8723 10:56:15.848557 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8724 10:56:15.848703 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8725 10:56:15.848833 # ok 499 sched_yield() SVE VL 16
8726 10:56:15.848952 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8727 10:56:15.849070 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8728 10:56:15.849189 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8729 10:56:15.849307 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8730 10:56:15.849426 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8731 10:56:15.849543 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8732 10:56:15.849674 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8733 10:56:15.849796 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8734 10:56:15.849946 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8735 10:56:15.850075 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8736 10:56:15.850194 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8737 10:56:15.850313 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8738 10:56:15.850438 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8739 10:56:15.850558 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8740 10:56:15.850676 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8741 10:56:15.850793 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8742 10:56:15.850910 ok 47 selftests: arm64: syscall-abi
8743 10:56:15.897305 # selftests: arm64: tpidr2
8744 10:56:16.046456 # TAP version 13
8745 10:56:16.046702 # 1..5
8746 10:56:16.046799 # # PID: 4303
8747 10:56:16.047096 # ok 1 default_value
8748 10:56:16.047190 # ok 2 write_read
8749 10:56:16.047276 # ok 3 write_sleep_read
8750 10:56:16.047362 # ok 4 write_fork_read
8751 10:56:16.047445 # ok 5 write_clone_read
8752 10:56:16.047534 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8753 10:56:16.057483 ok 48 selftests: arm64: tpidr2
8754 10:56:16.543066 arm64_tags_test pass
8755 10:56:16.543473 arm64_run_tags_test_sh pass
8756 10:56:16.543909 arm64_fake_sigreturn_bad_magic pass
8757 10:56:16.544089 arm64_fake_sigreturn_bad_size pass
8758 10:56:16.544283 arm64_fake_sigreturn_bad_size_for_magic0 pass
8759 10:56:16.544452 arm64_fake_sigreturn_duplicated_fpsimd pass
8760 10:56:16.544586 arm64_fake_sigreturn_misaligned_sp pass
8761 10:56:16.544706 arm64_fake_sigreturn_missing_fpsimd pass
8762 10:56:16.544824 arm64_fake_sigreturn_sme_change_vl pass
8763 10:56:16.544942 arm64_fake_sigreturn_sve_change_vl pass
8764 10:56:16.545063 arm64_mangle_pstate_invalid_compat_toggle pass
8765 10:56:16.545213 arm64_mangle_pstate_invalid_daif_bits pass
8766 10:56:16.545341 arm64_mangle_pstate_invalid_mode_el1h pass
8767 10:56:16.545461 arm64_mangle_pstate_invalid_mode_el1t pass
8768 10:56:16.545579 arm64_mangle_pstate_invalid_mode_el2h pass
8769 10:56:16.545713 arm64_mangle_pstate_invalid_mode_el2t pass
8770 10:56:16.545832 arm64_mangle_pstate_invalid_mode_el3h pass
8771 10:56:16.545950 arm64_mangle_pstate_invalid_mode_el3t pass
8772 10:56:16.546068 arm64_sme_trap_no_sm pass
8773 10:56:16.546190 arm64_sme_trap_non_streaming skip
8774 10:56:16.546306 arm64_sme_trap_za pass
8775 10:56:16.546424 arm64_sme_vl pass
8776 10:56:16.546540 arm64_ssve_regs pass
8777 10:56:16.546656 arm64_sve_regs pass
8778 10:56:16.546774 arm64_sve_vl pass
8779 10:56:16.546891 arm64_za_no_regs pass
8780 10:56:16.547007 arm64_za_regs pass
8781 10:56:16.547127 arm64_pac_global_corrupt_pac pass
8782 10:56:16.547274 arm64_pac_global_pac_instructions_not_nop pass
8783 10:56:16.547398 arm64_pac_global_pac_instructions_not_nop_generic pass
8784 10:56:16.547566 arm64_pac_global_single_thread_different_keys pass
8785 10:56:16.547702 arm64_pac_global_exec_changed_keys pass
8786 10:56:16.547822 arm64_pac_global_context_switch_keep_keys pass
8787 10:56:16.547940 arm64_pac_global_context_switch_keep_keys_generic pass
8788 10:56:16.548059 arm64_pac pass
8789 10:56:16.548180 arm64_fp-stress_FPSIMD-0-0 pass
8790 10:56:16.548298 arm64_fp-stress_SVE-VL-256-0 pass
8791 10:56:16.548414 arm64_fp-stress_SVE-VL-240-0 pass
8792 10:56:16.548531 arm64_fp-stress_SVE-VL-224-0 pass
8793 10:56:16.548646 arm64_fp-stress_SVE-VL-208-0 pass
8794 10:56:16.550189 arm64_fp-stress_SVE-VL-192-0 pass
8795 10:56:16.550533 arm64_fp-stress_SVE-VL-176-0 pass
8796 10:56:16.550665 arm64_fp-stress_SVE-VL-160-0 pass
8797 10:56:16.550787 arm64_fp-stress_SVE-VL-144-0 pass
8798 10:56:16.550907 arm64_fp-stress_SVE-VL-128-0 pass
8799 10:56:16.551026 arm64_fp-stress_SVE-VL-112-0 pass
8800 10:56:16.551145 arm64_fp-stress_SVE-VL-96-0 pass
8801 10:56:16.551290 arm64_fp-stress_SVE-VL-80-0 pass
8802 10:56:16.551430 arm64_fp-stress_SVE-VL-64-0 pass
8803 10:56:16.551569 arm64_fp-stress_SVE-VL-48-0 pass
8804 10:56:16.551690 arm64_fp-stress_SVE-VL-32-0 pass
8805 10:56:16.551810 arm64_fp-stress_SVE-VL-16-0 pass
8806 10:56:16.551927 arm64_fp-stress_SSVE-VL-256-0 pass
8807 10:56:16.552047 arm64_fp-stress_ZA-VL-256-0 pass
8808 10:56:16.552165 arm64_fp-stress_SSVE-VL-128-0 pass
8809 10:56:16.552283 arm64_fp-stress_ZA-VL-128-0 pass
8810 10:56:16.552402 arm64_fp-stress_SSVE-VL-64-0 pass
8811 10:56:16.552520 arm64_fp-stress_ZA-VL-64-0 pass
8812 10:56:16.552670 arm64_fp-stress_SSVE-VL-32-0 pass
8813 10:56:16.552796 arm64_fp-stress_ZA-VL-32-0 pass
8814 10:56:16.552917 arm64_fp-stress_SSVE-VL-16-0 pass
8815 10:56:16.553036 arm64_fp-stress_ZA-VL-16-0 pass
8816 10:56:16.553157 arm64_fp-stress pass
8817 10:56:16.553277 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8818 10:56:16.553395 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8819 10:56:16.553515 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8820 10:56:16.553633 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8821 10:56:16.553767 arm64_sve-ptrace_Set_SVE_VL_16 pass
8822 10:56:16.553886 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8823 10:56:16.554006 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8824 10:56:16.554128 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8825 10:56:16.554246 arm64_sve-ptrace_Set_SVE_VL_32 pass
8826 10:56:16.554415 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8827 10:56:16.554586 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8828 10:56:16.554714 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8829 10:56:16.554834 arm64_sve-ptrace_Set_SVE_VL_48 pass
8830 10:56:16.554952 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8831 10:56:16.555071 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8832 10:56:16.555194 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8833 10:56:16.555314 arm64_sve-ptrace_Set_SVE_VL_64 pass
8834 10:56:16.555481 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8835 10:56:16.555619 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8836 10:56:16.555741 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8837 10:56:16.555860 arm64_sve-ptrace_Set_SVE_VL_80 pass
8838 10:56:16.555979 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8839 10:56:16.556097 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8840 10:56:16.556426 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8841 10:56:16.556559 arm64_sve-ptrace_Set_SVE_VL_96 pass
8842 10:56:16.558261 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8843 10:56:16.558646 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8844 10:56:16.558781 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8845 10:56:16.558902 arm64_sve-ptrace_Set_SVE_VL_112 pass
8846 10:56:16.559045 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8847 10:56:16.559170 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8848 10:56:16.559316 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8849 10:56:16.559499 arm64_sve-ptrace_Set_SVE_VL_128 pass
8850 10:56:16.559637 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8851 10:56:16.559788 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8852 10:56:16.559913 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8853 10:56:16.560036 arm64_sve-ptrace_Set_SVE_VL_144 pass
8854 10:56:16.560158 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8855 10:56:16.560274 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8856 10:56:16.560393 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8857 10:56:16.560509 arm64_sve-ptrace_Set_SVE_VL_160 pass
8858 10:56:16.560627 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8859 10:56:16.560773 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8860 10:56:16.560896 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8861 10:56:16.561016 arm64_sve-ptrace_Set_SVE_VL_176 pass
8862 10:56:16.561135 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8863 10:56:16.561258 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8864 10:56:16.561376 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8865 10:56:16.561495 arm64_sve-ptrace_Set_SVE_VL_192 pass
8866 10:56:16.561615 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8867 10:56:16.561778 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8868 10:56:16.561905 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8869 10:56:16.562027 arm64_sve-ptrace_Set_SVE_VL_208 pass
8870 10:56:16.562146 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8871 10:56:16.562264 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8872 10:56:16.562382 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8873 10:56:16.562503 arm64_sve-ptrace_Set_SVE_VL_224 pass
8874 10:56:16.562621 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8875 10:56:16.562739 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8876 10:56:16.562858 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8877 10:56:16.562977 arm64_sve-ptrace_Set_SVE_VL_240 pass
8878 10:56:16.563121 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8879 10:56:16.563458 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8880 10:56:16.563599 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8881 10:56:16.566247 arm64_sve-ptrace_Set_SVE_VL_256 pass
8882 10:56:16.566606 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8883 10:56:16.566739 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8884 10:56:16.566862 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8885 10:56:16.567006 arm64_sve-ptrace_Set_SVE_VL_272 pass
8886 10:56:16.567129 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8887 10:56:16.567250 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8888 10:56:16.567387 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8889 10:56:16.567577 arm64_sve-ptrace_Set_SVE_VL_288 pass
8890 10:56:16.567761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8891 10:56:16.567888 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8892 10:56:16.568009 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8893 10:56:16.568128 arm64_sve-ptrace_Set_SVE_VL_304 pass
8894 10:56:16.568246 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8895 10:56:16.568365 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8896 10:56:16.568483 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8897 10:56:16.568602 arm64_sve-ptrace_Set_SVE_VL_320 pass
8898 10:56:16.568746 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8899 10:56:16.568872 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8900 10:56:16.568990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8901 10:56:16.569111 arm64_sve-ptrace_Set_SVE_VL_336 pass
8902 10:56:16.569253 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8903 10:56:16.569454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8904 10:56:16.569674 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8905 10:56:16.569913 arm64_sve-ptrace_Set_SVE_VL_352 pass
8906 10:56:16.570097 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8907 10:56:16.570264 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8908 10:56:16.570392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8909 10:56:16.570512 arm64_sve-ptrace_Set_SVE_VL_368 pass
8910 10:56:16.570631 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8911 10:56:16.570750 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8912 10:56:16.570867 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8913 10:56:16.570984 arm64_sve-ptrace_Set_SVE_VL_384 pass
8914 10:56:16.571103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8915 10:56:16.571220 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8916 10:56:16.571337 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8917 10:56:16.571509 arm64_sve-ptrace_Set_SVE_VL_400 pass
8918 10:56:16.571644 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8919 10:56:16.571766 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8920 10:56:16.574203 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8921 10:56:16.574545 arm64_sve-ptrace_Set_SVE_VL_416 pass
8922 10:56:16.574675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8923 10:56:16.574796 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8924 10:56:16.574939 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8925 10:56:16.575063 arm64_sve-ptrace_Set_SVE_VL_432 pass
8926 10:56:16.575181 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8927 10:56:16.575299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8928 10:56:16.575433 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8929 10:56:16.575590 arm64_sve-ptrace_Set_SVE_VL_448 pass
8930 10:56:16.575714 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8931 10:56:16.575833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8932 10:56:16.589986 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8933 10:56:16.590381 arm64_sve-ptrace_Set_SVE_VL_464 pass
8934 10:56:16.590516 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8935 10:56:16.590638 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8936 10:56:16.590783 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8937 10:56:16.590907 arm64_sve-ptrace_Set_SVE_VL_480 pass
8938 10:56:16.591028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8939 10:56:16.591146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8940 10:56:16.591269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8941 10:56:16.591399 arm64_sve-ptrace_Set_SVE_VL_496 pass
8942 10:56:16.591564 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8943 10:56:16.591691 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8944 10:56:16.591811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8945 10:56:16.591930 arm64_sve-ptrace_Set_SVE_VL_512 pass
8946 10:56:16.592049 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8947 10:56:16.592171 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8948 10:56:16.592316 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8949 10:56:16.592443 arm64_sve-ptrace_Set_SVE_VL_528 pass
8950 10:56:16.592562 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8951 10:56:16.592681 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8952 10:56:16.592801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8953 10:56:16.592920 arm64_sve-ptrace_Set_SVE_VL_544 pass
8954 10:56:16.593038 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8955 10:56:16.593157 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8956 10:56:16.593303 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8957 10:56:16.593427 arm64_sve-ptrace_Set_SVE_VL_560 pass
8958 10:56:16.593547 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8959 10:56:16.593683 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8960 10:56:16.593810 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8961 10:56:16.593985 arm64_sve-ptrace_Set_SVE_VL_576 pass
8962 10:56:16.594121 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8963 10:56:16.594244 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8964 10:56:16.594363 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8965 10:56:16.594481 arm64_sve-ptrace_Set_SVE_VL_592 pass
8966 10:56:16.594625 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8967 10:56:16.594752 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8968 10:56:16.594871 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8969 10:56:16.594991 arm64_sve-ptrace_Set_SVE_VL_608 pass
8970 10:56:16.595108 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
8971 10:56:16.595449 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
8972 10:56:16.595606 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
8973 10:56:16.598283 arm64_sve-ptrace_Set_SVE_VL_624 pass
8974 10:56:16.598476 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
8975 10:56:16.598812 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
8976 10:56:16.598966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
8977 10:56:16.599156 arm64_sve-ptrace_Set_SVE_VL_640 pass
8978 10:56:16.599361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
8979 10:56:16.599576 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
8980 10:56:16.599812 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
8981 10:56:16.599962 arm64_sve-ptrace_Set_SVE_VL_656 pass
8982 10:56:16.600123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
8983 10:56:16.600304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
8984 10:56:16.600457 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
8985 10:56:16.600647 arm64_sve-ptrace_Set_SVE_VL_672 pass
8986 10:56:16.600869 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
8987 10:56:16.601061 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
8988 10:56:16.601270 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
8989 10:56:16.601472 arm64_sve-ptrace_Set_SVE_VL_688 pass
8990 10:56:16.601630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
8991 10:56:16.601843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
8992 10:56:16.601994 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
8993 10:56:16.602121 arm64_sve-ptrace_Set_SVE_VL_704 pass
8994 10:56:16.602240 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
8995 10:56:16.602358 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
8996 10:56:16.602474 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
8997 10:56:16.602590 arm64_sve-ptrace_Set_SVE_VL_720 pass
8998 10:56:16.602705 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
8999 10:56:16.602850 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
9000 10:56:16.602974 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9001 10:56:16.603090 arm64_sve-ptrace_Set_SVE_VL_736 pass
9002 10:56:16.603209 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9003 10:56:16.603325 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9004 10:56:16.603488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9005 10:56:16.603627 arm64_sve-ptrace_Set_SVE_VL_752 pass
9006 10:56:16.606195 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9007 10:56:16.606513 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9008 10:56:16.606619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9009 10:56:16.606708 arm64_sve-ptrace_Set_SVE_VL_768 pass
9010 10:56:16.606810 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9011 10:56:16.606899 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9012 10:56:16.606997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9013 10:56:16.607105 arm64_sve-ptrace_Set_SVE_VL_784 pass
9014 10:56:16.607412 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9015 10:56:16.607530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9016 10:56:16.607635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9017 10:56:16.607737 arm64_sve-ptrace_Set_SVE_VL_800 pass
9018 10:56:16.608025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9019 10:56:16.608118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9020 10:56:16.608219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9021 10:56:16.608307 arm64_sve-ptrace_Set_SVE_VL_816 pass
9022 10:56:16.608405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9023 10:56:16.608691 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9024 10:56:16.608783 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9025 10:56:16.608884 arm64_sve-ptrace_Set_SVE_VL_832 pass
9026 10:56:16.608972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9027 10:56:16.609070 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9028 10:56:16.609188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9029 10:56:16.609518 arm64_sve-ptrace_Set_SVE_VL_848 pass
9030 10:56:16.609717 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9031 10:56:16.609907 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9032 10:56:16.610074 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9033 10:56:16.610204 arm64_sve-ptrace_Set_SVE_VL_864 pass
9034 10:56:16.610322 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9035 10:56:16.610463 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9036 10:56:16.614228 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9037 10:56:16.614678 arm64_sve-ptrace_Set_SVE_VL_880 pass
9038 10:56:16.614867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9039 10:56:16.615044 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9040 10:56:16.615225 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9041 10:56:16.615362 arm64_sve-ptrace_Set_SVE_VL_896 pass
9042 10:56:16.615566 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9043 10:56:16.615769 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9044 10:56:16.615940 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9045 10:56:16.616087 arm64_sve-ptrace_Set_SVE_VL_912 pass
9046 10:56:16.616294 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9047 10:56:16.616440 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9048 10:56:16.616570 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9049 10:56:16.616700 arm64_sve-ptrace_Set_SVE_VL_928 pass
9050 10:56:16.616826 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9051 10:56:16.616955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9052 10:56:16.617086 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9053 10:56:16.617216 arm64_sve-ptrace_Set_SVE_VL_944 pass
9054 10:56:16.617367 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9055 10:56:16.617592 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9056 10:56:16.617810 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9057 10:56:16.618000 arm64_sve-ptrace_Set_SVE_VL_960 pass
9058 10:56:16.618193 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9059 10:56:16.618379 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9060 10:56:16.618568 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9061 10:56:16.618779 arm64_sve-ptrace_Set_SVE_VL_976 pass
9062 10:56:16.618939 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9063 10:56:16.619067 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9064 10:56:16.619189 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9065 10:56:16.619307 arm64_sve-ptrace_Set_SVE_VL_992 pass
9066 10:56:16.619470 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9067 10:56:16.619638 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9068 10:56:16.619766 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9069 10:56:16.619886 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9070 10:56:16.620004 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9071 10:56:16.620124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9072 10:56:16.620244 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9073 10:56:16.622192 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9074 10:56:16.622565 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9075 10:56:16.622707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9076 10:56:16.622838 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9077 10:56:16.622965 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9078 10:56:16.623116 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9079 10:56:16.623290 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9080 10:56:16.623497 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9081 10:56:16.623692 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9082 10:56:16.623878 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9083 10:56:16.624101 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9084 10:56:16.624329 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9085 10:56:16.624501 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9086 10:56:16.624633 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9087 10:56:16.624752 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9088 10:56:16.624919 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9089 10:56:16.625052 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9090 10:56:16.625169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9091 10:56:16.625283 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9092 10:56:16.625428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9093 10:56:16.625552 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9094 10:56:16.637277 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9095 10:56:16.637584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9096 10:56:16.637691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9097 10:56:16.637779 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9098 10:56:16.637884 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9099 10:56:16.637972 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9100 10:56:16.638075 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9101 10:56:16.638422 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9102 10:56:16.638671 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9103 10:56:16.638833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9104 10:56:16.639005 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9105 10:56:16.639168 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9106 10:56:16.639308 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9107 10:56:16.639527 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9108 10:56:16.639679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9109 10:56:16.639835 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9110 10:56:16.640022 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9111 10:56:16.640189 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9112 10:56:16.640347 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9113 10:56:16.640539 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9114 10:56:16.640688 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9115 10:56:16.640848 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9116 10:56:16.641008 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9117 10:56:16.641140 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9118 10:56:16.641271 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9119 10:56:16.641445 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9120 10:56:16.641583 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9121 10:56:16.642211 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9122 10:56:16.642388 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9123 10:56:16.642536 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9124 10:56:16.642680 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9125 10:56:16.642823 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9126 10:56:16.643001 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9127 10:56:16.643138 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9128 10:56:16.643283 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9129 10:56:16.643433 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9130 10:56:16.646308 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9131 10:56:16.646546 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9132 10:56:16.646953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9133 10:56:16.647147 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9134 10:56:16.647310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9135 10:56:16.647439 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9136 10:56:16.647632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9137 10:56:16.647806 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9138 10:56:16.647944 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9139 10:56:16.648063 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9140 10:56:16.648179 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9141 10:56:16.648324 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9142 10:56:16.648500 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9143 10:56:16.648650 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9144 10:56:16.648803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9145 10:56:16.648948 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9146 10:56:16.649095 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9147 10:56:16.649214 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9148 10:56:16.649334 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9149 10:56:16.649487 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9150 10:56:16.649661 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9151 10:56:16.649816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9152 10:56:16.650020 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9153 10:56:16.650160 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9154 10:56:16.650278 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9155 10:56:16.650392 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9156 10:56:16.650507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9157 10:56:16.650651 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9158 10:56:16.650773 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9159 10:56:16.650890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9160 10:56:16.651006 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9161 10:56:16.654239 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9162 10:56:16.654707 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9163 10:56:16.654913 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9164 10:56:16.655077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9165 10:56:16.655226 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9166 10:56:16.655367 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9167 10:56:16.655488 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9168 10:56:16.655608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9169 10:56:16.655725 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9170 10:56:16.655842 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9171 10:56:16.655959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9172 10:56:16.656099 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9173 10:56:16.656221 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9174 10:56:16.656310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9175 10:56:16.656390 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9176 10:56:16.656469 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9177 10:56:16.656549 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9178 10:56:16.656628 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9179 10:56:16.656724 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9180 10:56:16.656811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9181 10:56:16.656897 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9182 10:56:16.656977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9183 10:56:16.657057 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9184 10:56:16.657136 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9185 10:56:16.657215 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9186 10:56:16.657312 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9187 10:56:16.657395 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9188 10:56:16.657476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9189 10:56:16.657555 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9190 10:56:16.657634 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9191 10:56:16.657723 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9192 10:56:16.657803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9193 10:56:16.657884 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9194 10:56:16.657979 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9195 10:56:16.658062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9196 10:56:16.658142 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9197 10:56:16.658224 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9198 10:56:16.658306 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9199 10:56:16.658576 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9200 10:56:16.658661 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9201 10:56:16.658742 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9202 10:56:16.662239 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9203 10:56:16.662515 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9204 10:56:16.662616 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9205 10:56:16.662699 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9206 10:56:16.662778 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9207 10:56:16.662858 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9208 10:56:16.662952 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9209 10:56:16.663034 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9210 10:56:16.663114 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9211 10:56:16.663193 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9212 10:56:16.663287 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9213 10:56:16.663369 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9214 10:56:16.663448 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9215 10:56:16.663541 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9216 10:56:16.663624 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9217 10:56:16.663704 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9218 10:56:16.663797 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9219 10:56:16.663878 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9220 10:56:16.663971 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9221 10:56:16.664053 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9222 10:56:16.664145 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9223 10:56:16.664240 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9224 10:56:16.664343 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9225 10:56:16.664452 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9226 10:56:16.664741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9227 10:56:16.664847 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9228 10:56:16.664928 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9229 10:56:16.665006 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9230 10:56:16.665099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9231 10:56:16.665179 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9232 10:56:16.665275 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9233 10:56:16.665356 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9234 10:56:16.665447 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9235 10:56:16.665539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9236 10:56:16.665632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9237 10:56:16.665720 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9238 10:56:16.665813 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9239 10:56:16.665906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9240 10:56:16.666176 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9241 10:56:16.670228 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9242 10:56:16.670526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9243 10:56:16.670629 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9244 10:56:16.670712 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9245 10:56:16.670805 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9246 10:56:16.670887 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9247 10:56:16.670981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9248 10:56:16.671073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9249 10:56:16.671165 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9250 10:56:16.671458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9251 10:56:16.671561 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9252 10:56:16.671657 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9253 10:56:16.671739 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9254 10:56:16.685314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9255 10:56:16.685774 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9256 10:56:16.685883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9257 10:56:16.685965 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9258 10:56:16.686047 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9259 10:56:16.686127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9260 10:56:16.686222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9261 10:56:16.686305 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9262 10:56:16.686405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9263 10:56:16.686487 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9264 10:56:16.686589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9265 10:56:16.686685 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9266 10:56:16.686966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9267 10:56:16.687065 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9268 10:56:16.687161 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9269 10:56:16.687245 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9270 10:56:16.687341 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9271 10:56:16.687436 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9272 10:56:16.687714 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9273 10:56:16.687800 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9274 10:56:16.687893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9275 10:56:16.687988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9276 10:56:16.688279 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9277 10:56:16.688396 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9278 10:56:16.688479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9279 10:56:16.688570 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9280 10:56:16.688663 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9281 10:56:16.688987 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9282 10:56:16.689103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9283 10:56:16.689186 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9284 10:56:16.689280 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9285 10:56:16.689595 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9286 10:56:16.689849 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9287 10:56:16.689950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9288 10:56:16.690031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9289 10:56:16.690124 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9290 10:56:16.694379 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9291 10:56:16.694710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9292 10:56:16.695319 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9293 10:56:16.695507 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9294 10:56:16.695647 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9295 10:56:16.695793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9296 10:56:16.695961 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9297 10:56:16.696130 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9298 10:56:16.696281 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9299 10:56:16.696438 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9300 10:56:16.696596 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9301 10:56:16.696987 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9302 10:56:16.697162 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9303 10:56:16.697989 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9304 10:56:16.698146 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9305 10:56:16.698271 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9306 10:56:16.698393 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9307 10:56:16.698511 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9308 10:56:16.698631 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9309 10:56:16.698750 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9310 10:56:16.698867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9311 10:56:16.698985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9312 10:56:16.699102 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9313 10:56:16.699221 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9314 10:56:16.699388 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9315 10:56:16.699525 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9316 10:56:16.699646 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9317 10:56:16.699764 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9318 10:56:16.699881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9319 10:56:16.699999 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9320 10:56:16.700117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9321 10:56:16.700234 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9322 10:56:16.700353 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9323 10:56:16.700471 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9324 10:56:16.700589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9325 10:56:16.700706 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9326 10:56:16.700824 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9327 10:56:16.700942 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9328 10:56:16.701061 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9329 10:56:16.701178 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9330 10:56:16.701296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9331 10:56:16.701623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9332 10:56:16.702369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9333 10:56:16.702584 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9334 10:56:16.702749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9335 10:56:16.702952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9336 10:56:16.703127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9337 10:56:16.703276 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9338 10:56:16.703467 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9339 10:56:16.703634 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9340 10:56:16.703833 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9341 10:56:16.704025 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9342 10:56:16.704208 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9343 10:56:16.704366 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9344 10:56:16.704511 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9345 10:56:16.704664 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9346 10:56:16.704817 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9347 10:56:16.704958 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9348 10:56:16.705130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9349 10:56:16.705282 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9350 10:56:16.705435 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9351 10:56:16.705590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9352 10:56:16.705792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9353 10:56:16.705994 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9354 10:56:16.706182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9355 10:56:16.706371 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9356 10:56:16.706533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9357 10:56:16.706720 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9358 10:56:16.706861 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9359 10:56:16.707007 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9360 10:56:16.707152 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9361 10:56:16.707298 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9362 10:56:16.707445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9363 10:56:16.707589 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9364 10:56:16.707734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9365 10:56:16.710184 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9366 10:56:16.710533 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9367 10:56:16.710670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9368 10:56:16.710819 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9369 10:56:16.710997 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9370 10:56:16.711149 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9371 10:56:16.711332 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9372 10:56:16.711478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9373 10:56:16.711606 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9374 10:56:16.711796 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9375 10:56:16.711935 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9376 10:56:16.712055 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9377 10:56:16.712173 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9378 10:56:16.712291 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9379 10:56:16.712412 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9380 10:56:16.712528 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9381 10:56:16.712672 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9382 10:56:16.712794 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9383 10:56:16.712913 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9384 10:56:16.713030 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9385 10:56:16.713146 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9386 10:56:16.713262 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9387 10:56:16.713384 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9388 10:56:16.713500 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9389 10:56:16.713618 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9390 10:56:16.713780 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9391 10:56:16.713904 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9392 10:56:16.714020 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9393 10:56:16.714135 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9394 10:56:16.714250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9395 10:56:16.714367 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9396 10:56:16.714481 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9397 10:56:16.714595 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9398 10:56:16.714708 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9399 10:56:16.714822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9400 10:56:16.714936 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9401 10:56:16.715072 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9402 10:56:16.715192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9403 10:56:16.715511 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9404 10:56:16.718206 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9405 10:56:16.718571 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9406 10:56:16.718701 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9407 10:56:16.718820 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9408 10:56:16.718959 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9409 10:56:16.719080 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9410 10:56:16.719196 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9411 10:56:16.719311 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9412 10:56:16.719425 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9413 10:56:16.719561 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9414 10:56:16.733605 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9415 10:56:16.733949 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9416 10:56:16.734140 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9417 10:56:16.734567 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9418 10:56:16.734670 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9419 10:56:16.734753 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9420 10:56:16.734832 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9421 10:56:16.734911 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9422 10:56:16.734990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9423 10:56:16.735085 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9424 10:56:16.735166 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9425 10:56:16.735245 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9426 10:56:16.735323 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9427 10:56:16.735636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9428 10:56:16.735726 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9429 10:56:16.735805 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9430 10:56:16.735882 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9431 10:56:16.735974 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9432 10:56:16.736055 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9433 10:56:16.736147 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9434 10:56:16.736228 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9435 10:56:16.736319 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9436 10:56:16.736413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9437 10:56:16.736731 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9438 10:56:16.736839 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9439 10:56:16.736934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9440 10:56:16.737015 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9441 10:56:16.737106 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9442 10:56:16.737199 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9443 10:56:16.737382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9444 10:56:16.737615 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9445 10:56:16.737857 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9446 10:56:16.738051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9447 10:56:16.738212 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9448 10:56:16.742192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9449 10:56:16.742502 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9450 10:56:16.742619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9451 10:56:16.742702 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9452 10:56:16.742794 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9453 10:56:16.742887 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9454 10:56:16.743421 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9455 10:56:16.743535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9456 10:56:16.743839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9457 10:56:16.743943 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9458 10:56:16.744024 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9459 10:56:16.744103 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9460 10:56:16.744195 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9461 10:56:16.744417 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9462 10:56:16.744513 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9463 10:56:16.744594 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9464 10:56:16.744673 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9465 10:56:16.744962 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9466 10:56:16.745070 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9467 10:56:16.745151 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9468 10:56:16.745230 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9469 10:56:16.745322 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9470 10:56:16.745404 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9471 10:56:16.745529 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9472 10:56:16.745658 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9473 10:56:16.745748 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9474 10:56:16.745840 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9475 10:56:16.746133 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9476 10:56:16.750185 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9477 10:56:16.750487 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9478 10:56:16.750589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9479 10:56:16.750673 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9480 10:56:16.750766 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9481 10:56:16.750846 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9482 10:56:16.750937 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9483 10:56:16.751018 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9484 10:56:16.751109 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9485 10:56:16.751201 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9486 10:56:16.751498 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9487 10:56:16.751602 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9488 10:56:16.751697 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9489 10:56:16.751781 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9490 10:56:16.751949 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9491 10:56:16.752047 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9492 10:56:16.752140 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9493 10:56:16.752231 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9494 10:56:16.752527 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9495 10:56:16.752644 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9496 10:56:16.752742 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9497 10:56:16.752836 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9498 10:56:16.752930 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9499 10:56:16.753257 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9500 10:56:16.753471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9501 10:56:16.753656 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9502 10:56:16.753860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9503 10:56:16.754028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9504 10:56:16.754185 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9505 10:56:16.754305 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9506 10:56:16.754423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9507 10:56:16.754566 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9508 10:56:16.758248 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9509 10:56:16.758571 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9510 10:56:16.758678 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9511 10:56:16.758771 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9512 10:56:16.758870 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9513 10:56:16.758996 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9514 10:56:16.759103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9515 10:56:16.759213 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9516 10:56:16.759644 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9517 10:56:16.759834 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9518 10:56:16.760004 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9519 10:56:16.760199 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9520 10:56:16.760364 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9521 10:56:16.760498 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9522 10:56:16.760656 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9523 10:56:16.760883 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9524 10:56:16.761112 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9525 10:56:16.761332 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9526 10:56:16.761548 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9527 10:56:16.762196 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9528 10:56:16.762381 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9529 10:56:16.762512 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9530 10:56:16.762631 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9531 10:56:16.762747 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9532 10:56:16.762868 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9533 10:56:16.763088 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9534 10:56:16.763262 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9535 10:56:16.763426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9536 10:56:16.766314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9537 10:56:16.766761 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9538 10:56:16.766962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9539 10:56:16.767164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9540 10:56:16.767420 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9541 10:56:16.767612 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9542 10:56:16.767786 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9543 10:56:16.767985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9544 10:56:16.768209 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9545 10:56:16.768465 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9546 10:56:16.768679 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9547 10:56:16.768879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9548 10:56:16.769055 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9549 10:56:16.769274 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9550 10:56:16.769493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9551 10:56:16.769736 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9552 10:56:16.769936 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9553 10:56:16.770175 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9554 10:56:16.770339 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9555 10:56:16.770487 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9556 10:56:16.770633 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9557 10:56:16.770777 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9558 10:56:16.770921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9559 10:56:16.771064 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9560 10:56:16.771207 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9561 10:56:16.771348 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9562 10:56:16.771494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9563 10:56:16.771637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9564 10:56:16.774267 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9565 10:56:16.774722 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9566 10:56:16.774940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9567 10:56:16.775146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9568 10:56:16.775355 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9569 10:56:16.775532 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9570 10:56:16.775666 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9571 10:56:16.775785 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9572 10:56:16.775927 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9573 10:56:16.776114 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9574 10:56:16.791458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9575 10:56:16.792030 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9576 10:56:16.792242 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9577 10:56:16.792424 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9578 10:56:16.792600 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9579 10:56:16.792797 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9580 10:56:16.793029 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9581 10:56:16.793210 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9582 10:56:16.793404 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9583 10:56:16.793599 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9584 10:56:16.793797 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9585 10:56:16.793985 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9586 10:56:16.794147 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9587 10:56:16.794310 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9588 10:56:16.794509 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9589 10:56:16.794652 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9590 10:56:16.794784 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9591 10:56:16.794913 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9592 10:56:16.795040 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9593 10:56:16.795167 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9594 10:56:16.795294 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9595 10:56:16.795420 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9596 10:56:16.795546 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9597 10:56:16.795665 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9598 10:56:16.795794 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9599 10:56:16.796013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9600 10:56:16.796171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9601 10:56:16.796344 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9602 10:56:16.796478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9603 10:56:16.796691 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9604 10:56:16.796861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9605 10:56:16.796994 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9606 10:56:16.797112 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9607 10:56:16.797227 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9608 10:56:16.797341 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9609 10:56:16.797455 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9610 10:56:16.797569 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9611 10:56:16.797761 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9612 10:56:16.798197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9613 10:56:16.798393 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9614 10:56:16.798577 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9615 10:56:16.798742 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9616 10:56:16.798899 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9617 10:56:16.799056 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9618 10:56:16.799213 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9619 10:56:16.799370 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9620 10:56:16.799528 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9621 10:56:16.799684 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9622 10:56:16.799840 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9623 10:56:16.800029 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9624 10:56:16.800192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9625 10:56:16.800349 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9626 10:56:16.800507 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9627 10:56:16.802212 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9628 10:56:16.802574 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9629 10:56:16.802696 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9630 10:56:16.802793 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9631 10:56:16.802901 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9632 10:56:16.803013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9633 10:56:16.803129 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9634 10:56:16.803236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9635 10:56:16.803369 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9636 10:56:16.803477 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9637 10:56:16.803600 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9638 10:56:16.803722 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9639 10:56:16.803855 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9640 10:56:16.803972 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9641 10:56:16.804081 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9642 10:56:16.804187 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9643 10:56:16.804293 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9644 10:56:16.804409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9645 10:56:16.804528 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9646 10:56:16.804678 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9647 10:56:16.804857 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9648 10:56:16.804997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9649 10:56:16.805117 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9650 10:56:16.805211 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9651 10:56:16.805325 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9652 10:56:16.805433 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9653 10:56:16.805540 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9654 10:56:16.805659 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9655 10:56:16.805991 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9656 10:56:16.806114 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9657 10:56:16.806224 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9658 10:56:16.814459 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9659 10:56:16.814659 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9660 10:56:16.814773 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9661 10:56:16.814865 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9662 10:56:16.814972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9663 10:56:16.815060 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9664 10:56:16.815161 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9665 10:56:16.815265 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9666 10:56:16.815612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9667 10:56:16.815852 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9668 10:56:16.816091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9669 10:56:16.816314 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9670 10:56:16.816525 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9671 10:56:16.816784 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9672 10:56:16.816952 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9673 10:56:16.817088 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9674 10:56:16.817209 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9675 10:56:16.817326 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9676 10:56:16.817444 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9677 10:56:16.817571 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9678 10:56:16.817786 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9679 10:56:16.818083 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9680 10:56:16.818253 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9681 10:56:16.818383 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9682 10:56:16.818501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9683 10:56:16.818605 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9684 10:56:16.818693 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9685 10:56:16.818781 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9686 10:56:16.818867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9687 10:56:16.818956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9688 10:56:16.819044 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9689 10:56:16.819131 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9690 10:56:16.819217 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9691 10:56:16.819303 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9692 10:56:16.819389 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9693 10:56:16.822196 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9694 10:56:16.822528 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9695 10:56:16.822640 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9696 10:56:16.822750 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9697 10:56:16.822872 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9698 10:56:16.822989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9699 10:56:16.823079 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9700 10:56:16.823205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9701 10:56:16.823332 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9702 10:56:16.823459 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9703 10:56:16.823574 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9704 10:56:16.823702 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9705 10:56:16.823829 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9706 10:56:16.823943 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9707 10:56:16.824075 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9708 10:56:16.824184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9709 10:56:16.824303 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9710 10:56:16.824435 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9711 10:56:16.824557 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9712 10:56:16.824663 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9713 10:56:16.824762 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9714 10:56:16.824893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9715 10:56:16.825002 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9716 10:56:16.825109 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9717 10:56:16.825213 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9718 10:56:16.825306 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9719 10:56:16.825373 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9720 10:56:16.825462 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9721 10:56:16.825543 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9722 10:56:16.825607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9723 10:56:16.825680 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9724 10:56:16.825753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9725 10:56:16.826023 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9726 10:56:16.826104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9727 10:56:16.826166 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9728 10:56:16.826227 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9729 10:56:16.826288 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9730 10:56:16.826347 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9731 10:56:16.826407 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9732 10:56:16.830212 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9733 10:56:16.830531 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9734 10:56:16.842141 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9735 10:56:16.842594 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9736 10:56:16.842690 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9737 10:56:16.842777 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9738 10:56:16.842861 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9739 10:56:16.842931 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9740 10:56:16.843188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9741 10:56:16.843261 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9742 10:56:16.843326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9743 10:56:16.843402 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9744 10:56:16.843468 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9745 10:56:16.843545 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9746 10:56:16.843623 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9747 10:56:16.843875 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9748 10:56:16.843960 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9749 10:56:16.844052 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9750 10:56:16.844164 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9751 10:56:16.844300 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9752 10:56:16.844404 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9753 10:56:16.844678 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9754 10:56:16.844771 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9755 10:56:16.844853 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9756 10:56:16.844924 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9757 10:56:16.844998 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9758 10:56:16.845086 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9759 10:56:16.845356 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9760 10:56:16.845430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9761 10:56:16.845506 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9762 10:56:16.845581 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9763 10:56:16.845843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9764 10:56:16.845919 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9765 10:56:16.845996 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9766 10:56:16.850194 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9767 10:56:16.850491 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9768 10:56:16.850576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9769 10:56:16.850875 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9770 10:56:16.851049 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9771 10:56:16.851220 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9772 10:56:16.851352 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9773 10:56:16.851476 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9774 10:56:16.851597 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9775 10:56:16.851737 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9776 10:56:16.851853 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9777 10:56:16.851987 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9778 10:56:16.852120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9779 10:56:16.852277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9780 10:56:16.852409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9781 10:56:16.852530 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9782 10:56:16.852665 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9783 10:56:16.852824 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9784 10:56:16.852961 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9785 10:56:16.853092 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9786 10:56:16.853224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9787 10:56:16.853358 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9788 10:56:16.853518 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9789 10:56:16.853680 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9790 10:56:16.853819 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9791 10:56:16.853959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9792 10:56:16.854093 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9793 10:56:16.854224 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9794 10:56:16.854382 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9795 10:56:16.854519 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9796 10:56:16.854654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9797 10:56:16.854785 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9798 10:56:16.858429 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9799 10:56:16.858624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9800 10:56:16.858797 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9801 10:56:16.858941 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9802 10:56:16.859080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9803 10:56:16.859243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9804 10:56:16.859384 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9805 10:56:16.859522 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9806 10:56:16.859683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9807 10:56:16.859829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9808 10:56:16.859968 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9809 10:56:16.860131 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9810 10:56:16.860272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9811 10:56:16.860410 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9812 10:56:16.860547 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9813 10:56:16.860711 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9814 10:56:16.860853 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9815 10:56:16.860992 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9816 10:56:16.861129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9817 10:56:16.861268 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9818 10:56:16.861407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9819 10:56:16.861574 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9820 10:56:16.861744 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9821 10:56:16.861885 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9822 10:56:16.862022 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9823 10:56:16.862160 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9824 10:56:16.862298 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9825 10:56:16.862436 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9826 10:56:16.862573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9827 10:56:16.862737 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9828 10:56:16.862879 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9829 10:56:16.863018 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9830 10:56:16.863158 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9831 10:56:16.866200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9832 10:56:16.866608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9833 10:56:16.866777 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9834 10:56:16.866920 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9835 10:56:16.867060 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9836 10:56:16.867225 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9837 10:56:16.867366 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9838 10:56:16.867504 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9839 10:56:16.867646 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9840 10:56:16.867784 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9841 10:56:16.867925 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9842 10:56:16.868090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9843 10:56:16.868232 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9844 10:56:16.868371 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9845 10:56:16.868510 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9846 10:56:16.868648 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9847 10:56:16.868786 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9848 10:56:16.868924 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9849 10:56:16.869063 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9850 10:56:16.869231 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9851 10:56:16.869373 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9852 10:56:16.869512 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9853 10:56:16.869677 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9854 10:56:16.869821 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9855 10:56:16.869959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9856 10:56:16.870097 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9857 10:56:16.870236 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9858 10:56:16.870373 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9859 10:56:16.870512 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9860 10:56:16.870681 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9861 10:56:16.870822 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9862 10:56:16.870960 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9863 10:56:16.871097 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9864 10:56:16.871235 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9865 10:56:16.871372 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9866 10:56:16.871508 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9867 10:56:16.871644 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9868 10:56:16.871782 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9869 10:56:16.874571 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9870 10:56:16.874750 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9871 10:56:16.874895 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9872 10:56:16.875059 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9873 10:56:16.875202 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9874 10:56:16.875340 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9875 10:56:16.875481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9876 10:56:16.875621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9877 10:56:16.875785 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9878 10:56:16.875925 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9879 10:56:16.876063 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9880 10:56:16.876201 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9881 10:56:16.876366 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9882 10:56:16.876507 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9883 10:56:16.876647 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9884 10:56:16.876786 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9885 10:56:16.876925 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9886 10:56:16.877063 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9887 10:56:16.877230 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9888 10:56:16.877372 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9889 10:56:16.877509 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9890 10:56:16.877672 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9891 10:56:16.877814 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9892 10:56:16.877953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9893 10:56:16.878091 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9894 10:56:16.892989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9895 10:56:16.893217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9896 10:56:16.893526 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9897 10:56:16.893637 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9898 10:56:16.893747 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9899 10:56:16.893840 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9900 10:56:16.893951 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9901 10:56:16.894045 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9902 10:56:16.894136 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9903 10:56:16.894225 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9904 10:56:16.894333 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9905 10:56:16.894425 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9906 10:56:16.894523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9907 10:56:16.894628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9908 10:56:16.894742 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9909 10:56:16.894848 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9910 10:56:16.894953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9911 10:56:16.895251 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9912 10:56:16.895350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9913 10:56:16.895456 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9914 10:56:16.895562 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9915 10:56:16.895666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9916 10:56:16.895775 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9917 10:56:16.895883 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9918 10:56:16.896182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9919 10:56:16.896283 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9920 10:56:16.896389 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9921 10:56:16.896480 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9922 10:56:16.896582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9923 10:56:16.896877 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9924 10:56:16.896976 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9925 10:56:16.897082 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9926 10:56:16.897174 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9927 10:56:16.897469 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9928 10:56:16.897567 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9929 10:56:16.897664 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9930 10:56:16.897780 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9931 10:56:16.897873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9932 10:56:16.897977 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9933 10:56:16.898068 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9934 10:56:16.902250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9935 10:56:16.902552 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9936 10:56:16.902654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9937 10:56:16.902742 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9938 10:56:16.902844 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9939 10:56:16.902955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9940 10:56:16.903066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9941 10:56:16.903177 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9942 10:56:16.903272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9943 10:56:16.903380 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9944 10:56:16.903681 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9945 10:56:16.903784 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9946 10:56:16.903892 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9947 10:56:16.903985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9948 10:56:16.904091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9949 10:56:16.904184 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9950 10:56:16.904289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9951 10:56:16.904399 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9952 10:56:16.904705 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9953 10:56:16.904814 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9954 10:56:16.904906 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9955 10:56:16.905006 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9956 10:56:16.905100 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9957 10:56:16.905205 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9958 10:56:16.905314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9959 10:56:16.905403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9960 10:56:16.905507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9961 10:56:16.905598 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9962 10:56:16.905728 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9963 10:56:16.905843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9964 10:56:16.905948 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9965 10:56:16.906054 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9966 10:56:16.910580 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9967 10:56:16.911384 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9968 10:56:16.911546 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9969 10:56:16.911678 arm64_sve-ptrace_Set_SVE_VL_4608 pass
9970 10:56:16.912100 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
9971 10:56:16.912313 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
9972 10:56:16.912492 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
9973 10:56:16.912668 arm64_sve-ptrace_Set_SVE_VL_4624 pass
9974 10:56:16.912870 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
9975 10:56:16.913040 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
9976 10:56:16.913214 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
9977 10:56:16.913421 arm64_sve-ptrace_Set_SVE_VL_4640 pass
9978 10:56:16.913616 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
9979 10:56:16.913846 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
9980 10:56:16.914010 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
9981 10:56:16.914134 arm64_sve-ptrace_Set_SVE_VL_4656 pass
9982 10:56:16.914253 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
9983 10:56:16.914369 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
9984 10:56:16.914486 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
9985 10:56:16.914626 arm64_sve-ptrace_Set_SVE_VL_4672 pass
9986 10:56:16.914752 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
9987 10:56:16.918227 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
9988 10:56:16.918672 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
9989 10:56:16.918848 arm64_sve-ptrace_Set_SVE_VL_4688 pass
9990 10:56:16.918986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
9991 10:56:16.919132 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
9992 10:56:16.919298 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
9993 10:56:16.919450 arm64_sve-ptrace_Set_SVE_VL_4704 pass
9994 10:56:16.919590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
9995 10:56:16.919738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
9996 10:56:16.919898 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
9997 10:56:16.920027 arm64_sve-ptrace_Set_SVE_VL_4720 pass
9998 10:56:16.920142 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
9999 10:56:16.920273 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
10000 10:56:16.920407 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10001 10:56:16.920513 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10002 10:56:16.920647 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10003 10:56:16.920778 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10004 10:56:16.920880 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10005 10:56:16.920985 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10006 10:56:16.921102 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10007 10:56:16.921243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10008 10:56:16.921382 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10009 10:56:16.921490 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10010 10:56:16.921607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10011 10:56:16.921746 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10012 10:56:16.921857 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10013 10:56:16.922031 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10014 10:56:16.922167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10015 10:56:16.922272 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10016 10:56:16.922366 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10017 10:56:16.922460 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10018 10:56:16.926185 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10019 10:56:16.926492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10020 10:56:16.926600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10021 10:56:16.926701 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10022 10:56:16.926790 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10023 10:56:16.926889 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10024 10:56:16.926974 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10025 10:56:16.927074 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10026 10:56:16.927176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10027 10:56:16.927473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10028 10:56:16.927579 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10029 10:56:16.927682 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10030 10:56:16.927768 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10031 10:56:16.927880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10032 10:56:16.927985 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10033 10:56:16.928088 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10034 10:56:16.928193 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10035 10:56:16.928499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10036 10:56:16.928620 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10037 10:56:16.928726 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10038 10:56:16.928835 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10039 10:56:16.929133 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10040 10:56:16.929240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10041 10:56:16.929347 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10042 10:56:16.929453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10043 10:56:16.929746 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10044 10:56:16.929859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10045 10:56:16.929965 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10046 10:56:16.934162 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10047 10:56:16.934506 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10048 10:56:16.934668 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10049 10:56:16.934852 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10050 10:56:16.935013 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10051 10:56:16.935183 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10052 10:56:16.935310 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10053 10:56:16.935429 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10054 10:56:16.946417 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10055 10:56:16.946980 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10056 10:56:16.947148 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10057 10:56:16.947338 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10058 10:56:16.947518 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10059 10:56:16.947669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10060 10:56:16.947851 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10061 10:56:16.948039 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10062 10:56:16.948202 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10063 10:56:16.948419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10064 10:56:16.948616 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10065 10:56:16.948787 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10066 10:56:16.949017 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10067 10:56:16.949204 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10068 10:56:16.949378 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10069 10:56:16.949547 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10070 10:56:16.949729 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10071 10:56:16.949893 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10072 10:56:16.950028 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10073 10:56:16.950150 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10074 10:56:16.950268 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10075 10:56:16.950416 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10076 10:56:16.950542 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10077 10:56:16.950662 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10078 10:56:16.950781 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10079 10:56:16.950899 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10080 10:56:16.951017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10081 10:56:16.951136 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10082 10:56:16.954165 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10083 10:56:16.954581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10084 10:56:16.954753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10085 10:56:16.954906 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10086 10:56:16.955109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10087 10:56:16.955291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10088 10:56:16.955445 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10089 10:56:16.955660 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10090 10:56:16.955909 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10091 10:56:16.956096 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10092 10:56:16.956290 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10093 10:56:16.956467 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10094 10:56:16.956617 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10095 10:56:16.956755 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10096 10:56:16.956987 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10097 10:56:16.957186 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10098 10:56:16.957356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10099 10:56:16.957523 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10100 10:56:16.957701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10101 10:56:16.957868 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10102 10:56:16.958025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10103 10:56:16.958151 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10104 10:56:16.958302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10105 10:56:16.958428 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10106 10:56:16.958548 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10107 10:56:16.958669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10108 10:56:16.958789 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10109 10:56:16.958910 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10110 10:56:16.959028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10111 10:56:16.959147 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10112 10:56:16.959266 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10113 10:56:16.959385 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10114 10:56:16.962445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10115 10:56:16.962655 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10116 10:56:16.962865 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10117 10:56:16.963017 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10118 10:56:16.963179 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10119 10:56:16.963359 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10120 10:56:16.963576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10121 10:56:16.963758 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10122 10:56:16.963932 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10123 10:56:16.964146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10124 10:56:16.964379 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10125 10:56:16.964590 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10126 10:56:16.964833 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10127 10:56:16.965037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10128 10:56:16.965253 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10129 10:56:16.965441 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10130 10:56:16.965596 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10131 10:56:16.965801 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10132 10:56:16.966007 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10133 10:56:16.966208 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10134 10:56:16.966362 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10135 10:56:16.966507 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10136 10:56:16.966693 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10137 10:56:16.966832 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10138 10:56:16.966977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10139 10:56:16.967123 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10140 10:56:16.967268 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10141 10:56:16.967412 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10142 10:56:16.967556 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10143 10:56:16.967700 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10144 10:56:16.967845 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10145 10:56:16.968031 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10146 10:56:16.970229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10147 10:56:16.970664 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10148 10:56:16.970854 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10149 10:56:16.971027 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10150 10:56:16.971213 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10151 10:56:16.971370 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10152 10:56:16.971577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10153 10:56:16.971795 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10154 10:56:16.971998 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10155 10:56:16.972157 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10156 10:56:16.972309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10157 10:56:16.972454 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10158 10:56:16.972604 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10159 10:56:16.972745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10160 10:56:16.972910 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10161 10:56:16.973036 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10162 10:56:16.973170 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10163 10:56:16.973323 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10164 10:56:16.973489 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10165 10:56:16.973635 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10166 10:56:16.974090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10167 10:56:16.974160 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10168 10:56:16.974239 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10169 10:56:16.974305 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10170 10:56:16.974367 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10171 10:56:16.974427 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10172 10:56:16.974487 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10173 10:56:16.974548 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10174 10:56:16.974609 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10175 10:56:16.974670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10176 10:56:16.974731 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10177 10:56:16.978175 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10178 10:56:16.978523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10179 10:56:16.978636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10180 10:56:16.978791 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10181 10:56:16.978905 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10182 10:56:16.978999 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10183 10:56:16.979120 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10184 10:56:16.979210 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10185 10:56:16.979294 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10186 10:56:16.979402 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10187 10:56:16.979490 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10188 10:56:16.979611 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10189 10:56:16.979707 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10190 10:56:16.979804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10191 10:56:16.980182 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10192 10:56:16.980289 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10193 10:56:16.980388 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10194 10:56:16.980488 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10195 10:56:16.980587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10196 10:56:16.980701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10197 10:56:16.980783 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10198 10:56:16.980857 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10199 10:56:16.980923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10200 10:56:16.981016 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10201 10:56:16.981103 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10202 10:56:16.981184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10203 10:56:16.981268 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10204 10:56:16.981346 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10205 10:56:16.981427 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10206 10:56:16.981527 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10207 10:56:16.981611 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10208 10:56:16.981717 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10209 10:56:16.981804 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10210 10:56:16.981903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10211 10:56:16.981987 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10212 10:56:16.986158 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10213 10:56:16.986466 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10214 10:56:16.996909 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10215 10:56:16.997356 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10216 10:56:16.997503 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10217 10:56:16.997609 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10218 10:56:16.997783 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10219 10:56:16.997944 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10220 10:56:16.998052 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10221 10:56:16.998167 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10222 10:56:16.998315 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10223 10:56:16.998440 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10224 10:56:16.998581 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10225 10:56:16.998705 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10226 10:56:16.998825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10227 10:56:16.998939 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10228 10:56:16.999049 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10229 10:56:16.999159 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10230 10:56:16.999256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10231 10:56:16.999364 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10232 10:56:16.999498 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10233 10:56:16.999616 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10234 10:56:16.999727 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10235 10:56:16.999841 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10236 10:56:16.999986 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10237 10:56:17.000110 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10238 10:56:17.000229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10239 10:56:17.000345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10240 10:56:17.000490 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10241 10:56:17.000603 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10242 10:56:17.000728 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10243 10:56:17.000849 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10244 10:56:17.000997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10245 10:56:17.001123 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10246 10:56:17.001231 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10247 10:56:17.001337 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10248 10:56:17.002045 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10249 10:56:17.002158 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10250 10:56:17.002250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10251 10:56:17.002339 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10252 10:56:17.002625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10253 10:56:17.002724 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10254 10:56:17.002814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10255 10:56:17.002903 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10256 10:56:17.006368 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10257 10:56:17.006554 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10258 10:56:17.006717 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10259 10:56:17.006864 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10260 10:56:17.007027 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10261 10:56:17.007161 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10262 10:56:17.007292 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10263 10:56:17.007452 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10264 10:56:17.007562 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10265 10:56:17.007673 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10266 10:56:17.007808 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10267 10:56:17.007914 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10268 10:56:17.008047 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10269 10:56:17.008155 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10270 10:56:17.008288 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10271 10:56:17.008394 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10272 10:56:17.008527 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10273 10:56:17.008661 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10274 10:56:17.008789 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10275 10:56:17.008917 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10276 10:56:17.009059 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10277 10:56:17.009284 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10278 10:56:17.009453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10279 10:56:17.009598 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10280 10:56:17.009720 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10281 10:56:17.009880 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10282 10:56:17.010004 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10283 10:56:17.010121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10284 10:56:17.014215 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10285 10:56:17.014345 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10286 10:56:17.014643 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10287 10:56:17.014754 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10288 10:56:17.014847 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10289 10:56:17.014956 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10290 10:56:17.015045 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10291 10:56:17.015154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10292 10:56:17.015266 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10293 10:56:17.015364 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10294 10:56:17.015471 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10295 10:56:17.015585 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10296 10:56:17.015890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10297 10:56:17.016000 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10298 10:56:17.016109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10299 10:56:17.016223 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10300 10:56:17.016327 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10301 10:56:17.016543 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10302 10:56:17.016668 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10303 10:56:17.016783 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10304 10:56:17.016886 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10305 10:56:17.016990 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10306 10:56:17.017095 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10307 10:56:17.017393 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10308 10:56:17.017498 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10309 10:56:17.017600 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10310 10:56:17.017710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10311 10:56:17.017815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10312 10:56:17.018119 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10313 10:56:17.022256 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10314 10:56:17.022684 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10315 10:56:17.022793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10316 10:56:17.022885 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10317 10:56:17.022993 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10318 10:56:17.023096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10319 10:56:17.023426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10320 10:56:17.023524 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10321 10:56:17.023807 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10322 10:56:17.023908 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10323 10:56:17.024001 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10324 10:56:17.024103 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10325 10:56:17.024193 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10326 10:56:17.024296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10327 10:56:17.024404 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10328 10:56:17.024512 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10329 10:56:17.024619 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10330 10:56:17.025033 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10331 10:56:17.025131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10332 10:56:17.025409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10333 10:56:17.025507 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10334 10:56:17.025612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10335 10:56:17.025711 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10336 10:56:17.025819 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10337 10:56:17.025909 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10338 10:56:17.026015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10339 10:56:17.030281 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10340 10:56:17.030590 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10341 10:56:17.030698 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10342 10:56:17.030807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10343 10:56:17.030903 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10344 10:56:17.031018 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10345 10:56:17.031111 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10346 10:56:17.031221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10347 10:56:17.031330 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10348 10:56:17.031635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10349 10:56:17.031745 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10350 10:56:17.031855 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10351 10:56:17.031969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10352 10:56:17.032077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10353 10:56:17.032182 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10354 10:56:17.032479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10355 10:56:17.032579 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10356 10:56:17.032686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10357 10:56:17.032787 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10358 10:56:17.032884 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10359 10:56:17.032988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10360 10:56:17.033337 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10361 10:56:17.033541 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10362 10:56:17.033775 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10363 10:56:17.033948 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10364 10:56:17.034093 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10365 10:56:17.034213 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10366 10:56:17.034354 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10367 10:56:17.034475 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10368 10:56:17.038234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10369 10:56:17.038386 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10370 10:56:17.038720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10371 10:56:17.038880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10372 10:56:17.039007 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10373 10:56:17.039173 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10374 10:56:17.049379 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10375 10:56:17.049860 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10376 10:56:17.050051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10377 10:56:17.050197 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10378 10:56:17.050351 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10379 10:56:17.050488 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10380 10:56:17.050643 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10381 10:56:17.050799 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10382 10:56:17.050985 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10383 10:56:17.051146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10384 10:56:17.051272 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10385 10:56:17.051392 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10386 10:56:17.051536 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10387 10:56:17.051661 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10388 10:56:17.051782 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10389 10:56:17.051902 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10390 10:56:17.052047 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10391 10:56:17.052172 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10392 10:56:17.052292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10393 10:56:17.052411 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10394 10:56:17.052553 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10395 10:56:17.052676 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10396 10:56:17.052820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10397 10:56:17.053011 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10398 10:56:17.053198 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10399 10:56:17.053357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10400 10:56:17.053493 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10401 10:56:17.053632 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10402 10:56:17.053792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10403 10:56:17.053976 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10404 10:56:17.054118 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10405 10:56:17.054239 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10406 10:56:17.054356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10407 10:56:17.054494 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10408 10:56:17.058222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10409 10:56:17.058567 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10410 10:56:17.058696 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10411 10:56:17.058817 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10412 10:56:17.058957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10413 10:56:17.059081 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10414 10:56:17.059200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10415 10:56:17.059341 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10416 10:56:17.059463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10417 10:56:17.059602 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10418 10:56:17.059743 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10419 10:56:17.059889 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10420 10:56:17.060050 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10421 10:56:17.060301 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10422 10:56:17.060467 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10423 10:56:17.060649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10424 10:56:17.060790 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10425 10:56:17.061210 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10426 10:56:17.061337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10427 10:56:17.061477 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10428 10:56:17.061626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10429 10:56:17.061777 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10430 10:56:17.062091 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10431 10:56:17.062213 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10432 10:56:17.062306 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10433 10:56:17.062397 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10434 10:56:17.062486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10435 10:56:17.062574 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10436 10:56:17.066145 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10437 10:56:17.066482 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10438 10:56:17.066597 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10439 10:56:17.066710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10440 10:56:17.066827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10441 10:56:17.066945 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10442 10:56:17.067064 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10443 10:56:17.067198 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10444 10:56:17.067524 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10445 10:56:17.067676 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10446 10:56:17.067834 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10447 10:56:17.067979 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10448 10:56:17.068105 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10449 10:56:17.068205 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10450 10:56:17.068319 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10451 10:56:17.068439 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10452 10:56:17.068604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10453 10:56:17.068748 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10454 10:56:17.068931 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10455 10:56:17.069086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10456 10:56:17.069252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10457 10:56:17.069391 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10458 10:56:17.069561 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10459 10:56:17.069720 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10460 10:56:17.069874 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10461 10:56:17.070045 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10462 10:56:17.070169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10463 10:56:17.070281 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10464 10:56:17.070391 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10465 10:56:17.074179 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10466 10:56:17.074538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10467 10:56:17.074703 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10468 10:56:17.074859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10469 10:56:17.075006 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10470 10:56:17.075137 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10471 10:56:17.075270 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10472 10:56:17.075436 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10473 10:56:17.075583 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10474 10:56:17.075721 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10475 10:56:17.075833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10476 10:56:17.076003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10477 10:56:17.076152 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10478 10:56:17.076300 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10479 10:56:17.076432 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10480 10:56:17.076564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10481 10:56:17.076712 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10482 10:56:17.076814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10483 10:56:17.076912 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10484 10:56:17.077062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10485 10:56:17.077171 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10486 10:56:17.077288 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10487 10:56:17.077453 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10488 10:56:17.077585 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10489 10:56:17.078112 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10490 10:56:17.078224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10491 10:56:17.078316 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10492 10:56:17.078429 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10493 10:56:17.078524 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10494 10:56:17.078614 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10495 10:56:17.078702 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10496 10:56:17.082190 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10497 10:56:17.082563 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10498 10:56:17.082732 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10499 10:56:17.082893 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10500 10:56:17.083068 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10501 10:56:17.083195 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10502 10:56:17.083318 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10503 10:56:17.083449 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10504 10:56:17.083604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10505 10:56:17.083740 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10506 10:56:17.083902 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10507 10:56:17.084043 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10508 10:56:17.084175 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10509 10:56:17.084358 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10510 10:56:17.084494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10511 10:56:17.084619 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10512 10:56:17.084736 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10513 10:56:17.084880 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10514 10:56:17.085028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10515 10:56:17.085160 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10516 10:56:17.085314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10517 10:56:17.085441 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10518 10:56:17.085562 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10519 10:56:17.085951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10520 10:56:17.086101 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10521 10:56:17.086211 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10522 10:56:17.086302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10523 10:56:17.086414 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10524 10:56:17.086505 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10525 10:56:17.086595 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10526 10:56:17.086681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10527 10:56:17.086768 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10528 10:56:17.086855 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10529 10:56:17.086942 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10530 10:56:17.087030 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10531 10:56:17.087119 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10532 10:56:17.090228 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10533 10:56:17.090607 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10534 10:56:17.101048 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10535 10:56:17.101519 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10536 10:56:17.101660 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10537 10:56:17.101807 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10538 10:56:17.101932 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10539 10:56:17.102080 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10540 10:56:17.102220 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10541 10:56:17.102361 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10542 10:56:17.102542 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10543 10:56:17.102670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10544 10:56:17.102770 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10545 10:56:17.102885 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10546 10:56:17.102993 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10547 10:56:17.103107 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10548 10:56:17.103243 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10549 10:56:17.103365 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10550 10:56:17.103497 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10551 10:56:17.103610 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10552 10:56:17.103767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10553 10:56:17.103918 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10554 10:56:17.104051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10555 10:56:17.104195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10556 10:56:17.104330 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10557 10:56:17.104466 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10558 10:56:17.104569 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10559 10:56:17.104684 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10560 10:56:17.104801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10561 10:56:17.104929 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10562 10:56:17.105072 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10563 10:56:17.105255 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10564 10:56:17.105421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10565 10:56:17.105585 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10566 10:56:17.106272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10567 10:56:17.106399 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10568 10:56:17.106497 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10569 10:56:17.106587 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10570 10:56:17.106678 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10571 10:56:17.106766 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10572 10:56:17.107051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10573 10:56:17.107151 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10574 10:56:17.107241 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10575 10:56:17.110177 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10576 10:56:17.110522 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10577 10:56:17.110638 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10578 10:56:17.110731 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10579 10:56:17.110844 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10580 10:56:17.110955 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10581 10:56:17.111076 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10582 10:56:17.111257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10583 10:56:17.111391 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10584 10:56:17.111549 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10585 10:56:17.111659 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10586 10:56:17.111769 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10587 10:56:17.111903 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10588 10:56:17.112023 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10589 10:56:17.112172 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10590 10:56:17.112349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10591 10:56:17.112474 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10592 10:56:17.112630 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10593 10:56:17.112769 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10594 10:56:17.112904 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10595 10:56:17.113067 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10596 10:56:17.113205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10597 10:56:17.113314 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10598 10:56:17.113434 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10599 10:56:17.113538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10600 10:56:17.113666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10601 10:56:17.113769 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10602 10:56:17.113880 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10603 10:56:17.113996 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10604 10:56:17.118186 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10605 10:56:17.118566 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10606 10:56:17.118686 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10607 10:56:17.118800 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10608 10:56:17.118899 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10609 10:56:17.118996 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10610 10:56:17.119109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10611 10:56:17.119209 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10612 10:56:17.119321 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10613 10:56:17.119432 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10614 10:56:17.119546 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10615 10:56:17.119854 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10616 10:56:17.119957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10617 10:56:17.120071 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10618 10:56:17.120172 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10619 10:56:17.120281 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10620 10:56:17.120591 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10621 10:56:17.120694 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10622 10:56:17.120807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10623 10:56:17.120906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10624 10:56:17.121017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10625 10:56:17.121132 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10626 10:56:17.121246 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10627 10:56:17.121553 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10628 10:56:17.121668 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10629 10:56:17.121834 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10630 10:56:17.121950 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10631 10:56:17.122098 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10632 10:56:17.126187 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10633 10:56:17.126737 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10634 10:56:17.126928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10635 10:56:17.127080 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10636 10:56:17.127229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10637 10:56:17.127401 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10638 10:56:17.127549 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10639 10:56:17.127697 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10640 10:56:17.127873 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10641 10:56:17.128050 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10642 10:56:17.128254 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10643 10:56:17.128403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10644 10:56:17.128569 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10645 10:56:17.128750 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10646 10:56:17.128924 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10647 10:56:17.129102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10648 10:56:17.129318 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10649 10:56:17.129504 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10650 10:56:17.129692 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10651 10:56:17.129823 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10652 10:56:17.129972 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10653 10:56:17.130124 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10654 10:56:17.130254 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10655 10:56:17.130403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10656 10:56:17.130526 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10657 10:56:17.130641 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10658 10:56:17.130757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10659 10:56:17.130873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10660 10:56:17.134386 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10661 10:56:17.134859 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10662 10:56:17.135029 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10663 10:56:17.135162 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10664 10:56:17.135288 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10665 10:56:17.135439 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10666 10:56:17.135572 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10667 10:56:17.135697 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10668 10:56:17.135845 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10669 10:56:17.135974 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10670 10:56:17.136098 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10671 10:56:17.136244 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10672 10:56:17.136370 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10673 10:56:17.136904 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10674 10:56:17.137036 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10675 10:56:17.137161 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10676 10:56:17.137278 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10677 10:56:17.137395 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10678 10:56:17.137532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10679 10:56:17.137667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10680 10:56:17.137791 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10681 10:56:17.137919 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10682 10:56:17.138112 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10683 10:56:17.138253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10684 10:56:17.138374 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10685 10:56:17.142382 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10686 10:56:17.145801 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10687 10:56:17.146057 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10688 10:56:17.146212 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10689 10:56:17.146352 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10690 10:56:17.146480 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10691 10:56:17.146606 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10692 10:56:17.146732 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10693 10:56:17.146855 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10694 10:56:17.161202 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10695 10:56:17.161675 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10696 10:56:17.161779 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10697 10:56:17.161881 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10698 10:56:17.162039 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10699 10:56:17.162130 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10700 10:56:17.162233 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10701 10:56:17.162358 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10702 10:56:17.162457 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10703 10:56:17.162561 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10704 10:56:17.162854 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10705 10:56:17.162975 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10706 10:56:17.163090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10707 10:56:17.163218 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10708 10:56:17.163335 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10709 10:56:17.163464 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10710 10:56:17.163586 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10711 10:56:17.163706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10712 10:56:17.163960 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10713 10:56:17.164071 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10714 10:56:17.164182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10715 10:56:17.164493 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10716 10:56:17.164600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10717 10:56:17.164709 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10718 10:56:17.164818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10719 10:56:17.164926 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10720 10:56:17.165203 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10721 10:56:17.165507 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10722 10:56:17.165612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10723 10:56:17.165728 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10724 10:56:17.165819 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10725 10:56:17.165921 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10726 10:56:17.166011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10727 10:56:17.170378 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10728 10:56:17.170709 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10729 10:56:17.170809 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10730 10:56:17.170909 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10731 10:56:17.170996 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10732 10:56:17.171093 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10733 10:56:17.171194 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10734 10:56:17.171494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10735 10:56:17.171602 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10736 10:56:17.171722 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10737 10:56:17.171845 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10738 10:56:17.171966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10739 10:56:17.172074 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10740 10:56:17.172197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10741 10:56:17.172316 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10742 10:56:17.172619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10743 10:56:17.172717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10744 10:56:17.172814 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10745 10:56:17.172935 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10746 10:56:17.173227 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10747 10:56:17.173342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10748 10:56:17.173423 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10749 10:56:17.173514 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10750 10:56:17.173601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10751 10:56:17.173706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10752 10:56:17.173805 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10753 10:56:17.174048 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10754 10:56:17.174139 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10755 10:56:17.178607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10756 10:56:17.178735 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10757 10:56:17.178843 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10758 10:56:17.178946 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10759 10:56:17.179049 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10760 10:56:17.179173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10761 10:56:17.179287 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10762 10:56:17.179601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10763 10:56:17.179707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10764 10:56:17.179816 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10765 10:56:17.179906 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10766 10:56:17.180011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10767 10:56:17.180115 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10768 10:56:17.180440 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10769 10:56:17.180572 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10770 10:56:17.180683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10771 10:56:17.180767 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10772 10:56:17.180872 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10773 10:56:17.180972 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10774 10:56:17.181072 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10775 10:56:17.181170 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10776 10:56:17.181487 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10777 10:56:17.181602 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10778 10:56:17.181711 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10779 10:56:17.181830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10780 10:56:17.181931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10781 10:56:17.182063 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10782 10:56:17.182167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10783 10:56:17.186351 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10784 10:56:17.186676 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10785 10:56:17.186764 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10786 10:56:17.186865 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10787 10:56:17.186951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10788 10:56:17.187046 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10789 10:56:17.187130 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10790 10:56:17.187241 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10791 10:56:17.187545 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10792 10:56:17.187739 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10793 10:56:17.187833 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10794 10:56:17.187913 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10795 10:56:17.188007 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10796 10:56:17.188089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10797 10:56:17.188182 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10798 10:56:17.188471 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10799 10:56:17.188585 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10800 10:56:17.188678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10801 10:56:17.188778 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10802 10:56:17.188867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10803 10:56:17.188965 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10804 10:56:17.189065 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10805 10:56:17.189167 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10806 10:56:17.189272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10807 10:56:17.189594 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10808 10:56:17.189722 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10809 10:56:17.189850 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10810 10:56:17.189949 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10811 10:56:17.190073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10812 10:56:17.194377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10813 10:56:17.194727 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10814 10:56:17.194818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10815 10:56:17.194907 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10816 10:56:17.194995 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10817 10:56:17.195062 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10818 10:56:17.195296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10819 10:56:17.195389 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10820 10:56:17.195498 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10821 10:56:17.195783 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10822 10:56:17.195875 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10823 10:56:17.195971 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10824 10:56:17.196078 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10825 10:56:17.196185 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10826 10:56:17.196309 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10827 10:56:17.196426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10828 10:56:17.196544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10829 10:56:17.196646 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10830 10:56:17.196752 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10831 10:56:17.196853 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10832 10:56:17.197269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10833 10:56:17.197368 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10834 10:56:17.197474 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10835 10:56:17.197577 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10836 10:56:17.197678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10837 10:56:17.197761 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10838 10:56:17.197855 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10839 10:56:17.197944 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10840 10:56:17.198059 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10841 10:56:17.198168 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10842 10:56:17.202383 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10843 10:56:17.202739 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10844 10:56:17.202842 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10845 10:56:17.202960 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10846 10:56:17.203065 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10847 10:56:17.203183 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10848 10:56:17.203280 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10849 10:56:17.203402 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10850 10:56:17.203524 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10851 10:56:17.203645 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10852 10:56:17.203763 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10853 10:56:17.203849 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10854 10:56:17.222575 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10855 10:56:17.222817 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10856 10:56:17.222908 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10857 10:56:17.223209 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10858 10:56:17.223313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10859 10:56:17.223390 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10860 10:56:17.223468 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10861 10:56:17.223539 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10862 10:56:17.223625 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10863 10:56:17.223708 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10864 10:56:17.223779 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10865 10:56:17.223843 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10866 10:56:17.223921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10867 10:56:17.223987 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10868 10:56:17.224049 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10869 10:56:17.224125 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10870 10:56:17.224191 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10871 10:56:17.224266 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10872 10:56:17.224342 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10873 10:56:17.224420 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10874 10:56:17.224702 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10875 10:56:17.224781 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10876 10:56:17.224871 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10877 10:56:17.225127 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10878 10:56:17.225235 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10879 10:56:17.225334 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10880 10:56:17.225600 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10881 10:56:17.225706 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10882 10:56:17.225800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10883 10:56:17.225894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10884 10:56:17.225984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10885 10:56:17.230338 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10886 10:56:17.230651 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10887 10:56:17.230797 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10888 10:56:17.230911 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10889 10:56:17.231014 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10890 10:56:17.231316 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10891 10:56:17.231636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10892 10:56:17.231742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10893 10:56:17.231850 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10894 10:56:17.231956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10895 10:56:17.232250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10896 10:56:17.232549 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10897 10:56:17.232663 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10898 10:56:17.232770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10899 10:56:17.232874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10900 10:56:17.232978 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10901 10:56:17.233291 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10902 10:56:17.233609 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10903 10:56:17.233721 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10904 10:56:17.234041 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10905 10:56:17.234145 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10906 10:56:17.238248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10907 10:56:17.238571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10908 10:56:17.238692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10909 10:56:17.238800 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10910 10:56:17.239133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10911 10:56:17.239283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10912 10:56:17.239406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10913 10:56:17.239516 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10914 10:56:17.239885 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10915 10:56:17.240074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10916 10:56:17.240262 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10917 10:56:17.240402 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10918 10:56:17.240558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10919 10:56:17.240710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10920 10:56:17.240878 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10921 10:56:17.241043 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10922 10:56:17.241216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10923 10:56:17.241349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10924 10:56:17.241534 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10925 10:56:17.241724 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10926 10:56:17.241922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10927 10:56:17.242102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10928 10:56:17.246261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10929 10:56:17.246757 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10930 10:56:17.246946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10931 10:56:17.247088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10932 10:56:17.247244 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10933 10:56:17.247416 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10934 10:56:17.247623 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10935 10:56:17.247812 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10936 10:56:17.248018 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10937 10:56:17.248247 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10938 10:56:17.248491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10939 10:56:17.248696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10940 10:56:17.248913 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10941 10:56:17.249125 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10942 10:56:17.249325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10943 10:56:17.249505 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10944 10:56:17.249738 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10945 10:56:17.250015 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10946 10:56:17.250202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10947 10:56:17.250339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10948 10:56:17.250459 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10949 10:56:17.250575 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10950 10:56:17.250691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10951 10:56:17.254358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10952 10:56:17.254573 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10953 10:56:17.255050 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10954 10:56:17.255289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10955 10:56:17.255566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10956 10:56:17.255791 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10957 10:56:17.255955 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10958 10:56:17.256148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10959 10:56:17.256314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10960 10:56:17.256478 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10961 10:56:17.256638 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10962 10:56:17.256803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10963 10:56:17.256967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10964 10:56:17.257128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10965 10:56:17.257294 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10966 10:56:17.257458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10967 10:56:17.257676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10968 10:56:17.257850 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10969 10:56:17.258008 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
10970 10:56:17.258138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
10971 10:56:17.258263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
10972 10:56:17.258388 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
10973 10:56:17.258512 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
10974 10:56:17.258635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
10975 10:56:17.258760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
10976 10:56:17.258883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
10977 10:56:17.259007 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
10978 10:56:17.259130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
10979 10:56:17.259251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
10980 10:56:17.259423 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
10981 10:56:17.259614 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
10982 10:56:17.259789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
10983 10:56:17.259962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
10984 10:56:17.260137 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
10985 10:56:17.262401 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
10986 10:56:17.262604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
10987 10:56:17.262897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
10988 10:56:17.262990 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
10989 10:56:17.263075 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
10990 10:56:17.263157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
10991 10:56:17.277244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
10992 10:56:17.277357 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
10993 10:56:17.277446 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
10994 10:56:17.277530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
10995 10:56:17.277614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
10996 10:56:17.277711 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
10997 10:56:17.277795 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
10998 10:56:17.277879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
10999 10:56:17.277962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
11000 10:56:17.278044 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11001 10:56:17.278127 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11002 10:56:17.278210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11003 10:56:17.278293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11004 10:56:17.278375 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11005 10:56:17.278652 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11006 10:56:17.278741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11007 10:56:17.278825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11008 10:56:17.278908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11009 10:56:17.278991 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11010 10:56:17.279073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11011 10:56:17.279154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11012 10:56:17.279237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11013 10:56:17.279319 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11014 10:56:17.279401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11015 10:56:17.279483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11016 10:56:17.279584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11017 10:56:17.279670 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11018 10:56:17.279752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11019 10:56:17.279835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11020 10:56:17.279917 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11021 10:56:17.279999 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11022 10:56:17.280081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11023 10:56:17.280163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11024 10:56:17.280245 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11025 10:56:17.280345 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11026 10:56:17.280436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11027 10:56:17.280518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11028 10:56:17.280601 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11029 10:56:17.280683 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11030 10:56:17.280765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11031 10:56:17.280864 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11032 10:56:17.280949 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11033 10:56:17.281033 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11034 10:56:17.281130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11035 10:56:17.281215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11036 10:56:17.281297 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11037 10:56:17.281570 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11038 10:56:17.281664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11039 10:56:17.281749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11040 10:56:17.281834 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11041 10:56:17.281917 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11042 10:56:17.282016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11043 10:56:17.282101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11044 10:56:17.282184 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11045 10:56:17.282267 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11046 10:56:17.282349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11047 10:56:17.282445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11048 10:56:17.286551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11049 10:56:17.286665 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11050 10:56:17.286944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11051 10:56:17.287033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11052 10:56:17.287116 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11053 10:56:17.287199 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11054 10:56:17.287296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11055 10:56:17.287381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11056 10:56:17.287483 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11057 10:56:17.287567 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11058 10:56:17.287664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11059 10:56:17.287749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11060 10:56:17.287847 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11061 10:56:17.287931 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11062 10:56:17.288027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11063 10:56:17.288125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11064 10:56:17.288409 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11065 10:56:17.288503 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11066 10:56:17.288585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11067 10:56:17.288681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11068 10:56:17.288766 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11069 10:56:17.288862 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11070 10:56:17.288946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11071 10:56:17.289041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11072 10:56:17.289140 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11073 10:56:17.289237 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11074 10:56:17.289334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11075 10:56:17.289614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11076 10:56:17.289725 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11077 10:56:17.289809 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11078 10:56:17.289904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11079 10:56:17.290002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11080 10:56:17.294288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11081 10:56:17.294382 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11082 10:56:17.294709 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11083 10:56:17.294895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11084 10:56:17.295051 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11085 10:56:17.295242 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11086 10:56:17.295400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11087 10:56:17.295561 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11088 10:56:17.295752 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11089 10:56:17.295919 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11090 10:56:17.296067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11091 10:56:17.296252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11092 10:56:17.296399 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11093 10:56:17.296591 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11094 10:56:17.296753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11095 10:56:17.296948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11096 10:56:17.297112 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11097 10:56:17.297303 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11098 10:56:17.297462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11099 10:56:17.297619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11100 10:56:17.297818 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11101 10:56:17.297986 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11102 10:56:17.298135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11103 10:56:17.298261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11104 10:56:17.302225 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11105 10:56:17.302613 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11106 10:56:17.302725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11107 10:56:17.302861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11108 10:56:17.302986 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11109 10:56:17.303109 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11110 10:56:17.303243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11111 10:56:17.303390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11112 10:56:17.303812 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11113 10:56:17.304118 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11114 10:56:17.304225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11115 10:56:17.304329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11116 10:56:17.304416 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11117 10:56:17.304724 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11118 10:56:17.304824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11119 10:56:17.305185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11120 10:56:17.305301 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11121 10:56:17.305399 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11122 10:56:17.305697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11123 10:56:17.305807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11124 10:56:17.305900 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11125 10:56:17.306005 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11126 10:56:17.306299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11127 10:56:17.322703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11128 10:56:17.323046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11129 10:56:17.323157 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11130 10:56:17.323492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11131 10:56:17.323598 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11132 10:56:17.323704 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11133 10:56:17.324034 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11134 10:56:17.324196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11135 10:56:17.324307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11136 10:56:17.324641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11137 10:56:17.324748 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11138 10:56:17.324853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11139 10:56:17.325345 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11140 10:56:17.325452 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11141 10:56:17.325546 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11142 10:56:17.325850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11143 10:56:17.325957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11144 10:56:17.326048 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11145 10:56:17.326150 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11146 10:56:17.330286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11147 10:56:17.330651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11148 10:56:17.330775 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11149 10:56:17.330886 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11150 10:56:17.330977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11151 10:56:17.331088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11152 10:56:17.331389 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11153 10:56:17.331508 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11154 10:56:17.331816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11155 10:56:17.331938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11156 10:56:17.332046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11157 10:56:17.332382 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11158 10:56:17.332504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11159 10:56:17.332798 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11160 10:56:17.332936 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11161 10:56:17.333048 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11162 10:56:17.333151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11163 10:56:17.333476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11164 10:56:17.333631 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11165 10:56:17.333746 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11166 10:56:17.333860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11167 10:56:17.338283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11168 10:56:17.338646 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11169 10:56:17.338754 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11170 10:56:17.338853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11171 10:56:17.338952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11172 10:56:17.339259 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11173 10:56:17.339471 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11174 10:56:17.339765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11175 10:56:17.339870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11176 10:56:17.339969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11177 10:56:17.340053 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11178 10:56:17.340403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11179 10:56:17.340713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11180 10:56:17.340817 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11181 10:56:17.340914 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11182 10:56:17.341008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11183 10:56:17.341306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11184 10:56:17.341423 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11185 10:56:17.341738 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11186 10:56:17.341843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11187 10:56:17.341940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11188 10:56:17.346147 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11189 10:56:17.346463 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11190 10:56:17.346579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11191 10:56:17.346686 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11192 10:56:17.346791 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11193 10:56:17.347119 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11194 10:56:17.347240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11195 10:56:17.347348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11196 10:56:17.347716 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11197 10:56:17.347821 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11198 10:56:17.347924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11199 10:56:17.348260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11200 10:56:17.348382 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11201 10:56:17.348471 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11202 10:56:17.348572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11203 10:56:17.348884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11204 10:56:17.349003 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11205 10:56:17.349106 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11206 10:56:17.349426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11207 10:56:17.349556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11208 10:56:17.349738 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11209 10:56:17.349858 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11210 10:56:17.349975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11211 10:56:17.354161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11212 10:56:17.354500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11213 10:56:17.354605 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11214 10:56:17.354901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11215 10:56:17.355005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11216 10:56:17.355095 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11217 10:56:17.355452 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11218 10:56:17.355580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11219 10:56:17.355682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11220 10:56:17.355794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11221 10:56:17.355903 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11222 10:56:17.356232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11223 10:56:17.356539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11224 10:56:17.356639 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11225 10:56:17.356764 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11226 10:56:17.356897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11227 10:56:17.357031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11228 10:56:17.357173 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11229 10:56:17.357512 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11230 10:56:17.357610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11231 10:56:17.357735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11232 10:56:17.358041 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11233 10:56:17.358140 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11234 10:56:17.362385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11235 10:56:17.362735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11236 10:56:17.362856 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11237 10:56:17.362974 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11238 10:56:17.363099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11239 10:56:17.363451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11240 10:56:17.363579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11241 10:56:17.363707 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11242 10:56:17.363835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11243 10:56:17.363958 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11244 10:56:17.364076 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11245 10:56:17.364403 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11246 10:56:17.364511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11247 10:56:17.364613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11248 10:56:17.364703 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11249 10:56:17.364978 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11250 10:56:17.365102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11251 10:56:17.365223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11252 10:56:17.365529 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11253 10:56:17.365638 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11254 10:56:17.365754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11255 10:56:17.365857 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11256 10:56:17.365957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11257 10:56:17.370263 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11258 10:56:17.370741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11259 10:56:17.370903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11260 10:56:17.371028 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11261 10:56:17.381242 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11262 10:56:17.381701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11263 10:56:17.381816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11264 10:56:17.381913 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11265 10:56:17.382025 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11266 10:56:17.382122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11267 10:56:17.382232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11268 10:56:17.382526 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11269 10:56:17.382636 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11270 10:56:17.382735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11271 10:56:17.382827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11272 10:56:17.383096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11273 10:56:17.383346 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11274 10:56:17.383427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11275 10:56:17.383504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11276 10:56:17.383778 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11277 10:56:17.383857 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11278 10:56:17.384116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11279 10:56:17.384220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11280 10:56:17.384505 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11281 10:56:17.384630 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11282 10:56:17.384906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11283 10:56:17.385023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11284 10:56:17.385118 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11285 10:56:17.385409 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11286 10:56:17.385518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11287 10:56:17.385918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11288 10:56:17.386004 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11289 10:56:17.386083 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11290 10:56:17.390307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11291 10:56:17.390679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11292 10:56:17.390886 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11293 10:56:17.391150 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11294 10:56:17.391423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11295 10:56:17.391686 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11296 10:56:17.391938 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11297 10:56:17.392124 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11298 10:56:17.392274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11299 10:56:17.392403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11300 10:56:17.392554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11301 10:56:17.392690 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11302 10:56:17.393103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11303 10:56:17.393193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11304 10:56:17.393263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11305 10:56:17.393329 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11306 10:56:17.393394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11307 10:56:17.393462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11308 10:56:17.393684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11309 10:56:17.393757 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11310 10:56:17.393822 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11311 10:56:17.393898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11312 10:56:17.393983 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11313 10:56:17.398287 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11314 10:56:17.398673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11315 10:56:17.398844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11316 10:56:17.398992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11317 10:56:17.399190 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11318 10:56:17.399392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11319 10:56:17.399558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11320 10:56:17.399736 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11321 10:56:17.399887 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11322 10:56:17.400041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11323 10:56:17.400240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11324 10:56:17.400416 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11325 10:56:17.400587 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11326 10:56:17.400786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11327 10:56:17.400960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11328 10:56:17.401135 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11329 10:56:17.401308 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11330 10:56:17.401475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11331 10:56:17.401730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11332 10:56:17.401938 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11333 10:56:17.402126 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11334 10:56:17.402275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11335 10:56:17.402456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11336 10:56:17.402599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11337 10:56:17.406308 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11338 10:56:17.406765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11339 10:56:17.406963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11340 10:56:17.407216 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11341 10:56:17.407438 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11342 10:56:17.407630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11343 10:56:17.407829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11344 10:56:17.408033 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11345 10:56:17.408191 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11346 10:56:17.408361 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11347 10:56:17.408514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11348 10:56:17.408680 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11349 10:56:17.408880 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11350 10:56:17.409047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11351 10:56:17.409212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11352 10:56:17.409374 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11353 10:56:17.409537 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11354 10:56:17.409764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11355 10:56:17.409972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11356 10:56:17.410161 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11357 10:56:17.410314 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11358 10:56:17.410460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11359 10:56:17.410606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11360 10:56:17.410783 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11361 10:56:17.414286 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11362 10:56:17.414702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11363 10:56:17.414879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11364 10:56:17.415075 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11365 10:56:17.415236 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11366 10:56:17.415374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11367 10:56:17.415540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11368 10:56:17.415686 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11369 10:56:17.415844 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11370 10:56:17.416036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11371 10:56:17.416202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11372 10:56:17.416444 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11373 10:56:17.416636 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11374 10:56:17.416804 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11375 10:56:17.417000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11376 10:56:17.417174 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11377 10:56:17.417341 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11378 10:56:17.417537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11379 10:56:17.417727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11380 10:56:17.417922 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11381 10:56:17.418068 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11382 10:56:17.418188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11383 10:56:17.418305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11384 10:56:17.422307 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11385 10:56:17.422425 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11386 10:56:17.422781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11387 10:56:17.422980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11388 10:56:17.423236 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11389 10:56:17.423422 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11390 10:56:17.423591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11391 10:56:17.423782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11392 10:56:17.423917 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11393 10:56:17.424038 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11394 10:56:17.424179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11395 10:56:17.443715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11396 10:56:17.444229 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11397 10:56:17.444337 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11398 10:56:17.444426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11399 10:56:17.444514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11400 10:56:17.444618 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11401 10:56:17.444708 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11402 10:56:17.444810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11403 10:56:17.444915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11404 10:56:17.445218 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11405 10:56:17.445325 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11406 10:56:17.445431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11407 10:56:17.445591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11408 10:56:17.445832 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11409 10:56:17.446024 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11410 10:56:17.446381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11411 10:56:17.446603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11412 10:56:17.446754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11413 10:56:17.446922 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11414 10:56:17.447057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11415 10:56:17.447214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11416 10:56:17.447372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11417 10:56:17.447530 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11418 10:56:17.447664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11419 10:56:17.447829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11420 10:56:17.447993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11421 10:56:17.448145 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11422 10:56:17.448285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11423 10:56:17.448438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11424 10:56:17.448592 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11425 10:56:17.448725 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11426 10:56:17.448874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11427 10:56:17.449047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11428 10:56:17.449237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11429 10:56:17.449402 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11430 10:56:17.449570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11431 10:56:17.450161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11432 10:56:17.450303 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11433 10:56:17.450424 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11434 10:56:17.454464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11435 10:56:17.454915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11436 10:56:17.455079 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11437 10:56:17.455297 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11438 10:56:17.455443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11439 10:56:17.455587 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11440 10:56:17.455769 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11441 10:56:17.455955 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11442 10:56:17.456127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11443 10:56:17.456310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11444 10:56:17.456465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11445 10:56:17.456624 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11446 10:56:17.456798 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11447 10:56:17.456932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11448 10:56:17.457068 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11449 10:56:17.457245 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11450 10:56:17.457433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11451 10:56:17.457616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11452 10:56:17.458157 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11453 10:56:17.458323 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11454 10:56:17.458449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11455 10:56:17.458569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11456 10:56:17.458688 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11457 10:56:17.462254 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11458 10:56:17.462722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11459 10:56:17.462918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11460 10:56:17.463111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11461 10:56:17.463275 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11462 10:56:17.463435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11463 10:56:17.463634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11464 10:56:17.463783 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11465 10:56:17.463923 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11466 10:56:17.464092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11467 10:56:17.464242 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11468 10:56:17.464393 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11469 10:56:17.464563 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11470 10:56:17.464713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11471 10:56:17.464912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11472 10:56:17.465134 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11473 10:56:17.465303 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11474 10:56:17.465471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11475 10:56:17.465603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11476 10:56:17.466129 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11477 10:56:17.466276 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11478 10:56:17.466405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11479 10:56:17.466533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11480 10:56:17.466663 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11481 10:56:17.470532 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11482 10:56:17.470760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11483 10:56:17.470929 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11484 10:56:17.471117 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11485 10:56:17.471252 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11486 10:56:17.471403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11487 10:56:17.471536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11488 10:56:17.471768 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11489 10:56:17.471910 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11490 10:56:17.473815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11491 10:56:17.473942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11492 10:56:17.474046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11493 10:56:17.474134 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11494 10:56:17.474220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11495 10:56:17.474305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11496 10:56:17.474390 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11497 10:56:17.474475 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11498 10:56:17.474560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11499 10:56:17.474644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11500 10:56:17.474729 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11501 10:56:17.474864 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11502 10:56:17.475005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11503 10:56:17.475150 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11504 10:56:17.475514 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11505 10:56:17.478497 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11506 10:56:17.478683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11507 10:56:17.478883 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11508 10:56:17.479048 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11509 10:56:17.479208 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11510 10:56:17.479347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11511 10:56:17.479500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11512 10:56:17.479655 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11513 10:56:17.479811 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11514 10:56:17.479973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11515 10:56:17.480162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11516 10:56:17.480329 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11517 10:56:17.480520 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11518 10:56:17.480728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11519 10:56:17.480899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11520 10:56:17.481094 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11521 10:56:17.481260 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11522 10:56:17.481441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11523 10:56:17.481600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11524 10:56:17.481790 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11525 10:56:17.481936 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11526 10:56:17.482094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11527 10:56:17.482252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11528 10:56:17.490244 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11529 10:56:17.500074 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11530 10:56:17.500569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11531 10:56:17.500782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11532 10:56:17.500987 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11533 10:56:17.501196 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11534 10:56:17.501365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11535 10:56:17.501500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11536 10:56:17.501629 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11537 10:56:17.501975 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11538 10:56:17.502214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11539 10:56:17.502413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11540 10:56:17.502591 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11541 10:56:17.502753 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11542 10:56:17.502923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11543 10:56:17.503097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11544 10:56:17.503251 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11545 10:56:17.503383 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11546 10:56:17.503511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11547 10:56:17.503636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11548 10:56:17.503760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11549 10:56:17.503914 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11550 10:56:17.504041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11551 10:56:17.504162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11552 10:56:17.504284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11553 10:56:17.504417 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11554 10:56:17.504609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11555 10:56:17.504781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11556 10:56:17.504950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11557 10:56:17.505099 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11558 10:56:17.505317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11559 10:56:17.505570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11560 10:56:17.506245 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11561 10:56:17.506383 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11562 10:56:17.506718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11563 10:56:17.506847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11564 10:56:17.506967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11565 10:56:17.507085 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11566 10:56:17.507202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11567 10:56:17.507318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11568 10:56:17.507434 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11569 10:56:17.510196 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11570 10:56:17.510516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11571 10:56:17.510697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11572 10:56:17.510908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11573 10:56:17.511082 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11574 10:56:17.511237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11575 10:56:17.511435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11576 10:56:17.511631 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11577 10:56:17.511829 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11578 10:56:17.512022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11579 10:56:17.512206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11580 10:56:17.512383 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11581 10:56:17.512581 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11582 10:56:17.512734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11583 10:56:17.512883 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11584 10:56:17.513081 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11585 10:56:17.513236 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11586 10:56:17.513430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11587 10:56:17.513591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11588 10:56:17.513755 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11589 10:56:17.513905 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11590 10:56:17.514082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11591 10:56:17.514211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11592 10:56:17.514329 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11593 10:56:17.514448 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11594 10:56:17.514567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11595 10:56:17.514683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11596 10:56:17.518414 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11597 10:56:17.518600 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11598 10:56:17.518779 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11599 10:56:17.518939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11600 10:56:17.519177 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11601 10:56:17.519372 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11602 10:56:17.519573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11603 10:56:17.519814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11604 10:56:17.520002 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11605 10:56:17.520143 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11606 10:56:17.520264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11607 10:56:17.520407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11608 10:56:17.520530 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11609 10:56:17.520647 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11610 10:56:17.520763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11611 10:56:17.520904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11612 10:56:17.521026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11613 10:56:17.521142 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11614 10:56:17.521259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11615 10:56:17.521374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11616 10:56:17.521515 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11617 10:56:17.521637 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11618 10:56:17.521770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11619 10:56:17.521889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11620 10:56:17.522029 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11621 10:56:17.522150 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11622 10:56:17.522286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11623 10:56:17.526460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11624 10:56:17.526640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11625 10:56:17.526784 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11626 10:56:17.526941 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11627 10:56:17.527120 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11628 10:56:17.527271 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11629 10:56:17.527423 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11630 10:56:17.527550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11631 10:56:17.527695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11632 10:56:17.527823 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11633 10:56:17.527974 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11634 10:56:17.528102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11635 10:56:17.528485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11636 10:56:17.528677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11637 10:56:17.528842 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11638 10:56:17.529026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11639 10:56:17.529161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11640 10:56:17.529288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11641 10:56:17.529443 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11642 10:56:17.529590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11643 10:56:17.529732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11644 10:56:17.529897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11645 10:56:17.530052 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11646 10:56:17.530202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11647 10:56:17.534155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11648 10:56:17.534569 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11649 10:56:17.534739 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11650 10:56:17.534892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11651 10:56:17.535020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11652 10:56:17.535165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11653 10:56:17.535295 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11654 10:56:17.535442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11655 10:56:17.535591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11656 10:56:17.535740 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11657 10:56:17.535889 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11658 10:56:17.536036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11659 10:56:17.536185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11660 10:56:17.536337 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11661 10:56:17.536689 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11662 10:56:17.536838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11663 10:56:17.551242 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11664 10:56:17.551802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11665 10:56:17.552047 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11666 10:56:17.552272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11667 10:56:17.552462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11668 10:56:17.552705 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11669 10:56:17.552894 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11670 10:56:17.553085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11671 10:56:17.553300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11672 10:56:17.553495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11673 10:56:17.553678 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11674 10:56:17.553844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11675 10:56:17.554044 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11676 10:56:17.554200 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11677 10:56:17.554319 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11678 10:56:17.554434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11679 10:56:17.554547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11680 10:56:17.554660 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11681 10:56:17.554773 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11682 10:56:17.554885 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11683 10:56:17.554998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11684 10:56:17.555110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11685 10:56:17.555222 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11686 10:56:17.558259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11687 10:56:17.558704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11688 10:56:17.558898 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11689 10:56:17.559059 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11690 10:56:17.559292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11691 10:56:17.559560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11692 10:56:17.559755 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11693 10:56:17.559931 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11694 10:56:17.560099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11695 10:56:17.560261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11696 10:56:17.560426 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11697 10:56:17.560636 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11698 10:56:17.560808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11699 10:56:17.560971 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11700 10:56:17.561127 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11701 10:56:17.561298 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11702 10:56:17.561465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11703 10:56:17.561622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11704 10:56:17.561846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11705 10:56:17.562027 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11706 10:56:17.562202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11707 10:56:17.562327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11708 10:56:17.562443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11709 10:56:17.562558 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11710 10:56:17.562671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11711 10:56:17.562785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11712 10:56:17.562898 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11713 10:56:17.563014 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11714 10:56:17.563126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11715 10:56:17.563239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11716 10:56:17.563353 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11717 10:56:17.563465 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11718 10:56:17.566270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11719 10:56:17.566775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11720 10:56:17.566958 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11721 10:56:17.567122 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11722 10:56:17.567287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11723 10:56:17.567498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11724 10:56:17.567754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11725 10:56:17.567974 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11726 10:56:17.568182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11727 10:56:17.568392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11728 10:56:17.568620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11729 10:56:17.568846 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11730 10:56:17.569048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11731 10:56:17.569266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11732 10:56:17.569435 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11733 10:56:17.569598 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11734 10:56:17.569802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11735 10:56:17.570020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11736 10:56:17.570213 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11737 10:56:17.570342 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11738 10:56:17.570457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11739 10:56:17.570570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11740 10:56:17.570683 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11741 10:56:17.570795 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11742 10:56:17.570907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11743 10:56:17.571020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11744 10:56:17.571133 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11745 10:56:17.571274 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11746 10:56:17.571394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11747 10:56:17.571509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11748 10:56:17.571623 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11749 10:56:17.571736 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11750 10:56:17.571848 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11751 10:56:17.572169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11752 10:56:17.572293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11753 10:56:17.574456 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11754 10:56:17.574658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11755 10:56:17.574831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11756 10:56:17.575285 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11757 10:56:17.575485 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11758 10:56:17.575650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11759 10:56:17.575817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11760 10:56:17.575982 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11761 10:56:17.576144 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11762 10:56:17.576306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11763 10:56:17.576449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11764 10:56:17.576571 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11765 10:56:17.576689 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11766 10:56:17.576830 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11767 10:56:17.576952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11768 10:56:17.577071 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11769 10:56:17.577187 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11770 10:56:17.577304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11771 10:56:17.577474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11772 10:56:17.577629 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11773 10:56:17.577803 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11774 10:56:17.577954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11775 10:56:17.578127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11776 10:56:17.578253 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11777 10:56:17.578370 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11778 10:56:17.578486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11779 10:56:17.578602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11780 10:56:17.582231 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11781 10:56:17.582655 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11782 10:56:17.582761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11783 10:56:17.582855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11784 10:56:17.582963 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11785 10:56:17.583056 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11786 10:56:17.583163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11787 10:56:17.583272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11788 10:56:17.583562 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11789 10:56:17.583662 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11790 10:56:17.583767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11791 10:56:17.583876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11792 10:56:17.584176 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11793 10:56:17.584287 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11794 10:56:17.584581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11795 10:56:17.584675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11796 10:56:17.584771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11797 10:56:17.598753 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11798 10:56:17.599019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11799 10:56:17.599368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11800 10:56:17.599501 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11801 10:56:17.599622 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11802 10:56:17.599762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11803 10:56:17.599909 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11804 10:56:17.600033 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11805 10:56:17.600183 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11806 10:56:17.600307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11807 10:56:17.600446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11808 10:56:17.600569 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11809 10:56:17.600909 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11810 10:56:17.601042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11811 10:56:17.601181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11812 10:56:17.601322 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11813 10:56:17.601463 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11814 10:56:17.601605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11815 10:56:17.601975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11816 10:56:17.602105 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11817 10:56:17.606187 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11818 10:56:17.606546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11819 10:56:17.606694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11820 10:56:17.606833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11821 10:56:17.606972 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11822 10:56:17.607113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11823 10:56:17.607251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11824 10:56:17.607584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11825 10:56:17.607711 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11826 10:56:17.607847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11827 10:56:17.607986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11828 10:56:17.608126 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11829 10:56:17.608264 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11830 10:56:17.608402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11831 10:56:17.608812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11832 10:56:17.608972 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11833 10:56:17.609119 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11834 10:56:17.609240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11835 10:56:17.609620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11836 10:56:17.609859 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11837 10:56:17.610068 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11838 10:56:17.610211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11839 10:56:17.610429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11840 10:56:17.614481 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11841 10:56:17.614710 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11842 10:56:17.614923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11843 10:56:17.615089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11844 10:56:17.615252 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11845 10:56:17.615445 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11846 10:56:17.615614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11847 10:56:17.615777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11848 10:56:17.615969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11849 10:56:17.616135 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11850 10:56:17.616296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11851 10:56:17.616459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11852 10:56:17.616655 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11853 10:56:17.616821 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11854 10:56:17.616984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11855 10:56:17.617137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11856 10:56:17.617307 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11857 10:56:17.617515 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11858 10:56:17.617717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11859 10:56:17.617924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11860 10:56:17.618112 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11861 10:56:17.618296 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11862 10:56:17.618454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11863 10:56:17.618599 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11864 10:56:17.618778 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11865 10:56:17.618917 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11866 10:56:17.619062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11867 10:56:17.622213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11868 10:56:17.622657 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11869 10:56:17.622870 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11870 10:56:17.623070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11871 10:56:17.623281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11872 10:56:17.623449 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11873 10:56:17.623588 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11874 10:56:17.623749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11875 10:56:17.623945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11876 10:56:17.624117 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11877 10:56:17.624286 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11878 10:56:17.624479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11879 10:56:17.624658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11880 10:56:17.624912 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11881 10:56:17.625126 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11882 10:56:17.625289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11883 10:56:17.625441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11884 10:56:17.625570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11885 10:56:17.625731 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11886 10:56:17.625890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11887 10:56:17.626090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11888 10:56:17.626234 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11889 10:56:17.626353 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11890 10:56:17.626469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11891 10:56:17.626585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11892 10:56:17.626700 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11893 10:56:17.626814 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11894 10:56:17.626929 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11895 10:56:17.630238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11896 10:56:17.630667 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11897 10:56:17.630836 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11898 10:56:17.630994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11899 10:56:17.631192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11900 10:56:17.631359 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11901 10:56:17.631517 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11902 10:56:17.631678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11903 10:56:17.631868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11904 10:56:17.632028 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11905 10:56:17.632189 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11906 10:56:17.632349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11907 10:56:17.632509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11908 10:56:17.632715 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11909 10:56:17.632885 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11910 10:56:17.633088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11911 10:56:17.633269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11912 10:56:17.633435 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11913 10:56:17.633602 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11914 10:56:17.634268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11915 10:56:17.634408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11916 10:56:17.634530 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11917 10:56:17.634656 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11918 10:56:17.634824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11919 10:56:17.634956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11920 10:56:17.635075 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11921 10:56:17.635212 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11922 10:56:17.635341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11923 10:56:17.635462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11924 10:56:17.635579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11925 10:56:17.638302 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11926 10:56:17.638755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11927 10:56:17.638917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11928 10:56:17.639041 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11929 10:56:17.639161 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11930 10:56:17.639314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11931 10:56:17.647777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11932 10:56:17.648159 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11933 10:56:17.648263 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11934 10:56:17.648372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11935 10:56:17.648465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11936 10:56:17.648569 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11937 10:56:17.648673 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11938 10:56:17.648980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11939 10:56:17.649102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11940 10:56:17.649209 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11941 10:56:17.649313 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11942 10:56:17.649678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11943 10:56:17.649875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11944 10:56:17.650084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11945 10:56:17.650228 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11946 10:56:17.650421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11947 10:56:17.650619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11948 10:56:17.650817 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11949 10:56:17.650986 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11950 10:56:17.651182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11951 10:56:17.651350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11952 10:56:17.651513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11953 10:56:17.651678 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11954 10:56:17.651838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11955 10:56:17.652029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11956 10:56:17.652188 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11957 10:56:17.652346 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11958 10:56:17.652521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11959 10:56:17.652689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11960 10:56:17.652895 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11961 10:56:17.653063 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11962 10:56:17.653207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11963 10:56:17.653362 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11964 10:56:17.653528 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11965 10:56:17.653764 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11966 10:56:17.654070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11967 10:56:17.654215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11968 10:56:17.654337 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11969 10:56:17.654454 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
11970 10:56:17.654573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
11971 10:56:17.654691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
11972 10:56:17.654809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
11973 10:56:17.654926 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
11974 10:56:17.655259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
11975 10:56:17.658441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
11976 10:56:17.658650 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
11977 10:56:17.658899 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
11978 10:56:17.659063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
11979 10:56:17.659210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
11980 10:56:17.659386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
11981 10:56:17.659780 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
11982 10:56:17.659978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
11983 10:56:17.660141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
11984 10:56:17.660276 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
11985 10:56:17.660406 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
11986 10:56:17.660536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
11987 10:56:17.660661 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
11988 10:56:17.660814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
11989 10:56:17.660948 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
11990 10:56:17.661081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
11991 10:56:17.661213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
11992 10:56:17.661348 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
11993 10:56:17.661477 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
11994 10:56:17.661631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
11995 10:56:17.661784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
11996 10:56:17.661921 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
11997 10:56:17.662098 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
11998 10:56:17.662270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
11999 10:56:17.662407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
12000 10:56:17.662555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12001 10:56:17.662683 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12002 10:56:17.662803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12003 10:56:17.666225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12004 10:56:17.666557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12005 10:56:17.666661 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12006 10:56:17.666767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12007 10:56:17.666861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12008 10:56:17.666963 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12009 10:56:17.667065 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12010 10:56:17.667371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12011 10:56:17.667491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12012 10:56:17.667601 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12013 10:56:17.667709 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12014 10:56:17.668015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12015 10:56:17.668120 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12016 10:56:17.668228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12017 10:56:17.668332 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12018 10:56:17.668631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12019 10:56:17.668752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12020 10:56:17.669103 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12021 10:56:17.669282 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12022 10:56:17.669461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12023 10:56:17.669602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12024 10:56:17.669854 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12025 10:56:17.670056 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12026 10:56:17.670294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12027 10:56:17.670458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12028 10:56:17.678165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12029 10:56:17.678602 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12030 10:56:17.678757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12031 10:56:17.678937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12032 10:56:17.679101 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12033 10:56:17.679259 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12034 10:56:17.679476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12035 10:56:17.679644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12036 10:56:17.679809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12037 10:56:17.680010 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12038 10:56:17.680181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12039 10:56:17.680336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12040 10:56:17.680484 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12041 10:56:17.680613 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12042 10:56:17.680731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12043 10:56:17.680867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12044 10:56:17.681046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12045 10:56:17.681190 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12046 10:56:17.681344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12047 10:56:17.681504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12048 10:56:17.682005 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12049 10:56:17.682185 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12050 10:56:17.682368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12051 10:56:17.682507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12052 10:56:17.682650 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12053 10:56:17.682792 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12054 10:56:17.687219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12055 10:56:17.687449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12056 10:56:17.687601 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12057 10:56:17.687722 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12058 10:56:17.687840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12059 10:56:17.687956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12060 10:56:17.688072 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12061 10:56:17.688402 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12062 10:56:17.688532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12063 10:56:17.688652 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12064 10:56:17.688770 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12065 10:56:17.696078 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12066 10:56:17.696464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12067 10:56:17.696598 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12068 10:56:17.696740 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12069 10:56:17.696863 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12070 10:56:17.697001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12071 10:56:17.697142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12072 10:56:17.697308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12073 10:56:17.697504 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12074 10:56:17.697725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12075 10:56:17.697872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12076 10:56:17.698108 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12077 10:56:17.698260 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12078 10:56:17.698405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12079 10:56:17.698591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12080 10:56:17.698787 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12081 10:56:17.698941 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12082 10:56:17.699137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12083 10:56:17.699310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12084 10:56:17.699501 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12085 10:56:17.699670 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12086 10:56:17.699835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12087 10:56:17.700024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12088 10:56:17.700187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12089 10:56:17.700344 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12090 10:56:17.700524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12091 10:56:17.700684 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12092 10:56:17.700846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12093 10:56:17.700998 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12094 10:56:17.701186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12095 10:56:17.701358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12096 10:56:17.701512 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12097 10:56:17.702241 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12098 10:56:17.702395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12099 10:56:17.702517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12100 10:56:17.702637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12101 10:56:17.702754 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12102 10:56:17.702872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12103 10:56:17.702990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12104 10:56:17.703106 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12105 10:56:17.706254 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12106 10:56:17.706706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12107 10:56:17.706931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12108 10:56:17.707136 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12109 10:56:17.707315 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12110 10:56:17.707509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12111 10:56:17.707668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12112 10:56:17.707810 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12113 10:56:17.708006 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12114 10:56:17.708155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12115 10:56:17.708314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12116 10:56:17.708494 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12117 10:56:17.708666 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12118 10:56:17.708829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12119 10:56:17.709022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12120 10:56:17.709187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12121 10:56:17.709343 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12122 10:56:17.709503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12123 10:56:17.709961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12124 10:56:17.710130 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12125 10:56:17.710261 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12126 10:56:17.710391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12127 10:56:17.710518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12128 10:56:17.710648 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12129 10:56:17.710776 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12130 10:56:17.710901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12131 10:56:17.711028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12132 10:56:17.711149 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12133 10:56:17.711301 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12134 10:56:17.711434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12135 10:56:17.711554 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12136 10:56:17.711674 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12137 10:56:17.714215 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12138 10:56:17.714630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12139 10:56:17.714827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12140 10:56:17.714991 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12141 10:56:17.715198 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12142 10:56:17.715422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12143 10:56:17.715620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12144 10:56:17.715795 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12145 10:56:17.715923 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12146 10:56:17.716042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12147 10:56:17.716159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12148 10:56:17.716277 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12149 10:56:17.716742 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12150 10:56:17.716914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12151 10:56:17.717081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12152 10:56:17.717244 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12153 10:56:17.717400 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12154 10:56:17.717553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12155 10:56:17.717727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12156 10:56:17.717884 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12157 10:56:17.718046 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12158 10:56:17.718187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12159 10:56:17.718339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12160 10:56:17.718463 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12161 10:56:17.718580 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12162 10:56:17.718696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12163 10:56:17.718812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12164 10:56:17.718927 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12165 10:56:17.719044 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12166 10:56:17.719159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12167 10:56:17.719275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12168 10:56:17.719390 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12169 10:56:17.719507 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12170 10:56:17.726244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12171 10:56:17.726722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12172 10:56:17.726925 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12173 10:56:17.727099 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12174 10:56:17.727300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12175 10:56:17.727474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12176 10:56:17.727637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12177 10:56:17.727803 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12178 10:56:17.727966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12179 10:56:17.728158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12180 10:56:17.728335 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12181 10:56:17.728504 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12182 10:56:17.728669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12183 10:56:17.728820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12184 10:56:17.729000 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12185 10:56:17.729139 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12186 10:56:17.729306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12187 10:56:17.729471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12188 10:56:17.729629 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12189 10:56:17.730265 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12190 10:56:17.730401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12191 10:56:17.730553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12192 10:56:17.730681 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12193 10:56:17.730801 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12194 10:56:17.730920 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12195 10:56:17.731037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12196 10:56:17.731156 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12197 10:56:17.731276 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12198 10:56:17.731395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12199 10:56:17.743471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12200 10:56:17.743955 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12201 10:56:17.744068 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12202 10:56:17.744162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12203 10:56:17.744265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12204 10:56:17.744376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12205 10:56:17.744484 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12206 10:56:17.744773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12207 10:56:17.744881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12208 10:56:17.745172 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12209 10:56:17.745282 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12210 10:56:17.745374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12211 10:56:17.745459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12212 10:56:17.745556 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12213 10:56:17.745652 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12214 10:56:17.745743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12215 10:56:17.745976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12216 10:56:17.746090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12217 10:56:17.746184 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12218 10:56:17.746275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12219 10:56:17.746382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12220 10:56:17.746469 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12221 10:56:17.746573 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12222 10:56:17.746903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12223 10:56:17.747189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12224 10:56:17.747389 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12225 10:56:17.747553 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12226 10:56:17.747727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12227 10:56:17.747980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12228 10:56:17.748193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12229 10:56:17.748384 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12230 10:56:17.748546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12231 10:56:17.748691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12232 10:56:17.748851 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12233 10:56:17.749037 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12234 10:56:17.749194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12235 10:56:17.749341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12236 10:56:17.749496 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12237 10:56:17.749714 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12238 10:56:17.749889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12239 10:56:17.750054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12240 10:56:17.750180 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12241 10:56:17.750295 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12242 10:56:17.750410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12243 10:56:17.750525 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12244 10:56:17.750641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12245 10:56:17.750781 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12246 10:56:17.750903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12247 10:56:17.754511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12248 10:56:17.754722 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12249 10:56:17.754885 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12250 10:56:17.755299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12251 10:56:17.755487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12252 10:56:17.755650 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12253 10:56:17.755808 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12254 10:56:17.755999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12255 10:56:17.756185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12256 10:56:17.756381 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12257 10:56:17.756557 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12258 10:56:17.756721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12259 10:56:17.756888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12260 10:56:17.757091 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12261 10:56:17.757265 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12262 10:56:17.757489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12263 10:56:17.757731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12264 10:56:17.757918 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12265 10:56:17.758067 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12266 10:56:17.758220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12267 10:56:17.758344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12268 10:56:17.758465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12269 10:56:17.758582 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12270 10:56:17.758697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12271 10:56:17.758814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12272 10:56:17.758929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12273 10:56:17.759045 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12274 10:56:17.759161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12275 10:56:17.759276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12276 10:56:17.759397 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12277 10:56:17.766189 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12278 10:56:17.766634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12279 10:56:17.766745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12280 10:56:17.766836 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12281 10:56:17.766928 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12282 10:56:17.767029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12283 10:56:17.767119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12284 10:56:17.767222 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12285 10:56:17.767311 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12286 10:56:17.767413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12287 10:56:17.767659 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12288 10:56:17.767787 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12289 10:56:17.767895 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12290 10:56:17.767999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12291 10:56:17.768111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12292 10:56:17.768417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12293 10:56:17.768527 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12294 10:56:17.768636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12295 10:56:17.768940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12296 10:56:17.769061 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12297 10:56:17.769170 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12298 10:56:17.769271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12299 10:56:17.769583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12300 10:56:17.769713 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12301 10:56:17.769819 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12302 10:56:17.769925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12303 10:56:17.770031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12304 10:56:17.774424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12305 10:56:17.774542 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12306 10:56:17.774655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12307 10:56:17.774990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12308 10:56:17.775198 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12309 10:56:17.775387 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12310 10:56:17.775627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12311 10:56:17.775910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12312 10:56:17.776105 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12313 10:56:17.776269 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12314 10:56:17.776430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12315 10:56:17.776598 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12316 10:56:17.776772 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12317 10:56:17.776939 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12318 10:56:17.777129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12319 10:56:17.777297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12320 10:56:17.777462 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12321 10:56:17.777630 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12322 10:56:17.777851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12323 10:56:17.778048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12324 10:56:17.778230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12325 10:56:17.778375 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12326 10:56:17.778521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12327 10:56:17.778744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12328 10:56:17.778908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12329 10:56:17.779055 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12330 10:56:17.779202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12331 10:56:17.779347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12332 10:56:17.779491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12333 10:56:17.790682 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12334 10:56:17.790970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12335 10:56:17.791414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12336 10:56:17.791599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12337 10:56:17.791779 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12338 10:56:17.791951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12339 10:56:17.792149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12340 10:56:17.792324 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12341 10:56:17.792526 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12342 10:56:17.792702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12343 10:56:17.792866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12344 10:56:17.793023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12345 10:56:17.793179 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12346 10:56:17.793332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12347 10:56:17.793498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12348 10:56:17.793672 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12349 10:56:17.793837 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12350 10:56:17.794035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12351 10:56:17.794165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12352 10:56:17.794281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12353 10:56:17.794400 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12354 10:56:17.794516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12355 10:56:17.794631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12356 10:56:17.794747 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12357 10:56:17.794863 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12358 10:56:17.794980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12359 10:56:17.795095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12360 10:56:17.795211 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12361 10:56:17.795328 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12362 10:56:17.795443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12363 10:56:17.798250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12364 10:56:17.798678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12365 10:56:17.798785 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12366 10:56:17.798873 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12367 10:56:17.799155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12368 10:56:17.799358 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12369 10:56:17.799573 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12370 10:56:17.799850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12371 10:56:17.800060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12372 10:56:17.800282 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12373 10:56:17.800489 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12374 10:56:17.800724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12375 10:56:17.800931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12376 10:56:17.801107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12377 10:56:17.801253 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12378 10:56:17.801444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12379 10:56:17.801668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12380 10:56:17.801874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12381 10:56:17.802071 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12382 10:56:17.802206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12383 10:56:17.802354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12384 10:56:17.802478 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12385 10:56:17.802596 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12386 10:56:17.802712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12387 10:56:17.802828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12388 10:56:17.802943 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12389 10:56:17.803058 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12390 10:56:17.803172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12391 10:56:17.806262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12392 10:56:17.806707 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12393 10:56:17.806900 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12394 10:56:17.807068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12395 10:56:17.807263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12396 10:56:17.807462 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12397 10:56:17.807700 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12398 10:56:17.807896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12399 10:56:17.808080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12400 10:56:17.808292 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12401 10:56:17.808462 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12402 10:56:17.808618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12403 10:56:17.808778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12404 10:56:17.808937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12405 10:56:17.809066 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12406 10:56:17.809189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12407 10:56:17.809340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12408 10:56:17.809488 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12409 10:56:17.809751 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12410 10:56:17.809971 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12411 10:56:17.810163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12412 10:56:17.810350 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12413 10:56:17.810498 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12414 10:56:17.810643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12415 10:56:17.810788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12416 10:56:17.810931 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12417 10:56:17.811074 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12418 10:56:17.811219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12419 10:56:17.811397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12420 10:56:17.814241 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12421 10:56:17.814680 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12422 10:56:17.814890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12423 10:56:17.815105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12424 10:56:17.815314 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12425 10:56:17.815499 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12426 10:56:17.815666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12427 10:56:17.815826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12428 10:56:17.816019 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12429 10:56:17.816194 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12430 10:56:17.816366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12431 10:56:17.816502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12432 10:56:17.816658 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12433 10:56:17.816866 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12434 10:56:17.817035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12435 10:56:17.817208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12436 10:56:17.817365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12437 10:56:17.817522 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12438 10:56:17.817730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12439 10:56:17.817904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12440 10:56:17.818059 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12441 10:56:17.818177 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12442 10:56:17.818289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12443 10:56:17.818402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12444 10:56:17.818515 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12445 10:56:17.818628 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12446 10:56:17.818739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12447 10:56:17.818876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12448 10:56:17.818994 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12449 10:56:17.819108 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12450 10:56:17.822372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12451 10:56:17.822502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12452 10:56:17.822792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12453 10:56:17.822898 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12454 10:56:17.823005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12455 10:56:17.823329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12456 10:56:17.823523 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12457 10:56:17.823718 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12458 10:56:17.824144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12459 10:56:17.824314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12460 10:56:17.824441 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12461 10:56:17.824561 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12462 10:56:17.824720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12463 10:56:17.824846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12464 10:56:17.824963 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12465 10:56:17.825078 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12466 10:56:17.825217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12467 10:56:17.836862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12468 10:56:17.837252 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12469 10:56:17.837361 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12470 10:56:17.837452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12471 10:56:17.837541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12472 10:56:17.837654 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12473 10:56:17.837747 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12474 10:56:17.837836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12475 10:56:17.837930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12476 10:56:17.838035 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12477 10:56:17.838125 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12478 10:56:17.838212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12479 10:56:17.838552 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12480 10:56:17.838659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12481 10:56:17.838763 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12482 10:56:17.838853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12483 10:56:17.838942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12484 10:56:17.839046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12485 10:56:17.839134 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12486 10:56:17.839222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12487 10:56:17.839326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12488 10:56:17.839414 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12489 10:56:17.839519 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12490 10:56:17.839607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12491 10:56:17.839711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12492 10:56:17.840060 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12493 10:56:17.840165 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12494 10:56:17.840256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12495 10:56:17.840359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12496 10:56:17.840451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12497 10:56:17.840539 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12498 10:56:17.840627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12499 10:56:17.840731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12500 10:56:17.840822 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12501 10:56:17.840926 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12502 10:56:17.841016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12503 10:56:17.841105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12504 10:56:17.841209 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12505 10:56:17.841300 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12506 10:56:17.841405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12507 10:56:17.841501 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12508 10:56:17.841895 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12509 10:56:17.842002 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12510 10:56:17.842092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12511 10:56:17.842182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12512 10:56:17.842286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12513 10:56:17.842380 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12514 10:56:17.846364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12515 10:56:17.846628 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12516 10:56:17.847099 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12517 10:56:17.847286 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12518 10:56:17.847439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12519 10:56:17.847577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12520 10:56:17.847697 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12521 10:56:17.847814 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12522 10:56:17.847930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12523 10:56:17.848073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12524 10:56:17.848231 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12525 10:56:17.848378 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12526 10:56:17.848509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12527 10:56:17.848657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12528 10:56:17.848798 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12529 10:56:17.848943 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12530 10:56:17.849122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12531 10:56:17.850888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12532 10:56:17.851051 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12533 10:56:17.851175 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12534 10:56:17.851296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12535 10:56:17.851413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12536 10:56:17.851530 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12537 10:56:17.851647 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12538 10:56:17.851763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12539 10:56:17.851880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12540 10:56:17.851998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12541 10:56:17.852115 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12542 10:56:17.852232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12543 10:56:17.854253 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12544 10:56:17.854717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12545 10:56:17.854826 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12546 10:56:17.854914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12547 10:56:17.855086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12548 10:56:17.856081 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12549 10:56:17.856209 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12550 10:56:17.856306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12551 10:56:17.856393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12552 10:56:17.856477 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12553 10:56:17.856569 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12554 10:56:17.856656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12555 10:56:17.856742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12556 10:56:17.856826 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12557 10:56:17.856911 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12558 10:56:17.856993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12559 10:56:17.857077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12560 10:56:17.857184 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12561 10:56:17.857273 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12562 10:56:17.857360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12563 10:56:17.857446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12564 10:56:17.857531 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12565 10:56:17.857614 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12566 10:56:17.857710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12567 10:56:17.857798 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12568 10:56:17.857905 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12569 10:56:17.857995 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12570 10:56:17.858082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12571 10:56:17.858167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12572 10:56:17.858254 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12573 10:56:17.858345 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12574 10:56:17.858449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12575 10:56:17.862155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12576 10:56:17.862491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12577 10:56:17.862647 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12578 10:56:17.862771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12579 10:56:17.863098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12580 10:56:17.863205 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12581 10:56:17.863294 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12582 10:56:17.863383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12583 10:56:17.863473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12584 10:56:17.863588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12585 10:56:17.863680 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12586 10:56:17.863768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12587 10:56:17.863874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12588 10:56:17.863965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12589 10:56:17.864069 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12590 10:56:17.864173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12591 10:56:17.864475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12592 10:56:17.864587 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12593 10:56:17.864676 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12594 10:56:17.864780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12595 10:56:17.864868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12596 10:56:17.864970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12597 10:56:17.865313 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12598 10:56:17.865417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12599 10:56:17.865510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12600 10:56:17.865620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12601 10:56:17.882061 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12602 10:56:17.882264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12603 10:56:17.882578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12604 10:56:17.882686 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12605 10:56:17.882779 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12606 10:56:17.882870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12607 10:56:17.882974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12608 10:56:17.883068 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12609 10:56:17.883159 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12610 10:56:17.883266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12611 10:56:17.883360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12612 10:56:17.883465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12613 10:56:17.883555 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12614 10:56:17.883658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12615 10:56:17.883747 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12616 10:56:17.883852 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12617 10:56:17.883943 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12618 10:56:17.884047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12619 10:56:17.884139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12620 10:56:17.884243 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12621 10:56:17.889795 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12622 10:56:17.889898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12623 10:56:17.889988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12624 10:56:17.890078 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12625 10:56:17.890164 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12626 10:56:17.890250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12627 10:56:17.890333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12628 10:56:17.890414 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12629 10:56:17.890494 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12630 10:56:17.890581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12631 10:56:17.890669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12632 10:56:17.890755 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12633 10:56:17.890841 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12634 10:56:17.895987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12635 10:56:17.896119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12636 10:56:17.896211 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12637 10:56:17.896296 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12638 10:56:17.896378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12639 10:56:17.896461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12640 10:56:17.896547 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12641 10:56:17.896631 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12642 10:56:17.896716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12643 10:56:17.896800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12644 10:56:17.896886 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12645 10:56:17.896971 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12646 10:56:17.897058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12647 10:56:17.897141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12648 10:56:17.897224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12649 10:56:17.897307 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12650 10:56:17.897392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12651 10:56:17.897476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12652 10:56:17.897563 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12653 10:56:17.897653 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12654 10:56:17.897741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12655 10:56:17.897825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12656 10:56:17.897909 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12657 10:56:17.897993 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12658 10:56:17.898078 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12659 10:56:17.898164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12660 10:56:17.898248 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12661 10:56:17.898334 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12662 10:56:17.898418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12663 10:56:17.898500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12664 10:56:17.898587 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12665 10:56:17.898672 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12666 10:56:17.899016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12667 10:56:17.899166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12668 10:56:17.899287 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12669 10:56:17.899373 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12670 10:56:17.899459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12671 10:56:17.899547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12672 10:56:17.899640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12673 10:56:17.899729 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12674 10:56:17.899815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12675 10:56:17.899902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12676 10:56:17.899990 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12677 10:56:17.900075 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12678 10:56:17.900163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12679 10:56:17.900251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12680 10:56:17.900340 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12681 10:56:17.900427 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12682 10:56:17.900513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12683 10:56:17.900626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12684 10:56:17.900718 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12685 10:56:17.900806 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12686 10:56:17.900889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12687 10:56:17.900976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12688 10:56:17.901060 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12689 10:56:17.901145 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12690 10:56:17.901231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12691 10:56:17.901318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12692 10:56:17.901405 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12693 10:56:17.901494 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12694 10:56:17.901583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12695 10:56:17.901702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12696 10:56:17.901792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12697 10:56:17.901881 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12698 10:56:17.902171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12699 10:56:17.902275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12700 10:56:17.902363 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12701 10:56:17.902448 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12702 10:56:17.902537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12703 10:56:17.902630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12704 10:56:17.902717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12705 10:56:17.906214 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12706 10:56:17.906725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12707 10:56:17.906921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12708 10:56:17.907085 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12709 10:56:17.907242 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12710 10:56:17.907431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12711 10:56:17.907606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12712 10:56:17.907825 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12713 10:56:17.908055 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12714 10:56:17.908249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12715 10:56:17.908426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12716 10:56:17.908586 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12717 10:56:17.908782 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12718 10:56:17.908950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12719 10:56:17.909117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12720 10:56:17.909250 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12721 10:56:17.909367 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12722 10:56:17.909483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12723 10:56:17.909609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12724 10:56:17.909765 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12725 10:56:17.909885 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12726 10:56:17.910010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12727 10:56:17.910126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12728 10:56:17.910244 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12729 10:56:17.910390 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12730 10:56:17.910512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12731 10:56:17.910630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12732 10:56:17.910745 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12733 10:56:17.910861 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12734 10:56:17.910977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12735 10:56:17.926687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12736 10:56:17.927027 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12737 10:56:17.927422 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12738 10:56:17.927530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12739 10:56:17.927620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12740 10:56:17.927706 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12741 10:56:17.927792 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12742 10:56:17.927876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12743 10:56:17.927960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12744 10:56:17.928060 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12745 10:56:17.928146 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12746 10:56:17.928228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12747 10:56:17.928312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12748 10:56:17.928412 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12749 10:56:17.928499 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12750 10:56:17.928596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12751 10:56:17.928704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12752 10:56:17.929001 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12753 10:56:17.929103 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12754 10:56:17.929203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12755 10:56:17.929491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12756 10:56:17.929593 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12757 10:56:17.929706 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12758 10:56:17.929806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12759 10:56:17.930118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12760 10:56:17.930235 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12761 10:56:17.934222 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12762 10:56:17.934324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12763 10:56:17.934640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12764 10:56:17.934837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12765 10:56:17.934979 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12766 10:56:17.935109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12767 10:56:17.935265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12768 10:56:17.935427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12769 10:56:17.935608 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12770 10:56:17.935753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12771 10:56:17.935911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12772 10:56:17.936048 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12773 10:56:17.936175 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12774 10:56:17.936301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12775 10:56:17.936428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12776 10:56:17.936583 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12777 10:56:17.936717 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12778 10:56:17.936845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12779 10:56:17.936970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12780 10:56:17.937092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12781 10:56:17.937225 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12782 10:56:17.937348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12783 10:56:17.937505 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12784 10:56:17.937640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12785 10:56:17.937818 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12786 10:56:17.937944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12787 10:56:17.938071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12788 10:56:17.938196 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12789 10:56:17.938312 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12790 10:56:17.938431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12791 10:56:17.938573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12792 10:56:17.938696 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12793 10:56:17.938814 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12794 10:56:17.939144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12795 10:56:17.939272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12796 10:56:17.942278 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12797 10:56:17.942919 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12798 10:56:17.943122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12799 10:56:17.943296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12800 10:56:17.943465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12801 10:56:17.943624 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12802 10:56:17.943787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12803 10:56:17.943988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12804 10:56:17.944162 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12805 10:56:17.944328 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12806 10:56:17.944490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12807 10:56:17.944651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12808 10:56:17.944814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12809 10:56:17.944978 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12810 10:56:17.945138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12811 10:56:17.945297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12812 10:56:17.945505 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12813 10:56:17.945697 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12814 10:56:17.945870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12815 10:56:17.946069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12816 10:56:17.946237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12817 10:56:17.946364 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12818 10:56:17.946484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12819 10:56:17.946601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12820 10:56:17.946721 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12821 10:56:17.946841 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12822 10:56:17.946958 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12823 10:56:17.947075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12824 10:56:17.947191 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12825 10:56:17.947308 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12826 10:56:17.947424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12827 10:56:17.947540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12828 10:56:17.947687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12829 10:56:17.948022 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12830 10:56:17.948152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12831 10:56:17.948270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12832 10:56:17.948386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12833 10:56:17.948502 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12834 10:56:17.948617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12835 10:56:17.950481 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12836 10:56:17.950689 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12837 10:56:17.950920 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12838 10:56:17.951102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12839 10:56:17.951280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12840 10:56:17.951448 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12841 10:56:17.951654 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12842 10:56:17.951827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12843 10:56:17.951995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12844 10:56:17.952153 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12845 10:56:17.952308 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12846 10:56:17.952472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12847 10:56:17.952666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12848 10:56:17.952844 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12849 10:56:17.953010 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12850 10:56:17.953183 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12851 10:56:17.953347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12852 10:56:17.953511 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12853 10:56:17.953693 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12854 10:56:17.953864 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12855 10:56:17.954142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12856 10:56:17.954350 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12857 10:56:17.954531 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12858 10:56:17.954692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12859 10:56:17.954841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12860 10:56:17.954986 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12861 10:56:17.955138 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12862 10:56:17.955265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12863 10:56:17.955391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12864 10:56:17.955524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12865 10:56:17.958214 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12866 10:56:17.958531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12867 10:56:17.958636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12868 10:56:17.958731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12869 10:56:17.975637 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12870 10:56:17.975920 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12871 10:56:17.976263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12872 10:56:17.976370 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12873 10:56:17.976461 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12874 10:56:17.976550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12875 10:56:17.976655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12876 10:56:17.976746 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12877 10:56:17.976832 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12878 10:56:17.976918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12879 10:56:17.977021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12880 10:56:17.977110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12881 10:56:17.977209 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12882 10:56:17.977509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12883 10:56:17.977613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12884 10:56:17.977725 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12885 10:56:17.977829 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12886 10:56:17.978135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12887 10:56:17.978422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12888 10:56:17.978514 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12889 10:56:17.978616 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12890 10:56:17.978717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12891 10:56:17.979024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12892 10:56:17.979128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12893 10:56:17.979229 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12894 10:56:17.979330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12895 10:56:17.979628 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12896 10:56:17.979722 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12897 10:56:17.979824 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12898 10:56:17.980100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12899 10:56:17.980205 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12900 10:56:17.980308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12901 10:56:17.980408 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12902 10:56:17.980692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12903 10:56:17.980799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12904 10:56:17.981084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12905 10:56:17.981174 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12906 10:56:17.981275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12907 10:56:17.981373 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12908 10:56:17.981474 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12909 10:56:17.981763 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12910 10:56:17.981854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12911 10:56:17.981953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12912 10:56:17.986161 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12913 10:56:17.986450 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12914 10:56:17.986542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12915 10:56:17.986643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12916 10:56:17.986744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12917 10:56:17.987031 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12918 10:56:17.987122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12919 10:56:17.987223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12920 10:56:17.987326 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12921 10:56:17.987426 arm64_sve-ptrace pass
12922 10:56:17.987534 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12923 10:56:17.987820 arm64_sve-probe-vls_All_vector_lengths_valid pass
12924 10:56:17.987928 arm64_sve-probe-vls pass
12925 10:56:17.988016 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12926 10:56:17.988100 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12927 10:56:17.988200 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12928 10:56:17.988301 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12929 10:56:17.988401 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12930 10:56:17.988501 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12931 10:56:17.988609 arm64_vec-syscfg_SVE_vector_length_used_default pass
12932 10:56:17.988909 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12933 10:56:17.989000 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12934 10:56:17.989100 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12935 10:56:17.989185 arm64_vec-syscfg_SME_default_vector_length_32 pass
12936 10:56:17.989285 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12937 10:56:17.989754 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12938 10:56:17.990107 arm64_vec-syscfg_SME_current_VL_is_32 pass
12939 10:56:17.990244 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12940 10:56:17.990581 arm64_vec-syscfg_SME_prctl_set_min_max pass
12941 10:56:17.990711 arm64_vec-syscfg_SME_vector_length_used_default pass
12942 10:56:17.990833 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12943 10:56:17.994219 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12944 10:56:17.994687 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12945 10:56:17.994891 arm64_vec-syscfg pass
12946 10:56:17.995077 arm64_za-fork_fork_test pass
12947 10:56:17.995293 arm64_za-fork pass
12948 10:56:17.995481 arm64_za-ptrace_Set_VL_16 pass
12949 10:56:17.995654 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12950 10:56:17.995822 arm64_za-ptrace_Data_match_for_VL_16 pass
12951 10:56:17.996042 arm64_za-ptrace_Set_VL_32 pass
12952 10:56:17.996247 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12953 10:56:17.996471 arm64_za-ptrace_Data_match_for_VL_32 pass
12954 10:56:17.996696 arm64_za-ptrace_Set_VL_48 pass
12955 10:56:17.996885 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12956 10:56:17.997090 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12957 10:56:17.997286 arm64_za-ptrace_Set_VL_64 pass
12958 10:56:17.997493 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12959 10:56:17.997729 arm64_za-ptrace_Data_match_for_VL_64 pass
12960 10:56:17.997956 arm64_za-ptrace_Set_VL_80 pass
12961 10:56:17.998141 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12962 10:56:17.998273 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12963 10:56:17.998391 arm64_za-ptrace_Set_VL_96 pass
12964 10:56:17.998508 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12965 10:56:17.998622 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12966 10:56:17.998737 arm64_za-ptrace_Set_VL_112 pass
12967 10:56:17.998853 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12968 10:56:17.998976 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12969 10:56:17.999119 arm64_za-ptrace_Set_VL_128 pass
12970 10:56:17.999272 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
12971 10:56:17.999396 arm64_za-ptrace_Data_match_for_VL_128 pass
12972 10:56:17.999513 arm64_za-ptrace_Set_VL_144 pass
12973 10:56:17.999627 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
12974 10:56:17.999744 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
12975 10:56:17.999862 arm64_za-ptrace_Set_VL_160 pass
12976 10:56:17.999977 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
12977 10:56:18.000092 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
12978 10:56:18.000207 arm64_za-ptrace_Set_VL_176 pass
12979 10:56:18.000323 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
12980 10:56:18.000437 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
12981 10:56:18.000553 arm64_za-ptrace_Set_VL_192 pass
12982 10:56:18.000667 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
12983 10:56:18.000784 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
12984 10:56:18.000899 arm64_za-ptrace_Set_VL_208 pass
12985 10:56:18.001015 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
12986 10:56:18.001130 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
12987 10:56:18.001246 arm64_za-ptrace_Set_VL_224 pass
12988 10:56:18.001361 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
12989 10:56:18.001476 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
12990 10:56:18.001592 arm64_za-ptrace_Set_VL_240 pass
12991 10:56:18.001804 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
12992 10:56:18.002253 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
12993 10:56:18.002453 arm64_za-ptrace_Set_VL_256 pass
12994 10:56:18.002640 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
12995 10:56:18.002798 arm64_za-ptrace_Data_match_for_VL_256 pass
12996 10:56:18.002944 arm64_za-ptrace_Set_VL_272 pass
12997 10:56:18.003088 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
12998 10:56:18.006194 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
12999 10:56:18.006398 arm64_za-ptrace_Set_VL_288 pass
13000 10:56:18.006803 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13001 10:56:18.006993 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13002 10:56:18.007155 arm64_za-ptrace_Set_VL_304 pass
13003 10:56:18.007310 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13004 10:56:18.007467 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13005 10:56:18.007623 arm64_za-ptrace_Set_VL_320 pass
13006 10:56:18.007776 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13007 10:56:18.007931 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13008 10:56:18.008340 arm64_za-ptrace_Set_VL_336 pass
13009 10:56:18.008621 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13010 10:56:18.008834 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13011 10:56:18.009015 arm64_za-ptrace_Set_VL_352 pass
13012 10:56:18.009200 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13013 10:56:18.009336 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13014 10:56:18.009455 arm64_za-ptrace_Set_VL_368 pass
13015 10:56:18.009583 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13016 10:56:18.009722 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13017 10:56:18.009839 arm64_za-ptrace_Set_VL_384 pass
13018 10:56:18.009954 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13019 10:56:18.010069 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13020 10:56:18.010184 arm64_za-ptrace_Set_VL_400 pass
13021 10:56:18.010298 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13022 10:56:18.010413 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13023 10:56:18.010527 arm64_za-ptrace_Set_VL_416 pass
13024 10:56:18.010641 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13025 10:56:18.010755 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13026 10:56:18.010869 arm64_za-ptrace_Set_VL_432 pass
13027 10:56:18.010982 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13028 10:56:18.011126 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13029 10:56:18.011249 arm64_za-ptrace_Set_VL_448 pass
13030 10:56:18.011366 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13031 10:56:18.011482 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13032 10:56:18.011598 arm64_za-ptrace_Set_VL_464 pass
13033 10:56:18.011714 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13034 10:56:18.011832 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13035 10:56:18.011946 arm64_za-ptrace_Set_VL_480 pass
13036 10:56:18.012061 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13037 10:56:18.012176 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13038 10:56:18.012290 arm64_za-ptrace_Set_VL_496 pass
13039 10:56:18.012404 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13040 10:56:18.026525 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13041 10:56:18.026807 arm64_za-ptrace_Set_VL_512 pass
13042 10:56:18.027451 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13043 10:56:18.027652 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13044 10:56:18.027832 arm64_za-ptrace_Set_VL_528 pass
13045 10:56:18.027984 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13046 10:56:18.028160 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13047 10:56:18.028369 arm64_za-ptrace_Set_VL_544 pass
13048 10:56:18.028545 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13049 10:56:18.028696 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13050 10:56:18.028843 arm64_za-ptrace_Set_VL_560 pass
13051 10:56:18.028988 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13052 10:56:18.029174 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13053 10:56:18.029384 arm64_za-ptrace_Set_VL_576 pass
13054 10:56:18.029583 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13055 10:56:18.029780 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13056 10:56:18.029976 arm64_za-ptrace_Set_VL_592 pass
13057 10:56:18.030134 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13058 10:56:18.030279 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13059 10:56:18.030465 arm64_za-ptrace_Set_VL_608 pass
13060 10:56:18.030635 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13061 10:56:18.030803 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13062 10:56:18.030945 arm64_za-ptrace_Set_VL_624 pass
13063 10:56:18.031061 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13064 10:56:18.031176 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13065 10:56:18.031288 arm64_za-ptrace_Set_VL_640 pass
13066 10:56:18.031401 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13067 10:56:18.031544 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13068 10:56:18.031664 arm64_za-ptrace_Set_VL_656 pass
13069 10:56:18.031779 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13070 10:56:18.031895 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13071 10:56:18.032009 arm64_za-ptrace_Set_VL_672 pass
13072 10:56:18.032122 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13073 10:56:18.032234 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13074 10:56:18.032347 arm64_za-ptrace_Set_VL_688 pass
13075 10:56:18.034220 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13076 10:56:18.034670 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13077 10:56:18.034878 arm64_za-ptrace_Set_VL_704 pass
13078 10:56:18.035049 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13079 10:56:18.035214 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13080 10:56:18.035386 arm64_za-ptrace_Set_VL_720 pass
13081 10:56:18.035593 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13082 10:56:18.035764 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13083 10:56:18.035930 arm64_za-ptrace_Set_VL_736 pass
13084 10:56:18.036087 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13085 10:56:18.036232 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13086 10:56:18.036389 arm64_za-ptrace_Set_VL_752 pass
13087 10:56:18.036549 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13088 10:56:18.036714 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13089 10:56:18.036884 arm64_za-ptrace_Set_VL_768 pass
13090 10:56:18.037091 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13091 10:56:18.037316 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13092 10:56:18.037492 arm64_za-ptrace_Set_VL_784 pass
13093 10:56:18.038175 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13094 10:56:18.038336 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13095 10:56:18.038460 arm64_za-ptrace_Set_VL_800 pass
13096 10:56:18.038576 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13097 10:56:18.038691 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13098 10:56:18.038806 arm64_za-ptrace_Set_VL_816 pass
13099 10:56:18.038924 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13100 10:56:18.039038 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13101 10:56:18.039152 arm64_za-ptrace_Set_VL_832 pass
13102 10:56:18.039266 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13103 10:56:18.039381 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13104 10:56:18.039495 arm64_za-ptrace_Set_VL_848 pass
13105 10:56:18.039610 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13106 10:56:18.039724 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13107 10:56:18.039840 arm64_za-ptrace_Set_VL_864 pass
13108 10:56:18.039956 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13109 10:56:18.040070 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13110 10:56:18.040184 arm64_za-ptrace_Set_VL_880 pass
13111 10:56:18.040299 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13112 10:56:18.040414 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13113 10:56:18.040559 arm64_za-ptrace_Set_VL_896 pass
13114 10:56:18.040682 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13115 10:56:18.040799 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13116 10:56:18.040918 arm64_za-ptrace_Set_VL_912 pass
13117 10:56:18.041034 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13118 10:56:18.041149 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13119 10:56:18.041264 arm64_za-ptrace_Set_VL_928 pass
13120 10:56:18.041378 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13121 10:56:18.041492 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13122 10:56:18.041817 arm64_za-ptrace_Set_VL_944 pass
13123 10:56:18.041948 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13124 10:56:18.042305 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13125 10:56:18.042528 arm64_za-ptrace_Set_VL_960 pass
13126 10:56:18.042696 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13127 10:56:18.042839 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13128 10:56:18.043013 arm64_za-ptrace_Set_VL_976 pass
13129 10:56:18.043157 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13130 10:56:18.043287 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13131 10:56:18.043478 arm64_za-ptrace_Set_VL_992 pass
13132 10:56:18.043733 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13133 10:56:18.043969 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13134 10:56:18.044178 arm64_za-ptrace_Set_VL_1008 pass
13135 10:56:18.044368 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13136 10:56:18.044574 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13137 10:56:18.044750 arm64_za-ptrace_Set_VL_1024 pass
13138 10:56:18.044925 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13139 10:56:18.045103 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13140 10:56:18.045266 arm64_za-ptrace_Set_VL_1040 pass
13141 10:56:18.045433 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13142 10:56:18.045599 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13143 10:56:18.045783 arm64_za-ptrace_Set_VL_1056 pass
13144 10:56:18.045957 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13145 10:56:18.046088 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13146 10:56:18.046203 arm64_za-ptrace_Set_VL_1072 pass
13147 10:56:18.046317 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13148 10:56:18.046430 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13149 10:56:18.046545 arm64_za-ptrace_Set_VL_1088 pass
13150 10:56:18.046658 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13151 10:56:18.046771 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13152 10:56:18.046889 arm64_za-ptrace_Set_VL_1104 pass
13153 10:56:18.047003 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13154 10:56:18.047117 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13155 10:56:18.047261 arm64_za-ptrace_Set_VL_1120 pass
13156 10:56:18.047380 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13157 10:56:18.047496 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13158 10:56:18.047610 arm64_za-ptrace_Set_VL_1136 pass
13159 10:56:18.047725 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13160 10:56:18.047839 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13161 10:56:18.047952 arm64_za-ptrace_Set_VL_1152 pass
13162 10:56:18.048066 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13163 10:56:18.050201 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13164 10:56:18.050643 arm64_za-ptrace_Set_VL_1168 pass
13165 10:56:18.050846 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13166 10:56:18.051054 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13167 10:56:18.051274 arm64_za-ptrace_Set_VL_1184 pass
13168 10:56:18.051474 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13169 10:56:18.051683 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13170 10:56:18.051851 arm64_za-ptrace_Set_VL_1200 pass
13171 10:56:18.052017 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13172 10:56:18.052184 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13173 10:56:18.052404 arm64_za-ptrace_Set_VL_1216 pass
13174 10:56:18.052582 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13175 10:56:18.052746 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13176 10:56:18.052894 arm64_za-ptrace_Set_VL_1232 pass
13177 10:56:18.053059 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13178 10:56:18.053223 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13179 10:56:18.053385 arm64_za-ptrace_Set_VL_1248 pass
13180 10:56:18.053586 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13181 10:56:18.054104 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13182 10:56:18.054208 arm64_za-ptrace_Set_VL_1264 pass
13183 10:56:18.054300 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13184 10:56:18.054391 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13185 10:56:18.054481 arm64_za-ptrace_Set_VL_1280 pass
13186 10:56:18.054569 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13187 10:56:18.054659 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13188 10:56:18.054748 arm64_za-ptrace_Set_VL_1296 pass
13189 10:56:18.054836 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13190 10:56:18.054926 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13191 10:56:18.055014 arm64_za-ptrace_Set_VL_1312 pass
13192 10:56:18.055104 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13193 10:56:18.055193 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13194 10:56:18.055282 arm64_za-ptrace_Set_VL_1328 pass
13195 10:56:18.055371 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13196 10:56:18.055459 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13197 10:56:18.055549 arm64_za-ptrace_Set_VL_1344 pass
13198 10:56:18.055638 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13199 10:56:18.055728 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13200 10:56:18.055818 arm64_za-ptrace_Set_VL_1360 pass
13201 10:56:18.055931 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13202 10:56:18.056027 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13203 10:56:18.056120 arm64_za-ptrace_Set_VL_1376 pass
13204 10:56:18.056211 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13205 10:56:18.058389 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13206 10:56:18.058524 arm64_za-ptrace_Set_VL_1392 pass
13207 10:56:18.058670 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13208 10:56:18.058797 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13209 10:56:18.058914 arm64_za-ptrace_Set_VL_1408 pass
13210 10:56:18.059058 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13211 10:56:18.059185 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13212 10:56:18.059303 arm64_za-ptrace_Set_VL_1424 pass
13213 10:56:18.059416 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13214 10:56:18.059557 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13215 10:56:18.059677 arm64_za-ptrace_Set_VL_1440 pass
13216 10:56:18.059795 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13217 10:56:18.059917 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13218 10:56:18.060056 arm64_za-ptrace_Set_VL_1456 pass
13219 10:56:18.060183 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13220 10:56:18.060304 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13221 10:56:18.060426 arm64_za-ptrace_Set_VL_1472 pass
13222 10:56:18.060575 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13223 10:56:18.060696 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13224 10:56:18.060815 arm64_za-ptrace_Set_VL_1488 pass
13225 10:56:18.060928 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13226 10:56:18.061041 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13227 10:56:18.061159 arm64_za-ptrace_Set_VL_1504 pass
13228 10:56:18.061314 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13229 10:56:18.061426 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13230 10:56:18.061518 arm64_za-ptrace_Set_VL_1520 pass
13231 10:56:18.061641 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13232 10:56:18.061811 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13233 10:56:18.061959 arm64_za-ptrace_Set_VL_1536 pass
13234 10:56:18.062102 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13235 10:56:18.078057 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13236 10:56:18.078288 arm64_za-ptrace_Set_VL_1552 pass
13237 10:56:18.078676 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13238 10:56:18.078833 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13239 10:56:18.079001 arm64_za-ptrace_Set_VL_1568 pass
13240 10:56:18.079171 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13241 10:56:18.079339 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13242 10:56:18.079538 arm64_za-ptrace_Set_VL_1584 pass
13243 10:56:18.079705 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13244 10:56:18.079865 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13245 10:56:18.080017 arm64_za-ptrace_Set_VL_1600 pass
13246 10:56:18.080153 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13247 10:56:18.080321 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13248 10:56:18.080488 arm64_za-ptrace_Set_VL_1616 pass
13249 10:56:18.080656 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13250 10:56:18.080804 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13251 10:56:18.080991 arm64_za-ptrace_Set_VL_1632 pass
13252 10:56:18.081122 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13253 10:56:18.081287 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13254 10:56:18.081490 arm64_za-ptrace_Set_VL_1648 pass
13255 10:56:18.082084 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13256 10:56:18.082244 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13257 10:56:18.082370 arm64_za-ptrace_Set_VL_1664 pass
13258 10:56:18.082489 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13259 10:56:18.082607 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13260 10:56:18.082725 arm64_za-ptrace_Set_VL_1680 pass
13261 10:56:18.082843 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13262 10:56:18.082960 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13263 10:56:18.083078 arm64_za-ptrace_Set_VL_1696 pass
13264 10:56:18.083194 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13265 10:56:18.083311 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13266 10:56:18.083460 arm64_za-ptrace_Set_VL_1712 pass
13267 10:56:18.083585 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13268 10:56:18.083704 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13269 10:56:18.083823 arm64_za-ptrace_Set_VL_1728 pass
13270 10:56:18.083940 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13271 10:56:18.084057 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13272 10:56:18.084174 arm64_za-ptrace_Set_VL_1744 pass
13273 10:56:18.084293 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13274 10:56:18.084410 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13275 10:56:18.084527 arm64_za-ptrace_Set_VL_1760 pass
13276 10:56:18.086237 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13277 10:56:18.086772 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13278 10:56:18.086981 arm64_za-ptrace_Set_VL_1776 pass
13279 10:56:18.087172 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13280 10:56:18.087354 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13281 10:56:18.087565 arm64_za-ptrace_Set_VL_1792 pass
13282 10:56:18.087751 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13283 10:56:18.087955 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13284 10:56:18.088141 arm64_za-ptrace_Set_VL_1808 pass
13285 10:56:18.088302 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13286 10:56:18.088442 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13287 10:56:18.088601 arm64_za-ptrace_Set_VL_1824 pass
13288 10:56:18.088767 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13289 10:56:18.088932 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13290 10:56:18.089094 arm64_za-ptrace_Set_VL_1840 pass
13291 10:56:18.089249 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13292 10:56:18.089409 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13293 10:56:18.089568 arm64_za-ptrace_Set_VL_1856 pass
13294 10:56:18.089744 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13295 10:56:18.089910 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13296 10:56:18.090142 arm64_za-ptrace_Set_VL_1872 pass
13297 10:56:18.090288 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13298 10:56:18.090407 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13299 10:56:18.090526 arm64_za-ptrace_Set_VL_1888 pass
13300 10:56:18.090644 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13301 10:56:18.090760 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13302 10:56:18.090876 arm64_za-ptrace_Set_VL_1904 pass
13303 10:56:18.090995 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13304 10:56:18.091112 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13305 10:56:18.091228 arm64_za-ptrace_Set_VL_1920 pass
13306 10:56:18.091343 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13307 10:56:18.091459 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13308 10:56:18.091575 arm64_za-ptrace_Set_VL_1936 pass
13309 10:56:18.091690 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13310 10:56:18.091806 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13311 10:56:18.091922 arm64_za-ptrace_Set_VL_1952 pass
13312 10:56:18.092039 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13313 10:56:18.092155 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13314 10:56:18.092272 arm64_za-ptrace_Set_VL_1968 pass
13315 10:56:18.092392 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13316 10:56:18.092509 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13317 10:56:18.092625 arm64_za-ptrace_Set_VL_1984 pass
13318 10:56:18.094419 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13319 10:56:18.094620 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13320 10:56:18.094820 arm64_za-ptrace_Set_VL_2000 pass
13321 10:56:18.094988 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13322 10:56:18.095140 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13323 10:56:18.095300 arm64_za-ptrace_Set_VL_2016 pass
13324 10:56:18.095490 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13325 10:56:18.095654 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13326 10:56:18.095791 arm64_za-ptrace_Set_VL_2032 pass
13327 10:56:18.095914 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13328 10:56:18.096012 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13329 10:56:18.096104 arm64_za-ptrace_Set_VL_2048 pass
13330 10:56:18.096216 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13331 10:56:18.096328 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13332 10:56:18.096424 arm64_za-ptrace_Set_VL_2064 pass
13333 10:56:18.096524 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13334 10:56:18.096627 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13335 10:56:18.096725 arm64_za-ptrace_Set_VL_2080 pass
13336 10:56:18.096813 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13337 10:56:18.096901 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13338 10:56:18.097009 arm64_za-ptrace_Set_VL_2096 pass
13339 10:56:18.097138 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13340 10:56:18.097265 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13341 10:56:18.097378 arm64_za-ptrace_Set_VL_2112 pass
13342 10:56:18.097500 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13343 10:56:18.098028 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13344 10:56:18.098116 arm64_za-ptrace_Set_VL_2128 pass
13345 10:56:18.098181 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13346 10:56:18.098261 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13347 10:56:18.098325 arm64_za-ptrace_Set_VL_2144 pass
13348 10:56:18.098387 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13349 10:56:18.098448 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13350 10:56:18.098509 arm64_za-ptrace_Set_VL_2160 pass
13351 10:56:18.098570 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13352 10:56:18.098631 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13353 10:56:18.098692 arm64_za-ptrace_Set_VL_2176 pass
13354 10:56:18.098752 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13355 10:56:18.098812 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13356 10:56:18.098872 arm64_za-ptrace_Set_VL_2192 pass
13357 10:56:18.102238 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13358 10:56:18.102558 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13359 10:56:18.102668 arm64_za-ptrace_Set_VL_2208 pass
13360 10:56:18.102775 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13361 10:56:18.102898 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13362 10:56:18.103009 arm64_za-ptrace_Set_VL_2224 pass
13363 10:56:18.103105 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13364 10:56:18.103227 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13365 10:56:18.103326 arm64_za-ptrace_Set_VL_2240 pass
13366 10:56:18.103411 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13367 10:56:18.103489 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13368 10:56:18.103568 arm64_za-ptrace_Set_VL_2256 pass
13369 10:56:18.103660 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13370 10:56:18.103746 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13371 10:56:18.103867 arm64_za-ptrace_Set_VL_2272 pass
13372 10:56:18.103966 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13373 10:56:18.104056 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13374 10:56:18.104146 arm64_za-ptrace_Set_VL_2288 pass
13375 10:56:18.104255 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13376 10:56:18.104351 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13377 10:56:18.104464 arm64_za-ptrace_Set_VL_2304 pass
13378 10:56:18.104567 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13379 10:56:18.104687 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13380 10:56:18.104791 arm64_za-ptrace_Set_VL_2320 pass
13381 10:56:18.104893 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13382 10:56:18.104976 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13383 10:56:18.105076 arm64_za-ptrace_Set_VL_2336 pass
13384 10:56:18.105194 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13385 10:56:18.105296 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13386 10:56:18.105404 arm64_za-ptrace_Set_VL_2352 pass
13387 10:56:18.105499 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13388 10:56:18.105584 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13389 10:56:18.106141 arm64_za-ptrace_Set_VL_2368 pass
13390 10:56:18.106227 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13391 10:56:18.106304 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13392 10:56:18.106379 arm64_za-ptrace_Set_VL_2384 pass
13393 10:56:18.106454 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13394 10:56:18.106529 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13395 10:56:18.106603 arm64_za-ptrace_Set_VL_2400 pass
13396 10:56:18.106677 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13397 10:56:18.110246 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13398 10:56:18.110628 arm64_za-ptrace_Set_VL_2416 pass
13399 10:56:18.110832 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13400 10:56:18.110999 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13401 10:56:18.111192 arm64_za-ptrace_Set_VL_2432 pass
13402 10:56:18.111382 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13403 10:56:18.111591 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13404 10:56:18.111771 arm64_za-ptrace_Set_VL_2448 pass
13405 10:56:18.111947 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13406 10:56:18.112134 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13407 10:56:18.112324 arm64_za-ptrace_Set_VL_2464 pass
13408 10:56:18.112543 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13409 10:56:18.112752 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13410 10:56:18.112950 arm64_za-ptrace_Set_VL_2480 pass
13411 10:56:18.113087 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13412 10:56:18.113207 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13413 10:56:18.113301 arm64_za-ptrace_Set_VL_2496 pass
13414 10:56:18.113406 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13415 10:56:18.113497 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13416 10:56:18.113585 arm64_za-ptrace_Set_VL_2512 pass
13417 10:56:18.113706 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13418 10:56:18.113861 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13419 10:56:18.113988 arm64_za-ptrace_Set_VL_2528 pass
13420 10:56:18.114072 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13421 10:56:18.114147 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13422 10:56:18.114221 arm64_za-ptrace_Set_VL_2544 pass
13423 10:56:18.114295 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13424 10:56:18.114370 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13425 10:56:18.114444 arm64_za-ptrace_Set_VL_2560 pass
13426 10:56:18.114517 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13427 10:56:18.114608 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13428 10:56:18.130268 arm64_za-ptrace_Set_VL_2576 pass
13429 10:56:18.130679 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13430 10:56:18.130782 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13431 10:56:18.130860 arm64_za-ptrace_Set_VL_2592 pass
13432 10:56:18.130924 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13433 10:56:18.131053 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13434 10:56:18.131247 arm64_za-ptrace_Set_VL_2608 pass
13435 10:56:18.131426 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13436 10:56:18.131573 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13437 10:56:18.131702 arm64_za-ptrace_Set_VL_2624 pass
13438 10:56:18.131887 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13439 10:56:18.132058 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13440 10:56:18.132220 arm64_za-ptrace_Set_VL_2640 pass
13441 10:56:18.132367 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13442 10:56:18.132529 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13443 10:56:18.132691 arm64_za-ptrace_Set_VL_2656 pass
13444 10:56:18.132853 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13445 10:56:18.133012 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13446 10:56:18.133266 arm64_za-ptrace_Set_VL_2672 pass
13447 10:56:18.133464 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13448 10:56:18.133658 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13449 10:56:18.133873 arm64_za-ptrace_Set_VL_2688 pass
13450 10:56:18.134570 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13451 10:56:18.134704 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13452 10:56:18.134825 arm64_za-ptrace_Set_VL_2704 pass
13453 10:56:18.134942 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13454 10:56:18.135063 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13455 10:56:18.135178 arm64_za-ptrace_Set_VL_2720 pass
13456 10:56:18.135295 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13457 10:56:18.135413 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13458 10:56:18.135530 arm64_za-ptrace_Set_VL_2736 pass
13459 10:56:18.135647 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13460 10:56:18.135763 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13461 10:56:18.135913 arm64_za-ptrace_Set_VL_2752 pass
13462 10:56:18.136039 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13463 10:56:18.136159 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13464 10:56:18.136291 arm64_za-ptrace_Set_VL_2768 pass
13465 10:56:18.136505 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13466 10:56:18.136679 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13467 10:56:18.136874 arm64_za-ptrace_Set_VL_2784 pass
13468 10:56:18.137046 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13469 10:56:18.138206 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13470 10:56:18.138412 arm64_za-ptrace_Set_VL_2800 pass
13471 10:56:18.138807 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13472 10:56:18.139007 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13473 10:56:18.139206 arm64_za-ptrace_Set_VL_2816 pass
13474 10:56:18.139415 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13475 10:56:18.139598 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13476 10:56:18.139807 arm64_za-ptrace_Set_VL_2832 pass
13477 10:56:18.140037 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13478 10:56:18.140265 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13479 10:56:18.140482 arm64_za-ptrace_Set_VL_2848 pass
13480 10:56:18.140681 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13481 10:56:18.140846 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13482 10:56:18.141149 arm64_za-ptrace_Set_VL_2864 pass
13483 10:56:18.141428 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13484 10:56:18.141605 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13485 10:56:18.141774 arm64_za-ptrace_Set_VL_2880 pass
13486 10:56:18.141990 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13487 10:56:18.142143 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13488 10:56:18.142265 arm64_za-ptrace_Set_VL_2896 pass
13489 10:56:18.142384 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13490 10:56:18.142501 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13491 10:56:18.142618 arm64_za-ptrace_Set_VL_2912 pass
13492 10:56:18.142734 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13493 10:56:18.142851 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13494 10:56:18.142966 arm64_za-ptrace_Set_VL_2928 pass
13495 10:56:18.143082 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13496 10:56:18.143201 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13497 10:56:18.143321 arm64_za-ptrace_Set_VL_2944 pass
13498 10:56:18.143438 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13499 10:56:18.143554 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13500 10:56:18.143671 arm64_za-ptrace_Set_VL_2960 pass
13501 10:56:18.143786 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13502 10:56:18.143903 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13503 10:56:18.144020 arm64_za-ptrace_Set_VL_2976 pass
13504 10:56:18.144137 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13505 10:56:18.144252 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13506 10:56:18.144369 arm64_za-ptrace_Set_VL_2992 pass
13507 10:56:18.144487 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13508 10:56:18.144628 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13509 10:56:18.144751 arm64_za-ptrace_Set_VL_3008 pass
13510 10:56:18.146205 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13511 10:56:18.146640 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13512 10:56:18.146825 arm64_za-ptrace_Set_VL_3024 pass
13513 10:56:18.147034 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13514 10:56:18.147220 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13515 10:56:18.147464 arm64_za-ptrace_Set_VL_3040 pass
13516 10:56:18.147641 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13517 10:56:18.147802 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13518 10:56:18.147964 arm64_za-ptrace_Set_VL_3056 pass
13519 10:56:18.148124 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13520 10:56:18.148286 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13521 10:56:18.148441 arm64_za-ptrace_Set_VL_3072 pass
13522 10:56:18.148600 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13523 10:56:18.148797 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13524 10:56:18.148960 arm64_za-ptrace_Set_VL_3088 pass
13525 10:56:18.149122 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13526 10:56:18.149281 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13527 10:56:18.149445 arm64_za-ptrace_Set_VL_3104 pass
13528 10:56:18.149608 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13529 10:56:18.149788 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13530 10:56:18.149958 arm64_za-ptrace_Set_VL_3120 pass
13531 10:56:18.150088 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13532 10:56:18.150205 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13533 10:56:18.150321 arm64_za-ptrace_Set_VL_3136 pass
13534 10:56:18.150438 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13535 10:56:18.150553 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13536 10:56:18.150668 arm64_za-ptrace_Set_VL_3152 pass
13537 10:56:18.150814 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13538 10:56:18.150935 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13539 10:56:18.151060 arm64_za-ptrace_Set_VL_3168 pass
13540 10:56:18.151177 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13541 10:56:18.151292 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13542 10:56:18.151407 arm64_za-ptrace_Set_VL_3184 pass
13543 10:56:18.151522 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13544 10:56:18.151638 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13545 10:56:18.151755 arm64_za-ptrace_Set_VL_3200 pass
13546 10:56:18.151871 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13547 10:56:18.151987 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13548 10:56:18.152103 arm64_za-ptrace_Set_VL_3216 pass
13549 10:56:18.152218 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13550 10:56:18.154475 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13551 10:56:18.154651 arm64_za-ptrace_Set_VL_3232 pass
13552 10:56:18.154860 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13553 10:56:18.155005 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13554 10:56:18.155156 arm64_za-ptrace_Set_VL_3248 pass
13555 10:56:18.155351 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13556 10:56:18.155560 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13557 10:56:18.155753 arm64_za-ptrace_Set_VL_3264 pass
13558 10:56:18.155952 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13559 10:56:18.156137 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13560 10:56:18.156341 arm64_za-ptrace_Set_VL_3280 pass
13561 10:56:18.156557 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13562 10:56:18.156780 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13563 10:56:18.156972 arm64_za-ptrace_Set_VL_3296 pass
13564 10:56:18.157148 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13565 10:56:18.157310 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13566 10:56:18.157479 arm64_za-ptrace_Set_VL_3312 pass
13567 10:56:18.157619 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13568 10:56:18.157793 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13569 10:56:18.157953 arm64_za-ptrace_Set_VL_3328 pass
13570 10:56:18.158092 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13571 10:56:18.158211 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13572 10:56:18.158329 arm64_za-ptrace_Set_VL_3344 pass
13573 10:56:18.158479 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13574 10:56:18.158605 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13575 10:56:18.158724 arm64_za-ptrace_Set_VL_3360 pass
13576 10:56:18.158843 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13577 10:56:18.158962 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13578 10:56:18.159084 arm64_za-ptrace_Set_VL_3376 pass
13579 10:56:18.159202 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13580 10:56:18.159320 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13581 10:56:18.159438 arm64_za-ptrace_Set_VL_3392 pass
13582 10:56:18.159556 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13583 10:56:18.159676 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13584 10:56:18.159794 arm64_za-ptrace_Set_VL_3408 pass
13585 10:56:18.159913 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13586 10:56:18.162350 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13587 10:56:18.162514 arm64_za-ptrace_Set_VL_3424 pass
13588 10:56:18.162684 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13589 10:56:18.162868 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13590 10:56:18.163090 arm64_za-ptrace_Set_VL_3440 pass
13591 10:56:18.163256 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13592 10:56:18.163460 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13593 10:56:18.163660 arm64_za-ptrace_Set_VL_3456 pass
13594 10:56:18.163914 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13595 10:56:18.164088 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13596 10:56:18.164235 arm64_za-ptrace_Set_VL_3472 pass
13597 10:56:18.164380 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13598 10:56:18.164545 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13599 10:56:18.164726 arm64_za-ptrace_Set_VL_3488 pass
13600 10:56:18.164906 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13601 10:56:18.165057 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13602 10:56:18.165252 arm64_za-ptrace_Set_VL_3504 pass
13603 10:56:18.165418 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13604 10:56:18.165562 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13605 10:56:18.165695 arm64_za-ptrace_Set_VL_3520 pass
13606 10:56:18.165817 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13607 10:56:18.165953 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13608 10:56:18.166074 arm64_za-ptrace_Set_VL_3536 pass
13609 10:56:18.166191 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13610 10:56:18.166305 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13611 10:56:18.166417 arm64_za-ptrace_Set_VL_3552 pass
13612 10:56:18.166529 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13613 10:56:18.166641 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13614 10:56:18.166753 arm64_za-ptrace_Set_VL_3568 pass
13615 10:56:18.166864 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13616 10:56:18.166976 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13617 10:56:18.167116 arm64_za-ptrace_Set_VL_3584 pass
13618 10:56:18.167234 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13619 10:56:18.167347 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13620 10:56:18.186573 arm64_za-ptrace_Set_VL_3600 pass
13621 10:56:18.186912 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13622 10:56:18.187328 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13623 10:56:18.187493 arm64_za-ptrace_Set_VL_3616 pass
13624 10:56:18.187632 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13625 10:56:18.187759 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13626 10:56:18.187881 arm64_za-ptrace_Set_VL_3632 pass
13627 10:56:18.188005 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13628 10:56:18.188128 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13629 10:56:18.188249 arm64_za-ptrace_Set_VL_3648 pass
13630 10:56:18.188363 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13631 10:56:18.188459 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13632 10:56:18.188574 arm64_za-ptrace_Set_VL_3664 pass
13633 10:56:18.188696 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13634 10:56:18.188814 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13635 10:56:18.188938 arm64_za-ptrace_Set_VL_3680 pass
13636 10:56:18.189057 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13637 10:56:18.189176 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13638 10:56:18.189298 arm64_za-ptrace_Set_VL_3696 pass
13639 10:56:18.189447 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13640 10:56:18.189572 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13641 10:56:18.189696 arm64_za-ptrace_Set_VL_3712 pass
13642 10:56:18.189814 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13643 10:56:18.189941 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13644 10:56:18.190065 arm64_za-ptrace_Set_VL_3728 pass
13645 10:56:18.190191 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13646 10:56:18.190289 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13647 10:56:18.190377 arm64_za-ptrace_Set_VL_3744 pass
13648 10:56:18.190485 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13649 10:56:18.190577 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13650 10:56:18.190665 arm64_za-ptrace_Set_VL_3760 pass
13651 10:56:18.190751 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13652 10:56:18.190836 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13653 10:56:18.190922 arm64_za-ptrace_Set_VL_3776 pass
13654 10:56:18.191008 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13655 10:56:18.194302 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13656 10:56:18.194476 arm64_za-ptrace_Set_VL_3792 pass
13657 10:56:18.194805 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13658 10:56:18.194932 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13659 10:56:18.195074 arm64_za-ptrace_Set_VL_3808 pass
13660 10:56:18.195186 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13661 10:56:18.195298 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13662 10:56:18.195390 arm64_za-ptrace_Set_VL_3824 pass
13663 10:56:18.195505 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13664 10:56:18.195673 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13665 10:56:18.195828 arm64_za-ptrace_Set_VL_3840 pass
13666 10:56:18.195986 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13667 10:56:18.196160 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13668 10:56:18.196305 arm64_za-ptrace_Set_VL_3856 pass
13669 10:56:18.196428 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13670 10:56:18.196558 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13671 10:56:18.196682 arm64_za-ptrace_Set_VL_3872 pass
13672 10:56:18.196836 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13673 10:56:18.196967 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13674 10:56:18.197093 arm64_za-ptrace_Set_VL_3888 pass
13675 10:56:18.197214 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13676 10:56:18.197333 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13677 10:56:18.197445 arm64_za-ptrace_Set_VL_3904 pass
13678 10:56:18.197568 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13679 10:56:18.197701 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13680 10:56:18.197860 arm64_za-ptrace_Set_VL_3920 pass
13681 10:56:18.197987 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13682 10:56:18.198099 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13683 10:56:18.198190 arm64_za-ptrace_Set_VL_3936 pass
13684 10:56:18.198277 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13685 10:56:18.198364 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13686 10:56:18.198451 arm64_za-ptrace_Set_VL_3952 pass
13687 10:56:18.198536 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13688 10:56:18.198622 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13689 10:56:18.198708 arm64_za-ptrace_Set_VL_3968 pass
13690 10:56:18.198793 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13691 10:56:18.198879 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13692 10:56:18.198964 arm64_za-ptrace_Set_VL_3984 pass
13693 10:56:18.199070 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13694 10:56:18.202186 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13695 10:56:18.202536 arm64_za-ptrace_Set_VL_4000 pass
13696 10:56:18.202653 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13697 10:56:18.202750 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13698 10:56:18.202858 arm64_za-ptrace_Set_VL_4016 pass
13699 10:56:18.202963 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13700 10:56:18.203082 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13701 10:56:18.203260 arm64_za-ptrace_Set_VL_4032 pass
13702 10:56:18.203431 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13703 10:56:18.203631 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13704 10:56:18.203819 arm64_za-ptrace_Set_VL_4048 pass
13705 10:56:18.203973 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13706 10:56:18.204150 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13707 10:56:18.204313 arm64_za-ptrace_Set_VL_4064 pass
13708 10:56:18.204438 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13709 10:56:18.204556 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13710 10:56:18.204672 arm64_za-ptrace_Set_VL_4080 pass
13711 10:56:18.204785 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13712 10:56:18.204899 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13713 10:56:18.205038 arm64_za-ptrace_Set_VL_4096 pass
13714 10:56:18.205158 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13715 10:56:18.205282 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13716 10:56:18.205425 arm64_za-ptrace_Set_VL_4112 pass
13717 10:56:18.205583 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13718 10:56:18.205761 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13719 10:56:18.205933 arm64_za-ptrace_Set_VL_4128 pass
13720 10:56:18.206107 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13721 10:56:18.206232 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13722 10:56:18.206349 arm64_za-ptrace_Set_VL_4144 pass
13723 10:56:18.206464 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13724 10:56:18.206578 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13725 10:56:18.206692 arm64_za-ptrace_Set_VL_4160 pass
13726 10:56:18.206804 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13727 10:56:18.206916 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13728 10:56:18.207030 arm64_za-ptrace_Set_VL_4176 pass
13729 10:56:18.207144 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13730 10:56:18.207259 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13731 10:56:18.207372 arm64_za-ptrace_Set_VL_4192 pass
13732 10:56:18.207488 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13733 10:56:18.207602 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13734 10:56:18.207716 arm64_za-ptrace_Set_VL_4208 pass
13735 10:56:18.207829 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13736 10:56:18.207944 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13737 10:56:18.210626 arm64_za-ptrace_Set_VL_4224 pass
13738 10:56:18.210834 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13739 10:56:18.211003 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13740 10:56:18.211356 arm64_za-ptrace_Set_VL_4240 pass
13741 10:56:18.211490 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13742 10:56:18.211592 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13743 10:56:18.211685 arm64_za-ptrace_Set_VL_4256 pass
13744 10:56:18.211777 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13745 10:56:18.211868 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13746 10:56:18.211962 arm64_za-ptrace_Set_VL_4272 pass
13747 10:56:18.212075 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13748 10:56:18.212173 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13749 10:56:18.212269 arm64_za-ptrace_Set_VL_4288 pass
13750 10:56:18.212364 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13751 10:56:18.212457 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13752 10:56:18.212551 arm64_za-ptrace_Set_VL_4304 pass
13753 10:56:18.212670 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13754 10:56:18.212815 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13755 10:56:18.212940 arm64_za-ptrace_Set_VL_4320 pass
13756 10:56:18.213059 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13757 10:56:18.213222 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13758 10:56:18.213340 arm64_za-ptrace_Set_VL_4336 pass
13759 10:56:18.213439 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13760 10:56:18.213532 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13761 10:56:18.213642 arm64_za-ptrace_Set_VL_4352 pass
13762 10:56:18.213777 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13763 10:56:18.213920 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13764 10:56:18.214034 arm64_za-ptrace_Set_VL_4368 pass
13765 10:56:18.214126 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13766 10:56:18.214214 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13767 10:56:18.214297 arm64_za-ptrace_Set_VL_4384 pass
13768 10:56:18.214397 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13769 10:56:18.218378 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13770 10:56:18.218746 arm64_za-ptrace_Set_VL_4400 pass
13771 10:56:18.218894 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13772 10:56:18.219007 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13773 10:56:18.219139 arm64_za-ptrace_Set_VL_4416 pass
13774 10:56:18.219265 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13775 10:56:18.219393 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13776 10:56:18.219531 arm64_za-ptrace_Set_VL_4432 pass
13777 10:56:18.219674 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13778 10:56:18.219794 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13779 10:56:18.219890 arm64_za-ptrace_Set_VL_4448 pass
13780 10:56:18.219976 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13781 10:56:18.220083 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13782 10:56:18.220179 arm64_za-ptrace_Set_VL_4464 pass
13783 10:56:18.220284 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13784 10:56:18.220403 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13785 10:56:18.220545 arm64_za-ptrace_Set_VL_4480 pass
13786 10:56:18.220661 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13787 10:56:18.220762 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13788 10:56:18.220887 arm64_za-ptrace_Set_VL_4496 pass
13789 10:56:18.221018 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13790 10:56:18.221199 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13791 10:56:18.221330 arm64_za-ptrace_Set_VL_4512 pass
13792 10:56:18.221440 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13793 10:56:18.221554 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13794 10:56:18.221663 arm64_za-ptrace_Set_VL_4528 pass
13795 10:56:18.221760 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13796 10:56:18.221851 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13797 10:56:18.221971 arm64_za-ptrace_Set_VL_4544 pass
13798 10:56:18.222099 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13799 10:56:18.222199 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13800 10:56:18.222287 arm64_za-ptrace_Set_VL_4560 pass
13801 10:56:18.226279 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13802 10:56:18.226652 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13803 10:56:18.226794 arm64_za-ptrace_Set_VL_4576 pass
13804 10:56:18.226918 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13805 10:56:18.227056 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13806 10:56:18.227205 arm64_za-ptrace_Set_VL_4592 pass
13807 10:56:18.227341 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13808 10:56:18.227460 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13809 10:56:18.227576 arm64_za-ptrace_Set_VL_4608 pass
13810 10:56:18.227714 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13811 10:56:18.227832 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13812 10:56:18.228175 arm64_za-ptrace_Set_VL_4624 pass
13813 10:56:18.251723 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13814 10:56:18.252024 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13815 10:56:18.252213 arm64_za-ptrace_Set_VL_4640 pass
13816 10:56:18.252430 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13817 10:56:18.252596 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13818 10:56:18.252761 arm64_za-ptrace_Set_VL_4656 pass
13819 10:56:18.252963 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13820 10:56:18.253139 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13821 10:56:18.253318 arm64_za-ptrace_Set_VL_4672 pass
13822 10:56:18.253510 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13823 10:56:18.253719 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13824 10:56:18.253903 arm64_za-ptrace_Set_VL_4688 pass
13825 10:56:18.254071 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13826 10:56:18.254192 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13827 10:56:18.254312 arm64_za-ptrace_Set_VL_4704 pass
13828 10:56:18.254426 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13829 10:56:18.254541 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13830 10:56:18.254657 arm64_za-ptrace_Set_VL_4720 pass
13831 10:56:18.254771 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13832 10:56:18.254884 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13833 10:56:18.254998 arm64_za-ptrace_Set_VL_4736 pass
13834 10:56:18.255139 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13835 10:56:18.255264 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13836 10:56:18.255380 arm64_za-ptrace_Set_VL_4752 pass
13837 10:56:18.258253 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13838 10:56:18.258574 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13839 10:56:18.258676 arm64_za-ptrace_Set_VL_4768 pass
13840 10:56:18.258763 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13841 10:56:18.258863 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13842 10:56:18.258950 arm64_za-ptrace_Set_VL_4784 pass
13843 10:56:18.259037 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13844 10:56:18.259139 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13845 10:56:18.259227 arm64_za-ptrace_Set_VL_4800 pass
13846 10:56:18.259325 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13847 10:56:18.259422 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13848 10:56:18.259527 arm64_za-ptrace_Set_VL_4816 pass
13849 10:56:18.259631 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13850 10:56:18.259734 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13851 10:56:18.259840 arm64_za-ptrace_Set_VL_4832 pass
13852 10:56:18.259947 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13853 10:56:18.260052 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13854 10:56:18.260157 arm64_za-ptrace_Set_VL_4848 pass
13855 10:56:18.260475 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13856 10:56:18.260674 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13857 10:56:18.260845 arm64_za-ptrace_Set_VL_4864 pass
13858 10:56:18.261039 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13859 10:56:18.261210 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13860 10:56:18.261378 arm64_za-ptrace_Set_VL_4880 pass
13861 10:56:18.261575 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13862 10:56:18.261752 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13863 10:56:18.261916 arm64_za-ptrace_Set_VL_4896 pass
13864 10:56:18.262058 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13865 10:56:18.262178 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13866 10:56:18.262317 arm64_za-ptrace_Set_VL_4912 pass
13867 10:56:18.262437 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13868 10:56:18.262555 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13869 10:56:18.262671 arm64_za-ptrace_Set_VL_4928 pass
13870 10:56:18.266313 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13871 10:56:18.266746 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13872 10:56:18.266847 arm64_za-ptrace_Set_VL_4944 pass
13873 10:56:18.266936 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13874 10:56:18.267022 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13875 10:56:18.267110 arm64_za-ptrace_Set_VL_4960 pass
13876 10:56:18.267210 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13877 10:56:18.267300 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13878 10:56:18.268276 arm64_za-ptrace_Set_VL_4976 pass
13879 10:56:18.268410 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13880 10:56:18.268505 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13881 10:56:18.268814 arm64_za-ptrace_Set_VL_4992 pass
13882 10:56:18.268935 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13883 10:56:18.269028 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13884 10:56:18.269123 arm64_za-ptrace_Set_VL_5008 pass
13885 10:56:18.269216 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13886 10:56:18.269305 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13887 10:56:18.269393 arm64_za-ptrace_Set_VL_5024 pass
13888 10:56:18.269481 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13889 10:56:18.269569 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13890 10:56:18.269673 arm64_za-ptrace_Set_VL_5040 pass
13891 10:56:18.269784 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13892 10:56:18.269894 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13893 10:56:18.270014 arm64_za-ptrace_Set_VL_5056 pass
13894 10:56:18.270121 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13895 10:56:18.270234 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13896 10:56:18.270327 arm64_za-ptrace_Set_VL_5072 pass
13897 10:56:18.270416 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13898 10:56:18.270504 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13899 10:56:18.270592 arm64_za-ptrace_Set_VL_5088 pass
13900 10:56:18.270680 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13901 10:56:18.270768 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13902 10:56:18.270856 arm64_za-ptrace_Set_VL_5104 pass
13903 10:56:18.270943 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13904 10:56:18.271031 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13905 10:56:18.271119 arm64_za-ptrace_Set_VL_5120 pass
13906 10:56:18.271207 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13907 10:56:18.271299 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13908 10:56:18.271412 arm64_za-ptrace_Set_VL_5136 pass
13909 10:56:18.274494 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13910 10:56:18.274697 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13911 10:56:18.274906 arm64_za-ptrace_Set_VL_5152 pass
13912 10:56:18.275074 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13913 10:56:18.275238 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13914 10:56:18.275406 arm64_za-ptrace_Set_VL_5168 pass
13915 10:56:18.275604 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13916 10:56:18.275754 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13917 10:56:18.275888 arm64_za-ptrace_Set_VL_5184 pass
13918 10:56:18.276043 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13919 10:56:18.276199 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13920 10:56:18.276361 arm64_za-ptrace_Set_VL_5200 pass
13921 10:56:18.276532 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13922 10:56:18.276693 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13923 10:56:18.276858 arm64_za-ptrace_Set_VL_5216 pass
13924 10:56:18.277019 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13925 10:56:18.277187 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13926 10:56:18.277339 arm64_za-ptrace_Set_VL_5232 pass
13927 10:56:18.277540 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13928 10:56:18.278269 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13929 10:56:18.278411 arm64_za-ptrace_Set_VL_5248 pass
13930 10:56:18.278559 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13931 10:56:18.278681 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13932 10:56:18.278799 arm64_za-ptrace_Set_VL_5264 pass
13933 10:56:18.278913 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13934 10:56:18.279028 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13935 10:56:18.279142 arm64_za-ptrace_Set_VL_5280 pass
13936 10:56:18.279256 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13937 10:56:18.279370 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13938 10:56:18.279484 arm64_za-ptrace_Set_VL_5296 pass
13939 10:56:18.279596 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13940 10:56:18.279710 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13941 10:56:18.279824 arm64_za-ptrace_Set_VL_5312 pass
13942 10:56:18.282259 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13943 10:56:18.282701 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13944 10:56:18.282886 arm64_za-ptrace_Set_VL_5328 pass
13945 10:56:18.283027 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13946 10:56:18.283175 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13947 10:56:18.283348 arm64_za-ptrace_Set_VL_5344 pass
13948 10:56:18.283506 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13949 10:56:18.283645 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13950 10:56:18.283802 arm64_za-ptrace_Set_VL_5360 pass
13951 10:56:18.283951 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13952 10:56:18.284119 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13953 10:56:18.284275 arm64_za-ptrace_Set_VL_5376 pass
13954 10:56:18.284368 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13955 10:56:18.284442 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13956 10:56:18.284522 arm64_za-ptrace_Set_VL_5392 pass
13957 10:56:18.284597 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13958 10:56:18.284676 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13959 10:56:18.284771 arm64_za-ptrace_Set_VL_5408 pass
13960 10:56:18.284853 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13961 10:56:18.284931 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13962 10:56:18.285008 arm64_za-ptrace_Set_VL_5424 pass
13963 10:56:18.285085 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13964 10:56:18.285160 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13965 10:56:18.285250 arm64_za-ptrace_Set_VL_5440 pass
13966 10:56:18.285336 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13967 10:56:18.285418 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13968 10:56:18.285502 arm64_za-ptrace_Set_VL_5456 pass
13969 10:56:18.285587 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
13970 10:56:18.285712 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
13971 10:56:18.285822 arm64_za-ptrace_Set_VL_5472 pass
13972 10:56:18.285964 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
13973 10:56:18.286067 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
13974 10:56:18.286151 arm64_za-ptrace_Set_VL_5488 pass
13975 10:56:18.286229 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
13976 10:56:18.290251 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
13977 10:56:18.290685 arm64_za-ptrace_Set_VL_5504 pass
13978 10:56:18.290820 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
13979 10:56:18.290927 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
13980 10:56:18.291036 arm64_za-ptrace_Set_VL_5520 pass
13981 10:56:18.291156 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
13982 10:56:18.291271 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
13983 10:56:18.291352 arm64_za-ptrace_Set_VL_5536 pass
13984 10:56:18.291452 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
13985 10:56:18.291566 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
13986 10:56:18.291662 arm64_za-ptrace_Set_VL_5552 pass
13987 10:56:18.291755 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
13988 10:56:18.291871 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
13989 10:56:18.291958 arm64_za-ptrace_Set_VL_5568 pass
13990 10:56:18.292045 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
13991 10:56:18.292157 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
13992 10:56:18.292263 arm64_za-ptrace_Set_VL_5584 pass
13993 10:56:18.292387 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
13994 10:56:18.292490 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
13995 10:56:18.292610 arm64_za-ptrace_Set_VL_5600 pass
13996 10:56:18.292750 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
13997 10:56:18.292864 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
13998 10:56:18.292976 arm64_za-ptrace_Set_VL_5616 pass
13999 10:56:18.293088 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
14000 10:56:18.293171 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14001 10:56:18.293260 arm64_za-ptrace_Set_VL_5632 pass
14002 10:56:18.293357 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14003 10:56:18.293426 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14004 10:56:18.293488 arm64_za-ptrace_Set_VL_5648 pass
14005 10:56:18.315017 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14006 10:56:18.315467 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14007 10:56:18.315580 arm64_za-ptrace_Set_VL_5664 pass
14008 10:56:18.315678 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14009 10:56:18.315768 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14010 10:56:18.315858 arm64_za-ptrace_Set_VL_5680 pass
14011 10:56:18.315966 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14012 10:56:18.316055 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14013 10:56:18.316138 arm64_za-ptrace_Set_VL_5696 pass
14014 10:56:18.316224 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14015 10:56:18.316327 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14016 10:56:18.316417 arm64_za-ptrace_Set_VL_5712 pass
14017 10:56:18.316506 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14018 10:56:18.316596 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14019 10:56:18.316699 arm64_za-ptrace_Set_VL_5728 pass
14020 10:56:18.316787 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14021 10:56:18.316875 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14022 10:56:18.316960 arm64_za-ptrace_Set_VL_5744 pass
14023 10:56:18.317061 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14024 10:56:18.317149 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14025 10:56:18.317239 arm64_za-ptrace_Set_VL_5760 pass
14026 10:56:18.317330 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14027 10:56:18.317435 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14028 10:56:18.317522 arm64_za-ptrace_Set_VL_5776 pass
14029 10:56:18.317605 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14030 10:56:18.317714 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14031 10:56:18.317801 arm64_za-ptrace_Set_VL_5792 pass
14032 10:56:18.317904 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14033 10:56:18.317993 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14034 10:56:18.318092 arm64_za-ptrace_Set_VL_5808 pass
14035 10:56:18.318175 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14036 10:56:18.322194 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14037 10:56:18.322507 arm64_za-ptrace_Set_VL_5824 pass
14038 10:56:18.322608 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14039 10:56:18.322698 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14040 10:56:18.322802 arm64_za-ptrace_Set_VL_5840 pass
14041 10:56:18.322893 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14042 10:56:18.322996 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14043 10:56:18.323087 arm64_za-ptrace_Set_VL_5856 pass
14044 10:56:18.323370 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14045 10:56:18.323468 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14046 10:56:18.323557 arm64_za-ptrace_Set_VL_5872 pass
14047 10:56:18.323664 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14048 10:56:18.323754 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14049 10:56:18.323860 arm64_za-ptrace_Set_VL_5888 pass
14050 10:56:18.324150 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14051 10:56:18.324251 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14052 10:56:18.324343 arm64_za-ptrace_Set_VL_5904 pass
14053 10:56:18.324433 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14054 10:56:18.324540 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14055 10:56:18.324636 arm64_za-ptrace_Set_VL_5920 pass
14056 10:56:18.324728 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14057 10:56:18.324835 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14058 10:56:18.324927 arm64_za-ptrace_Set_VL_5936 pass
14059 10:56:18.325016 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14060 10:56:18.325116 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14061 10:56:18.325251 arm64_za-ptrace_Set_VL_5952 pass
14062 10:56:18.325399 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14063 10:56:18.325493 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14064 10:56:18.325582 arm64_za-ptrace_Set_VL_5968 pass
14065 10:56:18.325703 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14066 10:56:18.325795 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14067 10:56:18.325898 arm64_za-ptrace_Set_VL_5984 pass
14068 10:56:18.326180 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14069 10:56:18.326278 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14070 10:56:18.330184 arm64_za-ptrace_Set_VL_6000 pass
14071 10:56:18.330486 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14072 10:56:18.330589 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14073 10:56:18.330695 arm64_za-ptrace_Set_VL_6016 pass
14074 10:56:18.330791 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14075 10:56:18.330900 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14076 10:56:18.330994 arm64_za-ptrace_Set_VL_6032 pass
14077 10:56:18.331101 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14078 10:56:18.331208 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14079 10:56:18.331300 arm64_za-ptrace_Set_VL_6048 pass
14080 10:56:18.331406 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14081 10:56:18.331517 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14082 10:56:18.331627 arm64_za-ptrace_Set_VL_6064 pass
14083 10:56:18.331732 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14084 10:56:18.331839 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14085 10:56:18.331928 arm64_za-ptrace_Set_VL_6080 pass
14086 10:56:18.332031 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14087 10:56:18.332136 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14088 10:56:18.332436 arm64_za-ptrace_Set_VL_6096 pass
14089 10:56:18.332534 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14090 10:56:18.332632 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14091 10:56:18.332721 arm64_za-ptrace_Set_VL_6112 pass
14092 10:56:18.332812 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14093 10:56:18.332919 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14094 10:56:18.333026 arm64_za-ptrace_Set_VL_6128 pass
14095 10:56:18.333118 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14096 10:56:18.333224 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14097 10:56:18.333318 arm64_za-ptrace_Set_VL_6144 pass
14098 10:56:18.333422 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14099 10:56:18.333522 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14100 10:56:18.333608 arm64_za-ptrace_Set_VL_6160 pass
14101 10:56:18.333715 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14102 10:56:18.334003 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14103 10:56:18.334091 arm64_za-ptrace_Set_VL_6176 pass
14104 10:56:18.338163 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14105 10:56:18.338486 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14106 10:56:18.338594 arm64_za-ptrace_Set_VL_6192 pass
14107 10:56:18.338699 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14108 10:56:18.338793 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14109 10:56:18.338896 arm64_za-ptrace_Set_VL_6208 pass
14110 10:56:18.339002 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14111 10:56:18.339110 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14112 10:56:18.339203 arm64_za-ptrace_Set_VL_6224 pass
14113 10:56:18.339309 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14114 10:56:18.339419 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14115 10:56:18.339514 arm64_za-ptrace_Set_VL_6240 pass
14116 10:56:18.339810 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14117 10:56:18.339911 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14118 10:56:18.340003 arm64_za-ptrace_Set_VL_6256 pass
14119 10:56:18.340108 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14120 10:56:18.340200 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14121 10:56:18.340292 arm64_za-ptrace_Set_VL_6272 pass
14122 10:56:18.340400 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14123 10:56:18.340496 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14124 10:56:18.340600 arm64_za-ptrace_Set_VL_6288 pass
14125 10:56:18.340687 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14126 10:56:18.340790 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14127 10:56:18.340880 arm64_za-ptrace_Set_VL_6304 pass
14128 10:56:18.340986 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14129 10:56:18.341076 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14130 10:56:18.341181 arm64_za-ptrace_Set_VL_6320 pass
14131 10:56:18.341272 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14132 10:56:18.341569 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14133 10:56:18.341683 arm64_za-ptrace_Set_VL_6336 pass
14134 10:56:18.341778 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14135 10:56:18.341871 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14136 10:56:18.341961 arm64_za-ptrace_Set_VL_6352 pass
14137 10:56:18.342046 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14138 10:56:18.342154 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14139 10:56:18.342248 arm64_za-ptrace_Set_VL_6368 pass
14140 10:56:18.342336 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14141 10:56:18.342426 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14142 10:56:18.346192 arm64_za-ptrace_Set_VL_6384 pass
14143 10:56:18.346616 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14144 10:56:18.346837 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14145 10:56:18.346999 arm64_za-ptrace_Set_VL_6400 pass
14146 10:56:18.347157 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14147 10:56:18.347296 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14148 10:56:18.347466 arm64_za-ptrace_Set_VL_6416 pass
14149 10:56:18.347638 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14150 10:56:18.347784 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14151 10:56:18.347946 arm64_za-ptrace_Set_VL_6432 pass
14152 10:56:18.348082 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14153 10:56:18.348212 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14154 10:56:18.348339 arm64_za-ptrace_Set_VL_6448 pass
14155 10:56:18.348468 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14156 10:56:18.348599 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14157 10:56:18.348726 arm64_za-ptrace_Set_VL_6464 pass
14158 10:56:18.348878 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14159 10:56:18.349013 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14160 10:56:18.349146 arm64_za-ptrace_Set_VL_6480 pass
14161 10:56:18.349275 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14162 10:56:18.349403 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14163 10:56:18.349529 arm64_za-ptrace_Set_VL_6496 pass
14164 10:56:18.349668 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14165 10:56:18.349801 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14166 10:56:18.349986 arm64_za-ptrace_Set_VL_6512 pass
14167 10:56:18.350148 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14168 10:56:18.350294 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14169 10:56:18.350443 arm64_za-ptrace_Set_VL_6528 pass
14170 10:56:18.350588 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14171 10:56:18.350731 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14172 10:56:18.350873 arm64_za-ptrace_Set_VL_6544 pass
14173 10:56:18.351016 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14174 10:56:18.351158 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14175 10:56:18.351334 arm64_za-ptrace_Set_VL_6560 pass
14176 10:56:18.354224 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14177 10:56:18.354590 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14178 10:56:18.354732 arm64_za-ptrace_Set_VL_6576 pass
14179 10:56:18.354907 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14180 10:56:18.355046 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14181 10:56:18.355221 arm64_za-ptrace_Set_VL_6592 pass
14182 10:56:18.355366 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14183 10:56:18.355558 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14184 10:56:18.355745 arm64_za-ptrace_Set_VL_6608 pass
14185 10:56:18.355925 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14186 10:56:18.356105 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14187 10:56:18.356269 arm64_za-ptrace_Set_VL_6624 pass
14188 10:56:18.356459 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14189 10:56:18.356663 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14190 10:56:18.356846 arm64_za-ptrace_Set_VL_6640 pass
14191 10:56:18.356985 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14192 10:56:18.357105 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14193 10:56:18.357264 arm64_za-ptrace_Set_VL_6656 pass
14194 10:56:18.357396 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14195 10:56:18.357515 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14196 10:56:18.357671 arm64_za-ptrace_Set_VL_6672 pass
14197 10:56:18.361818 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14198 10:56:18.374615 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14199 10:56:18.374853 arm64_za-ptrace_Set_VL_6688 pass
14200 10:56:18.374936 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14201 10:56:18.375031 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14202 10:56:18.375112 arm64_za-ptrace_Set_VL_6704 pass
14203 10:56:18.375190 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14204 10:56:18.375268 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14205 10:56:18.376125 arm64_za-ptrace_Set_VL_6720 pass
14206 10:56:18.376242 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14207 10:56:18.376335 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14208 10:56:18.376421 arm64_za-ptrace_Set_VL_6736 pass
14209 10:56:18.376521 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14210 10:56:18.376602 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14211 10:56:18.376679 arm64_za-ptrace_Set_VL_6752 pass
14212 10:56:18.376756 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14213 10:56:18.376831 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14214 10:56:18.376908 arm64_za-ptrace_Set_VL_6768 pass
14215 10:56:18.376985 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14216 10:56:18.377062 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14217 10:56:18.377155 arm64_za-ptrace_Set_VL_6784 pass
14218 10:56:18.377236 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14219 10:56:18.377313 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14220 10:56:18.377390 arm64_za-ptrace_Set_VL_6800 pass
14221 10:56:18.377466 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14222 10:56:18.377543 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14223 10:56:18.377620 arm64_za-ptrace_Set_VL_6816 pass
14224 10:56:18.377727 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14225 10:56:18.377808 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14226 10:56:18.377886 arm64_za-ptrace_Set_VL_6832 pass
14227 10:56:18.377970 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14228 10:56:18.378062 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14229 10:56:18.378139 arm64_za-ptrace_Set_VL_6848 pass
14230 10:56:18.378233 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14231 10:56:18.378306 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14232 10:56:18.382282 arm64_za-ptrace_Set_VL_6864 pass
14233 10:56:18.382596 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14234 10:56:18.382686 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14235 10:56:18.382770 arm64_za-ptrace_Set_VL_6880 pass
14236 10:56:18.382839 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14237 10:56:18.382915 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14238 10:56:18.382994 arm64_za-ptrace_Set_VL_6896 pass
14239 10:56:18.383073 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14240 10:56:18.383155 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14241 10:56:18.383428 arm64_za-ptrace_Set_VL_6912 pass
14242 10:56:18.383544 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14243 10:56:18.383661 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14244 10:56:18.383751 arm64_za-ptrace_Set_VL_6928 pass
14245 10:56:18.383852 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14246 10:56:18.383965 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14247 10:56:18.384073 arm64_za-ptrace_Set_VL_6944 pass
14248 10:56:18.384184 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14249 10:56:18.384292 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14250 10:56:18.384374 arm64_za-ptrace_Set_VL_6960 pass
14251 10:56:18.384471 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14252 10:56:18.384804 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14253 10:56:18.384911 arm64_za-ptrace_Set_VL_6976 pass
14254 10:56:18.384995 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14255 10:56:18.385104 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14256 10:56:18.385179 arm64_za-ptrace_Set_VL_6992 pass
14257 10:56:18.385271 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14258 10:56:18.385530 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14259 10:56:18.385604 arm64_za-ptrace_Set_VL_7008 pass
14260 10:56:18.385689 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14261 10:56:18.385782 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14262 10:56:18.385854 arm64_za-ptrace_Set_VL_7024 pass
14263 10:56:18.385963 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14264 10:56:18.390156 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14265 10:56:18.390435 arm64_za-ptrace_Set_VL_7040 pass
14266 10:56:18.390519 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14267 10:56:18.390613 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14268 10:56:18.390870 arm64_za-ptrace_Set_VL_7056 pass
14269 10:56:18.390942 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14270 10:56:18.391033 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14271 10:56:18.391289 arm64_za-ptrace_Set_VL_7072 pass
14272 10:56:18.391369 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14273 10:56:18.391472 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14274 10:56:18.391572 arm64_za-ptrace_Set_VL_7088 pass
14275 10:56:18.391679 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14276 10:56:18.391794 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14277 10:56:18.391884 arm64_za-ptrace_Set_VL_7104 pass
14278 10:56:18.391983 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14279 10:56:18.392256 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14280 10:56:18.392340 arm64_za-ptrace_Set_VL_7120 pass
14281 10:56:18.392416 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14282 10:56:18.392491 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14283 10:56:18.392570 arm64_za-ptrace_Set_VL_7136 pass
14284 10:56:18.392826 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14285 10:56:18.392905 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14286 10:56:18.392979 arm64_za-ptrace_Set_VL_7152 pass
14287 10:56:18.393226 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14288 10:56:18.393303 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14289 10:56:18.393377 arm64_za-ptrace_Set_VL_7168 pass
14290 10:56:18.393622 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14291 10:56:18.393707 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14292 10:56:18.393959 arm64_za-ptrace_Set_VL_7184 pass
14293 10:56:18.394038 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14294 10:56:18.398205 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14295 10:56:18.398515 arm64_za-ptrace_Set_VL_7200 pass
14296 10:56:18.398590 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14297 10:56:18.398659 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14298 10:56:18.398745 arm64_za-ptrace_Set_VL_7216 pass
14299 10:56:18.399022 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14300 10:56:18.399104 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14301 10:56:18.399195 arm64_za-ptrace_Set_VL_7232 pass
14302 10:56:18.399289 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14303 10:56:18.399378 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14304 10:56:18.399500 arm64_za-ptrace_Set_VL_7248 pass
14305 10:56:18.399596 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14306 10:56:18.399713 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14307 10:56:18.399813 arm64_za-ptrace_Set_VL_7264 pass
14308 10:56:18.399901 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14309 10:56:18.400168 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14310 10:56:18.400241 arm64_za-ptrace_Set_VL_7280 pass
14311 10:56:18.400332 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14312 10:56:18.401825 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14313 10:56:18.401900 arm64_za-ptrace_Set_VL_7296 pass
14314 10:56:18.401977 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14315 10:56:18.402053 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14316 10:56:18.402128 arm64_za-ptrace_Set_VL_7312 pass
14317 10:56:18.402203 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14318 10:56:18.402277 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14319 10:56:18.402351 arm64_za-ptrace_Set_VL_7328 pass
14320 10:56:18.402425 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14321 10:56:18.402499 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14322 10:56:18.402573 arm64_za-ptrace_Set_VL_7344 pass
14323 10:56:18.402647 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14324 10:56:18.402721 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14325 10:56:18.402795 arm64_za-ptrace_Set_VL_7360 pass
14326 10:56:18.402869 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14327 10:56:18.402944 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14328 10:56:18.403018 arm64_za-ptrace_Set_VL_7376 pass
14329 10:56:18.403092 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14330 10:56:18.403165 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14331 10:56:18.403239 arm64_za-ptrace_Set_VL_7392 pass
14332 10:56:18.403313 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14333 10:56:18.403569 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14334 10:56:18.406236 arm64_za-ptrace_Set_VL_7408 pass
14335 10:56:18.406537 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14336 10:56:18.406836 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14337 10:56:18.406922 arm64_za-ptrace_Set_VL_7424 pass
14338 10:56:18.407019 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14339 10:56:18.407110 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14340 10:56:18.407389 arm64_za-ptrace_Set_VL_7440 pass
14341 10:56:18.407498 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14342 10:56:18.407587 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14343 10:56:18.407663 arm64_za-ptrace_Set_VL_7456 pass
14344 10:56:18.407745 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14345 10:56:18.407847 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14346 10:56:18.407940 arm64_za-ptrace_Set_VL_7472 pass
14347 10:56:18.408044 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14348 10:56:18.408149 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14349 10:56:18.408262 arm64_za-ptrace_Set_VL_7488 pass
14350 10:56:18.408380 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14351 10:56:18.408485 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14352 10:56:18.408594 arm64_za-ptrace_Set_VL_7504 pass
14353 10:56:18.408689 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14354 10:56:18.408804 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14355 10:56:18.408914 arm64_za-ptrace_Set_VL_7520 pass
14356 10:56:18.409029 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14357 10:56:18.409158 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14358 10:56:18.409250 arm64_za-ptrace_Set_VL_7536 pass
14359 10:56:18.409338 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14360 10:56:18.409464 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14361 10:56:18.409566 arm64_za-ptrace_Set_VL_7552 pass
14362 10:56:18.409688 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14363 10:56:18.409797 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14364 10:56:18.409894 arm64_za-ptrace_Set_VL_7568 pass
14365 10:56:18.410007 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14366 10:56:18.410105 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14367 10:56:18.414278 arm64_za-ptrace_Set_VL_7584 pass
14368 10:56:18.414559 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14369 10:56:18.414670 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14370 10:56:18.414769 arm64_za-ptrace_Set_VL_7600 pass
14371 10:56:18.414858 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14372 10:56:18.415117 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14373 10:56:18.415189 arm64_za-ptrace_Set_VL_7616 pass
14374 10:56:18.415264 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14375 10:56:18.415355 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14376 10:56:18.415610 arm64_za-ptrace_Set_VL_7632 pass
14377 10:56:18.415683 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14378 10:56:18.415774 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14379 10:56:18.415860 arm64_za-ptrace_Set_VL_7648 pass
14380 10:56:18.416115 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14381 10:56:18.416187 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14382 10:56:18.416278 arm64_za-ptrace_Set_VL_7664 pass
14383 10:56:18.416365 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14384 10:56:18.416629 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14385 10:56:18.416701 arm64_za-ptrace_Set_VL_7680 pass
14386 10:56:18.416804 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14387 10:56:18.417057 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14388 10:56:18.417128 arm64_za-ptrace_Set_VL_7696 pass
14389 10:56:18.417218 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14390 10:56:18.452924 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14391 10:56:18.453193 arm64_za-ptrace_Set_VL_7712 pass
14392 10:56:18.453290 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14393 10:56:18.453598 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14394 10:56:18.453723 arm64_za-ptrace_Set_VL_7728 pass
14395 10:56:18.453813 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14396 10:56:18.453901 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14397 10:56:18.453991 arm64_za-ptrace_Set_VL_7744 pass
14398 10:56:18.454080 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14399 10:56:18.454171 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14400 10:56:18.454263 arm64_za-ptrace_Set_VL_7760 pass
14401 10:56:18.454354 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14402 10:56:18.454464 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14403 10:56:18.454555 arm64_za-ptrace_Set_VL_7776 pass
14404 10:56:18.454649 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14405 10:56:18.454737 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14406 10:56:18.454822 arm64_za-ptrace_Set_VL_7792 pass
14407 10:56:18.454907 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14408 10:56:18.454994 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14409 10:56:18.455083 arm64_za-ptrace_Set_VL_7808 pass
14410 10:56:18.455185 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14411 10:56:18.455276 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14412 10:56:18.455370 arm64_za-ptrace_Set_VL_7824 pass
14413 10:56:18.455457 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14414 10:56:18.455537 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14415 10:56:18.455623 arm64_za-ptrace_Set_VL_7840 pass
14416 10:56:18.455708 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14417 10:56:18.455811 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14418 10:56:18.455898 arm64_za-ptrace_Set_VL_7856 pass
14419 10:56:18.455983 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14420 10:56:18.456070 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14421 10:56:18.456155 arm64_za-ptrace_Set_VL_7872 pass
14422 10:56:18.456243 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14423 10:56:18.456330 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14424 10:56:18.456416 arm64_za-ptrace_Set_VL_7888 pass
14425 10:56:18.456503 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14426 10:56:18.456609 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14427 10:56:18.456703 arm64_za-ptrace_Set_VL_7904 pass
14428 10:56:18.456791 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14429 10:56:18.456878 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14430 10:56:18.456963 arm64_za-ptrace_Set_VL_7920 pass
14431 10:56:18.457049 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14432 10:56:18.457131 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14433 10:56:18.457210 arm64_za-ptrace_Set_VL_7936 pass
14434 10:56:18.457313 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14435 10:56:18.457401 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14436 10:56:18.457486 arm64_za-ptrace_Set_VL_7952 pass
14437 10:56:18.457572 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14438 10:56:18.458411 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14439 10:56:18.458516 arm64_za-ptrace_Set_VL_7968 pass
14440 10:56:18.458605 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14441 10:56:18.458690 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14442 10:56:18.458779 arm64_za-ptrace_Set_VL_7984 pass
14443 10:56:18.458869 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14444 10:56:18.458957 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14445 10:56:18.459041 arm64_za-ptrace_Set_VL_8000 pass
14446 10:56:18.459126 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14447 10:56:18.459213 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14448 10:56:18.459302 arm64_za-ptrace_Set_VL_8016 pass
14449 10:56:18.459391 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14450 10:56:18.459481 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14451 10:56:18.459570 arm64_za-ptrace_Set_VL_8032 pass
14452 10:56:18.459659 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14453 10:56:18.462261 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14454 10:56:18.462592 arm64_za-ptrace_Set_VL_8048 pass
14455 10:56:18.462694 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14456 10:56:18.462786 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14457 10:56:18.462877 arm64_za-ptrace_Set_VL_8064 pass
14458 10:56:18.462986 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14459 10:56:18.463080 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14460 10:56:18.463171 arm64_za-ptrace_Set_VL_8080 pass
14461 10:56:18.463262 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14462 10:56:18.463372 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14463 10:56:18.463465 arm64_za-ptrace_Set_VL_8096 pass
14464 10:56:18.463553 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14465 10:56:18.463645 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14466 10:56:18.463755 arm64_za-ptrace_Set_VL_8112 pass
14467 10:56:18.463847 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14468 10:56:18.463939 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14469 10:56:18.464032 arm64_za-ptrace_Set_VL_8128 pass
14470 10:56:18.464140 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14471 10:56:18.464231 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14472 10:56:18.464318 arm64_za-ptrace_Set_VL_8144 pass
14473 10:56:18.464406 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14474 10:56:18.464513 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14475 10:56:18.464604 arm64_za-ptrace_Set_VL_8160 pass
14476 10:56:18.464699 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14477 10:56:18.464788 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14478 10:56:18.464877 arm64_za-ptrace_Set_VL_8176 pass
14479 10:56:18.464983 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14480 10:56:18.465075 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14481 10:56:18.465164 arm64_za-ptrace_Set_VL_8192 pass
14482 10:56:18.465270 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14483 10:56:18.465362 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14484 10:56:18.465453 arm64_za-ptrace pass
14485 10:56:18.465559 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14486 10:56:18.465975 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14487 10:56:18.466083 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14488 10:56:18.470219 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14489 10:56:18.470552 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14490 10:56:18.470639 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14491 10:56:18.470897 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14492 10:56:18.470971 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14493 10:56:18.471054 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14494 10:56:18.471316 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14495 10:56:18.471649 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14496 10:56:18.471780 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14497 10:56:18.472140 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14498 10:56:18.472466 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14499 10:56:18.472619 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14500 10:56:18.472949 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14501 10:56:18.473357 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14502 10:56:18.473704 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14503 10:56:18.473811 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14504 10:56:18.474236 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14505 10:56:18.474344 arm64_check_buffer_fill fail
14506 10:56:18.474985 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14507 10:56:18.475091 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14508 10:56:18.482274 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14509 10:56:18.482840 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14510 10:56:18.482978 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14511 10:56:18.483090 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14512 10:56:18.484194 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14513 10:56:18.484293 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14514 10:56:18.484383 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14515 10:56:18.484488 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14516 10:56:18.484578 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14517 10:56:18.484891 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14518 10:56:18.485133 arm64_check_child_memory fail
14519 10:56:18.485367 arm64_check_gcr_el1_cswitch fail
14520 10:56:18.485704 arm64_check_ksm_options fail
14521 10:56:18.485965 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14522 10:56:18.486108 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14523 10:56:18.490248 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14524 10:56:18.490621 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14525 10:56:18.490947 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14526 10:56:18.496329 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14527 10:56:18.496808 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14528 10:56:18.497021 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14529 10:56:18.497250 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14530 10:56:18.497620 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14531 10:56:18.497966 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14532 10:56:18.498552 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14533 10:56:18.498924 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14534 10:56:18.499251 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14535 10:56:18.499549 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14536 10:56:18.499871 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14537 10:56:18.500191 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14538 10:56:18.500323 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14539 10:56:18.500675 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14540 10:56:18.500999 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14541 10:56:18.501342 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14542 10:56:18.501674 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14543 10:56:18.501984 arm64_check_mmap_options fail
14544 10:56:18.502078 arm64_check_prctl_check_basic_read pass
14545 10:56:18.502167 arm64_check_prctl_NONE pass
14546 10:56:18.502264 arm64_check_prctl_SYNC pass
14547 10:56:18.506491 arm64_check_prctl_ASYNC pass
14548 10:56:18.506662 arm64_check_prctl_SYNC_ASYNC pass
14549 10:56:18.506759 arm64_check_prctl pass
14550 10:56:18.506867 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14551 10:56:18.506962 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14552 10:56:18.507071 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14553 10:56:18.507377 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14554 10:56:18.507484 arm64_check_tags_inclusion fail
14555 10:56:18.507598 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14556 10:56:18.507988 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14557 10:56:18.508114 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14558 10:56:18.508416 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14559 10:56:18.508541 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14560 10:56:18.508845 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14561 10:56:18.508970 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14562 10:56:18.509285 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14563 10:56:18.509616 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14564 10:56:18.509752 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14565 10:56:18.510067 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14566 10:56:18.514240 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14567 10:56:18.514624 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14568 10:56:18.514754 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14569 10:56:18.515062 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14570 10:56:18.515191 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14571 10:56:18.515491 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14572 10:56:18.516385 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14573 10:56:18.516501 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14574 10:56:18.516589 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14575 10:56:18.516690 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14576 10:56:18.516792 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14577 10:56:18.517162 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14578 10:56:18.517280 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14579 10:56:18.517566 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14580 10:56:18.517679 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14581 10:56:18.519110 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14582 10:56:18.522337 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14583 10:56:18.522747 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14584 10:56:18.522851 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14585 10:56:18.522952 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14586 10:56:18.523260 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14587 10:56:18.523393 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14588 10:56:18.523506 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14589 10:56:18.523854 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14590 10:56:18.523978 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14591 10:56:18.524089 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14592 10:56:18.524417 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14593 10:56:18.524539 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14594 10:56:18.524619 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14595 10:56:18.524893 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14596 10:56:18.525170 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14597 10:56:18.525245 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14598 10:56:18.525340 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14599 10:56:18.525624 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14600 10:56:18.525733 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14601 10:56:18.526032 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14602 10:56:18.534242 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14603 10:56:18.534660 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14604 10:56:18.534772 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14605 10:56:18.534874 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14606 10:56:18.535174 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14607 10:56:18.535308 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14608 10:56:18.535612 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14609 10:56:18.535735 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14610 10:56:18.536449 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14611 10:56:18.536556 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14612 10:56:18.536641 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14613 10:56:18.536727 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14614 10:56:18.537011 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14615 10:56:18.537113 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14616 10:56:18.537398 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14617 10:56:18.551338 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14618 10:56:18.551776 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14619 10:56:18.551865 arm64_check_user_mem pass
14620 10:56:18.551936 arm64_btitest_nohint_func_call_using_br_x0 pass
14621 10:56:18.552001 arm64_btitest_nohint_func_call_using_br_x16 pass
14622 10:56:18.552066 arm64_btitest_nohint_func_call_using_blr pass
14623 10:56:18.552147 arm64_btitest_bti_none_func_call_using_br_x0 pass
14624 10:56:18.552214 arm64_btitest_bti_none_func_call_using_br_x16 pass
14625 10:56:18.552279 arm64_btitest_bti_none_func_call_using_blr pass
14626 10:56:18.552342 arm64_btitest_bti_c_func_call_using_br_x0 pass
14627 10:56:18.552407 arm64_btitest_bti_c_func_call_using_br_x16 pass
14628 10:56:18.552484 arm64_btitest_bti_c_func_call_using_blr pass
14629 10:56:18.552551 arm64_btitest_bti_j_func_call_using_br_x0 pass
14630 10:56:18.552617 arm64_btitest_bti_j_func_call_using_br_x16 pass
14631 10:56:18.552681 arm64_btitest_bti_j_func_call_using_blr pass
14632 10:56:18.552757 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14633 10:56:18.552829 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14634 10:56:18.552893 arm64_btitest_bti_jc_func_call_using_blr pass
14635 10:56:18.552971 arm64_btitest_paciasp_func_call_using_br_x0 pass
14636 10:56:18.553036 arm64_btitest_paciasp_func_call_using_br_x16 pass
14637 10:56:18.553111 arm64_btitest_paciasp_func_call_using_blr pass
14638 10:56:18.553188 arm64_btitest pass
14639 10:56:18.553255 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14640 10:56:18.553331 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14641 10:56:18.553396 arm64_nobtitest_nohint_func_call_using_blr pass
14642 10:56:18.553472 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14643 10:56:18.553539 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14644 10:56:18.553617 arm64_nobtitest_bti_none_func_call_using_blr pass
14645 10:56:18.553709 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14646 10:56:18.553786 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14647 10:56:18.554047 arm64_nobtitest_bti_c_func_call_using_blr pass
14648 10:56:18.554118 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14649 10:56:18.558314 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14650 10:56:18.558661 arm64_nobtitest_bti_j_func_call_using_blr pass
14651 10:56:18.558771 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14652 10:56:18.558868 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14653 10:56:18.558957 arm64_nobtitest_bti_jc_func_call_using_blr pass
14654 10:56:18.559065 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14655 10:56:18.559157 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14656 10:56:18.559246 arm64_nobtitest_paciasp_func_call_using_blr pass
14657 10:56:18.559333 arm64_nobtitest pass
14658 10:56:18.559441 arm64_hwcap_cpuinfo_match_RNG pass
14659 10:56:18.559528 arm64_hwcap_sigill_RNG pass
14660 10:56:18.559614 arm64_hwcap_cpuinfo_match_SME pass
14661 10:56:18.559699 arm64_hwcap_sigill_SME pass
14662 10:56:18.559782 arm64_hwcap_cpuinfo_match_SVE pass
14663 10:56:18.559885 arm64_hwcap_sigill_SVE pass
14664 10:56:18.559971 arm64_hwcap_cpuinfo_match_SVE_2 pass
14665 10:56:18.560056 arm64_hwcap_sigill_SVE_2 pass
14666 10:56:18.560144 arm64_hwcap_cpuinfo_match_SVE_AES pass
14667 10:56:18.560232 arm64_hwcap_sigill_SVE_AES pass
14668 10:56:18.560338 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14669 10:56:18.560428 arm64_hwcap_sigill_SVE2_PMULL pass
14670 10:56:18.560516 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14671 10:56:18.560603 arm64_hwcap_sigill_SVE2_BITPERM pass
14672 10:56:18.560713 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14673 10:56:18.560806 arm64_hwcap_sigill_SVE2_SHA3 pass
14674 10:56:18.560896 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14675 10:56:18.560983 arm64_hwcap_sigill_SVE2_SM4 pass
14676 10:56:18.561086 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14677 10:56:18.561175 arm64_hwcap_sigill_SVE2_I8MM pass
14678 10:56:18.561263 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14679 10:56:18.561367 arm64_hwcap_sigill_SVE2_F32MM pass
14680 10:56:18.561456 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14681 10:56:18.561561 arm64_hwcap_sigill_SVE2_F64MM pass
14682 10:56:18.561661 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14683 10:56:18.561767 arm64_hwcap_sigill_SVE2_BF16 pass
14684 10:56:18.561878 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14685 10:56:18.561970 arm64_hwcap_sigill_SVE2_EBF16 skip
14686 10:56:18.562055 arm64_hwcap pass
14687 10:56:18.562154 arm64_ptrace_read_tpidr_one pass
14688 10:56:18.566585 arm64_ptrace_write_tpidr_one pass
14689 10:56:18.566818 arm64_ptrace_verify_tpidr_one pass
14690 10:56:18.566930 arm64_ptrace_count_tpidrs pass
14691 10:56:18.567023 arm64_ptrace_tpidr2_write pass
14692 10:56:18.567113 arm64_ptrace_tpidr2_read pass
14693 10:56:18.567204 arm64_ptrace_write_tpidr_only pass
14694 10:56:18.567311 arm64_ptrace pass
14695 10:56:18.567401 arm64_syscall-abi_getpid_FPSIMD pass
14696 10:56:18.567485 arm64_syscall-abi_getpid_SVE_VL_256 pass
14697 10:56:18.567581 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14698 10:56:18.567666 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14699 10:56:18.567766 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14700 10:56:18.567852 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14701 10:56:18.567958 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14702 10:56:18.568058 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14703 10:56:18.568161 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14704 10:56:18.568260 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14705 10:56:18.568564 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14706 10:56:18.568657 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14707 10:56:18.568756 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14708 10:56:18.568854 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14709 10:56:18.568961 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14710 10:56:18.569250 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14711 10:56:18.569355 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14712 10:56:18.569458 arm64_syscall-abi_getpid_SVE_VL_240 pass
14713 10:56:18.569557 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14714 10:56:18.569878 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14715 10:56:18.569974 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14716 10:56:18.574533 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14717 10:56:18.575058 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14718 10:56:18.575158 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14719 10:56:18.575237 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14720 10:56:18.575314 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14721 10:56:18.575399 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14722 10:56:18.575493 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14723 10:56:18.575569 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14724 10:56:18.575643 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14725 10:56:18.575732 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14726 10:56:18.575824 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14727 10:56:18.575903 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14728 10:56:18.575978 arm64_syscall-abi_getpid_SVE_VL_224 pass
14729 10:56:18.576068 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14730 10:56:18.576159 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14731 10:56:18.576248 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14732 10:56:18.576350 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14733 10:56:18.576651 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14734 10:56:18.576759 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14735 10:56:18.576861 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14736 10:56:18.576946 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14737 10:56:18.577045 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14738 10:56:18.577349 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14739 10:56:18.577455 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14740 10:56:18.577556 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14741 10:56:18.577670 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14742 10:56:18.577776 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14743 10:56:18.578056 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14744 10:56:18.582532 arm64_syscall-abi_getpid_SVE_VL_208 pass
14745 10:56:18.583089 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14746 10:56:18.583181 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14747 10:56:18.583268 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14748 10:56:18.583345 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14749 10:56:18.583422 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14750 10:56:18.583515 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14751 10:56:18.583593 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14752 10:56:18.583672 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14753 10:56:18.583749 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14754 10:56:18.583840 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14755 10:56:18.583926 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14756 10:56:18.584021 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14757 10:56:18.584102 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14758 10:56:18.584196 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14759 10:56:18.584291 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14760 10:56:18.584374 arm64_syscall-abi_getpid_SVE_VL_192 pass
14761 10:56:18.584470 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14762 10:56:18.584569 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14763 10:56:18.584667 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14764 10:56:18.584989 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14765 10:56:18.585094 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14766 10:56:18.585187 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14767 10:56:18.585280 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14768 10:56:18.585360 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14769 10:56:18.585637 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14770 10:56:18.585738 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14771 10:56:18.585831 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14772 10:56:18.585924 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14773 10:56:18.586015 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14774 10:56:18.590594 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14775 10:56:18.591114 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14776 10:56:18.591202 arm64_syscall-abi_getpid_SVE_VL_176 pass
14777 10:56:18.591281 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14778 10:56:18.591358 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14779 10:56:18.591463 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14780 10:56:18.591541 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14781 10:56:18.591617 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14782 10:56:18.591707 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14783 10:56:18.591819 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14784 10:56:18.592112 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14785 10:56:18.592196 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14786 10:56:18.592968 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14787 10:56:18.612850 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14788 10:56:18.613371 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14789 10:56:18.613457 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14790 10:56:18.613535 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14791 10:56:18.613608 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14792 10:56:18.613714 arm64_syscall-abi_getpid_SVE_VL_160 pass
14793 10:56:18.613800 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14794 10:56:18.613891 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14795 10:56:18.613982 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14796 10:56:18.614060 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14797 10:56:18.614151 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14798 10:56:18.614458 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14799 10:56:18.614575 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14800 10:56:18.614663 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14801 10:56:18.615024 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14802 10:56:18.615323 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14803 10:56:18.615420 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14804 10:56:18.615531 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14805 10:56:18.615652 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14806 10:56:18.615765 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14807 10:56:18.615867 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14808 10:56:18.616153 arm64_syscall-abi_getpid_SVE_VL_144 pass
14809 10:56:18.616261 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14810 10:56:18.616345 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14811 10:56:18.616615 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14812 10:56:18.616711 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14813 10:56:18.616971 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14814 10:56:18.617042 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14815 10:56:18.617118 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14816 10:56:18.617203 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14817 10:56:18.617452 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14818 10:56:18.617548 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14819 10:56:18.617806 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14820 10:56:18.617889 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14821 10:56:18.617990 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14822 10:56:18.622575 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14823 10:56:18.623070 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14824 10:56:18.623155 arm64_syscall-abi_getpid_SVE_VL_128 pass
14825 10:56:18.623222 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14826 10:56:18.623287 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14827 10:56:18.623372 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14828 10:56:18.623450 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14829 10:56:18.623526 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14830 10:56:18.623604 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14831 10:56:18.623866 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14832 10:56:18.623948 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14833 10:56:18.624204 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14834 10:56:18.624285 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14835 10:56:18.624538 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14836 10:56:18.624611 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14837 10:56:18.624687 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14838 10:56:18.624950 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14839 10:56:18.625023 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14840 10:56:18.625097 arm64_syscall-abi_getpid_SVE_VL_112 pass
14841 10:56:18.625358 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14842 10:56:18.625429 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14843 10:56:18.625684 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14844 10:56:18.625759 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14845 10:56:18.626010 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14846 10:56:18.626082 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14847 10:56:18.630526 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14848 10:56:18.631011 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14849 10:56:18.631088 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14850 10:56:18.631156 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14851 10:56:18.631231 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14852 10:56:18.631306 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14853 10:56:18.631420 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14854 10:56:18.631701 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14855 10:56:18.631777 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14856 10:56:18.631854 arm64_syscall-abi_getpid_SVE_VL_96 pass
14857 10:56:18.631932 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14858 10:56:18.632206 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14859 10:56:18.632293 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14860 10:56:18.632548 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14861 10:56:18.632618 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14862 10:56:18.632695 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14863 10:56:18.632953 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14864 10:56:18.633039 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14865 10:56:18.633292 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14866 10:56:18.633365 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14867 10:56:18.633443 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14868 10:56:18.633680 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14869 10:56:18.633764 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14870 10:56:18.634018 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14871 10:56:18.638536 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14872 10:56:18.638988 arm64_syscall-abi_getpid_SVE_VL_80 pass
14873 10:56:18.639062 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14874 10:56:18.639135 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14875 10:56:18.639211 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14876 10:56:18.639293 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14877 10:56:18.639556 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14878 10:56:18.639641 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14879 10:56:18.639895 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14880 10:56:18.639970 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14881 10:56:18.640046 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14882 10:56:18.640303 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14883 10:56:18.640375 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14884 10:56:18.640627 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14885 10:56:18.640699 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14886 10:56:18.640953 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14887 10:56:18.641025 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14888 10:56:18.641103 arm64_syscall-abi_getpid_SVE_VL_64 pass
14889 10:56:18.641358 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14890 10:56:18.641450 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14891 10:56:18.641545 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14892 10:56:18.641636 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14893 10:56:18.641949 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14894 10:56:18.642052 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14895 10:56:18.646769 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14896 10:56:18.647053 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14897 10:56:18.647139 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14898 10:56:18.647254 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14899 10:56:18.647365 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14900 10:56:18.647491 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14901 10:56:18.647804 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14902 10:56:18.647897 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14903 10:56:18.648164 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14904 10:56:18.648238 arm64_syscall-abi_getpid_SVE_VL_48 pass
14905 10:56:18.648318 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14906 10:56:18.648396 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14907 10:56:18.648478 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14908 10:56:18.648740 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14909 10:56:18.648836 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14910 10:56:18.649104 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14911 10:56:18.649197 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14912 10:56:18.649274 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14913 10:56:18.649579 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14914 10:56:18.649703 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14915 10:56:18.649807 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14916 10:56:18.649899 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14917 10:56:18.649999 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14918 10:56:18.650297 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14919 10:56:18.658546 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14920 10:56:18.659116 arm64_syscall-abi_getpid_SVE_VL_32 pass
14921 10:56:18.659320 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14922 10:56:18.659410 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14923 10:56:18.659490 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14924 10:56:18.659587 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14925 10:56:18.659668 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14926 10:56:18.659746 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14927 10:56:18.659824 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14928 10:56:18.659919 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14929 10:56:18.659999 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14930 10:56:18.660095 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14931 10:56:18.660189 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14932 10:56:18.660306 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14933 10:56:18.660603 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14934 10:56:18.660729 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14935 10:56:18.660844 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14936 10:56:18.660963 arm64_syscall-abi_getpid_SVE_VL_16 pass
14937 10:56:18.661280 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14938 10:56:18.661362 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14939 10:56:18.681129 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14940 10:56:18.681640 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14941 10:56:18.681882 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14942 10:56:18.682131 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14943 10:56:18.682308 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14944 10:56:18.682457 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14945 10:56:18.682626 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14946 10:56:18.682773 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14947 10:56:18.682939 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14948 10:56:18.683084 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14949 10:56:18.683225 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14950 10:56:18.683391 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14951 10:56:18.683536 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14952 10:56:18.683677 arm64_syscall-abi_sched_yield_FPSIMD pass
14953 10:56:18.683842 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14954 10:56:18.683988 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14955 10:56:18.684154 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14956 10:56:18.684299 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14957 10:56:18.684464 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14958 10:56:18.684609 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14959 10:56:18.684773 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14960 10:56:18.684939 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14961 10:56:18.685105 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14962 10:56:18.685929 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14963 10:56:18.686121 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14964 10:56:18.686271 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14965 10:56:18.686415 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14966 10:56:18.686583 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14967 10:56:18.690264 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14968 10:56:18.690579 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14969 10:56:18.690674 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
14970 10:56:18.690791 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
14971 10:56:18.690907 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
14972 10:56:18.691225 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
14973 10:56:18.691351 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
14974 10:56:18.691457 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
14975 10:56:18.691755 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
14976 10:56:18.691849 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
14977 10:56:18.691958 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
14978 10:56:18.692279 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
14979 10:56:18.692495 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
14980 10:56:18.692650 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
14981 10:56:18.692838 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
14982 10:56:18.692990 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
14983 10:56:18.693217 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
14984 10:56:18.693402 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
14985 10:56:18.693614 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
14986 10:56:18.693855 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
14987 10:56:18.694031 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
14988 10:56:18.694208 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
14989 10:56:18.694340 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
14990 10:56:18.694440 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
14991 10:56:18.698334 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
14992 10:56:18.698877 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
14993 10:56:18.699065 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
14994 10:56:18.699222 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
14995 10:56:18.699518 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
14996 10:56:18.699629 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
14997 10:56:18.699727 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
14998 10:56:18.699834 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
14999 10:56:18.699924 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
15000 10:56:18.700298 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15001 10:56:18.700393 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15002 10:56:18.700462 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15003 10:56:18.700527 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15004 10:56:18.700785 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15005 10:56:18.700884 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15006 10:56:18.700966 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15007 10:56:18.701058 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15008 10:56:18.701154 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15009 10:56:18.701232 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15010 10:56:18.701324 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15011 10:56:18.701412 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15012 10:56:18.701684 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15013 10:56:18.701962 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15014 10:56:18.702045 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15015 10:56:18.706228 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15016 10:56:18.706716 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15017 10:56:18.706801 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15018 10:56:18.706896 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15019 10:56:18.707003 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15020 10:56:18.707113 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15021 10:56:18.707407 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15022 10:56:18.707519 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15023 10:56:18.707596 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15024 10:56:18.707683 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15025 10:56:18.708001 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15026 10:56:18.708267 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15027 10:56:18.708342 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15028 10:56:18.708434 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15029 10:56:18.708521 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15030 10:56:18.708786 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15031 10:56:18.708871 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15032 10:56:18.709138 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15033 10:56:18.709214 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15034 10:56:18.709305 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15035 10:56:18.709733 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15036 10:56:18.709807 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15037 10:56:18.709900 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15038 10:56:18.709988 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15039 10:56:18.714235 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15040 10:56:18.714512 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15041 10:56:18.714619 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15042 10:56:18.714969 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15043 10:56:18.715082 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15044 10:56:18.715215 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15045 10:56:18.715325 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15046 10:56:18.715443 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15047 10:56:18.715559 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15048 10:56:18.715686 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15049 10:56:18.715790 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15050 10:56:18.716088 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15051 10:56:18.716215 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15052 10:56:18.716331 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15053 10:56:18.716456 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15054 10:56:18.716590 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15055 10:56:18.716916 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15056 10:56:18.717025 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15057 10:56:18.717130 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15058 10:56:18.717391 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15059 10:56:18.717529 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15060 10:56:18.717658 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15061 10:56:18.717763 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15062 10:56:18.718058 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15063 10:56:18.722253 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15064 10:56:18.722572 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15065 10:56:18.722715 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15066 10:56:18.722854 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15067 10:56:18.722968 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15068 10:56:18.723090 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15069 10:56:18.723210 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15070 10:56:18.723500 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15071 10:56:18.723628 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15072 10:56:18.723750 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15073 10:56:18.723850 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15074 10:56:18.724159 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15075 10:56:18.724270 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15076 10:56:18.724381 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15077 10:56:18.724491 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15078 10:56:18.724792 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15079 10:56:18.744960 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15080 10:56:18.745285 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15081 10:56:18.745390 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15082 10:56:18.745491 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15083 10:56:18.745578 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15084 10:56:18.745681 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15085 10:56:18.745954 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15086 10:56:18.746071 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15087 10:56:18.746565 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15088 10:56:18.746878 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15089 10:56:18.746979 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15090 10:56:18.747078 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15091 10:56:18.747175 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15092 10:56:18.747278 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15093 10:56:18.747571 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15094 10:56:18.747689 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15095 10:56:18.747788 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15096 10:56:18.748084 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15097 10:56:18.748193 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15098 10:56:18.748304 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15099 10:56:18.748410 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15100 10:56:18.748718 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15101 10:56:18.748837 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15102 10:56:18.748937 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15103 10:56:18.749235 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15104 10:56:18.749354 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15105 10:56:18.749484 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15106 10:56:18.749605 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15107 10:56:18.749951 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15108 10:56:18.750070 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15109 10:56:18.754318 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15110 10:56:18.754640 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15111 10:56:18.754745 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15112 10:56:18.754839 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15113 10:56:18.755117 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15114 10:56:18.755235 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15115 10:56:18.755319 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15116 10:56:18.755416 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15117 10:56:18.755703 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15118 10:56:18.755818 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15119 10:56:18.755912 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15120 10:56:18.756199 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15121 10:56:18.756301 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15122 10:56:18.756395 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15123 10:56:18.756681 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15124 10:56:18.756788 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15125 10:56:18.756882 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15126 10:56:18.756975 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15127 10:56:18.757255 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15128 10:56:18.757369 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15129 10:56:18.757662 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15130 10:56:18.757778 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15131 10:56:18.757875 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15132 10:56:18.758165 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15133 10:56:18.762284 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15134 10:56:18.762582 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15135 10:56:18.762671 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15136 10:56:18.762953 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15137 10:56:18.763033 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15138 10:56:18.763112 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15139 10:56:18.763369 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15140 10:56:18.763453 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15141 10:56:18.763550 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15142 10:56:18.763806 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15143 10:56:18.763889 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15144 10:56:18.764140 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15145 10:56:18.764221 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15146 10:56:18.764475 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15147 10:56:18.764564 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15148 10:56:18.764821 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15149 10:56:18.764902 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15150 10:56:18.765154 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15151 10:56:18.765230 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15152 10:56:18.765482 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15153 10:56:18.765566 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15154 10:56:18.765829 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15155 10:56:18.765912 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15156 10:56:18.765996 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15157 10:56:18.770530 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15158 10:56:18.770665 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15159 10:56:18.771056 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15160 10:56:18.771173 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15161 10:56:18.771284 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15162 10:56:18.771590 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15163 10:56:18.771704 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15164 10:56:18.771816 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15165 10:56:18.771945 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15166 10:56:18.772055 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15167 10:56:18.772166 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15168 10:56:18.772303 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15169 10:56:18.772415 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15170 10:56:18.772551 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15171 10:56:18.772688 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15172 10:56:18.772815 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15173 10:56:18.772945 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15174 10:56:18.773073 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15175 10:56:18.773213 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15176 10:56:18.773351 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15177 10:56:18.773683 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15178 10:56:18.773815 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15179 10:56:18.773940 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15180 10:56:18.778295 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15181 10:56:18.778612 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15182 10:56:18.778727 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15183 10:56:18.778853 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15184 10:56:18.778995 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15185 10:56:18.779322 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15186 10:56:18.779430 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15187 10:56:18.779530 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15188 10:56:18.783549 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15189 10:56:18.783658 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15190 10:56:18.783745 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15191 10:56:18.783827 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15192 10:56:18.783908 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15193 10:56:18.783988 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15194 10:56:18.784069 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15195 10:56:18.784150 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15196 10:56:18.784230 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15197 10:56:18.784310 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15198 10:56:18.784390 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15199 10:56:18.784470 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15200 10:56:18.784549 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15201 10:56:18.784626 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15202 10:56:18.784702 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15203 10:56:18.784779 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15204 10:56:18.784857 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15205 10:56:18.784935 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15206 10:56:18.785014 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15207 10:56:18.785091 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15208 10:56:18.785168 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15209 10:56:18.785246 arm64_syscall-abi pass
15210 10:56:18.785327 arm64_tpidr2_default_value pass
15211 10:56:18.785404 arm64_tpidr2_write_read pass
15212 10:56:18.785481 arm64_tpidr2_write_sleep_read pass
15213 10:56:18.785558 arm64_tpidr2_write_fork_read pass
15214 10:56:18.785636 arm64_tpidr2_write_clone_read pass
15215 10:56:18.785723 arm64_tpidr2 pass
15216 10:56:18.809659 + ../../utils/send-to-lava.sh ./output/result.txt
15217 10:56:18.881709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15218 10:56:18.882557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15220 10:56:18.936883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15221 10:56:18.937333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15223 10:56:18.988098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15225 10:56:18.988555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15226 10:56:19.036468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15227 10:56:19.036897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15229 10:56:19.083460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15231 10:56:19.083996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15232 10:56:19.126003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15233 10:56:19.126493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15235 10:56:19.177585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15236 10:56:19.178026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15238 10:56:19.234363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15239 10:56:19.234803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15241 10:56:19.288418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15243 10:56:19.288834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15244 10:56:19.347840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15245 10:56:19.348296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15247 10:56:19.398084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15248 10:56:19.398430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15250 10:56:19.451730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15252 10:56:19.451968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15253 10:56:19.505356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15254 10:56:19.505664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15256 10:56:19.558992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15257 10:56:19.559291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15259 10:56:19.613327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15260 10:56:19.613621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15262 10:56:19.674171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15264 10:56:19.674727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15265 10:56:19.734212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15267 10:56:19.734677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15268 10:56:19.788792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15269 10:56:19.789093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15271 10:56:19.843486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15272 10:56:19.843885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15274 10:56:19.893201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15275 10:56:19.893552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15277 10:56:19.941632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15278 10:56:19.941939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15280 10:56:19.990076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15282 10:56:19.990387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15283 10:56:20.039849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15284 10:56:20.040292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15286 10:56:20.079637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15288 10:56:20.080038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15289 10:56:20.115347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15291 10:56:20.115655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15292 10:56:20.160859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15293 10:56:20.161125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15295 10:56:20.210740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15296 10:56:20.210999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15298 10:56:20.259588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15300 10:56:20.259847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15301 10:56:20.305058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15302 10:56:20.305321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15304 10:56:20.344267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15305 10:56:20.344530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15307 10:56:20.383963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15309 10:56:20.385768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15310 10:56:20.424283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15311 10:56:20.424700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15313 10:56:20.473137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15314 10:56:20.473453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15316 10:56:20.520996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15318 10:56:20.521460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15319 10:56:20.568316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15320 10:56:20.568617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15322 10:56:20.616979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15324 10:56:20.617292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15325 10:56:20.657955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15326 10:56:20.658225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15328 10:56:20.702187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15330 10:56:20.702603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15331 10:56:20.751457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15332 10:56:20.751761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15334 10:56:20.787601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15336 10:56:20.787988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15337 10:56:20.836330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15339 10:56:20.836781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15340 10:56:20.884957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15341 10:56:20.885347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15343 10:56:20.936542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15345 10:56:20.937000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15346 10:56:20.988941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15347 10:56:20.989241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15349 10:56:21.041184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15350 10:56:21.041490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15352 10:56:21.093437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15353 10:56:21.093678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15355 10:56:21.145758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15357 10:56:21.146151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15358 10:56:21.199568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15360 10:56:21.200054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15361 10:56:21.251991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15362 10:56:21.252430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15364 10:56:21.305035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15366 10:56:21.305478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15367 10:56:21.358803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15368 10:56:21.359137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15370 10:56:21.410918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15371 10:56:21.411508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15373 10:56:21.463789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15374 10:56:21.464127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15376 10:56:21.516330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15377 10:56:21.516707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15379 10:56:21.569074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15380 10:56:21.569424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15382 10:56:21.621235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15383 10:56:21.621591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15385 10:56:21.674143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15386 10:56:21.674542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15388 10:56:21.725591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15390 10:56:21.725861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15391 10:56:21.777924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15393 10:56:21.778706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15394 10:56:21.828221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15395 10:56:21.828510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15397 10:56:21.876907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15398 10:56:21.877221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15400 10:56:21.925604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15401 10:56:21.925947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15403 10:56:21.975489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15404 10:56:21.975802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15406 10:56:22.024380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15407 10:56:22.024779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15409 10:56:22.072933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15410 10:56:22.073285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15412 10:56:22.123162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15413 10:56:22.123558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15415 10:56:22.172871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15417 10:56:22.173194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15418 10:56:22.219463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15419 10:56:22.219806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15421 10:56:22.269088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15422 10:56:22.269409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15424 10:56:22.320056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15425 10:56:22.320352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15427 10:56:22.373682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15428 10:56:22.374049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15430 10:56:22.421855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15431 10:56:22.422173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15433 10:56:22.465334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15435 10:56:22.465641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15436 10:56:22.515822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15437 10:56:22.516098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15439 10:56:22.570419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15441 10:56:22.570772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15442 10:56:22.624118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15444 10:56:22.624443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15445 10:56:22.677516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15447 10:56:22.677828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15448 10:56:22.732307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15450 10:56:22.732649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15451 10:56:22.785775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15453 10:56:22.786175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15454 10:56:22.840187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15455 10:56:22.840616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15457 10:56:22.893773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15458 10:56:22.894095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15460 10:56:22.948406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15461 10:56:22.948824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15463 10:56:23.004975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15464 10:56:23.005375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15466 10:56:23.057746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15467 10:56:23.058091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15469 10:56:23.110877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15470 10:56:23.111297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15472 10:56:23.164311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15473 10:56:23.164729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15475 10:56:23.217240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15476 10:56:23.217699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15478 10:56:23.269266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15479 10:56:23.269600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15481 10:56:23.321621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15482 10:56:23.321992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15484 10:56:23.374636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15485 10:56:23.374978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15487 10:56:23.429381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15489 10:56:23.429872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15490 10:56:23.480375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15492 10:56:23.480837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15493 10:56:23.531727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15494 10:56:23.532149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15496 10:56:23.582309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15498 10:56:23.582769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15499 10:56:23.633049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15500 10:56:23.633435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15502 10:56:23.685701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15504 10:56:23.686124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15505 10:56:23.736198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15506 10:56:23.736621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15508 10:56:23.785916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15509 10:56:23.786342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15511 10:56:23.839697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15512 10:56:23.840143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15514 10:56:23.891424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15516 10:56:23.891886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15517 10:56:23.940283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15518 10:56:23.940679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15520 10:56:23.976760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15522 10:56:23.977204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15523 10:56:24.014456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15525 10:56:24.014787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15526 10:56:24.053121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15527 10:56:24.053415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15529 10:56:24.097531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15530 10:56:24.097824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15532 10:56:24.144941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15534 10:56:24.145249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15535 10:56:24.184214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15536 10:56:24.184531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15538 10:56:24.220774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15539 10:56:24.221066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15541 10:56:24.257125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15543 10:56:24.257429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15544 10:56:24.303209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15546 10:56:24.303536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15547 10:56:24.339633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15548 10:56:24.339934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15550 10:56:24.381082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15552 10:56:24.381555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15553 10:56:24.433522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15554 10:56:24.433930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15556 10:56:24.483180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15557 10:56:24.483524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15559 10:56:24.532798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15560 10:56:24.533112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15562 10:56:24.581745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15564 10:56:24.582050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15565 10:56:24.625867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15566 10:56:24.626166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15568 10:56:24.667689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15569 10:56:24.667995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15571 10:56:24.711013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15573 10:56:24.711332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15574 10:56:24.756410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15575 10:56:24.756707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15577 10:56:24.807414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15579 10:56:24.807726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15580 10:56:24.852261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15581 10:56:24.852558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15583 10:56:24.899759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15585 10:56:24.900060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15586 10:56:24.944292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15587 10:56:24.944589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15589 10:56:24.992067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15590 10:56:24.992361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15592 10:56:25.039645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15593 10:56:25.039955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15595 10:56:25.087901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15596 10:56:25.088242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15598 10:56:25.138067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15599 10:56:25.138499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15601 10:56:25.184495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15602 10:56:25.184922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15604 10:56:25.230699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15606 10:56:25.231198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15607 10:56:25.275545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15608 10:56:25.275928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15610 10:56:25.319652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15611 10:56:25.320065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15613 10:56:25.363617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15614 10:56:25.364000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15616 10:56:25.409922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15617 10:56:25.410360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15619 10:56:25.457284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15621 10:56:25.457771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15622 10:56:25.503952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15623 10:56:25.504386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15625 10:56:25.549229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15626 10:56:25.549684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15628 10:56:25.593412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15629 10:56:25.593814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15631 10:56:25.641633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15632 10:56:25.642069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15634 10:56:25.688794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15635 10:56:25.689227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15637 10:56:25.737285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15638 10:56:25.737691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15640 10:56:25.787795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15642 10:56:25.788210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15643 10:56:25.838630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15645 10:56:25.839254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15646 10:56:25.887147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15647 10:56:25.887584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15649 10:56:25.933654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15650 10:56:25.934046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15652 10:56:25.980888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15653 10:56:25.981310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15655 10:56:26.027496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15656 10:56:26.027924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15658 10:56:26.072515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15660 10:56:26.072975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15661 10:56:26.119704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15662 10:56:26.120141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15664 10:56:26.165460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15665 10:56:26.165899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15667 10:56:26.201224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15668 10:56:26.201637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15670 10:56:26.247604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15671 10:56:26.248016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15673 10:56:26.289927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15674 10:56:26.290363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15676 10:56:26.335298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15677 10:56:26.335724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15679 10:56:26.381790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15680 10:56:26.382186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15682 10:56:26.425993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15683 10:56:26.426414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15685 10:56:26.471380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15686 10:56:26.471808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15688 10:56:26.515570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15689 10:56:26.515980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15691 10:56:26.559970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15692 10:56:26.560389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15694 10:56:26.604325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15695 10:56:26.604764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15697 10:56:26.649016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15698 10:56:26.649435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15700 10:56:26.694429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15702 10:56:26.694882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15703 10:56:26.740079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15704 10:56:26.740478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15706 10:56:26.787602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15707 10:56:26.788025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15709 10:56:26.834958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15710 10:56:26.835374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15712 10:56:26.883989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15713 10:56:26.884435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15715 10:56:26.925581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15716 10:56:26.926021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15718 10:56:26.969761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15719 10:56:26.970188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15721 10:56:27.008238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15722 10:56:27.008654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15724 10:56:27.042167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15726 10:56:27.042615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15727 10:56:27.088350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15728 10:56:27.088747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15730 10:56:27.131083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15731 10:56:27.131475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15733 10:56:27.174488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15735 10:56:27.174860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15736 10:56:27.216702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15737 10:56:27.217097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15739 10:56:27.261184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15740 10:56:27.261584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15742 10:56:27.304492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15743 10:56:27.304900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15745 10:56:27.349106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15746 10:56:27.349503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15748 10:56:27.392279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15749 10:56:27.392691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15751 10:56:27.439060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15753 10:56:27.439506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15754 10:56:27.484935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15755 10:56:27.485348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15757 10:56:27.531362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15758 10:56:27.531782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15760 10:56:27.576769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15761 10:56:27.577190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15763 10:56:27.616227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15765 10:56:27.616681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15766 10:56:27.653007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15767 10:56:27.653401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15769 10:56:27.697842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15770 10:56:27.698249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15772 10:56:27.745615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15773 10:56:27.746043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15775 10:56:27.792888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15776 10:56:27.793324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15778 10:56:27.837660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15779 10:56:27.838080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15781 10:56:27.882867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15782 10:56:27.883289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15784 10:56:27.932865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15785 10:56:27.933304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15787 10:56:27.981198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15788 10:56:27.981612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15790 10:56:28.028624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15791 10:56:28.029045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15793 10:56:28.077410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15794 10:56:28.078412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15796 10:56:28.123324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15797 10:56:28.123742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15799 10:56:28.172083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15800 10:56:28.172504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15802 10:56:28.213325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15804 10:56:28.213769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15805 10:56:28.257781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15807 10:56:28.258222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15808 10:56:28.302372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15809 10:56:28.302779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15811 10:56:28.348871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15812 10:56:28.349303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15814 10:56:28.394931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15816 10:56:28.395369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15817 10:56:28.440312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15819 10:56:28.440685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15820 10:56:28.487675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15821 10:56:28.488108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15823 10:56:28.535778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15825 10:56:28.536219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15826 10:56:28.582301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15828 10:56:28.582798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15829 10:56:28.632814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15830 10:56:28.633234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15832 10:56:28.680887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15833 10:56:28.681313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15835 10:56:28.728226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15836 10:56:28.728629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15838 10:56:28.775199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15839 10:56:28.775608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15841 10:56:28.820384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15842 10:56:28.820755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15844 10:56:28.865222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15845 10:56:28.865606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15847 10:56:28.912324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15848 10:56:28.912708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15850 10:56:28.955679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15851 10:56:28.956126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15853 10:56:29.001238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15854 10:56:29.001678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15856 10:56:29.060097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15857 10:56:29.060506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15859 10:56:29.102139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15861 10:56:29.102575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15862 10:56:29.149389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15864 10:56:29.149853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15865 10:56:29.195097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15866 10:56:29.195539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15868 10:56:29.239673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15869 10:56:29.240110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15871 10:56:29.285376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15872 10:56:29.285802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15874 10:56:29.334298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15876 10:56:29.334781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15877 10:56:29.381357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15878 10:56:29.381746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15880 10:56:29.428571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15881 10:56:29.428969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15883 10:56:29.476090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15884 10:56:29.476505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15886 10:56:29.524278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15888 10:56:29.524724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15889 10:56:29.572131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15890 10:56:29.572571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15892 10:56:29.621850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15893 10:56:29.622304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15895 10:56:29.669973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15896 10:56:29.670401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15898 10:56:29.718210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15900 10:56:29.718696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15901 10:56:29.768081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15902 10:56:29.768514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15904 10:56:29.819014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15905 10:56:29.819438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15907 10:56:29.868361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15908 10:56:29.868811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15910 10:56:29.916804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15911 10:56:29.917199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15913 10:56:29.965657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15915 10:56:29.966096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15916 10:56:30.013280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15917 10:56:30.013685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15919 10:56:30.061379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15920 10:56:30.061775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15922 10:56:30.111514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15923 10:56:30.111909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15925 10:56:30.161023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15926 10:56:30.161417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15928 10:56:30.210503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15930 10:56:30.210988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15931 10:56:30.260355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15933 10:56:30.260780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15934 10:56:30.309426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15935 10:56:30.309820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15937 10:56:30.361149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15939 10:56:30.361599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15940 10:56:30.411689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15941 10:56:30.412085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15943 10:56:30.461217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15944 10:56:30.461688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15946 10:56:30.508978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15947 10:56:30.509389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15949 10:56:30.556539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15950 10:56:30.556992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15952 10:56:30.605371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15953 10:56:30.605808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15955 10:56:30.652910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15956 10:56:30.653337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15958 10:56:30.699388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15960 10:56:30.699837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15961 10:56:30.744910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15962 10:56:30.745263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15964 10:56:30.794054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15965 10:56:30.794460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15967 10:56:30.842326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
15969 10:56:30.842804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15970 10:56:30.889220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
15971 10:56:30.889652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
15973 10:56:30.935840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
15974 10:56:30.936224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
15976 10:56:30.982445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
15978 10:56:30.982921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
15979 10:56:31.029014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
15981 10:56:31.029430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
15982 10:56:31.076715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
15983 10:56:31.077158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
15985 10:56:31.125319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
15986 10:56:31.125675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
15988 10:56:31.175379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
15990 10:56:31.175832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
15991 10:56:31.224893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
15992 10:56:31.225302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
15994 10:56:31.273842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
15995 10:56:31.274254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
15997 10:56:31.321499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
15998 10:56:31.321894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
16000 10:56:31.357258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16001 10:56:31.357664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16003 10:56:31.398471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16005 10:56:31.399027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16006 10:56:31.443941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16007 10:56:31.444361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16009 10:56:31.488974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16010 10:56:31.489390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16012 10:56:31.535677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16013 10:56:31.536117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16015 10:56:31.581458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16017 10:56:31.581931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16018 10:56:31.626449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16020 10:56:31.626913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16021 10:56:31.671346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16022 10:56:31.671767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16024 10:56:31.718152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16025 10:56:31.718580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16027 10:56:31.764222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16028 10:56:31.764667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16030 10:56:31.809489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16031 10:56:31.809916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16033 10:56:31.855517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16034 10:56:31.855938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16036 10:56:31.901330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16037 10:56:31.901759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16039 10:56:31.947869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16041 10:56:31.948322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16042 10:56:31.994562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16044 10:56:31.995015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16045 10:56:32.039310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16046 10:56:32.039696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16048 10:56:32.082530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16050 10:56:32.082991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16051 10:56:32.127613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16052 10:56:32.128043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16054 10:56:32.175997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16055 10:56:32.176397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16057 10:56:32.221262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16059 10:56:32.221762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16060 10:56:32.268778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16061 10:56:32.269148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16063 10:56:32.313271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16064 10:56:32.313677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16066 10:56:32.359588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16067 10:56:32.359997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16069 10:56:32.404017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16070 10:56:32.404417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16072 10:56:32.449130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16073 10:56:32.449534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16075 10:56:32.495998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16076 10:56:32.496426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16078 10:56:32.543378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16080 10:56:32.543850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16081 10:56:32.587042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16082 10:56:32.587431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16084 10:56:32.633699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16086 10:56:32.634147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16087 10:56:32.680767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16088 10:56:32.681151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16090 10:56:32.727235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16091 10:56:32.727662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16093 10:56:32.777335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16095 10:56:32.777758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16096 10:56:32.828738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16098 10:56:32.829046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16099 10:56:32.880996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16100 10:56:32.881350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16102 10:56:32.932263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16103 10:56:32.932716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16105 10:56:32.984253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16107 10:56:32.984674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16108 10:56:33.036382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16109 10:56:33.036775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16111 10:56:33.089271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16113 10:56:33.089585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16114 10:56:33.140819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16116 10:56:33.141328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16117 10:56:33.192295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16118 10:56:33.192685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16120 10:56:33.244356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16122 10:56:33.244682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16123 10:56:33.295576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16124 10:56:33.295891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16126 10:56:33.347842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16127 10:56:33.348134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16129 10:56:33.400545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16130 10:56:33.400869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16132 10:56:33.453051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16133 10:56:33.453368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16135 10:56:33.507812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16137 10:56:33.508134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16138 10:56:33.563671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16139 10:56:33.563935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16141 10:56:33.617015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16142 10:56:33.617310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16144 10:56:33.670370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16146 10:56:33.670727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16147 10:56:33.725767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16148 10:56:33.726056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16150 10:56:33.777854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16151 10:56:33.778140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16153 10:56:33.829235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16154 10:56:33.829537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16156 10:56:33.881158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16157 10:56:33.881541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16159 10:56:33.933352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16161 10:56:33.933686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16162 10:56:33.986330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16164 10:56:33.986997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16165 10:56:34.038483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16167 10:56:34.038963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16168 10:56:34.091937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16170 10:56:34.092269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16171 10:56:34.147634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16172 10:56:34.147997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16174 10:56:34.201092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16175 10:56:34.201427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16177 10:56:34.252278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16179 10:56:34.252579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16180 10:56:34.304973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16181 10:56:34.305269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16183 10:56:34.356528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16184 10:56:34.356820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16186 10:56:34.407966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16187 10:56:34.408253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16189 10:56:34.459243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16190 10:56:34.459524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16192 10:56:34.509470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16194 10:56:34.509833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16195 10:56:34.560522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16197 10:56:34.560858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16198 10:56:34.612585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16199 10:56:34.612983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16201 10:56:34.664691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16202 10:56:34.664997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16204 10:56:34.716495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16206 10:56:34.716880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16207 10:56:34.768453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16208 10:56:34.768745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16210 10:56:34.821696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16211 10:56:34.822384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16213 10:56:34.872835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16214 10:56:34.873231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16216 10:56:34.924330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16217 10:56:34.924760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16219 10:56:34.976621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16221 10:56:34.977063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16222 10:56:35.028465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16223 10:56:35.028847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16225 10:56:35.080123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16226 10:56:35.080566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16228 10:56:35.131417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16229 10:56:35.131723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16231 10:56:35.181816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16232 10:56:35.182121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16234 10:56:35.233846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16236 10:56:35.234188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16237 10:56:35.284863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16238 10:56:35.285391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16240 10:56:35.336868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16241 10:56:35.337298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16243 10:56:35.388829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16245 10:56:35.389171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16246 10:56:35.439991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16247 10:56:35.440304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16249 10:56:35.492779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16251 10:56:35.493164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16252 10:56:35.544811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16253 10:56:35.545128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16255 10:56:35.596580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16257 10:56:35.596910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16258 10:56:35.649355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16260 10:56:35.649747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16261 10:56:35.700773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16263 10:56:35.701102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16264 10:56:35.753261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16265 10:56:35.753572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16267 10:56:35.804417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16268 10:56:35.804697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16270 10:56:35.856081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16271 10:56:35.856376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16273 10:56:35.907909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16274 10:56:35.908199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16276 10:56:35.960167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16277 10:56:35.960465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16279 10:56:36.011408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16280 10:56:36.011701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16282 10:56:36.061524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16283 10:56:36.061815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16285 10:56:36.112548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16286 10:56:36.112851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16288 10:56:36.164336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16290 10:56:36.164650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16291 10:56:36.215805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16292 10:56:36.216241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16294 10:56:36.265535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16295 10:56:36.265842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16297 10:56:36.316641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16299 10:56:36.316960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16300 10:56:36.368331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16301 10:56:36.368631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16303 10:56:36.419706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16304 10:56:36.420049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16306 10:56:36.471514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16307 10:56:36.471832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16309 10:56:36.521476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16310 10:56:36.521773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16312 10:56:36.572702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16314 10:56:36.573001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16315 10:56:36.624414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16317 10:56:36.624650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16318 10:56:36.675964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16320 10:56:36.676266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16321 10:56:36.727317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16322 10:56:36.727608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16324 10:56:36.778432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16326 10:56:36.778732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16327 10:56:36.829332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16328 10:56:36.829641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16330 10:56:36.881199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16332 10:56:36.881556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16333 10:56:36.931500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16335 10:56:36.931960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16336 10:56:36.975354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16337 10:56:36.975647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16339 10:56:37.014478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16341 10:56:37.014869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16342 10:56:37.069860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16343 10:56:37.070299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16345 10:56:37.124308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16346 10:56:37.124732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16348 10:56:37.177302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16349 10:56:37.177688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16351 10:56:37.230494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16353 10:56:37.230900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16354 10:56:37.285472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16355 10:56:37.285885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16357 10:56:37.339078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16358 10:56:37.339509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16360 10:56:37.392389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16361 10:56:37.392807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16363 10:56:37.445307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16364 10:56:37.445738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16366 10:56:37.499035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16367 10:56:37.499433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16369 10:56:37.552245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16370 10:56:37.552679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16372 10:56:37.607234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16373 10:56:37.607652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16375 10:56:37.661166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16377 10:56:37.661684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16378 10:56:37.713787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16379 10:56:37.714202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16381 10:56:37.767763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16382 10:56:37.768207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16384 10:56:37.821320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16385 10:56:37.821751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16387 10:56:37.875610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16388 10:56:37.876030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16390 10:56:37.929887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16391 10:56:37.930319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16393 10:56:37.984065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16394 10:56:37.984477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16396 10:56:38.037371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16397 10:56:38.037794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16399 10:56:38.090563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16401 10:56:38.091014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16402 10:56:38.144526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16403 10:56:38.144952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16405 10:56:38.197198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16406 10:56:38.197631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16408 10:56:38.251235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16409 10:56:38.251669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16411 10:56:38.304490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16412 10:56:38.304922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16414 10:56:38.357754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16415 10:56:38.358164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16417 10:56:38.412236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16418 10:56:38.412670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16420 10:56:38.465840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16421 10:56:38.466215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16423 10:56:38.520804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16425 10:56:38.521315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16426 10:56:38.575603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16427 10:56:38.576043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16429 10:56:38.630162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16430 10:56:38.630596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16432 10:56:38.686078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16433 10:56:38.686495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16435 10:56:38.740659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16437 10:56:38.741161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16438 10:56:38.794023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16439 10:56:38.794532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16441 10:56:38.848569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16442 10:56:38.849001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16444 10:56:38.902236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16445 10:56:38.903493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16447 10:56:38.957123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16449 10:56:38.957628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16450 10:56:39.011911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16451 10:56:39.012313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16453 10:56:39.066234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16455 10:56:39.066786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16456 10:56:39.120283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16457 10:56:39.120683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16459 10:56:39.172414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16460 10:56:39.172848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16462 10:56:39.223935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16463 10:56:39.224363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16465 10:56:39.275393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16466 10:56:39.275824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16468 10:56:39.327586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16469 10:56:39.328023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16471 10:56:39.378488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16473 10:56:39.378993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16474 10:56:39.428877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16475 10:56:39.429285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16477 10:56:39.481425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16478 10:56:39.481847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16480 10:56:39.532827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16481 10:56:39.533255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16483 10:56:39.585161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16485 10:56:39.585615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16486 10:56:39.623330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16487 10:56:39.623779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16489 10:56:39.668049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16490 10:56:39.668485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16492 10:56:39.718225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16493 10:56:39.718661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16495 10:56:39.765796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16496 10:56:39.766223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16498 10:56:39.804887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16499 10:56:39.805287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16501 10:56:39.856216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16502 10:56:39.856662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16504 10:56:39.908790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16505 10:56:39.909186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16507 10:56:39.960488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16508 10:56:39.960914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16510 10:56:40.012289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16512 10:56:40.012790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16513 10:56:40.064726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16514 10:56:40.065102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16516 10:56:40.117906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16517 10:56:40.118330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16519 10:56:40.169936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16520 10:56:40.170379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16522 10:56:40.223375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16524 10:56:40.223818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16525 10:56:40.276877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16526 10:56:40.277275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16528 10:56:40.330545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16530 10:56:40.331000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16531 10:56:40.384009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16532 10:56:40.384439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16534 10:56:40.437492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16535 10:56:40.437835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16537 10:56:40.492174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16538 10:56:40.492816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16540 10:56:40.545136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16541 10:56:40.545567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16543 10:56:40.602051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16544 10:56:40.602490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16546 10:56:40.654084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16548 10:56:40.654540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16549 10:56:40.705837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16550 10:56:40.706240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16552 10:56:40.757483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16553 10:56:40.757948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16555 10:56:40.810129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16556 10:56:40.810570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16558 10:56:40.864701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16559 10:56:40.865126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16561 10:56:40.917583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16563 10:56:40.918066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16564 10:56:40.971181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16565 10:56:40.971620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16567 10:56:41.024899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16569 10:56:41.025354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16570 10:56:41.076402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16572 10:56:41.076854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16573 10:56:41.128092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16574 10:56:41.128473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16576 10:56:41.180742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16577 10:56:41.181194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16579 10:56:41.235961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16580 10:56:41.236412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16582 10:56:41.289516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16583 10:56:41.289979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16585 10:56:41.341337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16586 10:56:41.341797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16588 10:56:41.393161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16589 10:56:41.393613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16591 10:56:41.445014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16592 10:56:41.445468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16594 10:56:41.498518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16595 10:56:41.499317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16597 10:56:41.549501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16598 10:56:41.549958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16600 10:56:41.601353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16601 10:56:41.601770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16603 10:56:41.655150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16605 10:56:41.656495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16606 10:56:41.709682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16608 10:56:41.710132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16609 10:56:41.764530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16611 10:56:41.765011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16612 10:56:41.818076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16613 10:56:41.818525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16615 10:56:41.872837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16616 10:56:41.873294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16618 10:56:41.927256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16619 10:56:41.927653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16621 10:56:41.980120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16622 10:56:41.980559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16624 10:56:42.032616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16625 10:56:42.033051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16627 10:56:42.084709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16628 10:56:42.085097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16630 10:56:42.137732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16631 10:56:42.139330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16633 10:56:42.189366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16634 10:56:42.189772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16636 10:56:42.240873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16638 10:56:42.241370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16639 10:56:42.293439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16640 10:56:42.293848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16642 10:56:42.347732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16643 10:56:42.348182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16645 10:56:42.404468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16646 10:56:42.404913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16648 10:56:42.462098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16650 10:56:42.462544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16651 10:56:42.518476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16653 10:56:42.518938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16654 10:56:42.569307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16655 10:56:42.569687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16657 10:56:42.620539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16658 10:56:42.620968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16660 10:56:42.673177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16661 10:56:42.673612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16663 10:56:42.724251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16664 10:56:42.724706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16666 10:56:42.775583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16668 10:56:42.776079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16669 10:56:42.825466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16670 10:56:42.825906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16672 10:56:42.877008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16674 10:56:42.877482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16675 10:56:42.928150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16676 10:56:42.928546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16678 10:56:42.981966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16679 10:56:42.982440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16681 10:56:43.036509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16682 10:56:43.036892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16684 10:56:43.090191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16686 10:56:43.090601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16687 10:56:43.144672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16689 10:56:43.145042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16690 10:56:43.200523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16691 10:56:43.200877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16693 10:56:43.255467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16694 10:56:43.255835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16696 10:56:43.309539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16697 10:56:43.309845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16699 10:56:43.364827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16700 10:56:43.365100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16702 10:56:43.418381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16704 10:56:43.418769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16705 10:56:43.472378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16706 10:56:43.472707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16708 10:56:43.525754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16710 10:56:43.526446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16711 10:56:43.584126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16713 10:56:43.584467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16714 10:56:43.641092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16715 10:56:43.641560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16717 10:56:43.697369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16718 10:56:43.697787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16720 10:56:43.756581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16721 10:56:43.756973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16723 10:56:43.811801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16724 10:56:43.812174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16726 10:56:43.865916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16727 10:56:43.866314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16729 10:56:43.920749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16731 10:56:43.921225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16732 10:56:43.975714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16733 10:56:43.976149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16735 10:56:44.030001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16736 10:56:44.030417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16738 10:56:44.085160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16739 10:56:44.085460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16741 10:56:44.140557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16742 10:56:44.140852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16744 10:56:44.196884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16745 10:56:44.197231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16747 10:56:44.253305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16748 10:56:44.253693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16750 10:56:44.307884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16751 10:56:44.308268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16753 10:56:44.363789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16755 10:56:44.364125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16756 10:56:44.419697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16758 10:56:44.419944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16759 10:56:44.473841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16760 10:56:44.474136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16762 10:56:44.528602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16763 10:56:44.528874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16765 10:56:44.583663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16766 10:56:44.583981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16768 10:56:44.637803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16769 10:56:44.638262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16771 10:56:44.693518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16772 10:56:44.693927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16774 10:56:44.749291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16775 10:56:44.749591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16777 10:56:44.805680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16778 10:56:44.806017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16780 10:56:44.861102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16781 10:56:44.861539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16783 10:56:44.916112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16784 10:56:44.916400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16786 10:56:44.971486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16788 10:56:44.971766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16789 10:56:45.025846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16790 10:56:45.026184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16792 10:56:45.080411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16793 10:56:45.080842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16795 10:56:45.134302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16797 10:56:45.134898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16798 10:56:45.188750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16799 10:56:45.189152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16801 10:56:45.241950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16802 10:56:45.242330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16804 10:56:45.297748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16805 10:56:45.298199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16807 10:56:45.351102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16808 10:56:45.351412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16810 10:56:45.405300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16811 10:56:45.405603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16813 10:56:45.459165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16814 10:56:45.459481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16816 10:56:45.514662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16818 10:56:45.515125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16819 10:56:45.569665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16820 10:56:45.570101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16822 10:56:45.628183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16823 10:56:45.628629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16825 10:56:45.684581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16826 10:56:45.685356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16828 10:56:45.739172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16829 10:56:45.739681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16831 10:56:45.793927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16832 10:56:45.794356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16834 10:56:45.848882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16835 10:56:45.849283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16837 10:56:45.902553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16839 10:56:45.903045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16840 10:56:45.957680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16841 10:56:45.958128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16843 10:56:46.012151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16844 10:56:46.012565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16846 10:56:46.066009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16847 10:56:46.066442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16849 10:56:46.121966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16850 10:56:46.122386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16852 10:56:46.179680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16853 10:56:46.180853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16855 10:56:46.233736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16856 10:56:46.234184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16858 10:56:46.285101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16859 10:56:46.285527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16861 10:56:46.337310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16862 10:56:46.337681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16864 10:56:46.391389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16865 10:56:46.391818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16867 10:56:46.445504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16868 10:56:46.445912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16870 10:56:46.498469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16872 10:56:46.499081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16873 10:56:46.549881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16874 10:56:46.550352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16876 10:56:46.600869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16877 10:56:46.601227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16879 10:56:46.653043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16880 10:56:46.653474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16882 10:56:46.705439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16883 10:56:46.705891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16885 10:56:46.756562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16886 10:56:46.756986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16888 10:56:46.808132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16889 10:56:46.808555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16891 10:56:46.860605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16892 10:56:46.861039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16894 10:56:46.912275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16895 10:56:46.912714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16897 10:56:46.964343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16899 10:56:46.964806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16900 10:56:47.016244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16902 10:56:47.016742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16903 10:56:47.068310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16905 10:56:47.068761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16906 10:56:47.119147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16907 10:56:47.119542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16909 10:56:47.168339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16910 10:56:47.168772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16912 10:56:47.219346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16913 10:56:47.219805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16915 10:56:47.269105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16916 10:56:47.269560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16918 10:56:47.319620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16920 10:56:47.320112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16921 10:56:47.363564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16922 10:56:47.363997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16924 10:56:47.407690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16925 10:56:47.408122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16927 10:56:47.456539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16928 10:56:47.456977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16930 10:56:47.511852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16931 10:56:47.512276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16933 10:56:47.561784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16934 10:56:47.562202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16936 10:56:47.606046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16937 10:56:47.606492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16939 10:56:47.658016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16941 10:56:47.658494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16942 10:56:47.708562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16943 10:56:47.709056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16945 10:56:47.758588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16947 10:56:47.759059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16948 10:56:47.809481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16949 10:56:47.809945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16951 10:56:47.860570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16953 10:56:47.860985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16954 10:56:47.911511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16955 10:56:47.911934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16957 10:56:47.960364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16958 10:56:47.960791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16960 10:56:48.012275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16961 10:56:48.012701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16963 10:56:48.056616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16965 10:56:48.057083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16966 10:56:48.107208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16967 10:56:48.107666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16969 10:56:48.150718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
16971 10:56:48.151205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
16972 10:56:48.189658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
16973 10:56:48.190102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
16975 10:56:48.240344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
16976 10:56:48.240774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
16978 10:56:48.292712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
16979 10:56:48.293152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
16981 10:56:48.336506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
16982 10:56:48.336939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
16984 10:56:48.383934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
16985 10:56:48.384367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
16987 10:56:48.433600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
16988 10:56:48.434045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
16990 10:56:48.470763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
16991 10:56:48.471173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
16993 10:56:48.517346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
16994 10:56:48.517966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
16996 10:56:48.555276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
16997 10:56:48.555720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
16999 10:56:48.601479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17000 10:56:48.601930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17002 10:56:48.647225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17003 10:56:48.649820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17005 10:56:48.695403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17006 10:56:48.695851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17008 10:56:48.741076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17009 10:56:48.741488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17011 10:56:48.794933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17013 10:56:48.795380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17014 10:56:48.836764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17015 10:56:48.837193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17017 10:56:48.876053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17018 10:56:48.876490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17020 10:56:48.919122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17021 10:56:48.919565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17023 10:56:48.968270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17025 10:56:48.968769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17026 10:56:49.012540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17027 10:56:49.013005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17029 10:56:49.060245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17030 10:56:49.060678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17032 10:56:49.111525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17034 10:56:49.111985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17035 10:56:49.161191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17036 10:56:49.161615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17038 10:56:49.210575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17040 10:56:49.211051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17041 10:56:49.259166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17042 10:56:49.259619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17044 10:56:49.300887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17045 10:56:49.301326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17047 10:56:49.343398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17048 10:56:49.343836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17050 10:56:49.392853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17051 10:56:49.393294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17053 10:56:49.436406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17055 10:56:49.436892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17056 10:56:49.484359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17057 10:56:49.484790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17059 10:56:49.529637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17061 10:56:49.530140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17062 10:56:49.580064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17063 10:56:49.580504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17065 10:56:49.629267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17066 10:56:49.629690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17068 10:56:49.676972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17069 10:56:49.677391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17071 10:56:49.720076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17072 10:56:49.720498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17074 10:56:49.771948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17076 10:56:49.772411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17077 10:56:49.817364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17079 10:56:49.817849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17080 10:56:49.862346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17082 10:56:49.862878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17083 10:56:49.912069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17084 10:56:49.912511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17086 10:56:49.961522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17087 10:56:49.961954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17089 10:56:50.011043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17091 10:56:50.011515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17092 10:56:50.057493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17093 10:56:50.057949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17095 10:56:50.107958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17097 10:56:50.108414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17098 10:56:50.159485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17099 10:56:50.159910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17101 10:56:50.211788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17102 10:56:50.212219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17104 10:56:50.263738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17105 10:56:50.264135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17107 10:56:50.315990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17108 10:56:50.316387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17110 10:56:50.368490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17111 10:56:50.368901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17113 10:56:50.428986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17114 10:56:50.429415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17116 10:56:50.476295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17117 10:56:50.476753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17119 10:56:50.529641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17120 10:56:50.530081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17122 10:56:50.567237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17123 10:56:50.567700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17125 10:56:50.604237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17127 10:56:50.604706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17128 10:56:50.653071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17130 10:56:50.653563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17131 10:56:50.699763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17132 10:56:50.700206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17134 10:56:50.739177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17135 10:56:50.739694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17137 10:56:50.776701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17138 10:56:50.777166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17140 10:56:50.824569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17142 10:56:50.825059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17143 10:56:50.876451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17144 10:56:50.876850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17146 10:56:50.925008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17148 10:56:50.925457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17149 10:56:50.972476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17150 10:56:50.972914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17152 10:56:51.024826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17153 10:56:51.025242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17155 10:56:51.076711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17156 10:56:51.077144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17158 10:56:51.121739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17159 10:56:51.122171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17161 10:56:51.168493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17162 10:56:51.168911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17164 10:56:51.216298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17166 10:56:51.216759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17167 10:56:51.265749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17168 10:56:51.266167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17170 10:56:51.314207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17171 10:56:51.314644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17173 10:56:51.364393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17174 10:56:51.364817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17176 10:56:51.411648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17177 10:56:51.412081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17179 10:56:51.451983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17180 10:56:51.452397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17182 10:56:51.500368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17183 10:56:51.500803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17185 10:56:51.547707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17186 10:56:51.548166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17188 10:56:51.593877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17189 10:56:51.594283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17191 10:56:51.644378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17193 10:56:51.644843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17194 10:56:51.695289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17195 10:56:51.695705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17197 10:56:51.744502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17198 10:56:51.744898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17200 10:56:51.795554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17201 10:56:51.795993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17203 10:56:51.844707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17204 10:56:51.845142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17206 10:56:51.893369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17207 10:56:51.893811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17209 10:56:51.942998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17211 10:56:51.943484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17212 10:56:51.993382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17213 10:56:51.993812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17215 10:56:52.038837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17216 10:56:52.039271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17218 10:56:52.082710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17220 10:56:52.083157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17221 10:56:52.128508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17222 10:56:52.128969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17224 10:56:52.179709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17226 10:56:52.180179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17227 10:56:52.229556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17228 10:56:52.230004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17230 10:56:52.279162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17231 10:56:52.279603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17233 10:56:52.329130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17234 10:56:52.329556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17236 10:56:52.380255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17237 10:56:52.380685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17239 10:56:52.432439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17240 10:56:52.432860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17242 10:56:52.484525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17243 10:56:52.484944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17245 10:56:52.529958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17246 10:56:52.530485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17248 10:56:52.580839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17250 10:56:52.581229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17251 10:56:52.629455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17252 10:56:52.629827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17254 10:56:52.677960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17255 10:56:52.678372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17257 10:56:52.724932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17259 10:56:52.725295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17260 10:56:52.773208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17261 10:56:52.773590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17263 10:56:52.820858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17265 10:56:52.821304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17266 10:56:52.872003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17267 10:56:52.872413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17269 10:56:52.919893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17270 10:56:52.920293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17272 10:56:52.958505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17274 10:56:52.958960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17275 10:56:53.004824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17276 10:56:53.005241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17278 10:56:53.051539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17279 10:56:53.051961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17281 10:56:53.095426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17282 10:56:53.095823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17284 10:56:53.140910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17285 10:56:53.141229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17287 10:56:53.191023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17288 10:56:53.191462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17290 10:56:53.241079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17292 10:56:53.241559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17293 10:56:53.284112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17294 10:56:53.284567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17296 10:56:53.333897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17298 10:56:53.334383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17299 10:56:53.380518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17300 10:56:53.380942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17302 10:56:53.425787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17303 10:56:53.426080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17305 10:56:53.474744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17306 10:56:53.475030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17308 10:56:53.524600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17309 10:56:53.524898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17311 10:56:53.577195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17312 10:56:53.577461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17314 10:56:53.635548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17315 10:56:53.635967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17317 10:56:53.680160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17318 10:56:53.680532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17320 10:56:53.736749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17321 10:56:53.737179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17323 10:56:53.788981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17325 10:56:53.789310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17326 10:56:53.825820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17328 10:56:53.826298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17329 10:56:53.864054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17330 10:56:53.864484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17332 10:56:53.916686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17333 10:56:53.917111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17335 10:56:53.968446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17336 10:56:53.968881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17338 10:56:54.021082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17339 10:56:54.021524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17341 10:56:54.073076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17343 10:56:54.073552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17344 10:56:54.124845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17345 10:56:54.125290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17347 10:56:54.178755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17349 10:56:54.179809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17350 10:56:54.231835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17351 10:56:54.232285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17353 10:56:54.284502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17354 10:56:54.284923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17356 10:56:54.336195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17357 10:56:54.336630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17359 10:56:54.388191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17360 10:56:54.388646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17362 10:56:54.441128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17363 10:56:54.441504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17365 10:56:54.492744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17366 10:56:54.493182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17368 10:56:54.544888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17370 10:56:54.545378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17371 10:56:54.596481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17372 10:56:54.596887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17374 10:56:54.648203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17375 10:56:54.648660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17377 10:56:54.701609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17378 10:56:54.702005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17380 10:56:54.754030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17381 10:56:54.754482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17383 10:56:54.805889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17384 10:56:54.806361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17386 10:56:54.857775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17387 10:56:54.858202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17389 10:56:54.909144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17390 10:56:54.909560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17392 10:56:54.960380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17393 10:56:54.960828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17395 10:56:55.012345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17396 10:56:55.012734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17398 10:56:55.064963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17399 10:56:55.065405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17401 10:56:55.116318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17402 10:56:55.116698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17404 10:56:55.168474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17405 10:56:55.168890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17407 10:56:55.220335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17408 10:56:55.220771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17410 10:56:55.273333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17411 10:56:55.273679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17413 10:56:55.324862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17414 10:56:55.325287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17416 10:56:55.377820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17417 10:56:55.378120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17419 10:56:55.429770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17420 10:56:55.430065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17422 10:56:55.484453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17424 10:56:55.484765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17425 10:56:55.557635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17426 10:56:55.557983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17428 10:56:55.610337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17430 10:56:55.610678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17431 10:56:55.660845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17432 10:56:55.661306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17434 10:56:55.713898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17435 10:56:55.714221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17437 10:56:55.768395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17438 10:56:55.768789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17440 10:56:55.821664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17441 10:56:55.822082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17443 10:56:55.874872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17444 10:56:55.875269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17446 10:56:55.924038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17447 10:56:55.924526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17449 10:56:55.972588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17450 10:56:55.973011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17452 10:56:56.018617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17454 10:56:56.019098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17455 10:56:56.067838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17456 10:56:56.068220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17458 10:56:56.116633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17459 10:56:56.116945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17461 10:56:56.163877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17463 10:56:56.164224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17464 10:56:56.211330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17465 10:56:56.211763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17467 10:56:56.256515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17468 10:56:56.256924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17470 10:56:56.295987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17471 10:56:56.296428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17473 10:56:56.340197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17474 10:56:56.340580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17476 10:56:56.391284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17477 10:56:56.391698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17479 10:56:56.439422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17480 10:56:56.439864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17482 10:56:56.488482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17483 10:56:56.488931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17485 10:56:56.535908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17487 10:56:56.536354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17488 10:56:56.576604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17489 10:56:56.577029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17491 10:56:56.623375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17492 10:56:56.623785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17494 10:56:56.671832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17495 10:56:56.672225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17497 10:56:56.717380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17498 10:56:56.717767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17500 10:56:56.763219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17501 10:56:56.763594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17503 10:56:56.809266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17504 10:56:56.809672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17506 10:56:56.856876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17508 10:56:56.857329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17509 10:56:56.901259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17510 10:56:56.901653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17512 10:56:56.948392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17513 10:56:56.949046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17515 10:56:56.991688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17516 10:56:56.992081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17518 10:56:57.033787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17519 10:56:57.034224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17521 10:56:57.068972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17522 10:56:57.069827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17524 10:56:57.107554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17525 10:56:57.108011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17527 10:56:57.145325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17528 10:56:57.145748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17530 10:56:57.187292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17531 10:56:57.187744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17533 10:56:57.223573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17534 10:56:57.224024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17536 10:56:57.272036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17538 10:56:57.272492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17539 10:56:57.309398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17540 10:56:57.309854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17542 10:56:57.352687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17543 10:56:57.353143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17545 10:56:57.389585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17546 10:56:57.390039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17548 10:56:57.426127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17549 10:56:57.426576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17551 10:56:57.463765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17552 10:56:57.464224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17554 10:56:57.501625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17555 10:56:57.502065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17557 10:56:57.538842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17558 10:56:57.539914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17560 10:56:57.585682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17561 10:56:57.586131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17563 10:56:57.626156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17564 10:56:57.626598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17566 10:56:57.673538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17567 10:56:57.673979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17569 10:56:57.722135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17571 10:56:57.722588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17572 10:56:57.764960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17573 10:56:57.765381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17575 10:56:57.813058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17576 10:56:57.813519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17578 10:56:57.863424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17579 10:56:57.863875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17581 10:56:57.913825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17583 10:56:57.914277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17584 10:56:57.954355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17586 10:56:57.954798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17587 10:56:57.997024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17588 10:56:57.997411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17590 10:56:58.039793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17591 10:56:58.040213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17593 10:56:58.087465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17595 10:56:58.087933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17596 10:56:58.124382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17597 10:56:58.124829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17599 10:56:58.161396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17601 10:56:58.161819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17602 10:56:58.197790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17603 10:56:58.198248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17605 10:56:58.244347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17606 10:56:58.244776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17608 10:56:58.292281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17609 10:56:58.292726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17611 10:56:58.341435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17613 10:56:58.341954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17614 10:56:58.386295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17616 10:56:58.386726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17617 10:56:58.428005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17618 10:56:58.428380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17620 10:56:58.472921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17621 10:56:58.473351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17623 10:56:58.529974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17624 10:56:58.530392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17626 10:56:58.590138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17627 10:56:58.590567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17629 10:56:58.648510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17630 10:56:58.648914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17632 10:56:58.707207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17633 10:56:58.707605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17635 10:56:58.765391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17636 10:56:58.765834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17638 10:56:58.824875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17640 10:56:58.825312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17641 10:56:58.879655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17643 10:56:58.880108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17644 10:56:58.933762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17645 10:56:58.934130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17647 10:56:58.988147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17648 10:56:58.988559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17650 10:56:59.044171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17652 10:56:59.044571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17653 10:56:59.097697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17655 10:56:59.098136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17656 10:56:59.152668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17657 10:56:59.153098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17659 10:56:59.206018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17660 10:56:59.206445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17662 10:56:59.259994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17663 10:56:59.260283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17665 10:56:59.309905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17666 10:56:59.310348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17668 10:56:59.357962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17669 10:56:59.358305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17671 10:56:59.406363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17673 10:56:59.406754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17674 10:56:59.459701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17675 10:56:59.459984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17677 10:56:59.512360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17678 10:56:59.512667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17680 10:56:59.563750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17681 10:56:59.564184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17683 10:56:59.615963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17684 10:56:59.616405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17686 10:56:59.667777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17687 10:56:59.668214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17689 10:56:59.718466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17690 10:56:59.718895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17692 10:56:59.768892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17693 10:56:59.769332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17695 10:56:59.820195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17696 10:56:59.820623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17698 10:56:59.872293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17700 10:56:59.872748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17701 10:56:59.923444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17702 10:56:59.923867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17704 10:56:59.973544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17705 10:56:59.973972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17707 10:57:00.024244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17708 10:57:00.024539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17710 10:57:00.076226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17711 10:57:00.076648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17713 10:57:00.128062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17714 10:57:00.128484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17716 10:57:00.181899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17717 10:57:00.182326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17719 10:57:00.233282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17720 10:57:00.233683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17722 10:57:00.284490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17723 10:57:00.284947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17725 10:57:00.335975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17726 10:57:00.336329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17728 10:57:00.387561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17729 10:57:00.387917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17731 10:57:00.437089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17732 10:57:00.437492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17734 10:57:00.488131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17735 10:57:00.488513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17737 10:57:00.539755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17738 10:57:00.540181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17740 10:57:00.591478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17741 10:57:00.591911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17743 10:57:00.659228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17744 10:57:00.659613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17746 10:57:00.703939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17747 10:57:00.704376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17749 10:57:00.749187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17750 10:57:00.749623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17752 10:57:00.797820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17753 10:57:00.798218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17755 10:57:00.846465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17757 10:57:00.846788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17758 10:57:00.891709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17759 10:57:00.892143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17761 10:57:00.940441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17762 10:57:00.940875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17764 10:57:00.990006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17765 10:57:00.990438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17767 10:57:01.031886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17768 10:57:01.032304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17770 10:57:01.081579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17771 10:57:01.081990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17773 10:57:01.132013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17774 10:57:01.132401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17776 10:57:01.184039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17777 10:57:01.184455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17779 10:57:01.237384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17780 10:57:01.237828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17782 10:57:01.291205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17783 10:57:01.291572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17785 10:57:01.341487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17786 10:57:01.341912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17788 10:57:01.389524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17790 10:57:01.389868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17791 10:57:01.438903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17792 10:57:01.439246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17794 10:57:01.487646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17795 10:57:01.488059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17797 10:57:01.532755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17798 10:57:01.533181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17800 10:57:01.580877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17801 10:57:01.581325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17803 10:57:01.628684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17804 10:57:01.629082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17806 10:57:01.670813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17807 10:57:01.671254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17809 10:57:01.720812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17810 10:57:01.721176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17812 10:57:01.769769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17813 10:57:01.770158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17815 10:57:01.811409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17816 10:57:01.811819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17818 10:57:01.858035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17820 10:57:01.858427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17821 10:57:01.899997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17822 10:57:01.900415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17824 10:57:01.953168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17825 10:57:01.953559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17827 10:57:02.006293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17829 10:57:02.006799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17830 10:57:02.059897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17831 10:57:02.060302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17833 10:57:02.113108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17834 10:57:02.113410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17836 10:57:02.166496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17838 10:57:02.166899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17839 10:57:02.220315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17841 10:57:02.220766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17842 10:57:02.274343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17844 10:57:02.274901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17845 10:57:02.329301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17846 10:57:02.329694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17848 10:57:02.383895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17849 10:57:02.384327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17851 10:57:02.441043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17852 10:57:02.441427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17854 10:57:02.497701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17855 10:57:02.498135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17857 10:57:02.556560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17859 10:57:02.556908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17860 10:57:02.613715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17861 10:57:02.614149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17863 10:57:02.669186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17864 10:57:02.669609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17866 10:57:02.723676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17868 10:57:02.724090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17869 10:57:02.776928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17870 10:57:02.777353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17872 10:57:02.830380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17874 10:57:02.830974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17875 10:57:02.884459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17876 10:57:02.884892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17878 10:57:02.937715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17879 10:57:02.938109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17881 10:57:02.992110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17882 10:57:02.992536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17884 10:57:03.045391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17885 10:57:03.045788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17887 10:57:03.099819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17889 10:57:03.100136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17890 10:57:03.154316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17892 10:57:03.154638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17893 10:57:03.208481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17894 10:57:03.208832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17896 10:57:03.262051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17898 10:57:03.262513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17899 10:57:03.316423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17900 10:57:03.316852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17902 10:57:03.369875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17903 10:57:03.370271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17905 10:57:03.424055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17906 10:57:03.424471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17908 10:57:03.479635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17909 10:57:03.480065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17911 10:57:03.532942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17912 10:57:03.533387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17914 10:57:03.587577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17915 10:57:03.588016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17917 10:57:03.641364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17919 10:57:03.641867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17920 10:57:03.696016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17922 10:57:03.696437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17923 10:57:03.749897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17924 10:57:03.750324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17926 10:57:03.804448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17928 10:57:03.804949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17929 10:57:03.857569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17930 10:57:03.857991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17932 10:57:03.912513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17934 10:57:03.912899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17935 10:57:03.966310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17937 10:57:03.966736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17938 10:57:04.021301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17939 10:57:04.021688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17941 10:57:04.075321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17942 10:57:04.075763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17944 10:57:04.129571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17945 10:57:04.130004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17947 10:57:04.183169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17948 10:57:04.183600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17950 10:57:04.236401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17951 10:57:04.236832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17953 10:57:04.289631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17954 10:57:04.290063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17956 10:57:04.344109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17957 10:57:04.344536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17959 10:57:04.397343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17960 10:57:04.397637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17962 10:57:04.451578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17964 10:57:04.452023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17965 10:57:04.505012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17966 10:57:04.505412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17968 10:57:04.557863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17969 10:57:04.558293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
17971 10:57:04.612418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
17972 10:57:04.612849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
17974 10:57:04.665859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
17975 10:57:04.666284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
17977 10:57:04.719645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
17978 10:57:04.720057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
17980 10:57:04.773229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
17981 10:57:04.773653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
17983 10:57:04.827397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
17984 10:57:04.827782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
17986 10:57:04.881887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
17988 10:57:04.882340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
17989 10:57:04.935913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
17990 10:57:04.936332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
17992 10:57:04.989436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
17994 10:57:04.990006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
17995 10:57:05.043870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
17997 10:57:05.044155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
17998 10:57:05.096844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18000 10:57:05.097283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
18001 10:57:05.150228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18002 10:57:05.150658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18004 10:57:05.205478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18005 10:57:05.205923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18007 10:57:05.260322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18009 10:57:05.260767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18010 10:57:05.313569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18011 10:57:05.314007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18013 10:57:05.367978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18014 10:57:05.368401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18016 10:57:05.421149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18017 10:57:05.421529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18019 10:57:05.470428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18021 10:57:05.473860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18022 10:57:05.517990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18023 10:57:05.518417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18025 10:57:05.561740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18026 10:57:05.562197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18028 10:57:05.610348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18030 10:57:05.610872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18031 10:57:05.648547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18032 10:57:05.648994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18034 10:57:05.698939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18036 10:57:05.699426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18037 10:57:05.760263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18038 10:57:05.760700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18040 10:57:05.815792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18042 10:57:05.816265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18043 10:57:05.851924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18044 10:57:05.852352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18046 10:57:05.905398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18047 10:57:05.905853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18049 10:57:05.958619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18051 10:57:05.959057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18052 10:57:06.003334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18053 10:57:06.003780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18055 10:57:06.039934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18056 10:57:06.040322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18058 10:57:06.089621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18059 10:57:06.090063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18061 10:57:06.135723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18063 10:57:06.136176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18064 10:57:06.179129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18065 10:57:06.179567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18067 10:57:06.214985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18068 10:57:06.215378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18070 10:57:06.251096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18071 10:57:06.251549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18073 10:57:06.288217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18075 10:57:06.288685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18076 10:57:06.324817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18077 10:57:06.325270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18079 10:57:06.361024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18081 10:57:06.361408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18082 10:57:06.409212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18084 10:57:06.409653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18085 10:57:06.459390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18086 10:57:06.459819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18088 10:57:06.508316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18089 10:57:06.508745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18091 10:57:06.550427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18093 10:57:06.550844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18094 10:57:06.592466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18095 10:57:06.592899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18097 10:57:06.641254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18098 10:57:06.641689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18100 10:57:06.696919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18102 10:57:06.697357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18103 10:57:06.750039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18104 10:57:06.750473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18106 10:57:06.804156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18107 10:57:06.804566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18109 10:57:06.857578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18110 10:57:06.857973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18112 10:57:06.911595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18113 10:57:06.911981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18115 10:57:06.965227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18116 10:57:06.965611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18118 10:57:07.002322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18120 10:57:07.002745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18121 10:57:07.051901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18122 10:57:07.052332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18124 10:57:07.099862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18126 10:57:07.100323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18127 10:57:07.149373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18128 10:57:07.149800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18130 10:57:07.199610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18131 10:57:07.200036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18133 10:57:07.245603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18134 10:57:07.246040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18136 10:57:07.295948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18138 10:57:07.296415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18139 10:57:07.339577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18141 10:57:07.340194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18142 10:57:07.388261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18143 10:57:07.388711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18145 10:57:07.436793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18146 10:57:07.437218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18148 10:57:07.476009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18150 10:57:07.476478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18151 10:57:07.526024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18152 10:57:07.526413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18154 10:57:07.575643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18155 10:57:07.576031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18157 10:57:07.615655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18159 10:57:07.616117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18160 10:57:07.664756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18161 10:57:07.665181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18163 10:57:07.714432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18165 10:57:07.714905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18166 10:57:07.763679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18168 10:57:07.764070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18169 10:57:07.811994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18170 10:57:07.812394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18172 10:57:07.860064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18174 10:57:07.860545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18175 10:57:07.904024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18176 10:57:07.904459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18178 10:57:07.952332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18179 10:57:07.952704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18181 10:57:08.000614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18182 10:57:08.000971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18184 10:57:08.049004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18186 10:57:08.049349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18187 10:57:08.097383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18188 10:57:08.097786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18190 10:57:08.145553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18191 10:57:08.145883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18193 10:57:08.193979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18194 10:57:08.194349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18196 10:57:08.244014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18197 10:57:08.244327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18199 10:57:08.291891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18200 10:57:08.292191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18202 10:57:08.339196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18204 10:57:08.339658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18205 10:57:08.387652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18206 10:57:08.388083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18208 10:57:08.436796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18209 10:57:08.437236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18211 10:57:08.485976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18212 10:57:08.486397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18214 10:57:08.533080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18216 10:57:08.533409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18217 10:57:08.581297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18218 10:57:08.581600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18220 10:57:08.631971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18221 10:57:08.632275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18223 10:57:08.685384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18225 10:57:08.685700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18226 10:57:08.735905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18227 10:57:08.736254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18229 10:57:08.784338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18230 10:57:08.784706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18232 10:57:08.824252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18234 10:57:08.824757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18235 10:57:08.873879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18236 10:57:08.874331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18238 10:57:08.925610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18239 10:57:08.926066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18241 10:57:08.980007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18242 10:57:08.980436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18244 10:57:09.033454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18245 10:57:09.033900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18247 10:57:09.088629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18248 10:57:09.088981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18250 10:57:09.142976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18251 10:57:09.143402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18253 10:57:09.196484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18254 10:57:09.196893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18256 10:57:09.250029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18258 10:57:09.250472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18259 10:57:09.304418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18261 10:57:09.304862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18262 10:57:09.357709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18264 10:57:09.358165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18265 10:57:09.401673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18266 10:57:09.402128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18268 10:57:09.447518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18269 10:57:09.447927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18271 10:57:09.492989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18273 10:57:09.493374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18274 10:57:09.536330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18275 10:57:09.536733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18277 10:57:09.577251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18278 10:57:09.577678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18280 10:57:09.622404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18282 10:57:09.622788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18283 10:57:09.667182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18284 10:57:09.667587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18286 10:57:09.712285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18287 10:57:09.712642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18289 10:57:09.757942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18290 10:57:09.758368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18292 10:57:09.803583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18293 10:57:09.803986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18295 10:57:09.847919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18297 10:57:09.848283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18298 10:57:09.881407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18299 10:57:09.881839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18301 10:57:09.927688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18303 10:57:09.928107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18304 10:57:09.972730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18305 10:57:09.973158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18307 10:57:10.017059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18309 10:57:10.017463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18310 10:57:10.061417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18312 10:57:10.061850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18313 10:57:10.105356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18314 10:57:10.105748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18316 10:57:10.148436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18317 10:57:10.148851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18319 10:57:10.193555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18321 10:57:10.194164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18322 10:57:10.239134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18323 10:57:10.239557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18325 10:57:10.283884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18326 10:57:10.284291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18328 10:57:10.321456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18330 10:57:10.321910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18331 10:57:10.366112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18332 10:57:10.366535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18334 10:57:10.414951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18335 10:57:10.415391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18337 10:57:10.460989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18338 10:57:10.461405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18340 10:57:10.505872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18341 10:57:10.506381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18343 10:57:10.551345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18344 10:57:10.551789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18346 10:57:10.595882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18347 10:57:10.596322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18349 10:57:10.640406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18350 10:57:10.640842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18352 10:57:10.684335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18353 10:57:10.684817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18355 10:57:10.729337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18356 10:57:10.729686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18358 10:57:10.775577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18359 10:57:10.775998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18361 10:57:10.820635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18362 10:57:10.821021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18364 10:57:10.876171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18366 10:57:10.876623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18367 10:57:10.929544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18368 10:57:10.930005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18370 10:57:10.975166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18372 10:57:10.975621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18373 10:57:11.019732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18374 10:57:11.020149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18376 10:57:11.064937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18377 10:57:11.065352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18379 10:57:11.110410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18381 10:57:11.110775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18382 10:57:11.143532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18383 10:57:11.143998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18385 10:57:11.188688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18386 10:57:11.189236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18388 10:57:11.235566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18389 10:57:11.235988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18391 10:57:11.281681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18392 10:57:11.282100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18394 10:57:11.315562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18396 10:57:11.316023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18397 10:57:11.355544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18398 10:57:11.355959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18400 10:57:11.402212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18401 10:57:11.402668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18403 10:57:11.439999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18404 10:57:11.440424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18406 10:57:11.479251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18407 10:57:11.479617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18409 10:57:11.523808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18410 10:57:11.524247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18412 10:57:11.568754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18413 10:57:11.569160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18415 10:57:11.613972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18417 10:57:11.614418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18418 10:57:11.655600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18420 10:57:11.655962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18421 10:57:11.700805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18422 10:57:11.701194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18424 10:57:11.745808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18425 10:57:11.746244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18427 10:57:11.791699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18428 10:57:11.792120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18430 10:57:11.836469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18431 10:57:11.836925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18433 10:57:11.880596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18435 10:57:11.881055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18436 10:57:11.927758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18437 10:57:11.928224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18439 10:57:11.973424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18440 10:57:11.973849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18442 10:57:12.019419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18443 10:57:12.019856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18445 10:57:12.063919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18446 10:57:12.064350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18448 10:57:12.108740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18449 10:57:12.109177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18451 10:57:12.154330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18453 10:57:12.154688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18454 10:57:12.197853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18455 10:57:12.198214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18457 10:57:12.242482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18459 10:57:12.242934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18460 10:57:12.287294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18461 10:57:12.287695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18463 10:57:12.332110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18465 10:57:12.332555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18466 10:57:12.377036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18468 10:57:12.377443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18469 10:57:12.421462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18471 10:57:12.421926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18472 10:57:12.465449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18473 10:57:12.465884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18475 10:57:12.510459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18476 10:57:12.510885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18478 10:57:12.552652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18479 10:57:12.553041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18481 10:57:12.597812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18482 10:57:12.598159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18484 10:57:12.643089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18486 10:57:12.643514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18487 10:57:12.688125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18488 10:57:12.688545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18490 10:57:12.732180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18492 10:57:12.732630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18493 10:57:12.776248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18494 10:57:12.776661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18496 10:57:12.820732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18498 10:57:12.821173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18499 10:57:12.865079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18500 10:57:12.865497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18502 10:57:12.899949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18503 10:57:12.900370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18505 10:57:12.943350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18507 10:57:12.943827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18508 10:57:12.984640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18510 10:57:12.985113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18511 10:57:13.028974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18512 10:57:13.029414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18514 10:57:13.073485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18515 10:57:13.073931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18517 10:57:13.117882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18518 10:57:13.118319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18520 10:57:13.162342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18522 10:57:13.162787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18523 10:57:13.207183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18524 10:57:13.207567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18526 10:57:13.251024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18527 10:57:13.251385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18529 10:57:13.294962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18530 10:57:13.295366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18532 10:57:13.338477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18534 10:57:13.338949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18535 10:57:13.383223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18536 10:57:13.383655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18538 10:57:13.428592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18540 10:57:13.429011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18541 10:57:13.473264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18542 10:57:13.473696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18544 10:57:13.517665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18545 10:57:13.518118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18547 10:57:13.559235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18548 10:57:13.559633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18550 10:57:13.603953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18551 10:57:13.604377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18553 10:57:13.648293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18554 10:57:13.648748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18556 10:57:13.693395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18557 10:57:13.694248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18559 10:57:13.738416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18561 10:57:13.738878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18562 10:57:13.784662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18564 10:57:13.785108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18565 10:57:13.830329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18567 10:57:13.830775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18568 10:57:13.876393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18569 10:57:13.876787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18571 10:57:13.921505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18572 10:57:13.921926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18574 10:57:13.967630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18575 10:57:13.968047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18577 10:57:14.013455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18578 10:57:14.013893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18580 10:57:14.058400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18582 10:57:14.058862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18583 10:57:14.103935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18584 10:57:14.104308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18586 10:57:14.148487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18588 10:57:14.148927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18589 10:57:14.192881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18590 10:57:14.193338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18592 10:57:14.238957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18593 10:57:14.239386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18595 10:57:14.283501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18596 10:57:14.283929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18598 10:57:14.328405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18599 10:57:14.328837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18601 10:57:14.373170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18602 10:57:14.373609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18604 10:57:14.417466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18605 10:57:14.417917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18607 10:57:14.461753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18608 10:57:14.462161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18610 10:57:14.507628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18611 10:57:14.508084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18613 10:57:14.553007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18615 10:57:14.553468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18616 10:57:14.597711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18617 10:57:14.598169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18619 10:57:14.641812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18620 10:57:14.642257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18622 10:57:14.684963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18623 10:57:14.685393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18625 10:57:14.729920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18626 10:57:14.730458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18628 10:57:14.775370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18629 10:57:14.775797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18631 10:57:14.819681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18632 10:57:14.820099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18634 10:57:14.865323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18636 10:57:14.865747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18637 10:57:14.909777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18638 10:57:14.910191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18640 10:57:14.955335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18641 10:57:14.955749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18643 10:57:15.000657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18645 10:57:15.001098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18646 10:57:15.045712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18647 10:57:15.046092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18649 10:57:15.090114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18650 10:57:15.092062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18652 10:57:15.134548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18654 10:57:15.135017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18655 10:57:15.179676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18657 10:57:15.180153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18658 10:57:15.224893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18659 10:57:15.225332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18661 10:57:15.270108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18662 10:57:15.270538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18664 10:57:15.314408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18666 10:57:15.314952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18667 10:57:15.359372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18668 10:57:15.359906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18670 10:57:15.403340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18671 10:57:15.403780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18673 10:57:15.447487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18674 10:57:15.448023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18676 10:57:15.493536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18677 10:57:15.493988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18679 10:57:15.539104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18681 10:57:15.539524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18682 10:57:15.583849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18684 10:57:15.584290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18685 10:57:15.628778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18686 10:57:15.629208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18688 10:57:15.673037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18689 10:57:15.673479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18691 10:57:15.717728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18692 10:57:15.718368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18694 10:57:15.761792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18696 10:57:15.762258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18697 10:57:15.806285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18699 10:57:15.806743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18700 10:57:15.850959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18701 10:57:15.851415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18703 10:57:15.896221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18705 10:57:15.896709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18706 10:57:15.941515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18707 10:57:15.941949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18709 10:57:15.993169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18710 10:57:15.993577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18712 10:57:16.050169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18713 10:57:16.050610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18715 10:57:16.095326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18716 10:57:16.095888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18718 10:57:16.139185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18719 10:57:16.140521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18721 10:57:16.182861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18722 10:57:16.183313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18724 10:57:16.228114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18725 10:57:16.228536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18727 10:57:16.272371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18728 10:57:16.272805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18730 10:57:16.317526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18731 10:57:16.317965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18733 10:57:16.362824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18734 10:57:16.363206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18736 10:57:16.407426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18737 10:57:16.407843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18739 10:57:16.451828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18741 10:57:16.452254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18742 10:57:16.495591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18743 10:57:16.495973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18745 10:57:16.540429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18746 10:57:16.540851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18748 10:57:16.584097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18749 10:57:16.584576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18751 10:57:16.624413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18752 10:57:16.624826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18754 10:57:16.669129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18755 10:57:16.669544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18757 10:57:16.714490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18759 10:57:16.714953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18760 10:57:16.760257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18761 10:57:16.760641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18763 10:57:16.812074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18765 10:57:16.812411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18766 10:57:16.859756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18768 10:57:16.860066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18769 10:57:16.907992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18770 10:57:16.908403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18772 10:57:16.957437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18773 10:57:16.957774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18775 10:57:17.006381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18777 10:57:17.006618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18778 10:57:17.058873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18779 10:57:17.059268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18781 10:57:17.107367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18782 10:57:17.107778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18784 10:57:17.155380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18785 10:57:17.155814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18787 10:57:17.204877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18789 10:57:17.205316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18790 10:57:17.252392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18791 10:57:17.252829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18793 10:57:17.297877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18795 10:57:17.298338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18796 10:57:17.341367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18797 10:57:17.341754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18799 10:57:17.385861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18800 10:57:17.386213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18802 10:57:17.431134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18803 10:57:17.431537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18805 10:57:17.475811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18806 10:57:17.476243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18808 10:57:17.520148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18810 10:57:17.520595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18811 10:57:17.563949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18812 10:57:17.564375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18814 10:57:17.607545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18815 10:57:17.607982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18817 10:57:17.652207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18818 10:57:17.652636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18820 10:57:17.696577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18821 10:57:17.696996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18823 10:57:17.737298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18824 10:57:17.737686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18826 10:57:17.783311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18828 10:57:17.783788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18829 10:57:17.827754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18830 10:57:17.828169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18832 10:57:17.867935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18833 10:57:17.868338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18835 10:57:17.913105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18836 10:57:17.913561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18838 10:57:17.957458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18839 10:57:17.957885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18841 10:57:18.001721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18842 10:57:18.002113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18844 10:57:18.045592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18845 10:57:18.046020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18847 10:57:18.088408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18848 10:57:18.088837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18850 10:57:18.131549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18852 10:57:18.131983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18853 10:57:18.166791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18854 10:57:18.167231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18856 10:57:18.206993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18858 10:57:18.207352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18859 10:57:18.252406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18860 10:57:18.252779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18862 10:57:18.295017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18863 10:57:18.295400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18865 10:57:18.340609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18866 10:57:18.341676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18868 10:57:18.388295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18869 10:57:18.388663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18871 10:57:18.432841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18873 10:57:18.433292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18874 10:57:18.486505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18876 10:57:18.486981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18877 10:57:18.543593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18878 10:57:18.544020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18880 10:57:18.590482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18882 10:57:18.590931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18883 10:57:18.633465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18885 10:57:18.633910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18886 10:57:18.679872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18887 10:57:18.680304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18889 10:57:18.726384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18891 10:57:18.726759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18892 10:57:18.774847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18893 10:57:18.775236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18895 10:57:18.819590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18896 10:57:18.820021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18898 10:57:18.869018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18900 10:57:18.869476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18901 10:57:18.920896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18902 10:57:18.921320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18904 10:57:18.969556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18905 10:57:18.969996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18907 10:57:19.020515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18908 10:57:19.020948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18910 10:57:19.067038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18911 10:57:19.067451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18913 10:57:19.111749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18914 10:57:19.112171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18916 10:57:19.157461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18917 10:57:19.157848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18919 10:57:19.198107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18920 10:57:19.198567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18922 10:57:19.245918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18923 10:57:19.246368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18925 10:57:19.291014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18926 10:57:19.291447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18928 10:57:19.337673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18930 10:57:19.338157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18931 10:57:19.384661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18932 10:57:19.385095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18934 10:57:19.419529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18936 10:57:19.420004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18937 10:57:19.465933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18939 10:57:19.466361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18940 10:57:19.508088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18941 10:57:19.508521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18943 10:57:19.555705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18944 10:57:19.556131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18946 10:57:19.603332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18947 10:57:19.603763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18949 10:57:19.649560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18950 10:57:19.649989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18952 10:57:19.695813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18953 10:57:19.696239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18955 10:57:19.743702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18956 10:57:19.744115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18958 10:57:19.789147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18959 10:57:19.789549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18961 10:57:19.835762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18962 10:57:19.836169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18964 10:57:19.882780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18965 10:57:19.883194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18967 10:57:19.928304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18968 10:57:19.928727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
18970 10:57:19.976413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
18971 10:57:19.976855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
18973 10:57:20.023214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
18974 10:57:20.023637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
18976 10:57:20.069453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
18977 10:57:20.069881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
18979 10:57:20.116370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
18980 10:57:20.116776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
18982 10:57:20.155512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
18984 10:57:20.155973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
18985 10:57:20.190561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
18987 10:57:20.191000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
18988 10:57:20.235735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
18989 10:57:20.236081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
18991 10:57:20.280396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
18992 10:57:20.280822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
18994 10:57:20.327268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
18996 10:57:20.327722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
18997 10:57:20.365218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
18998 10:57:20.365636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
19000 10:57:20.398870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19001 10:57:20.399289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19003 10:57:20.431292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19004 10:57:20.431671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19006 10:57:20.464876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19007 10:57:20.465283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19009 10:57:20.498430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19011 10:57:20.498875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19012 10:57:20.532720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19014 10:57:20.533169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19015 10:57:20.571896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19016 10:57:20.572326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19018 10:57:20.615876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19019 10:57:20.616304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19021 10:57:20.663613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19022 10:57:20.663997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19024 10:57:20.710334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19026 10:57:20.710796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19027 10:57:20.755944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19028 10:57:20.756366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19030 10:57:20.800628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19031 10:57:20.801052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19033 10:57:20.839810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19034 10:57:20.840241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19036 10:57:20.887066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19038 10:57:20.887536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19039 10:57:20.933370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19040 10:57:20.933759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19042 10:57:20.978368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19044 10:57:20.978789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19045 10:57:21.024987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19046 10:57:21.025400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19048 10:57:21.074245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19049 10:57:21.074657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19051 10:57:21.153188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19052 10:57:21.153658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19054 10:57:21.204930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19055 10:57:21.205346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19057 10:57:21.251385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19058 10:57:21.251789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19060 10:57:21.289183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19061 10:57:21.289586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19063 10:57:21.327494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19064 10:57:21.327911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19066 10:57:21.365516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19068 10:57:21.366008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19069 10:57:21.401756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19071 10:57:21.402163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19072 10:57:21.447135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19073 10:57:21.447516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19075 10:57:21.488937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19076 10:57:21.489387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19078 10:57:21.535710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19079 10:57:21.536132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19081 10:57:21.585609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19082 10:57:21.586075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19084 10:57:21.627400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19086 10:57:21.627895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19087 10:57:21.666534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19089 10:57:21.667012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19090 10:57:21.705735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19091 10:57:21.706207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19093 10:57:21.752405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19094 10:57:21.752819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19096 10:57:21.797813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19097 10:57:21.798231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19099 10:57:21.841951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19100 10:57:21.842373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19102 10:57:21.887484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19103 10:57:21.887928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19105 10:57:21.935467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19106 10:57:21.935860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19108 10:57:21.970157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19110 10:57:21.970774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19111 10:57:22.015915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19112 10:57:22.016304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19114 10:57:22.061019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19115 10:57:22.061444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19117 10:57:22.103420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19118 10:57:22.103851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19120 10:57:22.149666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19121 10:57:22.150071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19123 10:57:22.195680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19124 10:57:22.196031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19126 10:57:22.240880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19127 10:57:22.241275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19129 10:57:22.288887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19130 10:57:22.289244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19132 10:57:22.332250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19133 10:57:22.332636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19135 10:57:22.377131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19136 10:57:22.377529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19138 10:57:22.426919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19139 10:57:22.427322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19141 10:57:22.470045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19143 10:57:22.470462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19144 10:57:22.511388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19145 10:57:22.511791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19147 10:57:22.556026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19148 10:57:22.556444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19150 10:57:22.597312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19151 10:57:22.597692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19153 10:57:22.641224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19154 10:57:22.641635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19156 10:57:22.686773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19157 10:57:22.687151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19159 10:57:22.728929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19160 10:57:22.729302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19162 10:57:22.773864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19163 10:57:22.774224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19165 10:57:22.817303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19166 10:57:22.817667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19168 10:57:22.856953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19169 10:57:22.857350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19171 10:57:22.900717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19172 10:57:22.901116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19174 10:57:22.946329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19176 10:57:22.946687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19177 10:57:22.992100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19178 10:57:22.992495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19180 10:57:23.036669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19182 10:57:23.037088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19183 10:57:23.081623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19185 10:57:23.082037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19186 10:57:23.128030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19187 10:57:23.128383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19189 10:57:23.167632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19191 10:57:23.168013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19192 10:57:23.213000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19193 10:57:23.213387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19195 10:57:23.256883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19196 10:57:23.257297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19198 10:57:23.302043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19199 10:57:23.302494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19201 10:57:23.347373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19202 10:57:23.347749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19204 10:57:23.391582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19205 10:57:23.391993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19207 10:57:23.436354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19208 10:57:23.436763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19210 10:57:23.480175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19211 10:57:23.480597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19213 10:57:23.514772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19214 10:57:23.515169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19216 10:57:23.553442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19217 10:57:23.553825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19219 10:57:23.596460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19220 10:57:23.596848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19222 10:57:23.636852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19223 10:57:23.637256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19225 10:57:23.683034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19227 10:57:23.683487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19228 10:57:23.727226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19230 10:57:23.727665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19231 10:57:23.776598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19232 10:57:23.777014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19234 10:57:23.815994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19235 10:57:23.816401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19237 10:57:23.851526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19238 10:57:23.851937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19240 10:57:23.900701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19241 10:57:23.901109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19243 10:57:23.953137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19244 10:57:23.953555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19246 10:57:24.012252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19248 10:57:24.012682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19249 10:57:24.060761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19250 10:57:24.061167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19252 10:57:24.099573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19253 10:57:24.099990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19255 10:57:24.135440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19257 10:57:24.135814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19258 10:57:24.177644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19259 10:57:24.178061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19261 10:57:24.223651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19262 10:57:24.224063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19264 10:57:24.268925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19265 10:57:24.269354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19267 10:57:24.313588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19268 10:57:24.314000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19270 10:57:24.358918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19271 10:57:24.359335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19273 10:57:24.405869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19275 10:57:24.406330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19276 10:57:24.449432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19277 10:57:24.449866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19279 10:57:24.495310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19280 10:57:24.495742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19282 10:57:24.535402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19283 10:57:24.535827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19285 10:57:24.573667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19286 10:57:24.574073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19288 10:57:24.611428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19289 10:57:24.611817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19291 10:57:24.655076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19292 10:57:24.655468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19294 10:57:24.687644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19295 10:57:24.688055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19297 10:57:24.732641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19299 10:57:24.733021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19300 10:57:24.777196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19301 10:57:24.777615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19303 10:57:24.823510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19304 10:57:24.823922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19306 10:57:24.868985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19307 10:57:24.869401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19309 10:57:24.914302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19310 10:57:24.914731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19312 10:57:24.959745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19314 10:57:24.960232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19315 10:57:25.004262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19316 10:57:25.004612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19318 10:57:25.047907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19320 10:57:25.048387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19321 10:57:25.092315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19322 10:57:25.092723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19324 10:57:25.136946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19325 10:57:25.137379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19327 10:57:25.184629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19328 10:57:25.185066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19330 10:57:25.230470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19332 10:57:25.230962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19333 10:57:25.276235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19335 10:57:25.276664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19336 10:57:25.319723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19337 10:57:25.320105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19339 10:57:25.366324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19341 10:57:25.366752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19342 10:57:25.408659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19344 10:57:25.409084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19345 10:57:25.453062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19346 10:57:25.453464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19348 10:57:25.497956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19349 10:57:25.498360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19351 10:57:25.543398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19352 10:57:25.543767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19354 10:57:25.585854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19355 10:57:25.586258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19357 10:57:25.627867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19358 10:57:25.628276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19360 10:57:25.666346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19362 10:57:25.666769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19363 10:57:25.701497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19364 10:57:25.701907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19366 10:57:25.745872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19367 10:57:25.746290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19369 10:57:25.790819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19370 10:57:25.791232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19372 10:57:25.835057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19373 10:57:25.835475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19375 10:57:25.878833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19377 10:57:25.879276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19378 10:57:25.923747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19379 10:57:25.924160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19381 10:57:25.969432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19382 10:57:25.969876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19384 10:57:26.018000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19385 10:57:26.018426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19387 10:57:26.065965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19388 10:57:26.066375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19390 10:57:26.104310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19391 10:57:26.104714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19393 10:57:26.149813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19394 10:57:26.150222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19396 10:57:26.195691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19397 10:57:26.196115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19399 10:57:26.263767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19400 10:57:26.264193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19402 10:57:26.313144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19403 10:57:26.313574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19405 10:57:26.361596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19406 10:57:26.361993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19408 10:57:26.410877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19409 10:57:26.411268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19411 10:57:26.459547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19412 10:57:26.459939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19414 10:57:26.505768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19415 10:57:26.506165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19417 10:57:26.553536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19418 10:57:26.553958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19420 10:57:26.603441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19421 10:57:26.603851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19423 10:57:26.653257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19424 10:57:26.653673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19426 10:57:26.703123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19427 10:57:26.703553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19429 10:57:26.752559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19431 10:57:26.753020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19432 10:57:26.801655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19433 10:57:26.802081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19435 10:57:26.849663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19436 10:57:26.850087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19438 10:57:26.897169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19439 10:57:26.897558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19441 10:57:26.947112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19442 10:57:26.947539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19444 10:57:26.995306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19445 10:57:26.995738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19447 10:57:27.043504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19448 10:57:27.043934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19450 10:57:27.092118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19452 10:57:27.092500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19453 10:57:27.139463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19455 10:57:27.139885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19456 10:57:27.187707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19457 10:57:27.188102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19459 10:57:27.225856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19461 10:57:27.226300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19462 10:57:27.265688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19463 10:57:27.266085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19465 10:57:27.309885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19467 10:57:27.310342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19468 10:57:27.354049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19469 10:57:27.354490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19471 10:57:27.399027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19472 10:57:27.399453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19474 10:57:27.443753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19476 10:57:27.444214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19477 10:57:27.488678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19478 10:57:27.489103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19480 10:57:27.534843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19481 10:57:27.535271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19483 10:57:27.579676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19484 10:57:27.580110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19486 10:57:27.625598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19487 10:57:27.626033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19489 10:57:27.673171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19490 10:57:27.673604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19492 10:57:27.719710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19493 10:57:27.720156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19495 10:57:27.765794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19496 10:57:27.766226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19498 10:57:27.812669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19499 10:57:27.813103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19501 10:57:27.858422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19503 10:57:27.858897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19504 10:57:27.904989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19506 10:57:27.905457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19507 10:57:27.952034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19509 10:57:27.952520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19510 10:57:27.996878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19511 10:57:27.997299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19513 10:57:28.040120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19514 10:57:28.040541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19516 10:57:28.084725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19517 10:57:28.085141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19519 10:57:28.117046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19520 10:57:28.117424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19522 10:57:28.157898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19524 10:57:28.158384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19525 10:57:28.203473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19526 10:57:28.203843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19528 10:57:28.247506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19529 10:57:28.247930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19531 10:57:28.293579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19532 10:57:28.294018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19534 10:57:28.339788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19535 10:57:28.340221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19537 10:57:28.385802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19538 10:57:28.386236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19540 10:57:28.432543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19542 10:57:28.432988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19543 10:57:28.475602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19544 10:57:28.476023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19546 10:57:28.520459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19547 10:57:28.520881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19549 10:57:28.560387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19551 10:57:28.560857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19552 10:57:28.604663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19554 10:57:28.605124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19555 10:57:28.651603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19557 10:57:28.652066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19558 10:57:28.704474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19559 10:57:28.704925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19561 10:57:28.761317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19562 10:57:28.761750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19564 10:57:28.801251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19565 10:57:28.801689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19567 10:57:28.835911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19569 10:57:28.836356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19570 10:57:28.874458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19572 10:57:28.874952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19573 10:57:28.916910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19575 10:57:28.917386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19576 10:57:28.958535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19578 10:57:28.959101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19579 10:57:29.005009 <47>[ 200.389762] systemd-journald[109]: Sent WATCHDOG=1 notification.
19580 10:57:29.012889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19581 10:57:29.013266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19583 10:57:29.047733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19584 10:57:29.048116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19586 10:57:29.084832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19587 10:57:29.085225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19589 10:57:29.125287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19591 10:57:29.125787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19592 10:57:29.170424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19594 10:57:29.170908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19595 10:57:29.217706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19597 10:57:29.218184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19598 10:57:29.265600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19599 10:57:29.266054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19601 10:57:29.313957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19602 10:57:29.314392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19604 10:57:29.360179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19605 10:57:29.360601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19607 10:57:29.408857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19608 10:57:29.409261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19610 10:57:29.458176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19612 10:57:29.458623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19613 10:57:29.501274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19614 10:57:29.501689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19616 10:57:29.548972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19618 10:57:29.549381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19619 10:57:29.594114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19620 10:57:29.594471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19622 10:57:29.640978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19624 10:57:29.641434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19625 10:57:29.689378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19627 10:57:29.689792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19628 10:57:29.737504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19629 10:57:29.737895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19631 10:57:29.784657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19632 10:57:29.785039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19634 10:57:29.832288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19635 10:57:29.832711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19637 10:57:29.881198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19638 10:57:29.881584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19640 10:57:29.928873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19642 10:57:29.929342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19643 10:57:29.975895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19644 10:57:29.976334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19646 10:57:30.024604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19647 10:57:30.025031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19649 10:57:30.072783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19650 10:57:30.073216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19652 10:57:30.120850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19653 10:57:30.121278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19655 10:57:30.168056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19656 10:57:30.168435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19658 10:57:30.215748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19659 10:57:30.216156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19661 10:57:30.263900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19662 10:57:30.264316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19664 10:57:30.312201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19665 10:57:30.312589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19667 10:57:30.354750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19668 10:57:30.355182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19670 10:57:30.397930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19671 10:57:30.398329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19673 10:57:30.443309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19674 10:57:30.443740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19676 10:57:30.484474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19678 10:57:30.484914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19679 10:57:30.523601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19681 10:57:30.524053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19682 10:57:30.566878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19683 10:57:30.567309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19685 10:57:30.612970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19686 10:57:30.613393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19688 10:57:30.656069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19690 10:57:30.656683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19691 10:57:30.696706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19692 10:57:30.697136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19694 10:57:30.745142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19695 10:57:30.745566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19697 10:57:30.792998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19698 10:57:30.793449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19700 10:57:30.837837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19701 10:57:30.838272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19703 10:57:30.879772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19704 10:57:30.880170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19706 10:57:30.912387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19707 10:57:30.912800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19709 10:57:30.948869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19710 10:57:30.949299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19712 10:57:31.000103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19714 10:57:31.000563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19715 10:57:31.042886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19716 10:57:31.043351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19718 10:57:31.081699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19719 10:57:31.082124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19721 10:57:31.128195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19722 10:57:31.128607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19724 10:57:31.173077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19726 10:57:31.173539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19727 10:57:31.221070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19728 10:57:31.221503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19730 10:57:31.268287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19731 10:57:31.268695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19733 10:57:31.316036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19734 10:57:31.316458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19736 10:57:31.385927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19737 10:57:31.386354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19739 10:57:31.435628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19740 10:57:31.436056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19742 10:57:31.484718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19743 10:57:31.485139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19745 10:57:31.532749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19746 10:57:31.533180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19748 10:57:31.581016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19749 10:57:31.581418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19751 10:57:31.631469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19752 10:57:31.631883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19754 10:57:31.679200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19756 10:57:31.679610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19757 10:57:31.726787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19758 10:57:31.727218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19760 10:57:31.776588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19761 10:57:31.776995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19763 10:57:31.824762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19764 10:57:31.825171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19766 10:57:31.859191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19767 10:57:31.859633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19769 10:57:31.903149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19770 10:57:31.903571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19772 10:57:31.948276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19774 10:57:31.948711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19775 10:57:31.988626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19776 10:57:31.989044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19778 10:57:32.033233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19780 10:57:32.033705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19781 10:57:32.077000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19782 10:57:32.077427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19784 10:57:32.124020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19785 10:57:32.124444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19787 10:57:32.169619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19788 10:57:32.170052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19790 10:57:32.203486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19792 10:57:32.203951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19793 10:57:32.248764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19794 10:57:32.249190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19796 10:57:32.295602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19797 10:57:32.296032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19799 10:57:32.342211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19801 10:57:32.342696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19802 10:57:32.387803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19803 10:57:32.388220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19805 10:57:32.429387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19806 10:57:32.429812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19808 10:57:32.475507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19809 10:57:32.475940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19811 10:57:32.511399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19812 10:57:32.511825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19814 10:57:32.556519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19816 10:57:32.556971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19817 10:57:32.602468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19819 10:57:32.602914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19820 10:57:32.644684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19821 10:57:32.645109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19823 10:57:32.689073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19825 10:57:32.689511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19826 10:57:32.732869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19827 10:57:32.733284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19829 10:57:32.778814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19831 10:57:32.779261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19832 10:57:32.823904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19834 10:57:32.824374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19835 10:57:32.868521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19837 10:57:32.868966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19838 10:57:32.914266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19840 10:57:32.914758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19841 10:57:32.961350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19842 10:57:32.961800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19844 10:57:33.012408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19845 10:57:33.012828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19847 10:57:33.060293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19849 10:57:33.060732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19850 10:57:33.109073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19851 10:57:33.109449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19853 10:57:33.157036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19854 10:57:33.157445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19856 10:57:33.203958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19858 10:57:33.204409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19859 10:57:33.252330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19860 10:57:33.252730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19862 10:57:33.302107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19864 10:57:33.302555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19865 10:57:33.351620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19866 10:57:33.351997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19868 10:57:33.401840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19870 10:57:33.402287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19871 10:57:33.449745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19872 10:57:33.450180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19874 10:57:33.500008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19875 10:57:33.500405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19877 10:57:33.549437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19879 10:57:33.549929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19880 10:57:33.598058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19882 10:57:33.598489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19883 10:57:33.646513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19885 10:57:33.647075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19886 10:57:33.696133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19888 10:57:33.696589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19889 10:57:33.745923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19890 10:57:33.746343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19892 10:57:33.795034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19894 10:57:33.795481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19895 10:57:33.840787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19896 10:57:33.841179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19898 10:57:33.887717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19899 10:57:33.888121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19901 10:57:33.936094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19903 10:57:33.936543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19904 10:57:33.983635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19905 10:57:33.984052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19907 10:57:34.030054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19908 10:57:34.030444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19910 10:57:34.076723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19911 10:57:34.077103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19913 10:57:34.122962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19914 10:57:34.123327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19916 10:57:34.168963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19917 10:57:34.169365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19919 10:57:34.219942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19921 10:57:34.220394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19922 10:57:34.268421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19923 10:57:34.268831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19925 10:57:34.319306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19926 10:57:34.319716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19928 10:57:34.368176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19929 10:57:34.368590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19931 10:57:34.416624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19933 10:57:34.417060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19934 10:57:34.465591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19935 10:57:34.466016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19937 10:57:34.514974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19938 10:57:34.515359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19940 10:57:34.547260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19942 10:57:34.547720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19943 10:57:34.590813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19944 10:57:34.591260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19946 10:57:34.627512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19947 10:57:34.627944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19949 10:57:34.673107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19950 10:57:34.673539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19952 10:57:34.723807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19953 10:57:34.724226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19955 10:57:34.771858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19956 10:57:34.772267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19958 10:57:34.819345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19960 10:57:34.819784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19961 10:57:34.865702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19962 10:57:34.866135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19964 10:57:34.913065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19965 10:57:34.913492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19967 10:57:34.960143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19968 10:57:34.960582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19970 10:57:35.007895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
19971 10:57:35.008325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
19973 10:57:35.055129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
19975 10:57:35.055610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
19976 10:57:35.101087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
19977 10:57:35.101514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
19979 10:57:35.151011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
19980 10:57:35.151450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
19982 10:57:35.198572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
19984 10:57:35.199034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
19985 10:57:35.246032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
19986 10:57:35.246457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
19988 10:57:35.293176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
19989 10:57:35.293567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
19991 10:57:35.340077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
19992 10:57:35.340472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
19994 10:57:35.389557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
19995 10:57:35.389987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
19997 10:57:35.439494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
19999 10:57:35.439937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
20000 10:57:35.490537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20002 10:57:35.490963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
20003 10:57:35.539408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20004 10:57:35.539826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20006 10:57:35.588198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20007 10:57:35.588570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20009 10:57:35.636261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20010 10:57:35.636651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20012 10:57:35.683499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20013 10:57:35.683842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20015 10:57:35.730923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20016 10:57:35.731364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20018 10:57:35.782086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20019 10:57:35.782517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20021 10:57:35.832732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20022 10:57:35.833161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20024 10:57:35.882378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20026 10:57:35.882852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20027 10:57:35.931597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20028 10:57:35.932014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20030 10:57:35.980017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20031 10:57:35.980411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20033 10:57:36.029478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20034 10:57:36.029886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20036 10:57:36.079135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20037 10:57:36.079505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20039 10:57:36.126948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20040 10:57:36.127366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20042 10:57:36.169837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20043 10:57:36.170245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20045 10:57:36.216055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20046 10:57:36.216474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20048 10:57:36.256253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20049 10:57:36.256649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20051 10:57:36.301357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20053 10:57:36.301788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20054 10:57:36.346900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20055 10:57:36.347299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20057 10:57:36.392780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20059 10:57:36.393209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20060 10:57:36.439668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20061 10:57:36.440075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20063 10:57:36.505467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20064 10:57:36.505897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20066 10:57:36.553686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20067 10:57:36.554135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20069 10:57:36.601578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20070 10:57:36.601990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20072 10:57:36.649448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20073 10:57:36.649855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20075 10:57:36.699003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20076 10:57:36.699397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20078 10:57:36.746068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20079 10:57:36.746462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20081 10:57:36.793093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20082 10:57:36.793461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20084 10:57:36.840078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20085 10:57:36.840489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20087 10:57:36.887421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20088 10:57:36.887841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20090 10:57:36.934569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20092 10:57:36.934973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20093 10:57:36.981509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20094 10:57:36.981927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20096 10:57:37.028603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20097 10:57:37.029023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20099 10:57:37.074324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20101 10:57:37.074893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20102 10:57:37.119704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20103 10:57:37.120141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20105 10:57:37.166445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20107 10:57:37.166883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20108 10:57:37.211506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20109 10:57:37.211928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20111 10:57:37.256706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20113 10:57:37.257170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20114 10:57:37.295598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20116 10:57:37.296040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20117 10:57:37.338747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20118 10:57:37.339169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20120 10:57:37.383898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20121 10:57:37.384340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20123 10:57:37.429240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20124 10:57:37.429676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20126 10:57:37.475292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20127 10:57:37.475715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20129 10:57:37.515678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20130 10:57:37.516098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20132 10:57:37.560183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20133 10:57:37.560623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20135 10:57:37.604681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20137 10:57:37.605136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20138 10:57:37.649829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20140 10:57:37.650287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20141 10:57:37.693633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20142 10:57:37.694044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20144 10:57:37.738044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20145 10:57:37.738410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20147 10:57:37.775293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20148 10:57:37.775701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20150 10:57:37.820532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20151 10:57:37.820914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20153 10:57:37.857068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20155 10:57:37.857503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20156 10:57:37.891489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20157 10:57:37.891909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20159 10:57:37.925422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20160 10:57:37.925837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20162 10:57:37.959982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20164 10:57:37.960438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20165 10:57:37.997099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20166 10:57:37.997499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20168 10:57:38.033910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20169 10:57:38.034346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20171 10:57:38.074067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20173 10:57:38.074554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20174 10:57:38.115355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20175 10:57:38.115783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20177 10:57:38.160845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20178 10:57:38.161269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20180 10:57:38.200158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20181 10:57:38.200549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20183 10:57:38.237787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20185 10:57:38.238203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20186 10:57:38.283876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20187 10:57:38.284254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20189 10:57:38.329709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20191 10:57:38.330167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20192 10:57:38.365994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20193 10:57:38.366405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20195 10:57:38.400146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20196 10:57:38.400544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20198 10:57:38.436152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20199 10:57:38.436560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20201 10:57:38.473428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20202 10:57:38.473863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20204 10:57:38.521451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20205 10:57:38.521893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20207 10:57:38.569235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20209 10:57:38.569706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20210 10:57:38.614933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20211 10:57:38.615357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20213 10:57:38.661706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20215 10:57:38.662164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20216 10:57:38.711905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20217 10:57:38.712336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20219 10:57:38.758319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20221 10:57:38.758785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20222 10:57:38.803691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20223 10:57:38.804108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20225 10:57:38.852184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20226 10:57:38.852602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20228 10:57:38.900634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20229 10:57:38.905686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20231 10:57:38.949899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20233 10:57:38.950364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20234 10:57:39.007121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20236 10:57:39.007565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20237 10:57:39.061152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20238 10:57:39.061583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20240 10:57:39.098996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20241 10:57:39.099429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20243 10:57:39.135542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20245 10:57:39.136011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20246 10:57:39.172955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20248 10:57:39.173422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20249 10:57:39.216398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20250 10:57:39.216827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20252 10:57:39.261721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20253 10:57:39.262147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20255 10:57:39.306683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20256 10:57:39.307128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20258 10:57:39.352019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20259 10:57:39.352420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20261 10:57:39.397777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20262 10:57:39.398201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20264 10:57:39.444639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20266 10:57:39.445078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20267 10:57:39.490372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20269 10:57:39.490822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20270 10:57:39.536219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20271 10:57:39.536617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20273 10:57:39.581082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20275 10:57:39.581492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20276 10:57:39.625120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20277 10:57:39.625534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20279 10:57:39.668822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20281 10:57:39.669226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20282 10:57:39.713715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20284 10:57:39.714207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20285 10:57:39.760485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20286 10:57:39.760895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20288 10:57:39.805905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20289 10:57:39.806281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20291 10:57:39.852976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20292 10:57:39.853521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20294 10:57:39.896965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20295 10:57:39.897350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20297 10:57:39.938760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20298 10:57:39.939150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20300 10:57:39.982496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20302 10:57:39.982916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20303 10:57:40.027742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20304 10:57:40.028146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20306 10:57:40.073361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20307 10:57:40.073770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20309 10:57:40.120812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20311 10:57:40.121232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20312 10:57:40.166475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20314 10:57:40.166915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20315 10:57:40.211669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20316 10:57:40.212072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20318 10:57:40.256899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20319 10:57:40.257315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20321 10:57:40.302264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20323 10:57:40.302735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20324 10:57:40.348424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20326 10:57:40.348951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20327 10:57:40.388995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20328 10:57:40.389449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20330 10:57:40.432762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20331 10:57:40.433175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20333 10:57:40.468463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20334 10:57:40.468910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20336 10:57:40.507468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20337 10:57:40.507882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20339 10:57:40.552628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20340 10:57:40.553067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20342 10:57:40.596864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20344 10:57:40.597348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20345 10:57:40.643516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20346 10:57:40.643904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20348 10:57:40.688734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20349 10:57:40.689098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20351 10:57:40.733692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20352 10:57:40.734122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20354 10:57:40.780013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20355 10:57:40.780441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20357 10:57:40.829802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20358 10:57:40.830250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20360 10:57:40.868628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20361 10:57:40.869056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20363 10:57:40.915752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20364 10:57:40.916168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20366 10:57:40.962070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20367 10:57:40.962508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20369 10:57:41.010397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20371 10:57:41.010869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20372 10:57:41.055780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20373 10:57:41.056159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20375 10:57:41.100077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20376 10:57:41.100510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20378 10:57:41.143766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20379 10:57:41.144188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20381 10:57:41.189024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20382 10:57:41.189444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20384 10:57:41.234973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20385 10:57:41.235398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20387 10:57:41.280586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20388 10:57:41.281018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20390 10:57:41.324261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20391 10:57:41.324675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20393 10:57:41.368710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20394 10:57:41.369141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20396 10:57:41.412994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20397 10:57:41.413434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20399 10:57:41.457377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20401 10:57:41.457850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20402 10:57:41.501770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20403 10:57:41.502201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20405 10:57:41.547462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20406 10:57:41.547908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20408 10:57:41.608098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20409 10:57:41.608531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20411 10:57:41.657970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20412 10:57:41.658410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20414 10:57:41.703547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20415 10:57:41.703968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20417 10:57:41.748669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20418 10:57:41.749052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20420 10:57:41.792526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20422 10:57:41.792957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20423 10:57:41.836041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20424 10:57:41.836405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20426 10:57:41.881230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20427 10:57:41.881619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20429 10:57:41.925333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20430 10:57:41.925774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20432 10:57:41.971662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20433 10:57:41.972069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20435 10:57:42.014522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20437 10:57:42.014968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20438 10:57:42.059322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20439 10:57:42.059728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20441 10:57:42.103797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20442 10:57:42.104208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20444 10:57:42.147475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20445 10:57:42.147879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20447 10:57:42.192499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20448 10:57:42.192904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20450 10:57:42.237352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20451 10:57:42.237752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20453 10:57:42.282530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20455 10:57:42.282949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20456 10:57:42.328459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20457 10:57:42.328879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20459 10:57:42.371754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20461 10:57:42.372230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20462 10:57:42.424118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20464 10:57:42.424585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20465 10:57:42.474463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20467 10:57:42.475443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20468 10:57:42.526436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20470 10:57:42.526906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20471 10:57:42.576295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20472 10:57:42.576736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20474 10:57:42.609878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20476 10:57:42.610323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20477 10:57:42.643729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20478 10:57:42.644171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20480 10:57:42.679119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20482 10:57:42.679587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20483 10:57:42.725977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20484 10:57:42.726383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20486 10:57:42.773029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20488 10:57:42.773493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20489 10:57:42.815649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20490 10:57:42.816010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20492 10:57:42.859608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20493 10:57:42.860011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20495 10:57:42.893175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20497 10:57:42.893630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20498 10:57:42.939041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20499 10:57:42.939439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20501 10:57:42.984549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20502 10:57:42.984950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20504 10:57:43.030178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20506 10:57:43.030607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20507 10:57:43.068211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20508 10:57:43.068587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20510 10:57:43.105713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20511 10:57:43.106121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20513 10:57:43.141077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20515 10:57:43.141545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20516 10:57:43.188591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20518 10:57:43.189058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20519 10:57:43.233518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20521 10:57:43.234001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20522 10:57:43.279372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20524 10:57:43.279838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20525 10:57:43.327175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20526 10:57:43.327606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20528 10:57:43.371874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20529 10:57:43.372303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20531 10:57:43.407688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20532 10:57:43.408114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20534 10:57:43.452568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20535 10:57:43.453004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20537 10:57:43.497941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20539 10:57:43.498432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20540 10:57:43.543606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20541 10:57:43.544038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20543 10:57:43.589555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20544 10:57:43.589991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20546 10:57:43.634533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20548 10:57:43.635000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20549 10:57:43.679974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20550 10:57:43.680403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20552 10:57:43.723873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20553 10:57:43.724296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20555 10:57:43.769597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20556 10:57:43.770042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20558 10:57:43.816947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20559 10:57:43.817364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20561 10:57:43.864532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20563 10:57:43.864984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20564 10:57:43.912110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20565 10:57:43.912561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20567 10:57:43.960930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20569 10:57:43.961386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20570 10:57:44.009238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20571 10:57:44.009669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20573 10:57:44.060132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20574 10:57:44.060558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20576 10:57:44.109707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20577 10:57:44.110137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20579 10:57:44.156803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20580 10:57:44.157240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20582 10:57:44.201801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20584 10:57:44.202248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20585 10:57:44.247551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20587 10:57:44.247992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20588 10:57:44.282505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20590 10:57:44.282953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20591 10:57:44.327927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20592 10:57:44.328347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20594 10:57:44.363944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20595 10:57:44.364368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20597 10:57:44.410155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20599 10:57:44.410633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20600 10:57:44.451501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20601 10:57:44.451927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20603 10:57:44.496402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20604 10:57:44.496809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20606 10:57:44.535008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20607 10:57:44.535438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20609 10:57:44.579604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20611 10:57:44.580051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20612 10:57:44.624098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20613 10:57:44.624531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20615 10:57:44.670551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20617 10:57:44.671029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20618 10:57:44.715072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20619 10:57:44.715465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20621 10:57:44.761264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20622 10:57:44.761686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20624 10:57:44.807783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20625 10:57:44.808262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20627 10:57:44.851634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20629 10:57:44.852037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20630 10:57:44.896259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20631 10:57:44.896667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20633 10:57:44.939947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20634 10:57:44.940362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20636 10:57:44.975538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20637 10:57:44.975943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20639 10:57:45.015308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20640 10:57:45.015719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20642 10:57:45.055405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20643 10:57:45.055822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20645 10:57:45.091204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20647 10:57:45.091651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20648 10:57:45.137005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20649 10:57:45.137419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20651 10:57:45.177304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20652 10:57:45.177688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20654 10:57:45.210247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20656 10:57:45.210710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20657 10:57:45.250514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20659 10:57:45.250967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20660 10:57:45.287683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20661 10:57:45.288090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20663 10:57:45.325360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20664 10:57:45.325800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20666 10:57:45.365927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20667 10:57:45.366364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20669 10:57:45.403745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20671 10:57:45.404213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20672 10:57:45.438238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20674 10:57:45.438693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20675 10:57:45.485283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20676 10:57:45.485687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20678 10:57:45.518432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20680 10:57:45.518853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20681 10:57:45.561900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20683 10:57:45.562334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20684 10:57:45.605948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20685 10:57:45.606366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20687 10:57:45.644851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20688 10:57:45.645261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20690 10:57:45.677977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20692 10:57:45.678435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20693 10:57:45.723828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20694 10:57:45.724262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20696 10:57:45.769119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20697 10:57:45.769571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20699 10:57:45.813959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20701 10:57:45.814409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20702 10:57:45.857726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20703 10:57:45.858148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20705 10:57:45.903901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20706 10:57:45.904306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20708 10:57:45.943294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20710 10:57:45.943729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20711 10:57:45.984549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20713 10:57:45.984979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20714 10:57:46.029436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20715 10:57:46.029839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20717 10:57:46.062558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20719 10:57:46.062986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20720 10:57:46.095462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20721 10:57:46.095868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20723 10:57:46.130724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20725 10:57:46.131179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20726 10:57:46.175725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20727 10:57:46.176120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20729 10:57:46.218511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20731 10:57:46.218980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20732 10:57:46.264089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20734 10:57:46.264581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20735 10:57:46.308876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20737 10:57:46.309324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20738 10:57:46.355573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20739 10:57:46.355989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20741 10:57:46.399005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20742 10:57:46.399421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20744 10:57:46.443507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20745 10:57:46.443934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20747 10:57:46.488872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20749 10:57:46.489321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20750 10:57:46.533072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20751 10:57:46.533481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20753 10:57:46.575874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20755 10:57:46.576329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20756 10:57:46.621082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20758 10:57:46.621554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20759 10:57:46.665302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20760 10:57:46.665689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20762 10:57:46.729333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20763 10:57:46.729685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20765 10:57:46.780857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20766 10:57:46.781258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20768 10:57:46.828424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20769 10:57:46.828836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20771 10:57:46.876583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20772 10:57:46.877010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20774 10:57:46.924250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20775 10:57:46.924676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20777 10:57:46.973167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20778 10:57:46.973597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20780 10:57:47.024506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20782 10:57:47.025010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20783 10:57:47.073036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20784 10:57:47.073402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20786 10:57:47.117491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20787 10:57:47.117925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20789 10:57:47.164610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20791 10:57:47.165081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20792 10:57:47.209591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20793 10:57:47.210027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20795 10:57:47.252674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20796 10:57:47.253083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20798 10:57:47.298396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20800 10:57:47.298831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20801 10:57:47.345003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20802 10:57:47.345420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20804 10:57:47.392030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20806 10:57:47.392439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20807 10:57:47.426723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20808 10:57:47.427134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20810 10:57:47.465681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20812 10:57:47.466118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20813 10:57:47.499608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20814 10:57:47.500036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20816 10:57:47.539321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20817 10:57:47.539770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20819 10:57:47.585009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20821 10:57:47.585461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20822 10:57:47.630476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20824 10:57:47.630919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20825 10:57:47.676181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20827 10:57:47.676622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20828 10:57:47.724728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20829 10:57:47.725162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20831 10:57:47.770003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20832 10:57:47.770426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20834 10:57:47.815633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20835 10:57:47.816049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20837 10:57:47.853530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20838 10:57:47.853977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20840 10:57:47.899941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20841 10:57:47.900375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20843 10:57:47.948005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20844 10:57:47.948433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20846 10:57:47.993456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20847 10:57:47.993886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20849 10:57:48.039880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20851 10:57:48.040334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20852 10:57:48.084957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20853 10:57:48.085389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20855 10:57:48.130130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20857 10:57:48.130621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20858 10:57:48.173664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20859 10:57:48.174069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20861 10:57:48.220159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20862 10:57:48.220525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20864 10:57:48.265195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20865 10:57:48.265589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20867 10:57:48.311464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20869 10:57:48.311913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20870 10:57:48.356276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20871 10:57:48.356676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20873 10:57:48.401385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20875 10:57:48.401860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20876 10:57:48.445558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20878 10:57:48.446025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20879 10:57:48.491021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20880 10:57:48.491387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20882 10:57:48.534412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20884 10:57:48.534809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20885 10:57:48.579598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20887 10:57:48.580062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20888 10:57:48.625091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20890 10:57:48.625553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20891 10:57:48.671701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20892 10:57:48.672121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20894 10:57:48.719875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20896 10:57:48.720352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20897 10:57:48.761010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20899 10:57:48.761448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20900 10:57:48.813731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20902 10:57:48.814192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20903 10:57:48.864102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20905 10:57:48.864559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20906 10:57:48.912282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20907 10:57:48.912695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20909 10:57:48.969488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20910 10:57:48.970116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20912 10:57:49.021442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20913 10:57:49.021861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20915 10:57:49.073030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20916 10:57:49.073411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20918 10:57:49.121847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20920 10:57:49.122274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20921 10:57:49.169242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20922 10:57:49.169677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20924 10:57:49.220908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20925 10:57:49.221322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20927 10:57:49.271108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20928 10:57:49.271521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20930 10:57:49.320528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20931 10:57:49.320914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20933 10:57:49.372860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20934 10:57:49.373306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20936 10:57:49.421926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20937 10:57:49.422320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20939 10:57:49.458852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20940 10:57:49.459273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20942 10:57:49.504998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20944 10:57:49.505463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20945 10:57:49.550815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20947 10:57:49.551262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20948 10:57:49.595021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20950 10:57:49.595476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20951 10:57:49.639142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20952 10:57:49.639570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20954 10:57:49.684849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20956 10:57:49.685316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20957 10:57:49.729285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20959 10:57:49.729735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20960 10:57:49.769465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20962 10:57:49.769940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20963 10:57:49.805126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20964 10:57:49.805535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20966 10:57:49.847076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20967 10:57:49.847476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20969 10:57:49.895318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20970 10:57:49.895764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
20972 10:57:49.942139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
20973 10:57:49.942595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
20975 10:57:49.989802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
20976 10:57:49.990244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
20978 10:57:50.031710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
20979 10:57:50.032156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
20981 10:57:50.080777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
20983 10:57:50.081231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
20984 10:57:50.123939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
20985 10:57:50.124385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
20987 10:57:50.169118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
20988 10:57:50.169541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
20990 10:57:50.216493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
20991 10:57:50.216892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
20993 10:57:50.265717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
20994 10:57:50.266124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
20996 10:57:50.319669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
20997 10:57:50.320096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
20999 10:57:50.368594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
21000 10:57:50.368990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21002 10:57:50.419754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21003 10:57:50.420196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21005 10:57:50.468233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21006 10:57:50.468665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21008 10:57:50.519858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21009 10:57:50.520236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21011 10:57:50.567923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21013 10:57:50.568402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21014 10:57:50.615686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21015 10:57:50.616088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21017 10:57:50.663050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21018 10:57:50.663424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21020 10:57:50.709838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21021 10:57:50.710254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21023 10:57:50.757416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21024 10:57:50.757826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21026 10:57:50.804534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21027 10:57:50.804941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21029 10:57:50.851670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21030 10:57:50.852090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21032 10:57:50.899437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21033 10:57:50.899865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21035 10:57:50.947823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21036 10:57:50.948234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21038 10:57:50.996087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21039 10:57:50.996444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21041 10:57:51.045761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21042 10:57:51.046188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21044 10:57:51.094291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21046 10:57:51.094781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21047 10:57:51.142448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21049 10:57:51.142847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21050 10:57:51.190841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21051 10:57:51.191244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21053 10:57:51.239835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21054 10:57:51.240247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21056 10:57:51.288213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21057 10:57:51.288631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21059 10:57:51.338077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21060 10:57:51.338446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21062 10:57:51.386011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21064 10:57:51.386458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21065 10:57:51.433777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21066 10:57:51.434192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21068 10:57:51.481633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21069 10:57:51.482012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21071 10:57:51.529033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21072 10:57:51.529410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21074 10:57:51.576268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21076 10:57:51.576874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21077 10:57:51.625109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21078 10:57:51.625560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21080 10:57:51.673550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21081 10:57:51.673923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21083 10:57:51.723976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21084 10:57:51.724367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21086 10:57:51.771733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21087 10:57:51.772082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21089 10:57:51.819579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21090 10:57:51.819996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21092 10:57:51.893294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21093 10:57:51.893670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21095 10:57:51.941208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21096 10:57:51.941623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21098 10:57:51.991296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21099 10:57:51.991707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21101 10:57:52.040462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21102 10:57:52.040881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21104 10:57:52.083504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21105 10:57:52.083886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21107 10:57:52.123199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21108 10:57:52.123633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21110 10:57:52.167115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21112 10:57:52.167550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21113 10:57:52.211807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21115 10:57:52.212247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21116 10:57:52.256623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21117 10:57:52.257007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21119 10:57:52.301788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21120 10:57:52.302159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21122 10:57:52.347776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21124 10:57:52.348245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21125 10:57:52.395488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21126 10:57:52.395845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21128 10:57:52.441871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21129 10:57:52.442268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21131 10:57:52.488423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21132 10:57:52.488840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21134 10:57:52.533603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21135 10:57:52.534020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21137 10:57:52.579782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21138 10:57:52.580214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21140 10:57:52.625052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21141 10:57:52.625482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21143 10:57:52.671165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21145 10:57:52.671615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21146 10:57:52.716038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21147 10:57:52.716446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21149 10:57:52.753968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21150 10:57:52.754375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21152 10:57:52.799315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21153 10:57:52.799740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21155 10:57:52.844837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21157 10:57:52.845301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21158 10:57:52.889270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21159 10:57:52.889694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21161 10:57:52.935488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21162 10:57:52.935921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21164 10:57:52.976883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21165 10:57:52.977303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21167 10:57:53.015850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21168 10:57:53.016243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21170 10:57:53.056500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21172 10:57:53.056936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21173 10:57:53.097705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21174 10:57:53.098134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21176 10:57:53.143310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21177 10:57:53.143741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21179 10:57:53.181792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21180 10:57:53.182214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21182 10:57:53.216974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21184 10:57:53.217412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21185 10:57:53.250259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21186 10:57:53.250692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21188 10:57:53.296663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21189 10:57:53.297100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21191 10:57:53.342686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21193 10:57:53.343132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21194 10:57:53.379530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21195 10:57:53.379938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21197 10:57:53.412514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21198 10:57:53.412966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21200 10:57:53.447298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21201 10:57:53.447735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21203 10:57:53.492113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21204 10:57:53.492529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21206 10:57:53.537587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21207 10:57:53.538025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21209 10:57:53.581796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21210 10:57:53.582227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21212 10:57:53.626487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21214 10:57:53.626953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21215 10:57:53.669670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21216 10:57:53.670096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21218 10:57:53.713892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21220 10:57:53.714352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21221 10:57:53.759203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21222 10:57:53.759645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21224 10:57:53.804927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21225 10:57:53.805357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21227 10:57:53.852107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21229 10:57:53.852569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21230 10:57:53.897051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21231 10:57:53.897473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21233 10:57:53.941923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21234 10:57:53.942360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21236 10:57:53.989981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21238 10:57:53.990499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21239 10:57:54.029179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21240 10:57:54.029604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21242 10:57:54.076208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21244 10:57:54.076670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21245 10:57:54.123040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21247 10:57:54.123507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21248 10:57:54.169809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21249 10:57:54.170269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21251 10:57:54.211645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21252 10:57:54.212122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21254 10:57:54.252974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21255 10:57:54.253392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21257 10:57:54.299594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21258 10:57:54.299953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21260 10:57:54.344916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21261 10:57:54.345322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21263 10:57:54.389215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21265 10:57:54.389908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21266 10:57:54.433189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21267 10:57:54.433598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21269 10:57:54.479079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21271 10:57:54.479455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21272 10:57:54.517917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21273 10:57:54.518343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21275 10:57:54.552757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21276 10:57:54.553170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21278 10:57:54.589703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21279 10:57:54.590110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21281 10:57:54.623507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21282 10:57:54.623855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21284 10:57:54.666764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21286 10:57:54.667208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21287 10:57:54.699679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21288 10:57:54.700070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21290 10:57:54.742315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21292 10:57:54.742805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21293 10:57:54.787317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21295 10:57:54.787878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21296 10:57:54.835027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21297 10:57:54.835407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21299 10:57:54.879321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21300 10:57:54.879798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21302 10:57:54.923381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21303 10:57:54.923811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21305 10:57:54.967447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21306 10:57:54.967874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21308 10:57:55.012846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21309 10:57:55.013267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21311 10:57:55.053705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21313 10:57:55.054170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21314 10:57:55.099302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21316 10:57:55.099789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21317 10:57:55.143246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21318 10:57:55.143680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21320 10:57:55.187604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21321 10:57:55.188042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21323 10:57:55.229927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21324 10:57:55.230369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21326 10:57:55.278222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21327 10:57:55.278654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21329 10:57:55.315069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21330 10:57:55.315483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21332 10:57:55.357446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21333 10:57:55.357875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21335 10:57:55.404894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21336 10:57:55.405313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21338 10:57:55.452454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21339 10:57:55.452883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21341 10:57:55.500064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21342 10:57:55.500486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21344 10:57:55.550370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21346 10:57:55.550825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21347 10:57:55.599737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21348 10:57:55.600157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21350 10:57:55.647474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21351 10:57:55.647895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21353 10:57:55.695537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21354 10:57:55.695974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21356 10:57:55.742146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21357 10:57:55.742566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21359 10:57:55.789180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21360 10:57:55.789588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21362 10:57:55.836539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21364 10:57:55.836982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21365 10:57:55.884346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21366 10:57:55.884754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21368 10:57:55.931926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21370 10:57:55.932371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21371 10:57:55.977998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21372 10:57:55.978429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21374 10:57:56.025657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21376 10:57:56.026099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21377 10:57:56.073450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21378 10:57:56.073884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21380 10:57:56.122339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21382 10:57:56.122790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21383 10:57:56.169275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21384 10:57:56.169691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21386 10:57:56.216583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21387 10:57:56.217011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21389 10:57:56.263897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21390 10:57:56.264327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21392 10:57:56.311860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21393 10:57:56.312275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21395 10:57:56.358879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21397 10:57:56.359323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21398 10:57:56.405431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21399 10:57:56.405840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21401 10:57:56.452731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21402 10:57:56.453134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21404 10:57:56.499969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21405 10:57:56.500376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21407 10:57:56.547208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21409 10:57:56.547644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21410 10:57:56.594130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21411 10:57:56.594528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21413 10:57:56.642003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21414 10:57:56.642414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21416 10:57:56.689469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21417 10:57:56.689869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21419 10:57:56.738084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21420 10:57:56.738523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21422 10:57:56.785857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21423 10:57:56.786278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21425 10:57:56.833818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21426 10:57:56.834227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21428 10:57:56.881847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21429 10:57:56.882275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21431 10:57:56.929059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21432 10:57:56.929480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21434 10:57:56.999564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21435 10:57:56.999957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21437 10:57:57.044418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21438 10:57:57.044822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21440 10:57:57.077716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21441 10:57:57.078140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21443 10:57:57.121596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21444 10:57:57.122049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21446 10:57:57.167283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21448 10:57:57.167740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21449 10:57:57.208973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21451 10:57:57.209416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21452 10:57:57.253783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21453 10:57:57.254205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21455 10:57:57.298984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21457 10:57:57.299428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21458 10:57:57.344108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21459 10:57:57.344554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21461 10:57:57.391313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21462 10:57:57.391737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21464 10:57:57.429319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21465 10:57:57.429750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21467 10:57:57.474400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21469 10:57:57.474881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21470 10:57:57.518932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21471 10:57:57.519374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21473 10:57:57.558210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21474 10:57:57.558639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21476 10:57:57.597871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21477 10:57:57.598292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21479 10:57:57.642112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21481 10:57:57.642558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21482 10:57:57.686875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21483 10:57:57.687288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21485 10:57:57.731710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21486 10:57:57.732109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21488 10:57:57.775184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21489 10:57:57.775596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21491 10:57:57.819277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21492 10:57:57.819672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21494 10:57:57.859476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21495 10:57:57.859909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21497 10:57:57.893858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21498 10:57:57.894267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21500 10:57:57.932790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21501 10:57:57.933336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21503 10:57:57.977971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21505 10:57:57.978382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21506 10:57:58.022378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21508 10:57:58.022790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21509 10:57:58.067088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21510 10:57:58.067485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21512 10:57:58.112892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21513 10:57:58.113297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21515 10:57:58.147181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21516 10:57:58.147624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21518 10:57:58.191146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21519 10:57:58.191563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21521 10:57:58.236350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21522 10:57:58.236772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21524 10:57:58.270949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21526 10:57:58.271409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21527 10:57:58.304033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21528 10:57:58.304461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21530 10:57:58.348935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21531 10:57:58.350097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21533 10:57:58.387702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21534 10:57:58.388114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21536 10:57:58.432929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21537 10:57:58.433335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21539 10:57:58.478692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21540 10:57:58.479108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21542 10:57:58.512465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21543 10:57:58.512872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21545 10:57:58.549123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21546 10:57:58.549541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21548 10:57:58.591628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21549 10:57:58.592041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21551 10:57:58.636497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21553 10:57:58.636934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21554 10:57:58.680179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21555 10:57:58.680591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21557 10:57:58.725011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21559 10:57:58.725459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21560 10:57:58.773547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21561 10:57:58.774172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21563 10:57:58.824339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21564 10:57:58.824733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21566 10:57:58.874461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21568 10:57:58.874924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21569 10:57:58.922387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21571 10:57:58.922961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21572 10:57:58.972194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21574 10:57:58.972632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21575 10:57:59.024276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21576 10:57:59.024706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21578 10:57:59.077486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21579 10:57:59.077920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21581 10:57:59.127741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21582 10:57:59.128183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21584 10:57:59.175951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21586 10:57:59.176375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21587 10:57:59.222361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21589 10:57:59.222810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21590 10:57:59.270110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21591 10:57:59.270534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21593 10:57:59.318819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21594 10:57:59.319232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21596 10:57:59.365988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21597 10:57:59.366382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21599 10:57:59.413023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21600 10:57:59.413449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21602 10:57:59.459910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21603 10:57:59.460341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21605 10:57:59.507153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21607 10:57:59.507642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21608 10:57:59.553476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21609 10:57:59.553876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21611 10:57:59.601361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21612 10:57:59.601753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21614 10:57:59.648082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21615 10:57:59.648490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21617 10:57:59.695640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21618 10:57:59.696041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21620 10:57:59.742397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21622 10:57:59.742848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21623 10:57:59.789161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21624 10:57:59.789587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21626 10:57:59.836065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21627 10:57:59.836482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21629 10:57:59.883940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21630 10:57:59.884363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21632 10:57:59.931733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21633 10:57:59.932156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21635 10:57:59.979357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21637 10:57:59.979808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21638 10:58:00.025990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21639 10:58:00.026373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21641 10:58:00.073018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21642 10:58:00.073403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21644 10:58:00.120199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21645 10:58:00.120577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21647 10:58:00.167762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21648 10:58:00.168167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21650 10:58:00.215480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21651 10:58:00.215901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21653 10:58:00.263904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21654 10:58:00.264286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21656 10:58:00.311302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21657 10:58:00.311726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21659 10:58:00.358996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21660 10:58:00.359409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21662 10:58:00.406407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21664 10:58:00.406903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21665 10:58:00.454439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21667 10:58:00.455051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21668 10:58:00.503765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21670 10:58:00.504210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21671 10:58:00.551070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21673 10:58:00.551506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21674 10:58:00.597978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21676 10:58:00.598395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21677 10:58:00.645360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21678 10:58:00.645727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21680 10:58:00.692862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21681 10:58:00.693277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21683 10:58:00.740087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21685 10:58:00.740554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21686 10:58:00.786860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21687 10:58:00.787289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21689 10:58:00.833359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21690 10:58:00.833778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21692 10:58:00.879912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21693 10:58:00.880318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21695 10:58:00.926083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21696 10:58:00.926444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21698 10:58:00.974013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21699 10:58:00.974428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21701 10:58:01.024519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21702 10:58:01.024946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21704 10:58:01.072973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21705 10:58:01.073402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21707 10:58:01.125291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21708 10:58:01.125688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21710 10:58:01.175839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21711 10:58:01.176264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21713 10:58:01.212897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21715 10:58:01.213358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21716 10:58:01.257371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21718 10:58:01.257848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21719 10:58:01.301725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21720 10:58:01.302141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21722 10:58:01.347948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21723 10:58:01.348372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21725 10:58:01.388310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21726 10:58:01.388734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21728 10:58:01.427093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21729 10:58:01.427469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21731 10:58:01.461661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21733 10:58:01.462114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21734 10:58:01.505462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21736 10:58:01.505914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21737 10:58:01.549035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21738 10:58:01.549448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21740 10:58:01.593358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21741 10:58:01.593766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21743 10:58:01.637117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21744 10:58:01.637536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21746 10:58:01.681783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21747 10:58:01.682210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21749 10:58:01.728485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21751 10:58:01.728925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21752 10:58:01.772457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21753 10:58:01.772874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21755 10:58:01.817141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21756 10:58:01.817581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21758 10:58:01.854076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21759 10:58:01.854486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21761 10:58:01.898104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21762 10:58:01.898500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21764 10:58:01.943057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21765 10:58:01.943472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21767 10:58:01.982691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21768 10:58:01.983088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21770 10:58:02.023172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21771 10:58:02.023578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21773 10:58:02.076683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21774 10:58:02.077105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21776 10:58:02.133055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21778 10:58:02.133474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21779 10:58:02.176870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21780 10:58:02.177287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21782 10:58:02.220668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21784 10:58:02.221090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21785 10:58:02.263847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21786 10:58:02.264205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21788 10:58:02.306685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21790 10:58:02.307085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21791 10:58:02.351460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21792 10:58:02.351902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21794 10:58:02.396693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21795 10:58:02.397067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21797 10:58:02.441856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21799 10:58:02.442328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21800 10:58:02.478465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21802 10:58:02.478929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21803 10:58:02.515743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21805 10:58:02.516191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21806 10:58:02.548323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21807 10:58:02.548774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21809 10:58:02.592827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21810 10:58:02.593259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21812 10:58:02.628015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21813 10:58:02.628452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21815 10:58:02.667889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21816 10:58:02.668264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21818 10:58:02.703242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21820 10:58:02.703716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21821 10:58:02.739649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21822 10:58:02.739997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21824 10:58:02.783246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21825 10:58:02.783648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21827 10:58:02.827194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21828 10:58:02.827625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21830 10:58:02.871645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21831 10:58:02.872009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21833 10:58:02.916110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21834 10:58:02.916507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21836 10:58:02.959618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21837 10:58:02.960018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21839 10:58:03.002916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21840 10:58:03.003330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21842 10:58:03.046478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21844 10:58:03.046923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21845 10:58:03.091427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21846 10:58:03.091831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21848 10:58:03.134579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21850 10:58:03.135121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21851 10:58:03.177959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21853 10:58:03.178406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21854 10:58:03.222424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21856 10:58:03.222874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21857 10:58:03.266484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21859 10:58:03.266964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21860 10:58:03.311289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21861 10:58:03.311705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21863 10:58:03.354185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21865 10:58:03.354638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21866 10:58:03.398073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21868 10:58:03.398543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21869 10:58:03.450908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21871 10:58:03.451383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21872 10:58:03.507079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21873 10:58:03.507507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21875 10:58:03.561326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21877 10:58:03.561789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21878 10:58:03.616315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21879 10:58:03.616733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21881 10:58:03.669851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21882 10:58:03.670286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21884 10:58:03.724467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21885 10:58:03.724894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21887 10:58:03.780790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21888 10:58:03.781196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21890 10:58:03.840302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21891 10:58:03.840736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21893 10:58:03.899914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21894 10:58:03.900344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21896 10:58:03.955070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21897 10:58:03.955468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21899 10:58:04.009716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21900 10:58:04.010132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21902 10:58:04.066041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21903 10:58:04.066491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21905 10:58:04.120859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21906 10:58:04.121298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21908 10:58:04.167689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21909 10:58:04.168630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21911 10:58:04.204534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21912 10:58:04.205091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21914 10:58:04.245776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21915 10:58:04.246183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21917 10:58:04.300292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21918 10:58:04.300690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21920 10:58:04.350546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21922 10:58:04.351025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21923 10:58:04.388503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21924 10:58:04.388935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21926 10:58:04.429231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21927 10:58:04.429665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21929 10:58:04.474438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21931 10:58:04.474921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21932 10:58:04.516665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21933 10:58:04.517100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21935 10:58:04.556155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21937 10:58:04.556630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21938 10:58:04.595594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21940 10:58:04.596079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21941 10:58:04.645642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21943 10:58:04.646141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21944 10:58:04.695682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21946 10:58:04.696062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21947 10:58:04.746518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21949 10:58:04.746966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21950 10:58:04.794920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21951 10:58:04.795353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21953 10:58:04.844716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21954 10:58:04.845135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21956 10:58:04.896206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21957 10:58:04.896666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21959 10:58:04.945388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21960 10:58:04.945813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21962 10:58:04.995507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21964 10:58:04.995975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21965 10:58:05.034834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21966 10:58:05.035277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21968 10:58:05.071874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21969 10:58:05.072312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
21971 10:58:05.120294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
21972 10:58:05.120677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
21974 10:58:05.169462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
21975 10:58:05.169893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
21977 10:58:05.213174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
21979 10:58:05.213623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
21980 10:58:05.263751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
21981 10:58:05.264185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
21983 10:58:05.313044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
21984 10:58:05.313477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
21986 10:58:05.362992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
21987 10:58:05.363423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
21989 10:58:05.412094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
21990 10:58:05.412526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
21992 10:58:05.449995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
21993 10:58:05.450428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
21995 10:58:05.501167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
21996 10:58:05.501596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
21998 10:58:05.552220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
21999 10:58:05.552653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
22001 10:58:05.601892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22002 10:58:05.602334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22004 10:58:05.651521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22005 10:58:05.651945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22007 10:58:05.699920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22008 10:58:05.700365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22010 10:58:05.752873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22011 10:58:05.753317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22013 10:58:05.803788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22014 10:58:05.804210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22016 10:58:05.844332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22017 10:58:05.844629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22019 10:58:05.893802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22020 10:58:05.894242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22022 10:58:05.941875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22023 10:58:05.942183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22025 10:58:05.991804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22026 10:58:05.992232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22028 10:58:06.036574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22030 10:58:06.037050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22031 10:58:06.075632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22032 10:58:06.076092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22034 10:58:06.117861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22035 10:58:06.118299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22037 10:58:06.165623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22038 10:58:06.166087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22040 10:58:06.208615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22041 10:58:06.209017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22043 10:58:06.258425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22045 10:58:06.258903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22046 10:58:06.307999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22048 10:58:06.308490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22049 10:58:06.356847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22050 10:58:06.357271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22052 10:58:06.407316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22053 10:58:06.407744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22055 10:58:06.456777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22056 10:58:06.457131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22058 10:58:06.503773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22060 10:58:06.504213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22061 10:58:06.540707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22062 10:58:06.541162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22064 10:58:06.592320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22065 10:58:06.592711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22067 10:58:06.642046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22069 10:58:06.642489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22070 10:58:06.688449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22071 10:58:06.688870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22073 10:58:06.727683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22074 10:58:06.728126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22076 10:58:06.779896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22077 10:58:06.780326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22079 10:58:06.825726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22080 10:58:06.826172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22082 10:58:06.876923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22083 10:58:06.877312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22085 10:58:06.924642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22087 10:58:06.925088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22088 10:58:06.975698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22089 10:58:06.976128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22091 10:58:07.028610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22092 10:58:07.028993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22094 10:58:07.078372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22096 10:58:07.078768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22097 10:58:07.128238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22098 10:58:07.128668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22100 10:58:07.180115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22101 10:58:07.180551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22103 10:58:07.245456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22104 10:58:07.245899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22106 10:58:07.284468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22107 10:58:07.284914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22109 10:58:07.337176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22110 10:58:07.337628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22112 10:58:07.387948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22113 10:58:07.388392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22115 10:58:07.426942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22116 10:58:07.427495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22118 10:58:07.477207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22119 10:58:07.477625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22121 10:58:07.528404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22122 10:58:07.528798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22124 10:58:07.577541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22126 10:58:07.577984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22127 10:58:07.628033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22129 10:58:07.628507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22130 10:58:07.676383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22132 10:58:07.676771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22133 10:58:07.727275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22134 10:58:07.727693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22136 10:58:07.776402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22137 10:58:07.776820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22139 10:58:07.827909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22140 10:58:07.828336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22142 10:58:07.873660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22143 10:58:07.874068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22145 10:58:07.924805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22146 10:58:07.925232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22148 10:58:07.972929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22149 10:58:07.973297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22151 10:58:08.017627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22153 10:58:08.017967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22154 10:58:08.066395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22156 10:58:08.066704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22157 10:58:08.107219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22159 10:58:08.107547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22160 10:58:08.158552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22162 10:58:08.158866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22163 10:58:08.196187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22165 10:58:08.196754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22166 10:58:08.246526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22168 10:58:08.247014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22169 10:58:08.296878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22170 10:58:08.297303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22172 10:58:08.346502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22174 10:58:08.346970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22175 10:58:08.393342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22177 10:58:08.393836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22178 10:58:08.436557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22179 10:58:08.436969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22181 10:58:08.487528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22182 10:58:08.487964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22184 10:58:08.536774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22185 10:58:08.537209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22187 10:58:08.575779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22188 10:58:08.576124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22190 10:58:08.619347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22191 10:58:08.619637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22193 10:58:08.661671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22195 10:58:08.661968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22196 10:58:08.704614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22197 10:58:08.704911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22199 10:58:08.755484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22201 10:58:08.755929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22202 10:58:08.804998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22203 10:58:08.805429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22205 10:58:08.855855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22206 10:58:08.856235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22208 10:58:08.907166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22209 10:58:08.907591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22211 10:58:08.956474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22212 10:58:08.956913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22214 10:58:09.005956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22215 10:58:09.006395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22217 10:58:09.055987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22218 10:58:09.061726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22220 10:58:09.107836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22221 10:58:09.108270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22223 10:58:09.157436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22224 10:58:09.157872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22226 10:58:09.205853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22227 10:58:09.206248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22229 10:58:09.256314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22230 10:58:09.256706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22232 10:58:09.293291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22233 10:58:09.293633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22235 10:58:09.341920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22236 10:58:09.342198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22238 10:58:09.392402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22239 10:58:09.392767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22241 10:58:09.444214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22242 10:58:09.444523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22244 10:58:09.493080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22245 10:58:09.493347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22247 10:58:09.541830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22248 10:58:09.542124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22250 10:58:09.590045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22251 10:58:09.590335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22253 10:58:09.639403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22254 10:58:09.639650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22256 10:58:09.687956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22257 10:58:09.688229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22259 10:58:09.735825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22260 10:58:09.736121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22262 10:58:09.771204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22264 10:58:09.771558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22265 10:58:09.820044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22267 10:58:09.820373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22268 10:58:09.869005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22269 10:58:09.869301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22271 10:58:09.917875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22272 10:58:09.918167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22274 10:58:09.967245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22275 10:58:09.967519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22277 10:58:10.006011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22279 10:58:10.006309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22280 10:58:10.055398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22282 10:58:10.055696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22283 10:58:10.104747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22284 10:58:10.105050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22286 10:58:10.142319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22288 10:58:10.142820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22289 10:58:10.187072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22290 10:58:10.187510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22292 10:58:10.235818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22293 10:58:10.236253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22295 10:58:10.282880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22296 10:58:10.283338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22298 10:58:10.332326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22299 10:58:10.332754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22301 10:58:10.381677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22302 10:58:10.382098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22304 10:58:10.431944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22305 10:58:10.432364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22307 10:58:10.478013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22309 10:58:10.478471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22310 10:58:10.524018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22311 10:58:10.524454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22313 10:58:10.568674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22314 10:58:10.569120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22316 10:58:10.619469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22317 10:58:10.619907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22319 10:58:10.658599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22320 10:58:10.659053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22322 10:58:10.701694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22323 10:58:10.702126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22325 10:58:10.744335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22326 10:58:10.744764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22328 10:58:10.784869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22329 10:58:10.785304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22331 10:58:10.835199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22333 10:58:10.835648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22334 10:58:10.883641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22335 10:58:10.884022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22337 10:58:10.919769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22338 10:58:10.920216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22340 10:58:10.968412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22341 10:58:10.968848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22343 10:58:11.017437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22344 10:58:11.017878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22346 10:58:11.067422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22348 10:58:11.067900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22349 10:58:11.108349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22350 10:58:11.108807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22352 10:58:11.158619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22354 10:58:11.159086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22355 10:58:11.207141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22356 10:58:11.207584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22358 10:58:11.243578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22359 10:58:11.243999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22361 10:58:11.288612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22363 10:58:11.289070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22364 10:58:11.324555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22365 10:58:11.324983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22367 10:58:11.360918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22368 10:58:11.361368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22370 10:58:11.405680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22371 10:58:11.406068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22373 10:58:11.451757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22374 10:58:11.452201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22376 10:58:11.497717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22377 10:58:11.498137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22379 10:58:11.545390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22381 10:58:11.545844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22382 10:58:11.593713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22383 10:58:11.594102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22385 10:58:11.643015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22386 10:58:11.643439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22388 10:58:11.692568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22389 10:58:11.693010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22391 10:58:11.743083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22393 10:58:11.743558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22394 10:58:11.791905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22395 10:58:11.792299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22397 10:58:11.840437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22399 10:58:11.840914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22400 10:58:11.888504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22402 10:58:11.888970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22403 10:58:11.929231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22404 10:58:11.929686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22406 10:58:11.977513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22407 10:58:11.977978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22409 10:58:12.028752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22411 10:58:12.029216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22412 10:58:12.078465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22414 10:58:12.078868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22415 10:58:12.125554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22416 10:58:12.125963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22418 10:58:12.161627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22420 10:58:12.162103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22421 10:58:12.199180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22422 10:58:12.199636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22424 10:58:12.241029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22425 10:58:12.241443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22427 10:58:12.289680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22428 10:58:12.290103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22430 10:58:12.351582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22431 10:58:12.352036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22433 10:58:12.387907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22434 10:58:12.388339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22436 10:58:12.436931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22437 10:58:12.437360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22439 10:58:12.486362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22441 10:58:12.487047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22442 10:58:12.535765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22443 10:58:12.536185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22445 10:58:12.585409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22446 10:58:12.585842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22448 10:58:12.635835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22449 10:58:12.636277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22451 10:58:12.685564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22452 10:58:12.686008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22454 10:58:12.725122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22456 10:58:12.725599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22457 10:58:12.762464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22459 10:58:12.762933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22460 10:58:12.811178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22461 10:58:12.811618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22463 10:58:12.860405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22465 10:58:12.860894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22466 10:58:12.909864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22467 10:58:12.910283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22469 10:58:12.947520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22470 10:58:12.947901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22472 10:58:12.996305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22473 10:58:12.996733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22475 10:58:13.046320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22477 10:58:13.046775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22478 10:58:13.093721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22479 10:58:13.094150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22481 10:58:13.140247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22482 10:58:13.140656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22484 10:58:13.186532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22486 10:58:13.186991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22487 10:58:13.237343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22488 10:58:13.237788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22490 10:58:13.289910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22491 10:58:13.290366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22493 10:58:13.342100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22494 10:58:13.342862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22496 10:58:13.394224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22497 10:58:13.394675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22499 10:58:13.447396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22500 10:58:13.448185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22502 10:58:13.500354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22503 10:58:13.500807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22505 10:58:13.552812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22506 10:58:13.553264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22508 10:58:13.605172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22509 10:58:13.605600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22511 10:58:13.657226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22512 10:58:13.657660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22514 10:58:13.709520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22515 10:58:13.709958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22517 10:58:13.763059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22518 10:58:13.763354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22520 10:58:13.815325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22522 10:58:13.815668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22523 10:58:13.866101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22524 10:58:13.866494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22526 10:58:13.917435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22527 10:58:13.917766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22529 10:58:13.969123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22531 10:58:13.969530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22532 10:58:14.021372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22533 10:58:14.021672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22535 10:58:14.073003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22536 10:58:14.077739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22538 10:58:14.125991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22539 10:58:14.126430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22541 10:58:14.178077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22542 10:58:14.178504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22544 10:58:14.230474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22546 10:58:14.230946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22547 10:58:14.281481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22548 10:58:14.281935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22550 10:58:14.333258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22551 10:58:14.333690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22553 10:58:14.384577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22554 10:58:14.384844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22556 10:58:14.436617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22557 10:58:14.437018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22559 10:58:14.488279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22560 10:58:14.488584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22562 10:58:14.540141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22563 10:58:14.540410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22565 10:58:14.592726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22567 10:58:14.593040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22568 10:58:14.644513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22569 10:58:14.644799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22571 10:58:14.697044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22572 10:58:14.697331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22574 10:58:14.748476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22576 10:58:14.748790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22577 10:58:14.800358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22579 10:58:14.800661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22580 10:58:14.851813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22581 10:58:14.852112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22583 10:58:14.902613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22585 10:58:14.902948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22586 10:58:14.953450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22587 10:58:14.953745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22589 10:58:15.005157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22590 10:58:15.005448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22592 10:58:15.057115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22594 10:58:15.057559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22595 10:58:15.109420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22596 10:58:15.109863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22598 10:58:15.160787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22599 10:58:15.161246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22601 10:58:15.212961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22602 10:58:15.213390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22604 10:58:15.264517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22605 10:58:15.264855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22607 10:58:15.316430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22608 10:58:15.316871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22610 10:58:15.368398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22611 10:58:15.368792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22613 10:58:15.420936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22614 10:58:15.421231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22616 10:58:15.472473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22617 10:58:15.472815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22619 10:58:15.524846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22620 10:58:15.525165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22622 10:58:15.576605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22624 10:58:15.576919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22625 10:58:15.628645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22626 10:58:15.628941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22628 10:58:15.681926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22629 10:58:15.682363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22631 10:58:15.732944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22632 10:58:15.733238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22634 10:58:15.784431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22636 10:58:15.784740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22637 10:58:15.836803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22638 10:58:15.837104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22640 10:58:15.889207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22641 10:58:15.889468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22643 10:58:15.940699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22644 10:58:15.940990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22646 10:58:15.992791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22647 10:58:15.993084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22649 10:58:16.045192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22650 10:58:16.045487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22652 10:58:16.096703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22653 10:58:16.097128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22655 10:58:16.148665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22656 10:58:16.149001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22658 10:58:16.200325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22660 10:58:16.200572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22661 10:58:16.251954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22663 10:58:16.252299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22664 10:58:16.304111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22665 10:58:16.304514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22667 10:58:16.356025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22668 10:58:16.356445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22670 10:58:16.407907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22671 10:58:16.408343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22673 10:58:16.459673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22674 10:58:16.460108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22676 10:58:16.512533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22677 10:58:16.512958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22679 10:58:16.563804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22680 10:58:16.564242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22682 10:58:16.615727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22683 10:58:16.616143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22685 10:58:16.668198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22686 10:58:16.668623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22688 10:58:16.720915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22689 10:58:16.721363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22691 10:58:16.773092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22692 10:58:16.773539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22694 10:58:16.825853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22695 10:58:16.826280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22697 10:58:16.877987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22698 10:58:16.878399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22700 10:58:16.930548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22702 10:58:16.930991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22703 10:58:16.983406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22704 10:58:16.983867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22706 10:58:17.035709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22707 10:58:17.036110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22709 10:58:17.088965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22710 10:58:17.089375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22712 10:58:17.141201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22713 10:58:17.141546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22715 10:58:17.192173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22716 10:58:17.192474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22718 10:58:17.243842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22720 10:58:17.244110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22721 10:58:17.295574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22722 10:58:17.295882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22724 10:58:17.347917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22726 10:58:17.348229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22727 10:58:17.399033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22729 10:58:17.399335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22730 10:58:17.475528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22731 10:58:17.475961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22733 10:58:17.528139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22735 10:58:17.528532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22736 10:58:17.580686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22737 10:58:17.581119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22739 10:58:17.632507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22740 10:58:17.632947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22742 10:58:17.684542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22743 10:58:17.684977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22745 10:58:17.736275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22746 10:58:17.736703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22748 10:58:17.788758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22749 10:58:17.789184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22751 10:58:17.841170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22752 10:58:17.841935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22754 10:58:17.892688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22755 10:58:17.893029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22757 10:58:17.944189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22758 10:58:17.944472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22760 10:58:17.995981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22761 10:58:17.996277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22763 10:58:18.048178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22764 10:58:18.048457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22766 10:58:18.099854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22768 10:58:18.100157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22769 10:58:18.150949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22770 10:58:18.151249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22772 10:58:18.201308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22773 10:58:18.201760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22775 10:58:18.253332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22777 10:58:18.253820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22778 10:58:18.304857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22779 10:58:18.305301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22781 10:58:18.356413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22782 10:58:18.356853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22784 10:58:18.408845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22786 10:58:18.409287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22787 10:58:18.461502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22788 10:58:18.461940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22790 10:58:18.512988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22791 10:58:18.513429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22793 10:58:18.564788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22794 10:58:18.565211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22796 10:58:18.616602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22798 10:58:18.617054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22799 10:58:18.668380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22800 10:58:18.668819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22802 10:58:18.720614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22803 10:58:18.721057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22805 10:58:18.773026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22806 10:58:18.773467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22808 10:58:18.824339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22809 10:58:18.824767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22811 10:58:18.878290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22813 10:58:18.878865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22814 10:58:18.933665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22815 10:58:18.934065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22817 10:58:18.987985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22819 10:58:18.988448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22820 10:58:19.041739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22821 10:58:19.042170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22823 10:58:19.093207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22824 10:58:19.093605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22826 10:58:19.147143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22827 10:58:19.147489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22829 10:58:19.202297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22831 10:58:19.202622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22832 10:58:19.256022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22834 10:58:19.256331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22835 10:58:19.307982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22836 10:58:19.308282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22838 10:58:19.367236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22839 10:58:19.367674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22841 10:58:19.413785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22842 10:58:19.414190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22844 10:58:19.465065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22845 10:58:19.465461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22847 10:58:19.516463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22849 10:58:19.516915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22850 10:58:19.569822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22851 10:58:19.570248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22853 10:58:19.624191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22854 10:58:19.624615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22856 10:58:19.676500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22858 10:58:19.676952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22859 10:58:19.729309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22860 10:58:19.729751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22862 10:58:19.783643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22863 10:58:19.784071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22865 10:58:19.835976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22867 10:58:19.836438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22868 10:58:19.888345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22869 10:58:19.888814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22871 10:58:19.940701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22872 10:58:19.941145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22874 10:58:19.993204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22875 10:58:19.993630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22877 10:58:20.045298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22878 10:58:20.045686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22880 10:58:20.096981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22882 10:58:20.097420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22883 10:58:20.149511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22884 10:58:20.149924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22886 10:58:20.201001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22887 10:58:20.201293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22889 10:58:20.253017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22890 10:58:20.253459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22892 10:58:20.304904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22893 10:58:20.305357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22895 10:58:20.356478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22897 10:58:20.356938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22898 10:58:20.409634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22899 10:58:20.410100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22901 10:58:20.462135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22903 10:58:20.462616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22904 10:58:20.514572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22906 10:58:20.515958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22907 10:58:20.566450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22908 10:58:20.566856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22910 10:58:20.618007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22912 10:58:20.618429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22913 10:58:20.668955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22914 10:58:20.669331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22916 10:58:20.721565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22917 10:58:20.721978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22919 10:58:20.773201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22920 10:58:20.773631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22922 10:58:20.824687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22923 10:58:20.825067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22925 10:58:20.877596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22926 10:58:20.878004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22928 10:58:20.929409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22929 10:58:20.929865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22931 10:58:20.980913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22932 10:58:20.981367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22934 10:58:21.035558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22935 10:58:21.035988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22937 10:58:21.087407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22938 10:58:21.087861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22940 10:58:21.138573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22942 10:58:21.138990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22943 10:58:21.189525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22945 10:58:21.190011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22946 10:58:21.241168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22947 10:58:21.241602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22949 10:58:21.292854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22950 10:58:21.293305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22952 10:58:21.344817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22953 10:58:21.345210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22955 10:58:21.397702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22956 10:58:21.398142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22958 10:58:21.449205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22959 10:58:21.449609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22961 10:58:21.501058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22962 10:58:21.501478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22964 10:58:21.552998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22966 10:58:21.553451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22967 10:58:21.604945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22969 10:58:21.605394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22970 10:58:21.656729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
22971 10:58:21.657168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
22973 10:58:21.708927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
22974 10:58:21.709369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
22976 10:58:21.760942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
22977 10:58:21.761400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
22979 10:58:21.814603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
22981 10:58:21.815374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
22982 10:58:21.867045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
22983 10:58:21.867456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
22985 10:58:21.918413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
22987 10:58:21.919134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
22988 10:58:21.969778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
22989 10:58:21.970199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
22991 10:58:22.020841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
22992 10:58:22.021241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
22994 10:58:22.066117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
22995 10:58:22.066567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
22997 10:58:22.104135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
22998 10:58:22.104532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
23000 10:58:22.152431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23001 10:58:22.152877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23003 10:58:22.201008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23004 10:58:22.201449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23006 10:58:22.249327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23007 10:58:22.249769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23009 10:58:22.297809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23011 10:58:22.298284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23012 10:58:22.347474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23013 10:58:22.347736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23015 10:58:22.403180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23016 10:58:22.403605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23018 10:58:22.449100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23020 10:58:22.449472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23021 10:58:22.495925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23022 10:58:22.496345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23024 10:58:22.541541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23025 10:58:22.541962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23027 10:58:22.615379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23028 10:58:22.615788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23030 10:58:22.661247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23031 10:58:22.661633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23033 10:58:22.709279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23034 10:58:22.709663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23036 10:58:22.755536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23037 10:58:22.755926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23039 10:58:22.799850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23040 10:58:22.800212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23042 10:58:22.844426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23043 10:58:22.844817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23045 10:58:22.890509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23047 10:58:22.890884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23048 10:58:22.924370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23049 10:58:22.924805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23051 10:58:22.966335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23053 10:58:22.966807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23054 10:58:23.000526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23055 10:58:23.000934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23057 10:58:23.046615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23059 10:58:23.046980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23060 10:58:23.091365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23061 10:58:23.091752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23063 10:58:23.137029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23064 10:58:23.137444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23066 10:58:23.172376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23067 10:58:23.172783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23069 10:58:23.219120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23070 10:58:23.219496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23072 10:58:23.253258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23073 10:58:23.253687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23075 10:58:23.288312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23076 10:58:23.288726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23078 10:58:23.333790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23079 10:58:23.334192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23081 10:58:23.376951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23083 10:58:23.377378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23084 10:58:23.419649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23085 10:58:23.420071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23087 10:58:23.464684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23088 10:58:23.465077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23090 10:58:23.507174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23091 10:58:23.507626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23093 10:58:23.551963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23094 10:58:23.552385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23096 10:58:23.597080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23097 10:58:23.597493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23099 10:58:23.645143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23100 10:58:23.645556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23102 10:58:23.692298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23103 10:58:23.692706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23105 10:58:23.737620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23106 10:58:23.738018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23108 10:58:23.783923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23109 10:58:23.784356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23111 10:58:23.831438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23112 10:58:23.831867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23114 10:58:23.880763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23115 10:58:23.881168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23117 10:58:23.929715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23118 10:58:23.930118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23120 10:58:23.974479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23122 10:58:23.974982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23123 10:58:24.020976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23125 10:58:24.021402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23126 10:58:24.065611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23127 10:58:24.066041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23129 10:58:24.111218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23130 10:58:24.115187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23132 10:58:24.161081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23133 10:58:24.161532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23135 10:58:24.204094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23136 10:58:24.204517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23138 10:58:24.251550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23139 10:58:24.251980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23141 10:58:24.296764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23142 10:58:24.297192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23144 10:58:24.342339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23146 10:58:24.343051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23147 10:58:24.389413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23148 10:58:24.389862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23150 10:58:24.436083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23152 10:58:24.436550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23153 10:58:24.483651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23155 10:58:24.484102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23156 10:58:24.527685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23157 10:58:24.528098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23159 10:58:24.572480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23160 10:58:24.572916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23162 10:58:24.619075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23164 10:58:24.619471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23165 10:58:24.663889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23166 10:58:24.664320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23168 10:58:24.709122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23169 10:58:24.709492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23171 10:58:24.749538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23173 10:58:24.750022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23174 10:58:24.792664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23175 10:58:24.793092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23177 10:58:24.831985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23178 10:58:24.832410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23180 10:58:24.877809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23181 10:58:24.878228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23183 10:58:24.923382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23184 10:58:24.923806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23186 10:58:24.957916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23187 10:58:24.958342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23189 10:58:24.992668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23191 10:58:24.993118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23192 10:58:25.037274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23194 10:58:25.037729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23195 10:58:25.083283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23196 10:58:25.083720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23198 10:58:25.128634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23199 10:58:25.129064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23201 10:58:25.175143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23202 10:58:25.175565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23204 10:58:25.221345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23205 10:58:25.221748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23207 10:58:25.256704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23208 10:58:25.257135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23210 10:58:25.291767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23212 10:58:25.292219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23213 10:58:25.337545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23214 10:58:25.337926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23216 10:58:25.383499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23217 10:58:25.383911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23219 10:58:25.435558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23221 10:58:25.436042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23222 10:58:25.476651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23223 10:58:25.477032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23225 10:58:25.513256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23227 10:58:25.513696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23228 10:58:25.547172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23230 10:58:25.547626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23231 10:58:25.591795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23233 10:58:25.592276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23234 10:58:25.635757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23235 10:58:25.636143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23237 10:58:25.681019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23238 10:58:25.681463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23240 10:58:25.727485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23241 10:58:25.727913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23243 10:58:25.774876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23244 10:58:25.775326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23246 10:58:25.820820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23247 10:58:25.821219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23249 10:58:25.868732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23250 10:58:25.869148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23252 10:58:25.916419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23253 10:58:25.916812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23255 10:58:25.966268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23257 10:58:25.966813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23258 10:58:26.011806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23259 10:58:26.012238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23261 10:58:26.055858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23262 10:58:26.056281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23264 10:58:26.101069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23266 10:58:26.101534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23267 10:58:26.148956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23268 10:58:26.149384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23270 10:58:26.195631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23271 10:58:26.196064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23273 10:58:26.234446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23275 10:58:26.234913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23276 10:58:26.281909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23277 10:58:26.282326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23279 10:58:26.327391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23280 10:58:26.327801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23282 10:58:26.373156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23283 10:58:26.373584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23285 10:58:26.419822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23286 10:58:26.420230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23288 10:58:26.465190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23289 10:58:26.465605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23291 10:58:26.510254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23293 10:58:26.510765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23294 10:58:26.555654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23295 10:58:26.556051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23297 10:58:26.600786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23298 10:58:26.601207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23300 10:58:26.647267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23301 10:58:26.647670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23303 10:58:26.683725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23304 10:58:26.684128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23306 10:58:26.716612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23307 10:58:26.717006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23309 10:58:26.761026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23310 10:58:26.761454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23312 10:58:26.806318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23314 10:58:26.806948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23315 10:58:26.851393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23316 10:58:26.851811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23318 10:58:26.895993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23319 10:58:26.896430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23321 10:58:26.940975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23322 10:58:26.941392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23324 10:58:26.985787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23325 10:58:26.986175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23327 10:58:27.031594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23328 10:58:27.032011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23330 10:58:27.076575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23331 10:58:27.076951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23333 10:58:27.121488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23334 10:58:27.121897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23336 10:58:27.166464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23338 10:58:27.166915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23339 10:58:27.212177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23340 10:58:27.212606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23342 10:58:27.257082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23344 10:58:27.257528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23345 10:58:27.303002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23346 10:58:27.303407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23348 10:58:27.339666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23349 10:58:27.340053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23351 10:58:27.385239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23352 10:58:27.385711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23354 10:58:27.430436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23356 10:58:27.431104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23357 10:58:27.467268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23358 10:58:27.467665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23360 10:58:27.512110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23361 10:58:27.512526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23363 10:58:27.553940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23364 10:58:27.554352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23366 10:58:27.599390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23367 10:58:27.599817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23369 10:58:27.644568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23371 10:58:27.645000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23372 10:58:27.709713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23373 10:58:27.710124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23375 10:58:27.752542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23376 10:58:27.752917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23378 10:58:27.797707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23380 10:58:27.798144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23381 10:58:27.844554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23382 10:58:27.844978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23384 10:58:27.889199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23386 10:58:27.889642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23387 10:58:27.933955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23388 10:58:27.934343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23390 10:58:27.979095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23391 10:58:27.979489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23393 10:58:28.024003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23394 10:58:28.024361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23396 10:58:28.070302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23398 10:58:28.070784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23399 10:58:28.115720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23400 10:58:28.116128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23402 10:58:28.161172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23403 10:58:28.161576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23405 10:58:28.207528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23406 10:58:28.207977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23408 10:58:28.253269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23409 10:58:28.253692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23411 10:58:28.298409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23413 10:58:28.298902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23414 10:58:28.343878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23415 10:58:28.344305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23417 10:58:28.389568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23419 10:58:28.390016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23420 10:58:28.435518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23421 10:58:28.435907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23423 10:58:28.480455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23424 10:58:28.480880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23426 10:58:28.525515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23427 10:58:28.525931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23429 10:58:28.571040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23430 10:58:28.571467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23432 10:58:28.615717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23434 10:58:28.616163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23435 10:58:28.660747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23436 10:58:28.661176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23438 10:58:28.705562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23439 10:58:28.705973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23441 10:58:28.751163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23442 10:58:28.751576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23444 10:58:28.796119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23445 10:58:28.796528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23447 10:58:28.840846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23448 10:58:28.841250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23450 10:58:28.873664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23451 10:58:28.874082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23453 10:58:28.920582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23454 10:58:28.921030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23456 10:58:28.967889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23457 10:58:28.968319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23459 10:58:29.028696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23461 10:58:29.029084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23462 10:58:29.076003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23463 10:58:29.076440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23465 10:58:29.121429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23466 10:58:29.121821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23468 10:58:29.167725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23469 10:58:29.168166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23471 10:58:29.215875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23472 10:58:29.216289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23474 10:58:29.262321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23476 10:58:29.262791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23477 10:58:29.309900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23478 10:58:29.310287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23480 10:58:29.356881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23482 10:58:29.357229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23483 10:58:29.401027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23484 10:58:29.401443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23486 10:58:29.439400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23487 10:58:29.439823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23489 10:58:29.483999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23491 10:58:29.484437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23492 10:58:29.529901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23494 10:58:29.530381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23495 10:58:29.575085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23496 10:58:29.575531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23498 10:58:29.619277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23499 10:58:29.619986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23501 10:58:29.663723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23502 10:58:29.664159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23504 10:58:29.708171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23505 10:58:29.708585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23507 10:58:29.752834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23508 10:58:29.753250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23510 10:58:29.798129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23512 10:58:29.798599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23513 10:58:29.843679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23514 10:58:29.844103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23516 10:58:29.888783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23517 10:58:29.889203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23519 10:58:29.933538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23520 10:58:29.933957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23522 10:58:29.978233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23524 10:58:29.978668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23525 10:58:30.023109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23526 10:58:30.023534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23528 10:58:30.067467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23529 10:58:30.067898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23531 10:58:30.111991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23532 10:58:30.112432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23534 10:58:30.157134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23535 10:58:30.157583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23537 10:58:30.201713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23538 10:58:30.202112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23540 10:58:30.248295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23542 10:58:30.248744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23543 10:58:30.289813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23544 10:58:30.290203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23546 10:58:30.328775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23547 10:58:30.329178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23549 10:58:30.374088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23551 10:58:30.374548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23552 10:58:30.419646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23553 10:58:30.420043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23555 10:58:30.465596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23556 10:58:30.466005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23558 10:58:30.508659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23559 10:58:30.509031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23561 10:58:30.544562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23563 10:58:30.545044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23564 10:58:30.579981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23565 10:58:30.580391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23567 10:58:30.625565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23568 10:58:30.626041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23570 10:58:30.671331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23571 10:58:30.671750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23573 10:58:30.719986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23574 10:58:30.720408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23576 10:58:30.766253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23577 10:58:30.766670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23579 10:58:30.803406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23580 10:58:30.803827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23582 10:58:30.848594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23583 10:58:30.848978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23585 10:58:30.895954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23587 10:58:30.896405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23588 10:58:30.944459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23589 10:58:30.944882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23591 10:58:30.982110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23593 10:58:30.982530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23594 10:58:31.027713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23596 10:58:31.028104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23597 10:58:31.072149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23598 10:58:31.072571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23600 10:58:31.117778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23601 10:58:31.118189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23603 10:58:31.160644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23604 10:58:31.161074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23606 10:58:31.205045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23607 10:58:31.205477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23609 10:58:31.247119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23610 10:58:31.247531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23612 10:58:31.292564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23613 10:58:31.292975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23615 10:58:31.336947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23616 10:58:31.337394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23618 10:58:31.383916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23619 10:58:31.384349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23621 10:58:31.429023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23622 10:58:31.429462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23624 10:58:31.466742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23625 10:58:31.467125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23627 10:58:31.512056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23629 10:58:31.512507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23630 10:58:31.556957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23631 10:58:31.557376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23633 10:58:31.597478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23634 10:58:31.597899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23636 10:58:31.643488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23637 10:58:31.643839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23639 10:58:31.688126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23640 10:58:31.688534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23642 10:58:31.729632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23643 10:58:31.730047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23645 10:58:31.763942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23646 10:58:31.764368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23648 10:58:31.811679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23649 10:58:31.812072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23651 10:58:31.852501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23652 10:58:31.852925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23654 10:58:31.897702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23655 10:58:31.898089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23657 10:58:31.939785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23658 10:58:31.940167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23660 10:58:31.984326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23661 10:58:31.984710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23663 10:58:32.025550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23664 10:58:32.025944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23666 10:58:32.064906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23667 10:58:32.065321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23669 10:58:32.111471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23670 10:58:32.111865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23672 10:58:32.151431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23673 10:58:32.151867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23675 10:58:32.196481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23677 10:58:32.196924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23678 10:58:32.241911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23679 10:58:32.242332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23681 10:58:32.287629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23682 10:58:32.288037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23684 10:58:32.332777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23685 10:58:32.333197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23687 10:58:32.377300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23689 10:58:32.377762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23690 10:58:32.417656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23691 10:58:32.418060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23693 10:58:32.456688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23694 10:58:32.457107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23696 10:58:32.491662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23697 10:58:32.492085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23699 10:58:32.529731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23700 10:58:32.530119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23702 10:58:32.568153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23703 10:58:32.568580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23705 10:58:32.613033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23706 10:58:32.613450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23708 10:58:32.647557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23709 10:58:32.647948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23711 10:58:32.691670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23713 10:58:32.692129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23714 10:58:32.736516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23715 10:58:32.736883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23717 10:58:32.780317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23718 10:58:32.780745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23720 10:58:32.847902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23722 10:58:32.848355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23723 10:58:32.891335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23724 10:58:32.891764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23726 10:58:32.936544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23727 10:58:32.936926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23729 10:58:32.981745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23730 10:58:32.982151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23732 10:58:33.027717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23733 10:58:33.028126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23735 10:58:33.072873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23737 10:58:33.073330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23738 10:58:33.117941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23739 10:58:33.118318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23741 10:58:33.152095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23743 10:58:33.152550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23744 10:58:33.186440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23746 10:58:33.186888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23747 10:58:33.221136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23748 10:58:33.221575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23750 10:58:33.256133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23751 10:58:33.256544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23753 10:58:33.290336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23755 10:58:33.290780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23756 10:58:33.335570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23757 10:58:33.335952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23759 10:58:33.369012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23760 10:58:33.369462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23762 10:58:33.404096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23763 10:58:33.404506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23765 10:58:33.451331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23766 10:58:33.451767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23768 10:58:33.498215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23769 10:58:33.498655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23771 10:58:33.543961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23772 10:58:33.544373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23774 10:58:33.589099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23775 10:58:33.589497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23777 10:58:33.635196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23778 10:58:33.635618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23780 10:58:33.678037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23781 10:58:33.678431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23783 10:58:33.718118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23784 10:58:33.718549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23786 10:58:33.763749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23787 10:58:33.764173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23789 10:58:33.808835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23790 10:58:33.809215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23792 10:58:33.854980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23793 10:58:33.855421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23795 10:58:33.900151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23796 10:58:33.900599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23798 10:58:33.947129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23799 10:58:33.947549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23801 10:58:33.993001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23802 10:58:33.993396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23804 10:58:34.040222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23805 10:58:34.040630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23807 10:58:34.087856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23809 10:58:34.088346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23810 10:58:34.133952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23811 10:58:34.137701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23813 10:58:34.179688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23814 10:58:34.180123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23816 10:58:34.225931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23817 10:58:34.226373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23819 10:58:34.275390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23820 10:58:34.275837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23822 10:58:34.323519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23823 10:58:34.323958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23825 10:58:34.370868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23826 10:58:34.371292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23828 10:58:34.418620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23830 10:58:34.419084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23831 10:58:34.465744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23832 10:58:34.466172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23834 10:58:34.511867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23835 10:58:34.512296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23837 10:58:34.557865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23838 10:58:34.558277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23840 10:58:34.604443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23841 10:58:34.604867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23843 10:58:34.652413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23844 10:58:34.652841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23846 10:58:34.698578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23848 10:58:34.699040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23849 10:58:34.740748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23850 10:58:34.741164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23852 10:58:34.787377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23853 10:58:34.787788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23855 10:58:34.830453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23857 10:58:34.831031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23858 10:58:34.877034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23859 10:58:34.877416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23861 10:58:34.923496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23862 10:58:34.923886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23864 10:58:34.967978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23866 10:58:34.968398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23867 10:58:35.012458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23868 10:58:35.012867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23870 10:58:35.056960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23871 10:58:35.057374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23873 10:58:35.101217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23874 10:58:35.101607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23876 10:58:35.134891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23877 10:58:35.135264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23879 10:58:35.180613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23880 10:58:35.181036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23882 10:58:35.226422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23884 10:58:35.226847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23885 10:58:35.268030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23886 10:58:35.268439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23888 10:58:35.304822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23889 10:58:35.305195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23891 10:58:35.345033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23892 10:58:35.345586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23894 10:58:35.389249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23895 10:58:35.389669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23897 10:58:35.434117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23899 10:58:35.434541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23900 10:58:35.477759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23902 10:58:35.478185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23903 10:58:35.528006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23905 10:58:35.528476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23906 10:58:35.575575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23907 10:58:35.576006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23909 10:58:35.621108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23911 10:58:35.621546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23912 10:58:35.666222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23914 10:58:35.666653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23915 10:58:35.712382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23916 10:58:35.712792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23918 10:58:35.759265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23919 10:58:35.759686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23921 10:58:35.804926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23922 10:58:35.805330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23924 10:58:35.850344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23926 10:58:35.850745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23927 10:58:35.895498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23928 10:58:35.895927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23930 10:58:35.940789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23931 10:58:35.941208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23933 10:58:35.986447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23935 10:58:35.986929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23936 10:58:36.031855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23938 10:58:36.032298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23939 10:58:36.078174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23940 10:58:36.078567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23942 10:58:36.124115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23943 10:58:36.124532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23945 10:58:36.171665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23946 10:58:36.172091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23948 10:58:36.217119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23949 10:58:36.217533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23951 10:58:36.263534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23952 10:58:36.263969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23954 10:58:36.308950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23955 10:58:36.309372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23957 10:58:36.350495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23959 10:58:36.350949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23960 10:58:36.396984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23961 10:58:36.397402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23963 10:58:36.443897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23964 10:58:36.444316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23966 10:58:36.479505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23967 10:58:36.479933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23969 10:58:36.525306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
23970 10:58:36.525686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
23972 10:58:36.571800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
23973 10:58:36.572202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
23975 10:58:36.616242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
23976 10:58:36.616649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
23978 10:58:36.663195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
23979 10:58:36.663617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
23981 10:58:36.708178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
23982 10:58:36.708588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
23984 10:58:36.745164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
23985 10:58:36.745570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
23987 10:58:36.790527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
23989 10:58:36.790963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
23990 10:58:36.837309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
23991 10:58:36.837700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
23993 10:58:36.884999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
23994 10:58:36.885410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
23996 10:58:36.931068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
23997 10:58:36.931480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
23999 10:58:36.976763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24000 10:58:36.977172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24002 10:58:37.025727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24003 10:58:37.026166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24005 10:58:37.073031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24007 10:58:37.073472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24008 10:58:37.116241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24009 10:58:37.116660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24011 10:58:37.161096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24012 10:58:37.161529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24014 10:58:37.208399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24015 10:58:37.208819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24017 10:58:37.255579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24018 10:58:37.255953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24020 10:58:37.301519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24021 10:58:37.301926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24023 10:58:37.347932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24024 10:58:37.348356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24026 10:58:37.393236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24027 10:58:37.393713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24029 10:58:37.438346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24031 10:58:37.438794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24032 10:58:37.486312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24034 10:58:37.486721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24035 10:58:37.530677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24037 10:58:37.531158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24038 10:58:37.576724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24039 10:58:37.577129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24041 10:58:37.621908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24042 10:58:37.622313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24044 10:58:37.664301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24045 10:58:37.664670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24047 10:58:37.707349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24049 10:58:37.707812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24050 10:58:37.752794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24051 10:58:37.753216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24053 10:58:37.798602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24055 10:58:37.799074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24056 10:58:37.843425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24058 10:58:37.843892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24059 10:58:37.888219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24060 10:58:37.888634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24062 10:58:37.941360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24063 10:58:37.941754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24065 10:58:37.988747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24066 10:58:37.989221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24068 10:58:38.031364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24069 10:58:38.031761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24071 10:58:38.076702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24073 10:58:38.077169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24074 10:58:38.121794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24075 10:58:38.122193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24077 10:58:38.165937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24078 10:58:38.166344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24080 10:58:38.212099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24081 10:58:38.212499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24083 10:58:38.257823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24084 10:58:38.258207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24086 10:58:38.305073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24087 10:58:38.305462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24089 10:58:38.352593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24091 10:58:38.353036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24092 10:58:38.400623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24093 10:58:38.401062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24095 10:58:38.450062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24096 10:58:38.450473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24098 10:58:38.499426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24099 10:58:38.499851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24101 10:58:38.548098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24103 10:58:38.548576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24104 10:58:38.597656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24105 10:58:38.598053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24107 10:58:38.644676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24109 10:58:38.645145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24110 10:58:38.691799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24111 10:58:38.692217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24113 10:58:38.736755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24114 10:58:38.737191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24116 10:58:38.784933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24117 10:58:38.785364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24119 10:58:38.831093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24120 10:58:38.831517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24122 10:58:38.875645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24124 10:58:38.876066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24125 10:58:38.920683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24126 10:58:38.921065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24128 10:58:38.966393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24130 10:58:38.966866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24131 10:58:39.014458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24133 10:58:39.014927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24134 10:58:39.060952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24135 10:58:39.061381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24137 10:58:39.107972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24139 10:58:39.108420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24140 10:58:39.153444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24141 10:58:39.157724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24143 10:58:39.200351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24145 10:58:39.200799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24146 10:58:39.247507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24147 10:58:39.247919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24149 10:58:39.294016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24150 10:58:39.294403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24152 10:58:39.333139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24153 10:58:39.333521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24155 10:58:39.367270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24156 10:58:39.367637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24158 10:58:39.400756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24159 10:58:39.401257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24161 10:58:39.434518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24163 10:58:39.435197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24164 10:58:39.469834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24165 10:58:39.470212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24167 10:58:39.504029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24168 10:58:39.504501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24170 10:58:39.537248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24171 10:58:39.537672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24173 10:58:39.570925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24174 10:58:39.571393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24176 10:58:39.607506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24177 10:58:39.607925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24179 10:58:39.644674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24180 10:58:39.645031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24182 10:58:39.676953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24183 10:58:39.677320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24185 10:58:39.720085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24186 10:58:39.720517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24188 10:58:39.760085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24189 10:58:39.760515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24191 10:58:39.807109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24192 10:58:39.807541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24194 10:58:39.844971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24195 10:58:39.845389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24197 10:58:39.886440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24199 10:58:39.886915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24200 10:58:39.927537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24202 10:58:39.927978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24203 10:58:39.972668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24204 10:58:39.973172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24206 10:58:40.018988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24207 10:58:40.019396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24209 10:58:40.065825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24210 10:58:40.066257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24212 10:58:40.111260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24214 10:58:40.111750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24215 10:58:40.156521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24216 10:58:40.156909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24218 10:58:40.204460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24220 10:58:40.204832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24221 10:58:40.241617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24222 10:58:40.242040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24224 10:58:40.281450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24225 10:58:40.281897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24227 10:58:40.325926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24228 10:58:40.326344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24230 10:58:40.372615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24231 10:58:40.373029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24233 10:58:40.420197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24234 10:58:40.420615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24236 10:58:40.468408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24237 10:58:40.468817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24239 10:58:40.509486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24241 10:58:40.509951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24242 10:58:40.556910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24244 10:58:40.557383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24245 10:58:40.602933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24246 10:58:40.603360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24248 10:58:40.651030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24249 10:58:40.651463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24251 10:58:40.695776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24252 10:58:40.696199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24254 10:58:40.742453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24256 10:58:40.742914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24257 10:58:40.787853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24259 10:58:40.788299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24260 10:58:40.834323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24262 10:58:40.834780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24263 10:58:40.879443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24265 10:58:40.879896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24266 10:58:40.926518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24268 10:58:40.926964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24269 10:58:40.971956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24270 10:58:40.972380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24272 10:58:41.018261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24273 10:58:41.018686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24275 10:58:41.053440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24276 10:58:41.053848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24278 10:58:41.097478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24279 10:58:41.097883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24281 10:58:41.143419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24283 10:58:41.143878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24284 10:58:41.187835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24285 10:58:41.188238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24287 10:58:41.220905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24288 10:58:41.221302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24290 10:58:41.265948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24291 10:58:41.266364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24293 10:58:41.307668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24295 10:58:41.308096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24296 10:58:41.352687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24297 10:58:41.353087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24299 10:58:41.386788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24300 10:58:41.387179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24302 10:58:41.431746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24303 10:58:41.432160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24305 10:58:41.475855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24306 10:58:41.476252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24308 10:58:41.509269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24310 10:58:41.509720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24311 10:58:41.553002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24312 10:58:41.553378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24314 10:58:41.595722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24315 10:58:41.596129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24317 10:58:41.641277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24318 10:58:41.641682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24320 10:58:41.687696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24321 10:58:41.688077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24323 10:58:41.734340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24325 10:58:41.734808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24326 10:58:41.780166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24327 10:58:41.780565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24329 10:58:41.825580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24331 10:58:41.826029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24332 10:58:41.870888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24333 10:58:41.871316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24335 10:58:41.915577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24336 10:58:41.916012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24338 10:58:41.960672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24339 10:58:41.961115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24341 10:58:42.007209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24342 10:58:42.007635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24344 10:58:42.051884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24346 10:58:42.052353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24347 10:58:42.096940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24348 10:58:42.097359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24350 10:58:42.141765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24351 10:58:42.142144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24353 10:58:42.187803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24354 10:58:42.188229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24356 10:58:42.226469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24358 10:58:42.226940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24359 10:58:42.272302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24360 10:58:42.272726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24362 10:58:42.317194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24363 10:58:42.317620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24365 10:58:42.350984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24366 10:58:42.351415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24368 10:58:42.390177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24370 10:58:42.390647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24371 10:58:42.436695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24372 10:58:42.437120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24374 10:58:42.484282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24375 10:58:42.484713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24377 10:58:42.532055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24379 10:58:42.532514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24380 10:58:42.577732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24381 10:58:42.581693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24383 10:58:42.623790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24384 10:58:42.624247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24386 10:58:42.671786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24387 10:58:42.672137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24389 10:58:42.718481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24391 10:58:42.718938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24392 10:58:42.763872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24393 10:58:42.764306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24395 10:58:42.812180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24396 10:58:42.812560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24398 10:58:42.864699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24399 10:58:42.865133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24401 10:58:42.911917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24402 10:58:42.912351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24404 10:58:42.956851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24405 10:58:42.957270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24407 10:58:43.001868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24408 10:58:43.002318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24410 10:58:43.068244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24411 10:58:43.068656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24413 10:58:43.114820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24414 10:58:43.115230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24416 10:58:43.160059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24418 10:58:43.160523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24419 10:58:43.206051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24420 10:58:43.206521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24422 10:58:43.249627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24424 10:58:43.250099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24425 10:58:43.285943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24426 10:58:43.286381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24428 10:58:43.333327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24430 10:58:43.333790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24431 10:58:43.379741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24432 10:58:43.380160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24434 10:58:43.424886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24436 10:58:43.425312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24437 10:58:43.471849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24438 10:58:43.472255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24440 10:58:43.517506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24441 10:58:43.517909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24443 10:58:43.564172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24444 10:58:43.564585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24446 10:58:43.609860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24447 10:58:43.610296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24449 10:58:43.659090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24450 10:58:43.659540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24452 10:58:43.704809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24453 10:58:43.705254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24455 10:58:43.750044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24456 10:58:43.750474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24458 10:58:43.797302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24459 10:58:43.797735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24461 10:58:43.841017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24462 10:58:43.841437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24464 10:58:43.886340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24466 10:58:43.886780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24467 10:58:43.932192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24468 10:58:43.932612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24470 10:58:43.980241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24471 10:58:43.980663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24473 10:58:44.029465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24474 10:58:44.029922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24476 10:58:44.077098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24478 10:58:44.077531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24479 10:58:44.124245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24480 10:58:44.124634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24482 10:58:44.171343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24484 10:58:44.171760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24485 10:58:44.218446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24487 10:58:44.219026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24488 10:58:44.267351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24489 10:58:44.267771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24491 10:58:44.317833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24492 10:58:44.318226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24494 10:58:44.365725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24495 10:58:44.366139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24497 10:58:44.415553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24498 10:58:44.415978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24500 10:58:44.461026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24501 10:58:44.461455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24503 10:58:44.507252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24505 10:58:44.507725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24506 10:58:44.555310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24507 10:58:44.555678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24509 10:58:44.604130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24510 10:58:44.604550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24512 10:58:44.646980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24514 10:58:44.647428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24515 10:58:44.693949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24516 10:58:44.694371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24518 10:58:44.738423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24520 10:58:44.738869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24521 10:58:44.787905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24522 10:58:44.788311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24524 10:58:44.832930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24525 10:58:44.833356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24527 10:58:44.876712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24528 10:58:44.877143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24530 10:58:44.924014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24531 10:58:44.924406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24533 10:58:44.971815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24534 10:58:44.972229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24536 10:58:45.018799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24537 10:58:45.019189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24539 10:58:45.067212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24540 10:58:45.067610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24542 10:58:45.112910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24543 10:58:45.113321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24545 10:58:45.160907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24547 10:58:45.161301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24548 10:58:45.210563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24550 10:58:45.211038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24551 10:58:45.259097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24553 10:58:45.259554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24554 10:58:45.297804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24555 10:58:45.298203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24557 10:58:45.343972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24558 10:58:45.344425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24560 10:58:45.393270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24561 10:58:45.393693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24563 10:58:45.440158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24564 10:58:45.440539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24566 10:58:45.486521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24568 10:58:45.486992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24569 10:58:45.532956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24570 10:58:45.533397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24572 10:58:45.582502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24574 10:58:45.582998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24575 10:58:45.631989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24576 10:58:45.632432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24578 10:58:45.680244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24579 10:58:45.680674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24581 10:58:45.728343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24582 10:58:45.728773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24584 10:58:45.778530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24586 10:58:45.778980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24587 10:58:45.825230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24589 10:58:45.825726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24590 10:58:45.871828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24591 10:58:45.872252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24593 10:58:45.917718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24594 10:58:45.918142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24596 10:58:45.963531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24597 10:58:45.963974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24599 10:58:46.008528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24600 10:58:46.008973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24602 10:58:46.047057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24604 10:58:46.047532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24605 10:58:46.094678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24607 10:58:46.095155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24608 10:58:46.143897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24609 10:58:46.144319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24611 10:58:46.188205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24613 10:58:46.188665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24614 10:58:46.235668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24615 10:58:46.236114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24617 10:58:46.283796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24618 10:58:46.284223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24620 10:58:46.331288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24621 10:58:46.331814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24623 10:58:46.376388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24624 10:58:46.376810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24626 10:58:46.409669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24627 10:58:46.410082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24629 10:58:46.458389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24631 10:58:46.458805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24632 10:58:46.510295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24634 10:58:46.510730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24635 10:58:46.561709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24636 10:58:46.562123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24638 10:58:46.613762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24640 10:58:46.614167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24641 10:58:46.668101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24642 10:58:46.668489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24644 10:58:46.722018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24646 10:58:46.722447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24647 10:58:46.773928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24648 10:58:46.774331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24650 10:58:46.825632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24651 10:58:46.826050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24653 10:58:46.880228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24654 10:58:46.880618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24656 10:58:46.933481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24657 10:58:46.933904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24659 10:58:46.985946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24660 10:58:46.986369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24662 10:58:47.038004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24663 10:58:47.038460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24665 10:58:47.090287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24666 10:58:47.090695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24668 10:58:47.144300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24669 10:58:47.144735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24671 10:58:47.199493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24672 10:58:47.199934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24674 10:58:47.254044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24675 10:58:47.254463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24677 10:58:47.309060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24679 10:58:47.309488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24680 10:58:47.363731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24682 10:58:47.364111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24683 10:58:47.417955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24684 10:58:47.418407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24686 10:58:47.472207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24688 10:58:47.472665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24689 10:58:47.515813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24690 10:58:47.516226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24692 10:58:47.564219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24693 10:58:47.564620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24695 10:58:47.615576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24696 10:58:47.615973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24698 10:58:47.664358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24699 10:58:47.664770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24701 10:58:47.709072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24702 10:58:47.709467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24704 10:58:47.755414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24706 10:58:47.755895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24707 10:58:47.802418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24709 10:58:47.802850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24710 10:58:47.850204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24711 10:58:47.850623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24713 10:58:47.898502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24715 10:58:47.898942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24716 10:58:47.946547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24718 10:58:47.946981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24719 10:58:47.995921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24720 10:58:47.996334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24722 10:58:48.045706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24723 10:58:48.046135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24725 10:58:48.089888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24726 10:58:48.090315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24728 10:58:48.142546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24730 10:58:48.150726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24731 10:58:48.216955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24732 10:58:48.217375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24734 10:58:48.265293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24735 10:58:48.265681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24737 10:58:48.313047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24738 10:58:48.313454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24740 10:58:48.369630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24741 10:58:48.370080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24743 10:58:48.416071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24744 10:58:48.416483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24746 10:58:48.467439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24748 10:58:48.467938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24749 10:58:48.516650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24750 10:58:48.517075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24752 10:58:48.565952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24754 10:58:48.566441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24755 10:58:48.613712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24756 10:58:48.614108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24758 10:58:48.664420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24759 10:58:48.664829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24761 10:58:48.713093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24762 10:58:48.713510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24764 10:58:48.762380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24766 10:58:48.762859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24767 10:58:48.811064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24769 10:58:48.811536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24770 10:58:48.859438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24771 10:58:48.859867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24773 10:58:48.907677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24774 10:58:48.908100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24776 10:58:48.958653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24778 10:58:48.959154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24779 10:58:49.009927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24780 10:58:49.010378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24782 10:58:49.055627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24783 10:58:49.056073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24785 10:58:49.106528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24787 10:58:49.107013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24788 10:58:49.151860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24789 10:58:49.152297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24791 10:58:49.201449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24792 10:58:49.205719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24794 10:58:49.261312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24795 10:58:49.261744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24797 10:58:49.322877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24799 10:58:49.323332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24800 10:58:49.364468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24801 10:58:49.364855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24803 10:58:49.402754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24804 10:58:49.403146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24806 10:58:49.445952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24807 10:58:49.446400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24809 10:58:49.488215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24810 10:58:49.488652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24812 10:58:49.537301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24813 10:58:49.537733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24815 10:58:49.588561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24816 10:58:49.588957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24818 10:58:49.640737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24820 10:58:49.641222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24821 10:58:49.693856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24822 10:58:49.694238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24824 10:58:49.744916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24825 10:58:49.745336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24827 10:58:49.795981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24828 10:58:49.796402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24830 10:58:49.845995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24831 10:58:49.846415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24833 10:58:49.896813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24834 10:58:49.897229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24836 10:58:49.948471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24838 10:58:49.949156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24839 10:58:50.006364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24841 10:58:50.006808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24842 10:58:50.049501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24843 10:58:50.049914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24845 10:58:50.084824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24846 10:58:50.085219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24848 10:58:50.120181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24849 10:58:50.120614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24851 10:58:50.158846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24852 10:58:50.159247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24854 10:58:50.205161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24855 10:58:50.205533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24857 10:58:50.241349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24858 10:58:50.241772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24860 10:58:50.288774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24862 10:58:50.289203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24863 10:58:50.340017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24864 10:58:50.340413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24866 10:58:50.393486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24867 10:58:50.393923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24869 10:58:50.448064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24870 10:58:50.448485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24872 10:58:50.496997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24873 10:58:50.497434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24875 10:58:50.545538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24876 10:58:50.545982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24878 10:58:50.597723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24879 10:58:50.598143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24881 10:58:50.648230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24882 10:58:50.648655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24884 10:58:50.696895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24885 10:58:50.697286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24887 10:58:50.743619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24888 10:58:50.744050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24890 10:58:50.796857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24891 10:58:50.797290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24893 10:58:50.847122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24895 10:58:50.847603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24896 10:58:50.897213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24897 10:58:50.897708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24899 10:58:50.951968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24901 10:58:50.952441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24902 10:58:50.999340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24903 10:58:50.999761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24905 10:58:51.046356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24907 10:58:51.047222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24908 10:58:51.097472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24909 10:58:51.097898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24911 10:58:51.147733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24912 10:58:51.148147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24914 10:58:51.197883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24915 10:58:51.198300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24917 10:58:51.248731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24918 10:58:51.249142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24920 10:58:51.296679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24921 10:58:51.297095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24923 10:58:51.347703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24924 10:58:51.348131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24926 10:58:51.397599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24927 10:58:51.398022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24929 10:58:51.452528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24930 10:58:51.452979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24932 10:58:51.497244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24933 10:58:51.497670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24935 10:58:51.540860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24936 10:58:51.541282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24938 10:58:51.589140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24939 10:58:51.589583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24941 10:58:51.625450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24942 10:58:51.625884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24944 10:58:51.676358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24945 10:58:51.676793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24947 10:58:51.727934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24948 10:58:51.728371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24950 10:58:51.776476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24952 10:58:51.776881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24953 10:58:51.820940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24954 10:58:51.821366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24956 10:58:51.875926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24957 10:58:51.876305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24959 10:58:51.931209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24960 10:58:51.931635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24962 10:58:51.970032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24963 10:58:51.970430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24965 10:58:52.010947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24966 10:58:52.011386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24968 10:58:52.063655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24969 10:58:52.064072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
24971 10:58:52.114052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
24972 10:58:52.114436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
24974 10:58:52.164461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
24975 10:58:52.164889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
24977 10:58:52.210360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
24979 10:58:52.210818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
24980 10:58:52.243963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
24981 10:58:52.244389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
24983 10:58:52.288159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
24985 10:58:52.288615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
24986 10:58:52.333872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
24988 10:58:52.334318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
24989 10:58:52.368521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
24990 10:58:52.368923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
24992 10:58:52.401150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
24993 10:58:52.401529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
24995 10:58:52.447113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
24996 10:58:52.447524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
24998 10:58:52.492633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
24999 10:58:52.493056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25001 10:58:52.537426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25003 10:58:52.538027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25004 10:58:52.583016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25005 10:58:52.583434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25007 10:58:52.627347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25008 10:58:52.627789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25010 10:58:52.672603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25011 10:58:52.673030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25013 10:58:52.720022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25014 10:58:52.720443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25016 10:58:52.765861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25017 10:58:52.766278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25019 10:58:52.811578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25020 10:58:52.812003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25022 10:58:52.856361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25023 10:58:52.856791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25025 10:58:52.901460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25026 10:58:52.901894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25028 10:58:52.948378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25029 10:58:52.948795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25031 10:58:52.993350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25032 10:58:52.993756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25034 10:58:53.037231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25035 10:58:53.037639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25037 10:58:53.083152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25038 10:58:53.083514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25040 10:58:53.128068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25042 10:58:53.128502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25043 10:58:53.172718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25044 10:58:53.173134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25046 10:58:53.217531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25047 10:58:53.217955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25049 10:58:53.262490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25051 10:58:53.270437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25052 10:58:53.333717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25053 10:58:53.334105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25055 10:58:53.379514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25056 10:58:53.379886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25058 10:58:53.424988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25059 10:58:53.425393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25061 10:58:53.465734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25062 10:58:53.466152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25064 10:58:53.499667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25065 10:58:53.500087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25067 10:58:53.547526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25068 10:58:53.547910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25070 10:58:53.595734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25071 10:58:53.596137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25073 10:58:53.642382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25075 10:58:53.642984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25076 10:58:53.687469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25077 10:58:53.687886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25079 10:58:53.732759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25080 10:58:53.733178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25082 10:58:53.778050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25083 10:58:53.778469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25085 10:58:53.820907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25086 10:58:53.821288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25088 10:58:53.866560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25090 10:58:53.867019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25091 10:58:53.912359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25092 10:58:53.912771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25094 10:58:53.956735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25095 10:58:53.957136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25097 10:58:54.007159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25098 10:58:54.007556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25100 10:58:54.056742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25101 10:58:54.057170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25103 10:58:54.097531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25104 10:58:54.097966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25106 10:58:54.138078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25108 10:58:54.138532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25109 10:58:54.180037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25110 10:58:54.180458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25112 10:58:54.226528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25114 10:58:54.226999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25115 10:58:54.276290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25116 10:58:54.276721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25118 10:58:54.324496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25119 10:58:54.324896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25121 10:58:54.372737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25122 10:58:54.373146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25124 10:58:54.420507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25126 10:58:54.420944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25127 10:58:54.465804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25128 10:58:54.466200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25130 10:58:54.511712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25131 10:58:54.512129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25133 10:58:54.558405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25135 10:58:54.558854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25136 10:58:54.602249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25138 10:58:54.602670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25139 10:58:54.634998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25140 10:58:54.635396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25142 10:58:54.676884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25143 10:58:54.677295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25145 10:58:54.723153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25146 10:58:54.723562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25148 10:58:54.768671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25149 10:58:54.769072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25151 10:58:54.802433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25153 10:58:54.802843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25154 10:58:54.847831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25155 10:58:54.848229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25157 10:58:54.893362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25158 10:58:54.893744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25160 10:58:54.939724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25161 10:58:54.940130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25163 10:58:54.977414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25164 10:58:54.977845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25166 10:58:55.012653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25167 10:58:55.013028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25169 10:58:55.053532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25170 10:58:55.053946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25172 10:58:55.099920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25173 10:58:55.100331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25175 10:58:55.144989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25176 10:58:55.145388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25178 10:58:55.189769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25179 10:58:55.190185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25181 10:58:55.231301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25182 10:58:55.231718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25184 10:58:55.279295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25185 10:58:55.279717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25187 10:58:55.313925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25188 10:58:55.314319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25190 10:58:55.353483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25192 10:58:55.353919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25193 10:58:55.397591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25195 10:58:55.398021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25196 10:58:55.437622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25197 10:58:55.438030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25199 10:58:55.476991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25201 10:58:55.477425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25202 10:58:55.522802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25203 10:58:55.523211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25205 10:58:55.568993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25206 10:58:55.569402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25208 10:58:55.616522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25209 10:58:55.616946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25211 10:58:55.663609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25212 10:58:55.664042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25214 10:58:55.709129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25215 10:58:55.709557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25217 10:58:55.744392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25219 10:58:55.744745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25220 10:58:55.779167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25221 10:58:55.779593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25223 10:58:55.819342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25224 10:58:55.819763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25226 10:58:55.855079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25227 10:58:55.855521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25229 10:58:55.890553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25231 10:58:55.890991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25232 10:58:55.935732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25233 10:58:55.936097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25235 10:58:55.981640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25237 10:58:55.982066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25238 10:58:56.028529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25240 10:58:56.028960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25241 10:58:56.067466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25242 10:58:56.067892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25244 10:58:56.102427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25246 10:58:56.102802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25247 10:58:56.148521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25248 10:58:56.148956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25250 10:58:56.197956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25251 10:58:56.198380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25253 10:58:56.244731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25254 10:58:56.245163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25256 10:58:56.291246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25258 10:58:56.291613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25259 10:58:56.325144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25261 10:58:56.325596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25262 10:58:56.374270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25264 10:58:56.374710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25265 10:58:56.420092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25266 10:58:56.420532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25268 10:58:56.457391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25269 10:58:56.457812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25271 10:58:56.503923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25272 10:58:56.504348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25274 10:58:56.549495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25276 10:58:56.549979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25277 10:58:56.595638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25278 10:58:56.596052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25280 10:58:56.641562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25281 10:58:56.641987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25283 10:58:56.689308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25285 10:58:56.689767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25286 10:58:56.735688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25287 10:58:56.736126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25289 10:58:56.780563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25290 10:58:56.780974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25292 10:58:56.825306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25293 10:58:56.825740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25295 10:58:56.869217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25297 10:58:56.869709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25298 10:58:56.911342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25300 10:58:56.911735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25301 10:58:56.958053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25303 10:58:56.958519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25304 10:58:56.993699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25305 10:58:56.994134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25307 10:58:57.034063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25308 10:58:57.034500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25310 10:58:57.079017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25312 10:58:57.079408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25313 10:58:57.124354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25315 10:58:57.124802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25316 10:58:57.171140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25317 10:58:57.171574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25319 10:58:57.215866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25320 10:58:57.216320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25322 10:58:57.251632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25323 10:58:57.252019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25325 10:58:57.296708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25326 10:58:57.297136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25328 10:58:57.339651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25329 10:58:57.340091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25331 10:58:57.384456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25332 10:58:57.384882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25334 10:58:57.423554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25335 10:58:57.423965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25337 10:58:57.463790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25338 10:58:57.464214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25340 10:58:57.509851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25341 10:58:57.510284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25343 10:58:57.555451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25344 10:58:57.555869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25346 10:58:57.589916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25347 10:58:57.590339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25349 10:58:57.635914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25350 10:58:57.636337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25352 10:58:57.675364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25353 10:58:57.675772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25355 10:58:57.719060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25356 10:58:57.719500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25358 10:58:57.765230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25359 10:58:57.765676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25361 10:58:57.811874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25362 10:58:57.812298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25364 10:58:57.856931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25365 10:58:57.857366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25367 10:58:57.903960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25369 10:58:57.904411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25370 10:58:57.948862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25371 10:58:57.949280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25373 10:58:57.993688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25374 10:58:57.994094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25376 10:58:58.039738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25377 10:58:58.040159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25379 10:58:58.087857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25380 10:58:58.088302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25382 10:58:58.134638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25384 10:58:58.135126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25385 10:58:58.181254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25386 10:58:58.181678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25388 10:58:58.228114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25389 10:58:58.228545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25391 10:58:58.275823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25392 10:58:58.276236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25394 10:58:58.323153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25395 10:58:58.323565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25397 10:58:58.370878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25398 10:58:58.371285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25400 10:58:58.443118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25401 10:58:58.443536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25403 10:58:58.491392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25404 10:58:58.491822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25406 10:58:58.537551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25407 10:58:58.537994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25409 10:58:58.584239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25411 10:58:58.584673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25412 10:58:58.632622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25413 10:58:58.633054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25415 10:58:58.679245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25416 10:58:58.679689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25418 10:58:58.727338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25419 10:58:58.727747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25421 10:58:58.775009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25423 10:58:58.775501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25424 10:58:58.821551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25425 10:58:58.822004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25427 10:58:58.868093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25428 10:58:58.868510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25430 10:58:58.907591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25431 10:58:58.908007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25433 10:58:58.952371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25434 10:58:58.952776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25436 10:58:58.993783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25438 10:58:58.994245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25439 10:58:59.035413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25440 10:58:59.035804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25442 10:58:59.083113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25444 10:58:59.083526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25445 10:58:59.129905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25447 10:58:59.130352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25448 10:58:59.178921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25449 10:58:59.179321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25451 10:58:59.223611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25452 10:58:59.224013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25454 10:58:59.260256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25456 10:58:59.260696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25457 10:58:59.303143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25458 10:58:59.303573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25460 10:58:59.357708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25461 10:58:59.358114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25463 10:58:59.405385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25464 10:58:59.405823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25466 10:58:59.452191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25468 10:58:59.452646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25469 10:58:59.498412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25471 10:58:59.498965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25472 10:58:59.545054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25473 10:58:59.545479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25475 10:58:59.592347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25476 10:58:59.592754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25478 10:58:59.637973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25479 10:58:59.638422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25481 10:58:59.683725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25482 10:58:59.684165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25484 10:58:59.729593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25486 10:58:59.730052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25487 10:58:59.777073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25489 10:58:59.777505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25490 10:58:59.829561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25491 10:58:59.830002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25493 10:58:59.877635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25494 10:58:59.878072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25496 10:58:59.926365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25498 10:58:59.926739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25499 10:58:59.977016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25500 10:58:59.977474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25502 10:59:00.027833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25503 10:59:00.028281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25505 10:59:00.076167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25506 10:59:00.076561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25508 10:59:00.123606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25509 10:59:00.124046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25511 10:59:00.172102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25512 10:59:00.172529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25514 10:59:00.219548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25515 10:59:00.219941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25517 10:59:00.265626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25518 10:59:00.266032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25520 10:59:00.311630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25521 10:59:00.312036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25523 10:59:00.359389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25524 10:59:00.359826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25526 10:59:00.404951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25527 10:59:00.405403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25529 10:59:00.450983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25531 10:59:00.451418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25532 10:59:00.496911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25533 10:59:00.497357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25535 10:59:00.543946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25536 10:59:00.544372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25538 10:59:00.590861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25539 10:59:00.591277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25541 10:59:00.636287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25543 10:59:00.636716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25544 10:59:00.683460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25545 10:59:00.683853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25547 10:59:00.730245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25549 10:59:00.730717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25550 10:59:00.777067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25551 10:59:00.777452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25553 10:59:00.824097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25554 10:59:00.824463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25556 10:59:00.871639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25557 10:59:00.872058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25559 10:59:00.917386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25560 10:59:00.917803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25562 10:59:00.964787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25563 10:59:00.965207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25565 10:59:01.011633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25566 10:59:01.012055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25568 10:59:01.057428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25569 10:59:01.057860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25571 10:59:01.106342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25573 10:59:01.106832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25574 10:59:01.153151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25575 10:59:01.153580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25577 10:59:01.196956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25578 10:59:01.197380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25580 10:59:01.251000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25581 10:59:01.251467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25583 10:59:01.299706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25584 10:59:01.300133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25586 10:59:01.347944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25587 10:59:01.348378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25589 10:59:01.396803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25590 10:59:01.397222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25592 10:59:01.444442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25593 10:59:01.444846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25595 10:59:01.491779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25596 10:59:01.492209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25598 10:59:01.537817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25599 10:59:01.538177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25601 10:59:01.583548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25602 10:59:01.583965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25604 10:59:01.631705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25606 10:59:01.632177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25607 10:59:01.678036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25608 10:59:01.678450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25610 10:59:01.725031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25611 10:59:01.725448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25613 10:59:01.771493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25614 10:59:01.771875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25616 10:59:01.816342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25617 10:59:01.816730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25619 10:59:01.855203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25621 10:59:01.855665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25622 10:59:01.901171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25623 10:59:01.901585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25625 10:59:01.947569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25626 10:59:01.947945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25628 10:59:01.992354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25629 10:59:01.992799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25631 10:59:02.039671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25633 10:59:02.040136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25634 10:59:02.085214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25635 10:59:02.085675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25637 10:59:02.131530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25638 10:59:02.131990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25640 10:59:02.177829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25642 10:59:02.178286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25643 10:59:02.224979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25644 10:59:02.225346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25646 10:59:02.271368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25648 10:59:02.271804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25649 10:59:02.317949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25650 10:59:02.318359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25652 10:59:02.364171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25653 10:59:02.364562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25655 10:59:02.409697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25656 10:59:02.410120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25658 10:59:02.456074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25660 10:59:02.456525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25661 10:59:02.505542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25663 10:59:02.505998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25664 10:59:02.555504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25666 10:59:02.555952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25667 10:59:02.605723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25668 10:59:02.606170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25670 10:59:02.653563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25672 10:59:02.654081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25673 10:59:02.700420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25674 10:59:02.700857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25676 10:59:02.747440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25677 10:59:02.747869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25679 10:59:02.793977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25680 10:59:02.794379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25682 10:59:02.839955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25684 10:59:02.840418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25685 10:59:02.885097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25686 10:59:02.885518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25688 10:59:02.929237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25689 10:59:02.929640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25691 10:59:02.976082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25692 10:59:02.976521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25694 10:59:03.022300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25696 10:59:03.022732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25697 10:59:03.073498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25698 10:59:03.073946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25700 10:59:03.122149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25701 10:59:03.122551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25703 10:59:03.169012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25704 10:59:03.169438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25706 10:59:03.215518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25707 10:59:03.215941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25709 10:59:03.261071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25710 10:59:03.261477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25712 10:59:03.306102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25713 10:59:03.306521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25715 10:59:03.352228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25716 10:59:03.352661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25718 10:59:03.397338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25719 10:59:03.397772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25721 10:59:03.441224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25722 10:59:03.441642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25724 10:59:03.487682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25726 10:59:03.488125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25727 10:59:03.556359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25729 10:59:03.556834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25730 10:59:03.602559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25732 10:59:03.603032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25733 10:59:03.649274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25734 10:59:03.649692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25736 10:59:03.695648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25737 10:59:03.696053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25739 10:59:03.743572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25740 10:59:03.743991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25742 10:59:03.790010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25743 10:59:03.790527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25745 10:59:03.837704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25747 10:59:03.838160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25748 10:59:03.885414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25749 10:59:03.885814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25751 10:59:03.931571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25752 10:59:03.932011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25754 10:59:03.977352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25755 10:59:03.977780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25757 10:59:04.024699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25758 10:59:04.025153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25760 10:59:04.072176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25761 10:59:04.072622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25763 10:59:04.120686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25765 10:59:04.121159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25766 10:59:04.168357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25768 10:59:04.168812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25769 10:59:04.216221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25770 10:59:04.216651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25772 10:59:04.261715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25774 10:59:04.262199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25775 10:59:04.315973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25776 10:59:04.316422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25778 10:59:04.367990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25779 10:59:04.368414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25781 10:59:04.421156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25782 10:59:04.421590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25784 10:59:04.464361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25785 10:59:04.464782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25787 10:59:04.502043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25788 10:59:04.502422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25790 10:59:04.545381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25792 10:59:04.545818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25793 10:59:04.593011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25795 10:59:04.593374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25796 10:59:04.642240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25798 10:59:04.642688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25799 10:59:04.690413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25801 10:59:04.690867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25802 10:59:04.739537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25803 10:59:04.739957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25805 10:59:04.787645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25806 10:59:04.788074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25808 10:59:04.835586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25810 10:59:04.836032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25811 10:59:04.882202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25812 10:59:04.882639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25814 10:59:04.928740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25815 10:59:04.929187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25817 10:59:04.975048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25818 10:59:04.975493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25820 10:59:05.023848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25822 10:59:05.024295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25823 10:59:05.071593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25824 10:59:05.072012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25826 10:59:05.117221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25827 10:59:05.117635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25829 10:59:05.163998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25831 10:59:05.164464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25832 10:59:05.209517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25833 10:59:05.209940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25835 10:59:05.256939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25836 10:59:05.257376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25838 10:59:05.301639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25839 10:59:05.302076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25841 10:59:05.348631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25842 10:59:05.349048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25844 10:59:05.395691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25845 10:59:05.396099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25847 10:59:05.441153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25848 10:59:05.441545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25850 10:59:05.487337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25851 10:59:05.487745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25853 10:59:05.532072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25854 10:59:05.532496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25856 10:59:05.580646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25858 10:59:05.581015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25859 10:59:05.626930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25860 10:59:05.627355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25862 10:59:05.673068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25863 10:59:05.673447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25865 10:59:05.716524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25866 10:59:05.716955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25868 10:59:05.762846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25869 10:59:05.763242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25871 10:59:05.811386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25872 10:59:05.811792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25874 10:59:05.859415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25876 10:59:05.859807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25877 10:59:05.908554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25879 10:59:05.908970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25880 10:59:05.955527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25881 10:59:05.955945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25883 10:59:05.999698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25884 10:59:06.000091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25886 10:59:06.047440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25887 10:59:06.047833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25889 10:59:06.095691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25890 10:59:06.096093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25892 10:59:06.145139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25893 10:59:06.145541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25895 10:59:06.192045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25896 10:59:06.192442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25898 10:59:06.239988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25899 10:59:06.240382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25901 10:59:06.284384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25903 10:59:06.284793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25904 10:59:06.329112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25905 10:59:06.329858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25907 10:59:06.375159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25908 10:59:06.375586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25910 10:59:06.421449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25911 10:59:06.421915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25913 10:59:06.468155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25914 10:59:06.468583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25916 10:59:06.515531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25918 10:59:06.515981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25919 10:59:06.562143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25920 10:59:06.562569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25922 10:59:06.607765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25923 10:59:06.608206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25925 10:59:06.655218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25926 10:59:06.655672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25928 10:59:06.704539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25930 10:59:06.705027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25931 10:59:06.752077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25932 10:59:06.752507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25934 10:59:06.799046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25935 10:59:06.799476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25937 10:59:06.844896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25938 10:59:06.845296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25940 10:59:06.892300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25941 10:59:06.892755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25943 10:59:06.938691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25945 10:59:06.939183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25946 10:59:06.984826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25947 10:59:06.985254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25949 10:59:07.031864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25950 10:59:07.032280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25952 10:59:07.077565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25953 10:59:07.077987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25955 10:59:07.124886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25957 10:59:07.125346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25958 10:59:07.172726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25959 10:59:07.173173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25961 10:59:07.220162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25962 10:59:07.220589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25964 10:59:07.267900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25966 10:59:07.268349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25967 10:59:07.314907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25968 10:59:07.315324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
25970 10:59:07.359794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
25971 10:59:07.360164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
25973 10:59:07.407101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
25974 10:59:07.407511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
25976 10:59:07.453161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
25977 10:59:07.453565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
25979 10:59:07.500408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
25980 10:59:07.500807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
25982 10:59:07.547584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
25983 10:59:07.547977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
25985 10:59:07.594382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
25987 10:59:07.594852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
25988 10:59:07.640325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
25989 10:59:07.640752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
25991 10:59:07.687763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
25992 10:59:07.688212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
25994 10:59:07.734558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
25996 10:59:07.735037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
25997 10:59:07.781317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
25998 10:59:07.781736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
26000 10:59:07.827863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26001 10:59:07.828277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26003 10:59:07.875414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26005 10:59:07.875845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26006 10:59:07.921115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26007 10:59:07.921518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26009 10:59:07.967665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26010 10:59:07.968055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26012 10:59:08.013469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26013 10:59:08.013850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26015 10:59:08.059885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26016 10:59:08.060308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26018 10:59:08.107592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26019 10:59:08.108015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26021 10:59:08.155057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26022 10:59:08.155487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26024 10:59:08.201901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26025 10:59:08.202290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26027 10:59:08.249431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26028 10:59:08.249807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26030 10:59:08.296239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26032 10:59:08.296677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26033 10:59:08.343844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26034 10:59:08.344243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26036 10:59:08.390731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26037 10:59:08.391137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26039 10:59:08.437562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26040 10:59:08.437993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26042 10:59:08.484028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26043 10:59:08.484400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26045 10:59:08.530898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26046 10:59:08.531348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26048 10:59:08.578252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26050 10:59:08.578670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26051 10:59:08.640154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26052 10:59:08.640585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26054 10:59:08.693878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26055 10:59:08.694276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26057 10:59:08.740658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26058 10:59:08.741080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26060 10:59:08.788043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26061 10:59:08.788440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26063 10:59:08.835798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26064 10:59:08.836217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26066 10:59:08.882333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26068 10:59:08.882786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26069 10:59:08.930208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26070 10:59:08.930624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26072 10:59:08.976038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26073 10:59:08.976457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26075 10:59:09.005708 <47>[ 300.390587] systemd-journald[109]: Sent WATCHDOG=1 notification.
26076 10:59:09.029569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26077 10:59:09.029993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26079 10:59:09.078025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26080 10:59:09.078457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26082 10:59:09.128134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26083 10:59:09.128561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26085 10:59:09.176811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26086 10:59:09.177244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26088 10:59:09.225492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26090 10:59:09.225965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26091 10:59:09.273405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26092 10:59:09.277700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26094 10:59:09.320848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26095 10:59:09.321214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26097 10:59:09.370149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26099 10:59:09.370626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26100 10:59:09.416445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26101 10:59:09.416866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26103 10:59:09.464287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26104 10:59:09.464716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26106 10:59:09.513020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26107 10:59:09.513425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26109 10:59:09.562098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26110 10:59:09.562517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26112 10:59:09.608199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26113 10:59:09.608616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26115 10:59:09.654435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26117 10:59:09.654893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26118 10:59:09.700284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26120 10:59:09.700736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26121 10:59:09.746926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26122 10:59:09.747343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26124 10:59:09.794427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26126 10:59:09.794887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26127 10:59:09.840647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26128 10:59:09.841058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26130 10:59:09.888043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26131 10:59:09.888458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26133 10:59:09.935195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26135 10:59:09.935645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26136 10:59:09.981424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26137 10:59:09.981822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26139 10:59:10.027848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26140 10:59:10.028246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26142 10:59:10.076581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26143 10:59:10.076999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26145 10:59:10.123133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26146 10:59:10.123565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26148 10:59:10.172475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26149 10:59:10.172904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26151 10:59:10.218438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26153 10:59:10.218895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26154 10:59:10.264519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26156 10:59:10.264967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26157 10:59:10.311432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26158 10:59:10.311874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26160 10:59:10.357149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26161 10:59:10.357587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26163 10:59:10.403721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26164 10:59:10.404131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26166 10:59:10.452111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26167 10:59:10.452465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26169 10:59:10.497575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26170 10:59:10.497982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26172 10:59:10.545005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26173 10:59:10.545414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26175 10:59:10.592025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26176 10:59:10.592428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26178 10:59:10.638138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26179 10:59:10.638535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26181 10:59:10.683616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26182 10:59:10.684004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26184 10:59:10.727874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26185 10:59:10.728268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26187 10:59:10.774716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26189 10:59:10.775530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26190 10:59:10.823203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26192 10:59:10.823671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26193 10:59:10.869127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26194 10:59:10.869554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26196 10:59:10.916054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26198 10:59:10.916524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26199 10:59:10.964368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26200 10:59:10.964781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26202 10:59:11.013005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26203 10:59:11.013418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26205 10:59:11.061605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26206 10:59:11.062028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26208 10:59:11.108332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26209 10:59:11.108739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26211 10:59:11.155860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26213 10:59:11.156300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26214 10:59:11.202423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26216 10:59:11.202868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26217 10:59:11.244824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26218 10:59:11.245233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26220 10:59:11.285994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26221 10:59:11.286401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26223 10:59:11.324428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26224 10:59:11.324860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26226 10:59:11.370398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26228 10:59:11.371004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26229 10:59:11.416029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26230 10:59:11.416442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26232 10:59:11.461165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26233 10:59:11.461575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26235 10:59:11.499341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26236 10:59:11.499759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26238 10:59:11.545544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26239 10:59:11.545977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26241 10:59:11.592224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26243 10:59:11.592678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26244 10:59:11.638851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26245 10:59:11.639286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26247 10:59:11.683833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26248 10:59:11.684255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26250 10:59:11.729821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26251 10:59:11.730232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26253 10:59:11.772853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26254 10:59:11.773283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26256 10:59:11.817902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26257 10:59:11.818343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26259 10:59:11.865063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26261 10:59:11.865569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26262 10:59:11.911805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26263 10:59:11.912219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26265 10:59:11.956840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26266 10:59:11.957283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26268 10:59:11.997420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26270 10:59:11.997841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26271 10:59:12.043617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26272 10:59:12.044029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26274 10:59:12.086435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26276 10:59:12.086886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26277 10:59:12.133824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26278 10:59:12.134240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26280 10:59:12.176546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26281 10:59:12.176959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26283 10:59:12.224023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26284 10:59:12.224454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26286 10:59:12.269816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26287 10:59:12.270238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26289 10:59:12.316732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26291 10:59:12.317129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26292 10:59:12.365048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26293 10:59:12.365489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26295 10:59:12.413293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26297 10:59:12.413771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26298 10:59:12.462112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26300 10:59:12.462608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26301 10:59:12.511128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26302 10:59:12.511487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26304 10:59:12.556544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26305 10:59:12.556947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26307 10:59:12.604893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26308 10:59:12.605332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26310 10:59:12.652734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26312 10:59:12.653205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26313 10:59:12.702140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26314 10:59:12.702532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26316 10:59:12.749526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26317 10:59:12.749965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26319 10:59:12.792366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26320 10:59:12.792766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26322 10:59:12.831685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26323 10:59:12.832073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26325 10:59:12.876288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26326 10:59:12.876705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26328 10:59:12.920169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26329 10:59:12.920589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26331 10:59:12.966065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26332 10:59:12.966472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26334 10:59:13.007576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26335 10:59:13.008001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26337 10:59:13.052277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26338 10:59:13.052704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26340 10:59:13.099679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26341 10:59:13.100119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26343 10:59:13.145595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26345 10:59:13.146056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26346 10:59:13.191157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26348 10:59:13.191605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26349 10:59:13.236087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26350 10:59:13.236522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26352 10:59:13.275210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26353 10:59:13.275648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26355 10:59:13.320398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26356 10:59:13.320814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26358 10:59:13.365808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26359 10:59:13.366235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26361 10:59:13.413602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26362 10:59:13.414042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26364 10:59:13.460145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26365 10:59:13.460603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26367 10:59:13.507438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26368 10:59:13.507816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26370 10:59:13.553289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26371 10:59:13.553679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26373 10:59:13.595341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26374 10:59:13.595764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26376 10:59:13.635630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26377 10:59:13.636043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26379 10:59:13.670118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26381 10:59:13.670560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26382 10:59:13.711318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26383 10:59:13.711720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26385 10:59:13.775807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26386 10:59:13.776224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26388 10:59:13.817452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26389 10:59:13.817893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26391 10:59:13.863637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26392 10:59:13.864052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26394 10:59:13.908867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26395 10:59:13.909297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26397 10:59:13.955955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26399 10:59:13.956392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26400 10:59:14.000799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26401 10:59:14.001234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26403 10:59:14.046958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26404 10:59:14.047418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26406 10:59:14.091815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26407 10:59:14.092256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26409 10:59:14.138449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26411 10:59:14.139146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26412 10:59:14.184602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26413 10:59:14.185032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26415 10:59:14.231314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26416 10:59:14.231724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26418 10:59:14.277873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26419 10:59:14.281688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26421 10:59:14.324717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26422 10:59:14.325143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26424 10:59:14.371993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26425 10:59:14.372413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26427 10:59:14.419702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26428 10:59:14.420055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26430 10:59:14.467240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26431 10:59:14.467661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26433 10:59:14.515204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26435 10:59:14.515656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26436 10:59:14.561829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26437 10:59:14.562248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26439 10:59:14.607943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26441 10:59:14.608379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26442 10:59:14.653106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26444 10:59:14.653551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26445 10:59:14.698037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26446 10:59:14.698419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26448 10:59:14.743698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26449 10:59:14.744118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26451 10:59:14.789007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26452 10:59:14.789388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26454 10:59:14.833991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26455 10:59:14.834433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26457 10:59:14.879930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26459 10:59:14.880301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26460 10:59:14.923965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26462 10:59:14.924428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26463 10:59:14.968399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26464 10:59:14.968832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26466 10:59:15.014884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26467 10:59:15.015313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26469 10:59:15.060182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26470 10:59:15.060619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26472 10:59:15.104570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26473 10:59:15.104978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26475 10:59:15.150178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26476 10:59:15.150596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26478 10:59:15.196072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26480 10:59:15.196520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26481 10:59:15.241714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26482 10:59:15.242124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26484 10:59:15.280977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26485 10:59:15.281403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26487 10:59:15.323622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26488 10:59:15.324015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26490 10:59:15.367712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26491 10:59:15.368131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26493 10:59:15.413338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26494 10:59:15.413753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26496 10:59:15.458346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26498 10:59:15.458787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26499 10:59:15.503789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26500 10:59:15.504220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26502 10:59:15.548949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26504 10:59:15.549388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26505 10:59:15.594297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26507 10:59:15.594723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26508 10:59:15.640440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26509 10:59:15.640845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26511 10:59:15.686900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26512 10:59:15.687316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26514 10:59:15.730867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26515 10:59:15.731281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26517 10:59:15.775699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26519 10:59:15.776184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26520 10:59:15.820675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26521 10:59:15.821115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26523 10:59:15.866090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26524 10:59:15.866507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26526 10:59:15.911263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26527 10:59:15.911692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26529 10:59:15.956808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26530 10:59:15.957226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26532 10:59:16.003147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26534 10:59:16.003638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26535 10:59:16.048084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26536 10:59:16.048487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26538 10:59:16.093156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26539 10:59:16.093585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26541 10:59:16.139411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26542 10:59:16.139835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26544 10:59:16.184918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26545 10:59:16.185349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26547 10:59:16.229774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26548 10:59:16.230150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26550 10:59:16.276389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26552 10:59:16.276829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26553 10:59:16.320933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26554 10:59:16.321353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26556 10:59:16.365350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26557 10:59:16.365745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26559 10:59:16.411714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26560 10:59:16.412151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26562 10:59:16.456898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26563 10:59:16.457336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26565 10:59:16.503494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26566 10:59:16.503936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26568 10:59:16.548651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26570 10:59:16.549093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26571 10:59:16.595173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26572 10:59:16.595595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26574 10:59:16.641223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26575 10:59:16.641638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26577 10:59:16.683475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26578 10:59:16.683888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26580 10:59:16.717874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26581 10:59:16.718255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26583 10:59:16.764220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26584 10:59:16.764585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26586 10:59:16.808063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26587 10:59:16.808465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26589 10:59:16.853720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26590 10:59:16.854128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26592 10:59:16.899883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26593 10:59:16.900371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26595 10:59:16.945216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26596 10:59:16.945632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26598 10:59:16.989496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26599 10:59:16.989836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26601 10:59:17.032058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26603 10:59:17.032493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26604 10:59:17.076687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26605 10:59:17.077091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26607 10:59:17.123046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26609 10:59:17.123482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26610 10:59:17.168950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26611 10:59:17.169364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26613 10:59:17.215826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26614 10:59:17.216259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26616 10:59:17.260967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26617 10:59:17.261402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26619 10:59:17.306549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26621 10:59:17.307026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26622 10:59:17.345205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26623 10:59:17.345600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26625 10:59:17.391477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26626 10:59:17.391895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26628 10:59:17.437839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26630 10:59:17.438317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26631 10:59:17.472350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26632 10:59:17.472781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26634 10:59:17.509170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26636 10:59:17.509606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26637 10:59:17.555008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26639 10:59:17.555447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26640 10:59:17.597302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26641 10:59:17.597682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26643 10:59:17.640614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26644 10:59:17.641041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26646 10:59:17.690908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26647 10:59:17.691308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26649 10:59:17.737253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26651 10:59:17.737695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26652 10:59:17.784154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26653 10:59:17.784568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26655 10:59:17.829505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26656 10:59:17.829904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26658 10:59:17.875615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26659 10:59:17.876006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26661 10:59:17.922154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26663 10:59:17.922569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26664 10:59:17.967109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26665 10:59:17.967500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26667 10:59:18.000429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26668 10:59:18.000856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26670 10:59:18.037813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26671 10:59:18.038237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26673 10:59:18.083745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26674 10:59:18.084129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26676 10:59:18.127529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26677 10:59:18.127934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26679 10:59:18.172482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26680 10:59:18.172903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26682 10:59:18.209544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26683 10:59:18.209970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26685 10:59:18.255780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26686 10:59:18.256148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26688 10:59:18.288424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26689 10:59:18.288842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26691 10:59:18.336813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26692 10:59:18.337248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26694 10:59:18.383191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26695 10:59:18.383625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26697 10:59:18.428034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26699 10:59:18.428494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26700 10:59:18.471908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26701 10:59:18.472325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26703 10:59:18.516551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26704 10:59:18.516965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26706 10:59:18.561836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26707 10:59:18.562251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26709 10:59:18.608000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26710 10:59:18.608434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26712 10:59:18.647155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26713 10:59:18.647591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26715 10:59:18.681786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26717 10:59:18.682236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26718 10:59:18.715746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26719 10:59:18.716131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26721 10:59:18.761191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26722 10:59:18.761583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26724 10:59:18.806813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26725 10:59:18.807240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26727 10:59:18.852019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26728 10:59:18.852461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26730 10:59:18.908206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26731 10:59:18.908606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26733 10:59:18.942922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26734 10:59:18.943335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26736 10:59:18.987656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26737 10:59:18.988043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26739 10:59:19.023686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26741 10:59:19.024135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26742 10:59:19.073426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26743 10:59:19.073809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26745 10:59:19.125072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26746 10:59:19.125508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26748 10:59:19.176494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26750 10:59:19.176956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26751 10:59:19.223600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26752 10:59:19.224026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26754 10:59:19.268933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26755 10:59:19.269353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26757 10:59:19.315441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26758 10:59:19.315872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26760 10:59:19.368433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26761 10:59:19.368873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26763 10:59:19.420505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26764 10:59:19.420907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26766 10:59:19.468311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26768 10:59:19.468773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26769 10:59:19.517613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26771 10:59:19.518034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26772 10:59:19.557717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26773 10:59:19.558130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26775 10:59:19.603467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26776 10:59:19.603879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26778 10:59:19.647891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26779 10:59:19.648296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26781 10:59:19.683514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26782 10:59:19.683906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26784 10:59:19.723838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26785 10:59:19.724263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26787 10:59:19.768826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26788 10:59:19.769272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26790 10:59:19.815858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26791 10:59:19.816285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26793 10:59:19.861096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26795 10:59:19.861564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26796 10:59:19.909120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26797 10:59:19.909496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26799 10:59:19.956220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26800 10:59:19.956649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26802 10:59:20.003862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26803 10:59:20.004292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26805 10:59:20.050311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26807 10:59:20.050793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26808 10:59:20.084659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26810 10:59:20.085119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26811 10:59:20.125722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26812 10:59:20.126150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26814 10:59:20.170294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26815 10:59:20.170629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26817 10:59:20.216756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26819 10:59:20.217187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26820 10:59:20.260068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26821 10:59:20.260438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26823 10:59:20.301708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26824 10:59:20.302116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26826 10:59:20.342944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26827 10:59:20.343362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26829 10:59:20.387044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26830 10:59:20.387462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26832 10:59:20.431732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26833 10:59:20.432150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26835 10:59:20.477102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26836 10:59:20.477525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26838 10:59:20.523801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26839 10:59:20.524225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26841 10:59:20.569214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26842 10:59:20.569641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26844 10:59:20.615333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26845 10:59:20.615762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26847 10:59:20.659277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26848 10:59:20.659707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26850 10:59:20.693871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26851 10:59:20.694302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26853 10:59:20.730234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26855 10:59:20.730715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26856 10:59:20.765583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26858 10:59:20.766035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26859 10:59:20.811833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26860 10:59:20.812246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26862 10:59:20.845896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26864 10:59:20.846378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26865 10:59:20.891573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26866 10:59:20.891960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26868 10:59:20.936444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26869 10:59:20.936865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26871 10:59:20.981622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26872 10:59:20.982064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26874 10:59:21.028002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26876 10:59:21.028384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26877 10:59:21.073301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26878 10:59:21.073694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26880 10:59:21.117197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26881 10:59:21.117586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26883 10:59:21.164686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26884 10:59:21.165128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26886 10:59:21.212130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26887 10:59:21.212515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26889 10:59:21.257863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26890 10:59:21.258271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26892 10:59:21.307259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26893 10:59:21.307684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26895 10:59:21.353084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26896 10:59:21.353514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26898 10:59:21.400348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26900 10:59:21.400774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26901 10:59:21.447667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26902 10:59:21.448091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26904 10:59:21.495286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26906 10:59:21.495761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26907 10:59:21.541089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26909 10:59:21.541532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26910 10:59:21.588489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26911 10:59:21.588853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26913 10:59:21.633465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26914 10:59:21.633892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26916 10:59:21.680391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26917 10:59:21.680795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26919 10:59:21.725276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26921 10:59:21.725713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26922 10:59:21.760443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26924 10:59:21.760857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26925 10:59:21.801889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26926 10:59:21.802306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26928 10:59:21.846260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26929 10:59:21.846688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26931 10:59:21.891678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26932 10:59:21.892105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26934 10:59:21.938545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26936 10:59:21.938993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26937 10:59:21.985424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26938 10:59:21.985873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26940 10:59:22.033223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26942 10:59:22.033679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26943 10:59:22.080428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26944 10:59:22.080853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26946 10:59:22.126322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26948 10:59:22.126799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26949 10:59:22.172558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26950 10:59:22.172972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26952 10:59:22.217950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26953 10:59:22.218388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26955 10:59:22.263420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26956 10:59:22.263868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26958 10:59:22.308948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26959 10:59:22.309360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26961 10:59:22.354525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26963 10:59:22.355230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26964 10:59:22.399756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26965 10:59:22.400177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26967 10:59:22.444772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26968 10:59:22.445235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26970 10:59:22.491845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
26971 10:59:22.492267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
26973 10:59:22.534029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
26975 10:59:22.534533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
26976 10:59:22.580810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
26977 10:59:22.581202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
26979 10:59:22.629431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
26980 10:59:22.629829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
26982 10:59:22.675696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
26983 10:59:22.676103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
26985 10:59:22.720785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
26986 10:59:22.721188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
26988 10:59:22.766888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
26990 10:59:22.767313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
26991 10:59:22.813006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
26992 10:59:22.813422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
26994 10:59:22.858015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
26995 10:59:22.858460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
26997 10:59:22.903479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
26998 10:59:22.903904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
27000 10:59:22.948575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27001 10:59:22.948952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27003 10:59:22.988919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27004 10:59:22.989343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27006 10:59:23.035418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27007 10:59:23.035824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27009 10:59:23.080960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27010 10:59:23.081380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27012 10:59:23.127744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27014 10:59:23.128198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27015 10:59:23.172811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27017 10:59:23.173267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27018 10:59:23.218308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27020 10:59:23.218901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27021 10:59:23.259679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27022 10:59:23.260098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27024 10:59:23.305314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27025 10:59:23.305686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27027 10:59:23.351146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27028 10:59:23.351539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27030 10:59:23.397229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27031 10:59:23.397638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27033 10:59:23.443888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27034 10:59:23.444290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27036 10:59:23.488469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27037 10:59:23.488866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27039 10:59:23.534628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27041 10:59:23.535066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27042 10:59:23.582470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27044 10:59:23.583145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27045 10:59:23.628560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27046 10:59:23.628984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27048 10:59:23.673358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27049 10:59:23.673790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27051 10:59:23.718024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27052 10:59:23.718455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27054 10:59:23.754867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27055 10:59:23.755277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27057 10:59:23.800101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27058 10:59:23.800518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27060 10:59:23.845037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27061 10:59:23.845461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27063 10:59:23.889672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27064 10:59:23.890107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27066 10:59:23.929534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27067 10:59:23.929964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27069 10:59:23.975157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27070 10:59:23.975576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27072 10:59:24.047728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27073 10:59:24.048138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27075 10:59:24.095028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27076 10:59:24.095467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27078 10:59:24.141057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27079 10:59:24.141521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27081 10:59:24.187860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27083 10:59:24.188313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27084 10:59:24.234812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27085 10:59:24.235217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27087 10:59:24.279749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27089 10:59:24.280163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27090 10:59:24.324646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27091 10:59:24.325067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27093 10:59:24.372148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27095 10:59:24.372582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27096 10:59:24.420187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27097 10:59:24.420617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27099 10:59:24.468261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27100 10:59:24.468687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27102 10:59:24.516019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27103 10:59:24.516431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27105 10:59:24.561080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27106 10:59:24.561501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27108 10:59:24.609145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27109 10:59:24.609540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27111 10:59:24.655475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27113 10:59:24.655932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27114 10:59:24.700839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27115 10:59:24.701240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27117 10:59:24.746744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27118 10:59:24.747189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27120 10:59:24.793896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27121 10:59:24.794373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27123 10:59:24.839307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27124 10:59:24.839727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27126 10:59:24.885587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27127 10:59:24.886006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27129 10:59:24.930519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27131 10:59:24.930960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27132 10:59:24.975386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27133 10:59:24.975798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27135 10:59:25.011275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27137 10:59:25.011690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27138 10:59:25.056230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27139 10:59:25.056634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27141 10:59:25.097371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27142 10:59:25.097778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27144 10:59:25.142101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27145 10:59:25.142510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27147 10:59:25.187424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27148 10:59:25.187855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27150 10:59:25.232693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27151 10:59:25.233095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27153 10:59:25.268124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27154 10:59:25.268500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27156 10:59:25.312541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27157 10:59:25.312933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27159 10:59:25.357719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27160 10:59:25.358145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27162 10:59:25.403661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27163 10:59:25.404074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27165 10:59:25.448009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27166 10:59:25.448415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27168 10:59:25.492940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27169 10:59:25.493376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27171 10:59:25.538017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27173 10:59:25.538483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27174 10:59:25.583508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27175 10:59:25.583909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27177 10:59:25.617470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27178 10:59:25.617927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27180 10:59:25.661853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27181 10:59:25.662282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27183 10:59:25.697757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27184 10:59:25.698171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27186 10:59:25.743043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27187 10:59:25.743463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27189 10:59:25.777725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27190 10:59:25.778173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27192 10:59:25.823329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27193 10:59:25.823768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27195 10:59:25.862310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27197 10:59:25.862897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27198 10:59:25.904919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27199 10:59:25.905348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27201 10:59:25.952365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27203 10:59:25.952813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27204 10:59:25.998399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27206 10:59:25.998887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27207 10:59:26.039424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27208 10:59:26.039799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27210 10:59:26.078368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27212 10:59:26.078812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27213 10:59:26.112954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27214 10:59:26.113335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27216 10:59:26.157899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27217 10:59:26.158299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27219 10:59:26.191764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27220 10:59:26.192165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27222 10:59:26.227207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27223 10:59:26.227632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27225 10:59:26.269790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27226 10:59:26.270223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27228 10:59:26.315441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27230 10:59:26.315895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27231 10:59:26.360511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27232 10:59:26.360925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27234 10:59:26.400309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27235 10:59:26.400729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27237 10:59:26.435524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27239 10:59:26.435942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27240 10:59:26.471514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27241 10:59:26.471912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27243 10:59:26.513089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27245 10:59:26.513509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27246 10:59:26.559439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27247 10:59:26.559833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27249 10:59:26.604120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27250 10:59:26.604513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27252 10:59:26.640879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27253 10:59:26.641246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27255 10:59:26.686007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27256 10:59:26.686412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27258 10:59:26.729571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27259 10:59:26.729979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27261 10:59:26.775714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27263 10:59:26.776182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27264 10:59:26.820580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27265 10:59:26.821004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27267 10:59:26.868001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27268 10:59:26.868425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27270 10:59:26.913137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27271 10:59:26.913487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27273 10:59:26.957817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27274 10:59:26.958248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27276 10:59:27.004562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27278 10:59:27.005013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27279 10:59:27.038857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27280 10:59:27.039286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27282 10:59:27.073642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27283 10:59:27.074066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27285 10:59:27.109015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27287 10:59:27.113775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27288 10:59:27.163048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27289 10:59:27.163465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27291 10:59:27.208143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27292 10:59:27.208559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27294 10:59:27.247645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27296 10:59:27.248102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27297 10:59:27.284323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27298 10:59:27.284747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27300 10:59:27.318369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27302 10:59:27.318852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27303 10:59:27.351513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27305 10:59:27.351965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27306 10:59:27.384631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27307 10:59:27.385053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27309 10:59:27.417504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27311 10:59:27.417962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27312 10:59:27.457878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27313 10:59:27.458314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27315 10:59:27.502430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27317 10:59:27.502960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27318 10:59:27.547708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27320 10:59:27.548151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27321 10:59:27.592012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27322 10:59:27.592439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27324 10:59:27.625118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27325 10:59:27.625528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27327 10:59:27.660081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27328 10:59:27.660490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27330 10:59:27.707355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27331 10:59:27.707782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27333 10:59:27.752220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27334 10:59:27.752513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27336 10:59:27.799145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27337 10:59:27.799518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27339 10:59:27.843339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27340 10:59:27.843709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27342 10:59:27.887199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27343 10:59:27.887594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27345 10:59:27.920148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27346 10:59:27.920544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27348 10:59:27.953394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27349 10:59:27.953804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27351 10:59:27.987101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27352 10:59:27.987522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27354 10:59:28.031287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27355 10:59:28.031704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27357 10:59:28.075660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27358 10:59:28.076058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27360 10:59:28.120225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27362 10:59:28.120650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27363 10:59:28.164529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27365 10:59:28.164973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27366 10:59:28.208996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27367 10:59:28.209364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27369 10:59:28.253275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27371 10:59:28.253734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27372 10:59:28.286730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27373 10:59:28.287176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27375 10:59:28.327046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27376 10:59:28.327470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27378 10:59:28.372763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27379 10:59:28.373169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27381 10:59:28.422599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27383 10:59:28.423046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27384 10:59:28.470084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27385 10:59:28.470515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27387 10:59:28.516060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27388 10:59:28.516473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27390 10:59:28.560360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27391 10:59:28.560792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27393 10:59:28.605019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27394 10:59:28.605420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27396 10:59:28.653079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27397 10:59:28.653469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27399 10:59:28.698398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27401 10:59:28.699021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27402 10:59:28.742970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27403 10:59:28.743356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27405 10:59:28.783465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27406 10:59:28.783870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27408 10:59:28.817858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27409 10:59:28.818254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27411 10:59:28.851279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27412 10:59:28.851666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27414 10:59:28.887270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27415 10:59:28.887689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27417 10:59:28.924728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27418 10:59:28.925133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27420 10:59:28.969245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27422 10:59:28.969969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27423 10:59:29.013600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27424 10:59:29.013999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27426 10:59:29.059891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27428 10:59:29.060360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27429 10:59:29.116992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27430 10:59:29.117426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27432 10:59:29.162368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27434 10:59:29.162856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27435 10:59:29.197007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27436 10:59:29.197400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27438 10:59:29.242338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27440 10:59:29.242751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27441 10:59:29.287201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27442 10:59:29.287580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27444 10:59:29.331204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27445 10:59:29.333695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27447 10:59:29.368490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27448 10:59:29.368886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27450 10:59:29.416534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27452 10:59:29.416994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27453 10:59:29.466528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27455 10:59:29.467038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27456 10:59:29.512523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27457 10:59:29.512927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27459 10:59:29.560596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27460 10:59:29.561039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27462 10:59:29.613256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27463 10:59:29.613631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27465 10:59:29.664143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27467 10:59:29.664670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27468 10:59:29.713499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27470 10:59:29.713962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27471 10:59:29.762589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27473 10:59:29.763060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27474 10:59:29.812851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27475 10:59:29.813285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27477 10:59:29.847777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27479 10:59:29.848247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27480 10:59:29.880996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27482 10:59:29.881447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27483 10:59:29.925307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27485 10:59:29.925751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27486 10:59:29.969425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27487 10:59:29.969849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27489 10:59:30.003236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27490 10:59:30.003657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27492 10:59:30.047931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27494 10:59:30.048303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27495 10:59:30.081138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27496 10:59:30.081492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27498 10:59:30.125557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27499 10:59:30.125932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27501 10:59:30.169331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27502 10:59:30.169686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27504 10:59:30.213686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27505 10:59:30.214065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27507 10:59:30.247166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27508 10:59:30.247584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27510 10:59:30.291840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27511 10:59:30.292189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27513 10:59:30.324889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27514 10:59:30.325304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27516 10:59:30.368919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27517 10:59:30.369397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27519 10:59:30.411395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27520 10:59:30.411813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27522 10:59:30.451433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27523 10:59:30.451868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27525 10:59:30.497809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27526 10:59:30.498192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27528 10:59:30.542448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27529 10:59:30.542881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27531 10:59:30.587837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27532 10:59:30.588252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27534 10:59:30.632763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27535 10:59:30.633111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27537 10:59:30.677209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27539 10:59:30.677667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27540 10:59:30.709633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27541 10:59:30.710050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27543 10:59:30.743275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27545 10:59:30.743715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27546 10:59:30.776358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27547 10:59:30.776767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27549 10:59:30.809479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27551 10:59:30.809957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27552 10:59:30.842460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27554 10:59:30.842986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27555 10:59:30.885785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27557 10:59:30.886265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27558 10:59:30.922079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27559 10:59:30.922495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27561 10:59:30.965821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27562 10:59:30.966231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27564 10:59:30.999557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27565 10:59:30.999967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27567 10:59:31.032719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27568 10:59:31.033133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27570 10:59:31.065687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27571 10:59:31.066094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27573 10:59:31.098242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27575 10:59:31.098714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27576 10:59:31.131591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27578 10:59:31.132051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27579 10:59:31.165021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27581 10:59:31.165483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27582 10:59:31.199036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27583 10:59:31.199478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27585 10:59:31.232873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27586 10:59:31.233285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27588 10:59:31.274909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27589 10:59:31.275323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27591 10:59:31.307845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27592 10:59:31.308243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27594 10:59:31.351716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27595 10:59:31.352127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27597 10:59:31.395304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27598 10:59:31.395700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27600 10:59:31.439183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27602 10:59:31.439656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27603 10:59:31.483377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27604 10:59:31.483780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27606 10:59:31.528021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27607 10:59:31.528406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27609 10:59:31.572563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27610 10:59:31.572965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27612 10:59:31.617616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27613 10:59:31.618044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27615 10:59:31.662395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27617 10:59:31.662922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27618 10:59:31.706528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27620 10:59:31.706993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27621 10:59:31.740690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27622 10:59:31.741127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27624 10:59:31.773703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27626 10:59:31.774115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27627 10:59:31.807003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27628 10:59:31.807408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27630 10:59:31.840110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27631 10:59:31.840521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27633 10:59:31.873251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27634 10:59:31.873629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27636 10:59:31.906085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27637 10:59:31.906498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27639 10:59:31.939701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27640 10:59:31.940114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27642 10:59:31.974598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27644 10:59:31.975047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27645 10:59:32.009325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27646 10:59:32.009748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27648 10:59:32.042779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27649 10:59:32.043192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27651 10:59:32.076090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27652 10:59:32.076507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27654 10:59:32.109407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27656 10:59:32.109887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27657 10:59:32.142595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27659 10:59:32.143123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27660 10:59:32.176101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27661 10:59:32.176531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27663 10:59:32.209592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27664 10:59:32.210020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27666 10:59:32.253918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27668 10:59:32.254361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27669 10:59:32.298876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27670 10:59:32.299283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27672 10:59:32.342879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27674 10:59:32.343314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27675 10:59:32.375893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27676 10:59:32.376311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27678 10:59:32.420223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27679 10:59:32.420599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27681 10:59:32.464582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27682 10:59:32.464981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27684 10:59:32.508253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27685 10:59:32.508721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27687 10:59:32.555227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27688 10:59:32.555661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27690 10:59:32.603056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27692 10:59:32.603469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27693 10:59:32.649898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27694 10:59:32.650336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27696 10:59:32.697271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27698 10:59:32.697953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27699 10:59:32.739032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27700 10:59:32.739408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27702 10:59:32.784262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27703 10:59:32.784675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27705 10:59:32.828081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27706 10:59:32.828495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27708 10:59:32.871728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27709 10:59:32.872111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27711 10:59:32.915409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27713 10:59:32.915839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27714 10:59:32.959618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27715 10:59:32.960031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27717 10:59:32.993167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27718 10:59:32.993576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27720 10:59:33.026021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27722 10:59:33.026451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27723 10:59:33.069465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27724 10:59:33.069904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27726 10:59:33.115669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27727 10:59:33.116101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27729 10:59:33.158993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27730 10:59:33.159404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27732 10:59:33.202439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27733 10:59:33.202853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27735 10:59:33.246930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27736 10:59:33.247340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27738 10:59:33.291247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27739 10:59:33.291639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27741 10:59:33.334359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27743 10:59:33.334893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27744 10:59:33.378198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27745 10:59:33.378695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27747 10:59:33.420937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27748 10:59:33.421349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27750 10:59:33.453625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27752 10:59:33.454072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27753 10:59:33.487416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27754 10:59:33.487832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27756 10:59:33.520908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27757 10:59:33.521285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27759 10:59:33.553835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27760 10:59:33.554264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27762 10:59:33.596573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27763 10:59:33.596979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27765 10:59:33.642956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27766 10:59:33.643369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27768 10:59:33.675524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27770 10:59:33.675975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27771 10:59:33.719202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27772 10:59:33.719632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27774 10:59:33.763191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27776 10:59:33.763620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27777 10:59:33.795889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27779 10:59:33.796328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27780 10:59:33.840218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27781 10:59:33.840652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27783 10:59:33.884102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27784 10:59:33.884523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27786 10:59:33.927776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27788 10:59:33.928210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27789 10:59:33.960036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27791 10:59:33.960467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27792 10:59:33.992535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27794 10:59:33.992970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27795 10:59:34.025112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27796 10:59:34.025523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27798 10:59:34.057765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27799 10:59:34.058184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27801 10:59:34.091094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27803 10:59:34.091556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27804 10:59:34.124076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27806 10:59:34.124544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27807 10:59:34.156750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27808 10:59:34.157154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27810 10:59:34.199948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27811 10:59:34.200341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27813 10:59:34.255397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27814 10:59:34.255826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27816 10:59:34.288874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27818 10:59:34.289339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27819 10:59:34.325850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27821 10:59:34.326320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27822 10:59:34.372967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27823 10:59:34.373696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27825 10:59:34.422326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27826 10:59:34.422780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27828 10:59:34.464961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27829 10:59:34.465397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27831 10:59:34.508906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27832 10:59:34.509824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27834 10:59:34.556472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27836 10:59:34.556902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27837 10:59:34.605358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27839 10:59:34.605865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27840 10:59:34.651184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27842 10:59:34.651693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27843 10:59:34.686158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27844 10:59:34.686603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27846 10:59:34.720061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27847 10:59:34.720528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27849 10:59:34.765484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27850 10:59:34.765930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27852 10:59:34.811805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27853 10:59:34.812264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27855 10:59:34.851610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27856 10:59:34.852070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27858 10:59:34.896911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27860 10:59:34.897373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27861 10:59:34.942129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27862 10:59:34.942549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27864 10:59:34.987782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27866 10:59:34.988286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27867 10:59:35.032459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27868 10:59:35.032915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27870 10:59:35.076625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27871 10:59:35.077065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27873 10:59:35.121512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27874 10:59:35.121983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27876 10:59:35.168020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27877 10:59:35.168463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27879 10:59:35.213151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27880 10:59:35.213598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27882 10:59:35.246446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27884 10:59:35.246902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27885 10:59:35.291943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27887 10:59:35.292388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27888 10:59:35.326111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27889 10:59:35.326546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27891 10:59:35.366277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27893 10:59:35.366630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27894 10:59:35.412581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27896 10:59:35.413101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27897 10:59:35.457149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27898 10:59:35.457585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27900 10:59:35.491056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27901 10:59:35.491369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27903 10:59:35.541110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27904 10:59:35.541573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27906 10:59:35.580021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27907 10:59:35.580299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27909 10:59:35.615477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27911 10:59:35.615782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27912 10:59:35.667518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27913 10:59:35.667808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27915 10:59:35.715950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27916 10:59:35.716240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27918 10:59:35.760785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27919 10:59:35.761201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27921 10:59:35.801803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27922 10:59:35.802233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27924 10:59:35.841448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27926 10:59:35.841913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27927 10:59:35.887735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27928 10:59:35.888178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27930 10:59:35.932957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27931 10:59:35.933403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27933 10:59:35.981485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27934 10:59:35.981947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27936 10:59:36.034192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27937 10:59:36.034637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27939 10:59:36.084472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27940 10:59:36.084897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27942 10:59:36.129956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27944 10:59:36.130447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27945 10:59:36.163788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27946 10:59:36.164204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27948 10:59:36.208834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27950 10:59:36.209295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27951 10:59:36.262117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27953 10:59:36.262606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27954 10:59:36.300121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27955 10:59:36.300567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27957 10:59:36.337999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27959 10:59:36.338453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27960 10:59:36.387853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27961 10:59:36.388279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27963 10:59:36.432812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27964 10:59:36.433205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27966 10:59:36.473507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27967 10:59:36.473970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27969 10:59:36.508027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
27970 10:59:36.508459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
27972 10:59:36.548204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
27973 10:59:36.548668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
27975 10:59:36.597267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
27977 10:59:36.597800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
27978 10:59:36.640507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
27979 10:59:36.640795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
27981 10:59:36.687479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
27983 10:59:36.687936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
27984 10:59:36.733745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
27985 10:59:36.734212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
27987 10:59:36.781078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
27988 10:59:36.781553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
27990 10:59:36.819910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
27991 10:59:36.820339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
27993 10:59:36.866633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
27995 10:59:36.867235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
27996 10:59:36.919836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
27998 10:59:36.920285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
27999 10:59:36.960565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
28000 10:59:36.961016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28002 10:59:37.004991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28003 10:59:37.005434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28005 10:59:37.042149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28006 10:59:37.042594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28008 10:59:37.076304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28010 10:59:37.076755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28011 10:59:37.109937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28012 10:59:37.110357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28014 10:59:37.143177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28016 10:59:37.143654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28017 10:59:37.176084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28018 10:59:37.176528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28020 10:59:37.210883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28021 10:59:37.211309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28023 10:59:37.259025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28024 10:59:37.259414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28026 10:59:37.302358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28028 10:59:37.302801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28029 10:59:37.346974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28031 10:59:37.347417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28032 10:59:37.390070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28033 10:59:37.390487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28035 10:59:37.435391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28036 10:59:37.435815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28038 10:59:37.479389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28039 10:59:37.479808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28041 10:59:37.523385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28043 10:59:37.523820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28044 10:59:37.557167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28046 10:59:37.557609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28047 10:59:37.601265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28049 10:59:37.601706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28050 10:59:37.644815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28051 10:59:37.645244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28053 10:59:37.688769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28054 10:59:37.689199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28056 10:59:37.732366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28057 10:59:37.732793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28059 10:59:37.776327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28060 10:59:37.776745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28062 10:59:37.819967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28064 10:59:37.820403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28065 10:59:37.863246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28066 10:59:37.863662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28068 10:59:37.908113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28069 10:59:37.908542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28071 10:59:37.940674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28072 10:59:37.941112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28074 10:59:37.985489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28075 10:59:37.985912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28077 10:59:38.035792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28078 10:59:38.036200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28080 10:59:38.083640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28081 10:59:38.084055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28083 10:59:38.131338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28084 10:59:38.131728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28086 10:59:38.180157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28087 10:59:38.180551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28089 10:59:38.228517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28090 10:59:38.228924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28092 10:59:38.276162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28094 10:59:38.276622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28095 10:59:38.323735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28097 10:59:38.324182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28098 10:59:38.371592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28100 10:59:38.372044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28101 10:59:38.420237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28103 10:59:38.420687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28104 10:59:38.472873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28105 10:59:38.473309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28107 10:59:38.520858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28108 10:59:38.521261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28110 10:59:38.569656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28112 10:59:38.570167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28113 10:59:38.617173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28114 10:59:38.617613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28116 10:59:38.664795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28117 10:59:38.665230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28119 10:59:38.713793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28120 10:59:38.714218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28122 10:59:38.764191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28123 10:59:38.764624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28125 10:59:38.811990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28126 10:59:38.812374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28128 10:59:38.859789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28129 10:59:38.860212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28131 10:59:38.907706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28132 10:59:38.908109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28134 10:59:38.957136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28135 10:59:38.957556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28137 10:59:39.004657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28138 10:59:39.005078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28140 10:59:39.053251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28141 10:59:39.053684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28143 10:59:39.101449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28144 10:59:39.101931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28146 10:59:39.148608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28147 10:59:39.149003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28149 10:59:39.196155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28150 10:59:39.196454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28152 10:59:39.243183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28154 10:59:39.243527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28155 10:59:39.289344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28156 10:59:39.289613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28158 10:59:39.336718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28159 10:59:39.336999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28161 10:59:39.405527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28162 10:59:39.405980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28164 10:59:39.456313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28165 10:59:39.456692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28167 10:59:39.505880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28168 10:59:39.506142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28170 10:59:39.545624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28172 10:59:39.545943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28173 10:59:39.580015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28174 10:59:39.580387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28176 10:59:39.622014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28178 10:59:39.622317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28179 10:59:39.667121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28180 10:59:39.667411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28182 10:59:39.712670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28183 10:59:39.713078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28185 10:59:39.757149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28186 10:59:39.757565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28188 10:59:39.801476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28189 10:59:39.801895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28191 10:59:39.845175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28193 10:59:39.845608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28194 10:59:39.889505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28195 10:59:39.889800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28197 10:59:39.928478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28198 10:59:39.928884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28200 10:59:39.970418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28202 10:59:39.970741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28203 10:59:40.014435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28205 10:59:40.014761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28206 10:59:40.055847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28207 10:59:40.056255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28209 10:59:40.101856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28210 10:59:40.102164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28212 10:59:40.148735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28213 10:59:40.149020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28215 10:59:40.195763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28216 10:59:40.196203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28218 10:59:40.244970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28220 10:59:40.245398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28221 10:59:40.292397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28222 10:59:40.292691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28224 10:59:40.341867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28225 10:59:40.342154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28227 10:59:40.389148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28229 10:59:40.389520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28230 10:59:40.436134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28231 10:59:40.436599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28233 10:59:40.482826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28234 10:59:40.483099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28236 10:59:40.529903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28237 10:59:40.530188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28239 10:59:40.577119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28240 10:59:40.577418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28242 10:59:40.623735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28243 10:59:40.624039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28245 10:59:40.670335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28247 10:59:40.670828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28248 10:59:40.716732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28250 10:59:40.717052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28251 10:59:40.763318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28253 10:59:40.763656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28254 10:59:40.809505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28255 10:59:40.809823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28257 10:59:40.856327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28259 10:59:40.856597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28260 10:59:40.903906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28261 10:59:40.904206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28263 10:59:40.950772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28264 10:59:40.951032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28266 10:59:40.997273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28268 10:59:40.997567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28269 10:59:41.044000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28270 10:59:41.044423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28272 10:59:41.090188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28273 10:59:41.090488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28275 10:59:41.137324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28276 10:59:41.137743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28278 10:59:41.185005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28279 10:59:41.185347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28281 10:59:41.229340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28282 10:59:41.229679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28284 10:59:41.273596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28285 10:59:41.273895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28287 10:59:41.317642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28288 10:59:41.317918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28290 10:59:41.363311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28291 10:59:41.363639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28293 10:59:41.407031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28294 10:59:41.407469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28296 10:59:41.449924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28297 10:59:41.450198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28299 10:59:41.494182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28301 10:59:41.494561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28302 10:59:41.538015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28303 10:59:41.538310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28305 10:59:41.581841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28307 10:59:41.582145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28308 10:59:41.626049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28309 10:59:41.626341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28311 10:59:41.670001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28312 10:59:41.670295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28314 10:59:41.713239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28315 10:59:41.713537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28317 10:59:41.757057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28318 10:59:41.757337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28320 10:59:41.800577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28321 10:59:41.800986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28323 10:59:41.844338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28324 10:59:41.844678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28326 10:59:41.888311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28327 10:59:41.888607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28329 10:59:41.932069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28330 10:59:41.932359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28332 10:59:41.965133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28333 10:59:41.965419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28335 10:59:42.008427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28336 10:59:42.008714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28338 10:59:42.052614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28339 10:59:42.052910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28341 10:59:42.096108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28343 10:59:42.096402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28344 10:59:42.129022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28345 10:59:42.129310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28347 10:59:42.172855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28348 10:59:42.173288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28350 10:59:42.216591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28351 10:59:42.217004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28353 10:59:42.260387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28354 10:59:42.260804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28356 10:59:42.305204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28357 10:59:42.305618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28359 10:59:42.348639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28360 10:59:42.349011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28362 10:59:42.381914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28364 10:59:42.382214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28365 10:59:42.414618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28367 10:59:42.415062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28368 10:59:42.455407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28370 10:59:42.455846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28371 10:59:42.499805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28372 10:59:42.500220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28374 10:59:42.546119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28376 10:59:42.546508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28377 10:59:42.593193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28379 10:59:42.593667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28380 10:59:42.640431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28381 10:59:42.640856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28383 10:59:42.685113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28384 10:59:42.685527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28386 10:59:42.729372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28387 10:59:42.729789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28389 10:59:42.775378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28391 10:59:42.775825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28392 10:59:42.819851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28393 10:59:42.820310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28395 10:59:42.863334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28397 10:59:42.863634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28398 10:59:42.906274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28400 10:59:42.906589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28401 10:59:42.950291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28403 10:59:42.950720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28404 10:59:42.993675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28406 10:59:42.994120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28407 10:59:43.037895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28409 10:59:43.038275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28410 10:59:43.081159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28412 10:59:43.081467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28413 10:59:43.124311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28414 10:59:43.124607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28416 10:59:43.167492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28418 10:59:43.167786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28419 10:59:43.211121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28420 10:59:43.211416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28422 10:59:43.254328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28424 10:59:43.254636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28425 10:59:43.298027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28426 10:59:43.298324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28428 10:59:43.343387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28429 10:59:43.343672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28431 10:59:43.387259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28432 10:59:43.387561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28434 10:59:43.431573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28436 10:59:43.431995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28437 10:59:43.475409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28438 10:59:43.475704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28440 10:59:43.514897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28442 10:59:43.515171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28443 10:59:43.559454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28445 10:59:43.559906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28446 10:59:43.603205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28447 10:59:43.603501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28449 10:59:43.647417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28450 10:59:43.647775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28452 10:59:43.692087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28453 10:59:43.692345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28455 10:59:43.735610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28456 10:59:43.735871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28458 10:59:43.779454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28459 10:59:43.779753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28461 10:59:43.822951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28462 10:59:43.823238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28464 10:59:43.866736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28465 10:59:43.867015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28467 10:59:43.910164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28468 10:59:43.910489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28470 10:59:43.955465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28471 10:59:43.955834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28473 10:59:43.999064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28474 10:59:43.999416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28476 10:59:44.042863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28477 10:59:44.043243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28479 10:59:44.086413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28481 10:59:44.086865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28482 10:59:44.130151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28483 10:59:44.130448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28485 10:59:44.174749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28486 10:59:44.175038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28488 10:59:44.218354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28490 10:59:44.218689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28491 10:59:44.261856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28492 10:59:44.262291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28494 10:59:44.305449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28495 10:59:44.305768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28497 10:59:44.349168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28498 10:59:44.349514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28500 10:59:44.391281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28501 10:59:44.391539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28503 10:59:44.434991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28504 10:59:44.437693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28506 10:59:44.498024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28508 10:59:44.498527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28509 10:59:44.556456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28510 10:59:44.556879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28512 10:59:44.609055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28513 10:59:44.609436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28515 10:59:44.659948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28517 10:59:44.660398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28518 10:59:44.696239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28520 10:59:44.696717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28521 10:59:44.729532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28522 10:59:44.730022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28524 10:59:44.763570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28525 10:59:44.764020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28527 10:59:44.796834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28528 10:59:44.797288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28530 10:59:44.829860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28532 10:59:44.830348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28533 10:59:44.875080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28535 10:59:44.875558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28536 10:59:44.919419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28537 10:59:44.919868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28539 10:59:44.965351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28540 10:59:44.965798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28542 10:59:45.010307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28543 10:59:45.010767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28545 10:59:45.056796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28547 10:59:45.057252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28548 10:59:45.105453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28550 10:59:45.105936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28551 10:59:45.152122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28553 10:59:45.152571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28554 10:59:45.200268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28556 10:59:45.200721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28557 10:59:45.239401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28558 10:59:45.239863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28560 10:59:45.274194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28561 10:59:45.274633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28563 10:59:45.311217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28564 10:59:45.311676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28566 10:59:45.352569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28568 10:59:45.353064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28569 10:59:45.399811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28570 10:59:45.400271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28572 10:59:45.446059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28573 10:59:45.446817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28575 10:59:45.493917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28576 10:59:45.494377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28578 10:59:45.541626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28579 10:59:45.542089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28581 10:59:45.591444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28583 10:59:45.591926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28584 10:59:45.638399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28586 10:59:45.638889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28587 10:59:45.683561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28589 10:59:45.683868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28590 10:59:45.729127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28591 10:59:45.729423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28593 10:59:45.773448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28594 10:59:45.773752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28596 10:59:45.816799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28597 10:59:45.817083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28599 10:59:45.860930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28600 10:59:45.861220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28602 10:59:45.904289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28603 10:59:45.904596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28605 10:59:45.948913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28606 10:59:45.949206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28608 10:59:45.996315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28609 10:59:45.996607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28611 10:59:46.042339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28613 10:59:46.042676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28614 10:59:46.088371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28615 10:59:46.088684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28617 10:59:46.133179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28619 10:59:46.133591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28620 10:59:46.180497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28622 10:59:46.180804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28623 10:59:46.225032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28625 10:59:46.225483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28626 10:59:46.268917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28627 10:59:46.269201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28629 10:59:46.312980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28630 10:59:46.313261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28632 10:59:46.359680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28633 10:59:46.359962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28635 10:59:46.407054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28636 10:59:46.407345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28638 10:59:46.454783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28639 10:59:46.455080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28641 10:59:46.500234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28642 10:59:46.500512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28644 10:59:46.545483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28646 10:59:46.545774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28647 10:59:46.590152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28649 10:59:46.590505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28650 10:59:46.634795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28651 10:59:46.635066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28653 10:59:46.678408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28655 10:59:46.678837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28656 10:59:46.723245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28657 10:59:46.723523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28659 10:59:46.767842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28661 10:59:46.768269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28662 10:59:46.813505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28663 10:59:46.813921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28665 10:59:46.857323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28666 10:59:46.857608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28668 10:59:46.903142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28669 10:59:46.903439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28671 10:59:46.949448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28673 10:59:46.949788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28674 10:59:46.995946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28676 10:59:46.996242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28677 10:59:47.042291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28679 10:59:47.042618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28680 10:59:47.088255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28681 10:59:47.088545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28683 10:59:47.135098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28684 10:59:47.135387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28686 10:59:47.179301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28687 10:59:47.179595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28689 10:59:47.223725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28691 10:59:47.224170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28692 10:59:47.268562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28694 10:59:47.268943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28695 10:59:47.312972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28696 10:59:47.313263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28698 10:59:47.359090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28699 10:59:47.359389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28701 10:59:47.403360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28702 10:59:47.403652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28704 10:59:47.447524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28705 10:59:47.447800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28707 10:59:47.491406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28708 10:59:47.491719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28710 10:59:47.536599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28711 10:59:47.536857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28713 10:59:47.583321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28714 10:59:47.583611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28716 10:59:47.630956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28717 10:59:47.631245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28719 10:59:47.677850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28720 10:59:47.678152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28722 10:59:47.724537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28723 10:59:47.724828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28725 10:59:47.772499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28726 10:59:47.772796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28728 10:59:47.815979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28729 10:59:47.816271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28731 10:59:47.864094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28733 10:59:47.864389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28734 10:59:47.913424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28735 10:59:47.913686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28737 10:59:47.963396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28739 10:59:47.963694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28740 10:59:48.013687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28741 10:59:48.013975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28743 10:59:48.062245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28745 10:59:48.062580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28746 10:59:48.111759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28747 10:59:48.112045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28749 10:59:48.160343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28750 10:59:48.160635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28752 10:59:48.212319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28753 10:59:48.212620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28755 10:59:48.260469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28756 10:59:48.260882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28758 10:59:48.316167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28760 10:59:48.316611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28761 10:59:48.372099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28763 10:59:48.372522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28764 10:59:48.428231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28765 10:59:48.428670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28767 10:59:48.484558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28768 10:59:48.484997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28770 10:59:48.540039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28771 10:59:48.540481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28773 10:59:48.596173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28775 10:59:48.596593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28776 10:59:48.649810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28777 10:59:48.650231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28779 10:59:48.704416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28780 10:59:48.704858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28782 10:59:48.759801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28783 10:59:48.760241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28785 10:59:48.814320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28786 10:59:48.814767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28788 10:59:48.869921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28789 10:59:48.870360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28791 10:59:48.925718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28792 10:59:48.926171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28794 10:59:48.981497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28795 10:59:48.981935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28797 10:59:49.036827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28798 10:59:49.037279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28800 10:59:49.092873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28801 10:59:49.093288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28803 10:59:49.147464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28804 10:59:49.147913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28806 10:59:49.202512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28808 10:59:49.203006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28809 10:59:49.258035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28810 10:59:49.258498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28812 10:59:49.314216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28813 10:59:49.314641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28815 10:59:49.369661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28816 10:59:49.370106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28818 10:59:49.424321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28819 10:59:49.424768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28821 10:59:49.481110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28822 10:59:49.481948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28824 10:59:49.539820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28826 10:59:49.540279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28827 10:59:49.612504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28828 10:59:49.612946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28830 10:59:49.676331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28831 10:59:49.676757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28833 10:59:49.732558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28834 10:59:49.732983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28836 10:59:49.789136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28838 10:59:49.789580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28839 10:59:49.844435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28840 10:59:49.844875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28842 10:59:49.892626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28843 10:59:49.893059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28845 10:59:49.930306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28847 10:59:49.930862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28848 10:59:49.971806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28849 10:59:49.972260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28851 10:59:50.016568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28852 10:59:50.017005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28854 10:59:50.061643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28855 10:59:50.062060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28857 10:59:50.106520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28859 10:59:50.106990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28860 10:59:50.152244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28862 10:59:50.152707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28863 10:59:50.196309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28864 10:59:50.196814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28866 10:59:50.232496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28868 10:59:50.233130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28869 10:59:50.269173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28870 10:59:50.269620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28872 10:59:50.306944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28873 10:59:50.307367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28875 10:59:50.355811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28876 10:59:50.356232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28878 10:59:50.408776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28880 10:59:50.409230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28881 10:59:50.460005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28882 10:59:50.461960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28884 10:59:50.508370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28885 10:59:50.508774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28887 10:59:50.563992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28889 10:59:50.564449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28890 10:59:50.616135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28891 10:59:50.616576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28893 10:59:50.666346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28894 10:59:50.666792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28896 10:59:50.702126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28897 10:59:50.702557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28899 10:59:50.754480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28901 10:59:50.755082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28902 10:59:50.797217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28904 10:59:50.797679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28905 10:59:50.849238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28906 10:59:50.849666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28908 10:59:50.903712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28910 10:59:50.904170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28911 10:59:50.955598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28912 10:59:50.956001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28914 10:59:51.005667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28916 10:59:51.006076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28917 10:59:51.053617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28919 10:59:51.054108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28920 10:59:51.103158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28921 10:59:51.103618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28923 10:59:51.151978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28925 10:59:51.152441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28926 10:59:51.200932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28928 10:59:51.201413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28929 10:59:51.240663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28930 10:59:51.241105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28932 10:59:51.284953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28933 10:59:51.285403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28935 10:59:51.333044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28936 10:59:51.333478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28938 10:59:51.382097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28939 10:59:51.382544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28941 10:59:51.432257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28942 10:59:51.432704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28944 10:59:51.482221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28945 10:59:51.482669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28947 10:59:51.530345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28949 10:59:51.530912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28950 10:59:51.577174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28951 10:59:51.577586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28953 10:59:51.609332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28955 10:59:51.609807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28956 10:59:51.656072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28957 10:59:51.656652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28959 10:59:51.700504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28961 10:59:51.700995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28962 10:59:51.749232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28963 10:59:51.749691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28965 10:59:51.798387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28967 10:59:51.798923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28968 10:59:51.844195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28970 10:59:51.844686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
28971 10:59:51.892272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
28972 10:59:51.892719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
28974 10:59:51.934160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
28975 10:59:51.934586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
28977 10:59:51.980971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
28978 10:59:51.981399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
28980 10:59:52.013612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
28981 10:59:52.014065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
28983 10:59:52.065776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
28985 10:59:52.066279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
28986 10:59:52.120381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
28987 10:59:52.120842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
28989 10:59:52.174530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
28991 10:59:52.175159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
28992 10:59:52.216074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
28994 10:59:52.216519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
28995 10:59:52.250981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
28996 10:59:52.251403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
28998 10:59:52.293418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
28999 10:59:52.293860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29001 10:59:52.336681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29002 10:59:52.337017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29004 10:59:52.383426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29005 10:59:52.383688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29007 10:59:52.429099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29009 10:59:52.429481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29010 10:59:52.472818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29011 10:59:52.473111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29013 10:59:52.516527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29014 10:59:52.516950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29016 10:59:52.560299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29017 10:59:52.560705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29019 10:59:52.604466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29020 10:59:52.604892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29022 10:59:52.648132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29023 10:59:52.648514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29025 10:59:52.691326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29026 10:59:52.691735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29028 10:59:52.735891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29029 10:59:52.736307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29031 10:59:52.779468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29032 10:59:52.779799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29034 10:59:52.811803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29035 10:59:52.812221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29037 10:59:52.844429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29038 10:59:52.844846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29040 10:59:52.876978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29041 10:59:52.877353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29043 10:59:52.909771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29045 10:59:52.910219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29046 10:59:52.944251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29048 10:59:52.944693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29049 10:59:52.977562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29051 10:59:52.978008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29052 10:59:53.011009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29054 10:59:53.011469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29055 10:59:53.043767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29056 10:59:53.044187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29058 10:59:53.077330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29059 10:59:53.077768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29061 10:59:53.112276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29063 10:59:53.112744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29064 10:59:53.145115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29065 10:59:53.145510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29067 10:59:53.178591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29069 10:59:53.179042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29070 10:59:53.222502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29072 10:59:53.222976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29073 10:59:53.269559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29074 10:59:53.269917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29076 10:59:53.311684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29077 10:59:53.312105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29079 10:59:53.353207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29080 10:59:53.353639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29082 10:59:53.397351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29084 10:59:53.397822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29085 10:59:53.430907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29086 10:59:53.431326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29088 10:59:53.466572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29089 10:59:53.467018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29091 10:59:53.509965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29092 10:59:53.510377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29094 10:59:53.543438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29095 10:59:53.543853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29097 10:59:53.576318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29098 10:59:53.576728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29100 10:59:53.610167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29101 10:59:53.610607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29103 10:59:53.647252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29105 10:59:53.647704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29106 10:59:53.680604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29107 10:59:53.680997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29109 10:59:53.713533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29110 10:59:53.713962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29112 10:59:53.746869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29113 10:59:53.747307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29115 10:59:53.779561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29116 10:59:53.779967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29118 10:59:53.815252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29119 10:59:53.815654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29121 10:59:53.851770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29122 10:59:53.852205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29124 10:59:53.885085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29125 10:59:53.885507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29127 10:59:53.917921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29129 10:59:53.918357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29130 10:59:53.951542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29131 10:59:53.951968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29133 10:59:53.984439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29134 10:59:53.984834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29136 10:59:54.017354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29137 10:59:54.017761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29139 10:59:54.065461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29140 10:59:54.065906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29142 10:59:54.099434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29144 10:59:54.099896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29145 10:59:54.135617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29146 10:59:54.136049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29148 10:59:54.168898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29149 10:59:54.169271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29151 10:59:54.217191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29153 10:59:54.217612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29154 10:59:54.261451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29155 10:59:54.261897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29157 10:59:54.300360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29158 10:59:54.300763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29160 10:59:54.336475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29161 10:59:54.336896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29163 10:59:54.369492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29164 10:59:54.369932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29166 10:59:54.417872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29167 10:59:54.418284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29169 10:59:54.454351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29171 10:59:54.454833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29172 10:59:54.489663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29174 10:59:54.490100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29175 10:59:54.534873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29176 10:59:54.535288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29178 10:59:54.583555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29180 10:59:54.583995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29181 10:59:54.628395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29182 10:59:54.628854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29184 10:59:54.674279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29186 10:59:54.674801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29187 10:59:54.745732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29188 10:59:54.746147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29190 10:59:54.790835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29191 10:59:54.791270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29193 10:59:54.834744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29194 10:59:54.835170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29196 10:59:54.879546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29197 10:59:54.879979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29199 10:59:54.924354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29200 10:59:54.924750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29202 10:59:54.964623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29203 10:59:54.965045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29205 10:59:55.002102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29206 10:59:55.002401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29208 10:59:55.046138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29209 10:59:55.046430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29211 10:59:55.091122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29213 10:59:55.091421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29214 10:59:55.134361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29216 10:59:55.134689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29217 10:59:55.168568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29218 10:59:55.168975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29220 10:59:55.213468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29221 10:59:55.213905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29223 10:59:55.257351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29225 10:59:55.257744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29226 10:59:55.302795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29227 10:59:55.303215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29229 10:59:55.342391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29231 10:59:55.342892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29232 10:59:55.387584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29234 10:59:55.388030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29235 10:59:55.431621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29236 10:59:55.432041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29238 10:59:55.477791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29239 10:59:55.478217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29241 10:59:55.521704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29242 10:59:55.522118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29244 10:59:55.565485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29245 10:59:55.565864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29247 10:59:55.597698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29249 10:59:55.598117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29250 10:59:55.635404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29251 10:59:55.635701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29253 10:59:55.679354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29254 10:59:55.679628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29256 10:59:55.712185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29257 10:59:55.712610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29259 10:59:55.747333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29260 10:59:55.747764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29262 10:59:55.791169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29264 10:59:55.791631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29265 10:59:55.826129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29266 10:59:55.826579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29268 10:59:55.867605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29269 10:59:55.868052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29271 10:59:55.911439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29272 10:59:55.911841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29274 10:59:55.955302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29275 10:59:55.955678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29277 10:59:55.995173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29279 10:59:55.995643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29280 10:59:56.028267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29281 10:59:56.028697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29283 10:59:56.061718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29284 10:59:56.062250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29286 10:59:56.095364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29287 10:59:56.095806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29289 10:59:56.134224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29290 10:59:56.134678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29292 10:59:56.175940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29293 10:59:56.176361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29295 10:59:56.221284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29296 10:59:56.221689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29298 10:59:56.265230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29299 10:59:56.265580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29301 10:59:56.298034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29302 10:59:56.298485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29304 10:59:56.333477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29305 10:59:56.333905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29307 10:59:56.372537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29308 10:59:56.372925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29310 10:59:56.408839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29312 10:59:56.409297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29313 10:59:56.451135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29315 10:59:56.451562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29316 10:59:56.496174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29318 10:59:56.496603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29319 10:59:56.540570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29321 10:59:56.541024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29322 10:59:56.586032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29324 10:59:56.586492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29325 10:59:56.629722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29326 10:59:56.630136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29328 10:59:56.678857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29329 10:59:56.679416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29331 10:59:56.715495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29332 10:59:56.715947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29334 10:59:56.752424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29335 10:59:56.752869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29337 10:59:56.797887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29338 10:59:56.798276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29340 10:59:56.845943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29341 10:59:56.846407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29343 10:59:56.881381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29344 10:59:56.881763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29346 10:59:56.913936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29347 10:59:56.914233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29349 10:59:56.947863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29350 10:59:56.948814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29352 10:59:56.993635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29354 10:59:56.993959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29355 10:59:57.038434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29357 10:59:57.038851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29358 10:59:57.084795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29359 10:59:57.085158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29361 10:59:57.128765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29362 10:59:57.129061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29364 10:59:57.172998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29365 10:59:57.173274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29367 10:59:57.217690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29368 10:59:57.217987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29370 10:59:57.263344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29372 10:59:57.263640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29373 10:59:57.307035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29375 10:59:57.307331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29376 10:59:57.349362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29378 10:59:57.349665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29379 10:59:57.395075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29380 10:59:57.395492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29382 10:59:57.435453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29384 10:59:57.435750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29385 10:59:57.470699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29386 10:59:57.470986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29388 10:59:57.514764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29389 10:59:57.515054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29391 10:59:57.557793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29392 10:59:57.558185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29394 10:59:57.602810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29395 10:59:57.603251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29397 10:59:57.643327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29398 10:59:57.643744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29400 10:59:57.684431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29401 10:59:57.684825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29403 10:59:57.729406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29404 10:59:57.729796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29406 10:59:57.773744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29407 10:59:57.774035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29409 10:59:57.817295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29410 10:59:57.817580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29412 10:59:57.867015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29413 10:59:57.867312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29415 10:59:57.910829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29416 10:59:57.911241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29418 10:59:57.954386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29420 10:59:57.954848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29421 10:59:57.990012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29422 10:59:57.990366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29424 10:59:58.039708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29425 10:59:58.040089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29427 10:59:58.087957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29429 10:59:58.088333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29430 10:59:58.133633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29431 10:59:58.133907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29433 10:59:58.179035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29435 10:59:58.179334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29436 10:59:58.222806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29437 10:59:58.223085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29439 10:59:58.267074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29440 10:59:58.267347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29442 10:59:58.311559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29443 10:59:58.311843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29445 10:59:58.349032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29447 10:59:58.349467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29448 10:59:58.392945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29449 10:59:58.393367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29451 10:59:58.437383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29452 10:59:58.437805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29454 10:59:58.480093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29455 10:59:58.480484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29457 10:59:58.524544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29458 10:59:58.524966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29460 10:59:58.572052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29461 10:59:58.572450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29463 10:59:58.616655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29464 10:59:58.616943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29466 10:59:58.660610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29468 10:59:58.660911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29469 10:59:58.701082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29470 10:59:58.701493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29472 10:59:58.735127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29473 10:59:58.735549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29475 10:59:58.778289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29477 10:59:58.778794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29478 10:59:58.822488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29480 10:59:58.822923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29481 10:59:58.865100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29483 10:59:58.865537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29484 10:59:58.899298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29486 10:59:58.899772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29487 10:59:58.932464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29488 10:59:58.932883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29490 10:59:58.965431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29491 10:59:58.965844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29493 10:59:58.999348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29495 10:59:58.999821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29496 10:59:59.037042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29497 10:59:59.037496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29499 10:59:59.073680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29500 10:59:59.074096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29502 10:59:59.117190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29503 10:59:59.117604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29505 10:59:59.164617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29506 10:59:59.165015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29508 10:59:59.213020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29510 10:59:59.213479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29511 10:59:59.260849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29512 10:59:59.261279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29514 10:59:59.305704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29515 10:59:59.306121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29517 10:59:59.351468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29518 10:59:59.351890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29520 10:59:59.384547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29521 10:59:59.384968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29523 10:59:59.417964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29524 10:59:59.418386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29526 10:59:59.461956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29528 10:59:59.462403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29529 10:59:59.511041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29530 10:59:59.511454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29532 10:59:59.562389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29534 10:59:59.562860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29535 10:59:59.612779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29536 10:59:59.613161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29538 10:59:59.661381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29539 10:59:59.661796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29541 10:59:59.711580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29542 10:59:59.712014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29544 10:59:59.759048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29545 10:59:59.759356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29547 10:59:59.804067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29548 10:59:59.804412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29550 10:59:59.873690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29551 10:59:59.874106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29553 10:59:59.919388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29555 10:59:59.919853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29556 10:59:59.965945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29557 10:59:59.966400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29559 11:00:00.011716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29560 11:00:00.012166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29562 11:00:00.055723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29563 11:00:00.056051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29565 11:00:00.099643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29566 11:00:00.099982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29568 11:00:00.143455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29569 11:00:00.143763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29571 11:00:00.187536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29572 11:00:00.187848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29574 11:00:00.228887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29576 11:00:00.229262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29577 11:00:00.262290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29579 11:00:00.262628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29580 11:00:00.302897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29581 11:00:00.303353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29583 11:00:00.345540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29584 11:00:00.345863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29586 11:00:00.389497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29587 11:00:00.389841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29589 11:00:00.435151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29590 11:00:00.435485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29592 11:00:00.477832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29594 11:00:00.478254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29595 11:00:00.522875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29597 11:00:00.523369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29598 11:00:00.567358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29599 11:00:00.567730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29601 11:00:00.604196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29602 11:00:00.604604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29604 11:00:00.648905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29605 11:00:00.649319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29607 11:00:00.693973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29608 11:00:00.694400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29610 11:00:00.740207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29611 11:00:00.740624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29613 11:00:00.784693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29614 11:00:00.785134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29616 11:00:00.828829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29617 11:00:00.829251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29619 11:00:00.877474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29621 11:00:00.877940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29622 11:00:00.920621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29623 11:00:00.921068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29625 11:00:00.959424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29626 11:00:00.959848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29628 11:00:01.004513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29629 11:00:01.004962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29631 11:00:01.053752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29632 11:00:01.054199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29634 11:00:01.098702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29635 11:00:01.099142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29637 11:00:01.145248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29638 11:00:01.145544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29640 11:00:01.192167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29641 11:00:01.192574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29643 11:00:01.239676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29644 11:00:01.240103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29646 11:00:01.287231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29647 11:00:01.287601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29649 11:00:01.331620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29650 11:00:01.331915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29652 11:00:01.375855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29653 11:00:01.376119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29655 11:00:01.418772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29656 11:00:01.419089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29658 11:00:01.465713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29659 11:00:01.466136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29661 11:00:01.511997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29662 11:00:01.512424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29664 11:00:01.563873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29665 11:00:01.564229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29667 11:00:01.619089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29668 11:00:01.619550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29670 11:00:01.674484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29672 11:00:01.674989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29673 11:00:01.728881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29675 11:00:01.729313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29676 11:00:01.770949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29677 11:00:01.771400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29679 11:00:01.810504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29681 11:00:01.810993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29682 11:00:01.864550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29683 11:00:01.864972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29685 11:00:01.913756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29686 11:00:01.914253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29688 11:00:01.964264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29689 11:00:01.964676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29691 11:00:02.016834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29692 11:00:02.017258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29694 11:00:02.068752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29695 11:00:02.069105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29697 11:00:02.121814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29698 11:00:02.122248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29700 11:00:02.167032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29701 11:00:02.167453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29703 11:00:02.213156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29704 11:00:02.213579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29706 11:00:02.260013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29707 11:00:02.260441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29709 11:00:02.305842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29710 11:00:02.306226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29712 11:00:02.341780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29713 11:00:02.342181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29715 11:00:02.392168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29716 11:00:02.392624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29718 11:00:02.445007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29719 11:00:02.445462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29721 11:00:02.500549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29722 11:00:02.501010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29724 11:00:02.558111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29725 11:00:02.558569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29727 11:00:02.612595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29728 11:00:02.613012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29730 11:00:02.659702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29731 11:00:02.660153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29733 11:00:02.700398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29735 11:00:02.700872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29736 11:00:02.749491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29737 11:00:02.749924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29739 11:00:02.785815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29740 11:00:02.786244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29742 11:00:02.832569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29743 11:00:02.833000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29745 11:00:02.878383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29747 11:00:02.878881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29748 11:00:02.921910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29749 11:00:02.922357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29751 11:00:02.977046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29752 11:00:02.977485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29754 11:00:03.033266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29755 11:00:03.033685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29757 11:00:03.094532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29759 11:00:03.095278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29760 11:00:03.148816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29762 11:00:03.149286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29763 11:00:03.196909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29765 11:00:03.197354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29766 11:00:03.244064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29767 11:00:03.244497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29769 11:00:03.291590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29770 11:00:03.292045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29772 11:00:03.341731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29773 11:00:03.342160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29775 11:00:03.380627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29776 11:00:03.381074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29778 11:00:03.430533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29780 11:00:03.430985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29781 11:00:03.479051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29783 11:00:03.479453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29784 11:00:03.525319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29786 11:00:03.525741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29787 11:00:03.567612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29788 11:00:03.568013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29790 11:00:03.608771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29791 11:00:03.609076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29793 11:00:03.652817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29794 11:00:03.653192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29796 11:00:03.700322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29798 11:00:03.700834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29799 11:00:03.744830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29800 11:00:03.745286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29802 11:00:03.789768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29803 11:00:03.790198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29805 11:00:03.837021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29806 11:00:03.837443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29808 11:00:03.875617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29810 11:00:03.876082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29811 11:00:03.920516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29812 11:00:03.920945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29814 11:00:03.969926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29815 11:00:03.970309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29817 11:00:04.013495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29818 11:00:04.013951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29820 11:00:04.059024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29821 11:00:04.059434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29823 11:00:04.109859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29824 11:00:04.110296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29826 11:00:04.156870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29828 11:00:04.157304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29829 11:00:04.204349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29831 11:00:04.204797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29832 11:00:04.252549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29833 11:00:04.252978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29835 11:00:04.299671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29836 11:00:04.300143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29838 11:00:04.345813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29839 11:00:04.346223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29841 11:00:04.395215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29843 11:00:04.395694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29844 11:00:04.441389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29845 11:00:04.441829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29847 11:00:04.488089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29848 11:00:04.488495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29850 11:00:04.535451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29851 11:00:04.535834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29853 11:00:04.582493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29855 11:00:04.582975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29856 11:00:04.631824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29857 11:00:04.632268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29859 11:00:04.683167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29861 11:00:04.683679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29862 11:00:04.732780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29863 11:00:04.733235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29865 11:00:04.783385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29866 11:00:04.783795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29868 11:00:04.831844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29869 11:00:04.832305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29871 11:00:04.880619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29872 11:00:04.881055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29874 11:00:04.936098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29875 11:00:04.936516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29877 11:00:05.024746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29879 11:00:05.025197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29880 11:00:05.077219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29882 11:00:05.077674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29883 11:00:05.132243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29885 11:00:05.132686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29886 11:00:05.189854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29888 11:00:05.190380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29889 11:00:05.250146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29890 11:00:05.253030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29892 11:00:05.303532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29893 11:00:05.303984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29895 11:00:05.356702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29897 11:00:05.357208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29898 11:00:05.412560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29899 11:00:05.412999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29901 11:00:05.470044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29903 11:00:05.470502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29904 11:00:05.527384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29905 11:00:05.527811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29907 11:00:05.583483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29908 11:00:05.583921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29910 11:00:05.644211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29912 11:00:05.644688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29913 11:00:05.705892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29914 11:00:05.706329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29916 11:00:05.768936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29918 11:00:05.769392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29919 11:00:05.828351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29920 11:00:05.828792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29922 11:00:05.887852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29923 11:00:05.888337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29925 11:00:05.951405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29926 11:00:05.951825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29928 11:00:06.007350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29929 11:00:06.007778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29931 11:00:06.041541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29933 11:00:06.042045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29934 11:00:06.076569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29935 11:00:06.076990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29937 11:00:06.113959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29938 11:00:06.114389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29940 11:00:06.169198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29942 11:00:06.169660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29943 11:00:06.216376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29944 11:00:06.216799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29946 11:00:06.264656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29947 11:00:06.265081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29949 11:00:06.313165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29951 11:00:06.313615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29952 11:00:06.364720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29953 11:00:06.365156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29955 11:00:06.414980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29957 11:00:06.415429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29958 11:00:06.466268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29960 11:00:06.466892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29961 11:00:06.517474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29962 11:00:06.517937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29964 11:00:06.570011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29965 11:00:06.570468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29967 11:00:06.620892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29968 11:00:06.621336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29970 11:00:06.672764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
29971 11:00:06.673220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
29973 11:00:06.717557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
29974 11:00:06.718006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
29976 11:00:06.768290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
29977 11:00:06.768729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
29979 11:00:06.819650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
29980 11:00:06.820086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
29982 11:00:06.870021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
29983 11:00:06.870464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
29985 11:00:06.921315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
29986 11:00:06.921767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
29988 11:00:06.974288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
29990 11:00:06.974961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
29991 11:00:07.024701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
29993 11:00:07.025155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
29994 11:00:07.074369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
29996 11:00:07.074819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
29997 11:00:07.125326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
29999 11:00:07.125777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
30000 11:00:07.177725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30001 11:00:07.178167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30003 11:00:07.220401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30004 11:00:07.220840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30006 11:00:07.275516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30007 11:00:07.275949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30009 11:00:07.328050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30010 11:00:07.328450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30012 11:00:07.381313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30013 11:00:07.381775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30015 11:00:07.434965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30017 11:00:07.435443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30018 11:00:07.487112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30019 11:00:07.487551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30021 11:00:07.538469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30023 11:00:07.538921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30024 11:00:07.588533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30025 11:00:07.588956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30027 11:00:07.640081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30028 11:00:07.640511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30030 11:00:07.690280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30032 11:00:07.691174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30033 11:00:07.741288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30034 11:00:07.741757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30036 11:00:07.792144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30037 11:00:07.792634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30039 11:00:07.846686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30040 11:00:07.847140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30042 11:00:07.896705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30043 11:00:07.897121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30045 11:00:07.948207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30046 11:00:07.948621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30048 11:00:07.997705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30050 11:00:07.998227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30051 11:00:08.048073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30052 11:00:08.048479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30054 11:00:08.085769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30055 11:00:08.086232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30057 11:00:08.132074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30058 11:00:08.132504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30060 11:00:08.183442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30061 11:00:08.183844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30063 11:00:08.242852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30064 11:00:08.243288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30066 11:00:08.295954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30067 11:00:08.296372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30069 11:00:08.344138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30071 11:00:08.344557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30072 11:00:08.394025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30074 11:00:08.394488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30075 11:00:08.443257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30076 11:00:08.443698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30078 11:00:08.495301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30079 11:00:08.495686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30081 11:00:08.546717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30082 11:00:08.547133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30084 11:00:08.601122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30085 11:00:08.601571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30087 11:00:08.655577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30089 11:00:08.656010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30090 11:00:08.706397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30091 11:00:08.706837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30093 11:00:08.759296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30094 11:00:08.759692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30096 11:00:08.809710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30098 11:00:08.810164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30099 11:00:08.861921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30100 11:00:08.862335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30102 11:00:08.908542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30103 11:00:08.908969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30105 11:00:08.955625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30106 11:00:08.956072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30108 11:00:09.016467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30109 11:00:09.016905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30111 11:00:09.063896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30112 11:00:09.064312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30114 11:00:09.112145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30115 11:00:09.112582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30117 11:00:09.164212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30118 11:00:09.164644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30120 11:00:09.217788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30121 11:00:09.218235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30123 11:00:09.271481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30124 11:00:09.272052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30126 11:00:09.326477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30128 11:00:09.326990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30129 11:00:09.383145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30130 11:00:09.387199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30132 11:00:09.437390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30134 11:00:09.437841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30135 11:00:09.492357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30136 11:00:09.492789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30138 11:00:09.546859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30139 11:00:09.547254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30141 11:00:09.600558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30143 11:00:09.601012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30144 11:00:09.654458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30146 11:00:09.654925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30147 11:00:09.705481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30148 11:00:09.705922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30150 11:00:09.757816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30151 11:00:09.758281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30153 11:00:09.812618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30154 11:00:09.813030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30156 11:00:09.869059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30157 11:00:09.869462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30159 11:00:09.920352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30160 11:00:09.920825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30162 11:00:09.973207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30164 11:00:09.973695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30165 11:00:10.025493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30166 11:00:10.025951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30168 11:00:10.102035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30170 11:00:10.103986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30171 11:00:10.160679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30172 11:00:10.161124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30174 11:00:10.219251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30175 11:00:10.219700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30177 11:00:10.273334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30178 11:00:10.273785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30180 11:00:10.329927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30181 11:00:10.330327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30183 11:00:10.385708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30185 11:00:10.386111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30186 11:00:10.441720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30188 11:00:10.442162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30189 11:00:10.498450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30191 11:00:10.498921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30192 11:00:10.556229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30193 11:00:10.556657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30195 11:00:10.618310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30197 11:00:10.618832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30198 11:00:10.681130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30199 11:00:10.681569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30201 11:00:10.741621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30202 11:00:10.742065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30204 11:00:10.797030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30205 11:00:10.797459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30207 11:00:10.852582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30208 11:00:10.852964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30210 11:00:10.908201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30211 11:00:10.908604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30213 11:00:10.965847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30214 11:00:10.966270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30216 11:00:11.022512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30218 11:00:11.022982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30219 11:00:11.079749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30221 11:00:11.080222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30222 11:00:11.136780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30223 11:00:11.137217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30225 11:00:11.193282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30226 11:00:11.193698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30228 11:00:11.244172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30229 11:00:11.244601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30231 11:00:11.283786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30232 11:00:11.284208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30234 11:00:11.333145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30235 11:00:11.333592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30237 11:00:11.377929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30238 11:00:11.378334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30240 11:00:11.415452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30241 11:00:11.415760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30243 11:00:11.458397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30245 11:00:11.458952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30246 11:00:11.495996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30248 11:00:11.496443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30249 11:00:11.530791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30250 11:00:11.531221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30252 11:00:11.566566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30254 11:00:11.567008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30255 11:00:11.612807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30256 11:00:11.613229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30258 11:00:11.657712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30260 11:00:11.658143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30261 11:00:11.695711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30263 11:00:11.696173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30264 11:00:11.736748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30265 11:00:11.737201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30267 11:00:11.790144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30268 11:00:11.790586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30270 11:00:11.844527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30272 11:00:11.845031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30273 11:00:11.895521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30274 11:00:11.895964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30276 11:00:11.944120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30277 11:00:11.944567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30279 11:00:11.990114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30281 11:00:11.990537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30282 11:00:12.035708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30283 11:00:12.036128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30285 11:00:12.080690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30286 11:00:12.081112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30288 11:00:12.127373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30289 11:00:12.127674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30291 11:00:12.171503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30292 11:00:12.171935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30294 11:00:12.221239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30296 11:00:12.221564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30297 11:00:12.265682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30298 11:00:12.265954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30300 11:00:12.312254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30302 11:00:12.312559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30303 11:00:12.359252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30304 11:00:12.359547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30306 11:00:12.408616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30307 11:00:12.408908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30309 11:00:12.459513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30310 11:00:12.459820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30312 11:00:12.500996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30314 11:00:12.501333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30315 11:00:12.541355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30316 11:00:12.541775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30318 11:00:12.592738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30319 11:00:12.593074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30321 11:00:12.632440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30322 11:00:12.632733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30324 11:00:12.688859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30325 11:00:12.689163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30327 11:00:12.742031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30329 11:00:12.742515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30330 11:00:12.786368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30331 11:00:12.786797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30333 11:00:12.839261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30335 11:00:12.839801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30336 11:00:12.888064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30338 11:00:12.888534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30339 11:00:12.939433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30341 11:00:12.939919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30342 11:00:12.986489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30344 11:00:12.986986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30345 11:00:13.037274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30347 11:00:13.037752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30348 11:00:13.083867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30350 11:00:13.084338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30351 11:00:13.133319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30353 11:00:13.133758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30354 11:00:13.179797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30355 11:00:13.180240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30357 11:00:13.236389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30358 11:00:13.236859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30360 11:00:13.291210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30361 11:00:13.291625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30363 11:00:13.335641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30365 11:00:13.336111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30366 11:00:13.386962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30368 11:00:13.387397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30369 11:00:13.419631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30370 11:00:13.419949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30372 11:00:13.466371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30374 11:00:13.466892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30375 11:00:13.512842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30376 11:00:13.513279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30378 11:00:13.553814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30379 11:00:13.554246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30381 11:00:13.599806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30382 11:00:13.600247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30384 11:00:13.643622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30385 11:00:13.644068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30387 11:00:13.689432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30388 11:00:13.689887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30390 11:00:13.736204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30392 11:00:13.736700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30393 11:00:13.781708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30394 11:00:13.782134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30396 11:00:13.827788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30397 11:00:13.828214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30399 11:00:13.872894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30400 11:00:13.873319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30402 11:00:13.917797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30404 11:00:13.918287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30405 11:00:13.964300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30407 11:00:13.964782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30408 11:00:14.013509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30410 11:00:14.013997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30411 11:00:14.064052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30413 11:00:14.064519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30414 11:00:14.107436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30416 11:00:14.107911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30417 11:00:14.153772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30419 11:00:14.154280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30420 11:00:14.199032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30422 11:00:14.199503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30423 11:00:14.242314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30425 11:00:14.242722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30426 11:00:14.289119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30427 11:00:14.289549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30429 11:00:14.325022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30430 11:00:14.325470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30432 11:00:14.372001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30434 11:00:14.372464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30435 11:00:14.425479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30436 11:00:14.425913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30438 11:00:14.473937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30439 11:00:14.474395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30441 11:00:14.518169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30443 11:00:14.518619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30444 11:00:14.569338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30445 11:00:14.569762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30447 11:00:14.619594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30448 11:00:14.620016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30450 11:00:14.673532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30451 11:00:14.673996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30453 11:00:14.725205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30454 11:00:14.725634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30456 11:00:14.763784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30458 11:00:14.764255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30459 11:00:14.800663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30460 11:00:14.801041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30462 11:00:14.845202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30464 11:00:14.845688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30465 11:00:14.895821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30467 11:00:14.896228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30468 11:00:14.939898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30469 11:00:14.940328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30471 11:00:14.984744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30472 11:00:14.985134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30474 11:00:15.028496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30475 11:00:15.028910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30477 11:00:15.072215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30479 11:00:15.072624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30480 11:00:15.116286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30482 11:00:15.116737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30483 11:00:15.159907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30484 11:00:15.160331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30486 11:00:15.228498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30487 11:00:15.228846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30489 11:00:15.276553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30491 11:00:15.277034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30492 11:00:15.323718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30493 11:00:15.324053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30495 11:00:15.371409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30497 11:00:15.371713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30498 11:00:15.419173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30500 11:00:15.419472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30501 11:00:15.466977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30503 11:00:15.467274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30504 11:00:15.513692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30505 11:00:15.514114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30507 11:00:15.561569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30508 11:00:15.561986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30510 11:00:15.608402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30511 11:00:15.608704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30513 11:00:15.655546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30514 11:00:15.656102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30516 11:00:15.702747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30517 11:00:15.703158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30519 11:00:15.751531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30520 11:00:15.751969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30522 11:00:15.799802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30523 11:00:15.800088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30525 11:00:15.847404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30526 11:00:15.847701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30528 11:00:15.893813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30529 11:00:15.894098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30531 11:00:15.940654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30533 11:00:15.940962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30534 11:00:15.987734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30535 11:00:15.988021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30537 11:00:16.033855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30538 11:00:16.034272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30540 11:00:16.083185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30541 11:00:16.083605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30543 11:00:16.130448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30545 11:00:16.130894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30546 11:00:16.177333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30547 11:00:16.177747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30549 11:00:16.228698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30550 11:00:16.229062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30552 11:00:16.271789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30553 11:00:16.272058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30555 11:00:16.317934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30557 11:00:16.318208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30558 11:00:16.364980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30559 11:00:16.365266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30561 11:00:16.411825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30562 11:00:16.412136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30564 11:00:16.459664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30565 11:00:16.459950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30567 11:00:16.506531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30569 11:00:16.506978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30570 11:00:16.553673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30572 11:00:16.554111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30573 11:00:16.600578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30574 11:00:16.600932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30576 11:00:16.647617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30577 11:00:16.647889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30579 11:00:16.694251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30581 11:00:16.694577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30582 11:00:16.742037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30583 11:00:16.742332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30585 11:00:16.788710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30586 11:00:16.789026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30588 11:00:16.835740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30589 11:00:16.836164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30591 11:00:16.883127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30593 11:00:16.883626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30594 11:00:16.929417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30595 11:00:16.929842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30597 11:00:16.977712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30598 11:00:16.978120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30600 11:00:17.024199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30601 11:00:17.024602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30603 11:00:17.071873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30604 11:00:17.072251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30606 11:00:17.118467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30608 11:00:17.118913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30609 11:00:17.165230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30610 11:00:17.165603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30612 11:00:17.215511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30613 11:00:17.216001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30615 11:00:17.263568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30616 11:00:17.263998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30618 11:00:17.310886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30619 11:00:17.311293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30621 11:00:17.357658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30623 11:00:17.358128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30624 11:00:17.405040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30625 11:00:17.405444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30627 11:00:17.452245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30628 11:00:17.452597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30630 11:00:17.500654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30632 11:00:17.501018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30633 11:00:17.548111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30634 11:00:17.548408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30636 11:00:17.595801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30637 11:00:17.596181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30639 11:00:17.642911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30640 11:00:17.643355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30642 11:00:17.689772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30643 11:00:17.690141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30645 11:00:17.723101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30647 11:00:17.723553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30648 11:00:17.755586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30649 11:00:17.755993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30651 11:00:17.788122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30652 11:00:17.788529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30654 11:00:17.820193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30655 11:00:17.820621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30657 11:00:17.862880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30658 11:00:17.863298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30660 11:00:17.895912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30661 11:00:17.896313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30663 11:00:17.939439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30664 11:00:17.939863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30666 11:00:17.983343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30667 11:00:17.983759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30669 11:00:18.027914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30671 11:00:18.028365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30672 11:00:18.071384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30674 11:00:18.071817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30675 11:00:18.114744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30676 11:00:18.115131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30678 11:00:18.159777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30679 11:00:18.160190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30681 11:00:18.203438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30682 11:00:18.203844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30684 11:00:18.247380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30685 11:00:18.247808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30687 11:00:18.291428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30689 11:00:18.291869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30690 11:00:18.324111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30692 11:00:18.324571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30693 11:00:18.357719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30695 11:00:18.358200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30696 11:00:18.391062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30698 11:00:18.391526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30699 11:00:18.423662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30701 11:00:18.424130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30702 11:00:18.458347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30704 11:00:18.459731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30705 11:00:18.498472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30707 11:00:18.498972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30708 11:00:18.533352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30710 11:00:18.533815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30711 11:00:18.566267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30713 11:00:18.566713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30714 11:00:18.599408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30715 11:00:18.599825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30717 11:00:18.631551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30718 11:00:18.631965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30720 11:00:18.663798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30721 11:00:18.664233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30723 11:00:18.696493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30724 11:00:18.696912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30726 11:00:18.729434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30727 11:00:18.729837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30729 11:00:18.774675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30730 11:00:18.775092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30732 11:00:18.820433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30733 11:00:18.820767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30735 11:00:18.864665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30737 11:00:18.865089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30738 11:00:18.908736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30740 11:00:18.909429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30741 11:00:18.955414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30743 11:00:18.955845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30744 11:00:19.000108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30745 11:00:19.000549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30747 11:00:19.044312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30748 11:00:19.044737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30750 11:00:19.088791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30751 11:00:19.089210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30753 11:00:19.136437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30754 11:00:19.136883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30756 11:00:19.178418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30758 11:00:19.179015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30759 11:00:19.223784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30760 11:00:19.224217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30762 11:00:19.260478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30764 11:00:19.260955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30765 11:00:19.293184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30767 11:00:19.293667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30768 11:00:19.331927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30769 11:00:19.332349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30771 11:00:19.375478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30772 11:00:19.375896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30774 11:00:19.420131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30775 11:00:19.420521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30777 11:00:19.464058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30779 11:00:19.464506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30780 11:00:19.507767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30781 11:00:19.508189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30783 11:00:19.551617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30785 11:00:19.552059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30786 11:00:19.595326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30788 11:00:19.595759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30789 11:00:19.643766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30790 11:00:19.644217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30792 11:00:19.682303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30794 11:00:19.682753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30795 11:00:19.722125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30796 11:00:19.722553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30798 11:00:19.757403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30799 11:00:19.757809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30801 11:00:19.790937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30802 11:00:19.791355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30804 11:00:19.824630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30805 11:00:19.825045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30807 11:00:19.869788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30808 11:00:19.870203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30810 11:00:19.909779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30811 11:00:19.910240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30813 11:00:19.942748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30814 11:00:19.943161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30816 11:00:19.975502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30817 11:00:19.975924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30819 11:00:20.015939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30821 11:00:20.016409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30822 11:00:20.049134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30824 11:00:20.049576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30825 11:00:20.092173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30826 11:00:20.092593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30828 11:00:20.136247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30829 11:00:20.136672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30831 11:00:20.182082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30832 11:00:20.182487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30834 11:00:20.226915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30835 11:00:20.227320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30837 11:00:20.269792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30838 11:00:20.270222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30840 11:00:20.308092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30842 11:00:20.308550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30843 11:00:20.352332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30845 11:00:20.352808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30846 11:00:20.385569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30847 11:00:20.385986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30849 11:00:20.429688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30850 11:00:20.430108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30852 11:00:20.468758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30854 11:00:20.469205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30855 11:00:20.512894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30856 11:00:20.513297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30858 11:00:20.573830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30859 11:00:20.574293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30861 11:00:20.613562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30863 11:00:20.614055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30864 11:00:20.668246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30865 11:00:20.668674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30867 11:00:20.719194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30868 11:00:20.719489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30870 11:00:20.769754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30871 11:00:20.770074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30873 11:00:20.820805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30875 11:00:20.821101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30876 11:00:20.872863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30877 11:00:20.873268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30879 11:00:20.920247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30880 11:00:20.920698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30882 11:00:20.967988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30883 11:00:20.968434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30885 11:00:21.016256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30886 11:00:21.016715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30888 11:00:21.063657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30889 11:00:21.064081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30891 11:00:21.111216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30893 11:00:21.111696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30894 11:00:21.158864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30896 11:00:21.159321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30897 11:00:21.205524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30899 11:00:21.205839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30900 11:00:21.253891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30901 11:00:21.254328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30903 11:00:21.301700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30904 11:00:21.302058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30906 11:00:21.348642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30907 11:00:21.348932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30909 11:00:21.397530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30910 11:00:21.397921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30912 11:00:21.445749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30913 11:00:21.446187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30915 11:00:21.494348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30917 11:00:21.494777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30918 11:00:21.540543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30919 11:00:21.540984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30921 11:00:21.585224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30922 11:00:21.585625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30924 11:00:21.631023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30926 11:00:21.631479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30927 11:00:21.675782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30928 11:00:21.676124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30930 11:00:21.721636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30931 11:00:21.721934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30933 11:00:21.769455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30934 11:00:21.769750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30936 11:00:21.819221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30937 11:00:21.819674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30939 11:00:21.868501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30940 11:00:21.868898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30942 11:00:21.917401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30944 11:00:21.917868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30945 11:00:21.969438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30946 11:00:21.969882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30948 11:00:22.022310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30950 11:00:22.022950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30951 11:00:22.072509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30952 11:00:22.072885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30954 11:00:22.125496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30955 11:00:22.125904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30957 11:00:22.177327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30959 11:00:22.177797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30960 11:00:22.228654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30962 11:00:22.229118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30963 11:00:22.280614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30965 11:00:22.281066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30966 11:00:22.335271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30968 11:00:22.335745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30969 11:00:22.375283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
30970 11:00:22.375712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
30972 11:00:22.420901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
30974 11:00:22.421383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
30975 11:00:22.466027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
30976 11:00:22.466461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
30978 11:00:22.512114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
30979 11:00:22.512542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
30981 11:00:22.558591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
30983 11:00:22.559129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
30984 11:00:22.605958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
30986 11:00:22.606439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
30987 11:00:22.652548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
30988 11:00:22.652947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
30990 11:00:22.699322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
30991 11:00:22.699738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
30993 11:00:22.744485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
30994 11:00:22.744904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
30996 11:00:22.790918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
30997 11:00:22.791297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
30999 11:00:22.835998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31001 11:00:22.836421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
31002 11:00:22.883051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31003 11:00:22.883469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31005 11:00:22.917510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31006 11:00:22.917935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31008 11:00:22.962345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31009 11:00:22.962773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31011 11:00:22.996496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31012 11:00:22.996919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31014 11:00:23.031327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31016 11:00:23.031772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31017 11:00:23.073553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31019 11:00:23.074044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31020 11:00:23.107788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31021 11:00:23.108245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31023 11:00:23.141819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31024 11:00:23.142274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31026 11:00:23.187239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31028 11:00:23.187667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31029 11:00:23.231512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31031 11:00:23.231958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31032 11:00:23.265899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31034 11:00:23.266371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31035 11:00:23.300044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31036 11:00:23.300487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31038 11:00:23.334285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31039 11:00:23.334739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31041 11:00:23.368681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31042 11:00:23.369101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31044 11:00:23.403779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31046 11:00:23.404250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31047 11:00:23.438300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31049 11:00:23.438754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31050 11:00:23.483159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31051 11:00:23.483594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31053 11:00:23.524944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31054 11:00:23.525397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31056 11:00:23.567115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31057 11:00:23.567525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31059 11:00:23.613633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31060 11:00:23.614089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31062 11:00:23.667120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31063 11:00:23.667537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31065 11:00:23.709484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31066 11:00:23.709923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31068 11:00:23.752383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31070 11:00:23.752857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31071 11:00:23.792974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31072 11:00:23.793400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31074 11:00:23.828722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31075 11:00:23.829175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31077 11:00:23.872356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31078 11:00:23.872785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31080 11:00:23.908230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31081 11:00:23.908680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31083 11:00:23.943796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31084 11:00:23.944252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31086 11:00:23.979530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31087 11:00:23.979980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31089 11:00:24.015395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31090 11:00:24.015844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31092 11:00:24.051111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31093 11:00:24.051560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31095 11:00:24.085947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31096 11:00:24.086387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31098 11:00:24.132869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31099 11:00:24.133289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31101 11:00:24.168950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31102 11:00:24.169395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31104 11:00:24.203695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31105 11:00:24.204142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31107 11:00:24.239081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31108 11:00:24.239536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31110 11:00:24.274897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31111 11:00:24.275350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31113 11:00:24.319436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31114 11:00:24.319879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31116 11:00:24.363915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31118 11:00:24.364372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31119 11:00:24.412777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31120 11:00:24.413179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31122 11:00:24.459911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31123 11:00:24.460332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31125 11:00:24.505238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31126 11:00:24.505697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31128 11:00:24.550922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31129 11:00:24.551365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31131 11:00:24.595688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31132 11:00:24.596140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31134 11:00:24.641539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31135 11:00:24.641957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31137 11:00:24.686107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31138 11:00:24.686547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31140 11:00:24.738996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31141 11:00:24.739411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31143 11:00:24.790310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31145 11:00:24.790746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31146 11:00:24.843157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31147 11:00:24.843582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31149 11:00:24.893063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31150 11:00:24.893456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31152 11:00:24.945027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31153 11:00:24.945462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31155 11:00:24.998954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31156 11:00:24.999368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31158 11:00:25.051306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31159 11:00:25.051688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31161 11:00:25.099355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31162 11:00:25.099799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31164 11:00:25.151788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31165 11:00:25.152231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31167 11:00:25.200426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31168 11:00:25.200857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31170 11:00:25.250273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31171 11:00:25.250703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31173 11:00:25.300326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31174 11:00:25.300757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31176 11:00:25.349789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31177 11:00:25.350221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31179 11:00:25.400397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31180 11:00:25.400820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31182 11:00:25.471870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31183 11:00:25.472306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31185 11:00:25.511077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31186 11:00:25.511536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31188 11:00:25.549014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31189 11:00:25.549464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31191 11:00:25.586865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31193 11:00:25.587337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31194 11:00:25.624765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31195 11:00:25.625202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31197 11:00:25.663286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31198 11:00:25.663708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31200 11:00:25.713222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31201 11:00:25.713665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31203 11:00:25.759281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31204 11:00:25.759718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31206 11:00:25.811725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31207 11:00:25.812169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31209 11:00:25.863796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31210 11:00:25.864256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31212 11:00:25.912768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31214 11:00:25.913266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31215 11:00:25.960392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31217 11:00:25.960841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31218 11:00:26.008562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31219 11:00:26.008989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31221 11:00:26.056187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31222 11:00:26.056592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31224 11:00:26.109053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31225 11:00:26.109491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31227 11:00:26.165065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31228 11:00:26.165509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31230 11:00:26.219593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31231 11:00:26.220019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31233 11:00:26.275969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31234 11:00:26.276410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31236 11:00:26.333692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31238 11:00:26.334156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31239 11:00:26.390438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31241 11:00:26.390891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31242 11:00:26.447190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31243 11:00:26.447628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31245 11:00:26.503351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31246 11:00:26.503745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31248 11:00:26.553211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31249 11:00:26.553659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31251 11:00:26.602963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31252 11:00:26.603396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31254 11:00:26.640096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31256 11:00:26.640539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31257 11:00:26.688362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31259 11:00:26.688865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31260 11:00:26.739624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31261 11:00:26.740075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31263 11:00:26.788509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31265 11:00:26.788946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31266 11:00:26.841102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31268 11:00:26.841599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31269 11:00:26.880525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31270 11:00:26.880979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31272 11:00:26.919328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31274 11:00:26.919786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31275 11:00:26.956442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31276 11:00:26.956899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31278 11:00:27.008273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31279 11:00:27.008724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31281 11:00:27.059710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31282 11:00:27.060172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31284 11:00:27.108762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31285 11:00:27.109206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31287 11:00:27.159971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31288 11:00:27.160430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31290 11:00:27.211928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31292 11:00:27.212416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31293 11:00:27.261921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31294 11:00:27.262378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31296 11:00:27.303933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31297 11:00:27.304387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31299 11:00:27.344372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31301 11:00:27.344863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31302 11:00:27.392242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31303 11:00:27.392696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31305 11:00:27.441433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31307 11:00:27.441944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31308 11:00:27.489125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31309 11:00:27.489569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31311 11:00:27.528519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31312 11:00:27.528925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31314 11:00:27.580011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31315 11:00:27.580462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31317 11:00:27.630215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31318 11:00:27.630681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31320 11:00:27.668423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31321 11:00:27.668875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31323 11:00:27.706269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31324 11:00:27.706724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31326 11:00:27.745174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31327 11:00:27.745621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31329 11:00:27.794202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31330 11:00:27.794639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31332 11:00:27.847097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31333 11:00:27.847486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31335 11:00:27.893692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31336 11:00:27.894109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31338 11:00:27.940849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31339 11:00:27.941202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31341 11:00:27.987928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31342 11:00:27.988226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31344 11:00:28.035044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31346 11:00:28.035425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31347 11:00:28.080872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31349 11:00:28.081231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31350 11:00:28.128826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31351 11:00:28.129157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31353 11:00:28.176219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31354 11:00:28.176623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31356 11:00:28.222810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31357 11:00:28.223186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31359 11:00:28.269279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31361 11:00:28.269584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31362 11:00:28.315853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31364 11:00:28.316268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31365 11:00:28.363037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31367 11:00:28.363581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31368 11:00:28.409162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31369 11:00:28.409465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31371 11:00:28.456121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31372 11:00:28.456529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31374 11:00:28.503280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31375 11:00:28.503566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31377 11:00:28.549618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31379 11:00:28.549982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31380 11:00:28.596545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31382 11:00:28.596851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31383 11:00:28.643198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31385 11:00:28.643657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31386 11:00:28.689639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31388 11:00:28.690145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31389 11:00:28.736526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31391 11:00:28.736963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31392 11:00:28.783426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31393 11:00:28.783846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31395 11:00:28.829682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31396 11:00:28.830129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31398 11:00:28.876611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31399 11:00:28.877000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31401 11:00:28.923545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31403 11:00:28.923941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31404 11:00:28.971258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31406 11:00:28.971761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31407 11:00:29.008023 <47>[ 380.392786] systemd-journald[109]: Sent WATCHDOG=1 notification.
31408 11:00:29.032948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31410 11:00:29.033375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31411 11:00:29.080234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31412 11:00:29.080622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31414 11:00:29.127309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31415 11:00:29.127733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31417 11:00:29.174831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31418 11:00:29.175240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31420 11:00:29.221312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31421 11:00:29.221690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31423 11:00:29.269727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31424 11:00:29.270169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31426 11:00:29.319966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31428 11:00:29.320437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31429 11:00:29.370929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31431 11:00:29.371391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31432 11:00:29.417916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31433 11:00:29.418341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31435 11:00:29.468115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31436 11:00:29.468520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31438 11:00:29.517436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31439 11:00:29.517862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31441 11:00:29.565578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31442 11:00:29.565975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31444 11:00:29.613244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31445 11:00:29.613659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31447 11:00:29.667582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31449 11:00:29.668070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31450 11:00:29.720820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31451 11:00:29.721253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31453 11:00:29.774481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31455 11:00:29.774958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31456 11:00:29.827988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31457 11:00:29.828442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31459 11:00:29.881482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31460 11:00:29.881932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31462 11:00:29.936695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31464 11:00:29.937148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31465 11:00:29.987616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31466 11:00:29.988047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31468 11:00:30.034839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31469 11:00:30.035262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31471 11:00:30.083136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31472 11:00:30.083512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31474 11:00:30.131261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31475 11:00:30.131646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31477 11:00:30.179708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31479 11:00:30.180164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31480 11:00:30.227199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31481 11:00:30.227628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31483 11:00:30.273619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31484 11:00:30.274038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31486 11:00:30.320962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31487 11:00:30.321380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31489 11:00:30.367972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31490 11:00:30.368362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31492 11:00:30.415225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31493 11:00:30.415641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31495 11:00:30.462105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31497 11:00:30.462516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31498 11:00:30.512830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31500 11:00:30.513281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31501 11:00:30.585222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31503 11:00:30.585686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31504 11:00:30.631362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31505 11:00:30.631790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31507 11:00:30.673887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31508 11:00:30.674330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31510 11:00:30.706837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31511 11:00:30.707147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31513 11:00:30.739860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31514 11:00:30.740267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31516 11:00:30.773060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31517 11:00:30.773477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31519 11:00:30.816731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31520 11:00:30.817081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31522 11:00:30.862078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31524 11:00:30.862424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31525 11:00:30.906771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31527 11:00:30.907065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31528 11:00:30.950856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31529 11:00:30.951145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31531 11:00:30.995118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31532 11:00:30.995609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31534 11:00:31.039424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31535 11:00:31.039840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31537 11:00:31.083999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31538 11:00:31.084410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31540 11:00:31.128322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31541 11:00:31.128594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31543 11:00:31.174347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31545 11:00:31.174766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31546 11:00:31.212451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31548 11:00:31.212841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31549 11:00:31.257150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31550 11:00:31.257565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31552 11:00:31.301229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31554 11:00:31.301488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31555 11:00:31.345539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31556 11:00:31.345817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31558 11:00:31.392295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31559 11:00:31.392689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31561 11:00:31.436553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31563 11:00:31.436881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31564 11:00:31.484063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31565 11:00:31.484354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31567 11:00:31.531491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31569 11:00:31.531876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31570 11:00:31.577401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31571 11:00:31.577677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31573 11:00:31.621094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31575 11:00:31.621346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31576 11:00:31.664899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31577 11:00:31.665192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31579 11:00:31.708690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31580 11:00:31.709114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31582 11:00:31.753120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31583 11:00:31.753447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31585 11:00:31.797994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31587 11:00:31.798300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31588 11:00:31.842244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31590 11:00:31.842643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31591 11:00:31.885601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31592 11:00:31.885904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31594 11:00:31.929340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31596 11:00:31.929658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31597 11:00:31.974111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31598 11:00:31.974410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31600 11:00:32.018992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31601 11:00:32.019368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31603 11:00:32.053990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31604 11:00:32.054414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31606 11:00:32.097769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31607 11:00:32.098050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31609 11:00:32.141741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31611 11:00:32.142045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31612 11:00:32.185395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31613 11:00:32.185675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31615 11:00:32.228903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31616 11:00:32.229208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31618 11:00:32.272205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31619 11:00:32.272594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31621 11:00:32.316338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31623 11:00:32.316898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31624 11:00:32.359634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31625 11:00:32.359924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31627 11:00:32.403350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31628 11:00:32.403632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31630 11:00:32.447135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31631 11:00:32.447428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31633 11:00:32.491137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31635 11:00:32.491534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31636 11:00:32.534925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31637 11:00:32.535300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31639 11:00:32.579972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31641 11:00:32.580544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31642 11:00:32.623639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31643 11:00:32.623928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31645 11:00:32.667261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31646 11:00:32.667548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31648 11:00:32.711199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31650 11:00:32.711493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31651 11:00:32.755008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31652 11:00:32.755300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31654 11:00:32.799299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31655 11:00:32.799590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31657 11:00:32.842984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31658 11:00:32.843257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31660 11:00:32.886886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31661 11:00:32.887157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31663 11:00:32.930160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31665 11:00:32.930454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31666 11:00:32.973992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31667 11:00:32.974275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31669 11:00:33.018052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31670 11:00:33.018343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31672 11:00:33.062028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31673 11:00:33.062310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31675 11:00:33.106186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31677 11:00:33.106532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31678 11:00:33.150493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31680 11:00:33.150801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31681 11:00:33.194242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31683 11:00:33.194547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31684 11:00:33.237865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31685 11:00:33.238176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31687 11:00:33.281881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31688 11:00:33.282164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31690 11:00:33.327119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31691 11:00:33.327556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31693 11:00:33.361035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31694 11:00:33.361442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31696 11:00:33.394418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31698 11:00:33.394950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31699 11:00:33.427554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31700 11:00:33.427962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31702 11:00:33.471996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31704 11:00:33.472426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31705 11:00:33.515854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31706 11:00:33.516261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31708 11:00:33.559580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31710 11:00:33.560022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31711 11:00:33.603400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31712 11:00:33.603805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31714 11:00:33.636952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31716 11:00:33.637420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31717 11:00:33.670804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31718 11:00:33.671223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31720 11:00:33.703710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31722 11:00:33.704166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31723 11:00:33.737334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31724 11:00:33.737744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31726 11:00:33.770068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31727 11:00:33.770497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31729 11:00:33.803158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31730 11:00:33.803574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31732 11:00:33.835971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31734 11:00:33.836420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31735 11:00:33.869512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31736 11:00:33.869961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31738 11:00:33.903339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31739 11:00:33.903765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31741 11:00:33.936901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31742 11:00:33.937321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31744 11:00:33.971645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31745 11:00:33.972087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31747 11:00:34.007175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31748 11:00:34.007596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31750 11:00:34.041181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31751 11:00:34.041604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31753 11:00:34.074243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31755 11:00:34.074754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31756 11:00:34.107665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31758 11:00:34.108111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31759 11:00:34.140727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31760 11:00:34.141106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31762 11:00:34.184731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31764 11:00:34.185173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31765 11:00:34.230028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31766 11:00:34.230458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31768 11:00:34.275887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31769 11:00:34.276254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31771 11:00:34.323482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31772 11:00:34.323920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31774 11:00:34.367494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31775 11:00:34.367913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31777 11:00:34.412578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31778 11:00:34.413021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31780 11:00:34.456590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31782 11:00:34.457025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31783 11:00:34.501076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31784 11:00:34.501478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31786 11:00:34.545619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31787 11:00:34.546079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31789 11:00:34.592154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31791 11:00:34.592668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31792 11:00:34.637298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31793 11:00:34.637635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31795 11:00:34.681329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31796 11:00:34.681683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31798 11:00:34.725583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31800 11:00:34.725979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31801 11:00:34.769580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31802 11:00:34.769993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31804 11:00:34.817425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31805 11:00:34.817853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31807 11:00:34.861014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31808 11:00:34.861422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31810 11:00:34.904776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31812 11:00:34.905218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31813 11:00:34.949102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31814 11:00:34.949528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31816 11:00:34.985808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31817 11:00:34.986235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31819 11:00:35.015727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31820 11:00:35.016145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31822 11:00:35.048470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31823 11:00:35.048899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31825 11:00:35.081359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31826 11:00:35.081784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31828 11:00:35.113933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31829 11:00:35.114360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31831 11:00:35.160387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31833 11:00:35.160805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31834 11:00:35.203265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31836 11:00:35.203568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31837 11:00:35.237105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31838 11:00:35.237398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31840 11:00:35.280543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31841 11:00:35.280990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31843 11:00:35.327515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31845 11:00:35.327975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31846 11:00:35.372705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31848 11:00:35.373164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31849 11:00:35.417017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31851 11:00:35.417468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31852 11:00:35.460730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31854 11:00:35.461166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31855 11:00:35.504682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31856 11:00:35.505089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31858 11:00:35.536908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31859 11:00:35.537353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31861 11:00:35.569713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31862 11:00:35.570159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31864 11:00:35.603124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31866 11:00:35.603584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31867 11:00:35.647423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31868 11:00:35.647859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31870 11:00:35.704668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31872 11:00:35.704976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31873 11:00:35.737967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31875 11:00:35.738270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31876 11:00:35.782464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31878 11:00:35.782775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31879 11:00:35.826075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31881 11:00:35.826518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31882 11:00:35.869692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31883 11:00:35.870113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31885 11:00:35.917528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31887 11:00:35.917961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31888 11:00:35.950861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31889 11:00:35.951309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31891 11:00:35.987745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31893 11:00:35.988189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31894 11:00:36.031780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31895 11:00:36.032194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31897 11:00:36.075734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31898 11:00:36.076115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31900 11:00:36.119646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31901 11:00:36.120062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31903 11:00:36.163208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31904 11:00:36.163624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31906 11:00:36.207386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31907 11:00:36.207810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31909 11:00:36.252332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31911 11:00:36.252735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31912 11:00:36.295670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31913 11:00:36.296054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31915 11:00:36.339229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31916 11:00:36.339771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31918 11:00:36.371873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31919 11:00:36.372298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31921 11:00:36.415394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31922 11:00:36.415817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31924 11:00:36.462081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31925 11:00:36.462510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31927 11:00:36.509275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31928 11:00:36.509686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31930 11:00:36.545219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31931 11:00:36.545676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31933 11:00:36.591325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31934 11:00:36.591770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31936 11:00:36.635981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31938 11:00:36.636455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31939 11:00:36.670092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31940 11:00:36.670533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31942 11:00:36.716282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31943 11:00:36.716705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31945 11:00:36.760711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31946 11:00:36.761068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31948 11:00:36.804753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31949 11:00:36.805187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31951 11:00:36.849983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31953 11:00:36.851638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31954 11:00:36.895527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31955 11:00:36.895823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31957 11:00:36.939213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31958 11:00:36.939508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31960 11:00:36.982926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31961 11:00:36.983222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31963 11:00:37.026729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31964 11:00:37.026998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31966 11:00:37.069887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31967 11:00:37.070182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31969 11:00:37.114011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31970 11:00:37.114305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
31972 11:00:37.158033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
31974 11:00:37.158340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
31975 11:00:37.202300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
31977 11:00:37.202713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
31978 11:00:37.243434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
31979 11:00:37.243728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
31981 11:00:37.288568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
31982 11:00:37.288975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
31984 11:00:37.334349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
31986 11:00:37.334766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
31987 11:00:37.367243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
31988 11:00:37.367629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
31990 11:00:37.410783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
31992 11:00:37.411241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
31993 11:00:37.443438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
31994 11:00:37.443849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
31996 11:00:37.477093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
31997 11:00:37.477528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
31999 11:00:37.510127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32001 11:00:37.510576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
32002 11:00:37.543366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32003 11:00:37.543806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32005 11:00:37.576997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32006 11:00:37.577418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32008 11:00:37.616739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32009 11:00:37.617159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32011 11:00:37.663653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32012 11:00:37.664059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32014 11:00:37.707905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32015 11:00:37.708327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32017 11:00:37.752560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32018 11:00:37.752985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32020 11:00:37.797014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32021 11:00:37.797401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32023 11:00:37.841992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32025 11:00:37.842291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32026 11:00:37.880120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32028 11:00:37.880569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32029 11:00:37.924614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32030 11:00:37.925033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32032 11:00:37.958354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32034 11:00:37.958813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32035 11:00:38.007239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32036 11:00:38.007660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32038 11:00:38.044749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32039 11:00:38.045166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32041 11:00:38.081896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32042 11:00:38.082334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32044 11:00:38.117774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32045 11:00:38.118195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32047 11:00:38.156706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32048 11:00:38.157151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32050 11:00:38.200876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32051 11:00:38.201301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32053 11:00:38.235251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32054 11:00:38.235682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32056 11:00:38.278906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32057 11:00:38.279307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32059 11:00:38.323316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32060 11:00:38.323732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32062 11:00:38.356388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32063 11:00:38.356820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32065 11:00:38.403871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32067 11:00:38.404341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32068 11:00:38.441578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32070 11:00:38.442067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32071 11:00:38.475590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32072 11:00:38.476028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32074 11:00:38.511663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32076 11:00:38.512121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32077 11:00:38.557991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32078 11:00:38.558385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32080 11:00:38.603851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32081 11:00:38.604249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32083 11:00:38.648474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32084 11:00:38.648858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32086 11:00:38.693302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32087 11:00:38.693690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32089 11:00:38.737983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32091 11:00:38.738441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32092 11:00:38.781932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32093 11:00:38.782345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32095 11:00:38.826557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32097 11:00:38.826997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32098 11:00:38.871207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32100 11:00:38.871659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32101 11:00:38.917765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32102 11:00:38.918295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32104 11:00:38.960998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32106 11:00:38.961303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32107 11:00:39.005176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32108 11:00:39.005585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32110 11:00:39.049078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32111 11:00:39.049476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32113 11:00:39.094822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32115 11:00:39.095298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32116 11:00:39.129383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32118 11:00:39.129863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32119 11:00:39.165898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32121 11:00:39.166397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32122 11:00:39.199704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32123 11:00:39.200125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32125 11:00:39.234149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32127 11:00:39.234570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32128 11:00:39.279141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32130 11:00:39.279608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32131 11:00:39.312338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32132 11:00:39.312781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32134 11:00:39.348303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32135 11:00:39.348737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32137 11:00:39.381622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32139 11:00:39.382097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32140 11:00:39.414843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32142 11:00:39.415287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32143 11:00:39.449341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32144 11:00:39.449754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32146 11:00:39.489072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32148 11:00:39.489523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32149 11:00:39.522445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32151 11:00:39.522930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32152 11:00:39.558430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32153 11:00:39.558891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32155 11:00:39.597546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32156 11:00:39.600501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32158 11:00:39.642376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32160 11:00:39.642845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32161 11:00:39.691877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32163 11:00:39.692349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32164 11:00:39.740823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32166 11:00:39.741281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32167 11:00:39.793001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32169 11:00:39.793461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32170 11:00:39.835933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32172 11:00:39.836401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32173 11:00:39.884352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32175 11:00:39.884815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32176 11:00:39.931096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32178 11:00:39.931561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32179 11:00:39.975388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32181 11:00:39.975866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32182 11:00:40.008677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32183 11:00:40.009114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32185 11:00:40.052987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32186 11:00:40.053429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32188 11:00:40.094366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32190 11:00:40.094855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32191 11:00:40.128148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32192 11:00:40.128592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32194 11:00:40.161629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32195 11:00:40.162336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32197 11:00:40.196307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32198 11:00:40.196749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32200 11:00:40.229777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32201 11:00:40.230222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32203 11:00:40.263048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32204 11:00:40.263491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32206 11:00:40.296151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32207 11:00:40.296592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32209 11:00:40.329529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32210 11:00:40.330362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32212 11:00:40.363380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32213 11:00:40.363821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32215 11:00:40.397263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32216 11:00:40.397693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32218 11:00:40.430972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32219 11:00:40.431413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32221 11:00:40.463776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32222 11:00:40.464216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32224 11:00:40.497700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32225 11:00:40.498175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32227 11:00:40.531441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32228 11:00:40.531883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32230 11:00:40.570751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32231 11:00:40.571346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32233 11:00:40.604464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32234 11:00:40.604909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32236 11:00:40.638048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32237 11:00:40.638501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32239 11:00:40.671384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32240 11:00:40.671827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32242 11:00:40.704982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32243 11:00:40.705427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32245 11:00:40.747754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32246 11:00:40.748201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32248 11:00:40.812276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32249 11:00:40.812677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32251 11:00:40.862133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32252 11:00:40.862572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32254 11:00:40.912722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32255 11:00:40.913166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32257 11:00:40.962199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32258 11:00:40.962643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32260 11:00:41.012066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32261 11:00:41.012502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32263 11:00:41.061608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32264 11:00:41.062015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32266 11:00:41.109569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32267 11:00:41.110012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32269 11:00:41.159229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32271 11:00:41.159676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32272 11:00:41.206890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32273 11:00:41.207338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32275 11:00:41.259372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32276 11:00:41.259826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32278 11:00:41.310443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32279 11:00:41.310880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32281 11:00:41.360111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32282 11:00:41.360459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32284 11:00:41.411074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32285 11:00:41.411495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32287 11:00:41.460090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32288 11:00:41.460500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32290 11:00:41.509741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32291 11:00:41.510182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32293 11:00:41.561111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32294 11:00:41.561566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32296 11:00:41.611636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32297 11:00:41.614238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32299 11:00:41.661493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32301 11:00:41.661948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32302 11:00:41.711339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32304 11:00:41.711836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32305 11:00:41.763798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32306 11:00:41.764243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32308 11:00:41.816052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32309 11:00:41.816478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32311 11:00:41.868811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32312 11:00:41.869253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32314 11:00:41.917950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32315 11:00:41.918416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32317 11:00:41.970055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32318 11:00:41.970480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32320 11:00:42.019542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32322 11:00:42.020014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32323 11:00:42.067934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32325 11:00:42.068384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32326 11:00:42.117642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32327 11:00:42.118116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32329 11:00:42.168845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32330 11:00:42.169272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32332 11:00:42.219484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32333 11:00:42.219910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32335 11:00:42.269235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32336 11:00:42.269683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32338 11:00:42.318364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32339 11:00:42.318787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32341 11:00:42.367441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32342 11:00:42.367882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32344 11:00:42.415943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32345 11:00:42.416383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32347 11:00:42.464616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32349 11:00:42.465056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32350 11:00:42.513370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32351 11:00:42.513774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32353 11:00:42.563530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32355 11:00:42.564030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32356 11:00:42.612279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32357 11:00:42.612697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32359 11:00:42.660596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32361 11:00:42.661045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32362 11:00:42.708486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32363 11:00:42.708835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32365 11:00:42.756308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32366 11:00:42.756730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32368 11:00:42.805120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32369 11:00:42.805555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32371 11:00:42.855713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32373 11:00:42.856158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32374 11:00:42.905074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32376 11:00:42.905391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32377 11:00:42.950556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32379 11:00:42.951256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32380 11:00:42.995812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32381 11:00:42.996258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32383 11:00:43.043310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32384 11:00:43.043755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32386 11:00:43.089230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32387 11:00:43.089676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32389 11:00:43.134779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32390 11:00:43.135212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32392 11:00:43.178547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32394 11:00:43.179210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32395 11:00:43.223390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32396 11:00:43.223825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32398 11:00:43.268764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32399 11:00:43.269199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32401 11:00:43.312881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32402 11:00:43.313311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32404 11:00:43.357836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32405 11:00:43.358269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32407 11:00:43.403452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32408 11:00:43.403940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32410 11:00:43.447396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32411 11:00:43.447827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32413 11:00:43.492185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32414 11:00:43.492616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32416 11:00:43.537014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32417 11:00:43.537580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32419 11:00:43.583499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32420 11:00:43.583941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32422 11:00:43.630012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32423 11:00:43.630457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32425 11:00:43.676281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32426 11:00:43.676773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32428 11:00:43.726019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32429 11:00:43.726536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32431 11:00:43.769363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32432 11:00:43.769874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32434 11:00:43.815585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32435 11:00:43.816047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32437 11:00:43.859991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32438 11:00:43.860570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32440 11:00:43.905783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32441 11:00:43.906435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32443 11:00:43.952372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32444 11:00:43.952818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32446 11:00:43.997790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32447 11:00:43.998250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32449 11:00:44.032579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32450 11:00:44.033027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32452 11:00:44.067153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32453 11:00:44.067596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32455 11:00:44.101074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32456 11:00:44.101523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32458 11:00:44.135987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32460 11:00:44.136454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32461 11:00:44.172547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32462 11:00:44.172997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32464 11:00:44.208173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32465 11:00:44.208601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32467 11:00:44.253446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32468 11:00:44.253881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32470 11:00:44.299701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32472 11:00:44.300169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32473 11:00:44.333766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32474 11:00:44.334214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32476 11:00:44.367263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32477 11:00:44.367712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32479 11:00:44.408494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32480 11:00:44.408912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32482 11:00:44.449809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32483 11:00:44.450259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32485 11:00:44.488053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32486 11:00:44.489704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32488 11:00:44.528565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32490 11:00:44.529046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32491 11:00:44.574359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32493 11:00:44.575409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32494 11:00:44.612140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32495 11:00:44.612545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32497 11:00:44.646077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32499 11:00:44.646621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32500 11:00:44.695216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32501 11:00:44.695641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32503 11:00:44.741992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32504 11:00:44.742318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32506 11:00:44.789268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32507 11:00:44.789641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32509 11:00:44.836093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32510 11:00:44.836356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32512 11:00:44.877350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32513 11:00:44.877641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32515 11:00:44.920481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32516 11:00:44.920776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32518 11:00:44.965364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32519 11:00:44.965655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32521 11:00:45.011943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32523 11:00:45.012184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32524 11:00:45.059602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32525 11:00:45.059906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32527 11:00:45.096084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32528 11:00:45.096381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32530 11:00:45.132680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32531 11:00:45.133114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32533 11:00:45.168496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32535 11:00:45.168975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32536 11:00:45.204949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32538 11:00:45.205429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32539 11:00:45.241448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32540 11:00:45.241898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32542 11:00:45.276743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32543 11:00:45.277191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32545 11:00:45.319658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32547 11:00:45.320130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32548 11:00:45.365465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32550 11:00:45.365936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32551 11:00:45.409860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32552 11:00:45.410289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32554 11:00:45.455908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32555 11:00:45.456323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32557 11:00:45.500585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32559 11:00:45.501032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32560 11:00:45.548089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32561 11:00:45.548557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32563 11:00:45.595596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32564 11:00:45.596048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32566 11:00:45.641532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32567 11:00:45.641974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32569 11:00:45.687944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32570 11:00:45.688399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32572 11:00:45.734175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32573 11:00:45.734572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32575 11:00:45.779756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32577 11:00:45.780439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32578 11:00:45.813721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32579 11:00:45.814163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32581 11:00:45.847632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32582 11:00:45.848057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32584 11:00:45.883420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32585 11:00:45.883865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32587 11:00:45.935805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32589 11:00:45.936277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32590 11:00:45.972447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32592 11:00:45.972925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32593 11:00:46.007857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32594 11:00:46.008298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32596 11:00:46.041685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32597 11:00:46.042156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32599 11:00:46.075633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32600 11:00:46.076102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32602 11:00:46.109644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32603 11:00:46.110112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32605 11:00:46.143581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32606 11:00:46.144056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32608 11:00:46.178946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32609 11:00:46.179397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32611 11:00:46.221880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32612 11:00:46.222337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32614 11:00:46.256529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32615 11:00:46.256966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32617 11:00:46.290125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32619 11:00:46.290557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32620 11:00:46.323503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32621 11:00:46.323944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32623 11:00:46.358186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32624 11:00:46.358640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32626 11:00:46.392179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32627 11:00:46.392622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32629 11:00:46.425859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32630 11:00:46.426303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32632 11:00:46.461339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32633 11:00:46.461784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32635 11:00:46.496850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32636 11:00:46.497295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32638 11:00:46.536153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32640 11:00:46.536624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32641 11:00:46.571829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32642 11:00:46.572275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32644 11:00:46.607168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32645 11:00:46.607615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32647 11:00:46.642971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32648 11:00:46.643415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32650 11:00:46.680251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32651 11:00:46.680689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32653 11:00:46.726425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32655 11:00:46.726977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32656 11:00:46.771490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32658 11:00:46.771959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32659 11:00:46.812906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32660 11:00:46.813298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32662 11:00:46.848780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32664 11:00:46.849244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32665 11:00:46.884086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32666 11:00:46.884539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32668 11:00:46.927383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32670 11:00:46.927858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32671 11:00:46.961267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32672 11:00:46.961701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32674 11:00:46.996417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32675 11:00:46.996866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32677 11:00:47.030087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32678 11:00:47.030542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32680 11:00:47.064499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32681 11:00:47.064977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32683 11:00:47.099869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32684 11:00:47.100296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32686 11:00:47.136342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32687 11:00:47.136787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32689 11:00:47.171956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32690 11:00:47.172399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32692 11:00:47.208195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32693 11:00:47.208832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32695 11:00:47.249095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32696 11:00:47.249484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32698 11:00:47.302215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32699 11:00:47.302683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32701 11:00:47.353545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32703 11:00:47.353995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32704 11:00:47.392501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32705 11:00:47.392794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32707 11:00:47.439769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32708 11:00:47.440067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32710 11:00:47.480784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32711 11:00:47.481209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32713 11:00:47.536788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32714 11:00:47.537212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32716 11:00:47.591747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32717 11:00:47.592196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32719 11:00:47.640840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32720 11:00:47.641289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32722 11:00:47.692853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32723 11:00:47.695424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32725 11:00:47.729990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32726 11:00:47.730527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32728 11:00:47.767742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32729 11:00:47.768201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32731 11:00:47.806041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32733 11:00:47.806520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32734 11:00:47.843386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32735 11:00:47.843845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32737 11:00:47.884566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32738 11:00:47.885020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32740 11:00:47.925435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32741 11:00:47.925896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32743 11:00:47.964745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32744 11:00:47.965190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32746 11:00:48.014884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32748 11:00:48.015364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32749 11:00:48.051269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32751 11:00:48.051745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32752 11:00:48.097266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32753 11:00:48.097695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32755 11:00:48.144316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32756 11:00:48.144769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32758 11:00:48.183252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32760 11:00:48.183726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32761 11:00:48.227514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32762 11:00:48.227961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32764 11:00:48.275459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32766 11:00:48.275930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32767 11:00:48.324963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32769 11:00:48.325435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32770 11:00:48.365220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32771 11:00:48.365677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32773 11:00:48.408800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32774 11:00:48.409258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32776 11:00:48.445000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32777 11:00:48.445445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32779 11:00:48.485227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32780 11:00:48.485686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32782 11:00:48.532544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32784 11:00:48.533026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32785 11:00:48.570291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32786 11:00:48.570749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32788 11:00:48.607846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32790 11:00:48.608316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32791 11:00:48.648703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32793 11:00:48.649177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32794 11:00:48.685751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32795 11:00:48.686202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32797 11:00:48.723725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32798 11:00:48.724176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32800 11:00:48.773215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32802 11:00:48.773697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32803 11:00:48.820986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32804 11:00:48.821409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32806 11:00:48.871716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32807 11:00:48.872010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32809 11:00:48.911567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32810 11:00:48.911862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32812 11:00:48.949892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32813 11:00:48.950336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32815 11:00:48.988567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32816 11:00:48.989015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32818 11:00:49.025359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32819 11:00:49.025799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32821 11:00:49.062098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32822 11:00:49.062548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32824 11:00:49.099489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32825 11:00:49.099936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32827 11:00:49.136432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32828 11:00:49.136876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32830 11:00:49.173004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32831 11:00:49.173441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32833 11:00:49.210114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32834 11:00:49.210593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32836 11:00:49.248764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32837 11:00:49.249215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32839 11:00:49.286005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32841 11:00:49.286492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32842 11:00:49.320424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32843 11:00:49.320859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32845 11:00:49.355275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32846 11:00:49.355687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32848 11:00:49.392415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32849 11:00:49.392837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32851 11:00:49.427883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32853 11:00:49.428356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32854 11:00:49.463569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32856 11:00:49.464033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32857 11:00:49.503564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32859 11:00:49.504048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32860 11:00:49.540374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32861 11:00:49.540799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32863 11:00:49.579436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32865 11:00:49.579798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32866 11:00:49.623809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32867 11:00:49.624106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32869 11:00:49.668009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32870 11:00:49.668306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32872 11:00:49.719506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32874 11:00:49.719814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32875 11:00:49.781725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32876 11:00:49.782142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32878 11:00:49.837922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32879 11:00:49.838319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32881 11:00:49.884071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32883 11:00:49.884425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32884 11:00:49.920331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32885 11:00:49.920632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32887 11:00:49.963883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32888 11:00:49.964181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32890 11:00:50.013880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32891 11:00:50.014174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32893 11:00:50.055898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32894 11:00:50.056189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32896 11:00:50.103946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32897 11:00:50.104239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32899 11:00:50.152996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32900 11:00:50.153287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32902 11:00:50.189947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32903 11:00:50.190255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32905 11:00:50.226991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32906 11:00:50.227287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32908 11:00:50.270370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32910 11:00:50.270899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32911 11:00:50.323517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32912 11:00:50.323812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32914 11:00:50.376746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32916 11:00:50.377050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32917 11:00:50.429068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32919 11:00:50.429370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32920 11:00:50.477865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32922 11:00:50.478170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32923 11:00:50.527176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32924 11:00:50.527566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32926 11:00:50.575877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32927 11:00:50.576177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32929 11:00:50.624063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32930 11:00:50.624527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32932 11:00:50.673601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32934 11:00:50.673910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32935 11:00:50.729006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32936 11:00:50.729401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32938 11:00:50.783796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32939 11:00:50.784093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32941 11:00:50.836222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32942 11:00:50.836545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32944 11:00:50.870211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32946 11:00:50.870555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32947 11:00:50.911105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32949 11:00:50.911397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32950 11:00:50.949221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32951 11:00:50.949524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32953 11:00:51.003178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32954 11:00:51.003475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32956 11:00:51.083732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32958 11:00:51.084079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32959 11:00:51.131331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32960 11:00:51.131724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32962 11:00:51.176046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32963 11:00:51.176488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32965 11:00:51.220771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32966 11:00:51.221195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32968 11:00:51.255781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
32969 11:00:51.256217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32971 11:00:51.292772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
32972 11:00:51.293206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
32974 11:00:51.337105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
32976 11:00:51.337569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
32977 11:00:51.372258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
32978 11:00:51.372686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
32980 11:00:51.415888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
32981 11:00:51.416318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
32983 11:00:51.464305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
32984 11:00:51.464732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
32986 11:00:51.509706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
32987 11:00:51.510127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
32989 11:00:51.553967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
32991 11:00:51.554450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
32992 11:00:51.587692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
32993 11:00:51.588103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
32995 11:00:51.620688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
32997 11:00:51.621137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
32998 11:00:51.662035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
33000 11:00:51.662485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
33001 11:00:51.694800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33002 11:00:51.695188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33004 11:00:51.738536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33006 11:00:51.738996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33007 11:00:51.783351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33009 11:00:51.783822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33010 11:00:51.816154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33011 11:00:51.816519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33013 11:00:51.860090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33015 11:00:51.860833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33016 11:00:51.895546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33018 11:00:51.895995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33019 11:00:51.928172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33020 11:00:51.928610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33022 11:00:51.969568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33023 11:00:51.970007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33025 11:00:52.002420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33027 11:00:52.002878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33028 11:00:52.046885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33030 11:00:52.047348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33031 11:00:52.079332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33032 11:00:52.079746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33034 11:00:52.112455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33036 11:00:52.112920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33037 11:00:52.145840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33038 11:00:52.146281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33040 11:00:52.180635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33041 11:00:52.181059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33043 11:00:52.222364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33045 11:00:52.222818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33046 11:00:52.267253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33047 11:00:52.267657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33049 11:00:52.311362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33050 11:00:52.311782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33052 11:00:52.344157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33053 11:00:52.344536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33055 11:00:52.376902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33056 11:00:52.377268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33058 11:00:52.422098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33059 11:00:52.422606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33061 11:00:52.467263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33063 11:00:52.467658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33064 11:00:52.508384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33065 11:00:52.508824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33067 11:00:52.542801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33068 11:00:52.543174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33070 11:00:52.587612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33071 11:00:52.588043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33073 11:00:52.633047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33074 11:00:52.633482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33076 11:00:52.667477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33078 11:00:52.667942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33079 11:00:52.701428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33080 11:00:52.701941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33082 11:00:52.747068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33083 11:00:52.747497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33085 11:00:52.779856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33087 11:00:52.780320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33088 11:00:52.813858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33089 11:00:52.814290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33091 11:00:52.847158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33092 11:00:52.847581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33094 11:00:52.882277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33095 11:00:52.882703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33097 11:00:52.916651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33098 11:00:52.916942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33100 11:00:52.960817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33101 11:00:52.961233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33103 11:00:53.005628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33104 11:00:53.006055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33106 11:00:53.050280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33108 11:00:53.050718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33109 11:00:53.095727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33111 11:00:53.096151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33112 11:00:53.128565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33113 11:00:53.128978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33115 11:00:53.161718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33116 11:00:53.162111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33118 11:00:53.206406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33120 11:00:53.206926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33121 11:00:53.251909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33122 11:00:53.252301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33124 11:00:53.296745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33125 11:00:53.297161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33127 11:00:53.329607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33128 11:00:53.330006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33130 11:00:53.362466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33132 11:00:53.362924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33133 11:00:53.396003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33134 11:00:53.396388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33136 11:00:53.432755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33138 11:00:53.433201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33139 11:00:53.476704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33140 11:00:53.477118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33142 11:00:53.521255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33144 11:00:53.521691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33145 11:00:53.567402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33146 11:00:53.568021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33148 11:00:53.613557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33149 11:00:53.614002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33151 11:00:53.658748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33153 11:00:53.659441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33154 11:00:53.703614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33155 11:00:53.704026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33157 11:00:53.747255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33158 11:00:53.747695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33160 11:00:53.794862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33161 11:00:53.795261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33163 11:00:53.840592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33164 11:00:53.841015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33166 11:00:53.873454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33167 11:00:53.873849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33169 11:00:53.906928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33171 11:00:53.907331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33172 11:00:53.948640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33173 11:00:53.949056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33175 11:00:53.987347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33176 11:00:53.987776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33178 11:00:54.021102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33179 11:00:54.021485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33181 11:00:54.054857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33183 11:00:54.055304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33184 11:00:54.088577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33186 11:00:54.089020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33187 11:00:54.121566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33188 11:00:54.121993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33190 11:00:54.167447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33191 11:00:54.167836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33193 11:00:54.211861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33194 11:00:54.212292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33196 11:00:54.257828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33197 11:00:54.258262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33199 11:00:54.304259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33200 11:00:54.304678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33202 11:00:54.339603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33203 11:00:54.340028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33205 11:00:54.389690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33206 11:00:54.390120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33208 11:00:54.444636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33209 11:00:54.445063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33211 11:00:54.483957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33212 11:00:54.484393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33214 11:00:54.524950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33216 11:00:54.525411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33217 11:00:54.573880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33219 11:00:54.574366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33220 11:00:54.624551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33221 11:00:54.624987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33223 11:00:54.672302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33224 11:00:54.672712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33226 11:00:54.723919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33228 11:00:54.724382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33229 11:00:54.777638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33230 11:00:54.778068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33232 11:00:54.822451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33234 11:00:54.822902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33235 11:00:54.856583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33237 11:00:54.856950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33238 11:00:54.889822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33240 11:00:54.890298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33241 11:00:54.934216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33242 11:00:54.934643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33244 11:00:54.980011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33246 11:00:54.980445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33247 11:00:55.025224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33248 11:00:55.025650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33250 11:00:55.071768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33252 11:00:55.072226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33253 11:00:55.115763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33254 11:00:55.116181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33256 11:00:55.159894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33258 11:00:55.160353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33259 11:00:55.207211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33260 11:00:55.207643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33262 11:00:55.253712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33264 11:00:55.254168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33265 11:00:55.298105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33266 11:00:55.298547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33268 11:00:55.343952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33269 11:00:55.344393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33271 11:00:55.383761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33272 11:00:55.384189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33274 11:00:55.423990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33275 11:00:55.424390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33277 11:00:55.468726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33278 11:00:55.469146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33280 11:00:55.514988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33281 11:00:55.515407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33283 11:00:55.559312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33284 11:00:55.559749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33286 11:00:55.604464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33287 11:00:55.604847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33289 11:00:55.648933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33290 11:00:55.649353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33292 11:00:55.693170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33293 11:00:55.693578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33295 11:00:55.739552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33297 11:00:55.739996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33298 11:00:55.784967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33299 11:00:55.785523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33301 11:00:55.828780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33302 11:00:55.829201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33304 11:00:55.873361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33305 11:00:55.873768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33307 11:00:55.920450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33308 11:00:55.920838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33310 11:00:55.965868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33311 11:00:55.966254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33313 11:00:56.013572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33314 11:00:56.013864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33316 11:00:56.059582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33317 11:00:56.059855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33319 11:00:56.104352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33320 11:00:56.104650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33322 11:00:56.163758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33323 11:00:56.164047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33325 11:00:56.216767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33326 11:00:56.217164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33328 11:00:56.262445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33330 11:00:56.262915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33331 11:00:56.307031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33332 11:00:56.307527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33334 11:00:56.351025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33335 11:00:56.351442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33337 11:00:56.395585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33339 11:00:56.396020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33340 11:00:56.439936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33341 11:00:56.440334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33343 11:00:56.486083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33344 11:00:56.486510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33346 11:00:56.532423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33347 11:00:56.532835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33349 11:00:56.576588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33350 11:00:56.576982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33352 11:00:56.609978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33353 11:00:56.610404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33355 11:00:56.647302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33356 11:00:56.647747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33358 11:00:56.695128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33360 11:00:56.695578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33361 11:00:56.739528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33362 11:00:56.739950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33364 11:00:56.783671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33366 11:00:56.784103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33367 11:00:56.832831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33368 11:00:56.833285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33370 11:00:56.871149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33371 11:00:56.871572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33373 11:00:56.915096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33374 11:00:56.915463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33376 11:00:56.953333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33377 11:00:56.953621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33379 11:00:56.992356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33380 11:00:56.992644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33382 11:00:57.036799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33383 11:00:57.037091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33385 11:00:57.080342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33386 11:00:57.080632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33388 11:00:57.123997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33389 11:00:57.124414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33391 11:00:57.163151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33393 11:00:57.163616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33394 11:00:57.207116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33395 11:00:57.207538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33397 11:00:57.251441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33398 11:00:57.251863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33400 11:00:57.287753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33402 11:00:57.288225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33403 11:00:57.331818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33404 11:00:57.332250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33406 11:00:57.376100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33407 11:00:57.376558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33409 11:00:57.420540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33410 11:00:57.420961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33412 11:00:57.464411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33413 11:00:57.464812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33415 11:00:57.508580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33417 11:00:57.508997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33418 11:00:57.552683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33419 11:00:57.553021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33421 11:00:57.596631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33422 11:00:57.596923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33424 11:00:57.643727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33425 11:00:57.644021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33427 11:00:57.687568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33428 11:00:57.687839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33430 11:00:57.726056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33431 11:00:57.726452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33433 11:00:57.761099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33434 11:00:57.761437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33436 11:00:57.807321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33438 11:00:57.807628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33439 11:00:57.851637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33440 11:00:57.851931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33442 11:00:57.895649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33444 11:00:57.896104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33445 11:00:57.941538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33446 11:00:57.941950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33448 11:00:57.987357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33450 11:00:57.987805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33451 11:00:58.033731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33452 11:00:58.034155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33454 11:00:58.080106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33455 11:00:58.080549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33457 11:00:58.119442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33458 11:00:58.119895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33460 11:00:58.152997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33461 11:00:58.153427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33463 11:00:58.195625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33465 11:00:58.196070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33466 11:00:58.238316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33468 11:00:58.238756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33469 11:00:58.283994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33470 11:00:58.284409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33472 11:00:58.329939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33473 11:00:58.330273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33475 11:00:58.375458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33476 11:00:58.375709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33478 11:00:58.419741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33479 11:00:58.420034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33481 11:00:58.464240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33482 11:00:58.464531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33484 11:00:58.510061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33485 11:00:58.510359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33487 11:00:58.555193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33489 11:00:58.555491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33490 11:00:58.599479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33491 11:00:58.599779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33493 11:00:58.645256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33494 11:00:58.645548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33496 11:00:58.691701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33497 11:00:58.691985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33499 11:00:58.737565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33501 11:00:58.737872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33502 11:00:58.769654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33504 11:00:58.769951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33505 11:00:58.814411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33507 11:00:58.814735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33508 11:00:58.863378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33510 11:00:58.863711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33511 11:00:58.908923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33512 11:00:58.909221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33514 11:00:58.941492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33516 11:00:58.941804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33517 11:00:58.974165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33519 11:00:58.974460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33520 11:00:59.021389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33521 11:00:59.021678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33523 11:00:59.063352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33524 11:00:59.063744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33526 11:00:59.096240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33527 11:00:59.096529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33529 11:00:59.130698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33530 11:00:59.130999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33532 11:00:59.163628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33534 11:00:59.163933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33535 11:00:59.197343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33536 11:00:59.197632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33538 11:00:59.232176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33539 11:00:59.232557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33541 11:00:59.272849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33543 11:00:59.273321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33544 11:00:59.307777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33545 11:00:59.308073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33547 11:00:59.357829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33548 11:00:59.358292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33550 11:00:59.392236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33551 11:00:59.392682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33553 11:00:59.435221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33554 11:00:59.435644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33556 11:00:59.481389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33557 11:00:59.481821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33559 11:00:59.535470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33561 11:00:59.535928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33562 11:00:59.581621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33563 11:00:59.582051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33565 11:00:59.630590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33567 11:00:59.631088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33568 11:00:59.680759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33569 11:00:59.685709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33571 11:00:59.754376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33573 11:00:59.754824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33574 11:00:59.808765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33575 11:00:59.809137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33577 11:00:59.862603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33579 11:00:59.863067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33580 11:00:59.912629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33581 11:00:59.913022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33583 11:00:59.959682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33584 11:00:59.960053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33586 11:01:00.004989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33588 11:01:00.005699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33589 11:01:00.051587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33590 11:01:00.051923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33592 11:01:00.100353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33593 11:01:00.100707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33595 11:01:00.148821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33596 11:01:00.149386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33598 11:01:00.196081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33599 11:01:00.196495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33601 11:01:00.244193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33602 11:01:00.244597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33604 11:01:00.292031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33605 11:01:00.292436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33607 11:01:00.339691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33608 11:01:00.340121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33610 11:01:00.385904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33611 11:01:00.386339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33613 11:01:00.434968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33614 11:01:00.435403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33616 11:01:00.483558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33618 11:01:00.483984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33619 11:01:00.528020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33621 11:01:00.528477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33622 11:01:00.572742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33624 11:01:00.573159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33625 11:01:00.619557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33626 11:01:00.619961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33628 11:01:00.665555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33629 11:01:00.665992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33631 11:01:00.711822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33632 11:01:00.712250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33634 11:01:00.757726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33635 11:01:00.758135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33637 11:01:00.804013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33638 11:01:00.804400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33640 11:01:00.849402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33641 11:01:00.849738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33643 11:01:00.896464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33644 11:01:00.896857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33646 11:01:00.943286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33647 11:01:00.943704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33649 11:01:00.991619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33650 11:01:00.992015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33652 11:01:01.039760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33653 11:01:01.040183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33655 11:01:01.089186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33656 11:01:01.089608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33658 11:01:01.139055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33659 11:01:01.139472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33661 11:01:01.191389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33662 11:01:01.191842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33664 11:01:01.249798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33665 11:01:01.250342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33667 11:01:01.315334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33668 11:01:01.315756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33670 11:01:01.360030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33671 11:01:01.360413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33673 11:01:01.407905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33674 11:01:01.408295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33676 11:01:01.456962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33677 11:01:01.457396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33679 11:01:01.503839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33680 11:01:01.504270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33682 11:01:01.551922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33683 11:01:01.552371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33685 11:01:01.600169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33686 11:01:01.600568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33688 11:01:01.644545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33689 11:01:01.644970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33691 11:01:01.695290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33692 11:01:01.695695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33694 11:01:01.745933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33695 11:01:01.747377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33697 11:01:01.797314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33699 11:01:01.797787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33700 11:01:01.846429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33702 11:01:01.846904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33703 11:01:01.896105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33704 11:01:01.896495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33706 11:01:01.943844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33707 11:01:01.944270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33709 11:01:01.990504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33711 11:01:01.990981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33712 11:01:02.041220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33713 11:01:02.041663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33715 11:01:02.081120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33716 11:01:02.081556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33718 11:01:02.128536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33719 11:01:02.128980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33721 11:01:02.175537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33722 11:01:02.175973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33724 11:01:02.224605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33725 11:01:02.225062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33727 11:01:02.276091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33728 11:01:02.276517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33730 11:01:02.334485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33731 11:01:02.334931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33733 11:01:02.388389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33734 11:01:02.388833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33736 11:01:02.440608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33737 11:01:02.441057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33739 11:01:02.494355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33741 11:01:02.494883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33742 11:01:02.548473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33744 11:01:02.548953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33745 11:01:02.607597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33746 11:01:02.608026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33748 11:01:02.668264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33750 11:01:02.668725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33751 11:01:02.727692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33752 11:01:02.727987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33754 11:01:02.781122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33755 11:01:02.781396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33757 11:01:02.839851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33758 11:01:02.840273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33760 11:01:02.893177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33762 11:01:02.893643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33763 11:01:02.940534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33765 11:01:02.941006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33766 11:01:02.995024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33767 11:01:02.995476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33769 11:01:03.050688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33771 11:01:03.051200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33772 11:01:03.101202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33773 11:01:03.101633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33775 11:01:03.155705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33777 11:01:03.156325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33778 11:01:03.207972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33779 11:01:03.208396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33781 11:01:03.259480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33783 11:01:03.260085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33784 11:01:03.315087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33786 11:01:03.315687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33787 11:01:03.367768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33789 11:01:03.368371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33790 11:01:03.425918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33791 11:01:03.426366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33793 11:01:03.483338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33795 11:01:03.483952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33796 11:01:03.545767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33798 11:01:03.546252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33799 11:01:03.600500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33800 11:01:03.600893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33802 11:01:03.657832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33804 11:01:03.658313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33805 11:01:03.712245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33806 11:01:03.712674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33808 11:01:03.764364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33810 11:01:03.764845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33811 11:01:03.815493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33812 11:01:03.815918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33814 11:01:03.865011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33815 11:01:03.865444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33817 11:01:03.911767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33818 11:01:03.912198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33820 11:01:03.963840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33821 11:01:03.964266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33823 11:01:04.018088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33824 11:01:04.018549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33826 11:01:04.070282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33828 11:01:04.070923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33829 11:01:04.126010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33830 11:01:04.126455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33832 11:01:04.177018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33833 11:01:04.177449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33835 11:01:04.228566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33836 11:01:04.229076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33838 11:01:04.281118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33840 11:01:04.281595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33841 11:01:04.332151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33842 11:01:04.332567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33844 11:01:04.386231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33845 11:01:04.386667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33847 11:01:04.439779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33848 11:01:04.440214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33850 11:01:04.490057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33851 11:01:04.490495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33853 11:01:04.545780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33855 11:01:04.546249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33856 11:01:04.598516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33858 11:01:04.598993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33859 11:01:04.648649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33860 11:01:04.649074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33862 11:01:04.695217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33863 11:01:04.695648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33865 11:01:04.751765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33866 11:01:04.752185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33868 11:01:04.807257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33869 11:01:04.807648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33871 11:01:04.863921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33872 11:01:04.864305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33874 11:01:04.900224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33875 11:01:04.900645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33877 11:01:04.937194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33878 11:01:04.937616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33880 11:01:04.976593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33881 11:01:04.977023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33883 11:01:05.025302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33884 11:01:05.025736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33886 11:01:05.072694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33887 11:01:05.073114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33889 11:01:05.109068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33891 11:01:05.109545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33892 11:01:05.156056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33893 11:01:05.156495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33895 11:01:05.200977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33896 11:01:05.201408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33898 11:01:05.243882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33899 11:01:05.244339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33901 11:01:05.288502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33902 11:01:05.288923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33904 11:01:05.342016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33905 11:01:05.342451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33907 11:01:05.387488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33908 11:01:05.387916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33910 11:01:05.436986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33911 11:01:05.437397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33913 11:01:05.487883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33915 11:01:05.488270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33916 11:01:05.529124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33917 11:01:05.529517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33919 11:01:05.576857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33921 11:01:05.577342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33922 11:01:05.625725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33923 11:01:05.626162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33925 11:01:05.673776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33926 11:01:05.674204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33928 11:01:05.723460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33929 11:01:05.723898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33931 11:01:05.759172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33933 11:01:05.759627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33934 11:01:05.796889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33935 11:01:05.797351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33937 11:01:05.845516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33938 11:01:05.845902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33940 11:01:05.893606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33941 11:01:05.894021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33943 11:01:05.935165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33944 11:01:05.935595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33946 11:01:05.982216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33948 11:01:05.982695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33949 11:01:06.036916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33951 11:01:06.037381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33952 11:01:06.078849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33953 11:01:06.079265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33955 11:01:06.113552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33957 11:01:06.114038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33958 11:01:06.152625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33959 11:01:06.153055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33961 11:01:06.190839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33962 11:01:06.191293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33964 11:01:06.236357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33966 11:01:06.236803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33967 11:01:06.276930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33968 11:01:06.277365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33970 11:01:06.316982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33971 11:01:06.317416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33973 11:01:06.367251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33975 11:01:06.367724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33976 11:01:06.433550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
33978 11:01:06.434016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33979 11:01:06.470556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33981 11:01:06.470956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33982 11:01:06.503674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33983 11:01:06.504112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33985 11:01:06.549107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33986 11:01:06.549526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
33988 11:01:06.597044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33989 11:01:06.597475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33991 11:01:06.644146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33992 11:01:06.644575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33994 11:01:06.690025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33995 11:01:06.690506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
33997 11:01:06.737255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33998 11:01:06.737691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
34000 11:01:06.789963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34001 11:01:06.790360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34003 11:01:06.839862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34004 11:01:06.840299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34006 11:01:06.889780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34007 11:01:06.890286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34009 11:01:06.936938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34011 11:01:06.937429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34012 11:01:06.984659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34013 11:01:06.985092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34015 11:01:07.032454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34016 11:01:07.032887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34018 11:01:07.080258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34019 11:01:07.080675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34021 11:01:07.124601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34022 11:01:07.125014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34024 11:01:07.174466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34026 11:01:07.174988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34027 11:01:07.220163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34028 11:01:07.220595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34030 11:01:07.273390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34032 11:01:07.273851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34033 11:01:07.319777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34034 11:01:07.320166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34036 11:01:07.367072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34037 11:01:07.367488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34039 11:01:07.409024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34040 11:01:07.409414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34042 11:01:07.458273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34044 11:01:07.458743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34045 11:01:07.507440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34046 11:01:07.507822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34048 11:01:07.556896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34049 11:01:07.557296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34051 11:01:07.604422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34052 11:01:07.604856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34054 11:01:07.654702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34056 11:01:07.655429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34057 11:01:07.703987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34058 11:01:07.704364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34060 11:01:07.744058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34062 11:01:07.744528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34063 11:01:07.790150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34065 11:01:07.790643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34066 11:01:07.841275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34067 11:01:07.841686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34069 11:01:07.889336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34070 11:01:07.889777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34072 11:01:07.937835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34074 11:01:07.938324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34075 11:01:07.984242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34076 11:01:07.984640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34078 11:01:08.031074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34080 11:01:08.031850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34081 11:01:08.080336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34082 11:01:08.080764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34084 11:01:08.128172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34085 11:01:08.128603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34087 11:01:08.173629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34088 11:01:08.174069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34090 11:01:08.220491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34091 11:01:08.220922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34093 11:01:08.268059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34095 11:01:08.268481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34096 11:01:08.317182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34097 11:01:08.317585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34099 11:01:08.360282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34100 11:01:08.360853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34102 11:01:08.408004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34103 11:01:08.408437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34105 11:01:08.452941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34106 11:01:08.453360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34108 11:01:08.487696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34109 11:01:08.488121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34111 11:01:08.528630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34112 11:01:08.529072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34114 11:01:08.576580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34115 11:01:08.576976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34117 11:01:08.625138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34118 11:01:08.625563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34120 11:01:08.672460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34121 11:01:08.673023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34123 11:01:08.720229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34124 11:01:08.720654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34126 11:01:08.768090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34127 11:01:08.768500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34129 11:01:08.815693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34130 11:01:08.816076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34132 11:01:08.861708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34133 11:01:08.862136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34135 11:01:08.909599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34136 11:01:08.910036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34138 11:01:08.955919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34140 11:01:08.956367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34141 11:01:09.005820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34142 11:01:09.006249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34144 11:01:09.056338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34145 11:01:09.056769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34147 11:01:09.103440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34148 11:01:09.103879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34150 11:01:09.152590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34151 11:01:09.153032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34153 11:01:09.199406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34154 11:01:09.199852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34156 11:01:09.244011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34157 11:01:09.244420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34159 11:01:09.291802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34160 11:01:09.292235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34162 11:01:09.339135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34163 11:01:09.339560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34165 11:01:09.384915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34166 11:01:09.385345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34168 11:01:09.433225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34169 11:01:09.433662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34171 11:01:09.479983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34172 11:01:09.480365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34174 11:01:09.525202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34175 11:01:09.525635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34177 11:01:09.573902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34178 11:01:09.574361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34180 11:01:09.621088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34181 11:01:09.621500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34183 11:01:09.668333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34185 11:01:09.668788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34186 11:01:09.716124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34187 11:01:09.716500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34189 11:01:09.758729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34191 11:01:09.759227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34192 11:01:09.810978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34193 11:01:09.811423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34195 11:01:09.859845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34196 11:01:09.860259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34198 11:01:09.905624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34199 11:01:09.906067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34201 11:01:09.953254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34203 11:01:09.953720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34204 11:01:09.995817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34206 11:01:09.996328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34207 11:01:10.041587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34208 11:01:10.042034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34210 11:01:10.089151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34211 11:01:10.089584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34213 11:01:10.139184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34214 11:01:10.139618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34216 11:01:10.187885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34217 11:01:10.188311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34219 11:01:10.235489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34220 11:01:10.235922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34222 11:01:10.282447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34224 11:01:10.282912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34225 11:01:10.329483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34226 11:01:10.329902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34228 11:01:10.375495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34229 11:01:10.375912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34231 11:01:10.424018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34232 11:01:10.424424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34234 11:01:10.469368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34235 11:01:10.469797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34237 11:01:10.517907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34238 11:01:10.518333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34240 11:01:10.564607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34241 11:01:10.564979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34243 11:01:10.607338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34244 11:01:10.607773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34246 11:01:10.655000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34247 11:01:10.655419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34249 11:01:10.701139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34250 11:01:10.701525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34252 11:01:10.746474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34254 11:01:10.746874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34255 11:01:10.792634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34257 11:01:10.793120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34258 11:01:10.837303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34260 11:01:10.837767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34261 11:01:10.871972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34262 11:01:10.872394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34264 11:01:10.917510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34265 11:01:10.917965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34267 11:01:10.963764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34268 11:01:10.964188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34270 11:01:11.008070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34272 11:01:11.008368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34273 11:01:11.051457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34274 11:01:11.051865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34276 11:01:11.097587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34277 11:01:11.098009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34279 11:01:11.147200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34280 11:01:11.147639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34282 11:01:11.196630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34283 11:01:11.197032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34285 11:01:11.244521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34286 11:01:11.244938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34288 11:01:11.295723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34289 11:01:11.296136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34291 11:01:11.344256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34293 11:01:11.344730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34294 11:01:11.394046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34295 11:01:11.394474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34297 11:01:11.436258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34299 11:01:11.436742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34300 11:01:11.484753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34301 11:01:11.485169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34303 11:01:11.559204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34305 11:01:11.559653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34306 11:01:11.609202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34307 11:01:11.609604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34309 11:01:11.661846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34310 11:01:11.662188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34312 11:01:11.720317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34313 11:01:11.720757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34315 11:01:11.771395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34316 11:01:11.771800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34318 11:01:11.821613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34319 11:01:11.822081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34321 11:01:11.872078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34322 11:01:11.872396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34324 11:01:11.920670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34325 11:01:11.920947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34327 11:01:11.965548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34328 11:01:11.965983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34330 11:01:12.015949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34331 11:01:12.016558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34333 11:01:12.063428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34334 11:01:12.063837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34336 11:01:12.107987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34337 11:01:12.108433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34339 11:01:12.163141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34340 11:01:12.163572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34342 11:01:12.219531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34343 11:01:12.219829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34345 11:01:12.274205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34347 11:01:12.274521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34348 11:01:12.309555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34349 11:01:12.309945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34351 11:01:12.343915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34352 11:01:12.344295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34354 11:01:12.380383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34355 11:01:12.380835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34357 11:01:12.416147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34359 11:01:12.416617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34360 11:01:12.453909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34361 11:01:12.454340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34363 11:01:12.490274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34365 11:01:12.490748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34366 11:01:12.536132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34367 11:01:12.536549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34369 11:01:12.580423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34370 11:01:12.580802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34372 11:01:12.619937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34373 11:01:12.620324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34375 11:01:12.656201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34376 11:01:12.656629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34378 11:01:12.691157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34380 11:01:12.691609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34381 11:01:12.731460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34383 11:01:12.731916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34384 11:01:12.772607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34385 11:01:12.773032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34387 11:01:12.807516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34389 11:01:12.807895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34390 11:01:12.844076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34391 11:01:12.844505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34393 11:01:12.884352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34394 11:01:12.884800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34396 11:01:12.933852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34398 11:01:12.934415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34399 11:01:12.992576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34400 11:01:12.992975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34402 11:01:13.033397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34403 11:01:13.033802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34405 11:01:13.070392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34407 11:01:13.070811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34408 11:01:13.107882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34410 11:01:13.108334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34411 11:01:13.144528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34412 11:01:13.144810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34414 11:01:13.181133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34415 11:01:13.181502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34417 11:01:13.213590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34418 11:01:13.213990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34420 11:01:13.246865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34421 11:01:13.247312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34423 11:01:13.278837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34424 11:01:13.279161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34426 11:01:13.310025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34427 11:01:13.310391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34429 11:01:13.343135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34430 11:01:13.343515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34432 11:01:13.375335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34433 11:01:13.375747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34435 11:01:13.407549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34437 11:01:13.408015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34438 11:01:13.439221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34439 11:01:13.439580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34441 11:01:13.471256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34442 11:01:13.471612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34444 11:01:13.502901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34446 11:01:13.503352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34447 11:01:13.535036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34448 11:01:13.535319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34450 11:01:13.566663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34452 11:01:13.567174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34453 11:01:13.600075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34455 11:01:13.600557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34456 11:01:13.635075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34457 11:01:13.635444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34459 11:01:13.669349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34460 11:01:13.669685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34462 11:01:13.704381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34463 11:01:13.704674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34465 11:01:13.739214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34466 11:01:13.739651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34468 11:01:13.771744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34469 11:01:13.772195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34471 11:01:13.804449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34472 11:01:13.804840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34474 11:01:13.839227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34475 11:01:13.839592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34477 11:01:13.872797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34478 11:01:13.873328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34480 11:01:13.907365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34481 11:01:13.907747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34483 11:01:13.939233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34484 11:01:13.939546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34486 11:01:13.971132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34487 11:01:13.971490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34489 11:01:14.002824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34491 11:01:14.003256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34492 11:01:14.034048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34493 11:01:14.034398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34495 11:01:14.065986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34496 11:01:14.066443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34498 11:01:14.098511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34500 11:01:14.099227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34501 11:01:14.136473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34502 11:01:14.136857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34504 11:01:14.170774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34505 11:01:14.171126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34507 11:01:14.207210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34508 11:01:14.207619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34510 11:01:14.241966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34511 11:01:14.242322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34513 11:01:14.279388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34514 11:01:14.279760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34516 11:01:14.312808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34517 11:01:14.313209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34519 11:01:14.346660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34520 11:01:14.347119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34522 11:01:14.378709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34523 11:01:14.379203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34525 11:01:14.410914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34526 11:01:14.411389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34528 11:01:14.443820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34529 11:01:14.444294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34531 11:01:14.477855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34532 11:01:14.478325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34534 11:01:14.513350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34535 11:01:14.513814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34537 11:01:14.545800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34538 11:01:14.546283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34540 11:01:14.577826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34541 11:01:14.578247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34543 11:01:14.610923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34544 11:01:14.611338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34546 11:01:14.643063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34547 11:01:14.643529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34549 11:01:14.675592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34550 11:01:14.676043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34552 11:01:14.707254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34554 11:01:14.707700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34555 11:01:14.738454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34557 11:01:14.738917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34558 11:01:14.771470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34559 11:01:14.771952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34561 11:01:14.804114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34562 11:01:14.804572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34564 11:01:14.836607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34565 11:01:14.837090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34567 11:01:14.869195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34568 11:01:14.869479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34570 11:01:14.901362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34572 11:01:14.901691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34573 11:01:14.933243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34574 11:01:14.933532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34576 11:01:14.965183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34577 11:01:14.965469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34579 11:01:14.996925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34581 11:01:14.997384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34582 11:01:15.029379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34584 11:01:15.029822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34585 11:01:15.060285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34586 11:01:15.060650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34588 11:01:15.091716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34589 11:01:15.092069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34591 11:01:15.122990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34592 11:01:15.123340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34594 11:01:15.154493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34596 11:01:15.154941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34597 11:01:15.186944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34598 11:01:15.187325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34600 11:01:15.219186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34601 11:01:15.219653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34603 11:01:15.251080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34604 11:01:15.251476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34606 11:01:15.253717 + set +x
34607 11:01:15.253910 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 562569_1.1.3.5>
34608 11:01:15.254235 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 562569_1.1.3.5
34609 11:01:15.254375 Ending use of test pattern.
34610 11:01:15.254497 Ending test lava.1_kselftest-arm64_qemu (562569_1.1.3.5), duration 403.49
34612 11:01:15.256962 <LAVA_TEST_RUNNER EXIT>
34613 11:01:15.257285 ok: lava_test_shell seems to have completed
34614 11:01:15.331878 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34615 11:01:15.335073 end: 3.1 lava-test-shell (duration 00:06:45) [common]
34616 11:01:15.335175 end: 3 lava-test-retry (duration 00:06:45) [common]
34617 11:01:15.335268 start: 4 finalize (timeout 00:02:06) [common]
34618 11:01:15.335359 start: 4.1 power-off (timeout 00:00:30) [common]
34619 11:01:15.335444 end: 4.1 power-off (duration 00:00:00) [common]
34620 11:01:15.335526 start: 4.2 read-feedback (timeout 00:02:06) [common]
34621 11:01:15.335713 Listened to connection for namespace 'common' for up to 1s
34622 11:01:15.335988 Listened to connection for namespace 'common' for up to 1s
34623 11:01:16.340733 Finalising connection for namespace 'common'
34625 11:01:16.441736 / # poweroff
34626 11:01:16.442185 Already disconnected
34627 11:01:16.442340 poweroff
34628 11:01:16.543213 end: 4.2 read-feedback (duration 00:00:01) [common]
34629 11:01:16.543510 Already disconnected
34630 11:01:16.543683 end: 4 finalize (duration 00:00:01) [common]
34631 11:01:16.543864 Cleaning after the job
34632 11:01:16.544047 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/562569/deployimages-i9ddb_1e/kernel
34633 11:01:16.552718 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/562569/deployimages-i9ddb_1e/ramdisk
34634 11:01:16.569674 Stopping the qemu container lava-docker-qemu-562569-2.1.1-wjht5aez69
34635 11:01:17.623745 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/562569
34636 11:01:17.712967 Job finished correctly